diff options
Diffstat (limited to 'arch/arm')
42 files changed, 902 insertions, 486 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 970f1cf..b99d25b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -777,6 +777,8 @@ source "arch/arm/mach-meson/Kconfig" source "arch/arm/mach-moxart/Kconfig" +source "arch/arm/mach-aspeed/Kconfig" + source "arch/arm/mach-mv78xx0/Kconfig" source "arch/arm/mach-imx/Kconfig" @@ -806,6 +808,8 @@ source "arch/arm/plat-pxa/Kconfig" source "arch/arm/mach-mmp/Kconfig" +source "arch/arm/mach-oxnas/Kconfig" + source "arch/arm/mach-qcom/Kconfig" source "arch/arm/mach-realview/Kconfig" @@ -894,6 +898,18 @@ config MACH_STM32F429 depends on ARCH_STM32 default y +config ARCH_MPS2 + bool "ARM MPS2 paltform" + depends on ARM_SINGLE_ARMV7M + select ARM_AMBA + select CLKSRC_MPS2 + help + Support for Cortex-M Prototyping System (or V2M-MPS2) which comes + with a range of available cores like Cortex-M3/M4/M7. + + Please, note that depends which Application Note is used memory map + for the platform may vary, so adjustment of RAM base might be needed. + # Definitions to make life easier config ARCH_ACORN bool diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 8c3ce2a..274e8a6 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -183,6 +183,7 @@ machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MMP) += mmp +machine-$(CONFIG_ARCH_MPS2) += vexpress machine-$(CONFIG_ARCH_MOXART) += moxart machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 machine-$(CONFIG_ARCH_MVEBU) += mvebu diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig new file mode 100644 index 0000000..5225fbc --- /dev/null +++ b/arch/arm/mach-aspeed/Kconfig @@ -0,0 +1,30 @@ +menuconfig ARCH_ASPEED + bool "Aspeed BMC architectures" + depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 + select SRAM + select WATCHDOG + select ASPEED_WATCHDOG + select MOXART_TIMER + help + Say Y here if you want to run your kernel on an ASpeed BMC SoC. + +if ARCH_ASPEED + +config MACH_ASPEED_G4 + bool "Aspeed SoC 4th Generation" + depends on ARCH_MULTI_V5 + select CPU_ARM926T + help + Say yes if you intend to run on an Aspeed ast2400 or similar + fourth generation BMCs, such as those used by OpenPower Power8 + systems. + +config MACH_ASPEED_G5 + bool "Aspeed SoC 5th Generation" + depends on ARCH_MULTI_V6 + select CPU_V6 + help + Say yes if you intend to run on an Aspeed ast2500 or similar + fifth generation Aspeed BMCs. + +endif diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c index df8fdf1..922b85f 100644 --- a/arch/arm/mach-at91/sama5.c +++ b/arch/arm/mach-at91/sama5.c @@ -18,8 +18,26 @@ #include "soc.h" static const struct at91_soc sama5_socs[] = { - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27_EXID_MATCH, + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH, + "sama5d21", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH, + "sama5d22", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH, + "sama5d23", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH, + "sama5d24", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH, + "sama5d24", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH, + "sama5d26", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH, "sama5d27", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH, + "sama5d27", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH, + "sama5d28", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH, + "sama5d28", "sama5d2"), AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH, "sama5d31", "sama5d3"), AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH, diff --git a/arch/arm/mach-at91/soc.c b/arch/arm/mach-at91/soc.c index 54343ff..c6fda75 100644 --- a/arch/arm/mach-at91/soc.c +++ b/arch/arm/mach-at91/soc.c @@ -22,48 +22,93 @@ #include "soc.h" #define AT91_DBGU_CIDR 0x40 -#define AT91_DBGU_CIDR_VERSION(x) ((x) & 0x1f) -#define AT91_DBGU_CIDR_EXT BIT(31) -#define AT91_DBGU_CIDR_MATCH_MASK 0x7fffffe0 #define AT91_DBGU_EXID 0x44 +#define AT91_CHIPID_CIDR 0x00 +#define AT91_CHIPID_EXID 0x04 +#define AT91_CIDR_VERSION(x) ((x) & 0x1f) +#define AT91_CIDR_EXT BIT(31) +#define AT91_CIDR_MATCH_MASK 0x7fffffe0 -struct soc_device * __init at91_soc_init(const struct at91_soc *socs) +static int __init at91_get_cidr_exid_from_dbgu(u32 *cidr, u32 *exid) { - struct soc_device_attribute *soc_dev_attr; - const struct at91_soc *soc; - struct soc_device *soc_dev; struct device_node *np; void __iomem *regs; - u32 cidr, exid; np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu"); if (!np) np = of_find_compatible_node(NULL, NULL, "atmel,at91sam9260-dbgu"); + if (!np) + return -ENODEV; - if (!np) { - pr_warn("Could not find DBGU node"); - return NULL; + regs = of_iomap(np, 0); + of_node_put(np); + + if (!regs) { + pr_warn("Could not map DBGU iomem range"); + return -ENXIO; } + *cidr = readl(regs + AT91_DBGU_CIDR); + *exid = readl(regs + AT91_DBGU_EXID); + + iounmap(regs); + + return 0; +} + +static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid) +{ + struct device_node *np; + void __iomem *regs; + + np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid"); + if (!np) + return -ENODEV; + regs = of_iomap(np, 0); of_node_put(np); if (!regs) { pr_warn("Could not map DBGU iomem range"); - return NULL; + return -ENXIO; } - cidr = readl(regs + AT91_DBGU_CIDR); - exid = readl(regs + AT91_DBGU_EXID); + *cidr = readl(regs + AT91_CHIPID_CIDR); + *exid = readl(regs + AT91_CHIPID_EXID); iounmap(regs); + return 0; +} + +struct soc_device * __init at91_soc_init(const struct at91_soc *socs) +{ + struct soc_device_attribute *soc_dev_attr; + const struct at91_soc *soc; + struct soc_device *soc_dev; + u32 cidr, exid; + int ret; + + /* + * With SAMA5D2 and later SoCs, CIDR and EXID registers are no more + * in the dbgu device but in the chipid device whose purpose is only + * to expose these two registers. + */ + ret = at91_get_cidr_exid_from_dbgu(&cidr, &exid); + if (ret) + ret = at91_get_cidr_exid_from_chipid(&cidr, &exid); + if (ret) { + if (ret == -ENODEV) + pr_warn("Could not find identification node"); + return NULL; + } + for (soc = socs; soc->name; soc++) { - if (soc->cidr_match != (cidr & AT91_DBGU_CIDR_MATCH_MASK)) + if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK)) continue; - if (!(cidr & AT91_DBGU_CIDR_EXT) || soc->exid_match == exid) + if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid) break; } @@ -79,7 +124,7 @@ struct soc_device * __init at91_soc_init(const struct at91_soc *socs) soc_dev_attr->family = soc->family; soc_dev_attr->soc_id = soc->name; soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X", - AT91_DBGU_CIDR_VERSION(cidr)); + AT91_CIDR_VERSION(cidr)); soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { kfree(soc_dev_attr->revision); @@ -91,7 +136,7 @@ struct soc_device * __init at91_soc_init(const struct at91_soc *socs) if (soc->family) pr_info("Detected SoC family: %s\n", soc->family); pr_info("Detected SoC: %s, revision %X\n", soc->name, - AT91_DBGU_CIDR_VERSION(cidr)); + AT91_CIDR_VERSION(cidr)); return soc_dev; } diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h index 8ede0ef..228efde 100644 --- a/arch/arm/mach-at91/soc.h +++ b/arch/arm/mach-at91/soc.h @@ -63,7 +63,17 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 #define SAMA5D2_CIDR_MATCH 0x0a5c08c0 -#define SAMA5D27_EXID_MATCH 0x00000021 +#define SAMA5D21CU_EXID_MATCH 0x0000005a +#define SAMA5D22CU_EXID_MATCH 0x00000059 +#define SAMA5D22CN_EXID_MATCH 0x00000069 +#define SAMA5D23CU_EXID_MATCH 0x00000058 +#define SAMA5D24CX_EXID_MATCH 0x00000004 +#define SAMA5D24CU_EXID_MATCH 0x00000014 +#define SAMA5D26CU_EXID_MATCH 0x00000012 +#define SAMA5D27CU_EXID_MATCH 0x00000011 +#define SAMA5D27CN_EXID_MATCH 0x00000021 +#define SAMA5D28CU_EXID_MATCH 0x00000010 +#define SAMA5D28CN_EXID_MATCH 0x00000020 #define SAMA5D3_CIDR_MATCH 0x0a5c07c0 #define SAMA5D31_EXID_MATCH 0x00444300 diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 2e3464b..da4c336 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -14,8 +14,8 @@ obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o -obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o -obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o +obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o usb-da8xx.o +obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o usb-da8xx.o obj-$(CONFIG_AINTC) += irq.o obj-$(CONFIG_CP_INTC) += cp_intc.o diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 3424eac6..df42c93 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -195,6 +195,14 @@ int clk_set_parent(struct clk *clk, struct clk *parent) return -EINVAL; mutex_lock(&clocks_mutex); + if (clk->set_parent) { + int ret = clk->set_parent(clk, parent); + + if (ret) { + mutex_unlock(&clocks_mutex); + return ret; + } + } clk->parent = parent; list_del_init(&clk->childnode); list_add(&clk->childnode, &clk->parent->children); @@ -224,8 +232,17 @@ int clk_register(struct clk *clk) mutex_lock(&clocks_mutex); list_add_tail(&clk->node, &clocks); - if (clk->parent) + if (clk->parent) { + if (clk->set_parent) { + int ret = clk->set_parent(clk, clk->parent); + + if (ret) { + mutex_unlock(&clocks_mutex); + return ret; + } + } list_add_tail(&clk->childnode, &clk->parent->children); + } mutex_unlock(&clocks_mutex); /* If rate is already set, use it */ @@ -560,7 +577,7 @@ EXPORT_SYMBOL(davinci_set_pllrate); * than that used by default in <soc>.c file. The reference clock rate * should be updated early in the boot process; ideally soon after the * clock tree has been initialized once with the default reference clock - * rate (davinci_common_init()). + * rate (davinci_clk_init()). * * Returns 0 on success, error otherwise. */ diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 1e4e836..e2a5437 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -106,6 +106,7 @@ struct clk { int (*reset) (struct clk *clk, bool reset); void (*clk_enable) (struct clk *clk); void (*clk_disable) (struct clk *clk); + int (*set_parent) (struct clk *clk, struct clk *parent); }; /* Clock flags: SoC-specific flags start at BIT(16) */ diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c index 742133b..049025f 100644 --- a/arch/arm/mach-davinci/common.c +++ b/arch/arm/mach-davinci/common.c @@ -108,12 +108,6 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info) if (ret < 0) goto err; - if (davinci_soc_info.cpu_clks) { - ret = davinci_clk_init(davinci_soc_info.cpu_clks); - - if (ret != 0) - goto err; - } return; diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 7187e7f..426fd74 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -1214,4 +1214,6 @@ void __init da830_init(void) da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"); + + davinci_clk_init(davinci_soc_info_da830.cpu_clks); } diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 97d8779..2398862 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -34,9 +34,6 @@ #include "clock.h" #include "mux.h" -/* SoC specific clock flags */ -#define DA850_CLK_ASYNC3 BIT(16) - #define DA850_PLL1_BASE 0x01e1a000 #define DA850_TIMER64P2_BASE 0x01f0c000 #define DA850_TIMER64P3_BASE 0x01f0d000 @@ -161,6 +158,32 @@ static struct clk pll1_sysclk3 = { .div_reg = PLLDIV3, }; +static int da850_async3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 val; + + val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); + + if (parent == &pll0_sysclk2) { + val &= ~CFGCHIP3_ASYNC3_CLKSRC; + } else if (parent == &pll1_sysclk2) { + val |= CFGCHIP3_ASYNC3_CLKSRC; + } else { + pr_err("Bad parent on async3 clock mux\n"); + return -EINVAL; + } + + writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); + + return 0; +} + +static struct clk async3_clk = { + .name = "async3", + .parent = &pll1_sysclk2, + .set_parent = da850_async3_set_parent, +}; + static struct clk i2c0_clk = { .name = "i2c0", .parent = &pll0_aux_clk, @@ -234,18 +257,16 @@ static struct clk uart0_clk = { static struct clk uart1_clk = { .name = "uart1", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_UART1, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk uart2_clk = { .name = "uart2", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_UART2, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk aintc_clk = { @@ -300,10 +321,9 @@ static struct clk emac_clk = { static struct clk mcasp_clk = { .name = "mcasp", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_McASP0, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk lcdc_clk = { @@ -355,10 +375,9 @@ static struct clk spi0_clk = { static struct clk spi1_clk = { .name = "spi1", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_SPI1, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk vpif_clk = { @@ -386,10 +405,9 @@ static struct clk dsp_clk = { static struct clk ehrpwm_clk = { .name = "ehrpwm", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_PWM, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; #define DA8XX_EHRPWM_TBCLKSYNC BIT(12) @@ -421,10 +439,9 @@ static struct clk ehrpwm_tbclk = { static struct clk ecap_clk = { .name = "ecap", - .parent = &pll0_sysclk2, + .parent = &async3_clk, .lpsc = DA8XX_LPSC1_ECAP, .gpsc = 1, - .flags = DA850_CLK_ASYNC3, }; static struct clk_lookup da850_clks[] = { @@ -442,6 +459,7 @@ static struct clk_lookup da850_clks[] = { CLK(NULL, "pll1_aux", &pll1_aux_clk), CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), + CLK(NULL, "async3", &async3_clk), CLK("i2c_davinci.1", NULL, &i2c0_clk), CLK(NULL, "timer0", &timerp64_0_clk), CLK("davinci-wdt", NULL, &timerp64_1_clk), @@ -909,30 +927,6 @@ static struct davinci_timer_info da850_timer_info = { .clocksource_id = T0_TOP, }; -static void da850_set_async3_src(int pllnum) -{ - struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2; - struct clk_lookup *c; - unsigned int v; - int ret; - - for (c = da850_clks; c->clk; c++) { - clk = c->clk; - if (clk->flags & DA850_CLK_ASYNC3) { - ret = clk_set_parent(clk, newparent); - WARN(ret, "DA850: unable to re-parent clock %s", - clk->name); - } - } - - v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); - if (pllnum) - v |= CFGCHIP3_ASYNC3_CLKSRC; - else - v &= ~CFGCHIP3_ASYNC3_CLKSRC; - __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); -} - #ifdef CONFIG_CPU_FREQ /* * Notes: @@ -1328,15 +1322,6 @@ void __init da850_init(void) if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module")) return; - /* - * Move the clock source of Async3 domain to PLL1 SYSCLK2. - * This helps keeping the peripherals on this domain insulated - * from CPU frequency changes caused by DVFS. The firmware sets - * both PLL0 and PLL1 to the same frequency so, there should not - * be any noticeable change even in non-DVFS use cases. - */ - da850_set_async3_src(1); - /* Unlock writing to PLL0 registers */ v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG)); v &= ~CFGCHIP0_PLL_MASTER_LOCK; @@ -1346,4 +1331,6 @@ void __init da850_init(void) v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); v &= ~CFGCHIP3_PLL1_MASTER_LOCK; __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG)); + + davinci_clk_init(davinci_soc_info_da850.cpu_clks); } diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index a0ecf49..5a19cca 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -1052,6 +1052,7 @@ void __init dm355_init(void) { davinci_common_init(&davinci_soc_info_dm355); davinci_map_sysmod(); + davinci_clk_init(davinci_soc_info_dm355.cpu_clks); } int __init dm355_init_video(struct vpfe_config *vpfe_cfg, diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 384d367..8aa004b 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -1176,6 +1176,7 @@ void __init dm365_init(void) { davinci_common_init(&davinci_soc_info_dm365); davinci_map_sysmod(); + davinci_clk_init(davinci_soc_info_dm365.cpu_clks); } static struct resource dm365_vpss_resources[] = { diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index b4b3a8b..0afa279 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -932,6 +932,7 @@ void __init dm644x_init(void) { davinci_common_init(&davinci_soc_info_dm644x); davinci_map_sysmod(); + davinci_clk_init(davinci_soc_info_dm644x.cpu_clks); } int __init dm644x_init_video(struct vpfe_config *vpfe_cfg, diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index a43db0f..da21353 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -956,6 +956,7 @@ void __init dm646x_init(void) { davinci_common_init(&davinci_soc_info_dm646x); davinci_map_sysmod(); + davinci_clk_init(davinci_soc_info_dm646x.cpu_clks); } static int __init dm646x_init_devices(void) diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c new file mode 100644 index 0000000..f141f51 --- /dev/null +++ b/arch/arm/mach-davinci/usb-da8xx.c @@ -0,0 +1,107 @@ +/* + * DA8xx USB + */ +#include <linux/dma-mapping.h> +#include <linux/init.h> +#include <linux/platform_data/usb-davinci.h> +#include <linux/platform_device.h> +#include <linux/usb/musb.h> + +#include <mach/common.h> +#include <mach/cputype.h> +#include <mach/da8xx.h> +#include <mach/irqs.h> + +#define DA8XX_USB0_BASE 0x01e00000 +#define DA8XX_USB1_BASE 0x01e25000 + +#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) + +static struct musb_hdrc_config musb_config = { + .multipoint = true, + .num_eps = 5, + .ram_bits = 10, +}; + +static struct musb_hdrc_platform_data usb_data = { + /* OTG requires a Mini-AB connector */ + .mode = MUSB_OTG, + .clock = "usb20", + .config = &musb_config, +}; + +static struct resource da8xx_usb20_resources[] = { + { + .start = DA8XX_USB0_BASE, + .end = DA8XX_USB0_BASE + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DA8XX_USB_INT, + .flags = IORESOURCE_IRQ, + .name = "mc", + }, +}; + +static u64 usb_dmamask = DMA_BIT_MASK(32); + +static struct platform_device usb_dev = { + .name = "musb-da8xx", + .id = -1, + .dev = { + .platform_data = &usb_data, + .dma_mask = &usb_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = da8xx_usb20_resources, + .num_resources = ARRAY_SIZE(da8xx_usb20_resources), +}; + +int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt) +{ + usb_data.power = mA > 510 ? 255 : mA / 2; + usb_data.potpgt = (potpgt + 1) / 2; + + return platform_device_register(&usb_dev); +} + +#else + +int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt) +{ + return 0; +} + +#endif /* CONFIG_USB_MUSB_HDRC */ + +static struct resource da8xx_usb11_resources[] = { + [0] = { + .start = DA8XX_USB1_BASE, + .end = DA8XX_USB1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DA8XX_IRQN, + .end = IRQ_DA8XX_IRQN, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 da8xx_usb11_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device da8xx_usb11_device = { + .name = "ohci", + .id = 0, + .dev = { + .dma_mask = &da8xx_usb11_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(da8xx_usb11_resources), + .resource = da8xx_usb11_resources, +}; + +int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata) +{ + da8xx_usb11_device.dev.platform_data = pdata; + return platform_device_register(&da8xx_usb11_device); +} diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c index 6ed5a54..0e7e89c 100644 --- a/arch/arm/mach-davinci/usb.c +++ b/arch/arm/mach-davinci/usb.c @@ -10,14 +10,10 @@ #include <mach/common.h> #include <mach/irqs.h> #include <mach/cputype.h> -#include <mach/da8xx.h> #include <linux/platform_data/usb-davinci.h> #define DAVINCI_USB_OTG_BASE 0x01c64000 -#define DA8XX_USB0_BASE 0x01e00000 -#define DA8XX_USB1_BASE 0x01e25000 - #if IS_ENABLED(CONFIG_USB_MUSB_HDRC) static struct musb_hdrc_config musb_config = { .multipoint = true, @@ -81,79 +77,10 @@ void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms) platform_device_register(&usb_dev); } -#ifdef CONFIG_ARCH_DAVINCI_DA8XX -static struct resource da8xx_usb20_resources[] = { - { - .start = DA8XX_USB0_BASE, - .end = DA8XX_USB0_BASE + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_DA8XX_USB_INT, - .flags = IORESOURCE_IRQ, - .name = "mc", - }, -}; - -int __init da8xx_register_usb20(unsigned mA, unsigned potpgt) -{ - usb_data.clock = "usb20"; - usb_data.power = mA > 510 ? 255 : mA / 2; - usb_data.potpgt = (potpgt + 1) / 2; - - usb_dev.resource = da8xx_usb20_resources; - usb_dev.num_resources = ARRAY_SIZE(da8xx_usb20_resources); - usb_dev.name = "musb-da8xx"; - - return platform_device_register(&usb_dev); -} -#endif /* CONFIG_DAVINCI_DA8XX */ - #else void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms) { } -#ifdef CONFIG_ARCH_DAVINCI_DA8XX -int __init da8xx_register_usb20(unsigned mA, unsigned potpgt) -{ - return 0; -} -#endif - #endif /* CONFIG_USB_MUSB_HDRC */ - -#ifdef CONFIG_ARCH_DAVINCI_DA8XX -static struct resource da8xx_usb11_resources[] = { - [0] = { - .start = DA8XX_USB1_BASE, - .end = DA8XX_USB1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_DA8XX_IRQN, - .end = IRQ_DA8XX_IRQN, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 da8xx_usb11_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device da8xx_usb11_device = { - .name = "ohci", - .id = 0, - .dev = { - .dma_mask = &da8xx_usb11_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(da8xx_usb11_resources), - .resource = da8xx_usb11_resources, -}; - -int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata) -{ - da8xx_usb11_device.dev.platform_data = pdata; - return platform_device_register(&da8xx_usb11_device); -} -#endif /* CONFIG_DAVINCI_DA8XX */ diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 0cdaa38..0d420a2 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -88,8 +88,7 @@ static void __init dove_clk_init(void) struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; struct clk *xor0, *xor1, *ge, *gephy; - tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, - dove_tclk); + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk); usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 8973fae..dd905b9 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -526,7 +526,7 @@ config SOC_IMX6Q bool "i.MX6 Quad/DualLite support" select ARM_ERRATA_764369 if SMP select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if SMP + select HAVE_ARM_TWD select PCI_DOMAINS if PCI select PINCTRL_IMX6Q select SOC_IMX6 diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index 5b7a1e7..2f6067b 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c @@ -17,13 +17,6 @@ */ #include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/err.h> -#include <linux/i2c.h> -#include <linux/i2c-pnx.h> -#include <linux/io.h> #include <asm/mach/map.h> #include <asm/system_info.h> @@ -44,19 +37,6 @@ void lpc32xx_get_uid(u32 devid[4]) } /* - * Returns SYSCLK source - * 0 = PLL397, 1 = main oscillator - */ -int clk_is_sysclk_mainosc(void) -{ - if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) & - LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0) - return 1; - - return 0; -} - -/* * Detects and returns IRAM size for the device variation */ #define LPC32XX_IRAM_BANK_SIZE SZ_128K @@ -87,81 +67,6 @@ u32 lpc32xx_return_iram_size(void) } EXPORT_SYMBOL_GPL(lpc32xx_return_iram_size); -/* - * Computes PLL rate from PLL register and input clock - */ -u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup) -{ - u32 ilfreq, p, m, n, fcco, fref, cfreq; - int mode; - - /* - * PLL requirements - * ifreq must be >= 1MHz and <= 20MHz - * FCCO must be >= 156MHz and <= 320MHz - * FREF must be >= 1MHz and <= 27MHz - * Assume the passed input data is not valid - */ - - ilfreq = ifreq; - m = pllsetup->pll_m; - n = pllsetup->pll_n; - p = pllsetup->pll_p; - - mode = (pllsetup->cco_bypass_b15 << 2) | - (pllsetup->direct_output_b14 << 1) | - pllsetup->fdbk_div_ctrl_b13; - - switch (mode) { - case 0x0: /* Non-integer mode */ - cfreq = (m * ilfreq) / (2 * p * n); - fcco = (m * ilfreq) / n; - fref = ilfreq / n; - break; - - case 0x1: /* integer mode */ - cfreq = (m * ilfreq) / n; - fcco = (m * ilfreq) / (n * 2 * p); - fref = ilfreq / n; - break; - - case 0x2: - case 0x3: /* Direct mode */ - cfreq = (m * ilfreq) / n; - fcco = cfreq; - fref = ilfreq / n; - break; - - case 0x4: - case 0x5: /* Bypass mode */ - cfreq = ilfreq / (2 * p); - fcco = 156000000; - fref = 1000000; - break; - - case 0x6: - case 0x7: /* Direct bypass mode */ - default: - cfreq = ilfreq; - fcco = 156000000; - fref = 1000000; - break; - } - - if (fcco < 156000000 || fcco > 320000000) - cfreq = 0; - - if (fref < 1000000 || fref > 27000000) - cfreq = 0; - - return (u32) cfreq; -} - -u32 clk_get_pclk_div(void) -{ - return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F); -} - static struct map_desc lpc32xx_io_desc[] __initdata = { { .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START), diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h index 2d90801..30c9e64 100644 --- a/arch/arm/mach-lpc32xx/common.h +++ b/arch/arm/mach-lpc32xx/common.h @@ -19,37 +19,15 @@ #ifndef __LPC32XX_COMMON_H #define __LPC32XX_COMMON_H -#include <mach/board.h> -#include <linux/platform_device.h> -#include <linux/reboot.h> +#include <linux/init.h> /* * Other arch specific structures and functions */ -extern void lpc32xx_timer_init(void); extern void __init lpc32xx_init_irq(void); extern void __init lpc32xx_map_io(void); extern void __init lpc32xx_serial_init(void); - -/* - * Structure used for setting up and querying the PLLS - */ -struct clk_pll_setup { - int analog_on; - int cco_bypass_b15; - int direct_output_b14; - int fdbk_div_ctrl_b13; - int pll_p; - int pll_n; - u32 pll_m; -}; - -extern int clk_is_sysclk_mainosc(void); -extern u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup); -extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval); -extern u32 clk_get_pclk_div(void); - /* * Returns the LPC32xx unique 128-bit chip ID */ diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index f9209d0..81265e8 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -159,7 +159,7 @@ static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = { .dma_filter = pl08x_filter_id, }; -static const struct of_dev_auxdata const lpc32xx_auxdata_lookup[] __initconst = { +static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL), OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL), OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data), diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 8ced4ad..70e49d5 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -10,6 +10,10 @@ menuconfig ARCH_MEDIATEK if ARCH_MEDIATEK +config MACH_MT2701 + bool "MediaTek MT2701 SoCs support" + default ARCH_MEDIATEK + config MACH_MT6589 bool "MediaTek MT6589 SoCs support" default ARCH_MEDIATEK diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 99cc939..45a0520 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -168,8 +168,7 @@ static struct clk *tclk; static void __init clk_init(void) { - tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, - get_tclk()); + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, get_tclk()); orion_clkdev_init(tclk); } diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 0ba6a0e..04e276c 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ +ccflags-y := -I$(srctree)/$(src)/include \ -I$(srctree)/arch/arm/plat-omap/include # Common support diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 2c04f27..0c47543 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -327,6 +327,11 @@ static int irq_cpu_hotplug_notify(struct notifier_block *self, { unsigned int cpu = (unsigned int)hcpu; + /* + * Corresponding FROZEN transitions do not have to be handled, + * they are handled by at a higher level + * (drivers/cpuidle/coupled.c). + */ switch (action) { case CPU_ONLINE: wakeupgen_irqmask_all(cpu, 0); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 2af6ff6..83cb527 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2207,15 +2207,15 @@ static int _idle(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: idling\n", oh->name); + if (_are_all_hardreset_lines_asserted(oh)) + return 0; + if (oh->_state != _HWMOD_STATE_ENABLED) { WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", oh->name); return -EINVAL; } - if (_are_all_hardreset_lines_asserted(oh)) - return 0; - if (oh->class->sysc) _idle_sysc(oh); _del_initiator_dep(oh, mpu_oh); @@ -2262,6 +2262,9 @@ static int _shutdown(struct omap_hwmod *oh) int ret, i; u8 prev_state; + if (_are_all_hardreset_lines_asserted(oh)) + return 0; + if (oh->_state != _HWMOD_STATE_IDLE && oh->_state != _HWMOD_STATE_ENABLED) { WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", @@ -2269,9 +2272,6 @@ static int _shutdown(struct omap_hwmod *oh) return -EINVAL; } - if (_are_all_hardreset_lines_asserted(oh)) - return 0; - pr_debug("omap_hwmod: %s: disabling\n", oh->name); if (oh->class->pre_shutdown) { diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 7c7a311..4041bad 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -754,6 +754,8 @@ const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh); */ extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh); +void omap_hwmod_rtc_unlock(struct omap_hwmod *oh); +void omap_hwmod_rtc_lock(struct omap_hwmod *oh); /* * Chip variant-specific hwmod init routines - XXX should be converted diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 907a452b..aed3362 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -918,6 +918,8 @@ static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { static struct omap_hwmod_class am33xx_rtc_hwmod_class = { .name = "rtc", .sysc = &am33xx_rtc_sysc, + .unlock = &omap_hwmod_rtc_unlock, + .lock = &omap_hwmod_rtc_lock, }; struct omap_hwmod am33xx_rtc_hwmod = { diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 9442d89..d0e7e525 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -383,6 +383,68 @@ static struct omap_hwmod dra7xx_dcan2_hwmod = { }, }; +/* pwmss */ +static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x4, + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +/* + * epwmss class + */ +static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = { + .name = "epwmss", + .sysc = &dra7xx_epwmss_sysc, +}; + +/* epwmss0 */ +static struct omap_hwmod dra7xx_epwmss0_hwmod = { + .name = "epwmss0", + .class = &dra7xx_epwmss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .modulemode = MODULEMODE_SWCTRL, + .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET, + }, + }, +}; + +/* epwmss1 */ +static struct omap_hwmod dra7xx_epwmss1_hwmod = { + .name = "epwmss1", + .class = &dra7xx_epwmss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .modulemode = MODULEMODE_SWCTRL, + .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET, + }, + }, +}; + +/* epwmss2 */ +static struct omap_hwmod dra7xx_epwmss2_hwmod = { + .name = "epwmss2", + .class = &dra7xx_epwmss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .modulemode = MODULEMODE_SWCTRL, + .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET, + }, + }, +}; + /* * 'dma' class * @@ -1374,6 +1436,52 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = { .sysc = &dra7xx_mcasp_sysc, }; +/* mcasp1 */ +static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" }, + { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp1_hwmod = { + .name = "mcasp1", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "ipu_clkdm", + .main_clk = "mcasp1_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks), +}; + +/* mcasp2 */ +static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" }, + { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp2_hwmod = { + .name = "mcasp2", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp2_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks), +}; + /* mcasp3 */ static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = { { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" }, @@ -1396,6 +1504,116 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = { .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks), }; +/* mcasp4 */ +static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp4_hwmod = { + .name = "mcasp4", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp4_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks), +}; + +/* mcasp5 */ +static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp5_hwmod = { + .name = "mcasp5", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp5_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks), +}; + +/* mcasp6 */ +static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp6_hwmod = { + .name = "mcasp6", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp6_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks), +}; + +/* mcasp7 */ +static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp7_hwmod = { + .name = "mcasp7", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp7_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp7_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks), +}; + +/* mcasp8 */ +static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp8_hwmod = { + .name = "mcasp8", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp8_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp8_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks), +}; + /* * 'mmc' class * @@ -1707,6 +1925,8 @@ static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = { static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = { .name = "rtcss", .sysc = &dra7xx_rtcss_sysc, + .unlock = &omap_hwmod_rtc_unlock, + .lock = &omap_hwmod_rtc_lock, }; /* rtcss */ @@ -2065,6 +2285,20 @@ static struct omap_hwmod dra7xx_timer11_hwmod = { }, }; +/* timer12 */ +static struct omap_hwmod dra7xx_timer12_hwmod = { + .name = "timer12", + .class = &dra7xx_timer_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "secure_32k_clk_src_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET, + }, + }, +}; + /* timer13 */ static struct omap_hwmod dra7xx_timer13_hwmod = { .name = "timer13", @@ -2726,6 +2960,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per2 -> mcasp1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mcasp1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mcasp1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mcasp2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mcasp2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per2 -> mcasp3 */ static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = { .master = &dra7xx_l4_per2_hwmod, @@ -2742,6 +3008,46 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per2 -> mcasp4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp5 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp5_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp6 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp6_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp7 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp7_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp8 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp8_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per1 -> elm */ static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = { .master = &dra7xx_l4_per1_hwmod, @@ -3281,6 +3587,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_wkup -> timer12 */ +static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = { + .master = &dra7xx_l4_wkup_hwmod, + .slave = &dra7xx_timer12_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per3 -> timer13 */ static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = { .master = &dra7xx_l4_per3_hwmod, @@ -3465,6 +3779,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per2 -> epwmss0 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_epwmss0_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU, +}; + +/* l4_per2 -> epwmss1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_epwmss1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU, +}; + +/* l4_per2 -> epwmss2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_epwmss2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU, +}; + static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__dmm, &dra7xx_l3_main_2__l3_instr, @@ -3484,8 +3822,17 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_wkup__dcan1, &dra7xx_l4_per2__dcan2, &dra7xx_l4_per2__cpgmac0, + &dra7xx_l4_per2__mcasp1, + &dra7xx_l3_main_1__mcasp1, + &dra7xx_l4_per2__mcasp2, + &dra7xx_l3_main_1__mcasp2, &dra7xx_l4_per2__mcasp3, &dra7xx_l3_main_1__mcasp3, + &dra7xx_l4_per2__mcasp4, + &dra7xx_l4_per2__mcasp5, + &dra7xx_l4_per2__mcasp6, + &dra7xx_l4_per2__mcasp7, + &dra7xx_l4_per2__mcasp8, &dra7xx_gmac__mdio, &dra7xx_l4_cfg__dma_system, &dra7xx_l3_main_1__tpcc, @@ -3577,9 +3924,19 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__vcp2, &dra7xx_l4_per2__vcp2, &dra7xx_l4_wkup__wd_timer2, + &dra7xx_l4_per2__epwmss0, + &dra7xx_l4_per2__epwmss1, + &dra7xx_l4_per2__epwmss2, + NULL, +}; + +/* GP-only hwmod links */ +static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = { + &dra7xx_l4_wkup__timer12, NULL, }; +/* SoC variant specific hwmod links */ static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per3__usb_otg_ss4, NULL, @@ -3597,9 +3954,12 @@ int __init dra7xx_hwmod_init(void) ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); if (!ret && soc_is_dra74x()) - return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); + ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); else if (!ret && soc_is_dra72x()) - return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); + ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); + + if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP) + ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs); return ret; } diff --git a/arch/arm/mach-omap2/omap_hwmod_reset.c b/arch/arm/mach-omap2/omap_hwmod_reset.c index 65e186c..b68f9c0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_reset.c +++ b/arch/arm/mach-omap2/omap_hwmod_reset.c @@ -29,6 +29,16 @@ #include <sound/aess.h> #include "omap_hwmod.h" +#include "common.h" + +#define OMAP_RTC_STATUS_REG 0x44 +#define OMAP_RTC_KICK0_REG 0x6c +#define OMAP_RTC_KICK1_REG 0x70 + +#define OMAP_RTC_KICK0_VALUE 0x83E70B13 +#define OMAP_RTC_KICK1_VALUE 0x95A4F1E0 +#define OMAP_RTC_STATUS_BUSY BIT(0) +#define OMAP_RTC_MAX_READY_TIME 50 /** * omap_hwmod_aess_preprogram - enable AESS internal autogating @@ -51,3 +61,58 @@ int omap_hwmod_aess_preprogram(struct omap_hwmod *oh) return 0; } + +/** + * omap_rtc_wait_not_busy - Wait for the RTC BUSY flag + * @oh: struct omap_hwmod * + * + * For updating certain RTC registers, the MPU must wait + * for the BUSY status in OMAP_RTC_STATUS_REG to become zero. + * Once the BUSY status is zero, there is a 15 microseconds access + * period in which the MPU can program. + */ +static void omap_rtc_wait_not_busy(struct omap_hwmod *oh) +{ + int i; + + /* BUSY may stay active for 1/32768 second (~30 usec) */ + omap_test_timeout(omap_hwmod_read(oh, OMAP_RTC_STATUS_REG) + & OMAP_RTC_STATUS_BUSY, OMAP_RTC_MAX_READY_TIME, i); + /* now we have ~15 microseconds to read/write various registers */ +} + +/** + * omap_hwmod_rtc_unlock - Unlock the Kicker mechanism. + * @oh: struct omap_hwmod * + * + * RTC IP have kicker feature. This prevents spurious writes to its registers. + * In order to write into any of the RTC registers, KICK values has te be + * written in respective KICK registers. This is needed for hwmod to write into + * sysconfig register. + */ +void omap_hwmod_rtc_unlock(struct omap_hwmod *oh) +{ + local_irq_disable(); + omap_rtc_wait_not_busy(oh); + omap_hwmod_write(OMAP_RTC_KICK0_VALUE, oh, OMAP_RTC_KICK0_REG); + omap_hwmod_write(OMAP_RTC_KICK1_VALUE, oh, OMAP_RTC_KICK1_REG); + local_irq_enable(); +} + +/** + * omap_hwmod_rtc_lock - Lock the Kicker mechanism. + * @oh: struct omap_hwmod * + * + * RTC IP have kicker feature. This prevents spurious writes to its registers. + * Once the RTC registers are written, KICK mechanism needs to be locked, + * in order to prevent any spurious writes. This function locks back the RTC + * registers once hwmod completes its write into sysconfig register. + */ +void omap_hwmod_rtc_lock(struct omap_hwmod *oh) +{ + local_irq_disable(); + omap_rtc_wait_not_busy(oh); + omap_hwmod_write(0x0, oh, OMAP_RTC_KICK0_REG); + omap_hwmod_write(0x0, oh, OMAP_RTC_KICK1_REG); + local_irq_enable(); +} diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c index 287a203..0ec2d00 100644 --- a/arch/arm/mach-omap2/powerdomains7xx_data.c +++ b/arch/arm/mach-omap2/powerdomains7xx_data.c @@ -35,7 +35,7 @@ static struct powerdomain iva_7xx_pwrdm = { .name = "iva_pwrdm", .prcm_offs = DRA7XX_PRM_IVA_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 4, .pwrsts_mem_ret = { @@ -45,10 +45,10 @@ static struct powerdomain iva_7xx_pwrdm = { [3] = PWRSTS_OFF_RET, /* tcm2_mem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* hwa_mem */ - [1] = PWRSTS_OFF_RET, /* sl2_mem */ - [2] = PWRSTS_OFF_RET, /* tcm1_mem */ - [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + [0] = PWRSTS_ON, /* hwa_mem */ + [1] = PWRSTS_ON, /* sl2_mem */ + [2] = PWRSTS_ON, /* tcm1_mem */ + [3] = PWRSTS_ON, /* tcm2_mem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -75,7 +75,7 @@ static struct powerdomain ipu_7xx_pwrdm = { .name = "ipu_pwrdm", .prcm_offs = DRA7XX_PRM_IPU_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 2, .pwrsts_mem_ret = { @@ -83,8 +83,8 @@ static struct powerdomain ipu_7xx_pwrdm = { [1] = PWRSTS_OFF_RET, /* periphmem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* aessmem */ - [1] = PWRSTS_OFF_RET, /* periphmem */ + [0] = PWRSTS_ON, /* aessmem */ + [1] = PWRSTS_ON, /* periphmem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -94,14 +94,14 @@ static struct powerdomain dss_7xx_pwrdm = { .name = "dss_pwrdm", .prcm_offs = DRA7XX_PRM_DSS_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* dss_mem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* dss_mem */ + [0] = PWRSTS_ON, /* dss_mem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -112,15 +112,15 @@ static struct powerdomain l4per_7xx_pwrdm = { .prcm_offs = DRA7XX_PRM_L4PER_INST, .prcm_partition = DRA7XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 2, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* nonretained_bank */ [1] = PWRSTS_OFF_RET, /* retained_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* nonretained_bank */ - [1] = PWRSTS_OFF_RET, /* retained_bank */ + [0] = PWRSTS_ON, /* nonretained_bank */ + [1] = PWRSTS_ON, /* retained_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -136,7 +136,7 @@ static struct powerdomain gpu_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* gpu_mem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* gpu_mem */ + [0] = PWRSTS_ON, /* gpu_mem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -160,7 +160,7 @@ static struct powerdomain core_7xx_pwrdm = { .name = "core_pwrdm", .prcm_offs = DRA7XX_PRM_CORE_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_INA_ON, + .pwrsts = PWRSTS_ON, .pwrsts_logic_ret = PWRSTS_RET, .banks = 5, .pwrsts_mem_ret = { @@ -171,11 +171,11 @@ static struct powerdomain core_7xx_pwrdm = { [4] = PWRSTS_OFF_RET, /* ipu_unicache */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* core_nret_bank */ - [1] = PWRSTS_OFF_RET, /* core_ocmram */ - [2] = PWRSTS_OFF_RET, /* core_other_bank */ - [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ - [4] = PWRSTS_OFF_RET, /* ipu_unicache */ + [0] = PWRSTS_ON, /* core_nret_bank */ + [1] = PWRSTS_ON, /* core_ocmram */ + [2] = PWRSTS_ON, /* core_other_bank */ + [3] = PWRSTS_ON, /* ipu_l2ram */ + [4] = PWRSTS_ON, /* ipu_unicache */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -225,14 +225,14 @@ static struct powerdomain vpe_7xx_pwrdm = { .name = "vpe_pwrdm", .prcm_offs = DRA7XX_PRM_VPE_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_OFF_ON, + .pwrsts_logic_ret = PWRSTS_OFF, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* vpe_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* vpe_bank */ + [0] = PWRSTS_ON, /* vpe_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -250,8 +250,8 @@ static struct powerdomain mpu_7xx_pwrdm = { [1] = PWRSTS_RET, /* mpu_ram */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* mpu_l2 */ - [1] = PWRSTS_OFF_RET, /* mpu_ram */ + [0] = PWRSTS_ON, /* mpu_l2 */ + [1] = PWRSTS_ON, /* mpu_ram */ }, }; @@ -261,7 +261,7 @@ static struct powerdomain l3init_7xx_pwrdm = { .prcm_offs = DRA7XX_PRM_L3INIT_INST, .prcm_partition = DRA7XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 3, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* gmac_bank */ @@ -269,9 +269,9 @@ static struct powerdomain l3init_7xx_pwrdm = { [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* gmac_bank */ - [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ - [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ + [0] = PWRSTS_ON, /* gmac_bank */ + [1] = PWRSTS_ON, /* l3init_bank1 */ + [2] = PWRSTS_ON, /* l3init_bank2 */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -287,7 +287,7 @@ static struct powerdomain eve3_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* eve3_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve3_bank */ + [0] = PWRSTS_ON, /* eve3_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -303,7 +303,7 @@ static struct powerdomain emu_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* emu_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* emu_bank */ + [0] = PWRSTS_ON, /* emu_bank */ }, }; @@ -320,9 +320,9 @@ static struct powerdomain dsp2_7xx_pwrdm = { [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* dsp2_edma */ - [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ - [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ + [0] = PWRSTS_ON, /* dsp2_edma */ + [1] = PWRSTS_ON, /* dsp2_l1 */ + [2] = PWRSTS_ON, /* dsp2_l2 */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -340,9 +340,9 @@ static struct powerdomain dsp1_7xx_pwrdm = { [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* dsp1_edma */ - [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ - [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ + [0] = PWRSTS_ON, /* dsp1_edma */ + [1] = PWRSTS_ON, /* dsp1_l1 */ + [2] = PWRSTS_ON, /* dsp1_l2 */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -358,7 +358,7 @@ static struct powerdomain cam_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* vip_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* vip_bank */ + [0] = PWRSTS_ON, /* vip_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -374,7 +374,7 @@ static struct powerdomain eve4_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* eve4_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve4_bank */ + [0] = PWRSTS_ON, /* eve4_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -390,7 +390,7 @@ static struct powerdomain eve2_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* eve2_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve2_bank */ + [0] = PWRSTS_ON, /* eve2_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -406,7 +406,7 @@ static struct powerdomain eve1_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* eve1_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve1_bank */ + [0] = PWRSTS_ON, /* eve1_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 364418c..2aa01c2 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -39,82 +39,10 @@ #include <linux/of.h> /* - * Test if multicore OMAP support is needed + * OMAP2+ is always defined as ARCH_MULTIPLATFORM in Kconfig */ #undef MULTI_OMAP2 -#undef OMAP_NAME - -#ifdef CONFIG_ARCH_MULTIPLATFORM #define MULTI_OMAP2 -#endif -#ifdef CONFIG_SOC_OMAP2420 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2420 -# endif -#endif -#ifdef CONFIG_SOC_OMAP2430 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2430 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP3 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap3 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP4 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap4 -# endif -#endif - -#ifdef CONFIG_SOC_OMAP5 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap5 -# endif -#endif - -#ifdef CONFIG_SOC_AM33XX -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME am33xx -# endif -#endif - -#ifdef CONFIG_SOC_AM43XX -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME am43xx -# endif -#endif - -#ifdef CONFIG_SOC_DRA7XX -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME DRA7XX -# endif -#endif /* * Omap device type i.e. EMU/HS/TST/GP/BAD @@ -242,11 +170,6 @@ IS_AM_SUBCLASS(437x, 0x437) IS_DRA_SUBCLASS(75x, 0x75) IS_DRA_SUBCLASS(72x, 0x72) -#define soc_is_omap24xx() 0 -#define soc_is_omap242x() 0 -#define soc_is_omap243x() 0 -#define soc_is_omap34xx() 0 -#define soc_is_omap343x() 0 #define soc_is_ti81xx() 0 #define soc_is_ti816x() 0 #define soc_is_ti814x() 0 @@ -265,46 +188,27 @@ IS_DRA_SUBCLASS(72x, 0x72) #define soc_is_dra74x() 0 #define soc_is_dra72x() 0 -#if defined(MULTI_OMAP2) -# if defined(CONFIG_ARCH_OMAP2) -# undef soc_is_omap24xx -# define soc_is_omap24xx() is_omap24xx() -# endif -# if defined (CONFIG_SOC_OMAP2420) -# undef soc_is_omap242x -# define soc_is_omap242x() is_omap242x() -# endif -# if defined (CONFIG_SOC_OMAP2430) -# undef soc_is_omap243x -# define soc_is_omap243x() is_omap243x() -# endif -# if defined(CONFIG_ARCH_OMAP3) -# undef soc_is_omap34xx -# undef soc_is_omap343x -# define soc_is_omap34xx() is_omap34xx() -# define soc_is_omap343x() is_omap343x() -# endif +#if defined(CONFIG_ARCH_OMAP2) +# define soc_is_omap24xx() is_omap24xx() #else -# if defined(CONFIG_ARCH_OMAP2) -# undef soc_is_omap24xx -# define soc_is_omap24xx() 1 -# endif -# if defined(CONFIG_SOC_OMAP2420) -# undef soc_is_omap242x -# define soc_is_omap242x() 1 -# endif -# if defined(CONFIG_SOC_OMAP2430) -# undef soc_is_omap243x -# define soc_is_omap243x() 1 -# endif -# if defined(CONFIG_ARCH_OMAP3) -# undef soc_is_omap34xx -# define soc_is_omap34xx() 1 -# endif -# if defined(CONFIG_SOC_OMAP3430) -# undef soc_is_omap343x -# define soc_is_omap343x() 1 -# endif +# define soc_is_omap24xx() 0 +#endif +#if defined(CONFIG_SOC_OMAP2420) +# define soc_is_omap242x() is_omap242x() +#else +# define soc_is_omap242x() 0 +#endif +#if defined(CONFIG_SOC_OMAP2430) +# define soc_is_omap243x() is_omap243x() +#else +# define soc_is_omap243x() 0 +#endif +#if defined(CONFIG_ARCH_OMAP3) +# define soc_is_omap34xx() is_omap34xx() +# define soc_is_omap343x() is_omap343x() +#else +# define soc_is_omap34xx() 0 +# define soc_is_omap343x() 0 #endif /* @@ -339,7 +243,6 @@ IS_OMAP_TYPE(3430, 0x3430) #define soc_is_omap5430() 0 /* These are needed for the common code */ -#ifdef CONFIG_ARCH_OMAP2PLUS #define soc_is_omap7xx() 0 #define soc_is_omap15xx() 0 #define soc_is_omap16xx() 0 @@ -350,7 +253,6 @@ IS_OMAP_TYPE(3430, 0x3430) #define soc_is_omap1710() 0 #define cpu_class_is_omap1() 0 #define cpu_class_is_omap2() 1 -#endif #if defined(CONFIG_ARCH_OMAP2) # undef soc_is_omap2420 diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 70c3366..058994e 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -66,8 +66,7 @@ static struct clk *tclk; void __init clk_init(void) { - tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, - orion5x_tclk); + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, orion5x_tclk); orion_clkdev_init(tclk); } diff --git a/arch/arm/mach-oxnas/Kconfig b/arch/arm/mach-oxnas/Kconfig new file mode 100644 index 0000000..4fff3c7 --- /dev/null +++ b/arch/arm/mach-oxnas/Kconfig @@ -0,0 +1,24 @@ +menuconfig ARCH_OXNAS + bool "Oxford Semiconductor OXNAS Family SoCs" + select ARCH_REQUIRE_GPIOLIB + select ARCH_HAS_RESET_CONTROLLER + select PINCTRL + depends on ARCH_MULTI_V5 + help + Support for OxNas SoC family developed by Oxford Semiconductor. + +if ARCH_OXNAS + +config MACH_OX810SE + bool "Support OX810SE Based Products" + select ARM_TIMER_SP804 + select COMMON_CLK_OXNAS + select CPU_ARM926T + select MFD_SYSCON + select PINCTRL_OXNAS + select RESET_OXNAS + select VERSATILE_FPGA_IRQ + help + Include Support for the Oxford Semiconductor OX810SE SoC Based Products. + +endif diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c index 67d79f9..6196a63 100644 --- a/arch/arm/mach-shmobile/timer.c +++ b/arch/arm/mach-shmobile/timer.c @@ -20,28 +20,9 @@ #include "common.h" -static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz, - unsigned int mult, unsigned int div) -{ - /* calculate a worst-case loops-per-jiffy value - * based on maximum cpu core hz setting and the - * __delay() implementation in arch/arm/lib/delay.S - * - * this will result in a longer delay than expected - * when the cpu core runs on lower frequencies. - */ - - unsigned int value = HZ * div / mult; - - if (!preset_lpj) - preset_lpj = max_cpu_core_hz / value; -} - void __init shmobile_init_delay(void) { struct device_node *np, *cpus; - unsigned int div = 0; - bool has_arch_timer = false; u32 max_freq = 0; cpus = of_find_node_by_path("/cpus"); @@ -51,25 +32,32 @@ void __init shmobile_init_delay(void) for_each_child_of_node(cpus, np) { u32 freq; + if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER) && + (of_device_is_compatible(np, "arm,cortex-a7") || + of_device_is_compatible(np, "arm,cortex-a15"))) { + of_node_put(np); + of_node_put(cpus); + return; + } + if (!of_property_read_u32(np, "clock-frequency", &freq)) max_freq = max(max_freq, freq); - - if (of_device_is_compatible(np, "arm,cortex-a8")) { - div = 2; - } else if (of_device_is_compatible(np, "arm,cortex-a9")) { - div = 1; - } else if (of_device_is_compatible(np, "arm,cortex-a7") || - of_device_is_compatible(np, "arm,cortex-a15")) { - div = 1; - has_arch_timer = true; - } } of_node_put(cpus); - if (!max_freq || !div) + if (!max_freq) return; - if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) - shmobile_setup_delay_hz(max_freq, 1, div); + /* + * Calculate a worst-case loops-per-jiffy value + * based on maximum cpu core hz setting and the + * __delay() implementation in arch/arm/lib/delay.S. + * + * This will result in a longer delay than expected + * when the cpu core runs on lower frequencies. + */ + + if (!preset_lpj) + preset_lpj = max_freq / HZ; } diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index a196d14..6f1af29 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -18,11 +18,10 @@ menuconfig ARCH_STI select PL310_ERRATA_769419 if CACHE_L2X0 select RESET_CONTROLLER help - Include support for STiH41x SOCs like STiH415/416 using the device tree - for discovery - More information at Documentation/arm/STiH41x and - at Documentation/devicetree - + Include support for STMicroelectronics' STiH415/416, STiH407/10 and + STiH418 family SoCs using the Device Tree for discovery. More + information can be found in Documentation/arm/sti/ and + Documentation/devicetree. if ARCH_STI diff --git a/arch/arm/mach-uniphier/platsmp.c b/arch/arm/mach-uniphier/platsmp.c index db04142..e802ca8 100644 --- a/arch/arm/mach-uniphier/platsmp.c +++ b/arch/arm/mach-uniphier/platsmp.c @@ -99,16 +99,16 @@ static int __init uniphier_smp_prepare_trampoline(unsigned int max_cpus) int ret; np = of_find_compatible_node(NULL, NULL, "socionext,uniphier-smpctrl"); - of_node_put(np); ret = of_address_to_resource(np, 0, &res); + of_node_put(np); if (!ret) { rom_rsv2_phys = res.start + UNIPHIER_SMPCTRL_ROM_RSV2; } else { /* try old binding too */ np = of_find_compatible_node(NULL, NULL, "socionext,uniphier-system-bus-controller"); - of_node_put(np); ret = of_address_to_resource(np, 1, &res); + of_node_put(np); if (ret) { pr_err("failed to get resource of SMP control\n"); return ret; diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile index f5c1006..73caae7 100644 --- a/arch/arm/mach-vexpress/Makefile +++ b/arch/arm/mach-vexpress/Makefile @@ -4,7 +4,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := \ -I$(srctree)/arch/arm/plat-versatile/include -obj-y := v2m.o +obj-$(CONFIG_ARCH_VEXPRESS) := v2m.o obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o CFLAGS_dcscb.o += -march=armv7-a CFLAGS_REMOVE_dcscb.o = -pg @@ -15,3 +15,5 @@ CFLAGS_tc2_pm.o += -march=armv7-a CFLAGS_REMOVE_tc2_pm.o = -pg obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o + +obj-$(CONFIG_ARCH_MPS2) += v2m-mps2.o diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot new file mode 100644 index 0000000..eacfc3f --- /dev/null +++ b/arch/arm/mach-vexpress/Makefile.boot @@ -0,0 +1,3 @@ +# Empty file waiting for deletion once Makefile.boot isn't needed any more. +# Patch waits for application at +# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 . diff --git a/arch/arm/mach-vexpress/v2m-mps2.c b/arch/arm/mach-vexpress/v2m-mps2.c new file mode 100644 index 0000000..e7ad9c2 --- /dev/null +++ b/arch/arm/mach-vexpress/v2m-mps2.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 ARM Limited + * + * Author: Vladimir Murzin <vladimir.murzin@arm.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <asm/mach/arch.h> + +static const char *const mps2_compat[] __initconst = { + "arm,mps2", + NULL +}; + +DT_MACHINE_START(MPS2DT, "MPS2 (Device Tree Support)") + .dt_compat = mps2_compat, +MACHINE_END |
