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-rw-r--r--arch/arm/mach-ixp4xx/Kconfig2
-rw-r--r--arch/arm/mach-lh7a40x/Kconfig2
-rw-r--r--arch/arm/mach-s3c2410/Kconfig2
-rw-r--r--arch/arm/mm/Kconfig2
4 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 57f23b4..e316bd9 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -133,7 +133,7 @@ config IXP4XX_INDIRECT_PCI
into the kernel and we can use the standard read[bwl]/write[bwl]
macros. This is the preferred method due to speed but it
limits the system to just 64MB of PCI memory. This can be
- problamatic if using video cards and other memory-heavy devices.
+ problematic if using video cards and other memory-heavy devices.
2) If > 64MB of memory space is required, the IXP4xx can be
configured to use indirect registers to access PCI This allows
diff --git a/arch/arm/mach-lh7a40x/Kconfig b/arch/arm/mach-lh7a40x/Kconfig
index 147b019..6f4c6a1 100644
--- a/arch/arm/mach-lh7a40x/Kconfig
+++ b/arch/arm/mach-lh7a40x/Kconfig
@@ -8,7 +8,7 @@ config MACH_KEV7A400
help
Say Y here if you are using the Sharp KEV7A400 development
board. This hardware is discontinued, so I'd be very
- suprised if you wanted this option.
+ surprised if you wanted this option.
config MACH_LPD7A400
bool "LPD7A400 Card Engine"
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 63965c7..9aa26b9 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -91,7 +91,7 @@ config SMDK2440_CPU2442
config MACH_S3C2413
bool
help
- Internal node for S3C2413 verison of SMDK2413, so that
+ Internal node for S3C2413 version of SMDK2413, so that
machine_is_s3c2413() will work when MACH_SMDK2413 is
selected
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c0bfb82..b09a19f 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -197,7 +197,7 @@ config CPU_ARM940T
select CPU_CP15_MPU
help
ARM940T is a member of the ARM9TDMI family of general-
- purpose microprocessors with MPU and seperate 4KB
+ purpose microprocessors with MPU and separate 4KB
instruction and 4KB data cases, each with a 4-word line
length.
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