diff options
Diffstat (limited to 'arch/arm')
140 files changed, 3660 insertions, 2927 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index b87aed0..057beb8 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -154,7 +154,7 @@ machine-$(CONFIG_ARCH_MSM) := msm machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 machine-$(CONFIG_ARCH_MX1) := imx machine-$(CONFIG_ARCH_MX2) := imx -machine-$(CONFIG_ARCH_MX25) := mx25 +machine-$(CONFIG_ARCH_MX25) := imx machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_MX5) := mx5 machine-$(CONFIG_ARCH_MXC91231) := mxc91231 diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig index f0c339f..e648ea3 100644 --- a/arch/arm/configs/mx3_defconfig +++ b/arch/arm/configs/mx3_defconfig @@ -84,6 +84,7 @@ CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_IMX=y +CONFIG_SPI=y CONFIG_W1=y CONFIG_W1_MASTER_MXC=y CONFIG_W1_SLAVE_THERM=y diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 197f9e2..8a9de17 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -1,13 +1,37 @@ config IMX_HAVE_DMA_V1 bool -if ARCH_MX1 - config SOC_IMX1 + bool select CPU_ARM920T select IMX_HAVE_DMA_V1 select IMX_HAVE_IOMUX_V1 + select MXC_AVIC + +config SOC_IMX21 bool + select CPU_ARM926T + select ARCH_MXC_AUDMUX_V1 + select IMX_HAVE_DMA_V1 + select IMX_HAVE_IOMUX_V1 + select MXC_AVIC + +config SOC_IMX25 + bool + select CPU_ARM926T + select ARCH_MXC_AUDMUX_V2 + select ARCH_MXC_IOMUX_V3 + select MXC_AVIC + +config SOC_IMX27 + bool + select CPU_ARM926T + select ARCH_MXC_AUDMUX_V1 + select IMX_HAVE_DMA_V1 + select IMX_HAVE_IOMUX_V1 + select MXC_AVIC + +if ARCH_MX1 comment "MX1 platforms:" config MACH_MXLADS @@ -31,33 +55,17 @@ endif if ARCH_MX2 -config SOC_IMX21 - select CPU_ARM926T - select ARCH_MXC_AUDMUX_V1 - select IMX_HAVE_DMA_V1 - select IMX_HAVE_IOMUX_V1 - bool - -config SOC_IMX27 - select CPU_ARM926T - select ARCH_MXC_AUDMUX_V1 - select IMX_HAVE_DMA_V1 - select IMX_HAVE_IOMUX_V1 - bool - choice prompt "CPUs:" default MACH_MX21 config MACH_MX21 bool "i.MX21 support" - select SOC_IMX21 help This enables support for Freescale's MX2 based i.MX21 processor. config MACH_MX27 bool "i.MX27 support" - select SOC_IMX27 help This enables support for Freescale's MX2 based i.MX27 processor. @@ -71,7 +79,10 @@ comment "MX21 platforms:" config MACH_MX21ADS bool "MX21ADS platform" + select SOC_IMX21 + select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND help Include support for MX21ADS platform. This includes specific @@ -79,24 +90,78 @@ config MACH_MX21ADS endif +if ARCH_MX25 + +comment "MX25 platforms:" + +config MACH_MX25_3DS + bool "Support MX25PDK (3DS) Platform" + select SOC_IMX25 + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMXDI_RTC + select IMX_HAVE_PLATFORM_IMX_FB + select IMX_HAVE_PLATFORM_IMX_KEYPAD + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + +config MACH_EUKREA_CPUIMX25 + bool "Support Eukrea CPUIMX25 Platform" + select SOC_IMX25 + select IMX_HAVE_PLATFORM_FLEXCAN + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMXDI_RTC + select IMX_HAVE_PLATFORM_IMX_FB + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select MXC_ULPI if USB_ULPI + +choice + prompt "Baseboard" + depends on MACH_EUKREA_CPUIMX25 + default MACH_EUKREA_MBIMXSD25_BASEBOARD + +config MACH_EUKREA_MBIMXSD25_BASEBOARD + bool "Eukrea MBIMXSD development board" + select IMX_HAVE_PLATFORM_IMX_SSI + help + This adds board specific devices that can be found on Eukrea's + MBIMXSD evaluation board. + +endchoice + +endif + if MACH_MX27 comment "MX27 platforms:" config MACH_MX27ADS bool "MX27ADS platform" + select SOC_IMX27 + select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_MXC_W1 help Include support for MX27ADS platform. This includes specific configurations for the board and its peripherals. config MACH_PCM038 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" + select SOC_IMX27 + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_MXC_W1 select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help @@ -109,8 +174,9 @@ choice default MACH_PCM970_BASEBOARD config MACH_PCM970_BASEBOARD - prompt "PHYTEC PCM970 development board" - bool + bool "PHYTEC PCM970 development board" + select IMX_HAVE_PLATFORM_IMX_FB + select IMX_HAVE_PLATFORM_MXC_MMC help This adds board specific devices that can be found on Phytec's PCM970 evaluation board. @@ -119,9 +185,14 @@ endchoice config MACH_CPUIMX27 bool "Eukrea CPUIMX27 module" + select SOC_IMX27 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_MXC_W1 select MXC_ULPI if USB_ULPI help Include support for Eukrea CPUIMX27 platform. This includes @@ -130,6 +201,7 @@ config MACH_CPUIMX27 config MACH_EUKREA_CPUIMX27_USESDHC2 bool "CPUIMX27 integrates SDHC2 module" depends on MACH_CPUIMX27 + select IMX_HAVE_PLATFORM_MXC_MMC help This adds support for the internal SDHC2 used on CPUIMX27 for wifi or eMMC. @@ -148,8 +220,11 @@ choice config MACH_EUKREA_MBIMX27_BASEBOARD bool "Eukrea MBIMX27 development board" + select IMX_HAVE_PLATFORM_IMX_FB + select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_SPI_IMX help This adds board specific devices that can be found on Eukrea's @@ -159,15 +234,21 @@ endchoice config MACH_MX27_3DS bool "MX27PDK platform" + select SOC_IMX27 + select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_MMC help Include support for MX27PDK platform. This includes specific configurations for the board and its peripherals. config MACH_IMX27_VISSTRIM_M10 bool "Vista Silicon i.MX27 Visstrim_m10" + select SOC_IMX27 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_MMC + select IMX_HAVE_PLATFORM_MXC_EHCI help Include support for Visstrim_m10 platform and its different variants. This includes specific configurations for the board and its @@ -175,6 +256,7 @@ config MACH_IMX27_VISSTRIM_M10 config MACH_IMX27LITE bool "LogicPD MX27 LITEKIT platform" + select SOC_IMX27 select IMX_HAVE_PLATFORM_IMX_UART help Include support for MX27 LITEKIT platform. This includes specific @@ -182,10 +264,17 @@ config MACH_IMX27LITE config MACH_PCA100 bool "Phytec phyCARD-s (pca100)" + select SOC_IMX27 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_MXC_W1 select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help @@ -194,8 +283,11 @@ config MACH_PCA100 config MACH_MXT_TD60 bool "Maxtrack i-MXT TD60" + select SOC_IMX27 + select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND help Include support for i-MXT (aka td60) platform. This diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 5582692..77100bf 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -4,13 +4,13 @@ # Object file lists. -obj-y := devices.o - obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o +obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o + obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o @@ -22,6 +22,10 @@ obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o +obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o +obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o +obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o + obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index 7988a85..3953d60 100644 --- a/arch/arm/mach-imx/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot @@ -6,6 +6,10 @@ zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000 params_phys-$(CONFIG_MACH_MX21) := 0xC0000100 initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000 +zreladdr-$(CONFIG_ARCH_MX25) := 0x80008000 +params_phys-$(CONFIG_ARCH_MX25) := 0x80000100 +initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000 + zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000 params_phys-$(CONFIG_MACH_MX27) := 0xA0000100 initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000 diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-imx/clock-imx25.c index 9e4a557..9e4a557 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-imx/clock-imx25.c diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c index 98a25ba..2202b88 100644 --- a/arch/arm/mach-imx/clock-imx27.c +++ b/arch/arm/mach-imx/clock-imx27.c @@ -125,7 +125,7 @@ static int clk_cpu_set_parent(struct clk *clk, struct clk *parent) if (clk->parent == parent) return 0; - if (mx27_revision() >= CHIP_REV_2_0) { + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { if (parent == &mpll_main1_clk) { cscr |= CCM_CSCR_ARM_SRC; } else { @@ -174,7 +174,7 @@ static int set_rate_cpu(struct clk *clk, unsigned long rate) div--; reg = __raw_readl(CCM_CSCR); - if (mx27_revision() >= CHIP_REV_2_0) { + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { reg &= ~(3 << 12); reg |= div << 12; reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN); @@ -244,7 +244,7 @@ static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf) parent_rate = clk_get_rate(clk->parent); - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) pdf += 4; /* MX27 TO2+ */ else pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ @@ -269,7 +269,7 @@ static unsigned long get_rate_nfc(struct clk *clk) parent_rate = clk_get_rate(clk->parent); - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf; else nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf; @@ -284,7 +284,7 @@ static unsigned long get_rate_vpu(struct clk *clk) parent_rate = clk_get_rate(clk->parent); - if (mx27_revision() >= CHIP_REV_2_0) { + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f; vpu_pdf += 4; } else { @@ -347,7 +347,7 @@ static unsigned long get_rate_mpll_main(struct clk *clk) * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2 * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3 */ - if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1) return 2UL * parent_rate / 3UL; return parent_rate; @@ -365,7 +365,7 @@ static unsigned long get_rate_spll(struct clk *clk) /* On TO2 we have to write the value back. Otherwise we * read 0 from this register the next time. */ - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) __raw_writel(reg, CCM_SPCTL0); return mxc_decode_pll(reg, rate); @@ -376,7 +376,7 @@ static unsigned long get_rate_cpu(struct clk *clk) u32 div; unsigned long rate; - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) div = (__raw_readl(CCM_CSCR) >> 12) & 0x3; else div = (__raw_readl(CCM_CSCR) >> 13) & 0x7; @@ -389,7 +389,7 @@ static unsigned long get_rate_ahb(struct clk *clk) { unsigned long rate, bclk_pdf; - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3; else bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf; @@ -402,7 +402,7 @@ static unsigned long get_rate_ipg(struct clk *clk) { unsigned long rate, ipg_pdf; - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) return clk_get_rate(clk->parent); else ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1; @@ -683,7 +683,7 @@ static void __init to2_adjust_clocks(void) { unsigned long cscr = __raw_readl(CCM_CSCR); - if (mx27_revision() >= CHIP_REV_2_0) { + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { if (cscr & CCM_CSCR_ARM_SRC) cpu_clk.parent = &mpll_main1_clk; diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c index d8d3b2d..3b117be 100644 --- a/arch/arm/mach-imx/cpu-imx27.c +++ b/arch/arm/mach-imx/cpu-imx27.c @@ -42,7 +42,19 @@ static void query_silicon_parameter(void) val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + SYS_CHIP_ID)); - cpu_silicon_rev = (int)(val >> 28); + switch (val >> 28) { + case 0: + cpu_silicon_rev = IMX_CHIP_REVISION_1_0; + break; + case 1: + cpu_silicon_rev = IMX_CHIP_REVISION_2_0; + break; + case 2: + cpu_silicon_rev = IMX_CHIP_REVISION_2_1; + break; + default: + cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN; + } cpu_partnumber = (int)((val >> 12) & 0xFFFF); } diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h index d189039..16744d2 100644 --- a/arch/arm/mach-imx/devices-imx21.h +++ b/arch/arm/mach-imx/devices-imx21.h @@ -9,10 +9,26 @@ #include <mach/mx21.h> #include <mach/devices-common.h> +extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst; +#define imx21_add_imx21_hcd(pdata) \ + imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata) + +extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst; +#define imx21_add_imx2_wdt(pdata) \ + imx_add_imx2_wdt(&imx21_imx2_wdt_data) + +extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst; +#define imx21_add_imx_fb(pdata) \ + imx_add_imx_fb(&imx21_imx_fb_data, pdata) + extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst; #define imx21_add_imx_i2c(pdata) \ imx_add_imx_i2c(&imx21_imx_i2c_data, pdata) +extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst; +#define imx21_add_imx_keypad(pdata) \ + imx_add_imx_keypad(&imx21_imx_keypad_data, pdata) + extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst; #define imx21_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata) @@ -25,10 +41,18 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst; #define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata) #define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata) +extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst; +#define imx21_add_mxc_mmc(id, pdata) \ + imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata) + extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst; #define imx21_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) +extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst; +#define imx21_add_mxc_w1(pdata) \ + imx_add_mxc_w1(&imx21_mxc_w1_data) + extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst; #define imx21_add_cspi(id, pdata) \ imx_add_spi_imx(&imx21_cspi_data[id], pdata) diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h index d94d282..bde33ca 100644 --- a/arch/arm/mach-mx25/devices-imx25.h +++ b/arch/arm/mach-imx/devices-imx25.h @@ -13,10 +13,27 @@ extern const struct imx_fec_data imx25_fec_data __initconst; #define imx25_add_fec(pdata) \ imx_add_fec(&imx25_fec_data, pdata) -#define imx25_add_flexcan0(pdata) \ - imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata) -#define imx25_add_flexcan1(pdata) \ - imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata) +extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst; +#define imx25_add_flexcan(id, pdata) \ + imx_add_flexcan(&imx25_flexcan_data[id], pdata) +#define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata) +#define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata) + +extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst; +#define imx25_add_fsl_usb2_udc(pdata) \ + imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata) + +extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst; +#define imx25_add_imxdi_rtc(pdata) \ + imx_add_imxdi_rtc(&imx25_imxdi_rtc_data) + +extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst; +#define imx25_add_imx2_wdt(pdata) \ + imx_add_imx2_wdt(&imx25_imx2_wdt_data) + +extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst; +#define imx25_add_imx_fb(pdata) \ + imx_add_imx_fb(&imx25_imx_fb_data, pdata) extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst; #define imx25_add_imx_i2c(id, pdata) \ @@ -25,6 +42,10 @@ extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst; #define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata) #define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata) +extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst; +#define imx25_add_imx_keypad(pdata) \ + imx_add_imx_keypad(&imx25_imx_keypad_data, pdata) + extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst; #define imx25_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata) @@ -38,17 +59,29 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst; #define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata) #define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata) +extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst; +#define imx25_add_mx2_camera(pdata) \ + imx_add_mx2_camera(&imx25_mx2_camera_data, pdata) + +extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst; +#define imx25_add_mxc_ehci_otg(pdata) \ + imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata) +extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst; +#define imx25_add_mxc_ehci_hs(pdata) \ + imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata) + extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst; #define imx25_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx25_mxc_nand_data, pdata) +extern const struct imx_sdhci_esdhc_imx_data +imx25_sdhci_esdhc_imx_data[] __initconst; +#define imx25_add_sdhci_esdhc_imx(id, pdata) \ + imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata) + extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst; #define imx25_add_spi_imx(id, pdata) \ - imx_add_spi_imx(&imx25_cspi_data[id], pdata) + imx_add_spi_imx(&imx25_spi_imx_data[id], pdata) #define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) #define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) #define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) - -extern const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst; -#define imx25_add_esdhc(id, pdata) \ - imx_add_esdhc(&imx25_esdhc_data[id], pdata) diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index 7011690..f1272d4 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h @@ -13,10 +13,26 @@ extern const struct imx_fec_data imx27_fec_data __initconst; #define imx27_add_fec(pdata) \ imx_add_fec(&imx27_fec_data, pdata) +extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst; +#define imx27_add_fsl_usb2_udc(pdata) \ + imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata) + +extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst; +#define imx27_add_imx2_wdt(pdata) \ + imx_add_imx2_wdt(&imx27_imx2_wdt_data) + +extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst; +#define imx27_add_imx_fb(pdata) \ + imx_add_imx_fb(&imx27_imx_fb_data, pdata) + extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst; #define imx27_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata) +extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst; +#define imx27_add_imx_keypad(pdata) \ + imx_add_imx_keypad(&imx27_imx_keypad_data, pdata) + extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst; #define imx27_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata) @@ -31,10 +47,29 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst; #define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata) #define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata) +extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst; +#define imx27_add_mx2_camera(pdata) \ + imx_add_mx2_camera(&imx27_mx2_camera_data, pdata) + +extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst; +#define imx27_add_mxc_ehci_otg(pdata) \ + imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata) +extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst; +#define imx27_add_mxc_ehci_hs(id, pdata) \ + imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata) + +extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst; +#define imx27_add_mxc_mmc(id, pdata) \ + imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata) + extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst; #define imx27_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) +extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst; +#define imx27_add_mxc_w1(pdata) \ + imx_add_mxc_w1(&imx27_mxc_w1_data) + extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst; #define imx27_add_cspi(id, pdata) \ imx_add_spi_imx(&imx27_cspi_data[id], pdata) diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c deleted file mode 100644 index fba5047..0000000 --- a/arch/arm/mach-imx/devices.c +++ /dev/null @@ -1,553 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * <source@mvista.com> - * - * Based on the OMAP devices.c - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * Copyright 2008 Sascha Hauer, kernel@pengutronix.de - * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> - * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/dma-mapping.h> -#include <linux/serial.h> - -#include <mach/irqs.h> -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/mmc.h> - -#include "devices.h" - -#if defined(CONFIG_ARCH_MX1) -static struct resource imx1_camera_resources[] = { - { - .start = 0x00224000, - .end = 0x00224010, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_CSI_INT, - .end = MX1_CSI_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 imx1_camera_dmamask = DMA_BIT_MASK(32); - -struct platform_device imx1_camera_device = { - .name = "mx1-camera", - .id = 0, /* This is used to put cameras on this interface */ - .dev = { - .dma_mask = &imx1_camera_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = imx1_camera_resources, - .num_resources = ARRAY_SIZE(imx1_camera_resources), -}; - -static struct resource imx_rtc_resources[] = { - { - .start = 0x00204000, - .end = 0x00204024, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_RTC_INT, - .end = MX1_RTC_INT, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_RTC_SAMINT, - .end = MX1_RTC_SAMINT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_rtc_device = { - .name = "rtc-imx", - .id = 0, - .resource = imx_rtc_resources, - .num_resources = ARRAY_SIZE(imx_rtc_resources), -}; - -static struct resource imx_wdt_resources[] = { - { - .start = 0x00201000, - .end = 0x00201008, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_WDT_INT, - .end = MX1_WDT_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_wdt_device = { - .name = "imx-wdt", - .id = 0, - .resource = imx_wdt_resources, - .num_resources = ARRAY_SIZE(imx_wdt_resources), -}; - -static struct resource imx_usb_resources[] = { - { - .start = 0x00212000, - .end = 0x00212148, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_USBD_INT0, - .end = MX1_USBD_INT0, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT1, - .end = MX1_USBD_INT1, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT2, - .end = MX1_USBD_INT2, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT3, - .end = MX1_USBD_INT3, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT4, - .end = MX1_USBD_INT4, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT5, - .end = MX1_USBD_INT5, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT6, - .end = MX1_USBD_INT6, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_usb_device = { - .name = "imx_udc", - .id = 0, - .num_resources = ARRAY_SIZE(imx_usb_resources), - .resource = imx_usb_resources, -}; - -/* GPIO port description */ -static struct mxc_gpio_port imx_gpio_ports[] = { - { - .chip.label = "gpio-0", - .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), - .irq = MX1_GPIO_INT_PORTA, - .virtual_irq_start = MXC_GPIO_IRQ_START, - }, { - .chip.label = "gpio-1", - .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100), - .irq = MX1_GPIO_INT_PORTB, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, { - .chip.label = "gpio-2", - .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200), - .irq = MX1_GPIO_INT_PORTC, - .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - }, { - .chip.label = "gpio-3", - .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300), - .irq = MX1_GPIO_INT_PORTD, - .virtual_irq_start = MXC_GPIO_IRQ_START + 96, - } -}; - -int __init imx1_register_gpios(void) -{ - return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); -} -#endif - -#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) - -#ifdef CONFIG_MACH_MX27 -static struct resource mx27_camera_resources[] = { - { - .start = MX27_CSI_BASE_ADDR, - .end = MX27_CSI_BASE_ADDR + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_EMMA_PRP_BASE_ADDR, - .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_INT_CSI, - .end = MX27_INT_CSI, - .flags = IORESOURCE_IRQ, - },{ - .start = MX27_INT_EMMAPRP, - .end = MX27_INT_EMMAPRP, - .flags = IORESOURCE_IRQ, - }, -}; -struct platform_device mx27_camera_device = { - .name = "mx2-camera", - .id = 0, - .num_resources = ARRAY_SIZE(mx27_camera_resources), - .resource = mx27_camera_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; -#endif - -/* - * General Purpose Timer - * - i.MX21: 3 timers - * - i.MX27: 6 timers - */ -#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \ - static struct resource timer ## n ##_resources[] = { \ - { \ - .start = baseaddr, \ - .end = baseaddr + SZ_4K - 1, \ - .flags = IORESOURCE_MEM, \ - }, { \ - .start = irq, \ - .end = irq, \ - .flags = IORESOURCE_IRQ, \ - } \ - }; \ - \ - struct platform_device mxc_gpt ## n = { \ - .name = "imx_gpt", \ - .id = n, \ - .num_resources = ARRAY_SIZE(timer ## n ## _resources), \ - .resource = timer ## n ## _resources, \ - } - -/* We use gpt1 as system timer, so do not add a device for this one */ -DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2); -DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3); - -#ifdef CONFIG_MACH_MX27 -DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4); -DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5); -DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); -#endif - -/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */ -static struct resource mxc_wdt_resources[] = { - { - .start = MX2x_WDOG_BASE_ADDR, - .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_wdt = { - .name = "imx2-wdt", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_wdt_resources), - .resource = mxc_wdt_resources, -}; - -static struct resource mxc_w1_master_resources[] = { - { - .start = MX2x_OWIRE_BASE_ADDR, - .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_w1_master_device = { - .name = "mxc_w1", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_w1_master_resources), - .resource = mxc_w1_master_resources, -}; - -/* - * lcdc: - * - i.MX1: the basic controller - * - i.MX21: to be checked - * - i.MX27: like i.MX1, with slightly variations - */ -static struct resource mxc_fb[] = { - { - .start = MX2x_LCDC_BASE_ADDR, - .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX2x_INT_LCDC, - .end = MX2x_INT_LCDC, - .flags = IORESOURCE_IRQ, - } -}; - -/* mxc lcd driver */ -struct platform_device mxc_fb_device = { - .name = "imx-fb", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_fb), - .resource = mxc_fb, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource mxc_pwm_resources[] = { - { - .start = MX2x_PWM_BASE_ADDR, - .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX2x_INT_PWM, - .end = MX2x_INT_PWM, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_pwm_device = { - .name = "mxc_pwm", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_pwm_resources), - .resource = mxc_pwm_resources, -}; - -#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \ - static struct resource mxc_sdhc_resources ## n[] = { \ - { \ - .start = baseaddr, \ - .end = baseaddr + SZ_4K - 1, \ - .flags = IORESOURCE_MEM, \ - }, { \ - .start = irq, \ - .end = irq, \ - .flags = IORESOURCE_IRQ, \ - }, { \ - .start = dmareq, \ - .end = dmareq, \ - .flags = IORESOURCE_DMA, \ - }, \ - }; \ - \ - static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \ - \ - struct platform_device mxc_sdhc_device ## n = { \ - .name = "mxc-mmc", \ - .id = n, \ - .dev = { \ - .dma_mask = &mxc_sdhc ## n ## _dmamask, \ - .coherent_dma_mask = DMA_BIT_MASK(32), \ - }, \ - .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \ - .resource = mxc_sdhc_resources ## n, \ - } - -DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1); -DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2); - -#ifdef CONFIG_MACH_MX27 -static struct resource otg_resources[] = { - { - .start = MX27_USBOTG_BASE_ADDR, - .end = MX27_USBOTG_BASE_ADDR + 0x1ff, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_INT_USB3, - .end = MX27_INT_USB3, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 otg_dmamask = DMA_BIT_MASK(32); - -/* OTG gadget device */ -struct platform_device mxc_otg_udc_device = { - .name = "fsl-usb2-udc", - .id = -1, - .dev = { - .dma_mask = &otg_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), -}; - -/* OTG host */ -struct platform_device mxc_otg_host = { - .name = "mxc-ehci", - .id = 0, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - .dma_mask = &otg_dmamask, - }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), -}; - -/* USB host 1 */ - -static u64 usbh1_dmamask = DMA_BIT_MASK(32); - -static struct resource mxc_usbh1_resources[] = { - { - .start = MX27_USBOTG_BASE_ADDR + 0x200, - .end = MX27_USBOTG_BASE_ADDR + 0x3ff, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_INT_USB1, - .end = MX27_INT_USB1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_usbh1 = { - .name = "mxc-ehci", - .id = 1, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - .dma_mask = &usbh1_dmamask, - }, - .resource = mxc_usbh1_resources, - .num_resources = ARRAY_SIZE(mxc_usbh1_resources), -}; - -/* USB host 2 */ -static u64 usbh2_dmamask = DMA_BIT_MASK(32); - -static struct resource mxc_usbh2_resources[] = { - { - .start = MX27_USBOTG_BASE_ADDR + 0x400, - .end = MX27_USBOTG_BASE_ADDR + 0x5ff, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_INT_USB2, - .end = MX27_INT_USB2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_usbh2 = { - .name = "mxc-ehci", - .id = 2, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - .dma_mask = &usbh2_dmamask, - }, - .resource = mxc_usbh2_resources, - .num_resources = ARRAY_SIZE(mxc_usbh2_resources), -}; -#endif - -/* GPIO port description */ -#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \ - { \ - .chip.label = "gpio-" #n, \ - .irq = _irq, \ - .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ - n * 0x100), \ - .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ - } - -#define DEFINE_MXC_GPIO_PORT(SOC, n) \ - { \ - .chip.label = "gpio-" #n, \ - .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ - n * 0x100), \ - .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ - } - -#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \ - static struct mxc_gpio_port pfx ## _gpio_ports[] = { \ - DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \ - DEFINE_MXC_GPIO_PORT(SOC, 1), \ - DEFINE_MXC_GPIO_PORT(SOC, 2), \ - DEFINE_MXC_GPIO_PORT(SOC, 3), \ - DEFINE_MXC_GPIO_PORT(SOC, 4), \ - DEFINE_MXC_GPIO_PORT(SOC, 5), \ - } - -#ifdef CONFIG_MACH_MX21 -DEFINE_MXC_GPIO_PORTS(MX21, imx21); - -int __init imx21_register_gpios(void) -{ - return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); -} -#endif - -#ifdef CONFIG_MACH_MX27 -DEFINE_MXC_GPIO_PORTS(MX27, imx27); - -int __init imx27_register_gpios(void) -{ - return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); -} -#endif - -#ifdef CONFIG_MACH_MX21 -static struct resource mx21_usbhc_resources[] = { - { - .start = MX21_USBOTG_BASE_ADDR, - .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MX21_INT_USBHOST, - .end = MX21_INT_USBHOST, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mx21_usbhc_device = { - .name = "imx21-hcd", - .id = 0, - .dev = { - .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(mx21_usbhc_resources), - .resource = mx21_usbhc_resources, -}; -#endif - -static struct resource imx_kpp_resources[] = { - { - .start = MX2x_KPP_BASE_ADDR, - .end = MX2x_KPP_BASE_ADDR + 0xf, - .flags = IORESOURCE_MEM - }, { - .start = MX2x_INT_KPP, - .end = MX2x_INT_KPP, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_kpp_device = { - .name = "imx-keypad", - .id = -1, - .num_resources = ARRAY_SIZE(imx_kpp_resources), - .resource = imx_kpp_resources, -}; - -#endif diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h deleted file mode 100644 index 807f02a..0000000 --- a/arch/arm/mach-imx/devices.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifdef CONFIG_ARCH_MX1 -extern struct platform_device imx1_camera_device; -extern struct platform_device imx_rtc_device; -extern struct platform_device imx_wdt_device; -extern struct platform_device imx_usb_device; -#endif - -#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) -extern struct platform_device mxc_gpt1; -extern struct platform_device mxc_gpt2; -#ifdef CONFIG_MACH_MX27 -extern struct platform_device mxc_gpt3; -extern struct platform_device mxc_gpt4; -extern struct platform_device mxc_gpt5; -#endif -extern struct platform_device mxc_wdt; -extern struct platform_device mxc_w1_master_device; -extern struct platform_device mxc_fb_device; -extern struct platform_device mxc_pwm_device; -extern struct platform_device mxc_sdhc_device0; -extern struct platform_device mxc_sdhc_device1; -extern struct platform_device mxc_otg_udc_device; -extern struct platform_device mx27_camera_device; -extern struct platform_device mxc_otg_host; -extern struct platform_device mxc_usbh1; -extern struct platform_device mxc_usbh2; -extern struct platform_device mx21_usbhc_device; -extern struct platform_device imx_kpp_device; -#endif diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c index 3e8c47c..e9f1769 100644 --- a/arch/arm/mach-imx/dma-v1.c +++ b/arch/arm/mach-imx/dma-v1.c @@ -818,9 +818,11 @@ static int __init imx_dma_init(void) imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); else #endif - BUG(); + return 0; dma_clk = clk_get(NULL, "dma"); + if (IS_ERR(dma_clk)) + return PTR_ERR(dma_clk); clk_enable(dma_clk); /* reset DMA module */ diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index 7e1e9dc..275c858 100644 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -26,20 +26,16 @@ #include <linux/spi/ads7846.h> #include <linux/backlight.h> #include <video/platform_lcd.h> -#include <linux/input/matrix_keypad.h> #include <asm/mach/arch.h> #include <mach/common.h> #include <mach/iomux-mx27.h> -#include <mach/imxfb.h> #include <mach/hardware.h> -#include <mach/mmc.h> #include <mach/spi.h> #include <mach/audmux.h> #include "devices-imx27.h" -#include "devices.h" static const int eukrea_mbimx27_pins[] __initconst = { /* UART2 */ @@ -111,7 +107,8 @@ static const uint32_t eukrea_mbimx27_keymap[] = { KEY(1, 1, KEY_LEFT), }; -static struct matrix_keymap_data eukrea_mbimx27_keymap_data = { +static const struct matrix_keymap_data +eukrea_mbimx27_keymap_data __initconst = { .keymap = eukrea_mbimx27_keymap, .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap), }; @@ -196,7 +193,7 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = { }, }; -static struct imx_fb_platform_data eukrea_mbimx27_fb_data = { +static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = { .mode = eukrea_mbimx27_modes, .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes), @@ -300,7 +297,7 @@ static struct platform_device *platform_devices[] __initdata = { &leds_gpio, }; -static struct imxmmc_platform_data sdhc_pdata = { +static const struct imxmmc_platform_data sdhc_pdata __initconst = { .dat3_card_detect = 1, }; @@ -345,8 +342,8 @@ void __init eukrea_mbimx27_baseboard_init(void) imx27_add_imx_uart3(&uart_pdata); #endif - mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data); - mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata); + imx27_add_imx_fb(&eukrea_mbimx27_fb_data); + imx27_add_mxc_mmc(0, &sdhc_pdata); i2c_register_board_info(0, eukrea_mbimx27_i2c_devices, ARRAY_SIZE(eukrea_mbimx27_i2c_devices)); @@ -380,7 +377,7 @@ void __init eukrea_mbimx27_baseboard_init(void) gpio_request(GPIO_PORTA | 25, "lcd_enable"); platform_device_register(&eukrea_mbimx27_lcd_powerdev); - mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data); + imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c index e765ac5..cb705c2 100644 --- a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c @@ -33,13 +33,11 @@ #include <asm/mach/arch.h> #include <mach/mx25.h> #include <mach/imx-uart.h> -#include <mach/imxfb.h> #include <mach/audmux.h> #include "devices-imx25.h" -#include "devices.h" -static struct pad_desc eukrea_mbimxsd_pads[] = { +static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { /* LCD */ MX25_PAD_LD0__LD0, MX25_PAD_LD1__LD1, @@ -151,7 +149,7 @@ static struct imx_fb_videomode eukrea_mximxsd_modes[] = { }, }; -static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = { +static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = { .mode = eukrea_mximxsd_modes, .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes), .pwmr = 0x00A903FF, @@ -273,11 +271,11 @@ void __init eukrea_mbimxsd25_baseboard_init(void) #endif imx25_add_imx_uart1(&uart_pdata); - mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata); + imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata); imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); imx25_add_flexcan1(NULL); - imx25_add_esdhc(0, NULL); + imx25_add_sdhci_esdhc_imx(0, NULL); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 745ee60..6cf04da 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -28,7 +28,6 @@ #include <linux/serial_8250.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> -#include <linux/fsl_devices.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -40,11 +39,9 @@ #include <mach/hardware.h> #include <mach/iomux-mx27.h> #include <mach/mxc_nand.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx27.h" -#include "devices.h" static const int eukrea_cpuimx27_pins[] __initconst = { /* UART1 */ @@ -157,8 +154,6 @@ cpuimx27_nand_board_info __initconst = { static struct platform_device *platform_devices[] __initdata = { &eukrea_cpuimx27_nor_mtd_device, - &mxc_wdt, - &mxc_w1_master_device, }; static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = { @@ -215,18 +210,18 @@ static struct platform_device serial_device = { #endif #if defined(CONFIG_USB_ULPI) -static struct mxc_usbh_platform_data otg_pdata = { +static struct mxc_usbh_platform_data otg_pdata __initdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; #endif -static struct fsl_usb2_platform_data otg_device_pdata = { +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; @@ -262,10 +257,12 @@ static void __init eukrea_cpuimx27_init(void) imx27_add_fec(NULL); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + imx27_add_imx2_wdt(NULL); + imx27_add_mxc_w1(NULL); #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) /* SDHC2 can be used for Wifi */ - mxc_register_device(&mxc_sdhc_device1, NULL); + imx27_add_mxc_mmc(1, NULL); #endif #if defined(MACH_EUKREA_CPUIMX27_USEUART4) /* in which case UART4 is also used for Bluetooth */ @@ -281,16 +278,16 @@ static void __init eukrea_cpuimx27_init(void) otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_otg_host, &otg_pdata); + imx27_add_mxc_ehci_otg(&otg_pdata); } usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx27_add_mxc_ehci_hs(2, &usbh2_pdata); #endif if (!otg_mode_host) - mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + imx27_add_fsl_usb2_udc(&otg_device_pdata); #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD eukrea_mbimx27_baseboard_init(); diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c index f6f9ad6..eb395ab 100644 --- a/arch/arm/mach-mx25/mach-cpuimx25.c +++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c @@ -26,7 +26,6 @@ #include <linux/platform_device.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> -#include <linux/fsl_devices.h> #include <mach/eukrea-baseboards.h> #include <mach/hardware.h> @@ -39,17 +38,15 @@ #include <mach/mx25.h> #include <mach/mxc_nand.h> #include <mach/imxfb.h> -#include <mach/mxc_ehci.h> #include <mach/iomux-mx25.h> #include "devices-imx25.h" -#include "devices.h" static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct pad_desc eukrea_cpuimx25_pads[] = { +static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = { /* FEC - RMII */ MX25_PAD_FEC_MDC__FEC_MDC, MX25_PAD_FEC_MDIO__FEC_MDIO, @@ -87,18 +84,18 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = { }, }; -static struct mxc_usbh_platform_data otg_pdata = { +static const struct mxc_usbh_platform_data otg_pdata __initconst = { .portsc = MXC_EHCI_MODE_UTMI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; -static struct mxc_usbh_platform_data usbh2_pdata = { +static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { .portsc = MXC_EHCI_MODE_SERIAL, .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN, }; -static struct fsl_usb2_platform_data otg_device_pdata = { +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI, }; @@ -126,7 +123,7 @@ static void __init eukrea_cpuimx25_init(void) imx25_add_imx_uart0(&uart_pdata); imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); - mxc_register_device(&mx25_rtc_device, NULL); + imx25_add_imxdi_rtc(NULL); imx25_add_fec(&mx25_fec_pdata); i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, @@ -134,11 +131,11 @@ static void __init eukrea_cpuimx25_init(void) imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data); if (otg_mode_host) - mxc_register_device(&mxc_otg, &otg_pdata); + imx25_add_mxc_ehci_otg(&otg_pdata); else - mxc_register_device(&otg_udc_device, &otg_device_pdata); + imx25_add_fsl_usb2_udc(&otg_device_pdata); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx25_add_mxc_ehci_hs(&usbh2_pdata); #ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD eukrea_mbimxsd25_baseboard_init(); diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index 59716fa..40a3666 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -34,12 +34,9 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <mach/common.h> -#include <mach/mmc.h> #include <mach/iomux.h> -#include <mach/mxc_ehci.h> #include "devices-imx27.h" -#include "devices.h" #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) #define SDHC1_IRQ IRQ_GPIOB(25) @@ -156,7 +153,7 @@ static void visstrim_m10_sdhc1_exit(struct device *dev, void *data) free_irq(SDHC1_IRQ, data); } -static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = { +static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = { .init = visstrim_m10_sdhc1_init, .exit = visstrim_m10_sdhc1_exit, }; @@ -216,7 +213,8 @@ static int otg_phy_init(struct platform_device *pdev) return 0; } -static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = { +static const struct mxc_usbh_platform_data +visstrim_m10_usbotg_pdata __initconst = { .init = otg_phy_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED, @@ -237,8 +235,8 @@ static void __init visstrim_m10_board_init(void) ARRAY_SIZE(visstrim_m10_i2c_devices)); imx27_add_imx_i2c(0, &visstrim_m10_i2c_data); imx27_add_imx_i2c(1, &visstrim_m10_i2c_data); - mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata); - mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata); + imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata); + imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata); imx27_add_fec(NULL); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c index bbdbc75..3a1202e 100644 --- a/arch/arm/mach-imx/mach-imx27lite.c +++ b/arch/arm/mach-imx/mach-imx27lite.c @@ -25,7 +25,6 @@ #include <mach/iomux-mx27.h> #include "devices-imx27.h" -#include "devices.h" static const int mx27lite_pins[] __initconst = { /* UART1 */ diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 6187ce9..1f446e5 100644 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c @@ -30,7 +30,6 @@ #include <mach/irqs.h> #include "devices-imx1.h" -#include "devices.h" static const int mx1ads_pins[] __initconst = { /* UART1 */ diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index e1282e9..0a37257 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -24,13 +24,10 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/mach/map.h> -#include <mach/imxfb.h> #include <mach/iomux-mx21.h> #include <mach/mxc_nand.h> -#include <mach/mmc.h> #include "devices-imx21.h" -#include "devices.h" /* * Memory-mapped I/O on MX21ADS base board @@ -213,7 +210,7 @@ static struct imx_fb_videomode mx21ads_modes[] = { }, }; -static struct imx_fb_platform_data mx21ads_fb_data = { +static const struct imx_fb_platform_data mx21ads_fb_data __initconst = { .mode = mx21ads_modes, .num_modes = ARRAY_SIZE(mx21ads_modes), @@ -233,15 +230,8 @@ static int mx21ads_sdhc_get_ro(struct device *dev) static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq, void *data) { - int ret; - - ret = request_irq(IRQ_GPIOD(25), detect_irq, + return request_irq(IRQ_GPIOD(25), detect_irq, IRQF_TRIGGER_FALLING, "mmc-detect", data); - if (ret) - goto out; - return 0; -out: - return ret; } static void mx21ads_sdhc_exit(struct device *dev, void *data) @@ -249,7 +239,7 @@ static void mx21ads_sdhc_exit(struct device *dev, void *data) free_irq(IRQ_GPIOD(25), data); } -static struct imxmmc_platform_data mx21ads_sdhc_pdata = { +static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = { .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */ .get_ro = mx21ads_sdhc_get_ro, .init = mx21ads_sdhc_init, @@ -296,8 +286,8 @@ static void __init mx21ads_board_init(void) imx21_add_imx_uart0(&uart_pdata_rts); imx21_add_imx_uart2(&uart_pdata_norts); imx21_add_imx_uart3(&uart_pdata_rts); - mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); - mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); + imx21_add_imx_fb(&mx21ads_fb_data); + imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata); imx21_add_mxc_nand(&mx21ads_nand_board_info); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); diff --git a/arch/arm/mach-mx25/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index f8be1eb..8b8e75b 100644 --- a/arch/arm/mach-mx25/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c @@ -39,17 +39,15 @@ #include <asm/mach/map.h> #include <mach/common.h> #include <mach/mx25.h> -#include <mach/imxfb.h> #include <mach/iomux-mx25.h> #include "devices-imx25.h" -#include "devices.h" static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct pad_desc mx25pdk_pads[] = { +static iomux_v3_cfg_t mx25pdk_pads[] = { MX25_PAD_FEC_MDC__FEC_MDC, MX25_PAD_FEC_MDIO__FEC_MDIO, MX25_PAD_FEC_TDATA0__FEC_TDATA0, @@ -107,7 +105,7 @@ static struct pad_desc mx25pdk_pads[] = { }; static const struct fec_platform_data mx25_fec_pdata __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, + .phy = PHY_INTERFACE_MODE_RMII, }; #define FEC_ENABLE_GPIO 35 @@ -154,7 +152,7 @@ static struct imx_fb_videomode mx25pdk_modes[] = { }, }; -static struct imx_fb_platform_data mx25pdk_fb_pdata = { +static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = { .mode = mx25pdk_modes, .num_modes = ARRAY_SIZE(mx25pdk_modes), .pwmr = 0x00A903FF, @@ -181,7 +179,7 @@ static const uint32_t mx25pdk_keymap[] = { KEY(3, 3, KEY_POWER), }; -static struct matrix_keymap_data mx25pdk_keymap_data = { +static const struct matrix_keymap_data mx25pdk_keymap_data __initdata = { .keymap = mx25pdk_keymap, .keymap_size = ARRAY_SIZE(mx25pdk_keymap), }; @@ -192,17 +190,17 @@ static void __init mx25pdk_init(void) ARRAY_SIZE(mx25pdk_pads)); imx25_add_imx_uart0(&uart_pdata); - mxc_register_device(&mxc_usbh2, NULL); + imx25_add_mxc_ehci_hs(NULL); imx25_add_mxc_nand(&mx25pdk_nand_board_info); - mxc_register_device(&mx25_rtc_device, NULL); - mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata); - mxc_register_device(&mxc_wdt, NULL); + imx25_add_imxdi_rtc(NULL); + imx25_add_imx_fb(&mx25pdk_fb_pdata); + imx25_add_imx2_wdt(NULL); mx25pdk_fec_reset(); imx25_add_fec(&mx25_fec_pdata); - mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data); + imx25_add_imx_keypad(&mx25pdk_keymap_data); - imx25_add_esdhc(0, NULL); + imx25_add_sdhci_esdhc_imx(0, NULL); } static void __init mx25pdk_timer_init(void) diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 84a5ba03..3614e33 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -22,7 +22,6 @@ #include <linux/platform_device.h> #include <linux/gpio.h> -#include <linux/input/matrix_keypad.h> #include <linux/irq.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -30,10 +29,8 @@ #include <mach/hardware.h> #include <mach/common.h> #include <mach/iomux-mx27.h> -#include <mach/mmc.h> #include "devices-imx27.h" -#include "devices.h" #define SD1_EN_GPIO (GPIO_PORTB + 25) @@ -92,7 +89,7 @@ static const uint32_t mx27_3ds_keymap[] = { KEY(2, 3, KEY_F10), }; -static struct matrix_keymap_data mx27_3ds_keymap_data = { +static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = { .keymap = mx27_3ds_keymap, .keymap_size = ARRAY_SIZE(mx27_3ds_keymap), }; @@ -109,7 +106,7 @@ static void mx27_3ds_sdhc1_exit(struct device *dev, void *data) free_irq(IRQ_GPIOB(26), data); } -static struct imxmmc_platform_data sdhc1_pdata = { +static const struct imxmmc_platform_data sdhc1_pdata __initconst = { .init = mx27_3ds_sdhc1_init, .exit = mx27_3ds_sdhc1_exit, }; @@ -128,8 +125,8 @@ static void __init mx27pdk_init(void) mx27_3ds_sdhc1_enable_level_translator(); imx27_add_imx_uart0(&uart_pdata); imx27_add_fec(NULL); - mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data); - mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); + imx27_add_imx_keypad(&mx27_3ds_keymap_data); + imx27_add_mxc_mmc(0, &sdhc1_pdata); } static void __init mx27pdk_timer_init(void) diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index a1e4bc5..b832f96 100644 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c @@ -30,11 +30,8 @@ #include <mach/gpio.h> #include <mach/iomux-mx27.h> #include <mach/mxc_nand.h> -#include <mach/imxfb.h> -#include <mach/mmc.h> #include "devices-imx27.h" -#include "devices.h" /* * Base address of PBC controller, CS4 @@ -228,7 +225,7 @@ static struct imx_fb_videomode mx27ads_modes[] = { }, }; -static struct imx_fb_platform_data mx27ads_fb_data = { +static const struct imx_fb_platform_data mx27ads_fb_data __initconst = { .mode = mx27ads_modes, .num_modes = ARRAY_SIZE(mx27ads_modes), @@ -272,19 +269,18 @@ static void mx27ads_sdhc2_exit(struct device *dev, void *data) free_irq(IRQ_GPIOB(7), data); } -static struct imxmmc_platform_data sdhc1_pdata = { +static const struct imxmmc_platform_data sdhc1_pdata __initconst = { .init = mx27ads_sdhc1_init, .exit = mx27ads_sdhc1_exit, }; -static struct imxmmc_platform_data sdhc2_pdata = { +static const struct imxmmc_platform_data sdhc2_pdata __initconst = { .init = mx27ads_sdhc2_init, .exit = mx27ads_sdhc2_exit, }; static struct platform_device *platform_devices[] __initdata = { &mx27ads_nor_mtd_device, - &mxc_w1_master_device, }; static const struct imxuart_platform_data uart_pdata __initconst = { @@ -308,12 +304,13 @@ static void __init mx27ads_board_init(void) i2c_register_board_info(1, mx27ads_i2c_devices, ARRAY_SIZE(mx27ads_i2c_devices)); imx27_add_imx_i2c(1, &mx27ads_i2c1_data); - mxc_register_device(&mxc_fb_device, &mx27ads_fb_data); - mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); - mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata); + imx27_add_imx_fb(&mx27ads_fb_data); + imx27_add_mxc_mmc(0, &sdhc1_pdata); + imx27_add_mxc_mmc(1, &sdhc2_pdata); imx27_add_fec(NULL); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + imx27_add_mxc_w1(NULL); } static void __init mx27ads_timer_init(void) diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c index 38d3a4a..4ce71b0 100644 --- a/arch/arm/mach-imx/mach-mxt_td60.c +++ b/arch/arm/mach-imx/mach-mxt_td60.c @@ -31,11 +31,8 @@ #include <mach/iomux-mx27.h> #include <mach/mxc_nand.h> #include <linux/i2c/pca953x.h> -#include <mach/imxfb.h> -#include <mach/mmc.h> #include "devices-imx27.h" -#include "devices.h" static const int mxt_td60_pins[] __initconst = { /* UART0 */ @@ -196,7 +193,7 @@ static struct imx_fb_videomode mxt_td60_modes[] = { }, }; -static struct imx_fb_platform_data mxt_td60_fb_data = { +static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = { .mode = mxt_td60_modes, .num_modes = ARRAY_SIZE(mxt_td60_modes), @@ -226,7 +223,7 @@ static void mxt_td60_sdhc1_exit(struct device *dev, void *data) free_irq(IRQ_GPIOF(8), data); } -static struct imxmmc_platform_data sdhc1_pdata = { +static const struct imxmmc_platform_data sdhc1_pdata __initconst = { .init = mxt_td60_sdhc1_init, .exit = mxt_td60_sdhc1_exit, }; @@ -253,8 +250,8 @@ static void __init mxt_td60_board_init(void) imx27_add_imx_i2c(0, &mxt_td60_i2c0_data); imx27_add_imx_i2c(1, &mxt_td60_i2c1_data); - mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data); - mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); + imx27_add_imx_fb(&mxt_td60_fb_data); + imx27_add_mxc_mmc(0, &sdhc1_pdata); imx27_add_fec(NULL); } diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 8c720d4..cccc0a0 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -29,7 +29,6 @@ #include <linux/gpio.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> -#include <linux/fsl_devices.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -40,13 +39,9 @@ #include <mach/audmux.h> #include <mach/mxc_nand.h> #include <mach/irqs.h> -#include <mach/mmc.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> -#include <mach/imxfb.h> #include "devices-imx27.h" -#include "devices.h" #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) @@ -171,11 +166,6 @@ pca100_nand_board_info __initconst = { .hw_ecc = 1, }; -static struct platform_device *platform_devices[] __initdata = { - &mxc_w1_master_device, - &mxc_wdt, -}; - static const struct imxi2c_platform_data pca100_i2c1_data __initconst = { .bitrate = 100000, }; @@ -274,7 +264,7 @@ static void pca100_sdhc2_exit(struct device *dev, void *data) free_irq(IRQ_GPIOC(29), data); } -static struct imxmmc_platform_data sdhc_pdata = { +static const struct imxmmc_platform_data sdhc_pdata __initconst = { .init = pca100_sdhc2_init, .exit = pca100_sdhc2_exit, }; @@ -286,7 +276,7 @@ static int otg_phy_init(struct platform_device *pdev) return 0; } -static struct mxc_usbh_platform_data otg_pdata = { +static struct mxc_usbh_platform_data otg_pdata __initdata = { .init = otg_phy_init, .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, @@ -298,14 +288,14 @@ static int usbh2_phy_init(struct platform_device *pdev) return 0; } -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_phy_init, .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; #endif -static struct fsl_usb2_platform_data otg_device_pdata = { +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; @@ -355,7 +345,7 @@ static struct imx_fb_videomode pca100_fb_modes[] = { }, }; -static struct imx_fb_platform_data pca100_fb_data = { +static const struct imx_fb_platform_data pca100_fb_data __initconst = { .mode = pca100_fb_modes, .num_modes = ARRAY_SIZE(pca100_fb_modes), @@ -389,7 +379,7 @@ static void __init pca100_init(void) imx27_add_imx_uart0(&uart_pdata); - mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); + imx27_add_mxc_mmc(1, &sdhc_pdata); imx27_add_mxc_nand(&pca100_nand_board_info); @@ -417,23 +407,24 @@ static void __init pca100_init(void) otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_otg_host, &otg_pdata); + imx27_add_mxc_ehci_otg(&otg_pdata); } usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx27_add_mxc_ehci_hs(2, &usbh2_pdata); #endif if (!otg_mode_host) { gpio_set_value(OTG_PHY_CS_GPIO, 0); - mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + imx27_add_fsl_usb2_udc(&otg_device_pdata); } - mxc_register_device(&mxc_fb_device, &pca100_fb_data); + imx27_add_imx_fb(&pca100_fb_data); imx27_add_fec(NULL); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + imx27_add_imx2_wdt(NULL); + imx27_add_mxc_w1(NULL); } static void __init pca100_timer_init(void) diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 49a97ce..f667a26 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -37,11 +37,9 @@ #include <mach/hardware.h> #include <mach/iomux-mx27.h> #include <mach/mxc_nand.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx27.h" -#include "devices.h" static const int pcm038_pins[] __initconst = { /* UART1 */ @@ -172,9 +170,7 @@ pcm038_nand_board_info __initconst = { static struct platform_device *platform_devices[] __initdata = { &pcm038_nor_mtd_device, - &mxc_w1_master_device, &pcm038_sram_mtd_device, - &mxc_wdt, }; /* On pcm038 there's a sram attached to CS1, we enable the chipselect here and @@ -214,7 +210,7 @@ static const struct spi_imx_master pcm038_spi0_data __initconst = { static struct regulator_consumer_supply sdhc1_consumers[] = { { - .dev = &mxc_sdhc_device1.dev, + .dev_name = "mxc-mmc.1", .supply = "sdhc_vcc", }, }; @@ -285,7 +281,7 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = { } }; -static struct mxc_usbh_platform_data usbh2_pdata = { +static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, }; @@ -322,10 +318,12 @@ static void __init pcm038_init(void) spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx27_add_mxc_ehci_hs(2, &usbh2_pdata); imx27_add_fec(NULL); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + imx27_add_imx2_wdt(NULL); + imx27_add_mxc_w1(NULL); #ifdef CONFIG_MACH_PCM970_BASEBOARD pcm970_baseboard_init(); diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c index 1fbdd3f..eae878f 100644 --- a/arch/arm/mach-imx/mach-scb9328.c +++ b/arch/arm/mach-imx/mach-scb9328.c @@ -25,7 +25,6 @@ #include <mach/iomux-mx1.h> #include "devices-imx1.h" -#include "devices.h" /* * This scb9328 has a 32MiB flash diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c index 9be92b9..729ae09 100644 --- a/arch/arm/mach-imx/mm-imx1.c +++ b/arch/arm/mach-imx/mm-imx1.c @@ -25,12 +25,7 @@ #include <mach/hardware.h> static struct map_desc imx_io_desc[] __initdata = { - { - .virtual = MX1_IO_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX1_IO_BASE_ADDR), - .length = MX1_IO_SIZE, - .type = MT_DEVICE - } + imx_map_entry(MX1, IO, MT_DEVICE), }; void __init mx1_map_io(void) diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index 12faeeaa..e728af8 100644 --- a/arch/arm/mach-imx/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c @@ -35,33 +35,18 @@ static struct map_desc imx21_io_desc[] __initdata = { * - ROM Patch * - and some reserved space */ - { - .virtual = MX21_AIPI_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR), - .length = MX21_AIPI_SIZE, - .type = MT_DEVICE - }, + imx_map_entry(MX21, AIPI, MT_DEVICE), /* * this fixed mapping covers: * - CSI * - ATA */ - { - .virtual = MX21_SAHB1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR), - .length = MX21_SAHB1_SIZE, - .type = MT_DEVICE - }, + imx_map_entry(MX21, SAHB1, MT_DEVICE), /* * this fixed mapping covers: * - EMI */ - { - .virtual = MX21_X_MEMC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR), - .length = MX21_X_MEMC_SIZE, - .type = MT_DEVICE - }, + imx_map_entry(MX21, X_MEMC, MT_DEVICE), }; /* diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-imx/mm-imx25.c index bb67711..2edec6c 100644 --- a/arch/arm/mach-mx25/mm.c +++ b/arch/arm/mach-imx/mm-imx25.c @@ -30,25 +30,12 @@ /* * This table defines static virtual address mappings for I/O regions. - * These are the mappings common across all MX3 boards. + * These are the mappings common across all MX25 boards. */ -static struct map_desc mxc_io_desc[] __initdata = { - { - .virtual = MX25_AVIC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX25_AVIC_BASE_ADDR), - .length = MX25_AVIC_SIZE, - .type = MT_DEVICE_NONSHARED - }, { - .virtual = MX25_AIPS1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX25_AIPS1_BASE_ADDR), - .length = MX25_AIPS1_SIZE, - .type = MT_DEVICE_NONSHARED - }, { - .virtual = MX25_AIPS2_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX25_AIPS2_BASE_ADDR), - .length = MX25_AIPS2_SIZE, - .type = MT_DEVICE_NONSHARED - }, +static struct map_desc mx25_io_desc[] __initdata = { + imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED), + imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED), + imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED), }; /* @@ -62,14 +49,14 @@ void __init mx25_map_io(void) mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); + iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc)); } int imx25_register_gpios(void); void __init mx25_init_irq(void) { - mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT); + mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR)); imx25_register_gpios(); } diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index a246229..374e48b 100644 --- a/arch/arm/mach-imx/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c @@ -35,33 +35,18 @@ static struct map_desc imx27_io_desc[] __initdata = { * - ROM Patch * - and some reserved space */ - { - .virtual = MX27_AIPI_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR), - .length = MX27_AIPI_SIZE, - .type = MT_DEVICE - }, + imx_map_entry(MX27, AIPI, MT_DEVICE), /* * this fixed mapping covers: * - CSI * - ATA */ - { - .virtual = MX27_SAHB1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR), - .length = MX27_SAHB1_SIZE, - .type = MT_DEVICE - }, + imx_map_entry(MX27, SAHB1, MT_DEVICE), /* * this fixed mapping covers: * - EMI */ - { - .virtual = MX27_X_MEMC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR), - .length = MX27_X_MEMC_SIZE, - .type = MT_DEVICE - }, + imx_map_entry(MX27, X_MEMC, MT_DEVICE), }; /* diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c index 9110d9c..99afbc3 100644 --- a/arch/arm/mach-imx/pcm970-baseboard.c +++ b/arch/arm/mach-imx/pcm970-baseboard.c @@ -25,11 +25,9 @@ #include <mach/common.h> #include <mach/iomux-mx27.h> -#include <mach/imxfb.h> #include <mach/hardware.h> -#include <mach/mmc.h> -#include "devices.h" +#include "devices-imx27.h" static const int pcm970_pins[] __initconst = { /* SDHC */ @@ -119,7 +117,7 @@ static void pcm970_sdhc2_exit(struct device *dev, void *data) gpio_free(GPIO_PORTC + 28); } -static struct imxmmc_platform_data sdhc_pdata = { +static const struct imxmmc_platform_data sdhc_pdata __initconst = { .get_ro = pcm970_sdhc2_get_ro, .init = pcm970_sdhc2_init, .exit = pcm970_sdhc2_exit, @@ -179,7 +177,7 @@ static struct imx_fb_videomode pcm970_modes[] = { }, }; -static struct imx_fb_platform_data pcm038_fb_data = { +static const struct imx_fb_platform_data pcm038_fb_data __initconst = { .mode = pcm970_modes, .num_modes = ARRAY_SIZE(pcm970_modes), @@ -226,8 +224,8 @@ void __init pcm970_baseboard_init(void) mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins), "PCM970"); - mxc_register_device(&mxc_fb_device, &pcm038_fb_data); + imx27_add_imx_fb(&pcm038_fb_data); mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN); - mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); + imx27_add_mxc_mmc(1, &sdhc_pdata); platform_device_register(&pcm970_sja1000); } diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c index afc17ce..6bf81ce 100644 --- a/arch/arm/mach-imx/pm-imx27.c +++ b/arch/arm/mach-imx/pm-imx27.c @@ -39,6 +39,9 @@ static struct platform_suspend_ops mx27_suspend_ops = { static int __init mx27_pm_init(void) { + if (!cpu_is_mx27()) + return 0; + suspend_set_ops(&mx27_suspend_ops); return 0; } diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig deleted file mode 100644 index 38ca09a..0000000 --- a/arch/arm/mach-mx25/Kconfig +++ /dev/null @@ -1,34 +0,0 @@ -if ARCH_MX25 - -comment "MX25 platforms:" - -config MACH_MX25_3DS - bool "Support MX25PDK (3DS) Platform" - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_ESDHC - -config MACH_EUKREA_CPUIMX25 - bool "Support Eukrea CPUIMX25 Platform" - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_ESDHC - select MXC_ULPI if USB_ULPI - -choice - prompt "Baseboard" - depends on MACH_EUKREA_CPUIMX25 - default MACH_EUKREA_MBIMXSD25_BASEBOARD - -config MACH_EUKREA_MBIMXSD25_BASEBOARD - bool "Eukrea MBIMXSD development board" - select IMX_HAVE_PLATFORM_IMX_SSI - help - This adds board specific devices that can be found on Eukrea's - MBIMXSD evaluation board. - -endchoice - -endif diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile deleted file mode 100644 index d9e46ce..0000000 --- a/arch/arm/mach-mx25/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -obj-y := mm.o devices.o -obj-$(CONFIG_ARCH_MX25) += clock.o -obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o -obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-cpuimx25.o -obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd-baseboard.o diff --git a/arch/arm/mach-mx25/Makefile.boot b/arch/arm/mach-mx25/Makefile.boot deleted file mode 100644 index e1dd366..0000000 --- a/arch/arm/mach-mx25/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x80008000 -params_phys-y := 0x80000100 -initrd_phys-y := 0x80800000 diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c deleted file mode 100644 index 1d0eb3e..0000000 --- a/arch/arm/mach-mx25/devices.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/gpio.h> -#include <mach/mx25.h> -#include <mach/irqs.h> - -static u64 otg_dmamask = DMA_BIT_MASK(32); - -static struct resource mxc_otg_resources[] = { - { - .start = MX25_OTG_BASE_ADDR, - .end = MX25_OTG_BASE_ADDR + 0x1ff, - .flags = IORESOURCE_MEM, - }, { - .start = 37, - .end = 37, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_otg = { - .name = "mxc-ehci", - .id = 0, - .dev = { - .coherent_dma_mask = 0xffffffff, - .dma_mask = &otg_dmamask, - }, - .resource = mxc_otg_resources, - .num_resources = ARRAY_SIZE(mxc_otg_resources), -}; - -/* OTG gadget device */ -struct platform_device otg_udc_device = { - .name = "fsl-usb2-udc", - .id = -1, - .dev = { - .dma_mask = &otg_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .resource = mxc_otg_resources, - .num_resources = ARRAY_SIZE(mxc_otg_resources), -}; - -static u64 usbh2_dmamask = DMA_BIT_MASK(32); - -static struct resource mxc_usbh2_resources[] = { - { - .start = MX25_OTG_BASE_ADDR + 0x400, - .end = MX25_OTG_BASE_ADDR + 0x5ff, - .flags = IORESOURCE_MEM, - }, { - .start = 35, - .end = 35, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_usbh2 = { - .name = "mxc-ehci", - .id = 1, - .dev = { - .coherent_dma_mask = 0xffffffff, - .dma_mask = &usbh2_dmamask, - }, - .resource = mxc_usbh2_resources, - .num_resources = ARRAY_SIZE(mxc_usbh2_resources), -}; - -static struct resource mxc_pwm_resources0[] = { - { - .start = 0x53fe0000, - .end = 0x53fe3fff, - .flags = IORESOURCE_MEM, - }, { - .start = 26, - .end = 26, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_pwm_device0 = { - .name = "mxc_pwm", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_pwm_resources0), - .resource = mxc_pwm_resources0, -}; - -static struct resource mxc_pwm_resources1[] = { - { - .start = 0x53fa0000, - .end = 0x53fa3fff, - .flags = IORESOURCE_MEM, - }, { - .start = 36, - .end = 36, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_pwm_device1 = { - .name = "mxc_pwm", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_pwm_resources1), - .resource = mxc_pwm_resources1, -}; - -static struct resource mxc_pwm_resources2[] = { - { - .start = 0x53fa8000, - .end = 0x53fabfff, - .flags = IORESOURCE_MEM, - }, { - .start = 41, - .end = 41, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_pwm_device2 = { - .name = "mxc_pwm", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_pwm_resources2), - .resource = mxc_pwm_resources2, -}; - -static struct resource mxc_keypad_resources[] = { - { - .start = 0x43fa8000, - .end = 0x43fabfff, - .flags = IORESOURCE_MEM, - }, { - .start = 24, - .end = 24, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_keypad_device = { - .name = "mxc-keypad", - .id = -1, - .num_resources = ARRAY_SIZE(mxc_keypad_resources), - .resource = mxc_keypad_resources, -}; - -static struct resource mxc_pwm_resources3[] = { - { - .start = 0x53fc8000, - .end = 0x53fcbfff, - .flags = IORESOURCE_MEM, - }, { - .start = 42, - .end = 42, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_pwm_device3 = { - .name = "mxc_pwm", - .id = 3, - .num_resources = ARRAY_SIZE(mxc_pwm_resources3), - .resource = mxc_pwm_resources3, -}; - -static struct mxc_gpio_port imx_gpio_ports[] = { - { - .chip.label = "gpio-0", - .base = (void __iomem *)MX25_GPIO1_BASE_ADDR_VIRT, - .irq = 52, - .virtual_irq_start = MXC_GPIO_IRQ_START, - }, { - .chip.label = "gpio-1", - .base = (void __iomem *)MX25_GPIO2_BASE_ADDR_VIRT, - .irq = 51, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, { - .chip.label = "gpio-2", - .base = (void __iomem *)MX25_GPIO3_BASE_ADDR_VIRT, - .irq = 16, - .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - }, { - .chip.label = "gpio-3", - .base = (void __iomem *)MX25_GPIO4_BASE_ADDR_VIRT, - .irq = 23, - .virtual_irq_start = MXC_GPIO_IRQ_START + 96, - } -}; - -int __init imx25_register_gpios(void) -{ - return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); -} - -static struct resource mx25_rtc_resources[] = { - { - .start = MX25_DRYICE_BASE_ADDR, - .end = MX25_DRYICE_BASE_ADDR + 0x40, - .flags = IORESOURCE_MEM, - }, - { - .start = MX25_INT_DRYICE, - .flags = IORESOURCE_IRQ - }, -}; - -struct platform_device mx25_rtc_device = { - .name = "imxdi_rtc", - .id = 0, - .num_resources = ARRAY_SIZE(mx25_rtc_resources), - .resource = mx25_rtc_resources, -}; - -static struct resource mx25_fb_resources[] = { - { - .start = MX25_LCDC_BASE_ADDR, - .end = MX25_LCDC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - { - .start = MX25_INT_LCDC, - .end = MX25_INT_LCDC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mx25_fb_device = { - .name = "imx-fb", - .id = 0, - .resource = mx25_fb_resources, - .num_resources = ARRAY_SIZE(mx25_fb_resources), - .dev = { - .coherent_dma_mask = 0xFFFFFFFF, - }, -}; - -static struct resource mxc_wdt_resources[] = { - { - .start = MX25_WDOG_BASE_ADDR, - .end = MX25_WDOG_BASE_ADDR + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_wdt = { - .name = "imx2-wdt", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_wdt_resources), - .resource = mxc_wdt_resources, -}; - -static struct resource mx25_kpp_resources[] = { - { - .start = MX25_KPP_BASE_ADDR, - .end = MX25_KPP_BASE_ADDR + 0xf, - .flags = IORESOURCE_MEM, - }, - { - .start = MX25_INT_KPP, - .end = MX25_INT_KPP, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mx25_kpp_device = { - .name = "imx-keypad", - .id = -1, - .num_resources = ARRAY_SIZE(mx25_kpp_resources), - .resource = mx25_kpp_resources, -}; - -static struct resource mx25_csi_resources[] = { - { - .start = MX25_CSI_BASE_ADDR, - .end = MX25_CSI_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - { - .start = MX25_INT_CSI, - .flags = IORESOURCE_IRQ - }, -}; - -struct platform_device mx25_csi_device = { - .name = "mx2-camera", - .id = 0, - .num_resources = ARRAY_SIZE(mx25_csi_resources), - .resource = mx25_csi_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h deleted file mode 100644 index 7b70a43..0000000 --- a/arch/arm/mach-mx25/devices.h +++ /dev/null @@ -1,13 +0,0 @@ -extern struct platform_device mxc_otg; -extern struct platform_device otg_udc_device; -extern struct platform_device mxc_usbh2; -extern struct platform_device mxc_pwm_device0; -extern struct platform_device mxc_pwm_device1; -extern struct platform_device mxc_pwm_device2; -extern struct platform_device mxc_pwm_device3; -extern struct platform_device mxc_keypad_device; -extern struct platform_device mx25_rtc_device; -extern struct platform_device mx25_fb_device; -extern struct platform_device mxc_wdt; -extern struct platform_device mx25_kpp_device; -extern struct platform_device mx25_csi_device; diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 5000ac1..165e722 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -1,21 +1,35 @@ if ARCH_MX3 +# ARCH_MX31 and ARCH_MX35 are left for compatibility +# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2. +# To easily distinguish good and reviewed from unreviewed usages new (and IMHO +# more sensible) names are used: SOC_IMX31 and SOC_IMX35 config ARCH_MX31 - select ARCH_HAS_RNGA - select ARCH_MXC_AUDMUX_V2 bool config ARCH_MX35 bool + +config SOC_IMX31 + bool + select IMX_HAVE_PLATFORM_MXC_RNGA + select ARCH_MXC_AUDMUX_V2 + select ARCH_MX31 + select MXC_AVIC + +config SOC_IMX35 + bool select ARCH_MXC_IOMUX_V3 select ARCH_MXC_AUDMUX_V2 select HAVE_EPIT + select ARCH_MX35 + select MXC_AVIC comment "MX3 platforms:" config MACH_MX31ADS bool "Support MX31ADS platforms" - select ARCH_MX31 + select SOC_IMX31 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART @@ -37,10 +51,15 @@ config MACH_MX31ADS_WM1133_EV1 config MACH_PCM037 bool "Support Phytec pcm037 (i.MX31) platforms" - select ARCH_MX31 + select SOC_IMX31 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_MXC_W1 select MXC_ULPI if USB_ULPI help Include support for Phytec pcm037 platform. This includes @@ -57,9 +76,12 @@ config MACH_PCM037_EET config MACH_MX31LITE bool "Support MX31 LITEKIT (LogicPD)" - select ARCH_MX31 + select SOC_IMX31 select MXC_ULPI if USB_ULPI + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SPI_IMX help @@ -68,8 +90,10 @@ config MACH_MX31LITE config MACH_MX31_3DS bool "Support MX31PDK (3DS)" - select ARCH_MX31 + select SOC_IMX31 select MXC_DEBUG_BOARD + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SPI_IMX @@ -88,9 +112,12 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT config MACH_MX31MOBOARD bool "Support mx31moboard platforms (EPFL Mobots group)" - select ARCH_MX31 + select SOC_IMX31 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help @@ -99,8 +126,10 @@ config MACH_MX31MOBOARD config MACH_MX31LILLY bool "Support MX31 LILLY-1131 platforms (INCO startec)" - select ARCH_MX31 + select SOC_IMX31 select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help @@ -109,7 +138,7 @@ config MACH_MX31LILLY config MACH_QONG bool "Support Dave/DENX QongEVB-LITE platform" - select ARCH_MX31 + select SOC_IMX31 select IMX_HAVE_PLATFORM_IMX_UART help Include support for Dave/DENX QongEVB-LITE platform. This includes @@ -117,13 +146,16 @@ config MACH_QONG config MACH_PCM043 bool "Support Phytec pcm043 (i.MX35) platforms" - select ARCH_MX35 + select SOC_IMX35 + select IMX_HAVE_PLATFORM_FLEXCAN + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_ESDHC + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select MXC_ULPI if USB_ULPI help Include support for Phytec pcm043 platform. This includes @@ -131,9 +163,11 @@ config MACH_PCM043 config MACH_ARMADILLO5X0 bool "Support Atmark Armadillo-500 Development Base Board" - select ARCH_MX31 + select SOC_IMX31 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND select MXC_ULPI if USB_ULPI help @@ -142,19 +176,21 @@ config MACH_ARMADILLO5X0 config MACH_MX35_3DS bool "Support MX35PDK platform" - select ARCH_MX35 + select SOC_IMX35 select MXC_DEBUG_BOARD + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_ESDHC - default n + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX help Include support for MX35PDK platform. This includes specific configurations for the board and its peripherals. config MACH_KZM_ARM11_01 bool "Support KZM-ARM11-01(Kyoto Microcomputer)" - select ARCH_MX31 + select SOC_IMX31 select IMX_HAVE_PLATFORM_IMX_UART help Include support for KZM-ARM11-01. This includes specific @@ -162,12 +198,15 @@ config MACH_KZM_ARM11_01 config MACH_EUKREA_CPUIMX35 bool "Support Eukrea CPUIMX35 Platform" - select ARCH_MX35 - select IMX_HAVE_PLATFORM_IMX_UART + select SOC_IMX35 + select IMX_HAVE_PLATFORM_FLEXCAN + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_ESDHC + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select MXC_ULPI if USB_ULPI help Include support for Eukrea CPUIMX35 platform. This includes diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 8a182d0a..8db1329 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -5,17 +5,14 @@ # Object file lists. obj-y := mm.o devices.o cpu.o -CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS -CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS -obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o -obj-$(CONFIG_ARCH_MX35) += clock-imx35.o +obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o +obj-$(CONFIG_SOC_IMX35) += clock-imx35.o obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o -CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ mx31moboard-marxbot.o mx31moboard-smartbot.o obj-$(CONFIG_MACH_QONG) += mach-qong.o diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c index 109e98f..7cf6d29 100644 --- a/arch/arm/mach-mx3/clock-imx31.c +++ b/arch/arm/mach-mx3/clock-imx31.c @@ -615,7 +615,7 @@ int __init mx31_clocks_init(unsigned long fref) mx31_read_cpu_rev(); - if (mx31_revision() >= MX31_CHIP_REV_2_0) { + if (mx31_revision() >= IMX_CHIP_REVISION_2_0) { reg = __raw_readl(MXC_CCM_PMCR1); /* No PLL restart on DVFS switch; enable auto EMI handshake */ reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c index d00a754..d1d3395 100644 --- a/arch/arm/mach-mx3/cpu.c +++ b/arch/arm/mach-mx3/cpu.c @@ -25,15 +25,15 @@ struct mx3_cpu_type { }; static struct mx3_cpu_type mx31_cpu_type[] __initdata = { - { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = MX3x_CHIP_REV_1_0 }, - { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 }, - { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 }, - { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 }, - { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 }, - { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 }, - { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 }, - { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 }, - { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 }, + { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 }, + { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, + { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, + { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 }, + { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 }, + { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 }, + { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 }, + { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 }, + { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 }, }; void __init mx31_read_cpu_rev(void) @@ -53,6 +53,8 @@ void __init mx31_read_cpu_rev(void) return; } + mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN; + printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); } @@ -62,22 +64,25 @@ EXPORT_SYMBOL(mx35_cpu_rev); void __init mx35_read_cpu_rev(void) { u32 rev; - char *srev = "unknown"; + char *srev; rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); switch (rev) { case 0x00: - mx35_cpu_rev = MX3x_CHIP_REV_1_0; + mx35_cpu_rev = IMX_CHIP_REVISION_1_0; srev = "1.0"; break; case 0x10: - mx35_cpu_rev = MX3x_CHIP_REV_2_0; + mx35_cpu_rev = IMX_CHIP_REVISION_2_0; srev = "2.0"; break; case 0x11: - mx35_cpu_rev = MX3x_CHIP_REV_2_1; + mx35_cpu_rev = IMX_CHIP_REVISION_2_1; srev = "2.1"; break; + default: + mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN; + srev = "unknown"; } printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev); diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h index de95985..40f4e84 100644 --- a/arch/arm/mach-mx3/devices-imx31.h +++ b/arch/arm/mach-mx3/devices-imx31.h @@ -9,6 +9,14 @@ #include <mach/mx31.h> #include <mach/devices-common.h> +extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst; +#define imx31_add_fsl_usb2_udc(pdata) \ + imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata) + +extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst; +#define imx31_add_imx2_wdt(pdata) \ + imx_add_imx2_wdt(&imx31_imx2_wdt_data) + extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst; #define imx31_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata) @@ -16,6 +24,10 @@ extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst; #define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata) #define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata) +extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst; +#define imx31_add_imx_keypad(pdata) \ + imx_add_imx_keypad(&imx31_imx_keypad_data, pdata) + extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst; #define imx31_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata) @@ -29,10 +41,25 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst; #define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) #define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) +extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst; +#define imx31_add_mxc_ehci_otg(pdata) \ + imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata) +extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst; +#define imx31_add_mxc_ehci_hs(id, pdata) \ + imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata) + +extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst; +#define imx31_add_mxc_mmc(id, pdata) \ + imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata) + extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst; #define imx31_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) +extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst; +#define imx31_add_mxc_w1(pdata) \ + imx_add_mxc_w1(&imx31_mxc_w1_data) + extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst; #define imx31_add_cspi(id, pdata) \ imx_add_spi_imx(&imx31_cspi_data[id], pdata) diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h index 5eb917b..677b18a 100644 --- a/arch/arm/mach-mx3/devices-imx35.h +++ b/arch/arm/mach-mx3/devices-imx35.h @@ -13,10 +13,19 @@ extern const struct imx_fec_data imx35_fec_data __initconst; #define imx35_add_fec(pdata) \ imx_add_fec(&imx35_fec_data, pdata) -#define imx35_add_flexcan0(pdata) \ - imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata) -#define imx35_add_flexcan1(pdata) \ - imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata) +extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst; +#define imx35_add_fsl_usb2_udc(pdata) \ + imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata) + +extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst; +#define imx35_add_flexcan(id, pdata) \ + imx_add_flexcan(&imx35_flexcan_data[id], pdata) +#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata) +#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata) + +extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst; +#define imx35_add_imx2_wdt(pdata) \ + imx_add_imx2_wdt(&imx35_imx2_wdt_data) extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst; #define imx35_add_imx_i2c(id, pdata) \ @@ -25,6 +34,10 @@ extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst; #define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata) #define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) +extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst; +#define imx31_add_imx_keypad(pdata) \ + imx_add_imx_keypad(&imx35_imx_keypad_data, pdata) + extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst; #define imx35_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata) @@ -36,16 +49,28 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst; #define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) #define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) +extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst; +#define imx35_add_mxc_ehci_otg(pdata) \ + imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata) +extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst; +#define imx35_add_mxc_ehci_hs(pdata) \ + imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata) + extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst; #define imx35_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) +extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst; +#define imx35_add_mxc_w1(pdata) \ + imx_add_mxc_w1(&imx35_mxc_w1_data) + +extern const struct imx_sdhci_esdhc_imx_data +imx35_sdhci_esdhc_imx_data[] __initconst; +#define imx35_add_sdhci_esdhc_imx(id, pdata) \ + imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata) + extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst; #define imx35_add_cspi(id, pdata) \ imx_add_spi_imx(&imx35_cspi_data[id], pdata) #define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) #define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) - -extern const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst; -#define imx35_add_esdhc(id, pdata) \ - imx_add_esdhc(&imx35_esdhc_data[id], pdata) diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index d4da949..b6672db 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -29,120 +29,25 @@ #include "devices.h" -/* GPIO port description */ -static struct mxc_gpio_port imx_gpio_ports[] = { - { - .chip.label = "gpio-0", - .base = IO_ADDRESS(GPIO1_BASE_ADDR), - .irq = MXC_INT_GPIO1, - .virtual_irq_start = MXC_GPIO_IRQ_START, - }, { - .chip.label = "gpio-1", - .base = IO_ADDRESS(GPIO2_BASE_ADDR), - .irq = MXC_INT_GPIO2, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, { - .chip.label = "gpio-2", - .base = IO_ADDRESS(GPIO3_BASE_ADDR), - .irq = MXC_INT_GPIO3, - .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - } -}; - -int __init imx3x_register_gpios(void) -{ - return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); -} - -static struct resource mxc_w1_master_resources[] = { - { - .start = OWIRE_BASE_ADDR, - .end = OWIRE_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_w1_master_device = { - .name = "mxc_w1", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_w1_master_resources), - .resource = mxc_w1_master_resources, -}; - -#ifdef CONFIG_ARCH_MX31 -static struct resource mxcsdhc0_resources[] = { - { - .start = MX31_MMC_SDHC1_BASE_ADDR, - .end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX31_INT_MMC_SDHC1, - .end = MX31_INT_MMC_SDHC1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource mxcsdhc1_resources[] = { - { - .start = MX31_MMC_SDHC2_BASE_ADDR, - .end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX31_INT_MMC_SDHC2, - .end = MX31_INT_MMC_SDHC2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxcsdhc_device0 = { - .name = "mxc-mmc", - .id = 0, - .num_resources = ARRAY_SIZE(mxcsdhc0_resources), - .resource = mxcsdhc0_resources, -}; - -struct platform_device mxcsdhc_device1 = { - .name = "mxc-mmc", - .id = 1, - .num_resources = ARRAY_SIZE(mxcsdhc1_resources), - .resource = mxcsdhc1_resources, -}; - -static struct resource rnga_resources[] = { - { - .start = RNGA_BASE_ADDR, - .end = RNGA_BASE_ADDR + 0x28, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_rnga_device = { - .name = "mxc_rnga", - .id = -1, - .num_resources = 1, - .resource = rnga_resources, -}; -#endif /* CONFIG_ARCH_MX31 */ - /* i.MX31 Image Processing Unit */ /* The resource order is important! */ static struct resource mx3_ipu_rsrc[] = { { - .start = IPU_CTRL_BASE_ADDR, - .end = IPU_CTRL_BASE_ADDR + 0x5F, + .start = MX3x_IPU_CTRL_BASE_ADDR, + .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F, .flags = IORESOURCE_MEM, }, { - .start = IPU_CTRL_BASE_ADDR + 0x88, - .end = IPU_CTRL_BASE_ADDR + 0xB3, + .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88, + .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_IPU_SYN, - .end = MXC_INT_IPU_SYN, + .start = MX3x_INT_IPU_SYN, + .end = MX3x_INT_IPU_SYN, .flags = IORESOURCE_IRQ, }, { - .start = MXC_INT_IPU_ERR, - .end = MXC_INT_IPU_ERR, + .start = MX3x_INT_IPU_ERR, + .end = MX3x_INT_IPU_ERR, .flags = IORESOURCE_IRQ, }, }; @@ -156,8 +61,8 @@ struct platform_device mx3_ipu = { static struct resource fb_resources[] = { { - .start = IPU_CTRL_BASE_ADDR + 0xB4, - .end = IPU_CTRL_BASE_ADDR + 0x1BF, + .start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4, + .end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF, .flags = IORESOURCE_MEM, }, }; @@ -174,8 +79,8 @@ struct platform_device mx3_fb = { static struct resource camera_resources[] = { { - .start = IPU_CTRL_BASE_ADDR + 0x60, - .end = IPU_CTRL_BASE_ADDR + 0x87, + .start = MX3x_IPU_CTRL_BASE_ADDR + 0x60, + .end = MX3x_IPU_CTRL_BASE_ADDR + 0x87, .flags = IORESOURCE_MEM, }, }; @@ -190,110 +95,6 @@ struct platform_device mx3_camera = { }, }; -static struct resource otg_resources[] = { - { - .start = MX31_OTG_BASE_ADDR, - .end = MX31_OTG_BASE_ADDR + 0x1ff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_USB3, - .end = MXC_INT_USB3, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 otg_dmamask = DMA_BIT_MASK(32); - -/* OTG gadget device */ -struct platform_device mxc_otg_udc_device = { - .name = "fsl-usb2-udc", - .id = -1, - .dev = { - .dma_mask = &otg_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), -}; - -/* OTG host */ -struct platform_device mxc_otg_host = { - .name = "mxc-ehci", - .id = 0, - .dev = { - .coherent_dma_mask = 0xffffffff, - .dma_mask = &otg_dmamask, - }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), -}; - -/* USB host 1 */ - -static u64 usbh1_dmamask = ~(u32)0; - -static struct resource mxc_usbh1_resources[] = { - { - .start = MX31_OTG_BASE_ADDR + 0x200, - .end = MX31_OTG_BASE_ADDR + 0x3ff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_USB1, - .end = MXC_INT_USB1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_usbh1 = { - .name = "mxc-ehci", - .id = 1, - .dev = { - .coherent_dma_mask = 0xffffffff, - .dma_mask = &usbh1_dmamask, - }, - .resource = mxc_usbh1_resources, - .num_resources = ARRAY_SIZE(mxc_usbh1_resources), -}; - -/* USB host 2 */ -static u64 usbh2_dmamask = ~(u32)0; - -static struct resource mxc_usbh2_resources[] = { - { - .start = MX31_OTG_BASE_ADDR + 0x400, - .end = MX31_OTG_BASE_ADDR + 0x5ff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_USB2, - .end = MXC_INT_USB2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_usbh2 = { - .name = "mxc-ehci", - .id = 2, - .dev = { - .coherent_dma_mask = 0xffffffff, - .dma_mask = &usbh2_dmamask, - }, - .resource = mxc_usbh2_resources, - .num_resources = ARRAY_SIZE(mxc_usbh2_resources), -}; - -static struct resource imx_wdt_resources[] = { - { - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device imx_wdt_device0 = { - .name = "imx2-wdt", - .id = 0, - .num_resources = ARRAY_SIZE(imx_wdt_resources), - .resource = imx_wdt_resources, -}; - static struct resource imx_rtc_resources[] = { { .start = MX31_RTC_BASE_ADDR, @@ -312,51 +113,3 @@ struct platform_device imx_rtc_device0 = { .num_resources = ARRAY_SIZE(imx_rtc_resources), .resource = imx_rtc_resources, }; - -static struct resource imx_kpp_resources[] = { - { - .start = MX3x_KPP_BASE_ADDR, - .end = MX3x_KPP_BASE_ADDR + 0xf, - .flags = IORESOURCE_MEM - }, { - .start = MX3x_INT_KPP, - .end = MX3x_INT_KPP, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_kpp_device = { - .name = "imx-keypad", - .id = -1, - .num_resources = ARRAY_SIZE(imx_kpp_resources), - .resource = imx_kpp_resources, -}; - -static int __init mx3_devices_init(void) -{ -#if defined(CONFIG_ARCH_MX31) - if (cpu_is_mx31()) { - imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR; - imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff; - mxc_register_device(&mxc_rnga_device, NULL); - } -#endif -#if defined(CONFIG_ARCH_MX35) - if (cpu_is_mx35()) { - otg_resources[0].start = MX35_OTG_BASE_ADDR; - otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; - otg_resources[1].start = MXC_INT_USBOTG; - otg_resources[1].end = MXC_INT_USBOTG; - mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400; - mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; - mxc_usbh1_resources[1].start = MXC_INT_USBHS; - mxc_usbh1_resources[1].end = MXC_INT_USBHS; - imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; - imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; - } -#endif - - return 0; -} - -subsys_initcall(mx3_devices_init); diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index 585f814..121962c 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h @@ -1,14 +1,4 @@ -extern struct platform_device mxc_w1_master_device; extern struct platform_device mx3_ipu; extern struct platform_device mx3_fb; extern struct platform_device mx3_camera; -extern struct platform_device mxcsdhc_device0; -extern struct platform_device mxcsdhc_device1; -extern struct platform_device mxc_otg_udc_device; -extern struct platform_device mxc_otg_host; -extern struct platform_device mxc_usbh1; -extern struct platform_device mxc_usbh2; -extern struct platform_device mxc_rnga_device; -extern struct platform_device imx_wdt_device0; extern struct platform_device imx_rtc_device0; -extern struct platform_device imx_kpp_device; diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c index 1abc10d..14a5ffc 100644 --- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c @@ -111,7 +111,7 @@ static struct mx3fb_platform_data mx3fb_pdata = { .num_modes = ARRAY_SIZE(fb_modedb), }; -static struct pad_desc eukrea_mbimxsd_pads[] = { +static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { /* LCD */ MX35_PAD_LD0__IPU_DISPB_DAT_0, MX35_PAD_LD1__IPU_DISPB_DAT_1, @@ -289,7 +289,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void) imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); imx35_add_flexcan1(NULL); - imx35_add_esdhc(0, NULL); + imx35_add_sdhci_esdhc_imx(0, NULL); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c index aaa30fe..28b6f41 100644 --- a/arch/arm/mach-mx3/mach-armadillo5x0.c +++ b/arch/arm/mach-mx3/mach-armadillo5x0.c @@ -49,10 +49,8 @@ #include <mach/common.h> #include <mach/iomux-mx3.h> -#include <mach/mmc.h> #include <mach/ipu.h> #include <mach/mx3fb.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx31.h" @@ -245,13 +243,13 @@ h2_free_cs: return err; } -static struct mxc_usbh_platform_data usbotg_pdata = { +static struct mxc_usbh_platform_data usbotg_pdata __initdata = { .init = usbotg_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, }; -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, @@ -453,7 +451,7 @@ static void armadillo5x0_sdhc1_exit(struct device *dev, void *data) gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B)); } -static struct imxmmc_platform_data sdhc_pdata = { +static const struct imxmmc_platform_data sdhc_pdata __initconst = { .get_ro = armadillo5x0_sdhc1_get_ro, .init = armadillo5x0_sdhc1_init, .exit = armadillo5x0_sdhc1_exit, @@ -520,7 +518,7 @@ static void __init armadillo5x0_init(void) gpio_direction_input(MX31_PIN_GPIO1_0); /* Register SDHC */ - mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); + imx31_add_mxc_mmc(0, &sdhc_pdata); /* Register FB */ mxc_register_device(&mx3_ipu, &mx3_ipu_data); @@ -555,8 +553,8 @@ static void __init armadillo5x0_init(void) usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_otg_host, &usbotg_pdata); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx31_add_mxc_ehci_otg(&usbotg_pdata); + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); #endif } diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c index 9fde873..26ae90f 100644 --- a/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/arch/arm/mach-mx3/mach-cpuimx35.c @@ -30,7 +30,6 @@ #include <linux/i2c/tsc2007.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> -#include <linux/fsl_devices.h> #include <linux/i2c-gpio.h> #include <asm/mach-types.h> @@ -43,7 +42,6 @@ #include <mach/common.h> #include <mach/iomux-mx35.h> #include <mach/mxc_nand.h> -#include <mach/mxc_ehci.h> #include "devices-imx35.h" #include "devices.h" @@ -74,11 +72,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { }, }; -static struct platform_device *devices[] __initdata = { - &imx_wdt_device0, -}; - -static struct pad_desc eukrea_cpuimx35_pads[] = { +static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = { /* UART1 */ MX35_PAD_CTS1__UART1_CTS, MX35_PAD_RTS1__UART1_RTS, @@ -117,18 +111,18 @@ static const struct mxc_nand_platform_data .flash_bbt = 1, }; -static struct mxc_usbh_platform_data __maybe_unused otg_pdata = { +static const struct mxc_usbh_platform_data otg_pdata __initconst = { .portsc = MXC_EHCI_MODE_UTMI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; -static struct mxc_usbh_platform_data __maybe_unused usbh1_pdata = { +static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { .portsc = MXC_EHCI_MODE_SERIAL, .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN, }; -static struct fsl_usb2_platform_data otg_device_pdata = { +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI, .workaround = FLS_USB2_WORKAROUND_ENGCM09152, @@ -158,7 +152,7 @@ static void __init mxc_board_init(void) ARRAY_SIZE(eukrea_cpuimx35_pads)); imx35_add_fec(NULL); - platform_add_devices(devices, ARRAY_SIZE(devices)); + imx35_add_imx2_wdt(NULL); imx35_add_imx_uart0(&uart_pdata); imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info); @@ -168,11 +162,11 @@ static void __init mxc_board_init(void) imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data); if (otg_mode_host) - mxc_register_device(&mxc_otg_host, &otg_pdata); + imx35_add_mxc_ehci_otg(&otg_pdata); else - mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + imx35_add_fsl_usb2_udc(&otg_device_pdata); - mxc_register_device(&mxc_usbh1, &usbh1_pdata); + imx35_add_mxc_ehci_hs(&usbh1_pdata); #ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD eukrea_mbimxsd35_baseboard_init(); diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c index 042cd56..a5f3eb2 100644 --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c @@ -41,9 +41,9 @@ #include "devices-imx31.h" #include "devices.h" -#define KZM_ARM11_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX31_CS4) ?: \ - IMX_IO_ADDRESS(x, MX31_CS5) ?: \ +#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \ + IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \ + IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \ MX31_IO_ADDRESS(x)) /* diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 0ad9e78..e4efbfe 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -22,8 +22,6 @@ #include <linux/mfd/mc13783.h> #include <linux/spi/spi.h> #include <linux/regulator/machine.h> -#include <linux/fsl_devices.h> -#include <linux/input/matrix_keypad.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -102,7 +100,7 @@ static const uint32_t mx31_3ds_keymap[] = { KEY(2, 3, KEY_F10), }; -static struct matrix_keymap_data mx31_3ds_keymap_data = { +static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = { .keymap = mx31_3ds_keymap, .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), }; @@ -129,7 +127,7 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { static struct mc13783_platform_data mc13783_pdata __initdata = { .regulators = mx31_3ds_regulators, .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), - .flags = MC13783_USE_REGULATOR, + .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN, }; /* SPI */ @@ -214,7 +212,7 @@ usbotg_free_reset: return err; } -static struct fsl_usb2_platform_data usbotg_pdata = { +static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; @@ -246,10 +244,10 @@ static void __init mxc_board_init(void) spi_register_board_info(mx31_3ds_spi_devs, ARRAY_SIZE(mx31_3ds_spi_devs)); - mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data); + imx31_add_imx_keypad(&mx31_3ds_keymap_data); mx31_3ds_usbotg_init(); - mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata); + imx31_add_fsl_usb2_udc(&usbotg_pdata); if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) printk(KERN_WARNING "Init of the debug board failed, all " diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index 42f47fa..2c59548 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -42,7 +42,6 @@ #include <mach/common.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31lilly.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx31.h" @@ -230,13 +229,13 @@ static struct mxc_usbh_platform_data usbotg_pdata = { .flags = MXC_EHCI_POWER_PINS_ENABLED, }; -static struct mxc_usbh_platform_data usbh1_pdata = { +static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { .init = usbh1_init, .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, }; -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED, @@ -249,8 +248,8 @@ static void lilly1131_usb_init(void) usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_usbh1, &usbh1_pdata); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx31_add_mxc_ehci_hs(1, &usbh1_pdata); + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); } #else diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index b938958..9e64c66 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -40,7 +40,6 @@ #include <mach/board-mx31lite.h> #include <mach/iomux-mx3.h> #include <mach/irqs.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx31.h" @@ -171,7 +170,7 @@ static int usbh2_init(struct platform_device *pdev) return 0; } -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED, @@ -258,7 +257,7 @@ static void __init mxc_board_init(void) usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); #endif /* SMSC9117 IRQ pin */ diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index eb5f426..203d21a 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -40,8 +40,6 @@ #include <mach/hardware.h> #include <mach/iomux-mx3.h> #include <mach/ipu.h> -#include <mach/mmc.h> -#include <mach/mxc_ehci.h> #include <mach/mx3_camera.h> #include <mach/spi.h> #include <mach/ulpi.h> @@ -170,11 +168,11 @@ static const struct spi_imx_master moboard_spi1_pdata __initconst = { static struct regulator_consumer_supply sdhc_consumers[] = { { - .dev = &mxcsdhc_device0.dev, + .dev_name = "mxc-mmc.0", .supply = "sdhc0_vcc", }, { - .dev = &mxcsdhc_device1.dev, + .dev_name = "mxc-mmc.1", .supply = "sdhc1_vcc", }, }; @@ -345,7 +343,7 @@ static void moboard_sdhc1_exit(struct device *dev, void *data) gpio_free(SDHC1_CD); } -static struct imxmmc_platform_data sdhc1_pdata = { +static const struct imxmmc_platform_data sdhc1_pdata __initconst = { .get_ro = moboard_sdhc1_get_ro, .init = moboard_sdhc1_init, .exit = moboard_sdhc1_exit, @@ -404,17 +402,23 @@ static void usb_xcvr_reset(void) #if defined(CONFIG_USB_ULPI) -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED, }; static int __init moboard_usbh2_init(void) { + struct platform_device *pdev; + usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - return mxc_register_device(&mxc_usbh2, &usbh2_pdata); + pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + return 0; } #else static inline int moboard_usbh2_init(void) { return 0; } @@ -520,7 +524,7 @@ static void __init mxc_board_init(void) spi_register_board_info(moboard_spi_board_info, ARRAY_SIZE(moboard_spi_board_info)); - mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata); + imx31_add_mxc_mmc(0, &sdhc1_pdata); mxc_register_device(&mx3_ipu, &mx3_ipu_data); if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE)) diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index b66a75a..8bd8992 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -26,7 +26,6 @@ #include <linux/platform_device.h> #include <linux/memory.h> #include <linux/gpio.h> -#include <linux/fsl_devices.h> #include <linux/mtd/physmap.h> @@ -40,7 +39,6 @@ #include <mach/iomux-mx35.h> #include <mach/irqs.h> #include <mach/3ds_debugboard.h> -#include <mach/mxc_ehci.h> #include "devices-imx35.h" #include "devices.h" @@ -81,7 +79,7 @@ static struct platform_device *devices[] __initdata = { &mx35pdk_flash, }; -static struct pad_desc mx35pdk_pads[] = { +static iomux_v3_cfg_t mx35pdk_pads[] = { /* UART1 */ MX35_PAD_CTS1__UART1_CTS, MX35_PAD_RTS1__UART1_RTS, @@ -122,13 +120,13 @@ static struct pad_desc mx35pdk_pads[] = { }; /* OTG config */ -static struct fsl_usb2_platform_data usb_otg_pdata = { +static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI_WIDE, }; /* USB HOST config */ -static struct mxc_usbh_platform_data usb_host_pdata = { +static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { .portsc = MXC_EHCI_MODE_SERIAL, .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY, @@ -142,16 +140,17 @@ static void __init mxc_board_init(void) mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); imx35_add_fec(NULL); + imx35_add_imx2_wdt(NULL); platform_add_devices(devices, ARRAY_SIZE(devices)); imx35_add_imx_uart0(&uart_pdata); - mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata); + imx35_add_fsl_usb2_udc(&usb_otg_pdata); - mxc_register_device(&mxc_usbh1, &usb_host_pdata); + imx35_add_mxc_ehci_hs(&usb_host_pdata); imx35_add_mxc_nand(&mx35pdk_nand_board_info); - imx35_add_esdhc(0, NULL); + imx35_add_sdhci_esdhc_imx(0, NULL); if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT)) pr_warn("Init of the debugboard failed, all " diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index 2ff3f66..b752f6b 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -27,7 +27,6 @@ #include <linux/delay.h> #include <linux/spi/spi.h> #include <linux/irq.h> -#include <linux/fsl_devices.h> #include <linux/can/platform/sja1000.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> @@ -43,10 +42,8 @@ #include <mach/hardware.h> #include <mach/iomux-mx3.h> #include <mach/ipu.h> -#include <mach/mmc.h> #include <mach/mx3_camera.h> #include <mach/mx3fb.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx31.h" @@ -399,7 +396,7 @@ static void pcm970_sdhc1_exit(struct device *dev, void *data) gpio_free(SDHC1_GPIO_WP); } -static struct imxmmc_platform_data sdhc_pdata = { +static const struct imxmmc_platform_data sdhc_pdata __initconst = { #ifdef PCM970_SDHC_RW_SWITCH .get_ro = pcm970_sdhc1_get_ro, #endif @@ -441,7 +438,6 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size) static struct platform_device *devices[] __initdata = { &pcm037_flash, &pcm037_sram_device, - &imx_wdt_device0, &pcm037_mt9t031, &pcm037_mt9v022, }; @@ -538,18 +534,18 @@ static struct platform_device pcm970_sja1000 = { }; #if defined(CONFIG_USB_ULPI) -static struct mxc_usbh_platform_data otg_pdata = { +static struct mxc_usbh_platform_data otg_pdata __initdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; #endif -static struct fsl_usb2_platform_data otg_device_pdata = { +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; @@ -607,12 +603,13 @@ static void __init mxc_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); + imx31_add_imx2_wdt(NULL); imx31_add_imx_uart0(&uart_pdata); /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ imx31_add_imx_uart1(&uart_pdata); imx31_add_imx_uart2(&uart_pdata); - mxc_register_device(&mxc_w1_master_device, NULL); + imx31_add_mxc_w1(NULL); /* LAN9217 IRQ pin */ ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); @@ -632,7 +629,7 @@ static void __init mxc_board_init(void) imx31_add_imx_i2c2(&pcm037_i2c2_data); imx31_add_mxc_nand(&pcm037_nand_board_info); - mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); + imx31_add_mxc_mmc(0, &sdhc_pdata); mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); @@ -654,16 +651,16 @@ static void __init mxc_board_init(void) otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_otg_host, &otg_pdata); + imx31_add_mxc_ehci_otg(&otg_pdata); } usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); #endif if (!otg_mode_host) - mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + imx31_add_fsl_usb2_udc(&otg_device_pdata); } diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 4e1de87..e229a74 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -27,7 +27,6 @@ #include <linux/i2c/at24.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> -#include <linux/fsl_devices.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -39,7 +38,6 @@ #include <mach/iomux-mx35.h> #include <mach/ipu.h> #include <mach/mx3fb.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include <mach/audmux.h> @@ -140,10 +138,9 @@ static struct i2c_board_info pcm043_i2c_devices[] = { static struct platform_device *devices[] __initdata = { &pcm043_flash, - &imx_wdt_device0, }; -static struct pad_desc pcm043_pads[] = { +static iomux_v3_cfg_t pcm043_pads[] = { /* UART1 */ MX35_PAD_CTS1__UART1_CTS, MX35_PAD_RTS1__UART1_RTS, @@ -230,8 +227,8 @@ static struct pad_desc pcm043_pads[] = { static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) { - struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; - struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; + iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; + iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; int ret; ret = gpio_request(AC97_GPIO_TXFS, "SSI"); @@ -253,11 +250,11 @@ static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) { - struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; - struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; - struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28; - struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; - struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; + iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; + iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; + iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28; + iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; + iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; int ret; ret = gpio_request(AC97_GPIO_TXFS, "SSI"); @@ -311,19 +308,19 @@ pcm037_nand_board_info __initconst = { }; #if defined(CONFIG_USB_ULPI) -static struct mxc_usbh_platform_data otg_pdata = { +static struct mxc_usbh_platform_data otg_pdata __initdata = { .portsc = MXC_EHCI_MODE_UTMI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; -static struct mxc_usbh_platform_data usbh1_pdata = { +static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { .portsc = MXC_EHCI_MODE_SERIAL, .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN, }; #endif -static struct fsl_usb2_platform_data otg_device_pdata = { +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI, }; @@ -364,6 +361,7 @@ static void __init mxc_board_init(void) imx35_add_fec(NULL); platform_add_devices(devices, ARRAY_SIZE(devices)); + imx35_add_imx2_wdt(NULL); imx35_add_imx_uart0(&uart_pdata); imx35_add_mxc_nand(&pcm037_nand_board_info); @@ -386,16 +384,16 @@ static void __init mxc_board_init(void) otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_otg_host, &otg_pdata); + imx35_add_mxc_ehci_otg(&otg_pdata); } - mxc_register_device(&mxc_usbh1, &usbh1_pdata); + imx35_add_mxc_ehci_hs(&usbh1_pdata); #endif if (!otg_mode_host) - mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + imx35_add_fsl_usb2_udc(&otg_device_pdata); imx35_add_flexcan1(NULL); - imx35_add_esdhc(0, NULL); + imx35_add_sdhci_esdhc_imx(0, NULL); } static void __init pcm043_timer_init(void) diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c index b4ffc53..47118f7 100644 --- a/arch/arm/mach-mx3/mm.c +++ b/arch/arm/mach-mx3/mm.c @@ -36,40 +36,16 @@ * @ingroup Memory */ -/*! - * This table defines static virtual address mappings for I/O regions. - * These are the mappings common across all MX3 boards. - */ -static struct map_desc mxc_io_desc[] __initdata = { - { - .virtual = X_MEMC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), - .length = X_MEMC_SIZE, - .type = MT_DEVICE - }, { - .virtual = AVIC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(AVIC_BASE_ADDR), - .length = AVIC_SIZE, - .type = MT_DEVICE_NONSHARED - }, { - .virtual = AIPS1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), - .length = AIPS1_SIZE, - .type = MT_DEVICE_NONSHARED - }, { - .virtual = AIPS2_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), - .length = AIPS2_SIZE, - .type = MT_DEVICE_NONSHARED - }, { - .virtual = SPBA0_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), - .length = SPBA0_SIZE, - .type = MT_DEVICE_NONSHARED - }, +#ifdef CONFIG_SOC_IMX31 +static struct map_desc mx31_io_desc[] __initdata = { + imx_map_entry(MX31, X_MEMC, MT_DEVICE), + imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), + imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), + imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), + imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), }; -/*! +/* * This function initializes the memory map. It is called during the * system startup to create static physical to virtual memory mappings * for the IO modules. @@ -77,34 +53,44 @@ static struct map_desc mxc_io_desc[] __initdata = { void __init mx31_map_io(void) { mxc_set_cpu_type(MXC_CPU_MX31); - mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); + mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); + iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); } -#ifdef CONFIG_ARCH_MX35 -void __init mx35_map_io(void) +int imx31_register_gpios(void); +void __init mx31_init_irq(void) { - mxc_set_cpu_type(MXC_CPU_MX35); - mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); - - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); + mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); + imx31_register_gpios(); } -#endif - -int imx3x_register_gpios(void); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +static struct map_desc mx35_io_desc[] __initdata = { + imx_map_entry(MX35, X_MEMC, MT_DEVICE), + imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), + imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), + imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), + imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), +}; -void __init mx31_init_irq(void) +void __init mx35_map_io(void) { - mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); - imx3x_register_gpios(); + mxc_set_cpu_type(MXC_CPU_MX35); + mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); + mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); + + iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); } +int imx35_register_gpios(void); void __init mx35_init_irq(void) { - mx31_init_irq(); + mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); + imx35_register_gpios(); } +#endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_CACHE_L2X0 static int mxc_init_l2x0(void) @@ -129,7 +115,7 @@ static int mxc_init_l2x0(void) pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); } - l2x0_base = ioremap(L2CC_BASE_ADDR, 4096); + l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); if (IS_ERR(l2x0_base)) { printk(KERN_ERR "remapping L2 cache area failed with %ld\n", PTR_ERR(l2x0_base)); diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c index 827fd3c..8f1a38e 100644 --- a/arch/arm/mach-mx3/mx31lilly-db.c +++ b/arch/arm/mach-mx3/mx31lilly-db.c @@ -34,7 +34,6 @@ #include <mach/common.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31lilly.h> -#include <mach/mmc.h> #include <mach/mx3fb.h> #include <mach/ipu.h> @@ -158,7 +157,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data) free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); } -static struct imxmmc_platform_data mmc_pdata = { +static const struct imxmmc_platform_data mmc_pdata __initconst = { .get_ro = mxc_mmc1_get_ro, .init = mxc_mmc1_init, .exit = mxc_mmc1_exit, @@ -216,7 +215,7 @@ void __init mx31lilly_db_init(void) imx31_add_imx_uart0(&uart_pdata); imx31_add_imx_uart1(&uart_pdata); imx31_add_imx_uart2(&uart_pdata); - mxc_register_device(&mxcsdhc_device0, &mmc_pdata); + imx31_add_mxc_mmc(0, &mmc_pdata); mx31lilly_init_fb(); } diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c index 7b0e74e..3124ea8 100644 --- a/arch/arm/mach-mx3/mx31lite-db.c +++ b/arch/arm/mach-mx3/mx31lite-db.c @@ -35,7 +35,6 @@ #include <mach/common.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31lite.h> -#include <mach/mmc.h> #include "devices-imx31.h" #include "devices.h" @@ -142,7 +141,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data) free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data); } -static struct imxmmc_platform_data mmc_pdata = { +static const struct imxmmc_platform_data mmc_pdata __initconst = { .get_ro = mxc_mmc1_get_ro, .init = mxc_mmc1_init, .exit = mxc_mmc1_exit, @@ -197,10 +196,9 @@ void __init mx31lite_db_init(void) ARRAY_SIZE(litekit_db_board_pins), "development board pins"); imx31_add_imx_uart0(&uart_pdata); - mxc_register_device(&mxcsdhc_device0, &mmc_pdata); + imx31_add_mxc_mmc(0, &mmc_pdata); imx31_add_spi_imx0(&spi0_pdata); platform_device_register(&litekit_led_device); - mxc_register_device(&imx_wdt_device0, NULL); + imx31_add_imx2_wdt(NULL); mxc_register_device(&imx_rtc_device0, NULL); } - diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c index fc395a7..94a0b9e 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c @@ -18,15 +18,12 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/types.h> -#include <linux/fsl_devices.h> #include <linux/usb/otg.h> #include <mach/common.h> #include <mach/iomux-mx3.h> #include <mach/hardware.h> -#include <mach/mmc.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx31.h" @@ -103,7 +100,7 @@ static void devboard_sdhc2_exit(struct device *dev, void *data) gpio_free(SDHC2_CD); } -static struct imxmmc_platform_data sdhc2_pdata = { +static const struct imxmmc_platform_data sdhc2_pdata __initconst = { .get_ro = devboard_sdhc2_get_ro, .init = devboard_sdhc2_init, .exit = devboard_sdhc2_exit, @@ -187,7 +184,7 @@ static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on) return 0; } -static struct mxc_usbh_platform_data usbh1_pdata = { +static struct mxc_usbh_platform_data usbh1_pdata __initdata = { .init = devboard_usbh1_hw_init, .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, @@ -196,6 +193,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = { static int __init devboard_usbh1_init(void) { struct otg_transceiver *otg; + struct platform_device *pdev; otg = kzalloc(sizeof(*otg), GFP_KERNEL); if (!otg) @@ -207,11 +205,15 @@ static int __init devboard_usbh1_init(void) usbh1_pdata.otg = otg; - return mxc_register_device(&mxc_usbh1, &usbh1_pdata); + pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + return 0; } -static struct fsl_usb2_platform_data usb_pdata = { +static const struct fsl_usb2_platform_data usb_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; @@ -228,11 +230,11 @@ void __init mx31moboard_devboard_init(void) imx31_add_imx_uart1(&uart_pdata); - mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); + imx31_add_mxc_mmc(1, &sdhc2_pdata); devboard_init_sel_gpios(); - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + imx31_add_fsl_usb2_udc(&usb_pdata); devboard_usbh1_init(); } diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index 18069cb..f449a97 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -21,7 +21,6 @@ #include <linux/slab.h> #include <linux/platform_device.h> #include <linux/types.h> -#include <linux/fsl_devices.h> #include <linux/usb/otg.h> @@ -29,12 +28,11 @@ #include <mach/hardware.h> #include <mach/imx-uart.h> #include <mach/iomux-mx3.h> -#include <mach/mmc.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include <media/soc_camera.h> +#include "devices-imx31.h" #include "devices.h" static unsigned int marxbot_pins[] = { @@ -116,7 +114,7 @@ static void marxbot_sdhc2_exit(struct device *dev, void *data) gpio_free(SDHC2_CD); } -static struct imxmmc_platform_data sdhc2_pdata = { +static const struct imxmmc_platform_data sdhc2_pdata __initconst = { .get_ro = marxbot_sdhc2_get_ro, .init = marxbot_sdhc2_init, .exit = marxbot_sdhc2_exit, @@ -302,7 +300,7 @@ static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on) return 0; } -static struct mxc_usbh_platform_data usbh1_pdata = { +static struct mxc_usbh_platform_data usbh1_pdata __initdata = { .init = marxbot_usbh1_hw_init, .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, @@ -311,6 +309,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = { static int __init marxbot_usbh1_init(void) { struct otg_transceiver *otg; + struct platform_device *pdev; otg = kzalloc(sizeof(*otg), GFP_KERNEL); if (!otg) @@ -322,10 +321,14 @@ static int __init marxbot_usbh1_init(void) usbh1_pdata.otg = otg; - return mxc_register_device(&mxc_usbh1, &usbh1_pdata); + pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + return 0; } -static struct fsl_usb2_platform_data usb_pdata = { +static const struct fsl_usb2_platform_data usb_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; @@ -344,7 +347,7 @@ void __init mx31moboard_marxbot_init(void) dspics_resets_init(); - mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); + imx31_add_mxc_mmc(1, &sdhc2_pdata); spi_register_board_info(marxbot_spi_board_info, ARRAY_SIZE(marxbot_spi_board_info)); @@ -357,7 +360,7 @@ void __init mx31moboard_marxbot_init(void) gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + imx31_add_fsl_usb2_udc(&usb_pdata); marxbot_usbh1_init(); } diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c index 04760a5..bbec3c8 100644 --- a/arch/arm/mach-mx3/mx31moboard-smartbot.c +++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c @@ -19,7 +19,6 @@ #include <linux/i2c.h> #include <linux/platform_device.h> #include <linux/types.h> -#include <linux/fsl_devices.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> @@ -28,7 +27,6 @@ #include <mach/hardware.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31moboard.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include <media/soc_camera.h> @@ -118,24 +116,30 @@ static int __init smartbot_cam_init(void) return 0; } -static struct fsl_usb2_platform_data usb_pdata = { +static const struct fsl_usb2_platform_data usb_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; #if defined(CONFIG_USB_ULPI) -static struct mxc_usbh_platform_data otg_host_pdata = { +static struct mxc_usbh_platform_data otg_host_pdata __initdata = { .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED, }; static int __init smartbot_otg_host_init(void) { + struct platform_device *pdev; + otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - return mxc_register_device(&mxc_otg_host, &otg_host_pdata); + pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + return 0; } #else static inline int smartbot_otg_host_init(void) { return 0; } @@ -182,7 +186,7 @@ void __init mx31moboard_smartbot_init(int board) switch (board) { case MX31SMARTBOT: - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + imx31_add_fsl_usb2_udc(&usb_pdata); break; case MX31EYEBOT: smartbot_otg_host_init(); diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 3ec910a..7f5a696 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -1,20 +1,26 @@ if ARCH_MX5 +# ARCH_MX51 is left for compatibility config ARCH_MX51 bool - default y + +config SOC_IMX51 + bool select MXC_TZIC select ARCH_MXC_IOMUX_V3 select ARCH_MXC_AUDMUX_V2 select ARCH_HAS_CPUFREQ + select ARCH_MX51 comment "MX5 platforms:" config MACH_MX51_BABBAGE bool "Support MX51 BABBAGE platforms" + select SOC_IMX51 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_ESDHC + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select IMX_HAVE_PLATFORM_SPI_IMX help Include support for MX51 Babbage platform, also known as MX51EVK in u-boot. This includes specific configurations for the board and its @@ -22,7 +28,9 @@ config MACH_MX51_BABBAGE config MACH_MX51_3DS bool "Support MX51PDK (3DS)" + select SOC_IMX51 select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_SPI_IMX select MXC_DEBUG_BOARD help @@ -31,6 +39,7 @@ config MACH_MX51_3DS config MACH_EUKREA_CPUIMX51 bool "Support Eukrea CPUIMX51 module" + select SOC_IMX51 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_NAND @@ -47,7 +56,7 @@ choice config MACH_EUKREA_MBIMX51_BASEBOARD prompt "Eukrea MBIMX51 development board" bool - select IMX_HAVE_PLATFORM_ESDHC + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX help This adds board specific devices that can be found on Eukrea's MBIMX51 evaluation board. @@ -56,6 +65,7 @@ endchoice config MACH_EUKREA_CPUIMX51SD bool "Support Eukrea CPUIMX51SD module" + select SOC_IMX51 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_SPI_IMX select IMX_HAVE_PLATFORM_IMX_UART @@ -72,7 +82,7 @@ choice config MACH_EUKREA_MBIMXSD51_BASEBOARD prompt "Eukrea MBIMXSD development board" bool - select IMX_HAVE_PLATFORM_ESDHC + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX help This adds board specific devices that can be found on Eukrea's MBIMXSD evaluation board. @@ -81,7 +91,10 @@ endchoice config MACH_MX51_EFIKAMX bool "Support MX51 Genesi Efika MX nettop" + select SOC_IMX51 select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select IMX_HAVE_PLATFORM_SPI_IMX help Include support for Genesi Efika MX nettop. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 462f177..026cd85 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -3,7 +3,7 @@ # # Object file lists. -obj-y := cpu.o mm.o clock-mx51.o devices.o +obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c index 6a9792f..6ab002d 100644 --- a/arch/arm/mach-mx5/board-cpuimx51.c +++ b/arch/arm/mach-mx5/board-cpuimx51.c @@ -40,11 +40,11 @@ #include "devices-imx51.h" #include "devices.h" -#define CPUIMX51_USBH1_STP (0*32 + 27) -#define CPUIMX51_QUARTA_GPIO (2*32 + 28) -#define CPUIMX51_QUARTB_GPIO (2*32 + 25) -#define CPUIMX51_QUARTC_GPIO (2*32 + 26) -#define CPUIMX51_QUARTD_GPIO (2*32 + 27) +#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27) +#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28) +#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25) +#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26) +#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27) #define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO) #define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO) #define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO) @@ -113,7 +113,7 @@ static struct platform_device *devices[] __initdata = { #endif }; -static struct pad_desc eukrea_cpuimx51_pads[] = { +static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { /* UART1 */ MX51_PAD_UART1_RXD__UART1_RXD, MX51_PAD_UART1_TXD__UART1_TXD, @@ -292,7 +292,7 @@ static struct sys_timer mxc_timer = { MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") /* Maintainer: Eric Bénard <eric@eukrea.com> */ - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX51_PHYS_OFFSET + 0x100, .map_io = mx51_map_io, .init_irq = mx51_init_irq, .init_machine = eukrea_cpuimx51_init, diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c index 4b3a611..8e71c19 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c @@ -43,19 +43,19 @@ #include "devices-imx51.h" #include "devices.h" -#define USBH1_RST (1*32 + 28) -#define ETH_RST (1*32 + 31) -#define TSC2007_IRQGPIO (2*32 + 12) -#define CAN_IRQGPIO (0*32 + 1) -#define CAN_RST (3*32 + 15) -#define CAN_NCS (3*32 + 24) -#define CAN_RXOBF (0*32 + 4) -#define CAN_RX1BF (0*32 + 6) -#define CAN_TXORTS (0*32 + 7) -#define CAN_TX1RTS (0*32 + 8) -#define CAN_TX2RTS (0*32 + 9) -#define I2C_SCL (3*32 + 16) -#define I2C_SDA (3*32 + 17) +#define USBH1_RST IMX_GPIO_NR(2, 28) +#define ETH_RST IMX_GPIO_NR(2, 31) +#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12) +#define CAN_IRQGPIO IMX_GPIO_NR(1, 1) +#define CAN_RST IMX_GPIO_NR(4, 15) +#define CAN_NCS IMX_GPIO_NR(4, 24) +#define CAN_RXOBF IMX_GPIO_NR(1, 4) +#define CAN_RX1BF IMX_GPIO_NR(1, 6) +#define CAN_TXORTS IMX_GPIO_NR(1, 7) +#define CAN_TX1RTS IMX_GPIO_NR(1, 8) +#define CAN_TX2RTS IMX_GPIO_NR(1, 9) +#define I2C_SCL IMX_GPIO_NR(4, 16) +#define I2C_SDA IMX_GPIO_NR(4, 17) /* USB_CTRL_1 */ #define MX51_USB_CTRL_1_OFFSET 0x10 @@ -68,7 +68,7 @@ #define CPUIMX51SD_GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, \ MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) -static struct pad_desc eukrea_cpuimx51sd_pads[] = { +static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = { /* UART1 */ MX51_PAD_UART1_RXD__UART1_RXD, MX51_PAD_UART1_TXD__UART1_TXD, @@ -243,7 +243,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = { .mode = SPI_MODE_0, .chip_select = 0, .platform_data = &mcp251x_info, - .irq = gpio_to_irq(0 * 32 + 1) + .irq = gpio_to_irq(CAN_IRQGPIO) }, }; @@ -323,7 +323,7 @@ static struct sys_timer mxc_timer = { MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD") /* Maintainer: Eric Bénard <eric@eukrea.com> */ - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX51_PHYS_OFFSET + 0x100, .map_io = mx51_map_io, .init_irq = mx51_init_irq, .init_machine = eukrea_cpuimx51sd_init, diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index 79ce8dc..6cc2805 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -30,7 +30,7 @@ #define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6) #define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) -static struct pad_desc mx51_3ds_pads[] = { +static iomux_v3_cfg_t mx51_3ds_pads[] = { /* UART1 */ MX51_PAD_UART1_RXD__UART1_RXD, MX51_PAD_UART1_TXD__UART1_TXD, @@ -172,6 +172,7 @@ static void __init mxc_board_init(void) printk(KERN_WARNING "Init of the debugboard failed, all " "devices on the board are unusable.\n"); + imx51_add_sdhci_esdhc_imx(0, NULL); mxc_init_keypad(); } @@ -186,7 +187,7 @@ static struct sys_timer mxc_timer = { MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") /* Maintainer: Freescale Semiconductor, Inc. */ - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX51_PHYS_OFFSET + 0x100, .map_io = mx51_map_io, .init_irq = mx51_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index acbe30d..6442579 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -20,6 +20,8 @@ #include <linux/fec.h> #include <linux/gpio_keys.h> #include <linux/input.h> +#include <linux/spi/flash.h> +#include <linux/spi/spi.h> #include <mach/common.h> #include <mach/hardware.h> @@ -36,11 +38,13 @@ #include "devices.h" #include "cpu_op-mx51.h" -#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ -#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ -#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */ -#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */ -#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */ +#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7) +#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27) +#define BABBAGE_PHY_RESET IMX_GPIO_NR(2, 5) +#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14) +#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21) +#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24) +#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25) /* USB_CTRL_1 */ #define MX51_USB_CTRL_1_OFFSET 0x10 @@ -65,7 +69,7 @@ static const struct gpio_keys_platform_data imx_button_data __initconst = { .nbuttons = ARRAY_SIZE(babbage_buttons), }; -static struct pad_desc mx51babbage_pads[] = { +static iomux_v3_cfg_t mx51babbage_pads[] = { /* UART1 */ MX51_PAD_UART1_RXD__UART1_RXD, MX51_PAD_UART1_TXD__UART1_TXD, @@ -147,6 +151,13 @@ static struct pad_desc mx51babbage_pads[] = { MX51_PAD_SD2_DATA1__SD2_DATA1, MX51_PAD_SD2_DATA2__SD2_DATA2, MX51_PAD_SD2_DATA3__SD2_DATA3, + + /* eCSPI1 */ + MX51_PAD_CSPI1_MISO__ECSPI1_MISO, + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + MX51_PAD_CSPI1_SS0__GPIO_4_24, + MX51_PAD_CSPI1_SS1__GPIO_4_25, }; /* Serial ports */ @@ -177,8 +188,8 @@ static struct imxi2c_platform_data babbage_hsi2c_data = { static int gpio_usbh1_active(void) { - struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27; - struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5; + iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27; + iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5; int ret; /* Set USBH1_STP to GPIO and toggle it */ @@ -310,13 +321,34 @@ static int __init babbage_otg_mode(char *options) } __setup("otg_mode=", babbage_otg_mode); +static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = { + { + .modalias = "mtd_dataflash", + .max_speed_hz = 25000000, + .bus_num = 0, + .chip_select = 1, + .mode = SPI_MODE_0, + .platform_data = NULL, + }, +}; + +static int mx51_babbage_spi_cs[] = { + BABBAGE_ECSPI1_CS0, + BABBAGE_ECSPI1_CS1, +}; + +static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = { + .chipselect = mx51_babbage_spi_cs, + .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs), +}; + /* * Board specific initialization. */ static void __init mxc_board_init(void) { - struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; - struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21; + iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; + iomux_v3_cfg_t power_key = MX51_PAD_EIM_A27__GPIO_2_21; #if defined(CONFIG_CPU_FREQ_IMX) get_cpu_op = mx51_get_cpu_op; @@ -349,8 +381,12 @@ static void __init mxc_board_init(void) mxc_iomux_v3_setup_pad(&usbh1stp); babbage_usbhub_reset(); - imx51_add_esdhc(0, NULL); - imx51_add_esdhc(1, NULL); + imx51_add_sdhci_esdhc_imx(0, NULL); + imx51_add_sdhci_esdhc_imx(1, NULL); + + spi_register_board_info(mx51_babbage_spi_board_info, + ARRAY_SIZE(mx51_babbage_spi_board_info)); + imx51_add_ecspi(0, &mx51_babbage_spi_pdata); } static void __init mx51_babbage_timer_init(void) diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index 6e623bd..5ab21a0 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c @@ -18,9 +18,13 @@ #include <linux/platform_device.h> #include <linux/i2c.h> #include <linux/gpio.h> +#include <linux/leds.h> +#include <linux/input.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/fsl_devices.h> +#include <linux/spi/flash.h> +#include <linux/spi/spi.h> #include <mach/common.h> #include <mach/hardware.h> @@ -39,12 +43,81 @@ #define MX51_USB_PLL_DIV_24_MHZ 0x01 -static struct pad_desc mx51efikamx_pads[] = { +#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) +#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17) +#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11) + +#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13) +#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14) +#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15) + +#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31) + +#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24) +#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25) + +/* board 1.1 doesn't have same reset gpio */ +#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2) +#define EFIKAMX_RESET IMX_GPIO_NR(1, 4) + +/* the pci ids pin have pull up. they're driven low according to board id */ +#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) + +static iomux_v3_cfg_t mx51efikamx_pads[] = { /* UART1 */ MX51_PAD_UART1_RXD__UART1_RXD, MX51_PAD_UART1_TXD__UART1_TXD, MX51_PAD_UART1_RTS__UART1_RTS, MX51_PAD_UART1_CTS__UART1_CTS, + /* board id */ + MX51_PAD_PCBID0, + MX51_PAD_PCBID1, + MX51_PAD_PCBID2, + + /* SD 1 */ + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + + /* SD 2 */ + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + + /* SD/MMC WP/CD */ + MX51_PAD_GPIO_1_0__ESDHC1_CD, + MX51_PAD_GPIO_1_1__ESDHC1_WP, + MX51_PAD_GPIO_1_7__ESDHC2_WP, + MX51_PAD_GPIO_1_8__ESDHC2_CD, + + /* leds */ + MX51_PAD_CSI1_D9__GPIO_3_13, + MX51_PAD_CSI1_VSYNC__GPIO_3_14, + MX51_PAD_CSI1_HSYNC__GPIO_3_15, + + /* power key */ + MX51_PAD_PWRKEY, + + /* spi */ + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, + MX51_PAD_CSPI1_MISO__ECSPI1_MISO, + MX51_PAD_CSPI1_SS0__GPIO_4_24, + MX51_PAD_CSPI1_SS1__GPIO_4_25, + MX51_PAD_CSPI1_RDY__ECSPI1_RDY, + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + + /* reset */ + MX51_PAD_DI1_PIN13__GPIO_3_2, + MX51_PAD_GPIO_1_4__GPIO_1_4, }; /* Serial ports */ @@ -92,12 +165,182 @@ static struct mxc_usbh_platform_data dr_utmi_config = { .flags = MXC_EHCI_INTERNAL_PHY, }; +/* PCBID2 PCBID1 PCBID0 STATE + 1 1 1 ER1:rev1.1 + 1 1 0 ER2:rev1.2 + 1 0 1 ER3:rev1.3 + 1 0 0 ER4:rev1.4 +*/ +static void __init mx51_efikamx_board_id(void) +{ + int id; + + /* things are taking time to settle */ + msleep(150); + + gpio_request(EFIKAMX_PCBID0, "pcbid0"); + gpio_direction_input(EFIKAMX_PCBID0); + gpio_request(EFIKAMX_PCBID1, "pcbid1"); + gpio_direction_input(EFIKAMX_PCBID1); + gpio_request(EFIKAMX_PCBID2, "pcbid2"); + gpio_direction_input(EFIKAMX_PCBID2); + + id = gpio_get_value(EFIKAMX_PCBID0); + id |= gpio_get_value(EFIKAMX_PCBID1) << 1; + id |= gpio_get_value(EFIKAMX_PCBID2) << 2; + + switch (id) { + case 7: + system_rev = 0x11; + break; + case 6: + system_rev = 0x12; + break; + case 5: + system_rev = 0x13; + break; + case 4: + system_rev = 0x14; + break; + default: + system_rev = 0x10; + break; + } + + if ((system_rev == 0x10) + || (system_rev == 0x12) + || (system_rev == 0x14)) { + printk(KERN_WARNING + "EfikaMX: Unsupported board revision 1.%u!\n", + system_rev & 0xf); + } +} + +static struct gpio_led mx51_efikamx_leds[] = { + { + .name = "efikamx:green", + .default_trigger = "default-on", + .gpio = EFIKAMX_GREEN_LED, + }, + { + .name = "efikamx:red", + .default_trigger = "ide-disk", + .gpio = EFIKAMX_RED_LED, + }, + { + .name = "efikamx:blue", + .default_trigger = "mmc0", + .gpio = EFIKAMX_BLUE_LED, + }, +}; + +static struct gpio_led_platform_data mx51_efikamx_leds_data = { + .leds = mx51_efikamx_leds, + .num_leds = ARRAY_SIZE(mx51_efikamx_leds), +}; + +static struct platform_device mx51_efikamx_leds_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &mx51_efikamx_leds_data, + }, +}; + +static struct gpio_keys_button mx51_efikamx_powerkey[] = { + { + .code = KEY_POWER, + .gpio = EFIKAMX_POWER_KEY, + .type = EV_PWR, + .desc = "Power Button (CM)", + .wakeup = 1, + .debounce_interval = 10, /* ms */ + }, +}; + +static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = { + .buttons = mx51_efikamx_powerkey, + .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey), +}; + +static struct mtd_partition mx51_efikamx_spi_nor_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = SZ_256K, + }, + { + .name = "config", + .offset = MTDPART_OFS_APPEND, + .size = SZ_64K, + }, +}; + +static struct flash_platform_data mx51_efikamx_spi_flash_data = { + .name = "spi_flash", + .parts = mx51_efikamx_spi_nor_partitions, + .nr_parts = ARRAY_SIZE(mx51_efikamx_spi_nor_partitions), + .type = "sst25vf032b", +}; + +static struct spi_board_info mx51_efikamx_spi_board_info[] __initdata = { + { + .modalias = "m25p80", + .max_speed_hz = 25000000, + .bus_num = 0, + .chip_select = 1, + .platform_data = &mx51_efikamx_spi_flash_data, + .irq = -1, + }, +}; + +static int mx51_efikamx_spi_cs[] = { + EFIKAMX_SPI_CS0, + EFIKAMX_SPI_CS1, +}; + +static const struct spi_imx_master mx51_efikamx_spi_pdata __initconst = { + .chipselect = mx51_efikamx_spi_cs, + .num_chipselect = ARRAY_SIZE(mx51_efikamx_spi_cs), +}; + +void mx51_efikamx_reset(void) +{ + if (system_rev == 0x11) + gpio_direction_output(EFIKAMX_RESET1_1, 0); + else + gpio_direction_output(EFIKAMX_RESET, 0); +} + static void __init mxc_board_init(void) { mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, ARRAY_SIZE(mx51efikamx_pads)); + mx51_efikamx_board_id(); mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); mxc_init_imx_uart(); + imx51_add_sdhci_esdhc_imx(0, NULL); + + /* on < 1.2 boards both SD controllers are used */ + if (system_rev < 0x12) { + imx51_add_sdhci_esdhc_imx(1, NULL); + mx51_efikamx_leds[2].default_trigger = "mmc1"; + } + + platform_device_register(&mx51_efikamx_leds_device); + imx51_add_gpio_keys(&mx51_efikamx_powerkey_data); + + spi_register_board_info(mx51_efikamx_spi_board_info, + ARRAY_SIZE(mx51_efikamx_spi_board_info)); + imx51_add_ecspi(0, &mx51_efikamx_spi_pdata); + + if (system_rev == 0x11) { + gpio_request(EFIKAMX_RESET1_1, "reset"); + gpio_direction_output(EFIKAMX_RESET1_1, 1); + } else { + gpio_request(EFIKAMX_RESET, "reset"); + gpio_direction_output(EFIKAMX_RESET, 1); + } } static void __init mx51_efikamx_timer_init(void) diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 8ac36d8..344ee8e 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -33,6 +33,7 @@ static struct clk pll1_main_clk; static struct clk pll1_sw_clk; static struct clk pll2_sw_clk; static struct clk pll3_sw_clk; +static struct clk mx53_pll4_sw_clk; static struct clk lp_apm_clk; static struct clk periph_apm_clk; static struct clk ahb_clk; @@ -131,6 +132,8 @@ static inline void __iomem *_get_pll_base(struct clk *pll) return MX51_DPLL2_BASE; else if (pll == &pll3_sw_clk) return MX51_DPLL3_BASE; + else if (pll == &mx53_pll4_sw_clk) + return MX53_DPLL4_BASE; else BUG(); @@ -514,7 +517,10 @@ static int _clk_max_enable(struct clk *clk) /* Handshake with MAX when LPM is entered. */ reg = __raw_readl(MXC_CCM_CLPCR); - reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + if (cpu_is_mx51()) + reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; + else if (cpu_is_mx53()) + reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; __raw_writel(reg, MXC_CCM_CLPCR); return 0; @@ -528,7 +534,10 @@ static void _clk_max_disable(struct clk *clk) /* No Handshake with MAX when LPM is entered as its disabled. */ reg = __raw_readl(MXC_CCM_CLPCR); - reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + if (cpu_is_mx51()) + reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; + else if (cpu_is_mx53()) + reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; __raw_writel(reg, MXC_CCM_CLPCR); } @@ -739,6 +748,14 @@ static struct clk pll3_sw_clk = { .disable = _clk_pll_disable, }; +/* PLL4 SW supplies to LVDS Display Bridge(LDB) */ +static struct clk mx53_pll4_sw_clk = { + .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + /* Low-power Audio Playback Mode clock */ static struct clk lp_apm_clk = { .parent = &osc_clk, @@ -763,6 +780,12 @@ static struct clk ahb_clk = { .round_rate = _clk_ahb_round_rate, }; +static struct clk iim_clk = { + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, +}; + /* Main IP interface clock for access to registers */ static struct clk ipg_clk = { .parent = &ahb_clk, @@ -1053,7 +1076,7 @@ DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, .clk = &c, \ }, -static struct clk_lookup lookups[] = { +static struct clk_lookup mx51_lookups[] = { _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) @@ -1082,6 +1105,16 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) + _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) +}; + +static struct clk_lookup mx53_lookups[] = { + _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) + _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) + _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) + _REGISTER_CLOCK(NULL, "gpt", gpt_clk) + _REGISTER_CLOCK("fec.0", NULL, fec_clk) + _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) }; static void clk_tree_init(void) @@ -1114,14 +1147,18 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, ckih2_reference = ckih2; oscillator_reference = osc; - for (i = 0; i < ARRAY_SIZE(lookups); i++) - clkdev_add(&lookups[i]); + for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++) + clkdev_add(&mx51_lookups[i]); clk_tree_init(); clk_enable(&cpu_clk); clk_enable(&main_bus_clk); + clk_enable(&iim_clk); + mx51_revision(); + clk_disable(&iim_clk); + /* set the usboh3_clk parent to pll2_sw_clk */ clk_set_parent(&usboh3_clk, &pll2_sw_clk); @@ -1138,3 +1175,31 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, MX51_MXC_INT_GPT); return 0; } + +int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2) +{ + int i; + + external_low_reference = ckil; + external_high_reference = ckih1; + ckih2_reference = ckih2; + oscillator_reference = osc; + + for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++) + clkdev_add(&mx53_lookups[i]); + + clk_tree_init(); + + clk_enable(&cpu_clk); + clk_enable(&main_bus_clk); + + clk_enable(&iim_clk); + mx53_revision(); + clk_disable(&iim_clk); + + /* System timer */ + mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), + MX53_INT_GPT); + return 0; +} diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index eaacb6e..d40671d 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -20,37 +20,18 @@ static int cpu_silicon_rev = -1; -#define SI_REV 0x48 +#define IIM_SREV 0x24 -static void query_silicon_parameter(void) +static int get_mx51_srev(void) { - void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE); - u32 rev; + void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); + u32 rev = readl(iim_base + IIM_SREV) & 0xff; - if (!rom) { - cpu_silicon_rev = -EINVAL; - return; - } - - rev = readl(rom + SI_REV); - switch (rev) { - case 0x1: - cpu_silicon_rev = MX51_CHIP_REV_1_0; - break; - case 0x2: - cpu_silicon_rev = MX51_CHIP_REV_1_1; - break; - case 0x10: - cpu_silicon_rev = MX51_CHIP_REV_2_0; - break; - case 0x20: - cpu_silicon_rev = MX51_CHIP_REV_3_0; - break; - default: - cpu_silicon_rev = 0; - } - - iounmap(rom); + if (rev == 0x0) + return IMX_CHIP_REVISION_2_0; + else if (rev == 0x10) + return IMX_CHIP_REVISION_3_0; + return 0; } /* @@ -64,7 +45,7 @@ int mx51_revision(void) return -EINVAL; if (cpu_silicon_rev == -1) - query_silicon_parameter(); + cpu_silicon_rev = get_mx51_srev(); return cpu_silicon_rev; } @@ -79,7 +60,10 @@ EXPORT_SYMBOL(mx51_revision); */ static int __init mx51_neon_fixup(void) { - if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) { + if (!cpu_is_mx51()) + return 0; + + if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) { elf_hwcap &= ~HWCAP_NEON; pr_info("Turning off NEON support, detected broken NEON implementation\n"); } @@ -89,29 +73,65 @@ static int __init mx51_neon_fixup(void) late_initcall(mx51_neon_fixup); #endif +static int get_mx53_srev(void) +{ + void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); + u32 rev = readl(iim_base + IIM_SREV) & 0xff; + + if (rev == 0x0) + return IMX_CHIP_REVISION_1_0; + else if (rev == 0x10) + return IMX_CHIP_REVISION_2_0; + return 0; +} + +/* + * Returns: + * the silicon revision of the cpu + * -EINVAL - not a mx53 + */ +int mx53_revision(void) +{ + if (!cpu_is_mx53()) + return -EINVAL; + + if (cpu_silicon_rev == -1) + cpu_silicon_rev = get_mx53_srev(); + + return cpu_silicon_rev; +} +EXPORT_SYMBOL(mx53_revision); + static int __init post_cpu_init(void) { unsigned int reg; void __iomem *base; - if (!cpu_is_mx51()) - return 0; - - base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); - __raw_writel(0x0, base + 0x40); - __raw_writel(0x0, base + 0x44); - __raw_writel(0x0, base + 0x48); - __raw_writel(0x0, base + 0x4C); - reg = __raw_readl(base + 0x50) & 0x00FFFFFF; - __raw_writel(reg, base + 0x50); - - base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); - __raw_writel(0x0, base + 0x40); - __raw_writel(0x0, base + 0x44); - __raw_writel(0x0, base + 0x48); - __raw_writel(0x0, base + 0x4C); - reg = __raw_readl(base + 0x50) & 0x00FFFFFF; - __raw_writel(reg, base + 0x50); + if (cpu_is_mx51() || cpu_is_mx53()) { + if (cpu_is_mx51()) + base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); + else + base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR); + + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + + if (cpu_is_mx51()) + base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); + else + base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR); + + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + } return 0; } diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index c776b9a..51ff9bb 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -18,6 +18,9 @@ #define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) #define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) +/*MX53*/ +#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) + /* PLL Register Offsets */ #define MXC_PLL_DP_CTL 0x00 #define MXC_PLL_DP_CONFIG 0x04 @@ -380,7 +383,8 @@ /* Define the bits in register CLPCR */ #define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) #define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) -#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) +#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) +#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) #define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h index 8c50cb5..939d2e8 100644 --- a/arch/arm/mach-mx5/devices-imx51.h +++ b/arch/arm/mach-mx5/devices-imx51.h @@ -31,6 +31,11 @@ extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst; #define imx51_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) +extern const struct imx_sdhci_esdhc_imx_data +imx51_sdhci_esdhc_imx_data[] __initconst; +#define imx51_add_sdhci_esdhc_imx(id, pdata) \ + imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata) + extern const struct imx_spi_imx_data imx51_cspi_data __initconst; #define imx51_add_cspi(pdata) \ imx_add_spi_imx(&imx51_cspi_data, pdata) @@ -39,6 +44,6 @@ extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst; #define imx51_add_ecspi(id, pdata) \ imx_add_spi_imx(&imx51_ecspi_data[id], pdata) -extern const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst; -#define imx51_add_esdhc(id, pdata) \ - imx_add_esdhc(&imx51_esdhc_data[id], pdata) +extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data __initconst; +#define imx51_imx2_wdt_data(pdata) \ + imx_add_imx2_wdt_data(&imx51_imx2_wdt_data, pdata) diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 4c7be87..ac55f7f 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -97,21 +97,6 @@ struct platform_device mxc_usbh1_device = { }, }; -static struct resource mxc_wdt_resources[] = { - { - .start = MX51_WDOG_BASE_ADDR, - .end = MX51_WDOG_BASE_ADDR + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_wdt = { - .name = "imx2-wdt", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_wdt_resources), - .resource = mxc_wdt_resources, -}; - static struct resource mxc_kpp_resources[] = { { .start = MX51_MXC_INT_KPP, @@ -160,9 +145,36 @@ static struct mxc_gpio_port mxc_gpio_ports[] = { .irq_high = MX51_MXC_INT_GPIO4_HIGH, .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 }, + { + .chip.label = "gpio-4", + .base = MX53_IO_ADDRESS(MX53_GPIO5_BASE_ADDR), + .irq = MX53_INT_GPIO5_LOW, + .irq_high = MX53_INT_GPIO5_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4 + }, + { + .chip.label = "gpio-5", + .base = MX53_IO_ADDRESS(MX53_GPIO6_BASE_ADDR), + .irq = MX53_INT_GPIO6_LOW, + .irq_high = MX53_INT_GPIO6_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 5 + }, + { + .chip.label = "gpio-6", + .base = MX53_IO_ADDRESS(MX53_GPIO7_BASE_ADDR), + .irq = MX53_INT_GPIO7_LOW, + .irq_high = MX53_INT_GPIO7_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 6 + }, }; int __init imx51_register_gpios(void) { + return mxc_gpio_init(mxc_gpio_ports, 4); +} + +int __init imx53_register_gpios(void) +{ return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); } + diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index af1d07c..ccb7cdc 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h @@ -1,6 +1,5 @@ extern struct platform_device mxc_usbdr_host_device; extern struct platform_device mxc_usbh1_device; extern struct platform_device mxc_usbdr_udc_device; -extern struct platform_device mxc_wdt; extern struct platform_device mxc_hsi2c_device; extern struct platform_device mxc_keypad_device; diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index a2e6e8c..94c293f 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c @@ -33,12 +33,12 @@ #include "devices-imx51.h" #include "devices.h" -#define MBIMX51_TSC2007_GPIO (2*32 + 30) +#define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30) #define MBIMX51_TSC2007_IRQ (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO) -#define MBIMX51_LED0 (2*32 + 5) -#define MBIMX51_LED1 (2*32 + 6) -#define MBIMX51_LED2 (2*32 + 7) -#define MBIMX51_LED3 (2*32 + 8) +#define MBIMX51_LED0 IMX_GPIO_NR(3, 5) +#define MBIMX51_LED1 IMX_GPIO_NR(3, 6) +#define MBIMX51_LED2 IMX_GPIO_NR(3, 7) +#define MBIMX51_LED3 IMX_GPIO_NR(3, 8) static struct gpio_led mbimx51_leds[] = { { @@ -84,7 +84,7 @@ static struct platform_device *devices[] __initdata = { &mbimx51_leds_gpio, }; -static struct pad_desc mbimx51_pads[] = { +static iomux_v3_cfg_t mbimx51_pads[] = { /* UART2 */ MX51_PAD_UART2_RXD__UART2_RXD, MX51_PAD_UART2_TXD__UART2_TXD, @@ -217,6 +217,6 @@ void __init eukrea_mbimx51_baseboard_init(void) i2c_register_board_info(1, mbimx51_i2c_devices, ARRAY_SIZE(mbimx51_i2c_devices)); - imx51_add_esdhc(0, NULL); - imx51_add_esdhc(1, NULL); + imx51_add_sdhci_esdhc_imx(0, NULL); + imx51_add_sdhci_esdhc_imx(1, NULL); } diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c index 2b48f51..c6c2320 100644 --- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c @@ -48,7 +48,7 @@ #define MBIMXSD_GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, \ MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) -static struct pad_desc eukrea_mbimxsd_pads[] = { +static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { /* LED */ MX51_PAD_NANDF_D10__GPIO_3_30, /* SWITCH */ @@ -70,8 +70,8 @@ static struct pad_desc eukrea_mbimxsd_pads[] = { MX51_PAD_SD1_DATA3__SD1_DATA3, }; -#define GPIO_LED1 (2 * 32 + 30) -#define GPIO_SWITCH1 (2 * 32 + 31) +#define GPIO_LED1 IMX_GPIO_NR(3, 30) +#define GPIO_SWITCH1 IMX_GPIO_NR(3, 31) static struct gpio_led eukrea_mbimxsd_leds[] = { { @@ -149,7 +149,7 @@ void __init eukrea_mbimxsd51_baseboard_init(void) imx51_add_imx_uart(1, NULL); imx51_add_imx_uart(2, &uart_pdata); - imx51_add_esdhc(0, NULL); + imx51_add_sdhci_esdhc_imx(0, NULL); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index bc3f30d..e57f968 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -23,33 +23,21 @@ /* * Define the MX51 memory map. */ -static struct map_desc mxc_io_desc[] __initdata = { - { - .virtual = MX51_IRAM_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR), - .length = MX51_IRAM_SIZE, - .type = MT_DEVICE - }, { - .virtual = MX51_DEBUG_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR), - .length = MX51_DEBUG_SIZE, - .type = MT_DEVICE - }, { - .virtual = MX51_AIPS1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR), - .length = MX51_AIPS1_SIZE, - .type = MT_DEVICE - }, { - .virtual = MX51_SPBA0_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR), - .length = MX51_SPBA0_SIZE, - .type = MT_DEVICE - }, { - .virtual = MX51_AIPS2_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR), - .length = MX51_AIPS2_SIZE, - .type = MT_DEVICE - }, +static struct map_desc mx51_io_desc[] __initdata = { + imx_map_entry(MX51, IRAM, MT_DEVICE), + imx_map_entry(MX51, DEBUG, MT_DEVICE), + imx_map_entry(MX51, AIPS1, MT_DEVICE), + imx_map_entry(MX51, SPBA0, MT_DEVICE), + imx_map_entry(MX51, AIPS2, MT_DEVICE), +}; + +/* + * Define the MX53 memory map. + */ +static struct map_desc mx53_io_desc[] __initdata = { + imx_map_entry(MX53, AIPS1, MT_DEVICE), + imx_map_entry(MX53, SPBA0, MT_DEVICE), + imx_map_entry(MX53, AIPS2, MT_DEVICE), }; /* @@ -62,7 +50,15 @@ void __init mx51_map_io(void) mxc_set_cpu_type(MXC_CPU_MX51); mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR)); - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); + iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); +} + +void __init mx53_map_io(void) +{ + mxc_set_cpu_type(MXC_CPU_MX53); + mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); + mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR)); + iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); } int imx51_register_gpios(void); @@ -72,7 +68,7 @@ void __init mx51_init_irq(void) unsigned long tzic_addr; void __iomem *tzic_virt; - if (mx51_revision() < MX51_CHIP_REV_2_0) + if (mx51_revision() < IMX_CHIP_REVISION_2_0) tzic_addr = MX51_TZIC_BASE_ADDR_TO1; else tzic_addr = MX51_TZIC_BASE_ADDR; @@ -84,3 +80,20 @@ void __init mx51_init_irq(void) tzic_init_irq(tzic_virt); imx51_register_gpios(); } + +int imx53_register_gpios(void); + +void __init mx53_init_irq(void) +{ + unsigned long tzic_addr; + void __iomem *tzic_virt; + + tzic_addr = MX53_TZIC_BASE_ADDR; + + tzic_virt = ioremap(tzic_addr, SZ_16K); + if (!tzic_virt) + panic("unable to map TZIC interrupt controller\n"); + + tzic_init_irq(tzic_virt); + imx53_register_gpios(); +} diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c index aeccfd75..7652c30 100644 --- a/arch/arm/mach-mxc91231/mm.c +++ b/arch/arm/mach-mxc91231/mm.c @@ -27,48 +27,15 @@ /* * This structure defines the MXC memory map. */ -static struct map_desc mxc_io_desc[] __initdata = { - { - .virtual = MXC91231_L2CC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_L2CC_BASE_ADDR), - .length = MXC91231_L2CC_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_X_MEMC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_X_MEMC_BASE_ADDR), - .length = MXC91231_X_MEMC_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_ROMP_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_ROMP_BASE_ADDR), - .length = MXC91231_ROMP_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_AVIC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_AVIC_BASE_ADDR), - .length = MXC91231_AVIC_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_AIPS1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_AIPS1_BASE_ADDR), - .length = MXC91231_AIPS1_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_SPBA0_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_SPBA0_BASE_ADDR), - .length = MXC91231_SPBA0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_SPBA1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_SPBA1_BASE_ADDR), - .length = MXC91231_SPBA1_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_AIPS2_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_AIPS2_BASE_ADDR), - .length = MXC91231_AIPS2_SIZE, - .type = MT_DEVICE, - }, +static struct map_desc mxc91231_io_desc[] __initdata = { + imx_map_entry(MXC91231, L2CC, MT_DEVICE), + imx_map_entry(MXC91231, X_MEMC, MT_DEVICE), + imx_map_entry(MXC91231, ROMP, MT_DEVICE), + imx_map_entry(MXC91231, AVIC, MT_DEVICE), + imx_map_entry(MXC91231, AIPS1, MT_DEVICE), + imx_map_entry(MXC91231, SPBA0, MT_DEVICE), + imx_map_entry(MXC91231, SPBA1, MT_DEVICE), + imx_map_entry(MXC91231, AIPS2, MT_DEVICE), }; /* @@ -80,7 +47,7 @@ void __init mxc91231_map_io(void) { mxc_set_cpu_type(MXC_CPU_MXC91231); - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); + iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc)); } int mxc91231_register_gpios(void); diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 64e3a64..389f217 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -21,10 +21,6 @@ config ARCH_MX2 config ARCH_MX25 bool "MX25-based" - select CPU_ARM926T - select ARCH_MXC_IOMUX_V3 - select HAVE_FB_IMX - select ARCH_MXC_AUDMUX_V2 help This enables support for systems based on the Freescale i.MX25 family @@ -51,7 +47,6 @@ endchoice source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-mx3/Kconfig" -source "arch/arm/mach-mx25/Kconfig" source "arch/arm/mach-mxc91231/Kconfig" source "arch/arm/mach-mx5/Kconfig" @@ -68,12 +63,10 @@ config MXC_IRQ_PRIOR Say N here, unless you have a specialized requirement. config MXC_TZIC - bool "Enable TrustZone Interrupt Controller" - depends on ARCH_MX51 - help - This will be automatically selected for all processors - containing this interrupt controller. - Say N here only if you are really sure. + bool + +config MXC_AVIC + bool config MXC_PWM tristate "Enable PWM driver" diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 3726709..989cb59 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -3,10 +3,11 @@ # # Common support -obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o +obj-y := clock.o gpio.o time.o devices.o cpu.o system.o -# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) +# MX51 uses the TZIC interrupt controller, older platforms use AVIC obj-$(CONFIG_MXC_TZIC) += tzic.o +obj-$(CONFIG_MXC_AVIC) += avic.o obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 0be1ac7..175e364 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -209,7 +209,7 @@ static int mxc_audmux_v2_init(void) audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); } #endif -#if defined(CONFIG_ARCH_MX25) +#if defined(CONFIG_SOC_IMX25) if (cpu_is_mx25()) { audmux_clk = clk_get(NULL, "audmux"); if (IS_ERR(audmux_clk)) { @@ -220,7 +220,7 @@ static int mxc_audmux_v2_init(void) } audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); } -#endif +#endif /* if defined(CONFIG_SOC_IMX25) */ audmux_debugfs_init(); return 0; diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/avic.c index 7331f2a..7331f2a 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/avic.c diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index 735776d..e9bcefe 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c @@ -17,6 +17,7 @@ */ #include <linux/kernel.h> +#include <linux/slab.h> #include <linux/init.h> #include <linux/err.h> #include <linux/platform_device.h> @@ -36,9 +37,10 @@ int __init mxc_register_device(struct platform_device *pdev, void *data) return ret; } -struct platform_device *__init imx_add_platform_device(const char *name, int id, +struct platform_device *__init imx_add_platform_device_dmamask( + const char *name, int id, const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data) + const void *data, size_t size_data, u64 dmamask) { int ret = -ENOMEM; struct platform_device *pdev; @@ -47,6 +49,23 @@ struct platform_device *__init imx_add_platform_device(const char *name, int id, if (!pdev) goto err; + if (dmamask) { + /* + * This memory isn't freed when the device is put, + * I don't have a nice idea for that though. Conceptually + * dma_mask in struct device should not be a pointer. + * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 + */ + pdev->dev.dma_mask = + kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); + if (!pdev->dev.dma_mask) + /* ret is still -ENOMEM; */ + goto err; + + *pdev->dev.dma_mask = dmamask; + pdev->dev.coherent_dma_mask = dmamask; + } + if (res) { ret = platform_device_add_resources(pdev, res, num_resources); if (ret) diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 9aa6f3e..2537166 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -1,29 +1,73 @@ -config IMX_HAVE_PLATFORM_ESDHC - bool - config IMX_HAVE_PLATFORM_FEC bool - default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51 + default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 config IMX_HAVE_PLATFORM_FLEXCAN select HAVE_CAN_FLEXCAN if CAN bool +config IMX_HAVE_PLATFORM_FSL_USB2_UDC + bool + config IMX_HAVE_PLATFORM_GPIO_KEYS bool - default y if ARCH_MX51 + default y if SOC_IMX51 + +config IMX_HAVE_PLATFORM_IMX21_HCD + bool +config IMX_HAVE_PLATFORM_IMX2_WDT + bool + +config IMX_HAVE_PLATFORM_IMXDI_RTC + bool + +config IMX_HAVE_PLATFORM_IMX_FB + bool + select HAVE_FB_IMX + config IMX_HAVE_PLATFORM_IMX_I2C bool +config IMX_HAVE_PLATFORM_IMX_KEYPAD + bool + config IMX_HAVE_PLATFORM_IMX_SSI bool config IMX_HAVE_PLATFORM_IMX_UART bool +config IMX_HAVE_PLATFORM_IMX_UDC + bool + +config IMX_HAVE_PLATFORM_MX1_CAMERA + bool + +config IMX_HAVE_PLATFORM_MX2_CAMERA + bool + +config IMX_HAVE_PLATFORM_MXC_EHCI + bool + +config IMX_HAVE_PLATFORM_MXC_MMC + bool + config IMX_HAVE_PLATFORM_MXC_NAND bool +config IMX_HAVE_PLATFORM_MXC_PWM + bool + +config IMX_HAVE_PLATFORM_MXC_RNGA + bool + select ARCH_HAS_RNGA + +config IMX_HAVE_PLATFORM_MXC_W1 + bool + +config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + bool + config IMX_HAVE_PLATFORM_SPI_IMX bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 45aefeb..75cd2ec 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -1,10 +1,24 @@ -obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o obj-y += platform-imx-dma.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c deleted file mode 100644 index 2605bfa..0000000 --- a/arch/arm/plat-mxc/devices/platform-esdhc.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include <mach/hardware.h> -#include <mach/devices-common.h> -#include <mach/esdhc.h> - -#define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \ - { \ - .id = _id, \ - .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ - .irq = soc ## _INT_ESDHC ## hwid, \ - } - -#define imx_esdhc_imx_data_entry(soc, id, hwid) \ - [id] = imx_esdhc_imx_data_entry_single(soc, id, hwid) - -#ifdef CONFIG_ARCH_MX25 -const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = { -#define imx25_esdhc_data_entry(_id, _hwid) \ - imx_esdhc_imx_data_entry(MX25, _id, _hwid) - imx25_esdhc_data_entry(0, 1), - imx25_esdhc_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_ARCH_MX25 */ - -#ifdef CONFIG_ARCH_MX35 -const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = { -#define imx35_esdhc_data_entry(_id, _hwid) \ - imx_esdhc_imx_data_entry(MX35, _id, _hwid) - imx35_esdhc_data_entry(0, 1), - imx35_esdhc_data_entry(1, 2), - imx35_esdhc_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_ARCH_MX35 */ - -#ifdef CONFIG_ARCH_MX51 -const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = { -#define imx51_esdhc_data_entry(_id, _hwid) \ - imx_esdhc_imx_data_entry(MX51, _id, _hwid) - imx51_esdhc_data_entry(0, 1), - imx51_esdhc_data_entry(1, 2), - imx51_esdhc_data_entry(2, 3), - imx51_esdhc_data_entry(3, 4), -}; -#endif /* ifdef CONFIG_ARCH_MX51 */ - -struct platform_device *__init imx_add_esdhc( - const struct imx_esdhc_imx_data *data, - const struct esdhc_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("sdhci-esdhc-imx", data->id, res, - ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index 11d087f..269ec78 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c @@ -16,22 +16,22 @@ .irq = soc ## _INT_FEC, \ } -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_fec_data imx25_fec_data __initconst = imx_fec_data_entry_single(MX25); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_fec_data imx27_fec_data __initconst = imx_fec_data_entry_single(MX27); #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_fec_data imx35_fec_data __initconst = imx_fec_data_entry_single(MX35); #endif -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_fec_data imx51_fec_data __initconst = imx_fec_data_entry_single(MX51); #endif diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c index 5e97a01..4e8497a 100644 --- a/arch/arm/plat-mxc/devices/platform-flexcan.c +++ b/arch/arm/plat-mxc/devices/platform-flexcan.c @@ -5,26 +5,54 @@ * the terms of the GNU General Public License version 2 as published by the * Free Software Foundation. */ - +#include <mach/hardware.h> #include <mach/devices-common.h> -struct platform_device *__init imx_add_flexcan(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, +#define imx_flexcan_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_CAN ## _hwid, \ + } + +#define imx_flexcan_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX25 +const struct imx_flexcan_data imx25_flexcan_data[] __initconst = { +#define imx25_flexcan_data_entry(_id, _hwid) \ + imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_flexcan_data_entry(0, 1), + imx25_flexcan_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_flexcan_data imx35_flexcan_data[] __initconst = { +#define imx35_flexcan_data_entry(_id, _hwid) \ + imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K) + imx35_flexcan_data_entry(0, 1), + imx35_flexcan_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_flexcan( + const struct imx_flexcan_data *data, const struct flexcan_platform_data *pdata) { struct resource res[] = { { - .start = iobase, - .end = iobase + iosize - 1, + .start = data->iobase, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = irq, - .end = irq, + .start = data->irq, + .end = data->irq, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); + return imx_add_platform_device("flexcan", data->id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); } diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c new file mode 100644 index 0000000..59c33f6 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_fsl_usb2_udc_data_entry_single(soc) \ + { \ + .iobase = soc ## _USB_OTG_BASE_ADDR, \ + .irq = soc ## _INT_USB_OTG, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX25); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX35); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_fsl_usb2_udc( + const struct imx_fsl_usb2_udc_data *data, + const struct fsl_usb2_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("fsl-usb2-udc", -1, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index 3a705c7..33530d2 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c @@ -31,25 +31,25 @@ struct imx_imx_sdma_data { }, \ } -#ifdef CONFIG_ARCH_MX25 -const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = +#ifdef CONFIG_SOC_IMX25 +struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0); -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0); -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 -const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = +#ifdef CONFIG_SOC_IMX51 +struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0); -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ static struct platform_device __init __maybe_unused *imx_add_imx_sdma( const struct imx_imx_sdma_data *data) @@ -76,6 +76,83 @@ static struct platform_device __init __maybe_unused *imx_add_imx_dma(void) return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0); } +#ifdef CONFIG_ARCH_MX25 +static struct sdma_script_start_addrs addr_imx25_to1 = { + .ap_2_ap_addr = 729, + .uart_2_mcu_addr = 904, + .per_2_app_addr = 1255, + .mcu_2_app_addr = 834, + .uartsh_2_mcu_addr = 1120, + .per_2_shp_addr = 1329, + .mcu_2_shp_addr = 1048, + .ata_2_mcu_addr = 1560, + .mcu_2_ata_addr = 1479, + .app_2_per_addr = 1189, + .app_2_mcu_addr = 770, + .shp_2_per_addr = 1407, + .shp_2_mcu_addr = 979, +}; +#endif + +#ifdef CONFIG_ARCH_MX31 +static struct sdma_script_start_addrs addr_imx31_to1 = { + .per_2_per_addr = 1677, +}; + +static struct sdma_script_start_addrs addr_imx31_to2 = { + .ap_2_ap_addr = 423, + .ap_2_bp_addr = 829, + .bp_2_ap_addr = 1029, +}; +#endif + +#ifdef CONFIG_ARCH_MX35 +static struct sdma_script_start_addrs addr_imx35_to1 = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .uartsh_2_mcu_addr = 1183, + .per_2_shp_addr = 1033, + .mcu_2_shp_addr = 961, + .ata_2_mcu_addr = 1333, + .mcu_2_ata_addr = 1252, + .app_2_mcu_addr = 683, + .shp_2_per_addr = 1111, + .shp_2_mcu_addr = 892, +}; + +static struct sdma_script_start_addrs addr_imx35_to2 = { + .ap_2_ap_addr = 729, + .uart_2_mcu_addr = 904, + .per_2_app_addr = 1597, + .mcu_2_app_addr = 834, + .uartsh_2_mcu_addr = 1270, + .per_2_shp_addr = 1120, + .mcu_2_shp_addr = 1048, + .ata_2_mcu_addr = 1429, + .mcu_2_ata_addr = 1339, + .app_2_per_addr = 1531, + .app_2_mcu_addr = 770, + .shp_2_per_addr = 1198, + .shp_2_mcu_addr = 979, +}; +#endif + +#ifdef CONFIG_SOC_IMX51 +static struct sdma_script_start_addrs addr_imx51_to1 = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .mcu_2_shp_addr = 961, + .ata_2_mcu_addr = 1473, + .mcu_2_ata_addr = 1392, + .app_2_per_addr = 1033, + .app_2_mcu_addr = 683, + .shp_2_per_addr = 1251, + .shp_2_mcu_addr = 892, +}; +#endif + static int __init imxXX_add_imx_dma(void) { struct platform_device *ret; @@ -86,30 +163,42 @@ static int __init imxXX_add_imx_dma(void) else #endif -#if defined(CONFIG_ARCH_MX25) - if (cpu_is_mx25()) +#if defined(CONFIG_SOC_IMX25) + if (cpu_is_mx25()) { + imx25_imx_sdma_data.pdata.script_addrs = &addr_imx25_to1; ret = imx_add_imx_sdma(&imx25_imx_sdma_data); - else + } else #endif -#if defined(CONFIG_ARCH_MX31) +#if defined(CONFIG_SOC_IMX31) if (cpu_is_mx31()) { - imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4; + int to_version = mx31_revision() >> 4; + imx31_imx_sdma_data.pdata.to_version = to_version; + if (to_version == 1) + imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to1; + else + imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to2; ret = imx_add_imx_sdma(&imx31_imx_sdma_data); } else #endif -#if defined(CONFIG_ARCH_MX35) +#if defined(CONFIG_SOC_IMX35) if (cpu_is_mx35()) { - imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4; + int to_version = mx35_revision() >> 4; + imx35_imx_sdma_data.pdata.to_version = to_version; + if (to_version == 1) + imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to1; + else + imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to2; ret = imx_add_imx_sdma(&imx35_imx_sdma_data); } else #endif #if defined(CONFIG_ARCH_MX51) - if (cpu_is_mx51()) + if (cpu_is_mx51()) { + imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1; ret = imx_add_imx_sdma(&imx51_imx_sdma_data); - else + } else #endif ret = ERR_PTR(-ENODEV); diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c new file mode 100644 index 0000000..6100a7d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_fb_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _LCDC_BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_LCDC, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_fb_data imx21_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX21, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx_fb_data imx25_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX25, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_fb_data imx27_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX27, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_imx_fb( + const struct imx_imx_fb_data *data, + const struct imx_fb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("imx-fb", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index 6795884..72ba880 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -30,7 +30,7 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { #define imx25_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K) @@ -38,7 +38,7 @@ const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { imx25_imx_i2c_data_entry(1, 2), imx25_imx_i2c_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { @@ -49,7 +49,7 @@ const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { #define imx31_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K) @@ -57,9 +57,9 @@ const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { imx31_imx_i2c_data_entry(1, 2), imx31_imx_i2c_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { #define imx35_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) @@ -67,16 +67,16 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { imx35_imx_i2c_data_entry(1, 2), imx35_imx_i2c_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { #define imx51_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K) imx51_imx_i2c_data_entry(0, 1), imx51_imx_i2c_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ struct platform_device *__init imx_add_imx_i2c( const struct imx_imx_i2c_data *data, diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c new file mode 100644 index 0000000..40238f0 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_keypad_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _KPP_BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_KPP, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX21, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX25, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX27, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX31, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX35, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_imx_keypad( + const struct imx_imx_keypad_data *data, + const struct matrix_keymap_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-keypad", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c index 38a7a0b..ac3d572 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c @@ -30,14 +30,14 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { #define imx25_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) imx25_imx_ssi_data_entry(0, 1), imx25_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { @@ -48,32 +48,32 @@ const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { #define imx31_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) imx31_imx_ssi_data_entry(0, 1), imx31_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { #define imx35_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) imx35_imx_ssi_data_entry(0, 1), imx35_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { #define imx51_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) imx51_imx_ssi_data_entry(0, 1), imx51_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ struct platform_device *__init imx_add_imx_ssi( const struct imx_imx_ssi_data *data, diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index 2039640..7b45b78 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -47,7 +47,7 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { }; #endif -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { #define imx25_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) @@ -57,7 +57,7 @@ const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { imx25_imx_uart_data_entry(3, 4), imx25_imx_uart_data_entry(4, 5), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { @@ -72,7 +72,7 @@ const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { #define imx31_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) @@ -82,9 +82,9 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { imx31_imx_uart_data_entry(3, 4), imx31_imx_uart_data_entry(4, 5), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { #define imx35_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) @@ -92,9 +92,9 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { imx35_imx_uart_data_entry(1, 2), imx35_imx_uart_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { #define imx51_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K) @@ -102,7 +102,7 @@ const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { imx51_imx_uart_data_entry(1, 2), imx51_imx_uart_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ struct platform_device *__init imx_add_imx_uart_3irq( const struct imx_imx_uart_3irq_data *data, diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c new file mode 100644 index 0000000..8dc19f6 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx2_wdt_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _WDOG_BASE_ADDR, \ + .iosize = _size, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX21, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX25, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX27, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX31, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX35, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_imx2_wdt_data imx51_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX51, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX51 */ + +struct platform_device *__init imx_add_imx2_wdt( + const struct imx_imx2_wdt_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, + }; + return imx_add_platform_device("imx2-wdt", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx21-hcd.c b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c new file mode 100644 index 0000000..5770a42 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx21_hcd_data_entry_single(soc) \ + { \ + .iobase = soc ## _USBOTG_BASE_ADDR, \ + .irq = soc ## _INT_USBHOST, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst = + imx_imx21_hcd_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +struct platform_device *__init imx_add_imx21_hcd( + const struct imx_imx21_hcd_data *data, + const struct mx21_usbh_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("imx21-hcd", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx_udc.c b/arch/arm/plat-mxc/devices/platform-imx_udc.c new file mode 100644 index 0000000..6fd675d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_udc.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_udc_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _USBD_BASE_ADDR, \ + .iosize = _size, \ + .irq0 = soc ## _INT_USBD0, \ + .irq1 = soc ## _INT_USBD1, \ + .irq2 = soc ## _INT_USBD2, \ + .irq3 = soc ## _INT_USBD3, \ + .irq4 = soc ## _INT_USBD4, \ + .irq5 = soc ## _INT_USBD5, \ + .irq6 = soc ## _INT_USBD6, \ + } + +#define imx_imx_udc_data_entry(soc, _size) \ + [_id] = imx_imx_udc_data_entry_single(soc, _size) + +#ifdef CONFIG_SOC_IMX1 +const struct imx_imx_udc_data imx1_imx_udc_data __initconst = + imx_imx_udc_data_entry_single(MX1, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX1 */ + +struct platform_device *__init imx_add_imx_udc( + const struct imx_imx_udc_data *data, + const struct imxusb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq0, + .end = data->irq0, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq1, + .end = data->irq1, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq2, + .end = data->irq2, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq3, + .end = data->irq3, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq4, + .end = data->irq4, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq5, + .end = data->irq5, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq6, + .end = data->irq6, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx_udc", 0, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c new file mode 100644 index 0000000..10653cc --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imxdi_rtc_data_entry_single(soc) \ + { \ + .iobase = soc ## _DRYICE_BASE_ADDR, \ + .irq = soc ## _INT_DRYICE, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst = + imx_imxdi_rtc_data_entry_single(MX25); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +struct platform_device *__init imx_add_imxdi_rtc( + const struct imx_imxdi_rtc_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imxdi_rtc", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-mx1-camera.c b/arch/arm/plat-mxc/devices/platform-mx1-camera.c new file mode 100644 index 0000000..edcc581 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx1-camera.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mx1_camera_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _CSI ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_CSI, \ + } + +#ifdef CONFIG_SOC_IMX1 +const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst = + imx_mx1_camera_data_entry_single(MX1, 10); +#endif /* ifdef CONFIG_SOC_IMX1 */ + +struct platform_device *__init imx_add_mx1_camera( + const struct imx_mx1_camera_data *data, + const struct mx1_camera_pdata *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mx1-camera", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/plat-mxc/devices/platform-mx2-camera.c new file mode 100644 index 0000000..b3f4828 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx2-camera.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mx2_camera_data_entry_single(soc) \ + { \ + .iobasecsi = soc ## _CSI_BASE_ADDR, \ + .iosizecsi = SZ_4K, \ + .irqcsi = soc ## _INT_CSI, \ + } +#define imx_mx2_camera_data_entry_single_emma(soc) \ + { \ + .iobasecsi = soc ## _CSI_BASE_ADDR, \ + .iosizecsi = SZ_32, \ + .irqcsi = soc ## _INT_CSI, \ + .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \ + .iosizeemmaprp = SZ_32, \ + .irqemmaprp = soc ## _INT_EMMAPRP, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst = + imx_mx2_camera_data_entry_single(MX25); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst = + imx_mx2_camera_data_entry_single_emma(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_mx2_camera( + const struct imx_mx2_camera_data *data, + const struct mx2_camera_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobasecsi, + .end = data->iobasecsi + data->iosizecsi - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irqcsi, + .end = data->irqcsi, + .flags = IORESOURCE_IRQ, + }, { + .start = data->iobaseemmaprp, + .end = data->iobaseemmaprp + data->iosizeemmaprp - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irqemmaprp, + .end = data->irqemmaprp, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mx2-camera", 0, + res, data->iobaseemmaprp ? 4 : 2, + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c new file mode 100644 index 0000000..cc488f4 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_ehci_data_entry_single(soc, _id, hs) \ + { \ + .id = _id, \ + .iobase = soc ## _USB_ ## hs ## _BASE_ADDR, \ + .irq = soc ## _INT_USB_ ## hs, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX25, 0, OTG); +const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst = + imx_mxc_ehci_data_entry_single(MX25, 1, HS); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX27, 0, OTG); +const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX27, 1, HS1), + imx_mxc_ehci_data_entry_single(MX27, 2, HS2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX31, 0, OTG); +const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX31, 1, HS1), + imx_mxc_ehci_data_entry_single(MX31, 2, HS2), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX35, 0, OTG); +const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst = + imx_mxc_ehci_data_entry_single(MX35, 1, HS); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_mxc_ehci( + const struct imx_mxc_ehci_data *data, + const struct mxc_usbh_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mxc-ehci", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c new file mode 100644 index 0000000..90d762f --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_SDHC ## _hwid, \ + .dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \ + } +#define imx_mxc_mmc_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = { +#define imx21_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX21, _id, _hwid, SZ_4K) + imx21_mxc_mmc_data_entry(0, 1), + imx21_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = { +#define imx27_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX27, _id, _hwid, SZ_4K) + imx27_mxc_mmc_data_entry(0, 1), + imx27_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = { +#define imx31_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX31, _id, _hwid, SZ_16K) + imx31_mxc_mmc_data_entry(0, 1), + imx31_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + +struct platform_device *__init imx_add_mxc_mmc( + const struct imx_mxc_mmc_data *data, + const struct imxmmc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, { + .start = data->dmareq, + .end = data->dmareq, + .flags = IORESOURCE_DMA, + }, + }; + return imx_add_platform_device_dmamask("mxc-mmc", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c index 3fdcc32..1568f39 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -31,27 +31,27 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX21, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX25, SZ_8K); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX27, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX31, SZ_4K); #endif -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX35, SZ_8K); #endif -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst = imx_mxc_nandv3_data_entry_single(MX51, SZ_16K); #endif diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c new file mode 100644 index 0000000..3d8ebdb --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_PWM ## _hwid, \ + } +#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst = + imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = { +#define imx25_mxc_pwm_data_entry(_id, _hwid) \ + imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_mxc_pwm_data_entry(0, 1), + imx25_mxc_pwm_data_entry(1, 2), + imx25_mxc_pwm_data_entry(2, 3), + imx25_mxc_pwm_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst = + imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_mxc_pwm( + const struct imx_mxc_pwm_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_pwm", data->id, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rnga.c b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c new file mode 100644 index 0000000..b4b7612 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +struct imx_mxc_rnga_data { + resource_size_t iobase; +}; + +#define imx_mxc_rnga_data_entry_single(soc) \ + { \ + .iobase = soc ## _RNGA_BASE_ADDR, \ + } + +#ifdef CONFIG_SOC_IMX31 +static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst = + imx_mxc_rnga_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +static struct platform_device *__init imx_add_mxc_rnga( + const struct imx_mxc_rnga_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + }; + return imx_add_platform_device("mxc_rnga", -1, + res, ARRAY_SIZE(res), NULL, 0); +} + +static int __init imxXX_add_mxc_rnga(void) +{ + struct platform_device *ret; + +#if defined(CONFIG_SOC_IMX31) + if (cpu_is_mx31()) + ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data); + else +#endif /* if defined(CONFIG_SOC_IMX31) */ + ret = ERR_PTR(-ENODEV); + + if (IS_ERR(ret)) + return PTR_ERR(ret); + + return 0; +} +arch_initcall(imxXX_add_mxc_rnga); diff --git a/arch/arm/plat-mxc/devices/platform-mxc_w1.c b/arch/arm/plat-mxc/devices/platform-mxc_w1.c new file mode 100644 index 0000000..96fa5ea --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_w1.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_w1_data_entry_single(soc) \ + { \ + .iobase = soc ## _OWIRE_BASE_ADDR, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX35); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_mxc_w1( + const struct imx_mxc_w1_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return imx_add_platform_device("mxc_w1", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c new file mode 100644 index 0000000..b352564 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> +#include <mach/esdhc.h> + +#define imx_sdhci_esdhc_imx_data_entry_single(soc, _id, hwid) \ + { \ + .id = _id, \ + .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ + .irq = soc ## _INT_ESDHC ## hwid, \ + } + +#define imx_sdhci_esdhc_imx_data_entry(soc, id, hwid) \ + [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, id, hwid) + +#ifdef CONFIG_SOC_IMX25 +const struct imx_sdhci_esdhc_imx_data +imx25_sdhci_esdhc_imx_data[] __initconst = { +#define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX25, _id, _hwid) + imx25_sdhci_esdhc_imx_data_entry(0, 1), + imx25_sdhci_esdhc_imx_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_sdhci_esdhc_imx_data +imx35_sdhci_esdhc_imx_data[] __initconst = { +#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX35, _id, _hwid) + imx35_sdhci_esdhc_imx_data_entry(0, 1), + imx35_sdhci_esdhc_imx_data_entry(1, 2), + imx35_sdhci_esdhc_imx_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_sdhci_esdhc_imx_data +imx51_sdhci_esdhc_imx_data[] __initconst = { +#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX51, _id, _hwid) + imx51_sdhci_esdhc_imx_data_entry(0, 1), + imx51_sdhci_esdhc_imx_data_entry(1, 2), + imx51_sdhci_esdhc_imx_data_entry(2, 3), + imx51_sdhci_esdhc_imx_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + +struct platform_device *__init imx_add_sdhci_esdhc_imx( + const struct imx_sdhci_esdhc_imx_data *data, + const struct esdhc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("sdhci-esdhc-imx", data->id, res, + ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index 17f724c..8ea49ad 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -30,7 +30,7 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { }; #endif -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { #define imx25_cspi_data_entry(_id, _hwid) \ imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K) @@ -38,7 +38,7 @@ const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { imx25_cspi_data_entry(1, 2), imx25_cspi_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { @@ -50,7 +50,7 @@ const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { #define imx31_cspi_data_entry(_id, _hwid) \ imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) @@ -58,18 +58,18 @@ const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { imx31_cspi_data_entry(1, 2), imx31_cspi_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { #define imx35_cspi_data_entry(_id, _hwid) \ imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) imx35_cspi_data_entry(0, 1), imx35_cspi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_spi_imx_data imx51_cspi_data __initconst = imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K); @@ -79,7 +79,7 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = { imx51_ecspi_data_entry(0, 1), imx51_ecspi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ struct platform_device *__init imx_add_spi_imx( const struct imx_spi_imx_data *data, diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 9915607..c1a7146 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -69,9 +69,9 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) { unsigned int v; -#if defined(CONFIG_ARCH_MX25) +#if defined(CONFIG_SOC_IMX25) if (cpu_is_mx25()) { - v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -108,14 +108,14 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return -EINVAL; } - writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } -#endif /* CONFIG_ARCH_MX25 */ +#endif /* if defined(CONFIG_SOC_IMX25) */ #if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) { - v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + + v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -153,13 +153,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return -EINVAL; } - writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + + writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } if (cpu_is_mx35()) { - v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -196,7 +196,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return -EINVAL; } - writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } @@ -206,7 +206,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) /* On i.MX27 we can use the i.MX31 USBCTRL bits, they * are identical */ - v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { case 0: /* OTG port */ @@ -241,12 +241,12 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) default: return -EINVAL; } - writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } #endif /* CONFIG_MACH_MX27 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 if (cpu_is_mx51()) { void __iomem *usb_base; void __iomem *usbotg_base; diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 9c3e362..93a8d93 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) { u32 irq_stat; - struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); + struct mxc_gpio_port *port = get_irq_data(irq); irq_stat = __raw_readl(port->base + GPIO_ISR) & __raw_readl(port->base + GPIO_IMR); @@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) { int i; u32 irq_msk, irq_stat; - struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); + struct mxc_gpio_port *port = get_irq_data(irq); /* walk through all interrupt status registers */ for (i = 0; i < gpio_table_size; i++) { @@ -349,3 +349,96 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) return 0; } + +#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \ + { \ + .chip.label = "gpio-" #_id, \ + .irq = _irq, \ + .base = soc ## _IO_ADDRESS( \ + soc ## _GPIO ## _hwid ## _BASE_ADDR), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \ + } + +#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \ + DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0) + +#define DEFINE_REGISTER_FUNCTION(prefix) \ +int __init prefix ## _register_gpios(void) \ +{ \ + return mxc_gpio_init(prefix ## _gpio_ports, \ + ARRAY_SIZE(prefix ## _gpio_ports)); \ +} + +#if defined(CONFIG_SOC_IMX1) +static struct mxc_gpio_port imx1_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD), +}; + +DEFINE_REGISTER_FUNCTION(imx1) + +#endif /* if defined(CONFIG_SOC_IMX1) */ + +#if defined(CONFIG_SOC_IMX21) +static struct mxc_gpio_port imx21_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO), + DEFINE_IMX_GPIO_PORT(MX21, 1, 2), + DEFINE_IMX_GPIO_PORT(MX21, 2, 3), + DEFINE_IMX_GPIO_PORT(MX21, 3, 4), + DEFINE_IMX_GPIO_PORT(MX21, 4, 5), + DEFINE_IMX_GPIO_PORT(MX21, 5, 6), +}; + +DEFINE_REGISTER_FUNCTION(imx21) + +#endif /* if defined(CONFIG_SOC_IMX21) */ + +#if defined(CONFIG_SOC_IMX25) +static struct mxc_gpio_port imx25_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4), +}; + +DEFINE_REGISTER_FUNCTION(imx25) + +#endif /* if defined(CONFIG_SOC_IMX25) */ + +#if defined(CONFIG_SOC_IMX27) +static struct mxc_gpio_port imx27_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO), + DEFINE_IMX_GPIO_PORT(MX27, 1, 2), + DEFINE_IMX_GPIO_PORT(MX27, 2, 3), + DEFINE_IMX_GPIO_PORT(MX27, 3, 4), + DEFINE_IMX_GPIO_PORT(MX27, 4, 5), + DEFINE_IMX_GPIO_PORT(MX27, 5, 6), +}; + +DEFINE_REGISTER_FUNCTION(imx27) + +#endif /* if defined(CONFIG_SOC_IMX27) */ + +#if defined(CONFIG_SOC_IMX31) +static struct mxc_gpio_port imx31_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3), +}; + +DEFINE_REGISTER_FUNCTION(imx31) + +#endif /* if defined(CONFIG_SOC_IMX31) */ + +#if defined(CONFIG_SOC_IMX35) +static struct mxc_gpio_port imx35_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3), +}; + +DEFINE_REGISTER_FUNCTION(imx35) + +#endif /* if defined(CONFIG_SOC_IMX35) */ diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 7a1e1f8..9d58ce5 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -21,6 +21,7 @@ extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); extern void mx51_map_io(void); +extern void mx53_map_io(void); extern void mxc91231_map_io(void); extern void mxc_init_irq(void __iomem *); extern void tzic_init_irq(void __iomem *); @@ -31,6 +32,7 @@ extern void mx27_init_irq(void); extern void mx31_init_irq(void); extern void mx35_init_irq(void); extern void mx51_init_irq(void); +extern void mx53_init_irq(void); extern void mxc91231_init_irq(void); extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); @@ -42,6 +44,8 @@ extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); +extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2); extern int mxc91231_clocks_init(unsigned long fref); extern int mxc_register_gpios(void); extern int mxc_register_device(struct platform_device *pdev, void *data); @@ -50,5 +54,6 @@ extern void mxc_arch_reset_init(void __iomem *); extern void mxc91231_power_off(void); extern void mxc91231_arch_reset(int, const char *); extern void mxc91231_prepare_idle(void); - +extern void mx51_efikamx_reset(void); +extern int mx53_revision(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index d56213f..3b3a37c 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -10,58 +10,49 @@ * published by the Free Software Foundation. * */ -#define IMX_NEEDS_DEPRECATED_SYMBOLS +#include <mach/hardware.h> #ifdef CONFIG_ARCH_MX1 -#include <mach/mx1.h> -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX1_UART1_BASE_ADDR #endif #ifdef CONFIG_ARCH_MX25 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mx25.h> #define UART_PADDR MX25_UART1_BASE_ADDR -#define UART_VADDR MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR) #endif #ifdef CONFIG_ARCH_MX2 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mx2x.h> -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX2x_UART1_BASE_ADDR #endif #ifdef CONFIG_ARCH_MX3 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mx3x.h> -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX3x_UART1_BASE_ADDR #endif #ifdef CONFIG_ARCH_MX5 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mx51.h> #define UART_PADDR MX51_UART1_BASE_ADDR -#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR) #endif #ifdef CONFIG_ARCH_MXC91231 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mxc91231.h> #define UART_PADDR MXC91231_UART2_BASE_ADDR -#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) #endif + +#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) + .macro addruart, rp, rv ldr \rp, =UART_PADDR @ physical ldr \rv, =UART_VADDR @ virtual diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 8c6896f..3640eaf 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -10,9 +10,19 @@ #include <linux/platform_device.h> #include <linux/init.h> -struct platform_device *imx_add_platform_device(const char *name, int id, +struct platform_device *imx_add_platform_device_dmamask( + const char *name, int id, const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data); + const void *data, size_t size_data, u64 dmamask); + +static inline struct platform_device *imx_add_platform_device( + const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data) +{ + return imx_add_platform_device_dmamask( + name, id, res, num_resources, data, size_data, 0); +} #include <linux/fec.h> struct imx_fec_data { @@ -24,15 +34,62 @@ struct platform_device *__init imx_add_fec( const struct fec_platform_data *pdata); #include <linux/can/platform/flexcan.h> -struct platform_device *__init imx_add_flexcan(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, +struct imx_flexcan_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_flexcan( + const struct imx_flexcan_data *data, const struct flexcan_platform_data *pdata); +#include <linux/fsl_devices.h> +struct imx_fsl_usb2_udc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_fsl_usb2_udc( + const struct imx_fsl_usb2_udc_data *data, + const struct fsl_usb2_platform_data *pdata); + #include <linux/gpio_keys.h> struct platform_device *__init imx_add_gpio_keys( const struct gpio_keys_platform_data *pdata); +#include <mach/mx21-usbhost.h> +struct imx_imx21_hcd_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx21_hcd( + const struct imx_imx21_hcd_data *data, + const struct mx21_usbh_platform_data *pdata); + +struct imx_imx2_wdt_data { + resource_size_t iobase; + resource_size_t iosize; +}; +struct platform_device *__init imx_add_imx2_wdt( + const struct imx_imx2_wdt_data *data); + +struct imx_imxdi_rtc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imxdi_rtc( + const struct imx_imxdi_rtc_data *data); + +#include <mach/imxfb.h> +struct imx_imx_fb_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_fb( + const struct imx_imx_fb_data *data, + const struct imx_fb_platform_data *pdata); + #include <mach/i2c.h> struct imx_imx_i2c_data { int id; @@ -44,6 +101,16 @@ struct platform_device *__init imx_add_imx_i2c( const struct imx_imx_i2c_data *data, const struct imxi2c_platform_data *pdata); +#include <linux/input/matrix_keypad.h> +struct imx_imx_keypad_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_keypad( + const struct imx_imx_keypad_data *data, + const struct matrix_keymap_data *pdata); + #include <mach/ssi.h> struct imx_imx_ssi_data { int id; @@ -82,6 +149,67 @@ struct platform_device *__init imx_add_imx_uart_1irq( const struct imx_imx_uart_1irq_data *data, const struct imxuart_platform_data *pdata); +#include <mach/usb.h> +struct imx_imx_udc_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq0; + resource_size_t irq1; + resource_size_t irq2; + resource_size_t irq3; + resource_size_t irq4; + resource_size_t irq5; + resource_size_t irq6; +}; +struct platform_device *__init imx_add_imx_udc( + const struct imx_imx_udc_data *data, + const struct imxusb_platform_data *pdata); + +#include <mach/mx1_camera.h> +struct imx_mx1_camera_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mx1_camera( + const struct imx_mx1_camera_data *data, + const struct mx1_camera_pdata *pdata); + +#include <mach/mx2_cam.h> +struct imx_mx2_camera_data { + resource_size_t iobasecsi; + resource_size_t iosizecsi; + resource_size_t irqcsi; + resource_size_t iobaseemmaprp; + resource_size_t iosizeemmaprp; + resource_size_t irqemmaprp; +}; +struct platform_device *__init imx_add_mx2_camera( + const struct imx_mx2_camera_data *data, + const struct mx2_camera_platform_data *pdata); + +#include <mach/mxc_ehci.h> +struct imx_mxc_ehci_data { + int id; + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mxc_ehci( + const struct imx_mxc_ehci_data *data, + const struct mxc_usbh_platform_data *pdata); + +#include <mach/mmc.h> +struct imx_mxc_mmc_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; + resource_size_t dmareq; +}; +struct platform_device *__init imx_add_mxc_mmc( + const struct imx_mxc_mmc_data *data, + const struct imxmmc_platform_data *pdata); + #include <mach/mxc_nand.h> struct imx_mxc_nand_data { /* @@ -99,24 +227,39 @@ struct platform_device *__init imx_add_mxc_nand( const struct imx_mxc_nand_data *data, const struct mxc_nand_platform_data *pdata); -#include <mach/spi.h> -struct imx_spi_imx_data { - const char *devid; +struct imx_mxc_pwm_data { int id; resource_size_t iobase; resource_size_t iosize; - int irq; + resource_size_t irq; }; -struct platform_device *__init imx_add_spi_imx( - const struct imx_spi_imx_data *data, - const struct spi_imx_master *pdata); +struct platform_device *__init imx_add_mxc_pwm( + const struct imx_mxc_pwm_data *data); + +struct imx_mxc_w1_data { + resource_size_t iobase; +}; +struct platform_device *__init imx_add_mxc_w1( + const struct imx_mxc_w1_data *data); #include <mach/esdhc.h> -struct imx_esdhc_imx_data { +struct imx_sdhci_esdhc_imx_data { int id; resource_size_t iobase; resource_size_t irq; }; -struct platform_device *__init imx_add_esdhc( - const struct imx_esdhc_imx_data *data, +struct platform_device *__init imx_add_sdhci_esdhc_imx( + const struct imx_sdhci_esdhc_imx_data *data, const struct esdhc_platform_data *pdata); + +#include <mach/spi.h> +struct imx_spi_imx_data { + const char *devid; + int id; + resource_size_t iobase; + resource_size_t iosize; + int irq; +}; +struct platform_device *__init imx_add_spi_imx( + const struct imx_spi_imx_data *data, + const struct spi_imx_master *pdata); diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index af33b74..0044e2f 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -23,6 +23,11 @@ #include <mach/hardware.h> #include <asm-generic/gpio.h> + +/* There's a off-by-one betweem the gpio bank number and the gpiochip */ +/* range e.g. GPIO_1_5 is gpio 5 under linux */ +#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) + /* use gpiolib dispatchers */ #define gpio_get_value __gpio_get_value #define gpio_set_value __gpio_set_value diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index ebadf4a..f9ed0ba 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -22,13 +22,86 @@ #include <asm/sizes.h> -#define IMX_IO_ADDRESS(addr, module) \ - ((void __force __iomem *) \ - (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ - (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) +#ifdef __ASSEMBLER__ +#define IOMEM(addr) (addr) +#else +#define IOMEM(addr) ((void __force __iomem *)(addr)) +#endif + +#define IMX_IO_P2V_MODULE(addr, module) \ + (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \ + (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0) + +/* + * This is rather complicated for humans and ugly to verify, but for a machine + * it's OK. Still more as it is usually only applied to constants. The upsides + * on using this approach are: + * + * - same mapping on all i.MX machines + * - works for assembler, too + * - no need to nurture #defines for virtual addresses + * + * The downside it, it's hard to verify (but I have a script for that). + * + * Obviously this needs to be injective for each SoC. In general it maps the + * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff] + * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there). + * + * It applies the following mappings for the different SoCs: + * + * mx1: + * IO 0x00200000+0x100000 -> 0xf4000000+0x100000 + * mx21: + * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 + * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 + * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000 + * mx25: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * mx27: + * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 + * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 + * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000 + * mx31: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * mx35: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * mx51: + * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 + * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000 + * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 + * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 + * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 + * mxc91231: + * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000 + * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000 + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + */ +#define IMX_IO_P2V(x) ( \ + 0xf4000000 + \ + (((x) & 0x50000000) >> 6) + \ + (((x) & 0x0b000000) >> 4) + \ + (((x) & 0x000fffff))) + +#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) #ifdef CONFIG_ARCH_MX5 #include <mach/mx51.h> +#include <mach/mx53.h> #endif #ifdef CONFIG_ARCH_MX3 @@ -61,4 +134,11 @@ #include <mach/mxc.h> +#define imx_map_entry(soc, name, _type) { \ + .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ + .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ + .length = soc ## _ ## name ## _SIZE, \ + .type = _type, \ +} + #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h index 5263506..9de8f06 100644 --- a/arch/arm/plat-mxc/include/mach/imxfb.h +++ b/arch/arm/plat-mxc/include/mach/imxfb.h @@ -1,6 +1,8 @@ /* * This structure describes the machine which we are running on. */ +#ifndef __MACH_IMXFB_H__ +#define __MACH_IMXFB_H__ #include <linux/fb.h> @@ -79,3 +81,4 @@ struct imx_fb_platform_data { }; void set_imx_fb_info(struct imx_fb_platform_data *); +#endif /* ifndef __MACH_IMXFB_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index d7a41e9..e1600f3 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -40,6 +40,8 @@ typedef enum iomux_config { PAD_CTL_SRE_FAST) #define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) +#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) #define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_HYS) @@ -200,7 +202,9 @@ typedef enum iomux_config { #define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_VSYNC__GPIO_3_14 IOMUX_PAD(0x5AC, 0x1C4, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_HSYNC__GPIO_3_15 IOMUX_PAD(0x5B0, 0x1C8, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x000, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x000, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x000, 0, 0x0, 0, NO_PAD_CTRL) @@ -232,9 +236,9 @@ typedef enum iomux_config { #define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) @@ -368,20 +372,24 @@ typedef enum iomux_config { MX51_SDHCI_PAD_CTRL) #define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \ MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_GPIO_1_0__ESDHC1_CD IOMUX_PAD(0x7B4, 0x3AC, 0, 0x0, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_1__ESDHC1_WP IOMUX_PAD(0x7B8, 0x3B0, 0, 0x0, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ 0x9b8, 3, MX51_I2C_PAD_CTRL) -#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \ 0x9bc, 3, MX51_I2C_PAD_CTRL) #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_7__ESDHC2_WP IOMUX_PAD(0x810, 0x3E4, 6, 0x0, 0, MX51_ESDHC_PAD_CTRL) +#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_8__ESDHC2_CD IOMUX_PAD(0x814, 0x3E8, 6, 0x0, 0, MX51_ESDHC_PAD_CTRL) +#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) #endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h new file mode 100644 index 0000000..80cb3c5 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc.. + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX53_H__ +#define __MACH_IOMUX_MX53_H__ + +#include <mach/iomux-v3.h> + +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +/* These 2 defines are for pins that may not have a mux register, but could + * have a pad setting register, and vice-versa. */ +#define NON_MUX_I 0x00 +#define NON_PAD_I 0x00 + +#define MX53_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x348, 0x20,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x34C, 0x24,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x350, 0x28,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x354, 0x2C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x358, 0x30,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x35C, 0x34,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x360, 0x38,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x364, 0x3C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x368, 0x40,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x36C, 0x44,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x370, 0x48,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD IOMUX_PAD(0x374, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x378, 0x4C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x37C, 0x50,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x380, 0x54,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x384, 0x58,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x388, 0x5C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x38C, 0x60,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x390, 0x64,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x394, 0x68,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x398, 0x6C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x39C, 0x70,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x3A0, 0x74,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x3A4, 0x78,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x3A8, 0x7C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x3AC, 0x80,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x3B0, 0x84,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x3B8, 0x8C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x3BC, 0x90,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x3C0, 0x94,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x3C4, 0x98,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x3C8, 0x9C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x3F0, 0xC4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x3F4, 0xC8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x3F8, 0xCC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D4__GPIO_5_22 IOMUX_PAD(0x3FC, 0xD0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D5__GPIO_5_23 IOMUX_PAD(0x400, 0xD4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D6__GPIO_5_24 IOMUX_PAD(0x404, 0xD8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D7__GPIO_5_25 IOMUX_PAD(0x408, 0xDC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D8__GPIO_5_26 IOMUX_PAD(0x40C, 0xE0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D9__GPIO_5_27 IOMUX_PAD(0x410, 0xE4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D10__GPIO_5_28 IOMUX_PAD(0x414, 0xE8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D11__GPIO_5_29 IOMUX_PAD(0x418, 0xEC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D12__GPIO_5_30 IOMUX_PAD(0x41C, 0xF0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D13__GPIO_5_31 IOMUX_PAD(0x420, 0xF4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D14__GPIO_6_0 IOMUX_PAD(0x424, 0xF8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D15__GPIO_6_1 IOMUX_PAD(0x428, 0xFC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D16__GPIO_6_2 IOMUX_PAD(0x42C, 0x100,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D17__GPIO_6_3 IOMUX_PAD(0x430, 0x104,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D18__GPIO_6_4 IOMUX_PAD(0x434, 0x108,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D19__GPIO_6_5 IOMUX_PAD(0x438, 0x10C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_CSI0__NVCC_CSI0 IOMUX_PAD(0x43C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TMS__JTAG_TMS IOMUX_PAD(0x440, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_MOD__JTAG_MOD IOMUX_PAD(0x444, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TDI__JTAG_TDI IOMUX_PAD(0x44C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TCK__JTAG_TCK IOMUX_PAD(0x450, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TDO__JTAG_TDO IOMUX_PAD(0x454, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x458, 0x110,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x45C, 0x114,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x478, 0x130,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x47C, 0x134,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x480, 0x138,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x484, 0x13C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x488, 0x140,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x48C, 0x144,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x490, 0x148,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x494, 0x14C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x498, 0x150,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x49C, 0x154,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x4A0, 0x158,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM1__NVCC_EIM1 IOMUX_PAD(0x4A4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x4AC, 0x160,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x4B0, 0x164,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x4B4, 0x168,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x4B8, 0x16C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x4BC, 0x170,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x4C0, 0x174,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x4C4, 0x178,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x4C8, 0x17C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x4CC, 0x180,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x4D0, 0x184,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x4D4, 0x188,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x4D8, 0x18C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x4DC, 0x190,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM4__NVCC_EIM4 IOMUX_PAD(0x4E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x4E4, 0x194,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x4E8, 0x198,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x4EC, 0x19C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x4F0, 0x1A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x4F4, 0x1A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x4F8, 0x1A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x4FC, 0x1AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x500, 0x1B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x504, 0x1B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x508, 0x1B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x50C, 0x1BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x510, 0x1C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x514, 0x1C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x518, 0x1C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x51C, 0x1CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x520, 0x1D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x524, 0x1D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x528, 0x1D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WE_B__GPIO_6_12 IOMUX_PAD(0x52C, 0x1DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RE_B__GPIO_6_13 IOMUX_PAD(0x530, 0x1E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x534, 0x1E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM7__NVCC_EIM7 IOMUX_PAD(0x53C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_10__GPIO_4_0 IOMUX_PAD(0x540, 0x214, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_11__GPIO_4_1 IOMUX_PAD(0x544, 0x218, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_12__GPIO_4_2 IOMUX_PAD(0x548, 0x21C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_13__GPIO_4_3 IOMUX_PAD(0x54C, 0x220, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_14__GPIO_4_4 IOMUX_PAD(0x550, 0x224, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM3__DRAM_DQM3 IOMUX_PAD(0x554, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1 IOMUX_PAD(0x55C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM2__DRAM_DQM2 IOMUX_PAD(0x560, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1 IOMUX_PAD(0x564, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1 IOMUX_PAD(0x570, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_CAS__DRAM_CAS IOMUX_PAD(0x574, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0 IOMUX_PAD(0x578, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0 IOMUX_PAD(0x580, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM0__DRAM_DQM0 IOMUX_PAD(0x584, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_RAS__DRAM_RAS IOMUX_PAD(0x588, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0 IOMUX_PAD(0x58C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM1__DRAM_DQM1 IOMUX_PAD(0x594, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x598, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x59C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x5A0, 0x228,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x5A4, 0x22C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x5A8, 0x230,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x5AC, 0x234,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x5B0, 0x238,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x5B4, 0x23C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x5B8, 0x240,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x5BC, 0x244,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__GPIO_1_22 IOMUX_PAD(0x5C4, 0x248,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__GPIO_1_24 IOMUX_PAD(0x5CC, 0x250,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__GPIO_1_25 IOMUX_PAD(0x5D0, 0x254,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__GPIO_1_26 IOMUX_PAD(0x5D4, 0x258,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__GPIO_1_27 IOMUX_PAD(0x5D8, 0x25C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__GPIO_1_28 IOMUX_PAD(0x5DC, 0x260,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__GPIO_1_29 IOMUX_PAD(0x5E0, 0x264,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__GPIO_1_30 IOMUX_PAD(0x5E4, 0x268,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__GPIO_1_31 IOMUX_PAD(0x5E8, 0x26C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_FEC__NVCC_FEC IOMUX_PAD(0x5EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DIOW__GPIO_6_17 IOMUX_PAD(0x5F0, 0x270,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DMACK__GPIO_6_18 IOMUX_PAD(0x5F4, 0x274,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DMARQ__GPIO_7_0 IOMUX_PAD(0x5F8, 0x278,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1 IOMUX_PAD(0x5FC, 0x27C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_INTRQ__GPIO_7_2 IOMUX_PAD(0x600, 0x280,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DIOR__GPIO_7_3 IOMUX_PAD(0x604, 0x284,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_RESET_B__GPIO_7_4 IOMUX_PAD(0x608, 0x288,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_IORDY__GPIO_7_5 IOMUX_PAD(0x60C, 0x28C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_0__GPIO_7_6 IOMUX_PAD(0x610, 0x290,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_1__GPIO_7_7 IOMUX_PAD(0x614, 0x294,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_2__GPIO_7_8 IOMUX_PAD(0x618, 0x298,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_CS_0__GPIO_7_9 IOMUX_PAD(0x61C, 0x29C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_CS_1__GPIO_7_10 IOMUX_PAD(0x620, 0x2A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_ATA2__NVCC_ATA2 IOMUX_PAD(0x624, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA0__GPIO_2_0 IOMUX_PAD(0x628, 0x2A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA1__GPIO_2_1 IOMUX_PAD(0x62C, 0x2A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA2__GPIO_2_2 IOMUX_PAD(0x630, 0x2AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA3__GPIO_2_3 IOMUX_PAD(0x634, 0x2B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA4__GPIO_2_4 IOMUX_PAD(0x638, 0x2B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA5__GPIO_2_5 IOMUX_PAD(0x63C, 0x2B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA6__GPIO_2_6 IOMUX_PAD(0x640, 0x2BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA7__GPIO_2_7 IOMUX_PAD(0x644, 0x2C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA8__GPIO_2_8 IOMUX_PAD(0x648, 0x2C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA9__GPIO_2_9 IOMUX_PAD(0x64C, 0x2C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA10__GPIO_2_10 IOMUX_PAD(0x650, 0x2CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA11__GPIO_2_11 IOMUX_PAD(0x654, 0x2D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA12__GPIO_2_12 IOMUX_PAD(0x658, 0x2D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA13__GPIO_2_13 IOMUX_PAD(0x65C, 0x2D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA14__GPIO_2_14 IOMUX_PAD(0x660, 0x2DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA15__GPIO_2_15 IOMUX_PAD(0x664, 0x2E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_ATA0__NVCC_ATA0 IOMUX_PAD(0x668, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__GPIO_1_16 IOMUX_PAD(0x66C, 0x2E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__GPIO_1_17 IOMUX_PAD(0x670, 0x2E8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x674, 0x2EC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__GPIO_1_19 IOMUX_PAD(0x678, 0x2F0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x67C, 0x2F4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__GPIO_1_21 IOMUX_PAD(0x680, 0x2F8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_SD1__NVCC_SD1 IOMUX_PAD(0x684, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x688, 0x2FC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x68C, 0x300,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__GPIO_1_12 IOMUX_PAD(0x690, 0x304,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__GPIO_1_13 IOMUX_PAD(0x694, 0x308,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__GPIO_1_14 IOMUX_PAD(0x698, 0x30C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__GPIO_1_15 IOMUX_PAD(0x69C, 0x310,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_SD2__NVCC_SD2 IOMUX_PAD(0x6A0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x6A4, 0x314,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x6A8, 0x318,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x6AC, 0x31C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x6B0, 0x320,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x6B4, 0x324,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x6B8, 0x328,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x6BC, 0x32C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x6C0, 0x330,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x6C4, 0x334,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x6C8, 0x338,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x6CC, 0x33C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x6D0, 0x340,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x6D4, 0x344,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_GPIO__NVCC_GPIO IOMUX_PAD(0x6D8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_POR_B__POR_B IOMUX_PAD(0x6DC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_TEST_MODE__TEST_MODE IOMUX_PAD(0x6EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_ADDDS__GRP_ADDDS IOMUX_PAD(0x6F0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL IOMUX_PAD(0x6F4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRPK__GRP_DDRPK IOMUX_PAD(0x708, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3 IOMUX_PAD(0x70C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE IOMUX_PAD(0x714, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B0DS__GRP_B0DS IOMUX_PAD(0x718, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B1DS__GRP_B1DS IOMUX_PAD(0x71C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_CTLDS__GRP_CTLDS IOMUX_PAD(0x720, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE IOMUX_PAD(0x724, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B2DS__GRP_B2DS IOMUX_PAD(0x728, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B3DS__GRP_B3DS IOMUX_PAD(0x72C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index 0880a4a..811716f 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -44,7 +44,7 @@ * */ -struct pad_desc { +typedef struct deprecated_pad_desc { unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */ unsigned mux_mode:8; unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */ @@ -52,7 +52,37 @@ struct pad_desc { unsigned pad_ctrl:17; unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */ unsigned select_input:3; -}; +} iomux_v3_cfg_t; + +static inline unsigned int MUX_CTRL_OFS(iomux_v3_cfg_t *pad) +{ + return pad->mux_ctrl_ofs; +} + +static inline unsigned int MUX_MODE(iomux_v3_cfg_t *pad) +{ + return pad->mux_mode; +} + +static inline unsigned int MUX_SELECT_INPUT_OFS(iomux_v3_cfg_t *pad) +{ + return pad->select_input_ofs; +} + +static inline unsigned int MUX_SELECT_INPUT(iomux_v3_cfg_t *pad) +{ + return pad->select_input; +} + +static inline unsigned int MUX_PAD_CTRL_OFS(iomux_v3_cfg_t *pad) +{ + return pad->pad_ctrl_ofs; +} + +static inline unsigned int MUX_PAD_CTRL(iomux_v3_cfg_t *pad) +{ + return pad->pad_ctrl; +} #define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \ _select_input, _pad_ctrl) \ @@ -107,13 +137,13 @@ struct pad_desc { /* * setups a single pad in the iomuxer */ -int mxc_iomux_v3_setup_pad(struct pad_desc *pad); +int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t *pad); /* * setups mutliple pads * convenient way to call the above function with tables */ -int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); +int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); /* * Initialise the iomux controller diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 564ec9d..9a9a000 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -17,6 +17,7 @@ #define MX27_PHYS_OFFSET UL(0xa0000000) #define MX3x_PHYS_OFFSET UL(0x80000000) #define MX51_PHYS_OFFSET UL(0x90000000) +#define MX53_PHYS_OFFSET UL(0x70000000) #define MXC91231_PHYS_OFFSET UL(0x90000000) #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) @@ -32,8 +33,10 @@ # define PHYS_OFFSET MX3x_PHYS_OFFSET # elif defined CONFIG_ARCH_MXC91231 # define PHYS_OFFSET MXC91231_PHYS_OFFSET -# elif defined CONFIG_ARCH_MX5 +# elif defined CONFIG_ARCH_MX51 # define PHYS_OFFSET MX51_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX53 +# define PHYS_OFFSET MX53_PHYS_OFFSET # endif #endif diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 641b246..75d9621 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -19,7 +19,6 @@ */ #define MX1_IO_BASE_ADDR 0x00200000 #define MX1_IO_SIZE SZ_1M -#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END #define MX1_CS0_PHYS 0x10000000 #define MX1_CS0_SIZE 0x02000000 @@ -66,6 +65,10 @@ #define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) #define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) #define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR) +#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR) +#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR) #define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) #define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) #define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) @@ -73,12 +76,12 @@ #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) /* macro to get at IO space when running virtually */ -#define MX1_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX1_IO)) +#define MX1_IO_P2V(x) IMX_IO_P2V(x) +#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) /* fixed interrput numbers */ #define MX1_INT_SOFTINT 0 -#define MX1_CSI_INT 6 +#define MX1_INT_CSI 6 #define MX1_DSPA_MAC_INT 7 #define MX1_DSPA_INT 8 #define MX1_COMP_INT 9 @@ -115,13 +118,13 @@ #define MX1_SSI_RX_INT 44 #define MX1_SSI_RX_ERR_INT 45 #define MX1_TOUCH_INT 46 -#define MX1_USBD_INT0 47 -#define MX1_USBD_INT1 48 -#define MX1_USBD_INT2 49 -#define MX1_USBD_INT3 50 -#define MX1_USBD_INT4 51 -#define MX1_USBD_INT5 52 -#define MX1_USBD_INT6 53 +#define MX1_INT_USBD0 47 +#define MX1_INT_USBD1 48 +#define MX1_INT_USBD2 49 +#define MX1_INT_USBD3 50 +#define MX1_INT_USBD4 51 +#define MX1_INT_USBD5 52 +#define MX1_INT_USBD6 53 #define MX1_BTSYS_INT 55 #define MX1_BTTIM_INT 56 #define MX1_BTWUI_INT 57 @@ -164,134 +167,6 @@ * to not break drivers/usb/gadget/imx_udc. Should go * away after this driver uses the new name. */ -#define USBD_INT0 MX1_USBD_INT0 - -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define IMX_IO_PHYS MX1_IO_BASE_ADDR -#define IMX_IO_SIZE MX1_IO_SIZE -#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT -#define IMX_CS0_PHYS MX1_CS0_PHYS -#define IMX_CS0_SIZE MX1_CS0_SIZE -#define IMX_CS1_PHYS MX1_CS1_PHYS -#define IMX_CS1_SIZE MX1_CS1_SIZE -#define IMX_CS2_PHYS MX1_CS2_PHYS -#define IMX_CS2_SIZE MX1_CS2_SIZE -#define IMX_CS3_PHYS MX1_CS3_PHYS -#define IMX_CS3_SIZE MX1_CS3_SIZE -#define IMX_CS4_PHYS MX1_CS4_PHYS -#define IMX_CS4_SIZE MX1_CS4_SIZE -#define IMX_CS5_PHYS MX1_CS5_PHYS -#define IMX_CS5_SIZE MX1_CS5_SIZE -#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR -#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR -#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR -#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR -#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR -#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR -#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR -#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR -#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR -#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR -#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR -#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR -#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR -#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR -#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR -#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR -#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR -#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR -#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR -#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR -#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR -#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR -#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR -#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR -#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR -#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR -#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR -#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR -#define IO_ADDRESS(x) MX1_IO_ADDRESS(x) -#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) -#define INT_SOFTINT MX1_INT_SOFTINT -#define CSI_INT MX1_CSI_INT -#define DSPA_MAC_INT MX1_DSPA_MAC_INT -#define DSPA_INT MX1_DSPA_INT -#define COMP_INT MX1_COMP_INT -#define MSHC_XINT MX1_MSHC_XINT -#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA -#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB -#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC -#define LCDC_INT MX1_LCDC_INT -#define SIM_INT MX1_SIM_INT -#define SIM_DATA_INT MX1_SIM_DATA_INT -#define RTC_INT MX1_RTC_INT -#define RTC_SAMINT MX1_RTC_SAMINT -#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR -#define UART2_MINT_RTS MX1_UART2_MINT_RTS -#define UART2_MINT_DTR MX1_UART2_MINT_DTR -#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC -#define UART2_MINT_TX MX1_UART2_MINT_TX -#define UART2_MINT_RX MX1_UART2_MINT_RX -#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR -#define UART1_MINT_RTS MX1_UART1_MINT_RTS -#define UART1_MINT_DTR MX1_UART1_MINT_DTR -#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC -#define UART1_MINT_TX MX1_UART1_MINT_TX -#define UART1_MINT_RX MX1_UART1_MINT_RX -#define VOICE_DAC_INT MX1_VOICE_DAC_INT -#define VOICE_ADC_INT MX1_VOICE_ADC_INT -#define PEN_DATA_INT MX1_PEN_DATA_INT -#define PWM_INT MX1_PWM_INT -#define SDHC_INT MX1_SDHC_INT -#define I2C_INT MX1_INT_I2C -#define CSPI_INT MX1_CSPI_INT -#define SSI_TX_INT MX1_SSI_TX_INT -#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT -#define SSI_RX_INT MX1_SSI_RX_INT -#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT -#define TOUCH_INT MX1_TOUCH_INT -#define USBD_INT1 MX1_USBD_INT1 -#define USBD_INT2 MX1_USBD_INT2 -#define USBD_INT3 MX1_USBD_INT3 -#define USBD_INT4 MX1_USBD_INT4 -#define USBD_INT5 MX1_USBD_INT5 -#define USBD_INT6 MX1_USBD_INT6 -#define BTSYS_INT MX1_BTSYS_INT -#define BTTIM_INT MX1_BTTIM_INT -#define BTWUI_INT MX1_BTWUI_INT -#define TIM2_INT MX1_TIM2_INT -#define TIM1_INT MX1_TIM1_INT -#define DMA_ERR MX1_DMA_ERR -#define DMA_INT MX1_DMA_INT -#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD -#define WDT_INT MX1_WDT_INT -#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T -#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R -#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T -#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R -#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT -#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R -#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC -#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT -#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN -#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC -#define DMA_REQ_EXT MX1_DMA_REQ_EXT -#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC -#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R -#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T -#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T -#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R -#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC -#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC -#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x) -#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R -#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T -#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T -#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R -#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T -#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R -#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */ +#define USBD_INT0 MX1_INT_USBD0 #endif /* ifndef __MACH_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 8bc5972..6cd049e 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -26,7 +26,6 @@ #define __MACH_MX21_H__ #define MX21_AIPI_BASE_ADDR 0x10000000 -#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX21_AIPI_SIZE SZ_1M #define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) #define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) @@ -49,6 +48,12 @@ #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) +#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) +#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) +#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) +#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) +#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) +#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) @@ -64,7 +69,6 @@ #define MX21_AVIC_BASE_ADDR 0x10040000 #define MX21_SAHB1_BASE_ADDR 0x80000000 -#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000 #define MX21_SAHB1_SIZE SZ_1M #define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) @@ -82,7 +86,6 @@ /* NAND, SDRAM, WEIM etc controllers */ #define MX21_X_MEMC_BASE_ADDR 0xdf000000 -#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000 #define MX21_X_MEMC_SIZE SZ_256K #define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) @@ -92,10 +95,8 @@ #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ -#define MX21_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX21_AIPI) ?: \ - IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \ - IMX_IO_ADDRESS(x, MX21_X_MEMC)) +#define MX21_IO_P2V(x) IMX_IO_P2V(x) +#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) /* fixed interrupt numbers */ #define MX21_INT_CSPI3 6 @@ -184,39 +185,4 @@ #define MX21_DMA_REQ_CSI_STAT 30 #define MX21_DMA_REQ_CSI_RX 31 -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR -#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR -#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR -#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR -#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR -#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR -#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR -#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR -#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR -#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR -#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT -#define X_MEMC_SIZE MX21_X_MEMC_SIZE -#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR -#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR -#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR -#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR -#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR -#define MXC_INT_FIRI MX21_INT_FIRI -#define MXC_INT_BMI MX21_INT_BMI -#define MXC_INT_EMMAENC MX21_INT_EMMAENC -#define MXC_INT_EMMADEC MX21_INT_EMMADEC -#define MXC_INT_USBWKUP MX21_INT_USBWKUP -#define MXC_INT_USBDMA MX21_INT_USBDMA -#define MXC_INT_USBHOST MX21_INT_USBHOST -#define MXC_INT_USBFUNC MX21_INT_USBFUNC -#define MXC_INT_USBMNP MX21_INT_USBMNP -#define MXC_INT_USBCTRL MX21_INT_USBCTRL -#define MXC_INT_USBCTRL MX21_INT_USBCTRL -#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX -#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX -#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX -#endif - #endif /* ifndef __MACH_MX21_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index cf46a45..087cd7a 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -2,13 +2,10 @@ #define __MACH_MX25_H__ #define MX25_AIPS1_BASE_ADDR 0x43f00000 -#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX25_AIPS1_SIZE SZ_1M #define MX25_AIPS2_BASE_ADDR 0x53f00000 -#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX25_AIPS2_SIZE SZ_1M #define MX25_AVIC_BASE_ADDR 0x68000000 -#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX25_AVIC_SIZE SZ_1M #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) @@ -21,20 +18,15 @@ #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) +#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) +#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) +#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) +#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) +#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) +#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) +#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) - -#define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000) -#define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000) -#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) -#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) - -#define MX25_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ - IMX_IO_ADDRESS(x, MX25_AVIC)) - -#define MX25_AIPS1_IO_ADDRESS(x) \ - (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) +#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) #define MX25_UART1_BASE_ADDR 0x43f90000 #define MX25_UART2_BASE_ADDR 0x43f94000 @@ -55,9 +47,19 @@ #define MX25_LCDC_BASE_ADDR 0x53fbc000 #define MX25_KPP_BASE_ADDR 0x43fa8000 #define MX25_SDMA_BASE_ADDR 0x53fd4000 -#define MX25_OTG_BASE_ADDR 0x53ff4000 +#define MX25_USB_BASE_ADDR 0x53ff4000 +#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) +/* + * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200 + * for the host controller. Early documentation drafts specified 0x400 and + * Freescale internal sources confirm only the latter value to work. + */ +#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400) #define MX25_CSI_BASE_ADDR 0x53ff8000 +#define MX25_IO_P2V(x) IMX_IO_P2V(x) +#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) + #define MX25_INT_CSPI3 0 #define MX25_INT_I2C1 3 #define MX25_INT_I2C2 4 @@ -69,18 +71,28 @@ #define MX25_INT_SSI1 12 #define MX25_INT_CSPI2 13 #define MX25_INT_CSPI1 14 +#define MX25_INT_GPIO3 16 #define MX25_INT_CSI 17 #define MX25_INT_UART3 18 +#define MX25_INT_GPIO4 23 #define MX25_INT_KPP 24 #define MX25_INT_DRYICE 25 +#define MX25_INT_PWM1 26 #define MX25_INT_UART2 32 #define MX25_INT_NFC 33 #define MX25_INT_SDMA 34 +#define MX25_INT_USB_HS 35 +#define MX25_INT_PWM2 36 +#define MX25_INT_USB_OTG 37 #define MX25_INT_LCDC 39 #define MX25_INT_UART5 40 +#define MX25_INT_PWM3 41 +#define MX25_INT_PWM4 42 #define MX25_INT_CAN1 43 #define MX25_INT_CAN2 44 #define MX25_INT_UART1 45 +#define MX25_INT_GPIO2 51 +#define MX25_INT_GPIO1 52 #define MX25_INT_FEC 57 #define MX25_DMA_REQ_SSI2_RX1 22 diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 2237ba2..cbc43ad 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -29,7 +29,6 @@ #endif #define MX27_AIPI_BASE_ADDR 0x10000000 -#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX27_AIPI_SIZE SZ_1M #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) @@ -52,6 +51,12 @@ #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) +#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) +#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) +#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) +#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) +#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) +#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) @@ -65,11 +70,13 @@ #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) -#define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) -#define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR +#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) +#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) +#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) +#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) -#define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) -#define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) +#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) +#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) @@ -87,7 +94,6 @@ #define MX27_ROMP_BASE_ADDR 0x10041000 #define MX27_SAHB1_BASE_ADDR 0x80000000 -#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000 #define MX27_SAHB1_SIZE SZ_1M #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) @@ -105,7 +111,6 @@ /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX27_X_MEMC_BASE_ADDR 0xd8000000 -#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000 #define MX27_X_MEMC_SIZE SZ_1M #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) @@ -123,10 +128,8 @@ /* IRAM */ #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ -#define MX27_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX27_AIPI) ?: \ - IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \ - IMX_IO_ADDRESS(x, MX27_X_MEMC)) +#define MX27_IO_P2V(x) IMX_IO_P2V(x) +#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) #ifndef __ASSEMBLER__ static inline void mx27_setup_weimcs(size_t cs, @@ -192,9 +195,9 @@ static inline void mx27_setup_weimcs(size_t cs, #define MX27_INT_EMMAPRP 51 #define MX27_INT_EMMAPP 52 #define MX27_INT_VPU 53 -#define MX27_INT_USB1 54 -#define MX27_INT_USB2 55 -#define MX27_INT_USB3 56 +#define MX27_INT_USB_HS1 54 +#define MX27_INT_USB_HS2 55 +#define MX27_INT_USB_OTG 56 #define MX27_INT_SCC_SMN 57 #define MX27_INT_SCC_SCM 58 #define MX27_INT_SAHARA 59 @@ -241,82 +244,8 @@ static inline void mx27_setup_weimcs(size_t cs, #define MX27_DMA_REQ_SDHC3 36 #define MX27_DMA_REQ_NFC 37 -/* silicon revisions specific to i.MX27 */ -#define CHIP_REV_1_0 0x00 -#define CHIP_REV_2_0 0x01 - #ifndef __ASSEMBLY__ extern int mx27_revision(void); #endif -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR -#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR -#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR -#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR -#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR -#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR -#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR -#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR -#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR -#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR -#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR -#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR -#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR -#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR -#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR -#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR -#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR -#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR -#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR -#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR -#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR -#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR -#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR -#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR -#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR -#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR -#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR -#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR -#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT -#define X_MEMC_SIZE MX27_X_MEMC_SIZE -#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR -#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR -#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR -#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR -#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR -#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR -#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR -#define MXC_INT_I2C2 MX27_INT_I2C2 -#define MXC_INT_GPT6 MX27_INT_GPT6 -#define MXC_INT_GPT5 MX27_INT_GPT5 -#define MXC_INT_GPT4 MX27_INT_GPT4 -#define MXC_INT_RTIC MX27_INT_RTIC -#define MXC_INT_SDHC MX27_INT_SDHC -#define MXC_INT_SDHC3 MX27_INT_SDHC3 -#define MXC_INT_ATA MX27_INT_ATA -#define MXC_INT_UART6 MX27_INT_UART6 -#define MXC_INT_UART5 MX27_INT_UART5 -#define MXC_INT_FEC MX27_INT_FEC -#define MXC_INT_VPU MX27_INT_VPU -#define MXC_INT_USB1 MX27_INT_USB1 -#define MXC_INT_USB2 MX27_INT_USB2 -#define MXC_INT_USB3 MX27_INT_USB3 -#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN -#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM -#define MXC_INT_SAHARA MX27_INT_SAHARA -#define MXC_INT_IIM MX27_INT_IIM -#define MXC_INT_CCM MX27_INT_CCM -#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC -#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX -#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV -#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX -#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX -#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX -#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX -#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 -#define DMA_REQ_NFC MX27_DMA_REQ_NFC -#endif - #endif /* ifndef __MACH_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index afb895a..6d07839 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -27,7 +27,6 @@ /* Register offsets */ #define MX2x_AIPI_BASE_ADDR 0x10000000 -#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX2x_AIPI_SIZE SZ_1M #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) @@ -65,43 +64,9 @@ #define MX2x_AVIC_BASE_ADDR 0x10040000 #define MX2x_SAHB1_BASE_ADDR 0x80000000 -#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000 #define MX2x_SAHB1_SIZE SZ_1M #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) -/* - * This macro defines the physical to virtual address mapping for all the - * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. If the physical address is not mapped, - * it returns 0xDEADBEEF - */ -#define IO_ADDRESS(x) \ - (void __force __iomem *) \ - (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ - AIPI_IO_ADDRESS(x) : \ - ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ - SAHB1_IO_ADDRESS(x) : \ - ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \ - X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF) - -/* define the address mapping macros: in physical address order */ -#define AIPI_IO_ADDRESS(x) \ - (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) - -#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x) - -#define SAHB1_IO_ADDRESS(x) \ - (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT) - -#define CS4_IO_ADDRESS(x) \ - (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) - -#define X_MEMC_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - -#define PCMCIA_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - /* fixed interrupt numbers */ #define MX2x_INT_CSPI3 6 #define MX2x_INT_GPIO 8 @@ -176,118 +141,4 @@ #define MX2x_DMA_REQ_CSI_STAT 30 #define MX2x_DMA_REQ_CSI_RX 31 -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR -#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT -#define AIPI_SIZE MX2x_AIPI_SIZE -#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR -#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR -#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR -#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR -#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR -#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR -#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR -#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR -#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR -#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR -#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR -#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR -#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR -#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR -#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR -#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR -#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR -#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR -#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR -#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR -#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR -#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR -#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR -#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR -#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR -#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR -#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR -#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR -#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR -#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR -#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR -#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR -#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR -#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT -#define SAHB1_SIZE MX2x_SAHB1_SIZE -#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR -#define MXC_INT_CSPI3 MX2x_INT_CSPI3 -#define MXC_INT_GPIO MX2x_INT_GPIO -#define MXC_INT_SDHC2 MX2x_INT_SDHC2 -#define MXC_INT_SDHC1 MX2x_INT_SDHC1 -#define MXC_INT_I2C MX2x_INT_I2C -#define MXC_INT_SSI2 MX2x_INT_SSI2 -#define MXC_INT_SSI1 MX2x_INT_SSI1 -#define MXC_INT_CSPI2 MX2x_INT_CSPI2 -#define MXC_INT_CSPI1 MX2x_INT_CSPI1 -#define MXC_INT_UART4 MX2x_INT_UART4 -#define MXC_INT_UART3 MX2x_INT_UART3 -#define MXC_INT_UART2 MX2x_INT_UART2 -#define MXC_INT_UART1 MX2x_INT_UART1 -#define MXC_INT_KPP MX2x_INT_KPP -#define MXC_INT_RTC MX2x_INT_RTC -#define MXC_INT_PWM MX2x_INT_PWM -#define MXC_INT_GPT3 MX2x_INT_GPT3 -#define MXC_INT_GPT2 MX2x_INT_GPT2 -#define MXC_INT_GPT1 MX2x_INT_GPT1 -#define MXC_INT_WDOG MX2x_INT_WDOG -#define MXC_INT_PCMCIA MX2x_INT_PCMCIA -#define MXC_INT_NANDFC MX2x_INT_NANDFC -#define MXC_INT_CSI MX2x_INT_CSI -#define MXC_INT_DMACH0 MX2x_INT_DMACH0 -#define MXC_INT_DMACH1 MX2x_INT_DMACH1 -#define MXC_INT_DMACH2 MX2x_INT_DMACH2 -#define MXC_INT_DMACH3 MX2x_INT_DMACH3 -#define MXC_INT_DMACH4 MX2x_INT_DMACH4 -#define MXC_INT_DMACH5 MX2x_INT_DMACH5 -#define MXC_INT_DMACH6 MX2x_INT_DMACH6 -#define MXC_INT_DMACH7 MX2x_INT_DMACH7 -#define MXC_INT_DMACH8 MX2x_INT_DMACH8 -#define MXC_INT_DMACH9 MX2x_INT_DMACH9 -#define MXC_INT_DMACH10 MX2x_INT_DMACH10 -#define MXC_INT_DMACH11 MX2x_INT_DMACH11 -#define MXC_INT_DMACH12 MX2x_INT_DMACH12 -#define MXC_INT_DMACH13 MX2x_INT_DMACH13 -#define MXC_INT_DMACH14 MX2x_INT_DMACH14 -#define MXC_INT_DMACH15 MX2x_INT_DMACH15 -#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP -#define MXC_INT_EMMAPP MX2x_INT_EMMAPP -#define MXC_INT_SLCDC MX2x_INT_SLCDC -#define MXC_INT_LCDC MX2x_INT_LCDC -#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX -#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX -#define DMA_REQ_EXT MX2x_DMA_REQ_EXT -#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2 -#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1 -#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0 -#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0 -#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1 -#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1 -#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0 -#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0 -#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1 -#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1 -#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX -#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX -#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX -#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX -#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX -#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX -#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX -#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX -#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX -#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX -#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX -#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX -#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT -#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX -#endif - #endif /* ifndef __MACH_MX2x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 61cfe82..79e7fc0 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -15,7 +15,6 @@ #define MX31_L2CC_SIZE SZ_1M #define MX31_AIPS1_BASE_ADDR 0x43f00000 -#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX31_AIPS1_SIZE SZ_1M #define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) #define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) @@ -25,7 +24,10 @@ #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) #define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) -#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) +#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) +#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) @@ -41,10 +43,9 @@ #define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) #define MX31_SPBA0_BASE_ADDR 0x50000000 -#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000 #define MX31_SPBA0_SIZE SZ_1M -#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) -#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) +#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) +#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) #define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) #define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) #define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) @@ -55,7 +56,6 @@ #define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) #define MX31_AIPS2_BASE_ADDR 0x53f00000 -#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX31_AIPS2_SIZE SZ_1M #define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) #define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) @@ -84,7 +84,6 @@ #define MX31_ROMP_SIZE SZ_1M #define MX31_AVIC_BASE_ADDR 0x68000000 -#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX31_AVIC_SIZE SZ_1M #define MX31_IPU_MEM_BASE_ADDR 0x70000000 @@ -97,15 +96,14 @@ #define MX31_CS3_BASE_ADDR 0xb2000000 #define MX31_CS4_BASE_ADDR 0xb4000000 -#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000 #define MX31_CS4_SIZE SZ_32M #define MX31_CS5_BASE_ADDR 0xb6000000 -#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000 #define MX31_CS5_SIZE SZ_32M #define MX31_X_MEMC_BASE_ADDR 0xb8000000 -#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000 #define MX31_X_MEMC_SIZE SZ_64K #define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) #define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) @@ -121,12 +119,8 @@ #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 -#define MX31_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \ - IMX_IO_ADDRESS(x, MX31_AVIC) ?: \ - IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \ - IMX_IO_ADDRESS(x, MX31_SPBA0)) +#define MX31_IO_P2V(x) IMX_IO_P2V(x) +#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) #ifndef __ASSEMBLER__ static inline void mx31_setup_weimcs(size_t cs, @@ -143,8 +137,8 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_MPEG4_ENCODER 5 #define MX31_INT_RTIC 6 #define MX31_INT_FIRI 7 -#define MX31_INT_MMC_SDHC2 8 -#define MX31_INT_MMC_SDHC1 9 +#define MX31_INT_SDHC2 8 +#define MX31_INT_SDHC1 9 #define MX31_INT_I2C1 10 #define MX31_INT_SSI2 11 #define MX31_INT_SSI1 12 @@ -170,10 +164,9 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_UART2 32 #define MX31_INT_NFC 33 #define MX31_INT_SDMA 34 -#define MX31_INT_USB1 35 -#define MX31_INT_USB2 36 -#define MX31_INT_USB3 37 -#define MX31_INT_USB4 38 +#define MX31_INT_USB_HS1 35 +#define MX31_INT_USB_HS2 36 +#define MX31_INT_USB_OTG 37 #define MX31_INT_MSHC1 39 #define MX31_INT_MSHC2 40 #define MX31_INT_IPU_ERR 41 @@ -197,6 +190,8 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_EXT_WDOG 62 #define MX31_INT_EXT_TV 63 +#define MX31_DMA_REQ_SDHC1 20 +#define MX31_DMA_REQ_SDHC2 21 #define MX31_DMA_REQ_SSI2_RX1 22 #define MX31_DMA_REQ_SSI2_TX1 23 #define MX31_DMA_REQ_SSI2_RX0 24 @@ -208,52 +203,4 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ -/* silicon revisions specific to i.MX31 */ -#define MX31_CHIP_REV_1_0 0x10 -#define MX31_CHIP_REV_1_1 0x11 -#define MX31_CHIP_REV_1_2 0x12 -#define MX31_CHIP_REV_1_3 0x13 -#define MX31_CHIP_REV_2_0 0x20 -#define MX31_CHIP_REV_2_1 0x21 -#define MX31_CHIP_REV_2_2 0x22 -#define MX31_CHIP_REV_2_3 0x23 -#define MX31_CHIP_REV_3_0 0x30 -#define MX31_CHIP_REV_3_1 0x31 -#define MX31_CHIP_REV_3_2 0x32 - -#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 -#define MX31_SYSTEM_REV_NUM 3 - -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR -#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR -#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR -#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR -#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR -#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR -#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR -#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR -#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR -#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR -#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR -#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR -#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER -#define MXC_INT_FIRI MX31_INT_FIRI -#define MXC_INT_MBX MX31_INT_MBX -#define MXC_INT_CSPI3 MX31_INT_CSPI3 -#define MXC_INT_SIM2 MX31_INT_SIM2 -#define MXC_INT_SIM1 MX31_INT_SIM1 -#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS -#define MXC_INT_USB1 MX31_INT_USB1 -#define MXC_INT_USB2 MX31_INT_USB2 -#define MXC_INT_USB3 MX31_INT_USB3 -#define MXC_INT_USB4 MX31_INT_USB4 -#define MXC_INT_MSHC2 MX31_INT_MSHC2 -#define MXC_INT_UART4 MX31_INT_UART4 -#define MXC_INT_UART5 MX31_INT_UART5 -#define MXC_INT_CCM MX31_INT_CCM -#define MXC_INT_PCMCIA MX31_INT_PCMCIA -#endif - #endif /* ifndef __MACH_MX31_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 6267cff..d13dbfe 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -11,7 +11,6 @@ #define MX35_L2CC_SIZE SZ_1M #define MX35_AIPS1_BASE_ADDR 0x43f00000 -#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX35_AIPS1_SIZE SZ_1M #define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) #define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) @@ -33,7 +32,6 @@ #define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) #define MX35_SPBA0_BASE_ADDR 0x50000000 -#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000 #define MX35_SPBA0_SIZE SZ_1M #define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) #define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) @@ -44,7 +42,6 @@ #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) #define MX35_AIPS2_BASE_ADDR 0x53f00000 -#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX35_AIPS2_SIZE SZ_1M #define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) #define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) @@ -68,15 +65,19 @@ #define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) #define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) - -#define MX35_OTG_BASE_ADDR 0x53ff4000 +#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000) +#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000) +/* + * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for + * HS. When host support was implemented only a preliminary document was + * available, which told 0x400. This works fine. + */ +#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400) #define MX35_ROMP_BASE_ADDR 0x60000000 -#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000 #define MX35_ROMP_SIZE SZ_1M #define MX35_AVIC_BASE_ADDR 0x68000000 -#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX35_AVIC_SIZE SZ_1M /* @@ -92,18 +93,17 @@ #define MX35_CS3_BASE_ADDR 0xb2000000 #define MX35_CS4_BASE_ADDR 0xb4000000 -#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000 #define MX35_CS4_SIZE SZ_32M #define MX35_CS5_BASE_ADDR 0xb6000000 -#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000 #define MX35_CS5_SIZE SZ_32M /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX35_X_MEMC_BASE_ADDR 0xb8000000 -#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000 #define MX35_X_MEMC_SIZE SZ_64K #define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) #define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) @@ -114,12 +114,8 @@ #define MX35_NFC_BASE_ADDR 0xbb000000 #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 -#define MX35_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \ - IMX_IO_ADDRESS(x, MX35_AVIC) ?: \ - IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \ - IMX_IO_ADDRESS(x, MX35_SPBA0)) +#define MX35_IO_P2V(x) IMX_IO_P2V(x) +#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) /* * Interrupt numbers @@ -153,8 +149,8 @@ #define MX35_INT_UART2 32 #define MX35_INT_NFC 33 #define MX35_INT_SDMA 34 -#define MX35_INT_USBHS 35 -#define MX35_INT_USBOTG 37 +#define MX35_INT_USB_HS 35 +#define MX35_INT_USB_OTG 37 #define MX35_INT_MSHC1 39 #define MX35_INT_ESAI 40 #define MX35_INT_IPU_ERR 41 @@ -190,23 +186,4 @@ #define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ -#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 -#define MX35_SYSTEM_REV_NUM 3 - -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR -#define MXC_INT_OWIRE MX35_INT_OWIRE -#define MXC_INT_GPU2D MX35_INT_GPU2D -#define MXC_INT_ASRC MX35_INT_ASRC -#define MXC_INT_USBHS MX35_INT_USBHS -#define MXC_INT_USBOTG MX35_INT_USBOTG -#define MXC_INT_ESAI MX35_INT_ESAI -#define MXC_INT_CAN1 MX35_INT_CAN1 -#define MXC_INT_CAN2 MX35_INT_CAN2 -#define MXC_INT_MLB MX35_INT_MLB -#define MXC_INT_SPDIF MX35_INT_SPDIF -#define MXC_INT_FEC MX35_INT_FEC -#endif - #endif /* ifndef __MACH_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index d1bd26d..388a407 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -44,7 +44,6 @@ * AIPS 1 */ #define MX3x_AIPS1_BASE_ADDR 0x43f00000 -#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX3x_AIPS1_SIZE SZ_1M #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) @@ -69,7 +68,6 @@ * SPBA global module enabled #0 */ #define MX3x_SPBA0_BASE_ADDR 0x50000000 -#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000 #define MX3x_SPBA0_SIZE SZ_1M #define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) #define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) @@ -82,7 +80,6 @@ * AIPS 2 */ #define MX3x_AIPS2_BASE_ADDR 0x53f00000 -#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX3x_AIPS2_SIZE SZ_1M #define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) #define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) @@ -105,11 +102,9 @@ * ROMP and AVIC */ #define MX3x_ROMP_BASE_ADDR 0x60000000 -#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000 #define MX3x_ROMP_SIZE SZ_1M #define MX3x_AVIC_BASE_ADDR 0x68000000 -#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX3x_AVIC_SIZE SZ_1M /* @@ -125,18 +120,17 @@ #define MX3x_CS3_BASE_ADDR 0xb2000000 #define MX3x_CS4_BASE_ADDR 0xb4000000 -#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000 #define MX3x_CS4_SIZE SZ_32M #define MX3x_CS5_BASE_ADDR 0xb6000000 -#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000 #define MX3x_CS5_SIZE SZ_32M /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX3x_X_MEMC_BASE_ADDR 0xb8000000 -#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000 #define MX3x_X_MEMC_SIZE SZ_64K #define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) #define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) @@ -146,56 +140,6 @@ #define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 -/*! - * This macro defines the physical to virtual address mapping for all the - * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. If the physical address is not mapped, - * it returns 0xDEADBEEF - */ -#define IO_ADDRESS(x) \ - (void __force __iomem *) \ - (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ - ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ - ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ - ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ - ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ - ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ - ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ - 0xDEADBEEF) - -/* - * define the address mapping macros: in physical address order - */ -#define L2CC_IO_ADDRESS(x) \ - (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) - -#define AIPS1_IO_ADDRESS(x) \ - (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) - -#define SPBA0_IO_ADDRESS(x) \ - (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) - -#define AIPS2_IO_ADDRESS(x) \ - (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) - -#define ROMP_IO_ADDRESS(x) \ - (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) - -#define AVIC_IO_ADDRESS(x) \ - (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) - -#define CS4_IO_ADDRESS(x) \ - (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) - -#define CS5_IO_ADDRESS(x) \ - (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT) - -#define X_MEMC_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - -#define PCMCIA_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - /* * Interrupt numbers */ @@ -240,22 +184,6 @@ #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ -/* silicon revisions specific to i.MX31 and i.MX35 */ -#define MX3x_CHIP_REV_1_0 0x10 -#define MX3x_CHIP_REV_1_1 0x11 -#define MX3x_CHIP_REV_1_2 0x12 -#define MX3x_CHIP_REV_1_3 0x13 -#define MX3x_CHIP_REV_2_0 0x20 -#define MX3x_CHIP_REV_2_1 0x21 -#define MX3x_CHIP_REV_2_2 0x22 -#define MX3x_CHIP_REV_2_3 0x23 -#define MX3x_CHIP_REV_3_0 0x30 -#define MX3x_CHIP_REV_3_1 0x31 -#define MX3x_CHIP_REV_3_2 0x32 - -#define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 -#define MX3x_SYSTEM_REV_NUM 3 - /* Mandatory defines used globally */ #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) @@ -277,126 +205,4 @@ static inline int mx35_revision(void) } #endif -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR -#define L2CC_SIZE MX3x_L2CC_SIZE -#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR -#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT -#define AIPS1_SIZE MX3x_AIPS1_SIZE -#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR -#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR -#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR -#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR -#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR -#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR -#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR -#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR -#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR -#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR -#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR -#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR -#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR -#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR -#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR -#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR -#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR -#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR -#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT -#define SPBA0_SIZE MX3x_SPBA0_SIZE -#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR -#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR -#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR -#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR -#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR -#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR -#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR -#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT -#define AIPS2_SIZE MX3x_AIPS2_SIZE -#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR -#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR -#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR -#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR -#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR -#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR -#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR -#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR -#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR -#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR -#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR -#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR -#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR -#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR -#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR -#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR -#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR -#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT -#define ROMP_SIZE MX3x_ROMP_SIZE -#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR -#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT -#define AVIC_SIZE MX3x_AVIC_SIZE -#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR -#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR -#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR -#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR -#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR -#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR -#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR -#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR -#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT -#define CS4_SIZE MX3x_CS4_SIZE -#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR -#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT -#define CS5_SIZE MX3x_CS5_SIZE -#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR -#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT -#define X_MEMC_SIZE MX3x_X_MEMC_SIZE -#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR -#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR -#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR -#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR -#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR -#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR -#define MXC_INT_I2C3 MX3x_INT_I2C3 -#define MXC_INT_I2C2 MX3x_INT_I2C2 -#define MXC_INT_RTIC MX3x_INT_RTIC -#define MXC_INT_I2C MX3x_INT_I2C -#define MXC_INT_CSPI2 MX3x_INT_CSPI2 -#define MXC_INT_CSPI1 MX3x_INT_CSPI1 -#define MXC_INT_ATA MX3x_INT_ATA -#define MXC_INT_UART3 MX3x_INT_UART3 -#define MXC_INT_IIM MX3x_INT_IIM -#define MXC_INT_RNGA MX3x_INT_RNGA -#define MXC_INT_EVTMON MX3x_INT_EVTMON -#define MXC_INT_KPP MX3x_INT_KPP -#define MXC_INT_RTC MX3x_INT_RTC -#define MXC_INT_PWM MX3x_INT_PWM -#define MXC_INT_EPIT2 MX3x_INT_EPIT2 -#define MXC_INT_EPIT1 MX3x_INT_EPIT1 -#define MXC_INT_GPT MX3x_INT_GPT -#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL -#define MXC_INT_UART2 MX3x_INT_UART2 -#define MXC_INT_NANDFC MX3x_INT_NANDFC -#define MXC_INT_SDMA MX3x_INT_SDMA -#define MXC_INT_MSHC1 MX3x_INT_MSHC1 -#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR -#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN -#define MXC_INT_UART1 MX3x_INT_UART1 -#define MXC_INT_ECT MX3x_INT_ECT -#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM -#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN -#define MXC_INT_GPIO2 MX3x_INT_GPIO2 -#define MXC_INT_GPIO1 MX3x_INT_GPIO1 -#define MXC_INT_WDOG MX3x_INT_WDOG -#define MXC_INT_GPIO3 MX3x_INT_GPIO3 -#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER -#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER -#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60 -#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61 -#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG -#define MXC_INT_EXT_TV MX3x_INT_EXT_TV -#define PROD_SIGNATURE MX3x_PROD_SIGNATURE -#endif - #endif /* ifndef __MACH_MX3x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 2af7a10..8fddfef 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -2,31 +2,6 @@ #define __MACH_MX51_H__ /* - * MX51 memory map: - * - * - * Virt Phys Size What - * --------------------------------------------------------------------------- - * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM) - * 30000000 256M GPU - * 40000000 512M IPU - * fa200000 60000000 1M DEBUG - * fb100000 70000000 1M SPBA 0 - * fb000000 73f00000 1M AIPS 1 - * fb200000 83f00000 1M AIPS 2 - * 8fffc000 16K TZIC (interrupt controller) - * 90000000 256M CSD0 SDRAM/DDR - * a0000000 256M CSD1 SDRAM/DDR - * b0000000 128M CS0 Flash - * b8000000 128M CS1 Flash - * c0000000 128M CS2 Flash - * c8000000 64M CS3 Flash - * cc000000 32M CS4 SRAM - * ce000000 32M CS5 SRAM - * cfff0000 64K NFC (NAND Flash AXI) - */ - -/* * IROM */ #define MX51_IROM_BASE_ADDR 0x0 @@ -36,7 +11,6 @@ * IRAM */ #define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ -#define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000 #define MX51_IRAM_PARTITIONS 16 #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ @@ -45,7 +19,6 @@ #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 #define MX51_DEBUG_BASE_ADDR 0x60000000 -#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000 #define MX51_DEBUG_SIZE SZ_1M #define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) @@ -61,7 +34,6 @@ * SPBA global module enabled #0 */ #define MX51_SPBA0_BASE_ADDR 0x70000000 -#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000 #define MX51_SPBA0_SIZE SZ_1M #define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) @@ -81,7 +53,6 @@ * AIPS 1 */ #define MX51_AIPS1_BASE_ADDR 0x73f00000 -#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000 #define MX51_AIPS1_SIZE SZ_1M #define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) @@ -109,7 +80,6 @@ * AIPS 2 */ #define MX51_AIPS2_BASE_ADDR 0x83f00000 -#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000 #define MX51_AIPS2_SIZE SZ_1M #define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) @@ -163,16 +133,8 @@ #define MX51_GPU2D_BASE_ADDR 0xd0000000 #define MX51_TZIC_BASE_ADDR 0xe0000000 -#define MX51_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX51_IRAM) ?: \ - IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \ - IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \ - IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX51_AIPS2)) - -/* This is currently used in <mach/debug-macro.S>, but should go away */ -#define MX51_AIPS1_IO_ADDRESS(x) \ - (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT) +#define MX51_IO_P2V(x) IMX_IO_P2V(x) +#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) /* * defines for SPBA modules @@ -383,19 +345,6 @@ #define MX51_MXC_INT_EMI_NFC 101 #define MX51_MXC_INT_GPU_IDLE 102 -/* silicon revisions specific to i.MX51 */ -#define MX51_CHIP_REV_1_0 0x10 -#define MX51_CHIP_REV_1_1 0x11 -#define MX51_CHIP_REV_1_2 0x12 -#define MX51_CHIP_REV_1_3 0x13 -#define MX51_CHIP_REV_2_0 0x20 -#define MX51_CHIP_REV_2_1 0x21 -#define MX51_CHIP_REV_2_2 0x22 -#define MX51_CHIP_REV_2_3 0x23 -#define MX51_CHIP_REV_3_0 0x30 -#define MX51_CHIP_REV_3_1 0x31 -#define MX51_CHIP_REV_3_2 0x32 - #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) extern int mx51_revision(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h new file mode 100644 index 0000000..9577cdb --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -0,0 +1,353 @@ +#ifndef __MACH_MX53_H__ +#define __MACH_MX53_H__ + +/* + * IROM + */ +#define MX53_IROM_BASE_ADDR 0x0 +#define MX53_IROM_SIZE SZ_64K + +/* TZIC */ +#define MX53_TZIC_BASE_ADDR 0x0FFFC000 + +/* + * AHCI SATA + */ +#define MX53_SATA_BASE_ADDR 0x10000000 + +/* + * NFC + */ +#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */ +#define MX53_NFC_AXI_SIZE SZ_64K + +/* + * IRAM + */ +#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */ +#define MX53_IRAM_PARTITIONS 16 +#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */ + +/* + * Graphics Memory of GPU + */ +#define MX53_IPU_CTRL_BASE_ADDR 0x18000000 +#define MX53_GPU2D_BASE_ADDR 0x20000000 +#define MX53_GPU_BASE_ADDR 0x30000000 +#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000 + +#define MX53_DEBUG_BASE_ADDR 0x40000000 +#define MX53_DEBUG_SIZE SZ_1M +#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000) +#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000) +#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000) +#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000) +#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000) +#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000) +#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000) +#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000) + +/* + * SPBA global module enabled #0 + */ +#define MX53_SPBA0_BASE_ADDR 0x50000000 +#define MX53_SPBA0_SIZE SZ_1M + +#define MX53_MMC_SDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) +#define MX53_MMC_SDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) +#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) +#define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) +#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) +#define MX53_MMC_SDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) +#define MX53_MMC_SDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) +#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) +#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) +#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) +#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000) +#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000) +#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000) + +/* + * AIPS 1 + */ +#define MX53_AIPS1_BASE_ADDR 0x53F00000 +#define MX53_AIPS1_SIZE SZ_1M + +#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000) +#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000) +#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000) +#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) +#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) +#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) +#define MX53_WDOG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) +#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) +#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) +#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) +#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000) +#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000) +#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000) +#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000) +#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000) +#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000) +#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000) +#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000) +#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000) +#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000) +#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000) +#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000) +#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000) +#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000) +#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000) +#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000) + +/* + * AIPS 2 + */ +#define MX53_AIPS2_BASE_ADDR 0x63F00000 +#define MX53_AIPS2_SIZE SZ_1M + +#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000) +#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000) +#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000) +#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000) +#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000) +#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000) +#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000) +#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000) +#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) +#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) +#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) +#define MX53_CSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) +#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) +#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) +#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) +#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) +#define MX53_CSPI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) +#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) +#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) +#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) +#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000) +#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000) +#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000) +#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000) +#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000) +#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000) +#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00) +#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000) +#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000) +#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000) +#define MX53_MXC_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) +#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000) +#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000) +#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000) +#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000) + +/* + * Memory regions and CS + */ +#define MX53_CSD0_BASE_ADDR 0x90000000 +#define MX53_CSD1_BASE_ADDR 0xA0000000 +#define MX53_CS0_BASE_ADDR 0xB0000000 +#define MX53_CS1_BASE_ADDR 0xB8000000 +#define MX53_CS2_BASE_ADDR 0xC0000000 +#define MX53_CS3_BASE_ADDR 0xC8000000 +#define MX53_CS4_BASE_ADDR 0xCC000000 +#define MX53_CS5_BASE_ADDR 0xCE000000 + +#define MX53_IO_P2V(x) IMX_IO_P2V(x) +#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x)) + +/* + * defines for SPBA modules + */ +#define MX53_SPBA_SDHC1 0x04 +#define MX53_SPBA_SDHC2 0x08 +#define MX53_SPBA_UART3 0x0C +#define MX53_SPBA_CSPI1 0x10 +#define MX53_SPBA_SSI2 0x14 +#define MX53_SPBA_SDHC3 0x20 +#define MX53_SPBA_SDHC4 0x24 +#define MX53_SPBA_SPDIF 0x28 +#define MX53_SPBA_ATA 0x30 +#define MX53_SPBA_SLIM 0x34 +#define MX53_SPBA_HSI2C 0x38 +#define MX53_SPBA_CTRL 0x3C + +/* + * DMA request assignments + */ +#define MX53_DMA_REQ_SSI3_TX1 47 +#define MX53_DMA_REQ_SSI3_RX1 46 +#define MX53_DMA_REQ_SSI3_TX2 45 +#define MX53_DMA_REQ_SSI3_RX2 44 +#define MX53_DMA_REQ_UART3_TX 43 +#define MX53_DMA_REQ_UART3_RX 42 +#define MX53_DMA_REQ_ESAI_TX 41 +#define MX53_DMA_REQ_ESAI_RX 40 +#define MX53_DMA_REQ_CSPI_TX 39 +#define MX53_DMA_REQ_CSPI_RX 38 +#define MX53_DMA_REQ_ASRC_DMA6 37 +#define MX53_DMA_REQ_ASRC_DMA5 36 +#define MX53_DMA_REQ_ASRC_DMA4 35 +#define MX53_DMA_REQ_ASRC_DMA3 34 +#define MX53_DMA_REQ_ASRC_DMA2 33 +#define MX53_DMA_REQ_ASRC_DMA1 32 +#define MX53_DMA_REQ_EMI_WR 31 +#define MX53_DMA_REQ_EMI_RD 30 +#define MX53_DMA_REQ_SSI1_TX1 29 +#define MX53_DMA_REQ_SSI1_RX1 28 +#define MX53_DMA_REQ_SSI1_TX2 27 +#define MX53_DMA_REQ_SSI1_RX2 26 +#define MX53_DMA_REQ_SSI2_TX1 25 +#define MX53_DMA_REQ_SSI2_RX1 24 +#define MX53_DMA_REQ_SSI2_TX2 23 +#define MX53_DMA_REQ_SSI2_RX2 22 +#define MX53_DMA_REQ_I2C2_SDHC2 21 +#define MX53_DMA_REQ_I2C1_SDHC1 20 +#define MX53_DMA_REQ_UART1_TX 19 +#define MX53_DMA_REQ_UART1_RX 18 +#define MX53_DMA_REQ_UART5_TX 17 +#define MX53_DMA_REQ_UART5_RX 16 +#define MX53_DMA_REQ_SPDIF_TX 15 +#define MX53_DMA_REQ_SPDIF_RX 14 +#define MX53_DMA_REQ_UART2_FIRI_TX 13 +#define MX53_DMA_REQ_UART2_FIRI_RX 12 +#define MX53_DMA_REQ_SDHC4 11 +#define MX53_DMA_REQ_I2C3_SDHC3 10 +#define MX53_DMA_REQ_CSPI2_TX 9 +#define MX53_DMA_REQ_CSPI2_RX 8 +#define MX53_DMA_REQ_CSPI1_TX 7 +#define MX53_DMA_REQ_CSPI1_RX 6 +#define MX53_DMA_REQ_IPU 5 +#define MX53_DMA_REQ_ATA_TX_END 4 +#define MX53_DMA_REQ_ATA_UART4_TX 3 +#define MX53_DMA_REQ_ATA_UART4_RX 2 +#define MX53_DMA_REQ_GPC 1 +#define MX53_DMA_REQ_VPU 0 + +/* + * Interrupt numbers + */ +#define MX53_INT_RESV0 0 +#define MX53_INT_MMC_SDHC1 1 +#define MX53_INT_MMC_SDHC2 2 +#define MX53_INT_MMC_SDHC3 3 +#define MX53_INT_MMC_SDHC4 4 +#define MX53_INT_RESV5 5 +#define MX53_INT_SDMA 6 +#define MX53_INT_IOMUX 7 +#define MX53_INT_NFC 8 +#define MX53_INT_VPU 9 +#define MX53_INT_IPU_ERR 10 +#define MX53_INT_IPU_SYN 11 +#define MX53_INT_GPU 12 +#define MX53_INT_RESV13 13 +#define MX53_INT_USB_H1 14 +#define MX53_INT_EMI 15 +#define MX53_INT_USB_H2 16 +#define MX53_INT_USB_H3 17 +#define MX53_INT_USB_OTG 18 +#define MX53_INT_SAHARA_H0 19 +#define MX53_INT_SAHARA_H1 20 +#define MX53_INT_SCC_SMN 21 +#define MX53_INT_SCC_STZ 22 +#define MX53_INT_SCC_SCM 23 +#define MX53_INT_SRTC_NTZ 24 +#define MX53_INT_SRTC_TZ 25 +#define MX53_INT_RTIC 26 +#define MX53_INT_CSU 27 +#define MX53_INT_SATA 28 +#define MX53_INT_SSI1 29 +#define MX53_INT_SSI2 30 +#define MX53_INT_UART1 31 +#define MX53_INT_UART2 32 +#define MX53_INT_UART3 33 +#define MX53_INT_RESV34 34 +#define MX53_INT_RESV35 35 +#define MX53_INT_CSPI1 36 +#define MX53_INT_CSPI2 37 +#define MX53_INT_CSPI 38 +#define MX53_INT_GPT 39 +#define MX53_INT_EPIT1 40 +#define MX53_INT_EPIT2 41 +#define MX53_INT_GPIO1_INT7 42 +#define MX53_INT_GPIO1_INT6 43 +#define MX53_INT_GPIO1_INT5 44 +#define MX53_INT_GPIO1_INT4 45 +#define MX53_INT_GPIO1_INT3 46 +#define MX53_INT_GPIO1_INT2 47 +#define MX53_INT_GPIO1_INT1 48 +#define MX53_INT_GPIO1_INT0 49 +#define MX53_INT_GPIO1_LOW 50 +#define MX53_INT_GPIO1_HIGH 51 +#define MX53_INT_GPIO2_LOW 52 +#define MX53_INT_GPIO2_HIGH 53 +#define MX53_INT_GPIO3_LOW 54 +#define MX53_INT_GPIO3_HIGH 55 +#define MX53_INT_GPIO4_LOW 56 +#define MX53_INT_GPIO4_HIGH 57 +#define MX53_INT_WDOG1 58 +#define MX53_INT_WDOG2 59 +#define MX53_INT_KPP 60 +#define MX53_INT_PWM1 61 +#define MX53_INT_I2C1 62 +#define MX53_INT_I2C2 63 +#define MX53_INT_I2C3 64 +#define MX53_INT_RESV65 65 +#define MX53_INT_RESV66 66 +#define MX53_INT_SPDIF 67 +#define MX53_INT_SIM_DAT 68 +#define MX53_INT_IIM 69 +#define MX53_INT_ATA 70 +#define MX53_INT_CCM1 71 +#define MX53_INT_CCM2 72 +#define MX53_INT_GPC1 73 +#define MX53_INT_GPC2 74 +#define MX53_INT_SRC 75 +#define MX53_INT_NM 76 +#define MX53_INT_PMU 77 +#define MX53_INT_CTI_IRQ 78 +#define MX53_INT_CTI1_TG0 79 +#define MX53_INT_CTI1_TG1 80 +#define MX53_INT_ESAI 81 +#define MX53_INT_CAN1 82 +#define MX53_INT_CAN2 83 +#define MX53_INT_GPU2_IRQ 84 +#define MX53_INT_GPU2_BUSY 85 +#define MX53_INT_RESV86 86 +#define MX53_INT_FEC 87 +#define MX53_INT_OWIRE 88 +#define MX53_INT_CTI1_TG2 89 +#define MX53_INT_SJC 90 +#define MX53_INT_TVE 92 +#define MX53_INT_FIRI 93 +#define MX53_INT_PWM2 94 +#define MX53_INT_SLIM_EXP 95 +#define MX53_INT_SSI3 96 +#define MX53_INT_EMI_BOOT 97 +#define MX53_INT_CTI1_TG3 98 +#define MX53_INT_SMC_RX 99 +#define MX53_INT_VPU_IDLE 100 +#define MX53_INT_EMI_NFC 101 +#define MX53_INT_GPU_IDLE 102 +#define MX53_INT_GPIO5_LOW 103 +#define MX53_INT_GPIO5_HIGH 104 +#define MX53_INT_GPIO6_LOW 105 +#define MX53_INT_GPIO6_HIGH 106 +#define MX53_INT_GPIO7_LOW 107 +#define MX53_INT_GPIO7_HIGH 108 + +/* silicon revisions specific to i.MX53 */ +#define MX53_CHIP_REV_1_0 0x10 +#define MX53_CHIP_REV_1_1 0x11 +#define MX53_CHIP_REV_1_2 0x12 +#define MX53_CHIP_REV_1_3 0x13 +#define MX53_CHIP_REV_2_0 0x20 +#define MX53_CHIP_REV_2_1 0x21 +#define MX53_CHIP_REV_2_2 0x22 +#define MX53_CHIP_REV_2_3 0x23 +#define MX53_CHIP_REV_3_0 0x30 +#define MX53_CHIP_REV_3_1 0x31 +#define MX53_CHIP_REV_3_2 0x32 + +#endif /* ifndef __MACH_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index a42c720..4abbdd1 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -33,8 +33,23 @@ #define MXC_CPU_MX31 31 #define MXC_CPU_MX35 35 #define MXC_CPU_MX51 51 +#define MXC_CPU_MX53 53 #define MXC_CPU_MXC91231 91231 +#define IMX_CHIP_REVISION_1_0 0x10 +#define IMX_CHIP_REVISION_1_1 0x11 +#define IMX_CHIP_REVISION_1_2 0x12 +#define IMX_CHIP_REVISION_1_3 0x13 +#define IMX_CHIP_REVISION_2_0 0x20 +#define IMX_CHIP_REVISION_2_1 0x21 +#define IMX_CHIP_REVISION_2_2 0x22 +#define IMX_CHIP_REVISION_2_3 0x23 +#define IMX_CHIP_REVISION_3_0 0x30 +#define IMX_CHIP_REVISION_3_1 0x31 +#define IMX_CHIP_REVISION_3_2 0x32 +#define IMX_CHIP_REVISION_3_3 0x33 +#define IMX_CHIP_REVISION_UNKNOWN 0xff + #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; #endif @@ -119,6 +134,7 @@ extern unsigned int __mxc_cpu_type; # define mxc_cpu_type MXC_CPU_MX51 # endif # define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51) +# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) #else # define cpu_is_mx51() (0) #endif diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 0ca3101..765190f 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h @@ -21,14 +21,12 @@ * L2CC */ #define MXC91231_L2CC_BASE_ADDR 0x30000000 -#define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000 #define MXC91231_L2CC_SIZE SZ_64K /* * AIPS 1 */ #define MXC91231_AIPS1_BASE_ADDR 0x43F00000 -#define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000 #define MXC91231_AIPS1_SIZE SZ_1M #define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR @@ -53,7 +51,6 @@ * AIPS 2 */ #define MXC91231_AIPS2_BASE_ADDR 0x53F00000 -#define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000 #define MXC91231_AIPS2_SIZE SZ_1M #define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) @@ -79,7 +76,6 @@ * SPBA global module 0 */ #define MXC91231_SPBA0_BASE_ADDR 0x50000000 -#define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000 #define MXC91231_SPBA0_SIZE SZ_1M #define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) @@ -109,7 +105,6 @@ * SPBA global module 1 */ #define MXC91231_SPBA1_BASE_ADDR 0x52000000 -#define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000 #define MXC91231_SPBA1_SIZE SZ_1M #define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) @@ -144,18 +139,15 @@ * ROMP and AVIC */ #define MXC91231_ROMP_BASE_ADDR 0x60000000 -#define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000 #define MXC91231_ROMP_SIZE SZ_64K #define MXC91231_AVIC_BASE_ADDR 0x68000000 -#define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000 #define MXC91231_AVIC_SIZE SZ_64K /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 -#define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000 #define MXC91231_X_MEMC_SIZE SZ_64K #define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) @@ -183,19 +175,10 @@ /* * This macro defines the physical to virtual address mapping for all the * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. If the physical address is not mapped, - * it returns 0. + * and returning the virtual address. */ - -#define MXC91231_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \ - IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \ - IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \ - IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \ - IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \ - IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \ - IMX_IO_ADDRESS(x, MXC91231_AIPS2)) +#define MXC91231_IO_P2V(x) IMX_IO_P2V(x) +#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x)) /* * Interrupt numbers diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h index 9be1122..913e043 100644 --- a/arch/arm/plat-mxc/include/mach/sdma.h +++ b/arch/arm/plat-mxc/include/mach/sdma.h @@ -2,16 +2,62 @@ #define __MACH_MXC_SDMA_H__ /** + * struct sdma_script_start_addrs - SDMA script start pointers + * + * start addresses of the different functions in the physical + * address space of the SDMA engine. + */ +struct sdma_script_start_addrs { + s32 ap_2_ap_addr; + s32 ap_2_bp_addr; + s32 ap_2_ap_fixed_addr; + s32 bp_2_ap_addr; + s32 loopback_on_dsp_side_addr; + s32 mcu_interrupt_only_addr; + s32 firi_2_per_addr; + s32 firi_2_mcu_addr; + s32 per_2_firi_addr; + s32 mcu_2_firi_addr; + s32 uart_2_per_addr; + s32 uart_2_mcu_addr; + s32 per_2_app_addr; + s32 mcu_2_app_addr; + s32 per_2_per_addr; + s32 uartsh_2_per_addr; + s32 uartsh_2_mcu_addr; + s32 per_2_shp_addr; + s32 mcu_2_shp_addr; + s32 ata_2_mcu_addr; + s32 mcu_2_ata_addr; + s32 app_2_per_addr; + s32 app_2_mcu_addr; + s32 shp_2_per_addr; + s32 shp_2_mcu_addr; + s32 mshc_2_mcu_addr; + s32 mcu_2_mshc_addr; + s32 spdif_2_mcu_addr; + s32 mcu_2_spdif_addr; + s32 asrc_2_mcu_addr; + s32 ext_mem_2_ipu_addr; + s32 descrambler_addr; + s32 dptc_dvfs_addr; + s32 utra_addr; + s32 ram_code_start_addr; +}; + +/** * struct sdma_platform_data - platform specific data for SDMA engine * * @sdma_version The version of this SDMA engine * @cpu_name used to generate the firmware name * @to_version CPU Tape out version + * @script_addrs SDMA scripts addresses in SDMA ROM */ struct sdma_platform_data { int sdma_version; char *cpu_name; int to_version; + struct sdma_script_start_addrs *script_addrs; }; #endif /* __MACH_MXC_SDMA_H__ */ diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c index b318c6a..4cbbf2c 100644 --- a/arch/arm/plat-mxc/iomux-v3.c +++ b/arch/arm/plat-mxc/iomux-v3.c @@ -32,26 +32,26 @@ static void __iomem *base; /* - * setups a single pad in the iomuxer + * configures a single pad in the iomuxer */ -int mxc_iomux_v3_setup_pad(struct pad_desc *pad) +int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t *pad) { - if (pad->mux_ctrl_ofs) - __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs); + if (MUX_CTRL_OFS(pad)) + __raw_writel(MUX_MODE(pad), base + MUX_CTRL_OFS(pad)); - if (pad->select_input_ofs) - __raw_writel(pad->select_input, - base + pad->select_input_ofs); + if (MUX_SELECT_INPUT_OFS(pad)) + __raw_writel(MUX_SELECT_INPUT(pad), + base + MUX_SELECT_INPUT_OFS(pad)); - if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs) - __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs); + if (!(MUX_PAD_CTRL(pad) & NO_PAD_CTRL) && MUX_PAD_CTRL_OFS(pad)) + __raw_writel(MUX_PAD_CTRL(pad), base + MUX_PAD_CTRL_OFS(pad)); return 0; } EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); -int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count) +int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) { - struct pad_desc *p = pad_list; + iomux_v3_cfg_t *p = pad_list; int i; int ret; diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 925bce4..c3972c5 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -26,6 +26,7 @@ #include <mach/common.h> #include <asm/proc-fns.h> #include <asm/system.h> +#include <asm/mach-types.h> static void __iomem *wdog_base; @@ -42,6 +43,13 @@ void arch_reset(char mode, const char *cmd) return; } #endif +#ifdef CONFIG_MACH_MX51_EFIKAMX + if (machine_is_mx51_efikamx()) { + mx51_efikamx_reset(); + return; + } +#endif + if (cpu_is_mx1()) { wcr_enable = (1 << 0); } else { |