diff options
Diffstat (limited to 'arch/arm')
277 files changed, 5557 insertions, 12851 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 67874b8..2ec4ff3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -393,6 +393,7 @@ config ARCH_GEMINI config ARCH_SIRF bool "CSR SiRF" select ARCH_REQUIRE_GPIOLIB + select AUTO_ZRELADDR select COMMON_CLK select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP @@ -640,8 +641,10 @@ config ARCH_LPC32XX config ARCH_TEGRA bool "NVIDIA Tegra" select ARCH_HAS_CPUFREQ + select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP select CLKSRC_MMIO + select CLKSRC_OF select COMMON_CLK select GENERIC_CLOCKEVENTS select GENERIC_GPIO @@ -949,22 +952,6 @@ config ARCH_OMAP help Support for TI's OMAP platform (OMAP1/2/3/4). -config ARCH_VT8500_SINGLE - bool "VIA/WonderMedia 85xx" - select ARCH_HAS_CPUFREQ - select ARCH_REQUIRE_GPIOLIB - select CLKDEV_LOOKUP - select COMMON_CLK - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select GENERIC_GPIO - select HAVE_CLK - select MULTI_IRQ_HANDLER - select SPARSE_IRQ - select USE_OF - help - Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. - endchoice menu "Multiple platform selection" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 661030d..305ceb8 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -205,12 +205,19 @@ choice Say Y here if you want kernel low-level debugging support on i.MX28. - config DEBUG_IMX31_IMX35_UART - bool "i.MX31 and i.MX35 Debug UART" - depends on SOC_IMX31 || SOC_IMX35 + config DEBUG_IMX31_UART + bool "i.MX31 Debug UART" + depends on SOC_IMX31 help Say Y here if you want kernel low-level debugging support - on i.MX31 or i.MX35. + on i.MX31. + + config DEBUG_IMX35_UART + bool "i.MX35 Debug UART" + depends on SOC_IMX35 + help + Say Y here if you want kernel low-level debugging support + on i.MX35. config DEBUG_IMX51_UART bool "i.MX51 Debug UART" @@ -219,12 +226,12 @@ choice Say Y here if you want kernel low-level debugging support on i.MX51. - config DEBUG_IMX50_IMX53_UART - bool "i.MX50 and i.MX53 Debug UART" - depends on SOC_IMX50 || SOC_IMX53 + config DEBUG_IMX53_UART + bool "i.MX53 Debug UART" + depends on SOC_IMX53 help Say Y here if you want kernel low-level debugging support - on i.MX50 or i.MX53. + on i.MX53. config DEBUG_IMX6Q_UART bool "i.MX6Q Debug UART" @@ -386,6 +393,20 @@ choice Say Y here if you want kernel low-level debugging support on Tegra based platforms. + config DEBUG_SIRFPRIMA2_UART1 + bool "Kernel low-level debugging messages via SiRFprimaII UART1" + depends on ARCH_PRIMA2 + help + Say Y here if you want the debug print routines to direct + their output to the uart1 port on SiRFprimaII devices. + + config DEBUG_SIRFMARCO_UART1 + bool "Kernel low-level debugging messages via SiRFmarco UART1" + depends on ARCH_MARCO + help + Say Y here if you want the debug print routines to direct + their output to the uart1 port on SiRFmarco devices. + config DEBUG_VEXPRESS_UART0_DETECT bool "Autodetect UART0 on Versatile Express Cortex-A core tiles" depends on ARCH_VEXPRESS && CPU_CP15_MMU @@ -412,6 +433,13 @@ choice of the tiles using the RS1 memory map, including all new A-class core tiles, FPGA-based SMMs and software models. + config DEBUG_VT8500_UART0 + bool "Use UART0 on VIA/Wondermedia SoCs" + depends on ARCH_VT8500 + help + This option selects UART0 on VIA/Wondermedia System-on-a-chip + devices, including VT8500, WM8505, WM8650 and WM8850. + config DEBUG_LL_UART_NONE bool "No low-level debugging UART" depends on !ARCH_MULTIPLATFORM @@ -450,11 +478,16 @@ choice endchoice -config DEBUG_IMX6Q_UART_PORT - int "i.MX6Q Debug UART Port (1-5)" if DEBUG_IMX6Q_UART - range 1 5 +config DEBUG_IMX_UART_PORT + int "i.MX Debug UART Port Selection" if DEBUG_IMX1_UART || \ + DEBUG_IMX25_UART || \ + DEBUG_IMX21_IMX27_UART || \ + DEBUG_IMX31_UART || \ + DEBUG_IMX35_UART || \ + DEBUG_IMX51_UART || \ + DEBUG_IMX50_IMX53_UART || \ + DEBUG_IMX6Q_UART default 1 - depends on SOC_IMX6Q help Choose UART port on which kernel low-level debug messages should be output. @@ -495,9 +528,10 @@ config DEBUG_LL_INCLUDE default "debug/imx.S" if DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \ DEBUG_IMX21_IMX27_UART || \ - DEBUG_IMX31_IMX35_UART || \ + DEBUG_IMX31_UART || \ + DEBUG_IMX35_UART || \ DEBUG_IMX51_UART || \ - DEBUG_IMX50_IMX53_UART ||\ + DEBUG_IMX53_UART ||\ DEBUG_IMX6Q_UART default "debug/highbank.S" if DEBUG_HIGHBANK_UART default "debug/mvebu.S" if DEBUG_MVEBU_UART @@ -506,6 +540,7 @@ config DEBUG_LL_INCLUDE default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 + default "debug/vt8500.S" if DEBUG_VT8500_UART0 default "debug/tegra.S" if DEBUG_TEGRA_UART default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 default "mach/debug-macro.S" diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e44da40..042f211 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \ kirkwood-ts219-6281.dtb \ kirkwood-ts219-6282.dtb \ kirkwood-openblocks_a6.dtb +dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ msm8960-cdp.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ @@ -124,6 +125,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a7740-armadillo800eva.dtb \ sh73a0-kzm9g.dtb \ sh7372-mackerel.dtb +dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \ + socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ spear1340-evb.dtb dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ @@ -143,7 +146,9 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-ventana.dtb \ tegra20-whistler.dtb \ tegra30-cardhu-a02.dtb \ - tegra30-cardhu-a04.dtb + tegra30-cardhu-a04.dtb \ + tegra114-dalmore.dtb \ + tegra114-pluto.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ vexpress-v2p-ca9.dtb \ vexpress-v2p-ca15-tc1.dtb \ @@ -151,10 +156,12 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ xenvm-4.2.dtb dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ wm8505-ref.dtb \ - wm8650-mid.dtb + wm8650-mid.dtb \ + wm8850-w70v2.dtb dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb targets += dtbs +targets += $(dtb-y) endif # *.dtb used to be generated in the directory above. Clean out the diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 0004402..9b82fac 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -26,7 +26,7 @@ memory { device_type = "memory"; - reg = <0x00000000 0x20000000>; /* 512 MB */ + reg = <0x00000000 0x40000000>; /* 1 GB */ }; soc { diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 271855a..e041f42 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -50,27 +50,25 @@ }; gpio0: gpio@d0018100 { - compatible = "marvell,armadaxp-gpio"; - reg = <0xd0018100 0x40>, - <0xd0018800 0x30>; + compatible = "marvell,orion-gpio"; + reg = <0xd0018100 0x40>; ngpios = <32>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupts-cells = <2>; - interrupts = <16>, <17>, <18>, <19>; + interrupts = <82>, <83>, <84>, <85>; }; gpio1: gpio@d0018140 { - compatible = "marvell,armadaxp-gpio"; - reg = <0xd0018140 0x40>, - <0xd0018840 0x30>; + compatible = "marvell,orion-gpio"; + reg = <0xd0018140 0x40>; ngpios = <17>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupts-cells = <2>; - interrupts = <20>, <21>, <22>; + interrupts = <87>, <88>, <89>; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 1c1937d..9e23bd8 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -51,39 +51,36 @@ }; gpio0: gpio@d0018100 { - compatible = "marvell,armadaxp-gpio"; - reg = <0xd0018100 0x40>, - <0xd0018800 0x30>; + compatible = "marvell,orion-gpio"; + reg = <0xd0018100 0x40>; ngpios = <32>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupts-cells = <2>; - interrupts = <16>, <17>, <18>, <19>; + interrupts = <82>, <83>, <84>, <85>; }; gpio1: gpio@d0018140 { - compatible = "marvell,armadaxp-gpio"; - reg = <0xd0018140 0x40>, - <0xd0018840 0x30>; + compatible = "marvell,orion-gpio"; + reg = <0xd0018140 0x40>; ngpios = <32>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupts-cells = <2>; - interrupts = <20>, <21>, <22>, <23>; + interrupts = <87>, <88>, <89>, <90>; }; gpio2: gpio@d0018180 { - compatible = "marvell,armadaxp-gpio"; - reg = <0xd0018180 0x40>, - <0xd0018870 0x30>; + compatible = "marvell,orion-gpio"; + reg = <0xd0018180 0x40>; ngpios = <3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupts-cells = <2>; - interrupts = <24>; + interrupts = <91>; }; ethernet@d0034000 { diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 4905cf3..9659661 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -66,39 +66,36 @@ }; gpio0: gpio@d0018100 { - compatible = "marvell,armadaxp-gpio"; - reg = <0xd0018100 0x40>, - <0xd0018800 0x30>; + compatible = "marvell,orion-gpio"; + reg = <0xd0018100 0x40>; ngpios = <32>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupts-cells = <2>; - interrupts = <16>, <17>, <18>, <19>; + interrupts = <82>, <83>, <84>, <85>; }; gpio1: gpio@d0018140 { - compatible = "marvell,armadaxp-gpio"; - reg = <0xd0018140 0x40>, - <0xd0018840 0x30>; + compatible = "marvell,orion-gpio"; + reg = <0xd0018140 0x40>; ngpios = <32>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupts-cells = <2>; - interrupts = <20>, <21>, <22>, <23>; + interrupts = <87>, <88>, <89>, <90>; }; gpio2: gpio@d0018180 { - compatible = "marvell,armadaxp-gpio"; - reg = <0xd0018180 0x40>, - <0xd0018870 0x30>; + compatible = "marvell,orion-gpio"; + reg = <0xd0018180 0x40>; ngpios = <3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupts-cells = <2>; - interrupts = <24>; + interrupts = <91>; }; ethernet@d0034000 { diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index e154f24..222047f 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -336,8 +336,8 @@ i2c@0 { compatible = "i2c-gpio"; - gpios = <&pioA 23 0 /* sda */ - &pioA 24 0 /* scl */ + gpios = <&pioA 25 0 /* sda */ + &pioA 26 0 /* scl */ >; i2c-gpio,sda-open-drain; i2c-gpio,scl-open-drain; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 68bccf4..cb7bcc5 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -306,6 +306,22 @@ }; }; + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + <1 16 0x1 0x0 /* PB16 periph A */ + 1 17 0x1 0x0 /* PB17 periph A */ + 1 18 0x1 0x0>; /* PB18 periph A */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + <1 19 0x1 0x0 /* PB19 periph A */ + 1 20 0x1 0x0 /* PB20 periph A */ + 1 21 0x1 0x0>; /* PB21 periph A */ + }; + }; + pioA: gpio@fffff400 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; @@ -450,6 +466,8 @@ compatible = "atmel,at91rm9200-ssc"; reg = <0xfffbc000 0x4000>; interrupts = <14 4 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 32ec62c..271d4de 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -271,6 +271,38 @@ }; }; + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + <1 0 0x2 0x0 /* PB0 periph B */ + 1 1 0x2 0x0 /* PB1 periph B */ + 1 2 0x2 0x0>; /* PB2 periph B */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + <1 3 0x2 0x0 /* PB3 periph B */ + 1 4 0x2 0x0 /* PB4 periph B */ + 1 5 0x2 0x0>; /* PB5 periph B */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx-0 { + atmel,pins = + <1 6 0x1 0x0 /* PB6 periph A */ + 1 7 0x1 0x0 /* PB7 periph A */ + 1 8 0x1 0x0>; /* PB8 periph A */ + }; + + pinctrl_ssc1_rx: ssc1_rx-0 { + atmel,pins = + <1 9 0x1 0x0 /* PB9 periph A */ + 1 10 0x1 0x0 /* PB10 periph A */ + 1 11 0x1 0x0>; /* PB11 periph A */ + }; + }; + pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; @@ -368,6 +400,8 @@ compatible = "atmel,at91rm9200-ssc"; reg = <0xfff98000 0x4000>; interrupts = <16 4 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; }; @@ -375,6 +409,8 @@ compatible = "atmel,at91rm9200-ssc"; reg = <0xfff9c000 0x4000>; interrupts = <17 4 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 231858f..6b1d4ca 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -290,6 +290,38 @@ }; }; + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + <3 0 0x1 0x0 /* PD0 periph A */ + 3 1 0x1 0x0 /* PD1 periph A */ + 3 2 0x1 0x0>; /* PD2 periph A */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + <3 3 0x1 0x0 /* PD3 periph A */ + 3 4 0x1 0x0 /* PD4 periph A */ + 3 5 0x1 0x0>; /* PD5 periph A */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx-0 { + atmel,pins = + <3 10 0x1 0x0 /* PD10 periph A */ + 3 11 0x1 0x0 /* PD11 periph A */ + 3 12 0x1 0x0>; /* PD12 periph A */ + }; + + pinctrl_ssc1_rx: ssc1_rx-0 { + atmel,pins = + <3 13 0x1 0x0 /* PD13 periph A */ + 3 14 0x1 0x0 /* PD14 periph A */ + 3 15 0x1 0x0>; /* PD15 periph A */ + }; + }; + pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; @@ -425,6 +457,8 @@ compatible = "atmel,at91sam9g45-ssc"; reg = <0xfff9c000 0x4000>; interrupts = <16 4 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; status = "disabled"; }; @@ -432,6 +466,8 @@ compatible = "atmel,at91sam9g45-ssc"; reg = <0xfffa0000 0x4000>; interrupts = <17 4 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index e9efb34..80e29c6 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -28,6 +28,7 @@ tcb1 = &tcb1; i2c0 = &i2c0; i2c1 = &i2c1; + ssc0 = &ssc0; }; cpus { cpu@0 { @@ -244,6 +245,22 @@ }; }; + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + <0 24 0x2 0x0 /* PA24 periph B */ + 0 25 0x2 0x0 /* PA25 periph B */ + 0 26 0x2 0x0>; /* PA26 periph B */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + <0 27 0x2 0x0 /* PA27 periph B */ + 0 28 0x2 0x0 /* PA28 periph B */ + 0 29 0x2 0x0>; /* PA29 periph B */ + }; + }; + pioA: gpio@fffff400 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; @@ -294,6 +311,15 @@ status = "disabled"; }; + ssc0: ssc@f0010000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf0010000 0x4000>; + interrupts = <28 4 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + status = "disabled"; + }; + usart0: serial@f801c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x4000>; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 40ac3a4..8ecca69 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -88,13 +88,6 @@ interrupts = <1 4 7>; }; - ssc0: ssc@f0010000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0010000 0x4000>; - interrupts = <28 4 5>; - status = "disabled"; - }; - tcb0: timer@f8008000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8008000 0x100>; @@ -150,6 +143,11 @@ atmel,pins = <0 3 0x1 0x0>; /* PA3 periph A */ }; + + pinctrl_usart0_sck: usart0_sck-0 { + atmel,pins = + <0 4 0x1 0x0>; /* PA4 periph A */ + }; }; usart1 { @@ -161,12 +159,17 @@ pinctrl_usart1_rts: usart1_rts-0 { atmel,pins = - <3 27 0x3 0x0>; /* PC27 periph C */ + <2 27 0x3 0x0>; /* PC27 periph C */ }; pinctrl_usart1_cts: usart1_cts-0 { atmel,pins = - <3 28 0x3 0x0>; /* PC28 periph C */ + <2 28 0x3 0x0>; /* PC28 periph C */ + }; + + pinctrl_usart1_sck: usart1_sck-0 { + atmel,pins = + <2 28 0x3 0x0>; /* PC29 periph C */ }; }; @@ -179,46 +182,56 @@ pinctrl_uart2_rts: uart2_rts-0 { atmel,pins = - <0 0 0x2 0x0>; /* PB0 periph B */ + <1 0 0x2 0x0>; /* PB0 periph B */ }; pinctrl_uart2_cts: uart2_cts-0 { atmel,pins = - <0 1 0x2 0x0>; /* PB1 periph B */ + <1 1 0x2 0x0>; /* PB1 periph B */ + }; + + pinctrl_usart2_sck: usart2_sck-0 { + atmel,pins = + <1 2 0x2 0x0>; /* PB2 periph B */ }; }; usart3 { pinctrl_uart3: usart3-0 { atmel,pins = - <3 23 0x2 0x1 /* PC22 periph B with pullup */ - 3 23 0x2 0x0>; /* PC23 periph B */ + <2 23 0x2 0x1 /* PC22 periph B with pullup */ + 2 23 0x2 0x0>; /* PC23 periph B */ }; pinctrl_usart3_rts: usart3_rts-0 { atmel,pins = - <3 24 0x2 0x0>; /* PC24 periph B */ + <2 24 0x2 0x0>; /* PC24 periph B */ }; pinctrl_usart3_cts: usart3_cts-0 { atmel,pins = - <3 25 0x2 0x0>; /* PC25 periph B */ + <2 25 0x2 0x0>; /* PC25 periph B */ + }; + + pinctrl_usart3_sck: usart3_sck-0 { + atmel,pins = + <2 26 0x2 0x0>; /* PC26 periph B */ }; }; uart0 { pinctrl_uart0: uart0-0 { atmel,pins = - <3 8 0x3 0x0 /* PC8 periph C */ - 3 9 0x3 0x1>; /* PC9 periph C with pullup */ + <2 8 0x3 0x0 /* PC8 periph C */ + 2 9 0x3 0x1>; /* PC9 periph C with pullup */ }; }; uart1 { pinctrl_uart1: uart1-0 { atmel,pins = - <3 16 0x3 0x0 /* PC16 periph C */ - 3 17 0x3 0x1>; /* PC17 periph C with pullup */ + <2 16 0x3 0x0 /* PC16 periph C */ + 2 17 0x3 0x1>; /* PC17 periph C with pullup */ }; }; @@ -247,14 +260,14 @@ pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { atmel,pins = - <1 8 0x1 0x0 /* PA8 periph A */ - 1 11 0x1 0x0 /* PA11 periph A */ - 1 12 0x1 0x0 /* PA12 periph A */ - 1 13 0x1 0x0 /* PA13 periph A */ - 1 14 0x1 0x0 /* PA14 periph A */ - 1 15 0x1 0x0 /* PA15 periph A */ - 1 16 0x1 0x0 /* PA16 periph A */ - 1 17 0x1 0x0>; /* PA17 periph A */ + <1 8 0x1 0x0 /* PB8 periph A */ + 1 11 0x1 0x0 /* PB11 periph A */ + 1 12 0x1 0x0 /* PB12 periph A */ + 1 13 0x1 0x0 /* PB13 periph A */ + 1 14 0x1 0x0 /* PB14 periph A */ + 1 15 0x1 0x0 /* PB15 periph A */ + 1 16 0x1 0x0 /* PB16 periph A */ + 1 17 0x1 0x0>; /* PB17 periph A */ }; }; @@ -290,6 +303,22 @@ }; }; + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + <0 24 0x2 0x0 /* PA24 periph B */ + 0 25 0x2 0x0 /* PA25 periph B */ + 0 26 0x2 0x0>; /* PA26 periph B */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + <0 27 0x2 0x0 /* PA27 periph B */ + 0 28 0x2 0x0 /* PA28 periph B */ + 0 29 0x2 0x0>; /* PA29 periph B */ + }; + }; + pioA: gpio@fffff400 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; @@ -333,6 +362,15 @@ }; }; + ssc0: ssc@f0010000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf0010000 0x4000>; + interrupts = <28 4 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + status = "disabled"; + }; + mmc0: mmc@f0008000 { compatible = "atmel,hsmci"; reg = <0xf0008000 0x600>; diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi index fddd174..46c0980 100644 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ b/arch/arm/boot/dts/cros5250-common.dtsi @@ -96,8 +96,8 @@ fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3 3>; - samsung,dw-mshc-ddr-timing = <1 2 3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>; @@ -120,8 +120,8 @@ fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3 3>; - samsung,dw-mshc-ddr-timing = <1 2 3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>; @@ -141,8 +141,8 @@ fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3 3>; - samsung,dw-mshc-ddr-timing = <1 2 3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index fed7d3f..cdee96f 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -26,10 +26,15 @@ }; &uart0 { status = "okay"; }; -&sdio0 { status = "okay"; }; &sata0 { status = "okay"; }; &i2c0 { status = "okay"; }; +&sdio0 { + status = "okay"; + /* sdio0 card detect is connected to wrong pin on CuBox */ + cd-gpios = <&gpio0 12 1>; +}; + &spi0 { status = "okay"; @@ -42,9 +47,14 @@ }; &pinctrl { - pinctrl-0 = <&pmx_gpio_18>; + pinctrl-0 = <&pmx_gpio_12 &pmx_gpio_18>; pinctrl-names = "default"; + pmx_gpio_12: pmx-gpio-12 { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + pmx_gpio_18: pmx-gpio-18 { marvell,pins = "mpp18"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 42eac1f..740630f 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -93,6 +93,7 @@ reg = <0xd0400 0x20>; ngpios = <32>; interrupt-controller; + #interrupt-cells = <2>; interrupts = <12>, <13>, <14>, <60>; }; @@ -103,6 +104,7 @@ reg = <0xd0420 0x20>; ngpios = <32>; interrupt-controller; + #interrupt-cells = <2>; interrupts = <61>; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 942d576..e05b18f 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -115,8 +115,8 @@ fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3 3>; - samsung,dw-mshc-ddr-timing = <1 2 3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>; @@ -139,8 +139,8 @@ fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3 3>; - samsung,dw-mshc-ddr-timing = <1 2 3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index eef7099..454c2d1 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -45,6 +45,8 @@ compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43f90000 0x4000>; interrupts = <45>; + clocks = <&clks 10>, <&clks 30>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -52,12 +54,16 @@ compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43f94000 0x4000>; interrupts = <32>; + clocks = <&clks 10>, <&clks 31>; + clock-names = "ipg", "per"; status = "disabled"; }; uart4: serial@43fb0000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43fb0000 0x4000>; + clocks = <&clks 10>, <&clks 49>; + clock-names = "ipg", "per"; interrupts = <46>; status = "disabled"; }; @@ -66,6 +72,8 @@ compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43fb4000 0x4000>; interrupts = <47>; + clocks = <&clks 10>, <&clks 50>; + clock-names = "ipg", "per"; status = "disabled"; }; }; @@ -81,8 +89,17 @@ compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; interrupts = <18>; + clocks = <&clks 10>, <&clks 48>; + clock-names = "ipg", "per"; status = "disabled"; }; + + clks: ccm@53f80000{ + compatible = "fsl,imx31-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <0 31 0x04 0 53 0x04>; + #clock-cells = <1>; + }; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index 9bc6785..77d21ab 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -1,4 +1,5 @@ /include/ "kirkwood.dtsi" +/include/ "kirkwood-6281.dtsi" / { chosen { @@ -6,6 +7,21 @@ }; ocp@f1000000 { + pinctrl: pinctrl@10000 { + pinctrl-0 = < &pmx_spi &pmx_twsi0 &pmx_uart0 + &pmx_ns2_sata0 &pmx_ns2_sata1>; + pinctrl-names = "default"; + + pmx_ns2_sata0: pmx-ns2-sata0 { + marvell,pins = "mpp21"; + marvell,function = "sata0"; + }; + pmx_ns2_sata1: pmx-ns2-sata1 { + marvell,pins = "mpp20"; + marvell,function = "sata1"; + }; + }; + serial@12000 { clock-frequency = <166666667>; status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 110d6cb..d6ab442 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -36,6 +36,7 @@ reg = <0x10100 0x40>; ngpios = <32>; interrupt-controller; + #interrupt-cells = <2>; interrupts = <35>, <36>, <37>, <38>; }; @@ -46,6 +47,7 @@ reg = <0x10140 0x40>; ngpios = <18>; interrupt-controller; + #interrupt-cells = <2>; interrupts = <39>, <40>, <41>; }; diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts index e8814fe..b4dc3ed 100644 --- a/arch/arm/boot/dts/kizbox.dts +++ b/arch/arm/boot/dts/kizbox.dts @@ -48,6 +48,8 @@ macb0: ethernet@fffc4000 { phy-mode = "mii"; + pinctrl-0 = <&pinctrl_macb_rmii + &pinctrl_macb_rmii_mii_alt>; status = "okay"; }; diff --git a/arch/arm/boot/dts/marco-evb.dts b/arch/arm/boot/dts/marco-evb.dts new file mode 100644 index 0000000..5130aea --- /dev/null +++ b/arch/arm/boot/dts/marco-evb.dts @@ -0,0 +1,54 @@ +/* + * DTS file for CSR SiRFmarco Evaluation Board + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; + +/include/ "marco.dtsi" + +/ { + model = "CSR SiRFmarco Evaluation Board"; + compatible = "sirf,marco-cb", "sirf,marco"; + + memory { + reg = <0x40000000 0x60000000>; + }; + + axi { + peri-iobg { + uart1: uart@cc060000 { + status = "okay"; + }; + uart2: uart@cc070000 { + status = "okay"; + }; + i2c0: i2c@cc0e0000 { + status = "okay"; + fpga-cpld@4d { + compatible = "sirf,fpga-cpld"; + reg = <0x4d>; + }; + }; + spi1: spi@cc170000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + pci-iobg { + sd0: sdhci@cd000000 { + bus-width = <8>; + status = "okay"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi new file mode 100644 index 0000000..1579c34 --- /dev/null +++ b/arch/arm/boot/dts/marco.dtsi @@ -0,0 +1,756 @@ +/* + * DTS file for CSR SiRFmarco SoC + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" +/ { + compatible = "sirf,marco"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x40000000 0x40000000 0xa0000000>; + + l2-cache-controller@c0030000 { + compatible = "sirf,marco-pl310-cache", "arm,pl310-cache"; + reg = <0xc0030000 0x1000>; + interrupts = <0 59 0>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <1 1 1>; + arm,filter-ranges = <0x40000000 0x80000000>; + }; + + gic: interrupt-controller@c0011000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xc0011000 0x1000>, + <0xc0010100 0x0100>; + }; + + rstc-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc2000000 0xc2000000 0x1000000>; + + reset-controller@c2000000 { + compatible = "sirf,marco-rstc"; + reg = <0xc2000000 0x10000>; + }; + }; + + sys-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc3000000 0xc3000000 0x1000000>; + + clock-controller@c3000000 { + compatible = "sirf,marco-clkc"; + reg = <0xc3000000 0x1000>; + interrupts = <0 3 0>; + }; + + rsc-controller@c3010000 { + compatible = "sirf,marco-rsc"; + reg = <0xc3010000 0x1000>; + }; + }; + + mem-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc4000000 0xc4000000 0x1000000>; + + memory-controller@c4000000 { + compatible = "sirf,marco-memc"; + reg = <0xc4000000 0x10000>; + interrupts = <0 27 0>; + }; + }; + + disp-iobg0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc5000000 0xc5000000 0x1000000>; + + display0@c5000000 { + compatible = "sirf,marco-lcd"; + reg = <0xc5000000 0x10000>; + interrupts = <0 30 0>; + }; + + vpp0@c5010000 { + compatible = "sirf,marco-vpp"; + reg = <0xc5010000 0x10000>; + interrupts = <0 31 0>; + }; + }; + + disp-iobg1 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc6000000 0xc6000000 0x1000000>; + + display1@c6000000 { + compatible = "sirf,marco-lcd"; + reg = <0xc6000000 0x10000>; + interrupts = <0 62 0>; + }; + + vpp1@c6010000 { + compatible = "sirf,marco-vpp"; + reg = <0xc6010000 0x10000>; + interrupts = <0 63 0>; + }; + }; + + graphics-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc8000000 0xc8000000 0x1000000>; + + graphics@c8000000 { + compatible = "powervr,sgx540"; + reg = <0xc8000000 0x1000000>; + interrupts = <0 6 0>; + }; + }; + + multimedia-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc9000000 0xc9000000 0x1000000>; + + multimedia@a0000000 { + compatible = "sirf,marco-video-codec"; + reg = <0xc9000000 0x1000000>; + interrupts = <0 5 0>; + }; + }; + + dsp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xca000000 0xca000000 0x2000000>; + + dspif@ca000000 { + compatible = "sirf,marco-dspif"; + reg = <0xca000000 0x10000>; + interrupts = <0 9 0>; + }; + + gps@ca010000 { + compatible = "sirf,marco-gps"; + reg = <0xca010000 0x10000>; + interrupts = <0 7 0>; + }; + + dsp@cb000000 { + compatible = "sirf,marco-dsp"; + reg = <0xcb000000 0x1000000>; + interrupts = <0 8 0>; + }; + }; + + peri-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xcc000000 0xcc000000 0x2000000>; + + timer@cc020000 { + compatible = "sirf,marco-tick"; + reg = <0xcc020000 0x1000>; + interrupts = <0 0 0>, + <0 1 0>, + <0 2 0>, + <0 49 0>, + <0 50 0>, + <0 51 0>; + }; + + nand@cc030000 { + compatible = "sirf,marco-nand"; + reg = <0xcc030000 0x10000>; + interrupts = <0 41 0>; + }; + + audio@cc040000 { + compatible = "sirf,marco-audio"; + reg = <0xcc040000 0x10000>; + interrupts = <0 35 0>; + }; + + uart0: uart@cc050000 { + cell-index = <0>; + compatible = "sirf,marco-uart"; + reg = <0xcc050000 0x1000>; + interrupts = <0 17 0>; + fifosize = <128>; + status = "disabled"; + }; + + uart1: uart@cc060000 { + cell-index = <1>; + compatible = "sirf,marco-uart"; + reg = <0xcc060000 0x1000>; + interrupts = <0 18 0>; + fifosize = <32>; + status = "disabled"; + }; + + uart2: uart@cc070000 { + cell-index = <2>; + compatible = "sirf,marco-uart"; + reg = <0xcc070000 0x1000>; + interrupts = <0 19 0>; + fifosize = <128>; + status = "disabled"; + }; + + uart3: uart@cc190000 { + cell-index = <3>; + compatible = "sirf,marco-uart"; + reg = <0xcc190000 0x1000>; + interrupts = <0 66 0>; + fifosize = <128>; + status = "disabled"; + }; + + uart4: uart@cc1a0000 { + cell-index = <4>; + compatible = "sirf,marco-uart"; + reg = <0xcc1a0000 0x1000>; + interrupts = <0 69 0>; + fifosize = <128>; + status = "disabled"; + }; + + usp0: usp@cc080000 { + cell-index = <0>; + compatible = "sirf,marco-usp"; + reg = <0xcc080000 0x10000>; + interrupts = <0 20 0>; + status = "disabled"; + }; + + usp1: usp@cc090000 { + cell-index = <1>; + compatible = "sirf,marco-usp"; + reg = <0xcc090000 0x10000>; + interrupts = <0 21 0>; + status = "disabled"; + }; + + usp2: usp@cc0a0000 { + cell-index = <2>; + compatible = "sirf,marco-usp"; + reg = <0xcc0a0000 0x10000>; + interrupts = <0 22 0>; + status = "disabled"; + }; + + dmac0: dma-controller@cc0b0000 { + cell-index = <0>; + compatible = "sirf,marco-dmac"; + reg = <0xcc0b0000 0x10000>; + interrupts = <0 12 0>; + }; + + dmac1: dma-controller@cc160000 { + cell-index = <1>; + compatible = "sirf,marco-dmac"; + reg = <0xcc160000 0x10000>; + interrupts = <0 13 0>; + }; + + vip@cc0c0000 { + compatible = "sirf,marco-vip"; + reg = <0xcc0c0000 0x10000>; + }; + + spi0: spi@cc0d0000 { + cell-index = <0>; + compatible = "sirf,marco-spi"; + reg = <0xcc0d0000 0x10000>; + interrupts = <0 15 0>; + sirf,spi-num-chipselects = <1>; + cs-gpios = <&gpio 0 0>; + sirf,spi-dma-rx-channel = <25>; + sirf,spi-dma-tx-channel = <20>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@cc170000 { + cell-index = <1>; + compatible = "sirf,marco-spi"; + reg = <0xcc170000 0x10000>; + interrupts = <0 16 0>; + sirf,spi-num-chipselects = <1>; + cs-gpios = <&gpio 0 0>; + sirf,spi-dma-rx-channel = <12>; + sirf,spi-dma-tx-channel = <13>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@cc0e0000 { + cell-index = <0>; + compatible = "sirf,marco-i2c"; + reg = <0xcc0e0000 0x10000>; + interrupts = <0 24 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@cc0f0000 { + cell-index = <1>; + compatible = "sirf,marco-i2c"; + reg = <0xcc0f0000 0x10000>; + interrupts = <0 25 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + tsc@cc110000 { + compatible = "sirf,marco-tsc"; + reg = <0xcc110000 0x10000>; + interrupts = <0 33 0>; + }; + + gpio: pinctrl@cc120000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sirf,marco-pinctrl"; + reg = <0xcc120000 0x10000>; + interrupts = <0 43 0>, + <0 44 0>, + <0 45 0>, + <0 46 0>, + <0 47 0>; + gpio-controller; + interrupt-controller; + + lcd_16pins_a: lcd0_0 { + lcd { + sirf,pins = "lcd_16bitsgrp"; + sirf,function = "lcd_16bits"; + }; + }; + lcd_18pins_a: lcd0_1 { + lcd { + sirf,pins = "lcd_18bitsgrp"; + sirf,function = "lcd_18bits"; + }; + }; + lcd_24pins_a: lcd0_2 { + lcd { + sirf,pins = "lcd_24bitsgrp"; + sirf,function = "lcd_24bits"; + }; + }; + lcdrom_pins_a: lcdrom0_0 { + lcd { + sirf,pins = "lcdromgrp"; + sirf,function = "lcdrom"; + }; + }; + uart0_pins_a: uart0_0 { + uart { + sirf,pins = "uart0grp"; + sirf,function = "uart0"; + }; + }; + uart1_pins_a: uart1_0 { + uart { + sirf,pins = "uart1grp"; + sirf,function = "uart1"; + }; + }; + uart2_pins_a: uart2_0 { + uart { + sirf,pins = "uart2grp"; + sirf,function = "uart2"; + }; + }; + uart2_noflow_pins_a: uart2_1 { + uart { + sirf,pins = "uart2_nostreamctrlgrp"; + sirf,function = "uart2_nostreamctrl"; + }; + }; + spi0_pins_a: spi0_0 { + spi { + sirf,pins = "spi0grp"; + sirf,function = "spi0"; + }; + }; + spi1_pins_a: spi1_0 { + spi { + sirf,pins = "spi1grp"; + sirf,function = "spi1"; + }; + }; + i2c0_pins_a: i2c0_0 { + i2c { + sirf,pins = "i2c0grp"; + sirf,function = "i2c0"; + }; + }; + i2c1_pins_a: i2c1_0 { + i2c { + sirf,pins = "i2c1grp"; + sirf,function = "i2c1"; + }; + }; + pwm0_pins_a: pwm0_0 { + pwm { + sirf,pins = "pwm0grp"; + sirf,function = "pwm0"; + }; + }; + pwm1_pins_a: pwm1_0 { + pwm { + sirf,pins = "pwm1grp"; + sirf,function = "pwm1"; + }; + }; + pwm2_pins_a: pwm2_0 { + pwm { + sirf,pins = "pwm2grp"; + sirf,function = "pwm2"; + }; + }; + pwm3_pins_a: pwm3_0 { + pwm { + sirf,pins = "pwm3grp"; + sirf,function = "pwm3"; + }; + }; + gps_pins_a: gps_0 { + gps { + sirf,pins = "gpsgrp"; + sirf,function = "gps"; + }; + }; + vip_pins_a: vip_0 { + vip { + sirf,pins = "vipgrp"; + sirf,function = "vip"; + }; + }; + sdmmc0_pins_a: sdmmc0_0 { + sdmmc0 { + sirf,pins = "sdmmc0grp"; + sirf,function = "sdmmc0"; + }; + }; + sdmmc1_pins_a: sdmmc1_0 { + sdmmc1 { + sirf,pins = "sdmmc1grp"; + sirf,function = "sdmmc1"; + }; + }; + sdmmc2_pins_a: sdmmc2_0 { + sdmmc2 { + sirf,pins = "sdmmc2grp"; + sirf,function = "sdmmc2"; + }; + }; + sdmmc3_pins_a: sdmmc3_0 { + sdmmc3 { + sirf,pins = "sdmmc3grp"; + sirf,function = "sdmmc3"; + }; + }; + sdmmc4_pins_a: sdmmc4_0 { + sdmmc4 { + sirf,pins = "sdmmc4grp"; + sirf,function = "sdmmc4"; + }; + }; + sdmmc5_pins_a: sdmmc5_0 { + sdmmc5 { + sirf,pins = "sdmmc5grp"; + sirf,function = "sdmmc5"; + }; + }; + i2s_pins_a: i2s_0 { + i2s { + sirf,pins = "i2sgrp"; + sirf,function = "i2s"; + }; + }; + ac97_pins_a: ac97_0 { + ac97 { + sirf,pins = "ac97grp"; + sirf,function = "ac97"; + }; + }; + nand_pins_a: nand_0 { + nand { + sirf,pins = "nandgrp"; + sirf,function = "nand"; + }; + }; + usp0_pins_a: usp0_0 { + usp0 { + sirf,pins = "usp0grp"; + sirf,function = "usp0"; + }; + }; + usp1_pins_a: usp1_0 { + usp1 { + sirf,pins = "usp1grp"; + sirf,function = "usp1"; + }; + }; + usp2_pins_a: usp2_0 { + usp2 { + sirf,pins = "usp2grp"; + sirf,function = "usp2"; + }; + }; + usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus_0 { + usb0_utmi_drvbus { + sirf,pins = "usb0_utmi_drvbusgrp"; + sirf,function = "usb0_utmi_drvbus"; + }; + }; + usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus_0 { + usb1_utmi_drvbus { + sirf,pins = "usb1_utmi_drvbusgrp"; + sirf,function = "usb1_utmi_drvbus"; + }; + }; + warm_rst_pins_a: warm_rst_0 { + warm_rst { + sirf,pins = "warm_rstgrp"; + sirf,function = "warm_rst"; + }; + }; + pulse_count_pins_a: pulse_count_0 { + pulse_count { + sirf,pins = "pulse_countgrp"; + sirf,function = "pulse_count"; + }; + }; + cko0_rst_pins_a: cko0_rst_0 { + cko0_rst { + sirf,pins = "cko0_rstgrp"; + sirf,function = "cko0_rst"; + }; + }; + cko1_rst_pins_a: cko1_rst_0 { + cko1_rst { + sirf,pins = "cko1_rstgrp"; + sirf,function = "cko1_rst"; + }; + }; + }; + + pwm@cc130000 { + compatible = "sirf,marco-pwm"; + reg = <0xcc130000 0x10000>; + }; + + efusesys@cc140000 { + compatible = "sirf,marco-efuse"; + reg = <0xcc140000 0x10000>; + }; + + pulsec@cc150000 { + compatible = "sirf,marco-pulsec"; + reg = <0xcc150000 0x10000>; + interrupts = <0 48 0>; + }; + + pci-iobg { + compatible = "sirf,marco-pciiobg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xcd000000 0xcd000000 0x1000000>; + + sd0: sdhci@cd000000 { + cell-index = <0>; + compatible = "sirf,marco-sdhc"; + reg = <0xcd000000 0x100000>; + interrupts = <0 38 0>; + status = "disabled"; + }; + + sd1: sdhci@cd100000 { + cell-index = <1>; + compatible = "sirf,marco-sdhc"; + reg = <0xcd100000 0x100000>; + interrupts = <0 38 0>; + status = "disabled"; + }; + + sd2: sdhci@cd200000 { + cell-index = <2>; + compatible = "sirf,marco-sdhc"; + reg = <0xcd200000 0x100000>; + interrupts = <0 23 0>; + status = "disabled"; + }; + + sd3: sdhci@cd300000 { + cell-index = <3>; + compatible = "sirf,marco-sdhc"; + reg = <0xcd300000 0x100000>; + interrupts = <0 23 0>; + status = "disabled"; + }; + + sd4: sdhci@cd400000 { + cell-index = <4>; + compatible = "sirf,marco-sdhc"; + reg = <0xcd400000 0x100000>; + interrupts = <0 39 0>; + status = "disabled"; + }; + + sd5: sdhci@cd500000 { + cell-index = <5>; + compatible = "sirf,marco-sdhc"; + reg = <0xcd500000 0x100000>; + interrupts = <0 39 0>; + status = "disabled"; + }; + + pci-copy@cd900000 { + compatible = "sirf,marco-pcicp"; + reg = <0xcd900000 0x100000>; + interrupts = <0 40 0>; + }; + + rom-interface@cda00000 { + compatible = "sirf,marco-romif"; + reg = <0xcda00000 0x100000>; + }; + }; + }; + + rtc-iobg { + compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xc1000000 0x10000>; + + gpsrtc@1000 { + compatible = "sirf,marco-gpsrtc"; + reg = <0x1000 0x1000>; + interrupts = <0 55 0>, + <0 56 0>, + <0 57 0>; + }; + + sysrtc@2000 { + compatible = "sirf,marco-sysrtc"; + reg = <0x2000 0x1000>; + interrupts = <0 52 0>, + <0 53 0>, + <0 54 0>; + }; + + pwrc@3000 { + compatible = "sirf,marco-pwrc"; + reg = <0x3000 0x1000>; + interrupts = <0 32 0>; + }; + }; + + uus-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xce000000 0xce000000 0x1000000>; + + usb0: usb@ce000000 { + compatible = "chipidea,ci13611a-marco"; + reg = <0xce000000 0x10000>; + interrupts = <0 10 0>; + }; + + usb1: usb@ce010000 { + compatible = "chipidea,ci13611a-marco"; + reg = <0xce010000 0x10000>; + interrupts = <0 11 0>; + }; + + security@ce020000 { + compatible = "sirf,marco-security"; + reg = <0xce020000 0x10000>; + interrupts = <0 42 0>; + }; + }; + + can-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xd0000000 0xd0000000 0x1000000>; + + can0: can@d0000000 { + compatible = "sirf,marco-can"; + reg = <0xd0000000 0x10000>; + }; + + can1: can@d0010000 { + compatible = "sirf,marco-can"; + reg = <0xd0010000 0x10000>; + }; + }; + + lvds-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xd1000000 0xd1000000 0x1000000>; + + lvds@d1000000 { + compatible = "sirf,marco-lvds"; + reg = <0xd1000000 0x10000>; + interrupts = <0 64 0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 19aec42..936d230 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -25,6 +25,10 @@ ethernet0 = &gmac0; serial0 = &uart0; serial1 = &uart1; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; }; cpus { @@ -98,47 +102,41 @@ interrupts = <1 13 0xf04>; }; - timer0: timer@ffc08000 { + timer0: timer0@ffc08000 { compatible = "snps,dw-apb-timer-sp"; interrupts = <0 167 4>; - clock-frequency = <200000000>; reg = <0xffc08000 0x1000>; }; - timer1: timer@ffc09000 { + timer1: timer1@ffc09000 { compatible = "snps,dw-apb-timer-sp"; interrupts = <0 168 4>; - clock-frequency = <200000000>; reg = <0xffc09000 0x1000>; }; - timer2: timer@ffd00000 { + timer2: timer2@ffd00000 { compatible = "snps,dw-apb-timer-osc"; interrupts = <0 169 4>; - clock-frequency = <200000000>; reg = <0xffd00000 0x1000>; }; - timer3: timer@ffd01000 { + timer3: timer3@ffd01000 { compatible = "snps,dw-apb-timer-osc"; interrupts = <0 170 4>; - clock-frequency = <200000000>; reg = <0xffd01000 0x1000>; }; - uart0: uart@ffc02000 { + uart0: serial0@ffc02000 { compatible = "snps,dw-apb-uart"; reg = <0xffc02000 0x1000>; - clock-frequency = <7372800>; interrupts = <0 162 4>; reg-shift = <2>; reg-io-width = <4>; }; - uart1: uart@ffc03000 { + uart1: serial1@ffc03000 { compatible = "snps,dw-apb-uart"; reg = <0xffc03000 0x1000>; - clock-frequency = <7372800>; interrupts = <0 163 4>; reg-shift = <2>; reg-io-width = <4>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts index ab7e4a9..3ae8a83 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts @@ -20,7 +20,7 @@ / { model = "Altera SOCFPGA Cyclone V"; - compatible = "altr,socfpga-cyclone5"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; chosen { bootargs = "console=ttyS0,57600"; @@ -29,6 +29,36 @@ memory { name = "memory"; device_type = "memory"; - reg = <0x0 0x10000000>; /* 256MB */ + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + timer0@ffc08000 { + clock-frequency = <100000000>; + }; + + timer1@ffc09000 { + clock-frequency = <100000000>; + }; + + timer2@ffd00000 { + clock-frequency = <25000000>; + }; + + timer3@ffd01000 { + clock-frequency = <25000000>; + }; + + serial0@ffc02000 { + clock-frequency = <100000000>; + }; + + serial1@ffc03000 { + clock-frequency = <100000000>; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; }; }; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts new file mode 100644 index 0000000..1036eba --- /dev/null +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +/include/ "socfpga.dtsi" + +/ { + model = "Altera SOCFPGA VT"; + compatible = "altr,socfpga-vt", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1 GB */ + }; + + soc { + timer0@ffc08000 { + clock-frequency = <7000000>; + }; + + timer1@ffc09000 { + clock-frequency = <7000000>; + }; + + timer2@ffd00000 { + clock-frequency = <7000000>; + }; + + timer3@ffd01000 { + clock-frequency = <7000000>; + }; + + serial0@ffc02000 { + clock-frequency = <7372800>; + }; + + serial1@ffc03000 { + clock-frequency = <7372800>; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd08010>; + }; + }; +}; diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi index 8bbc2bf..8b36abe 100644 --- a/arch/arm/boot/dts/sunxi.dtsi +++ b/arch/arm/boot/dts/sunxi.dtsi @@ -60,19 +60,21 @@ }; uart0: uart@01c28000 { - compatible = "ns8250"; + compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <1>; reg-shift = <2>; + reg-io-width = <4>; clock-frequency = <24000000>; status = "disabled"; }; uart1: uart@01c28400 { - compatible = "ns8250"; + compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <2>; reg-shift = <2>; + reg-io-width = <4>; clock-frequency = <24000000>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts new file mode 100644 index 0000000..a30aca6 --- /dev/null +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -0,0 +1,21 @@ +/dts-v1/; + +/include/ "tegra114.dtsi" + +/ { + model = "NVIDIA Tegra114 Dalmore evaluation board"; + compatible = "nvidia,dalmore", "nvidia,tegra114"; + + memory { + reg = <0x80000000 0x40000000>; + }; + + serial@70006300 { + status = "okay"; + clock-frequency = <408000000>; + }; + + pmc { + nvidia,invert-interrupt; + }; +}; diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts new file mode 100644 index 0000000..9bea8f5 --- /dev/null +++ b/arch/arm/boot/dts/tegra114-pluto.dts @@ -0,0 +1,21 @@ +/dts-v1/; + +/include/ "tegra114.dtsi" + +/ { + model = "NVIDIA Tegra114 Pluto evaluation board"; + compatible = "nvidia,pluto", "nvidia,tegra114"; + + memory { + reg = <0x80000000 0x40000000>; + }; + + serial@70006300 { + status = "okay"; + clock-frequency = <408000000>; + }; + + pmc { + nvidia,invert-interrupt; + }; +}; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi new file mode 100644 index 0000000..1dfaf28 --- /dev/null +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -0,0 +1,153 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra114"; + interrupt-parent = <&gic>; + + gic: interrupt-controller { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x50041000 0x1000>, + <0x50042000 0x1000>, + <0x50044000 0x2000>, + <0x50046000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer@60005000 { + compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; + reg = <0x60005000 0x400>; + interrupts = <0 0 0x04 + 0 1 0x04 + 0 41 0x04 + 0 42 0x04 + 0 121 0x04 + 0 122 0x04>; + }; + + tegra_car: clock { + compatible = "nvidia,tegra114-car, nvidia,tegra30-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + + ahb: ahb { + compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; + reg = <0x6000c004 0x14c>; + }; + + gpio: gpio { + compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; + reg = <0x6000d000 0x1000>; + interrupts = <0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 + 0 125 0x04>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + pinmux: pinmux { + compatible = "nvidia,tegra114-pinmux"; + reg = <0x70000868 0x148 /* Pad control registers */ + 0x70003000 0x40c>; /* Mux registers */ + }; + + serial@70006000 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = <0 36 0x04>; + status = "disabled"; + }; + + serial@70006040 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = <0 37 0x04>; + status = "disabled"; + }; + + serial@70006200 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = <0 46 0x04>; + status = "disabled"; + }; + + serial@70006300 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = <0 90 0x04>; + status = "disabled"; + }; + + rtc { + compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <0 2 0x04>; + }; + + pmc { + compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc"; + reg = <0x7000e400 0x400>; + }; + + iommu { + compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; + reg = <0x7000f010 0x02c + 0x7000f1f0 0x010 + 0x7000f228 0x074>; + nvidia,#asids = <4>; + dma-window = <0 0x40000000>; + nvidia,swgroups = <0x18659fe>; + nvidia,ahb = <&ahb>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; +}; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 43eb72a..2b41697 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -432,6 +432,10 @@ status = "okay"; }; + usb-phy@c5004400 { + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + }; + sdhci@c8000200 { status = "okay"; cd-gpios = <&gpio 69 0>; /* gpio PI5 */ diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 6a93d14..11b30db 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -266,6 +266,8 @@ clock-frequency = <80000>; request-gpios = <&gpio 170 0>; /* gpio PV2 */ slave-addr = <138>; + clocks = <&tegra_car 67>, <&tegra_car 124>; + clock-names = "div-clk", "fast-clk"; }; i2c@7000d000 { @@ -418,6 +420,10 @@ status = "okay"; }; + usb-phy@c5004400 { + nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ + }; + sdhci@c8000000 { status = "okay"; cd-gpios = <&gpio 173 0>; /* gpio PV5 */ diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 4204598..607bf0c 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -561,6 +561,10 @@ status = "okay"; }; + usb-phy@c5004400 { + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + }; + sdhci@c8000000 { status = "okay"; power-gpios = <&gpio 86 0>; /* gpio PK6 */ diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index b70b4cb..e47cf6a 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -310,6 +310,10 @@ status = "okay"; }; + usb-phy@c5004400 { + nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ + }; + sdhci@c8000000 { status = "okay"; bus-width = <4>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index adc4754..f6c61d1 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -497,6 +497,10 @@ status = "okay"; }; + usb-phy@c5004400 { + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + }; + sdhci@c8000000 { status = "okay"; power-gpios = <&gpio 86 0>; /* gpio PK6 */ diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index b8effa1..2e7c83c 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -9,6 +9,7 @@ reg = <0x50000000 0x00024000>; interrupts = <0 65 0x04 /* mpcore syncpt */ 0 67 0x04>; /* mpcore general */ + clocks = <&tegra_car 28>; #address-cells = <1>; #size-cells = <1>; @@ -19,41 +20,49 @@ compatible = "nvidia,tegra20-mpe"; reg = <0x54040000 0x00040000>; interrupts = <0 68 0x04>; + clocks = <&tegra_car 60>; }; vi { compatible = "nvidia,tegra20-vi"; reg = <0x54080000 0x00040000>; interrupts = <0 69 0x04>; + clocks = <&tegra_car 100>; }; epp { compatible = "nvidia,tegra20-epp"; reg = <0x540c0000 0x00040000>; interrupts = <0 70 0x04>; + clocks = <&tegra_car 19>; }; isp { compatible = "nvidia,tegra20-isp"; reg = <0x54100000 0x00040000>; interrupts = <0 71 0x04>; + clocks = <&tegra_car 23>; }; gr2d { compatible = "nvidia,tegra20-gr2d"; reg = <0x54140000 0x00040000>; interrupts = <0 72 0x04>; + clocks = <&tegra_car 21>; }; gr3d { compatible = "nvidia,tegra20-gr3d"; reg = <0x54180000 0x00040000>; + clocks = <&tegra_car 24>; }; dc@54200000 { compatible = "nvidia,tegra20-dc"; reg = <0x54200000 0x00040000>; interrupts = <0 73 0x04>; + clocks = <&tegra_car 27>, <&tegra_car 121>; + clock-names = "disp1", "parent"; rgb { status = "disabled"; @@ -64,6 +73,8 @@ compatible = "nvidia,tegra20-dc"; reg = <0x54240000 0x00040000>; interrupts = <0 74 0x04>; + clocks = <&tegra_car 26>, <&tegra_car 121>; + clock-names = "disp2", "parent"; rgb { status = "disabled"; @@ -74,6 +85,8 @@ compatible = "nvidia,tegra20-hdmi"; reg = <0x54280000 0x00040000>; interrupts = <0 75 0x04>; + clocks = <&tegra_car 51>, <&tegra_car 117>; + clock-names = "hdmi", "parent"; status = "disabled"; }; @@ -81,12 +94,14 @@ compatible = "nvidia,tegra20-tvo"; reg = <0x542c0000 0x00040000>; interrupts = <0 76 0x04>; + clocks = <&tegra_car 102>; status = "disabled"; }; dsi { compatible = "nvidia,tegra20-dsi"; reg = <0x54300000 0x00040000>; + clocks = <&tegra_car 48>; status = "disabled"; }; }; @@ -123,6 +138,12 @@ 0 42 0x04>; }; + tegra_car: clock { + compatible = "nvidia,tegra20-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + apbdma: dma { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; @@ -142,6 +163,7 @@ 0 117 0x04 0 118 0x04 0 119 0x04>; + clocks = <&tegra_car 34>; }; ahb { @@ -183,6 +205,7 @@ reg = <0x70002800 0x200>; interrupts = <0 13 0x04>; nvidia,dma-request-selector = <&apbdma 2>; + clocks = <&tegra_car 11>; status = "disabled"; }; @@ -191,6 +214,7 @@ reg = <0x70002a00 0x200>; interrupts = <0 3 0x04>; nvidia,dma-request-selector = <&apbdma 1>; + clocks = <&tegra_car 18>; status = "disabled"; }; @@ -199,6 +223,7 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <0 36 0x04>; + clocks = <&tegra_car 6>; status = "disabled"; }; @@ -207,6 +232,7 @@ reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <0 37 0x04>; + clocks = <&tegra_car 96>; status = "disabled"; }; @@ -215,6 +241,7 @@ reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <0 46 0x04>; + clocks = <&tegra_car 55>; status = "disabled"; }; @@ -223,6 +250,7 @@ reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <0 90 0x04>; + clocks = <&tegra_car 65>; status = "disabled"; }; @@ -231,6 +259,7 @@ reg = <0x70006400 0x100>; reg-shift = <2>; interrupts = <0 91 0x04>; + clocks = <&tegra_car 66>; status = "disabled"; }; @@ -238,6 +267,7 @@ compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; + clocks = <&tegra_car 17>; }; rtc { @@ -252,6 +282,8 @@ interrupts = <0 38 0x04>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 12>, <&tegra_car 124>; + clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -262,6 +294,7 @@ nvidia,dma-request-selector = <&apbdma 11>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 43>; status = "disabled"; }; @@ -271,6 +304,8 @@ interrupts = <0 84 0x04>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 54>, <&tegra_car 124>; + clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -280,6 +315,8 @@ interrupts = <0 92 0x04>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 67>, <&tegra_car 124>; + clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -289,6 +326,8 @@ interrupts = <0 53 0x04>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 47>, <&tegra_car 124>; + clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -299,6 +338,7 @@ nvidia,dma-request-selector = <&apbdma 15>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 41>; status = "disabled"; }; @@ -309,6 +349,7 @@ nvidia,dma-request-selector = <&apbdma 16>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 44>; status = "disabled"; }; @@ -319,6 +360,7 @@ nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 46>; status = "disabled"; }; @@ -329,6 +371,7 @@ nvidia,dma-request-selector = <&apbdma 18>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 68>; status = "disabled"; }; @@ -357,12 +400,40 @@ #size-cells = <0>; }; + phy1: usb-phy@c5000400 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5000400 0x3c00>; + phy_type = "utmi"; + nvidia,has-legacy-mode; + clocks = <&tegra_car 22>, <&tegra_car 127>; + clock-names = "phy", "pll_u"; + }; + + phy2: usb-phy@c5004400 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5004400 0x3c00>; + phy_type = "ulpi"; + clocks = <&tegra_car 94>, <&tegra_car 127>; + clock-names = "phy", "pll_u"; + }; + + phy3: usb-phy@c5008400 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5008400 0x3C00>; + phy_type = "utmi"; + clocks = <&tegra_car 22>, <&tegra_car 127>; + clock-names = "phy", "pll_u"; + }; + usb@c5000000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5000000 0x4000>; interrupts = <0 20 0x04>; phy_type = "utmi"; nvidia,has-legacy-mode; + clocks = <&tegra_car 22>; + nvidia,needs-double-reset; + nvidia,phy = <&phy1>; status = "disabled"; }; @@ -371,6 +442,8 @@ reg = <0xc5004000 0x4000>; interrupts = <0 21 0x04>; phy_type = "ulpi"; + clocks = <&tegra_car 58>; + nvidia,phy = <&phy2>; status = "disabled"; }; @@ -379,6 +452,8 @@ reg = <0xc5008000 0x4000>; interrupts = <0 97 0x04>; phy_type = "utmi"; + clocks = <&tegra_car 59>; + nvidia,phy = <&phy3>; status = "disabled"; }; @@ -386,6 +461,7 @@ compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; interrupts = <0 14 0x04>; + clocks = <&tegra_car 14>; status = "disabled"; }; @@ -393,6 +469,7 @@ compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; interrupts = <0 15 0x04>; + clocks = <&tegra_car 9>; status = "disabled"; }; @@ -400,6 +477,7 @@ compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; interrupts = <0 19 0x04>; + clocks = <&tegra_car 69>; status = "disabled"; }; @@ -407,9 +485,27 @@ compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; interrupts = <0 31 0x04>; + clocks = <&tegra_car 15>; status = "disabled"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 56 0x04 diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 529fdb8..2de8b91 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -9,6 +9,7 @@ reg = <0x50000000 0x00024000>; interrupts = <0 65 0x04 /* mpcore syncpt */ 0 67 0x04>; /* mpcore general */ + clocks = <&tegra_car 28>; #address-cells = <1>; #size-cells = <1>; @@ -19,41 +20,50 @@ compatible = "nvidia,tegra30-mpe"; reg = <0x54040000 0x00040000>; interrupts = <0 68 0x04>; + clocks = <&tegra_car 60>; }; vi { compatible = "nvidia,tegra30-vi"; reg = <0x54080000 0x00040000>; interrupts = <0 69 0x04>; + clocks = <&tegra_car 164>; }; epp { compatible = "nvidia,tegra30-epp"; reg = <0x540c0000 0x00040000>; interrupts = <0 70 0x04>; + clocks = <&tegra_car 19>; }; isp { compatible = "nvidia,tegra30-isp"; reg = <0x54100000 0x00040000>; interrupts = <0 71 0x04>; + clocks = <&tegra_car 23>; }; gr2d { compatible = "nvidia,tegra30-gr2d"; reg = <0x54140000 0x00040000>; interrupts = <0 72 0x04>; + clocks = <&tegra_car 21>; }; gr3d { compatible = "nvidia,tegra30-gr3d"; reg = <0x54180000 0x00040000>; + clocks = <&tegra_car 24 &tegra_car 98>; + clock-names = "3d", "3d2"; }; dc@54200000 { compatible = "nvidia,tegra30-dc"; reg = <0x54200000 0x00040000>; interrupts = <0 73 0x04>; + clocks = <&tegra_car 27>, <&tegra_car 179>; + clock-names = "disp1", "parent"; rgb { status = "disabled"; @@ -64,6 +74,8 @@ compatible = "nvidia,tegra30-dc"; reg = <0x54240000 0x00040000>; interrupts = <0 74 0x04>; + clocks = <&tegra_car 26>, <&tegra_car 179>; + clock-names = "disp2", "parent"; rgb { status = "disabled"; @@ -74,6 +86,8 @@ compatible = "nvidia,tegra30-hdmi"; reg = <0x54280000 0x00040000>; interrupts = <0 75 0x04>; + clocks = <&tegra_car 51>, <&tegra_car 189>; + clock-names = "hdmi", "parent"; status = "disabled"; }; @@ -81,12 +95,14 @@ compatible = "nvidia,tegra30-tvo"; reg = <0x542c0000 0x00040000>; interrupts = <0 76 0x04>; + clocks = <&tegra_car 169>; status = "disabled"; }; dsi { compatible = "nvidia,tegra30-dsi"; reg = <0x54300000 0x00040000>; + clocks = <&tegra_car 48>; status = "disabled"; }; }; @@ -125,6 +141,12 @@ 0 122 0x04>; }; + tegra_car: clock { + compatible = "nvidia,tegra30-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + apbdma: dma { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; @@ -160,6 +182,7 @@ 0 141 0x04 0 142 0x04 0 143 0x04>; + clocks = <&tegra_car 34>; }; ahb: ahb { @@ -195,6 +218,7 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <0 36 0x04>; + clocks = <&tegra_car 6>; status = "disabled"; }; @@ -203,6 +227,7 @@ reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <0 37 0x04>; + clocks = <&tegra_car 160>; status = "disabled"; }; @@ -211,6 +236,7 @@ reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <0 46 0x04>; + clocks = <&tegra_car 55>; status = "disabled"; }; @@ -219,6 +245,7 @@ reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <0 90 0x04>; + clocks = <&tegra_car 65>; status = "disabled"; }; @@ -227,6 +254,7 @@ reg = <0x70006400 0x100>; reg-shift = <2>; interrupts = <0 91 0x04>; + clocks = <&tegra_car 66>; status = "disabled"; }; @@ -234,6 +262,7 @@ compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; + clocks = <&tegra_car 17>; }; rtc { @@ -248,6 +277,8 @@ interrupts = <0 38 0x04>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 12>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -257,6 +288,8 @@ interrupts = <0 84 0x04>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 54>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -266,6 +299,8 @@ interrupts = <0 92 0x04>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 67>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -275,6 +310,8 @@ interrupts = <0 120 0x04>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 103>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -284,6 +321,8 @@ interrupts = <0 53 0x04>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 47>, <&tegra_car 182>; + clock-names = "div-clk", "fast-clk"; status = "disabled"; }; @@ -294,6 +333,7 @@ nvidia,dma-request-selector = <&apbdma 15>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 41>; status = "disabled"; }; @@ -304,6 +344,7 @@ nvidia,dma-request-selector = <&apbdma 16>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 44>; status = "disabled"; }; @@ -314,6 +355,7 @@ nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 46>; status = "disabled"; }; @@ -324,6 +366,7 @@ nvidia,dma-request-selector = <&apbdma 18>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 68>; status = "disabled"; }; @@ -334,6 +377,7 @@ nvidia,dma-request-selector = <&apbdma 27>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 104>; status = "disabled"; }; @@ -344,6 +388,7 @@ nvidia,dma-request-selector = <&apbdma 28>; #address-cells = <1>; #size-cells = <0>; + clocks = <&tegra_car 105>; status = "disabled"; }; @@ -377,7 +422,13 @@ 0x70080200 0x100>; interrupts = <0 103 0x04>; nvidia,dma-request-selector = <&apbdma 1>; - + clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, + <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, + <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, + <&tegra_car 110>, <&tegra_car 162>; + clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + "i2s3", "i2s4", "dam0", "dam1", "dam2", + "spdif_in"; ranges; #address-cells = <1>; #size-cells = <1>; @@ -386,6 +437,7 @@ compatible = "nvidia,tegra30-i2s"; reg = <0x70080300 0x100>; nvidia,ahub-cif-ids = <4 4>; + clocks = <&tegra_car 30>; status = "disabled"; }; @@ -393,6 +445,7 @@ compatible = "nvidia,tegra30-i2s"; reg = <0x70080400 0x100>; nvidia,ahub-cif-ids = <5 5>; + clocks = <&tegra_car 11>; status = "disabled"; }; @@ -400,6 +453,7 @@ compatible = "nvidia,tegra30-i2s"; reg = <0x70080500 0x100>; nvidia,ahub-cif-ids = <6 6>; + clocks = <&tegra_car 18>; status = "disabled"; }; @@ -407,6 +461,7 @@ compatible = "nvidia,tegra30-i2s"; reg = <0x70080600 0x100>; nvidia,ahub-cif-ids = <7 7>; + clocks = <&tegra_car 101>; status = "disabled"; }; @@ -414,6 +469,7 @@ compatible = "nvidia,tegra30-i2s"; reg = <0x70080700 0x100>; nvidia,ahub-cif-ids = <8 8>; + clocks = <&tegra_car 102>; status = "disabled"; }; }; @@ -422,6 +478,7 @@ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000000 0x200>; interrupts = <0 14 0x04>; + clocks = <&tegra_car 14>; status = "disabled"; }; @@ -429,6 +486,7 @@ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000200 0x200>; interrupts = <0 15 0x04>; + clocks = <&tegra_car 9>; status = "disabled"; }; @@ -436,6 +494,7 @@ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000400 0x200>; interrupts = <0 19 0x04>; + clocks = <&tegra_car 69>; status = "disabled"; }; @@ -443,9 +502,39 @@ compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000600 0x200>; interrupts = <0 31 0x04>; + clocks = <&tegra_car 15>; status = "disabled"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + }; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 144 0x04 diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 1fc405a..cf8071a 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -45,7 +45,6 @@ reg = <1>; }; -/* A7s disabled till big.LITTLE patches are available... cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; @@ -63,7 +62,6 @@ compatible = "arm,cortex-a7"; reg = <0x102>; }; -*/ }; memory@80000000 { diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts new file mode 100644 index 0000000..fcc660c --- /dev/null +++ b/arch/arm/boot/dts/wm8850-w70v2.dts @@ -0,0 +1,47 @@ +/* + * wm8850-w70v2.dts + * - Device tree file for Wondermedia WM8850 Tablet + * - 'W70-V2' mainboard + * - HongLianYing 'HLY070ML268-21A' 7" LCD panel + * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +/include/ "wm8850.dtsi" + +/ { + model = "Wondermedia WM8850-W70v2 Tablet"; + + /* + * Display node is based on Sascha Hauer's patch on dri-devel. + * Added a bpp property to calculate the size of the framebuffer + * until the binding is formalized. + */ + display: display@0 { + modes { + mode0: mode@0 { + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hfront-porch = <40>; + hsync-len = <0>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <1>; + clock = <0>; /* unused but required */ + bpp = <16>; /* non-standard but required */ + }; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 1>; /* duty inverted */ + + brightness-levels = <0 40 60 80 100 130 190 255>; + default-brightness-level = <5>; + }; +}; diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi new file mode 100644 index 0000000..e8cbfdc --- /dev/null +++ b/arch/arm/boot/dts/wm8850.dtsi @@ -0,0 +1,224 @@ +/* + * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC + * + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "wm,wm8850"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc0>; + + intc0: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + /* Secondary IC cascaded to intc0 */ + intc1: interrupt-controller@d8150000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xD8150000 0x10000>; + interrupts = <56 57 58 59 60 61 62 63>; + }; + + gpio: gpio-controller@d8110000 { + compatible = "wm,wm8650-gpio"; + gpio-controller; + reg = <0xd8110000 0x10000>; + #gpio-cells = <3>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref25: ref25M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + plla: plla { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x200>; + }; + + pllb: pllb { + #clock-cells = <0>; + compatible = "wm,wm8750-pll-clock"; + clocks = <&ref25>; + reg = <0x204>; + }; + + clkuart0: uart0 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <24>; + }; + + clkuart1: uart1 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <25>; + }; + + clkuart2: uart2 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <26>; + }; + + clkuart3: uart3 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <27>; + }; + + clkpwm: pwm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x350>; + enable-reg = <0x250>; + enable-bit = <17>; + }; + + clksdhc: sdhc { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x330>; + divisor-mask = <0x3f>; + enable-reg = <0x250>; + enable-bit = <0>; + }; + }; + }; + + fb@d8051700 { + compatible = "wm,wm8505-fb"; + reg = <0xd8051700 0x200>; + display = <&display>; + default-mode = <&mode0>; + }; + + ge_rops@d8050400 { + compatible = "wm,prizm-ge-rops"; + reg = <0xd8050400 0x100>; + }; + + pwm: pwm@d8220000 { + #pwm-cells = <3>; + compatible = "via,vt8500-pwm"; + reg = <0xd8220000 0x100>; + clocks = <&clkpwm>; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007900 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007900 0x200>; + interrupts = <26>; + }; + + uhci@d8007b00 { + compatible = "platform-uhci"; + reg = <0xd8007b00 0x200>; + interrupts = <26>; + }; + + uhci@d8008d00 { + compatible = "platform-uhci"; + reg = <0xd8008d00 0x200>; + interrupts = <26>; + }; + + uart0: uart@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&clkuart0>; + }; + + uart1: uart@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&clkuart1>; + }; + + uart2: uart@d8210000 { + compatible = "via,vt8500-uart"; + reg = <0xd8210000 0x1040>; + interrupts = <47>; + clocks = <&clkuart2>; + }; + + uart3: uart@d82c0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82c0000 0x1040>; + interrupts = <50>; + clocks = <&clkuart3>; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + + sdhc@d800a000 { + compatible = "wm,wm8505-sdhc"; + reg = <0xd800a000 0x1000>; + interrupts = <20 21>; + clocks = <&clksdhc>; + bus-width = <4>; + sdon-inverted; + }; + }; +}; diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index b175577..1ea9590 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -19,6 +19,7 @@ CONFIG_SOC_AT91SAM9260=y CONFIG_SOC_AT91SAM9263=y CONFIG_SOC_AT91SAM9G45=y CONFIG_SOC_AT91SAM9X5=y +CONFIG_SOC_AT91SAM9N12=y CONFIG_MACH_AT91SAM_DT=y CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_TIMER_HZ=128 @@ -31,7 +32,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" +CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" CONFIG_KEXEC=y CONFIG_AUTO_ZRELADDR=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 6966713..0a39667 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -19,6 +19,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_ARCH_MXC=y CONFIG_ARCH_MULTI_V6=y CONFIG_ARCH_MULTI_V7=y +CONFIG_MACH_IMX31_DT=y CONFIG_MACH_MX31LILLY=y CONFIG_MACH_MX31LITE=y CONFIG_MACH_PCM037=y @@ -32,7 +33,6 @@ CONFIG_MACH_PCM043=y CONFIG_MACH_MX35_3DS=y CONFIG_MACH_VPR200=y CONFIG_MACH_IMX51_DT=y -CONFIG_MACH_MX51_3DS=y CONFIG_MACH_EUKREA_CPUIMX51SD=y CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y @@ -151,6 +151,7 @@ CONFIG_MFD_MC13XXX_I2C=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_DA9052=y +CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y CONFIG_MEDIA_SUPPORT=y @@ -159,6 +160,7 @@ CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_SOC_CAMERA=y CONFIG_SOC_CAMERA_OV2640=y +CONFIG_DRM=y CONFIG_VIDEO_MX3=y CONFIG_FB=y CONFIG_LCD_PLATFORM=y @@ -197,9 +199,14 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MXC=y +CONFIG_RTC_DRV_SNVS=y CONFIG_DMADEVICES=y CONFIG_IMX_SDMA=y CONFIG_MXS_DMA=y +CONFIG_STAGING=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_IPUV3_CORE=y +CONFIG_DRM_IMX_IPUV3=y CONFIG_COMMON_CLK_DEBUG=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT2_FS=y diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index 93f3794..13482ea 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -56,6 +56,7 @@ CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_KIRKWOOD=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index b5bc96c..cbd91bc 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -33,6 +33,8 @@ CONFIG_MVNETA=y CONFIG_MARVELL_PHY=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_I2C=y +CONFIG_I2C_MV64XXX=y CONFIG_SERIAL_8250_DW=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 7bf5351..fbbc5bb 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -1,5 +1,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y @@ -8,7 +10,6 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y # CONFIG_UTS_NS is not set # CONFIG_IPC_NS is not set -# CONFIG_USER_NS is not set # CONFIG_PID_NS is not set # CONFIG_NET_NS is not set CONFIG_PERF_EVENTS=y @@ -24,8 +25,6 @@ CONFIG_BLK_DEV_INTEGRITY=y CONFIG_ARCH_MXS=y CONFIG_MACH_MXS_DT=y # CONFIG_ARM_THUMB is not set -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT_VOLUNTARY=y CONFIG_AEABI=y CONFIG_AUTO_ZRELADDR=y @@ -46,25 +45,34 @@ CONFIG_SYN_COOKIES=y CONFIG_CAN=m CONFIG_CAN_RAW=m CONFIG_CAN_BCM=m -CONFIG_CAN_DEV=m CONFIG_CAN_FLEXCAN=m # CONFIG_WIRELESS is not set CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FIRMWARE_IN_KERNEL is not set -# CONFIG_BLK_DEV is not set CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y CONFIG_MTD_DATAFLASH=y -CONFIG_MTD_M25P80 +CONFIG_MTD_M25P80=y +# CONFIG_M25PXX_USE_FAST_READ is not set +CONFIG_MTD_SST25L=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_UBI=y +# CONFIG_BLK_DEV is not set +CONFIG_EEPROM_AT24=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y CONFIG_ENC28J60=y CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC95XX=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set +CONFIG_SMSC_PHY=y +CONFIG_ICPLUS_PHY=y +CONFIG_REALTEK_PHY=y +CONFIG_MICREL_PHY=y # CONFIG_WLAN is not set # CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_EVDEV=m @@ -91,21 +99,6 @@ CONFIG_SPI_MXS=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set -# CONFIG_MFD_SUPPORT is not set -CONFIG_DISPLAY_SUPPORT=m -# CONFIG_HID_SUPPORT is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_JACK=y -CONFIG_SND_DRIVERS=y -CONFIG_SND_ARM=y -CONFIG_SND_SOC=y -CONFIG_SND_MXS_SOC=y -CONFIG_SND_SOC_MXS_SGTL5000=y -CONFIG_SND_SOC_I2C_AND_SPI=y -CONFIG_SND_SOC_SGTL5000=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_FB=y @@ -117,13 +110,16 @@ CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FONTS=y CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_MXS_SOC=y +CONFIG_SND_SOC_MXS_SGTL5000=y CONFIG_USB=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_STORAGE=y CONFIG_USB_MXS_PHY=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y CONFIG_MMC=y CONFIG_MMC_MXS=y CONFIG_NEW_LEDS=y @@ -147,16 +143,23 @@ CONFIG_COMMON_CLK_DEBUG=y CONFIG_IIO=y CONFIG_PWM=y CONFIG_PWM_MXS=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y CONFIG_EXT3_FS=y +CONFIG_EXT4_FS=y # CONFIG_DNOTIFY is not set CONFIG_FSCACHE=m CONFIG_FSCACHE_STATS=y CONFIG_CACHEFILES=m CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RUBIN=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y CONFIG_NFS_FS=y -CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y @@ -170,17 +173,12 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_UNUSED_SYMBOLS=y CONFIG_DEBUG_KERNEL=y CONFIG_LOCKUP_DETECTOR=y -CONFIG_DETECT_HUNG_TASK=y CONFIG_TIMER_STATS=y CONFIG_PROVE_LOCKING=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y CONFIG_DEBUG_INFO=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_BLK_DEV_IO_TRACE=y CONFIG_STRICT_DEVMEM=y CONFIG_DEBUG_USER=y -CONFIG_CRYPTO=y -CONFIG_CRYPTO_CRC32C=m # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set CONFIG_CRC_ITU_T=m diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig index 6a936c7..002a1ce 100644 --- a/arch/arm/configs/prima2_defconfig +++ b/arch/arm/configs/prima2_defconfig @@ -11,6 +11,9 @@ CONFIG_PARTITION_ADVANCED=y CONFIG_BSD_DISKLABEL=y CONFIG_SOLARIS_X86_PARTITION=y CONFIG_ARCH_SIRF=y +# CONFIG_SWP_EMULATE is not set +CONFIG_SMP=y +CONFIG_SCHED_MC=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_KEXEC=y diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index a59dcb5..ad41ec2 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -64,6 +64,24 @@ extern unsigned int processor_id; #define read_cpuid_ext(reg) 0 #endif +#define ARM_CPU_IMP_ARM 0x41 +#define ARM_CPU_IMP_INTEL 0x69 + +#define ARM_CPU_PART_ARM1136 0xB360 +#define ARM_CPU_PART_ARM1156 0xB560 +#define ARM_CPU_PART_ARM1176 0xB760 +#define ARM_CPU_PART_ARM11MPCORE 0xB020 +#define ARM_CPU_PART_CORTEX_A8 0xC080 +#define ARM_CPU_PART_CORTEX_A9 0xC090 +#define ARM_CPU_PART_CORTEX_A5 0xC050 +#define ARM_CPU_PART_CORTEX_A15 0xC0F0 +#define ARM_CPU_PART_CORTEX_A7 0xC070 + +#define ARM_CPU_XSCALE_ARCH_MASK 0xe000 +#define ARM_CPU_XSCALE_ARCH_V1 0x2000 +#define ARM_CPU_XSCALE_ARCH_V2 0x4000 +#define ARM_CPU_XSCALE_ARCH_V3 0x6000 + /* * The CPU ID never changes at run time, so we might as well tell the * compiler that it's constant. Use this function to read the CPU ID @@ -74,6 +92,21 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) return read_cpuid(CPUID_ID); } +static inline unsigned int __attribute_const__ read_cpuid_implementor(void) +{ + return (read_cpuid_id() & 0xFF000000) >> 24; +} + +static inline unsigned int __attribute_const__ read_cpuid_part_number(void) +{ + return read_cpuid_id() & 0xFFF0; +} + +static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void) +{ + return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK; +} + static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) { return read_cpuid(CPUID_CACHETYPE); diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h index 4eb6d00..006f026 100644 --- a/arch/arm/include/asm/smp_scu.h +++ b/arch/arm/include/asm/smp_scu.h @@ -6,6 +6,23 @@ #define SCU_PM_POWEROFF 3 #ifndef __ASSEMBLER__ + +#include <asm/cputype.h> + +static inline bool scu_a9_has_base(void) +{ + return read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9; +} + +static inline unsigned long scu_a9_get_base(void) +{ + unsigned long pa; + + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa)); + + return pa; +} + unsigned int scu_get_core_count(void __iomem *); void scu_enable(void __iomem *); int scu_power_mode(void __iomem *, unsigned int); diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h new file mode 100644 index 0000000..91d38e3 --- /dev/null +++ b/arch/arm/include/debug/imx-uart.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DEBUG_IMX_UART_H +#define __DEBUG_IMX_UART_H + +#define IMX1_UART1_BASE_ADDR 0x00206000 +#define IMX1_UART2_BASE_ADDR 0x00207000 +#define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR +#define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n) + +#define IMX21_UART1_BASE_ADDR 0x1000a000 +#define IMX21_UART2_BASE_ADDR 0x1000b000 +#define IMX21_UART3_BASE_ADDR 0x1000c000 +#define IMX21_UART4_BASE_ADDR 0x1000d000 +#define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR +#define IMX21_UART_BASE(n) IMX21_UART_BASE_ADDR(n) + +#define IMX25_UART1_BASE_ADDR 0x43f90000 +#define IMX25_UART2_BASE_ADDR 0x43f94000 +#define IMX25_UART3_BASE_ADDR 0x5000c000 +#define IMX25_UART4_BASE_ADDR 0x50008000 +#define IMX25_UART5_BASE_ADDR 0x5002c000 +#define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR +#define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n) + +#define IMX31_UART1_BASE_ADDR 0x43f90000 +#define IMX31_UART2_BASE_ADDR 0x43f94000 +#define IMX31_UART3_BASE_ADDR 0x5000c000 +#define IMX31_UART4_BASE_ADDR 0x43fb0000 +#define IMX31_UART5_BASE_ADDR 0x43fb4000 +#define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR +#define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n) + +#define IMX35_UART1_BASE_ADDR 0x43f90000 +#define IMX35_UART2_BASE_ADDR 0x43f94000 +#define IMX35_UART3_BASE_ADDR 0x5000c000 +#define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR +#define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n) + +#define IMX51_UART1_BASE_ADDR 0x73fbc000 +#define IMX51_UART2_BASE_ADDR 0x73fc0000 +#define IMX51_UART3_BASE_ADDR 0x7000c000 +#define IMX51_UART_BASE_ADDR(n) IMX51_UART##n##_BASE_ADDR +#define IMX51_UART_BASE(n) IMX51_UART_BASE_ADDR(n) + +#define IMX53_UART1_BASE_ADDR 0x53fbc000 +#define IMX53_UART2_BASE_ADDR 0x53fc0000 +#define IMX53_UART3_BASE_ADDR 0x5000c000 +#define IMX53_UART4_BASE_ADDR 0x53ff0000 +#define IMX53_UART5_BASE_ADDR 0x63f90000 +#define IMX53_UART_BASE_ADDR(n) IMX53_UART##n##_BASE_ADDR +#define IMX53_UART_BASE(n) IMX53_UART_BASE_ADDR(n) + +#define IMX6Q_UART1_BASE_ADDR 0x02020000 +#define IMX6Q_UART2_BASE_ADDR 0x021e8000 +#define IMX6Q_UART3_BASE_ADDR 0x021ec000 +#define IMX6Q_UART4_BASE_ADDR 0x021f0000 +#define IMX6Q_UART5_BASE_ADDR 0x021f4000 +#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR +#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) + +#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT) + +#ifdef CONFIG_DEBUG_IMX1_UART +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX1) +#elif defined(CONFIG_DEBUG_IMX21_IMX27_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX21) +#elif defined(CONFIG_DEBUG_IMX25_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX25) +#elif defined(CONFIG_DEBUG_IMX31_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX31) +#elif defined(CONFIG_DEBUG_IMX35_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX35) +#elif defined(CONFIG_DEBUG_IMX51_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX51) +#elif defined(CONFIG_DEBUG_IMX53_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX53) +#elif defined(CONFIG_DEBUG_IMX6Q_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) +#endif + +#endif /* __DEBUG_IMX_UART_H */ diff --git a/arch/arm/include/debug/imx.S b/arch/arm/include/debug/imx.S index 0c4e17d..619d8cc 100644 --- a/arch/arm/include/debug/imx.S +++ b/arch/arm/include/debug/imx.S @@ -10,35 +10,8 @@ * published by the Free Software Foundation. * */ -#define IMX6Q_UART1_BASE_ADDR 0x02020000 -#define IMX6Q_UART2_BASE_ADDR 0x021e8000 -#define IMX6Q_UART3_BASE_ADDR 0x021ec000 -#define IMX6Q_UART4_BASE_ADDR 0x021f0000 -#define IMX6Q_UART5_BASE_ADDR 0x021f4000 -/* - * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion - * of IMX6Q_UART##n##_BASE_ADDR. - */ -#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR -#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) -#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT) - -#ifdef CONFIG_DEBUG_IMX1_UART -#define UART_PADDR 0x00206000 -#elif defined (CONFIG_DEBUG_IMX25_UART) -#define UART_PADDR 0x43f90000 -#elif defined (CONFIG_DEBUG_IMX21_IMX27_UART) -#define UART_PADDR 0x1000a000 -#elif defined (CONFIG_DEBUG_IMX31_IMX35_UART) -#define UART_PADDR 0x43f90000 -#elif defined (CONFIG_DEBUG_IMX51_UART) -#define UART_PADDR 0x73fbc000 -#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART) -#define UART_PADDR 0x53fbc000 -#elif defined (CONFIG_DEBUG_IMX6Q_UART) -#define UART_PADDR IMX6Q_DEBUG_UART_BASE -#endif +#include "imx-uart.h" /* * FIXME: This is a copy of IMX_IO_P2V in hardware.h, and needs to diff --git a/arch/arm/mach-vt8500/include/mach/debug-macro.S b/arch/arm/include/debug/vt8500.S index ca292f2..0e0ca08 100644 --- a/arch/arm/mach-vt8500/include/mach/debug-macro.S +++ b/arch/arm/include/debug/vt8500.S @@ -1,20 +1,24 @@ -/* - * arch/arm/mach-vt8500/include/mach/debug-macro.S +/* + * Debugging macro include header * * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * Debugging macro include header + * Moved from arch/arm/mach-vt8500/include/mach/debug-macro.S + * Minor changes for readability. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * -*/ + */ + +#define DEBUG_LL_PHYS_BASE 0xD8000000 +#define DEBUG_LL_VIRT_BASE 0xF8000000 +#define DEBUG_LL_UART_OFFSET 0x00200000 +#if defined(CONFIG_DEBUG_VT8500_UART0) .macro addruart, rp, rv, tmp - mov \rp, #0x00200000 - orr \rv, \rp, #0xf8000000 - orr \rp, \rp, #0xd8000000 + mov \rp, #DEBUG_LL_UART_OFFSET + orr \rv, \rp, #DEBUG_LL_VIRT_BASE + orr \rp, \rp, #DEBUG_LL_PHYS_BASE .endm .macro senduart,rd,rx @@ -29,3 +33,5 @@ .macro waituart,rd,rx .endm + +#endif diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index 6809200..14f7c3b 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S @@ -100,12 +100,14 @@ ENTRY(printch) b 1b ENDPROC(printch) +#ifdef CONFIG_MMU ENTRY(debug_ll_addr) addruart r2, r3, ip str r2, [r0] str r3, [r1] mov pc, lr ENDPROC(debug_ll_addr) +#endif #else diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 4eee351..486a15a 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -246,6 +246,7 @@ __create_page_tables: /* * Then map boot params address in r2 if specified. + * We map 2 sections in case the ATAGs/DTB crosses a section boundary. */ mov r0, r2, lsr #SECTION_SHIFT movs r0, r0, lsl #SECTION_SHIFT @@ -253,6 +254,8 @@ __create_page_tables: addne r3, r3, #PAGE_OFFSET addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) orrne r6, r7, r0 + strne r6, [r3], #1 << PMD_ORDER + addne r6, r6, #1 << SECTION_SHIFT strne r6, [r3] #ifdef CONFIG_DEBUG_LL @@ -331,7 +334,7 @@ ENTRY(secondary_startup) * as it has already been validated by the primary processor. */ #ifdef CONFIG_ARM_VIRT_EXT - bl __hyp_stub_install + bl __hyp_stub_install_secondary #endif safe_svcmode_maskall r9 diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S index 65b2417..1315c4c 100644 --- a/arch/arm/kernel/hyp-stub.S +++ b/arch/arm/kernel/hyp-stub.S @@ -99,7 +99,7 @@ ENTRY(__hyp_stub_install_secondary) * immediately. */ compare_cpu_mode_with_primary r4, r5, r6, r7 - bxne lr + movne pc, lr /* * Once we have given up on one CPU, we do not try to install the @@ -111,7 +111,7 @@ ENTRY(__hyp_stub_install_secondary) */ cmp r4, #HYP_MODE - bxne lr @ give up if the CPU is not in HYP mode + movne pc, lr @ give up if the CPU is not in HYP mode /* * Configure HSCTLR to set correct exception endianness/instruction set @@ -120,7 +120,8 @@ ENTRY(__hyp_stub_install_secondary) * Eventually, CPU-specific code might be needed -- assume not for now * * This code relies on the "eret" instruction to synchronize the - * various coprocessor accesses. + * various coprocessor accesses. This is done when we switch to SVC + * (see safe_svcmode_maskall). */ @ Now install the hypervisor stub: adr r7, __hyp_stub_vectors @@ -155,14 +156,7 @@ THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE 1: #endif - bic r7, r4, #MODE_MASK - orr r7, r7, #SVC_MODE -THUMB( orr r7, r7, #PSR_T_BIT ) - msr spsr_cxsf, r7 @ This is SPSR_hyp. - - __MSR_ELR_HYP(14) @ msr elr_hyp, lr - __ERET @ return, switching to SVC mode - @ The boot CPU mode is left in r4. + bx lr @ The boot CPU mode is left in r4. ENDPROC(__hyp_stub_install_secondary) __hyp_stub_do_trap: @@ -200,7 +194,7 @@ ENDPROC(__hyp_get_vectors) @ fall through ENTRY(__hyp_set_vectors) __HVC(0) - bx lr + mov pc, lr ENDPROC(__hyp_set_vectors) #ifndef ZIMAGE diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index f9e8657..31e0eb3 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -149,12 +149,6 @@ again: static void armpmu_read(struct perf_event *event) { - struct hw_perf_event *hwc = &event->hw; - - /* Don't read disabled counters! */ - if (hwc->idx < 0) - return; - armpmu_event_update(event); } @@ -207,8 +201,6 @@ armpmu_del(struct perf_event *event, int flags) struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; - WARN_ON(idx < 0); - armpmu_stop(event, PERF_EF_UPDATE); hw_events->events[idx] = NULL; clear_bit(idx, hw_events->used_mask); @@ -358,7 +350,7 @@ __hw_perf_event_init(struct perf_event *event) { struct arm_pmu *armpmu = to_arm_pmu(event->pmu); struct hw_perf_event *hwc = &event->hw; - int mapping, err; + int mapping; mapping = armpmu->map_event(event); @@ -407,14 +399,12 @@ __hw_perf_event_init(struct perf_event *event) local64_set(&hwc->period_left, hwc->sample_period); } - err = 0; if (event->group_leader != event) { - err = validate_group(event); - if (err) + if (validate_group(event) != 0); return -EINVAL; } - return err; + return 0; } static int armpmu_event_init(struct perf_event *event) diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c index 5f66206..1f2740e 100644 --- a/arch/arm/kernel/perf_event_cpu.c +++ b/arch/arm/kernel/perf_event_cpu.c @@ -147,7 +147,7 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->free_irq = cpu_pmu_free_irq; /* Ensure the PMU has sane values out of reset. */ - if (cpu_pmu && cpu_pmu->reset) + if (cpu_pmu->reset) on_each_cpu(cpu_pmu->reset, cpu_pmu, 1); } @@ -201,48 +201,46 @@ static struct platform_device_id cpu_pmu_plat_device_ids[] = { static int probe_current_pmu(struct arm_pmu *pmu) { int cpu = get_cpu(); - unsigned long cpuid = read_cpuid_id(); - unsigned long implementor = (cpuid & 0xFF000000) >> 24; - unsigned long part_number = (cpuid & 0xFFF0); + unsigned long implementor = read_cpuid_implementor(); + unsigned long part_number = read_cpuid_part_number(); int ret = -ENODEV; pr_info("probing PMU on CPU %d\n", cpu); /* ARM Ltd CPUs. */ - if (0x41 == implementor) { + if (implementor == ARM_CPU_IMP_ARM) { switch (part_number) { - case 0xB360: /* ARM1136 */ - case 0xB560: /* ARM1156 */ - case 0xB760: /* ARM1176 */ + case ARM_CPU_PART_ARM1136: + case ARM_CPU_PART_ARM1156: + case ARM_CPU_PART_ARM1176: ret = armv6pmu_init(pmu); break; - case 0xB020: /* ARM11mpcore */ + case ARM_CPU_PART_ARM11MPCORE: ret = armv6mpcore_pmu_init(pmu); break; - case 0xC080: /* Cortex-A8 */ + case ARM_CPU_PART_CORTEX_A8: ret = armv7_a8_pmu_init(pmu); break; - case 0xC090: /* Cortex-A9 */ + case ARM_CPU_PART_CORTEX_A9: ret = armv7_a9_pmu_init(pmu); break; - case 0xC050: /* Cortex-A5 */ + case ARM_CPU_PART_CORTEX_A5: ret = armv7_a5_pmu_init(pmu); break; - case 0xC0F0: /* Cortex-A15 */ + case ARM_CPU_PART_CORTEX_A15: ret = armv7_a15_pmu_init(pmu); break; - case 0xC070: /* Cortex-A7 */ + case ARM_CPU_PART_CORTEX_A7: ret = armv7_a7_pmu_init(pmu); break; } /* Intel CPUs [xscale]. */ - } else if (0x69 == implementor) { - part_number = (cpuid >> 13) & 0x7; - switch (part_number) { - case 1: + } else if (implementor == ARM_CPU_IMP_INTEL) { + switch (xscale_cpu_arch_version()) { + case ARM_CPU_XSCALE_ARCH_V1: ret = xscale1pmu_init(pmu); break; - case 2: + case ARM_CPU_XSCALE_ARCH_V2: ret = xscale2pmu_init(pmu); break; } @@ -279,17 +277,22 @@ static int cpu_pmu_device_probe(struct platform_device *pdev) } if (ret) { - pr_info("failed to register PMU devices!"); - kfree(pmu); - return ret; + pr_info("failed to probe PMU!"); + goto out_free; } cpu_pmu = pmu; cpu_pmu->plat_device = pdev; cpu_pmu_init(cpu_pmu); - armpmu_register(cpu_pmu, PERF_TYPE_RAW); + ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW); - return 0; + if (!ret) + return 0; + +out_free: + pr_info("failed to register PMU devices!"); + kfree(pmu); + return ret; } static struct platform_driver cpu_pmu_driver = { diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c index 041d052..03664b0 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/arch/arm/kernel/perf_event_v6.c @@ -106,7 +106,7 @@ static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, @@ -259,7 +259,7 @@ static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 4fbc757..8c79a9e 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -157,8 +157,8 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS, - [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, @@ -282,7 +282,7 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, @@ -399,8 +399,8 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, - [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, /* * The prefetch counters don't differentiate between the I @@ -527,8 +527,8 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, - [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, @@ -651,8 +651,8 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, - [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c index 2b0fe30..63990c4 100644 --- a/arch/arm/kernel/perf_event_xscale.c +++ b/arch/arm/kernel/perf_event_xscale.c @@ -83,7 +83,7 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index 180b302..2acdff4 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -174,7 +174,6 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) static struct clock_event_device clkevt = { .name = "at91_tick", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .rating = 150, .set_next_event = clkevt32k_next_event, .set_mode = clkevt32k_mode, @@ -265,11 +264,9 @@ void __init at91rm9200_timer_init(void) at91_st_write(AT91_ST_RTMR, 1); /* Setup timer clockevent, with minimum of two ticks (important!!) */ - clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift); - clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt); - clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1; clkevt.cpumask = cpumask_of(0); - clockevents_register_device(&clkevt); + clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK, + 2, AT91_ST_ALMV); /* register clocksource */ clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 9ee866c..4b67847 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -105,6 +105,8 @@ static void __init soc_detect(u32 dbgu_base) switch (socid) { case ARCH_ID_AT91RM9200: at91_soc_initdata.type = AT91_SOC_RM9200; + if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE) + at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; at91_boot_soc = at91rm9200_soc; break; diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c index 23ed015..f0f9aba 100644 --- a/arch/arm/mach-bcm/board_bcm.c +++ b/arch/arm/mach-bcm/board_bcm.c @@ -24,6 +24,7 @@ static void timer_init(void) { } + static void __init board_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c index 176d2d2..1a446a1 100644 --- a/arch/arm/mach-bcm2835/bcm2835.c +++ b/arch/arm/mach-bcm2835/bcm2835.c @@ -26,11 +26,13 @@ #include <mach/bcm2835_soc.h> #define PM_RSTC 0x1c +#define PM_RSTS 0x20 #define PM_WDOG 0x24 #define PM_PASSWORD 0x5a000000 #define PM_RSTC_WRCFG_MASK 0x00000030 #define PM_RSTC_WRCFG_FULL_RESET 0x00000020 +#define PM_RSTS_HADWRH_SET 0x00000040 static void __iomem *wdt_regs; @@ -67,6 +69,29 @@ static void bcm2835_restart(char mode, const char *cmd) mdelay(1); } +/* + * We can't really power off, but if we do the normal reset scheme, and + * indicate to bootcode.bin not to reboot, then most of the chip will be + * powered off. + */ +static void bcm2835_power_off(void) +{ + u32 val; + + /* + * We set the watchdog hard reset bit here to distinguish this reset + * from the normal (full) reset. bootcode.bin will not reboot after a + * hard reset. + */ + val = readl_relaxed(wdt_regs + PM_RSTS); + val &= ~PM_RSTC_WRCFG_MASK; + val |= PM_PASSWORD | PM_RSTS_HADWRH_SET; + writel_relaxed(val, wdt_regs + PM_RSTS); + + /* Continue with normal reset mechanism */ + bcm2835_restart(0, ""); +} + static struct map_desc io_map __initdata = { .virtual = BCM2835_PERIPH_VIRT, .pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS), @@ -84,6 +109,9 @@ static void __init bcm2835_init(void) int ret; bcm2835_setup_restart(); + if (wdt_regs) + pm_power_off = bcm2835_power_off; + bcm2835_init_clocks(); ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index 27d57d1..e698f26 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -134,7 +134,6 @@ static int cns3xxx_timer_set_next_event(unsigned long evt, static struct clock_event_device cns3xxx_tmr1_clockevent = { .name = "cns3xxx timer1", - .shift = 8, .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_mode = cns3xxx_timer_set_mode, .set_next_event = cns3xxx_timer_set_next_event, @@ -145,15 +144,9 @@ static struct clock_event_device cns3xxx_tmr1_clockevent = { static void __init cns3xxx_clockevents_init(unsigned int timer_irq) { cns3xxx_tmr1_clockevent.irq = timer_irq; - cns3xxx_tmr1_clockevent.mult = - div_sc((cns3xxx_cpu_clock() >> 3) * 1000000, NSEC_PER_SEC, - cns3xxx_tmr1_clockevent.shift); - cns3xxx_tmr1_clockevent.max_delta_ns = - clockevent_delta2ns(0xffffffff, &cns3xxx_tmr1_clockevent); - cns3xxx_tmr1_clockevent.min_delta_ns = - clockevent_delta2ns(0xf, &cns3xxx_tmr1_clockevent); - - clockevents_register_device(&cns3xxx_tmr1_clockevent); + clockevents_config_and_register(&cns3xxx_tmr1_clockevent, + (cns3xxx_cpu_clock() >> 3) * 1000000, + 0xf, 0xffffffff); } /* diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index e374271..6da25ee 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -652,8 +652,13 @@ static __init void da830_evm_init(void) if (ret) pr_warning("da830_evm_init: rtc setup failed: %d\n", ret); - ret = da8xx_register_spi(0, da830evm_spi_info, - ARRAY_SIZE(da830evm_spi_info)); + ret = spi_register_board_info(da830evm_spi_info, + ARRAY_SIZE(da830evm_spi_info)); + if (ret) + pr_warn("%s: spi info registration failed: %d\n", __func__, + ret); + + ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info)); if (ret) pr_warning("da830_evm_init: spi 0 registration failed: %d\n", ret); diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 3b33560..3a76a47 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -1565,8 +1565,13 @@ static __init void da850_evm_init(void) da850_vpif_init(); - ret = da8xx_register_spi(1, da850evm_spi_info, - ARRAY_SIZE(da850evm_spi_info)); + ret = spi_register_board_info(da850evm_spi_info, + ARRAY_SIZE(da850evm_spi_info)); + if (ret) + pr_warn("%s: spi info registration failed: %d\n", __func__, + ret); + + ret = da8xx_register_spi_bus(1, ARRAY_SIZE(da850evm_spi_info)); if (ret) pr_warning("da850_evm_init: spi 1 registration failed: %d\n", ret); diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index b0df578..9549d53 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -529,8 +529,13 @@ static void __init mityomapl138_init(void) mityomapl138_setup_nand(); - ret = da8xx_register_spi(1, mityomapl138_spi_flash_info, - ARRAY_SIZE(mityomapl138_spi_flash_info)); + ret = spi_register_board_info(mityomapl138_spi_flash_info, + ARRAY_SIZE(mityomapl138_spi_flash_info)); + if (ret) + pr_warn("spi info registration failed: %d\n", ret); + + ret = da8xx_register_spi_bus(1, + ARRAY_SIZE(mityomapl138_spi_flash_info)); if (ret) pr_warning("spi 1 registration failed: %d\n", ret); diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 34668ea..d458558 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -52,6 +52,40 @@ static void __clk_disable(struct clk *clk) __clk_disable(clk->parent); } +int davinci_clk_reset(struct clk *clk, bool reset) +{ + unsigned long flags; + + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + spin_lock_irqsave(&clockfw_lock, flags); + if (clk->flags & CLK_PSC) + davinci_psc_reset(clk->gpsc, clk->lpsc, reset); + spin_unlock_irqrestore(&clockfw_lock, flags); + + return 0; +} +EXPORT_SYMBOL(davinci_clk_reset); + +int davinci_clk_reset_assert(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk) || !clk->reset) + return -EINVAL; + + return clk->reset(clk, true); +} +EXPORT_SYMBOL(davinci_clk_reset_assert); + +int davinci_clk_reset_deassert(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk) || !clk->reset) + return -EINVAL; + + return clk->reset(clk, false); +} +EXPORT_SYMBOL(davinci_clk_reset_deassert); + int clk_enable(struct clk *clk) { unsigned long flags; @@ -535,7 +569,7 @@ int davinci_set_refclk_rate(unsigned long rate) } int __init davinci_clk_init(struct clk_lookup *clocks) - { +{ struct clk_lookup *c; struct clk *clk; size_t num_clocks = 0; @@ -576,6 +610,9 @@ int __init davinci_clk_init(struct clk_lookup *clocks) if (clk->lpsc) clk->flags |= CLK_PSC; + if (clk->flags & PSC_LRST) + clk->reset = davinci_clk_reset; + clk_register(clk); num_clocks++; diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 46f0f1b..8694b39 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -103,6 +103,7 @@ struct clk { unsigned long (*recalc) (struct clk *); int (*set_rate) (struct clk *clk, unsigned long rate); int (*round_rate) (struct clk *clk, unsigned long rate); + int (*reset) (struct clk *clk, bool reset); }; /* Clock flags: SoC-specific flags start at BIT(16) */ @@ -112,6 +113,7 @@ struct clk { #define PRE_PLL BIT(4) /* source is before PLL mult/div */ #define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */ #define PSC_FORCE BIT(6) /* Force module state transtition */ +#define PSC_LRST BIT(8) /* Use local reset on enable/disable */ #define CLK(dev, con, ck) \ { \ @@ -126,6 +128,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); int davinci_set_refclk_rate(unsigned long rate); int davinci_simple_set_rate(struct clk *clk, unsigned long rate); +int davinci_clk_reset(struct clk *clk, bool reset); extern struct platform_device davinci_wdt_device; extern void davinci_watchdog_reset(struct platform_device *); diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 6b9154e..0c4a26d 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -76,6 +76,13 @@ static struct clk pll0_aux_clk = { .flags = CLK_PLL | PRE_PLL, }; +static struct clk pll0_sysclk1 = { + .name = "pll0_sysclk1", + .parent = &pll0_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + static struct clk pll0_sysclk2 = { .name = "pll0_sysclk2", .parent = &pll0_clk, @@ -368,10 +375,19 @@ static struct clk sata_clk = { .flags = PSC_FORCE, }; +static struct clk dsp_clk = { + .name = "dsp", + .parent = &pll0_sysclk1, + .domain = DAVINCI_GPSC_DSPDOMAIN, + .lpsc = DA8XX_LPSC0_GEM, + .flags = PSC_LRST | PSC_FORCE, +}; + static struct clk_lookup da850_clks[] = { CLK(NULL, "ref", &ref_clk), CLK(NULL, "pll0", &pll0_clk), CLK(NULL, "pll0_aux", &pll0_aux_clk), + CLK(NULL, "pll0_sysclk1", &pll0_sysclk1), CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), @@ -413,6 +429,7 @@ static struct clk_lookup da850_clks[] = { CLK("spi_davinci.1", NULL, &spi1_clk), CLK("vpif", NULL, &vpif_clk), CLK("ahci", NULL, &sata_clk), + CLK("davinci-rproc.0", NULL, &dsp_clk), CLK(NULL, NULL, NULL), }; diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 2d5502d..aa402bc 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -751,7 +751,7 @@ void __iomem * __init da8xx_get_mem_ctlr(void) da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K); if (!da8xx_ddr2_ctlr_base) - pr_warning("%s: Unable to map DDR2 controller", __func__); + pr_warn("%s: Unable to map DDR2 controller", __func__); return da8xx_ddr2_ctlr_base; } @@ -832,7 +832,7 @@ static struct resource da8xx_spi1_resources[] = { }, }; -struct davinci_spi_platform_data da8xx_spi_pdata[] = { +static struct davinci_spi_platform_data da8xx_spi_pdata[] = { [0] = { .version = SPI_VERSION_2, .intr_line = 1, @@ -866,20 +866,12 @@ static struct platform_device da8xx_spi_device[] = { }, }; -int __init da8xx_register_spi(int instance, const struct spi_board_info *info, - unsigned len) +int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect) { - int ret; - if (instance < 0 || instance > 1) return -EINVAL; - ret = spi_register_board_info(info, len); - if (ret) - pr_warning("%s: failed to register board info for spi %d :" - " %d\n", __func__, instance, ret); - - da8xx_spi_pdata[instance].num_chipselect = len; + da8xx_spi_pdata[instance].num_chipselect = num_chipselect; if (instance == 1 && cpu_is_davinci_da850()) { da8xx_spi1_resources[0].start = DA850_SPI1_BASE; diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h index a3b0402..3e8af6a 100644 --- a/arch/arm/mach-davinci/include/mach/clock.h +++ b/arch/arm/mach-davinci/include/mach/clock.h @@ -18,4 +18,7 @@ struct clk; extern int clk_register(struct clk *clk); extern void clk_unregister(struct clk *clk); +int davinci_clk_reset_assert(struct clk *c); +int davinci_clk_reset_deassert(struct clk *c); + #endif diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 700d311..1b14aea 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -82,8 +82,7 @@ void __init da850_init(void); int da830_register_edma(struct edma_rsv_info *rsv); int da850_register_edma(struct edma_rsv_info *rsv[2]); int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); -int da8xx_register_spi(int instance, - const struct spi_board_info *info, unsigned len); +int da8xx_register_spi_bus(int instance, unsigned num_chipselect); int da8xx_register_watchdog(void); int da8xx_register_usb20(unsigned mA, unsigned potpgt); int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata); @@ -110,7 +109,6 @@ extern struct platform_device da8xx_serial_device; extern struct emac_platform_data da8xx_emac_pdata; extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata; extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata; -extern struct davinci_spi_platform_data da8xx_spi_pdata[]; extern struct platform_device da8xx_wdt_device; diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 40a0027..0a22710 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -246,6 +246,7 @@ #define MDSTAT_STATE_MASK 0x3f #define PDSTAT_STATE_MASK 0x1f +#define MDCTL_LRST BIT(8) #define MDCTL_FORCE BIT(31) #define PDCTL_NEXT BIT(0) #define PDCTL_EPCGOOD BIT(8) @@ -253,6 +254,8 @@ #ifndef __ASSEMBLER__ extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); +extern void davinci_psc_reset(unsigned int ctlr, unsigned int id, + bool reset); extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, unsigned int id, bool enable, u32 flags); diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index d7e210f..82fdc69 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -35,7 +35,7 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) struct davinci_soc_info *soc_info = &davinci_soc_info; if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { - pr_warning("PSC: Bad psc data: 0x%x[%d]\n", + pr_warn("PSC: Bad psc data: 0x%x[%d]\n", (int)soc_info->psc_bases, ctlr); return 0; } @@ -48,6 +48,31 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) return mdstat & BIT(12); } +/* Control "reset" line associated with PSC domain */ +void davinci_psc_reset(unsigned int ctlr, unsigned int id, bool reset) +{ + u32 mdctl; + void __iomem *psc_base; + struct davinci_soc_info *soc_info = &davinci_soc_info; + + if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { + pr_warn("PSC: Bad psc data: 0x%x[%d]\n", + (int)soc_info->psc_bases, ctlr); + return; + } + + psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); + + mdctl = readl(psc_base + MDCTL + 4 * id); + if (reset) + mdctl &= ~MDCTL_LRST; + else + mdctl |= MDCTL_LRST; + writel(mdctl, psc_base + MDCTL + 4 * id); + + iounmap(psc_base); +} + /* Enable or disable a PSC domain */ void davinci_psc_config(unsigned int domain, unsigned int ctlr, unsigned int id, bool enable, u32 flags) @@ -58,7 +83,7 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr, u32 next_state = PSC_STATE_ENABLE; if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { - pr_warning("PSC: Bad psc data: 0x%x[%d]\n", + pr_warn("PSC: Bad psc data: 0x%x[%d]\n", (int)soc_info->psc_bases, ctlr); return; } diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c index 668d1a6..c9d6650 100644 --- a/arch/arm/mach-exynos/mct.c +++ b/arch/arm/mach-exynos/mct.c @@ -254,13 +254,9 @@ static struct irqaction mct_comp_event_irq = { static void exynos4_clockevent_init(void) { - clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5); - mct_comp_device.max_delta_ns = - clockevent_delta2ns(0xffffffff, &mct_comp_device); - mct_comp_device.min_delta_ns = - clockevent_delta2ns(0xf, &mct_comp_device); mct_comp_device.cpumask = cpumask_of(0); - clockevents_register_device(&mct_comp_device); + clockevents_config_and_register(&mct_comp_device, clk_rate, + 0xf, 0xffffffff); if (soc_is_exynos5250()) setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq); @@ -403,14 +399,8 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) evt->set_mode = exynos4_tick_set_mode; evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; evt->rating = 450; - - clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5); - evt->max_delta_ns = - clockevent_delta2ns(0x7fffffff, evt); - evt->min_delta_ns = - clockevent_delta2ns(0xf, evt); - - clockevents_register_device(evt); + clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), + 0xf, 0x7fffffff); exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index 9f14b1d..9ee78f7 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c @@ -101,10 +101,6 @@ void __init footbridge_timer_init(void) setup_irq(ce->irq, &footbridge_timer_irq); - clockevents_calc_mult_shift(ce, mem_fclk_21285, 5); - ce->max_delta_ns = clockevent_delta2ns(0xffffff, ce); - ce->min_delta_ns = clockevent_delta2ns(0x000004, ce); ce->cpumask = cpumask_of(smp_processor_id()); - - clockevents_register_device(ce); + clockevents_config_and_register(ce, mem_fclk_21285, 0x4, 0xffffff); } diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3e628fd..7b11d33 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -95,9 +95,6 @@ config MACH_MX27 config ARCH_MX5 bool -config ARCH_MX50 - bool - config ARCH_MX51 bool @@ -164,11 +161,6 @@ config SOC_IMX5 select CPU_V7 select MXC_TZIC -config SOC_IMX50 - bool - select ARCH_MX50 - select SOC_IMX5 - config SOC_IMX51 bool select ARCH_MX5 @@ -738,25 +730,10 @@ endif if ARCH_MULTI_V7 -comment "i.MX5 platforms:" - -config MACH_MX50_RDP - bool "Support MX50 reference design platform" - depends on BROKEN - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select SOC_IMX50 - help - Include support for MX50 reference design platform (RDP) board. This - includes specific configurations for the board and its peripherals. - comment "i.MX51 machines:" config MACH_IMX51_DT bool "Support i.MX51 platforms from device tree" - select MACH_MX51_BABBAGE select SOC_IMX51 help Include support for Freescale i.MX51 based platforms @@ -777,19 +754,6 @@ config MACH_MX51_BABBAGE u-boot. This includes specific configurations for the board and its peripherals. -config MACH_MX51_3DS - bool "Support MX51PDK (3DS)" - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_DEBUG_BOARD - select SOC_IMX51 - help - Include support for MX51PDK (3DS) platform. This includes specific - configurations for the board and its peripherals. - config MACH_EUKREA_CPUIMX51SD bool "Support Eukrea CPUIMX51SD module" select IMX_HAVE_PLATFORM_FSL_USB2_UDC @@ -851,6 +815,7 @@ config SOC_IMX6Q select HAVE_CAN_FLEXCAN if CAN select HAVE_IMX_GPC select HAVE_IMX_MMDC + select HAVE_IMX_SRC select HAVE_SMP select MFD_SYSCON select PINCTRL diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 0634b31..c4ce090 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -28,7 +28,11 @@ obj-$(CONFIG_MXC_ULPI) += ulpi.o obj-$(CONFIG_MXC_USE_EPIT) += epit.o obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o -obj-$(CONFIG_CPU_IDLE) += cpuidle.o + +ifeq ($(CONFIG_CPU_IDLE),y) +obj-y += cpuidle.o +obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o +endif ifdef CONFIG_SND_IMX_SOC obj-y += ssi-fiq.o @@ -88,7 +92,6 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o -obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o obj-$(CONFIG_HAVE_IMX_SRC) += src.o @@ -103,10 +106,8 @@ endif # i.MX5 based machines obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o -obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o -obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o obj-$(CONFIG_SOC_IMX53) += mach-imx53.o diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index b27815d..41ba1bb 100644 --- a/arch/arm/mach-imx/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot @@ -22,10 +22,6 @@ zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000 params_phys-$(CONFIG_SOC_IMX35) := 0x80000100 initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000 -zreladdr-$(CONFIG_SOC_IMX50) += 0x70008000 -params_phys-$(CONFIG_SOC_IMX50) := 0x70000100 -initrd_phys-$(CONFIG_SOC_IMX50) := 0x70800000 - zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000 params_phys-$(CONFIG_SOC_IMX51) := 0x90000100 initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000 diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index b197aa7..2c570cda 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -254,9 +254,9 @@ int __init mx25_clocks_init(void) clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2"); clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); - clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc"); - clk_register_clkdev(clk[usbotg_ahb], "ahb", "fsl-usb2-udc"); - clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc"); + clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); + clk_register_clkdev(clk[usbotg_ahb], "ahb", "imx-udc-mx27"); + clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0"); /* i.mx25 has the i.mx35 type cspi */ clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0"); diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index 4c1d1e4..d24b0d6 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -62,7 +62,7 @@ static const char *clko_sel_clks[] = { "32k", "usb_div", "dptc", }; -static const char *ssi_sel_clks[] = { "spll", "mpll", }; +static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; enum mx27_clks { dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div, @@ -82,7 +82,7 @@ enum mx27_clks { csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate, uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate, uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel, - mpll_sel, clk_max + mpll_sel, spll_gate, clk_max }; static struct clk *clk[clk_max]; @@ -104,6 +104,7 @@ int __init mx27_clocks_init(unsigned long fref) ARRAY_SIZE(mpll_sel_clks)); clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0); + clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { @@ -121,7 +122,7 @@ int __init mx27_clocks_init(unsigned long fref) clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); - clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3); + clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3); clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); if (mx27_revision() >= IMX_CHIP_REVISION_2_0) @@ -236,9 +237,9 @@ int __init mx27_clocks_init(unsigned long fref) clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0"); clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0"); clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0"); - clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc"); - clk_register_clkdev(clk[usb_ipg_gate], "ipg", "fsl-usb2-udc"); - clk_register_clkdev(clk[usb_ahb_gate], "ahb", "fsl-usb2-udc"); + clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); + clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27"); + clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27"); clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0"); clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0"); diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c index 8be64e0..b5b65f3 100644 --- a/arch/arm/mach-imx/clk-imx31.c +++ b/arch/arm/mach-imx/clk-imx31.c @@ -34,8 +34,8 @@ static const char *csi_sel[] = { "upll", "spll", }; static const char *fir_sel[] = { "mcu_main", "upll", "spll" }; enum mx31_clks { - ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div, - per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre, + dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, + per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre, fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate, iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate, uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate, @@ -46,12 +46,15 @@ enum mx31_clks { }; static struct clk *clk[clk_max]; +static struct clk_onecell_data clk_data; int __init mx31_clocks_init(unsigned long fref) { void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); int i; + struct device_node *np; + clk[dummy] = imx_clk_fixed("dummy", 0); clk[ckih] = imx_clk_fixed("ckih", fref); clk[ckil] = imx_clk_fixed("ckil", 32768); clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL); @@ -116,6 +119,14 @@ int __init mx31_clocks_init(unsigned long fref) pr_err("imx31 clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); + np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm"); + + if (np) { + clk_data.clks = clk; + clk_data.clk_num = ARRAY_SIZE(clk); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + } + clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0"); @@ -139,9 +150,9 @@ int __init mx31_clocks_init(unsigned long fref) clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2"); clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2"); clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); - clk_register_clkdev(clk[usb_div_post], "per", "fsl-usb2-udc"); - clk_register_clkdev(clk[usb_gate], "ahb", "fsl-usb2-udc"); - clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc"); + clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27"); + clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27"); + clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); /* i.mx31 has the i.mx21 type uart */ clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c index 66f3d65..74e3a34 100644 --- a/arch/arm/mach-imx/clk-imx35.c +++ b/arch/arm/mach-imx/clk-imx35.c @@ -67,13 +67,13 @@ enum mx35_clks { static struct clk *clk[clk_max]; -int __init mx35_clocks_init() +int __init mx35_clocks_init(void) { void __iomem *base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); u32 pdr0, consumer_sel, hsp_sel; struct arm_ahb_div *aad; unsigned char *hsp_div; - int i; + u32 i; pdr0 = __raw_readl(base + MXC_CCM_PDR0); consumer_sel = (pdr0 >> 16) & 0xf; @@ -251,9 +251,9 @@ int __init mx35_clocks_init() clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2"); - clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc"); - clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc"); - clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc"); + clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); + clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); + clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27"); clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0"); clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 579023f..fb7cb84 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -269,9 +269,9 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2"); clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2"); clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2"); - clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc"); - clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc"); - clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc"); + clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51"); + clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51"); + clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51"); clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand"); clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 7f2c10c..540138c 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -54,9 +54,18 @@ #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) +#define CGPR 0x64 +#define BM_CGPR_CHICKEN_BIT (0x1 << 17) + static void __iomem *ccm_base; -void __init imx6q_clock_map_io(void) { } +void imx6q_set_chicken_bit(void) +{ + u32 val = readl_relaxed(ccm_base + CGPR); + + val |= BM_CGPR_CHICKEN_BIT; + writel_relaxed(val, ccm_base + CGPR); +} int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) { @@ -68,6 +77,7 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) break; case WAIT_UNCLOCKED: val |= 0x1 << BP_CLPCR_LPM; + val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; break; case STOP_POWER_ON: val |= 0x2 << BP_CLPCR_LPM; @@ -436,6 +446,9 @@ int __init mx6q_clocks_init(void) for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clk[clks_init_on[i]]); + /* Set initial power mode */ + imx6q_set_lpm(WAIT_CLOCKED); + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); base = of_iomap(np, 0); WARN_ON(!base); diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index b0164da..5a800bf 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -21,7 +21,6 @@ extern void mx25_map_io(void); extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); -extern void mx50_map_io(void); extern void mx51_map_io(void); extern void mx53_map_io(void); extern void imx1_init_early(void); @@ -30,7 +29,6 @@ extern void imx25_init_early(void); extern void imx27_init_early(void); extern void imx31_init_early(void); extern void imx35_init_early(void); -extern void imx50_init_early(void); extern void imx51_init_early(void); extern void imx53_init_early(void); extern void mxc_init_irq(void __iomem *); @@ -41,7 +39,6 @@ extern void mx25_init_irq(void); extern void mx27_init_irq(void); extern void mx31_init_irq(void); extern void mx35_init_irq(void); -extern void mx50_init_irq(void); extern void mx51_init_irq(void); extern void mx53_init_irq(void); extern void imx1_soc_init(void); @@ -50,7 +47,6 @@ extern void imx25_soc_init(void); extern void imx27_soc_init(void); extern void imx31_soc_init(void); extern void imx35_soc_init(void); -extern void imx50_soc_init(void); extern void imx51_soc_init(void); extern void imx51_init_late(void); extern void imx53_init_late(void); @@ -109,26 +105,22 @@ void tzic_handle_irq(struct pt_regs *); #define imx27_handle_irq avic_handle_irq #define imx31_handle_irq avic_handle_irq #define imx35_handle_irq avic_handle_irq -#define imx50_handle_irq tzic_handle_irq #define imx51_handle_irq tzic_handle_irq #define imx53_handle_irq tzic_handle_irq extern void imx_enable_cpu(int cpu, bool enable); extern void imx_set_cpu_jump(int cpu, void *jump_addr); -#ifdef CONFIG_DEBUG_LL -extern void imx_lluart_map_io(void); -#else -static inline void imx_lluart_map_io(void) {} -#endif extern void v7_cpu_resume(void); extern u32 *pl310_get_save_ptr(void); #ifdef CONFIG_SMP extern void v7_secondary_startup(void); extern void imx_scu_map_io(void); extern void imx_smp_prepare(void); +extern void imx_scu_standby_enable(void); #else static inline void imx_scu_map_io(void) {} static inline void imx_smp_prepare(void) {} +static inline void imx_scu_standby_enable(void) {} #endif extern void imx_enable_cpu(int cpu, bool enable); extern void imx_set_cpu_jump(int cpu, void *jump_addr); @@ -138,9 +130,10 @@ extern void imx_gpc_init(void); extern void imx_gpc_pre_suspend(void); extern void imx_gpc_post_resume(void); extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -extern void imx6q_clock_map_io(void); +extern void imx6q_set_chicken_bit(void); extern void imx_cpu_die(unsigned int cpu); +extern int imx_cpu_kill(unsigned int cpu); #ifdef CONFIG_PM extern void imx6q_pm_init(void); diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c index d887600..d7ce722 100644 --- a/arch/arm/mach-imx/cpu-imx5.c +++ b/arch/arm/mach-imx/cpu-imx5.c @@ -22,7 +22,6 @@ static int mx5_cpu_rev = -1; #define IIM_SREV 0x24 -#define MX50_HW_ADADIG_DIGPROG 0xB0 static int get_mx51_srev(void) { @@ -108,41 +107,3 @@ int mx53_revision(void) return mx5_cpu_rev; } EXPORT_SYMBOL(mx53_revision); - -static int get_mx50_srev(void) -{ - void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K); - u32 rev; - - if (!anatop) { - mx5_cpu_rev = -EINVAL; - return 0; - } - - rev = readl(anatop + MX50_HW_ADADIG_DIGPROG); - rev &= 0xff; - - iounmap(anatop); - if (rev == 0x0) - return IMX_CHIP_REVISION_1_0; - else if (rev == 0x1) - return IMX_CHIP_REVISION_1_1; - return 0; -} - -/* - * Returns: - * the silicon revision of the cpu - * -EINVAL - not a mx50 - */ -int mx50_revision(void) -{ - if (!cpu_is_mx50()) - return -EINVAL; - - if (mx5_cpu_rev == -1) - mx5_cpu_rev = get_mx50_srev(); - - return mx5_cpu_rev; -} -EXPORT_SYMBOL(mx50_revision); diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c new file mode 100644 index 0000000..d533e26 --- /dev/null +++ b/arch/arm/mach-imx/cpuidle-imx6q.c @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/clockchips.h> +#include <linux/cpuidle.h> +#include <linux/module.h> +#include <asm/cpuidle.h> +#include <asm/proc-fns.h> + +#include "common.h" +#include "cpuidle.h" + +static atomic_t master = ATOMIC_INIT(0); +static DEFINE_SPINLOCK(master_lock); + +static int imx6q_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + int cpu = dev->cpu; + + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); + + if (atomic_inc_return(&master) == num_online_cpus()) { + /* + * With this lock, we prevent other cpu to exit and enter + * this function again and become the master. + */ + if (!spin_trylock(&master_lock)) + goto idle; + imx6q_set_lpm(WAIT_UNCLOCKED); + cpu_do_idle(); + imx6q_set_lpm(WAIT_CLOCKED); + spin_unlock(&master_lock); + goto done; + } + +idle: + cpu_do_idle(); +done: + atomic_dec(&master); + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); + + return index; +} + +/* + * For each cpu, setup the broadcast timer because local timer + * stops for the states other than WFI. + */ +static void imx6q_setup_broadcast_timer(void *arg) +{ + int cpu = smp_processor_id(); + + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu); +} + +static struct cpuidle_driver imx6q_cpuidle_driver = { + .name = "imx6q_cpuidle", + .owner = THIS_MODULE, + .en_core_tk_irqen = 1, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .flags = CPUIDLE_FLAG_TIME_VALID, + .enter = imx6q_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + }, + .state_count = 2, + .safe_state_index = 0, +}; + +int __init imx6q_cpuidle_init(void) +{ + /* Need to enable SCU standby for entering WAIT modes */ + imx_scu_standby_enable(); + + /* Set chicken bit to get a reliable WAIT mode support */ + imx6q_set_chicken_bit(); + + /* Configure the broadcast timer on each cpu */ + on_each_cpu(imx6q_setup_broadcast_timer, NULL, 1); + + return imx_cpuidle_init(&imx6q_cpuidle_driver); +} diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h index bc932d1..e092d13 100644 --- a/arch/arm/mach-imx/cpuidle.h +++ b/arch/arm/mach-imx/cpuidle.h @@ -14,9 +14,14 @@ #ifdef CONFIG_CPU_IDLE extern int imx_cpuidle_init(struct cpuidle_driver *drv); +extern int imx6q_cpuidle_init(void); #else static inline int imx_cpuidle_init(struct cpuidle_driver *drv) { return -ENODEV; } +static inline int imx6q_cpuidle_init(void) +{ + return -ENODEV; +} #endif diff --git a/arch/arm/mach-imx/devices-imx50.h b/arch/arm/mach-imx/devices-imx50.h deleted file mode 100644 index 2c29039..0000000 --- a/arch/arm/mach-imx/devices-imx50.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include "devices/devices-common.h" - -extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[]; -#define imx50_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata) - -extern const struct imx_fec_data imx50_fec_data; -#define imx50_add_fec(pdata) \ - imx_add_fec(&imx50_fec_data, pdata) - -extern const struct imx_imx_i2c_data imx50_imx_i2c_data[]; -#define imx50_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata) diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig index 9a8f1ca..9b9ba1f 100644 --- a/arch/arm/mach-imx/devices/Kconfig +++ b/arch/arm/mach-imx/devices/Kconfig @@ -1,6 +1,6 @@ config IMX_HAVE_PLATFORM_FEC bool - default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53 + default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53 config IMX_HAVE_PLATFORM_FLEXCAN bool diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h index 6277baf..9bd5777 100644 --- a/arch/arm/mach-imx/devices/devices-common.h +++ b/arch/arm/mach-imx/devices/devices-common.h @@ -63,6 +63,7 @@ struct platform_device *__init imx_add_flexcan( #include <linux/fsl_devices.h> struct imx_fsl_usb2_udc_data { + const char *devid; resource_size_t iobase; resource_size_t irq; }; diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c index 2cb188a..63eba08 100644 --- a/arch/arm/mach-imx/devices/platform-fec.c +++ b/arch/arm/mach-imx/devices/platform-fec.c @@ -35,12 +35,6 @@ const struct imx_fec_data imx35_fec_data __initconst = imx_fec_data_entry_single(MX35, "imx27-fec"); #endif -#ifdef CONFIG_SOC_IMX50 -/* i.mx50 has the i.mx25 type fec */ -const struct imx_fec_data imx50_fec_data __initconst = - imx_fec_data_entry_single(MX50, "imx25-fec"); -#endif - #ifdef CONFIG_SOC_IMX51 /* i.mx51 has the i.mx27 type fec */ const struct imx_fec_data imx51_fec_data __initconst = diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c index 37e4439..3c06bd9 100644 --- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c +++ b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c @@ -11,35 +11,36 @@ #include "../hardware.h" #include "devices-common.h" -#define imx_fsl_usb2_udc_data_entry_single(soc) \ +#define imx_fsl_usb2_udc_data_entry_single(soc, _devid) \ { \ + .devid = _devid, \ .iobase = soc ## _USB_OTG_BASE_ADDR, \ .irq = soc ## _INT_USB_OTG, \ } #ifdef CONFIG_SOC_IMX25 const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX25); + imx_fsl_usb2_udc_data_entry_single(MX25, "imx-udc-mx27"); #endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX27); + imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27"); #endif /* ifdef CONFIG_SOC_IMX27 */ #ifdef CONFIG_SOC_IMX31 const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX31); + imx_fsl_usb2_udc_data_entry_single(MX31, "imx-udc-mx27"); #endif /* ifdef CONFIG_SOC_IMX31 */ #ifdef CONFIG_SOC_IMX35 const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX35); + imx_fsl_usb2_udc_data_entry_single(MX35, "imx-udc-mx27"); #endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_SOC_IMX51 const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX51); + imx_fsl_usb2_udc_data_entry_single(MX51, "imx-udc-mx51"); #endif struct platform_device *__init imx_add_fsl_usb2_udc( @@ -57,7 +58,7 @@ struct platform_device *__init imx_add_fsl_usb2_udc( .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device_dmamask("fsl-usb2-udc", -1, + return imx_add_platform_device_dmamask(data->devid, -1, res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); } diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c index 10b0ed3..25a47c6 100644 --- a/arch/arm/mach-imx/devices/platform-imx-fb.c +++ b/arch/arm/mach-imx/devices/platform-imx-fb.c @@ -54,7 +54,7 @@ struct platform_device *__init imx_add_imx_fb( .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device_dmamask("imx-fb", 0, + return imx_add_platform_device_dmamask(data->devid, 0, res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); } diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c index 8e30e57..57d342e 100644 --- a/arch/arm/mach-imx/devices/platform-imx-i2c.c +++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c @@ -70,16 +70,6 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_SOC_IMX50 -const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = { -#define imx50_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX50, "imx21-i2c", _id, _hwid, SZ_4K) - imx50_imx_i2c_data_entry(0, 1), - imx50_imx_i2c_data_entry(1, 2), - imx50_imx_i2c_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX51 */ - #ifdef CONFIG_SOC_IMX51 const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { #define imx51_imx_i2c_data_entry(_id, _hwid) \ diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c index 67bf866..faac4aa 100644 --- a/arch/arm/mach-imx/devices/platform-imx-uart.c +++ b/arch/arm/mach-imx/devices/platform-imx-uart.c @@ -94,18 +94,6 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_SOC_IMX50 -const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = { -#define imx50_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K) - imx50_imx_uart_data_entry(0, 1), - imx50_imx_uart_data_entry(1, 2), - imx50_imx_uart_data_entry(2, 3), - imx50_imx_uart_data_entry(3, 4), - imx50_imx_uart_data_entry(4, 5), -}; -#endif /* ifdef CONFIG_SOC_IMX50 */ - #ifdef CONFIG_SOC_IMX51 const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { #define imx51_imx_uart_data_entry(_id, _hwid) \ diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c index 04a5961..e02de18 100644 --- a/arch/arm/mach-imx/epit.c +++ b/arch/arm/mach-imx/epit.c @@ -178,7 +178,6 @@ static struct irqaction epit_timer_irq = { static struct clock_event_device clockevent_epit = { .name = "epit", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .set_mode = epit_set_mode, .set_next_event = epit_set_next_event, .rating = 200, @@ -186,18 +185,10 @@ static struct clock_event_device clockevent_epit = { static int __init epit_clockevent_init(struct clk *timer_clk) { - unsigned int c = clk_get_rate(timer_clk); - - clockevent_epit.mult = div_sc(c, NSEC_PER_SEC, - clockevent_epit.shift); - clockevent_epit.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_epit); - clockevent_epit.min_delta_ns = - clockevent_delta2ns(0x800, &clockevent_epit); - clockevent_epit.cpumask = cpumask_of(0); - - clockevents_register_device(&clockevent_epit); + clockevents_config_and_register(&clockevent_epit, + clk_get_rate(timer_clk), + 0x800, 0xfffffffe); return 0; } diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index ff24920..a96ccc7 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -101,11 +101,16 @@ static void imx_gpc_irq_mask(struct irq_data *d) void __init imx_gpc_init(void) { struct device_node *np; + int i; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); gpc_base = of_iomap(np, 0); WARN_ON(!gpc_base); + /* Initially mask all interrupts */ + for (i = 0; i < IMR_NUM; i++) + writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); + /* Register GPC as the secondary interrupt controller behind GIC */ gic_arch_extn.irq_mask = imx_gpc_irq_mask; gic_arch_extn.irq_unmask = imx_gpc_irq_unmask; diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h index 3ce7fa3..911e9b3 100644 --- a/arch/arm/mach-imx/hardware.h +++ b/arch/arm/mach-imx/hardware.h @@ -72,11 +72,6 @@ * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 - * mx50: - * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 - * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 - * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 - * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 * mx51: * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 @@ -108,7 +103,6 @@ #include "mxc.h" #include "mx6q.h" -#include "mx50.h" #include "mx51.h" #include "mx53.h" #include "mx3x.h" diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index 7e49deb..921fc15 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -17,53 +17,6 @@ .section ".text.head", "ax" -/* - * The secondary kernel init calls v7_flush_dcache_all before it enables - * the L1; however, the L1 comes out of reset in an undefined state, so - * the clean + invalidate performed by v7_flush_dcache_all causes a bunch - * of cache lines with uninitialized data and uninitialized tags to get - * written out to memory, which does really unpleasant things to the main - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * - * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs - * to be called for both secondary cores startup and primary core resume - * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. - */ -ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) - mcr p15, 0, r5, c7, c6, 2 - bgt 2b - cmp r2, #0 - bgt 1b - dsb - isb - mov pc, lr -ENDPROC(v7_invalidate_l1) - #ifdef CONFIG_SMP ENTRY(v7_secondary_startup) bl v7_invalidate_l1 diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c index 3dec962..7bc5fe1 100644 --- a/arch/arm/mach-imx/hotplug.c +++ b/arch/arm/mach-imx/hotplug.c @@ -46,9 +46,11 @@ static inline void cpu_enter_lowpower(void) void imx_cpu_die(unsigned int cpu) { cpu_enter_lowpower(); - imx_enable_cpu(cpu, false); + cpu_do_idle(); +} - /* spin here until hardware takes it down */ - while (1) - ; +int imx_cpu_kill(unsigned int cpu) +{ + imx_enable_cpu(cpu, false); + return 1; } diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c index f9a6909..00737eb 100644 --- a/arch/arm/mach-imx/imx31-dt.c +++ b/arch/arm/mach-imx/imx31-dt.c @@ -18,24 +18,9 @@ #include "common.h" #include "mx31.h" -static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = { - OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR, - "imx21-uart.0", NULL), - OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART2_BASE_ADDR, - "imx21-uart.1", NULL), - OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART3_BASE_ADDR, - "imx21-uart.2", NULL), - OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART4_BASE_ADDR, - "imx21-uart.3", NULL), - OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART5_BASE_ADDR, - "imx21-uart.4", NULL), - { /* sentinel */ } -}; - static void __init imx31_dt_init(void) { - of_platform_populate(NULL, of_default_bus_match_table, - imx31_auxdata_lookup, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char *imx31_dt_board_compat[] __initdata = { diff --git a/arch/arm/mach-imx/iomux-mx50.h b/arch/arm/mach-imx/iomux-mx50.h deleted file mode 100644 index 00f56e0..0000000 --- a/arch/arm/mach-imx/iomux-mx50.h +++ /dev/null @@ -1,977 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef __MACH_IOMUX_MX50_H__ -#define __MACH_IOMUX_MX50_H__ - -#include "iomux-v3.h" - -#define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH) - -#define MX50_SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) - -#define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE) - -#define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) - -#define MX50_USB_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP) - -#define MX50_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH) - -#define MX50_OWIRE_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) - -#define MX50_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) - -#define MX50_CSPI_SS_PAD (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL0__GPIO_4_0 IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL0__NANDF_CLE IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, MX50_KEYPAD_CTRL) -#define MX50_PAD_KEY_ROW0__GPIO_4_1 IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW0__NANDF_ALE IOMUX_PAD(0x2D0, 0x24, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL1__GPIO_4_2 IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL1__NANDF_CE0 IOMUX_PAD(0x2D4, 0x28, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, MX50_KEYPAD_CTRL) -#define MX50_PAD_KEY_ROW1__GPIO_4_3 IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW1__NANDF_CE1 IOMUX_PAD(0x2D8, 0x2C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, MX50_KEYPAD_CTRL) -#define MX50_PAD_KEY_COL2__GPIO_4_4 IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL2__NANDF_CE2 IOMUX_PAD(0x2DC, 0x30, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, MX50_KEYPAD_CTRL) -#define MX50_PAD_KEY_ROW2__GPIO_4_5 IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW2__NANDF_CE3 IOMUX_PAD(0x2E0, 0x34, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL3__GPIO_4_6 IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_COL3__NANDF_READY IOMUX_PAD(0x2E4, 0x38, 2, 0x7b4, 0, PAD_CTL_PKE | \ - PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) -#define MX50_PAD_KEY_COL3__SDMA_EXT0 IOMUX_PAD(0x2E4, 0x38, 6, 0x7b8, 0, NO_PAD_CTRL) - -#define MX50_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, MX50_KEYPAD_CTRL) -#define MX50_PAD_KEY_ROW3__GPIO_4_7 IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_KEY_ROW3__NANDF_DQS IOMUX_PAD(0x2E8, 0x3C, 2, 0x7b0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_KEY_ROW3__SDMA_EXT1 IOMUX_PAD(0x2E8, 0x3C, 6, 0x7bc, 0, NO_PAD_CTRL) - -#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \ - MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x0, 0, MX50_UART_PAD_CTRL) - -#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \ - MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C1_SDA__GPIO_6_19 IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C1_SDA__UART2_RXD IOMUX_PAD(0x2F0, 0x44, 2, 0x7cc, 1, MX50_UART_PAD_CTRL) - -#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \ - MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \ - MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C2_SDA__GPIO_6_21 IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C2_SDA__UART2_RTS IOMUX_PAD(0x2F8, 0x4C, 2, 0x7c8, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_I2C2_SDA__PWRSTABLE IOMUX_PAD(0x2F8, 0x4C, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x50, IOMUX_CONFIG_SION, 0x0, 0, \ - MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__GPIO_6_22 IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__FEC_MDC IOMUX_PAD(0x2FC, 0x50, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_I2C3_SCL__PMIC_RDY IOMUX_PAD(0x2FC, 0x50, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 IOMUX_PAD(0x2FC, 0x50, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SCL__USBOTG_OC IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, MX50_USB_PAD_CTRL) - -#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x54, IOMUX_CONFIG_SION, 0x0, 0, \ - MX50_I2C_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__GPIO_6_23 IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__FEC_MDIO IOMUX_PAD(0x300, 0x54, 2, 0x774, 0, MX50_FEC_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__PWRFAIL_INT IOMUX_PAD(0x300, 0x54, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__ALARM_DEB IOMUX_PAD(0x300, 0x54, 4, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__GPT_CAPIN1 IOMUX_PAD(0x300, 0x54, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_I2C3_SDA__USBOTG_PWR IOMUX_PAD(0x300, 0x54, 7, 0x0, 0, \ - PAD_CTL_PKE | PAD_CTL_DSE_HIGH) - -#define MX50_PAD_PWM1__PWM1_PWMO IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM1__GPIO_6_24 IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM1__USBOTG_OC IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, MX50_USB_PAD_CTRL) -#define MX50_PAD_PWM1__GPT_CMPOUT1 IOMUX_PAD(0x304, 0x58, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PWM2__PWM2_PWMO IOMUX_PAD(0x308, 0x5C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__GPIO_6_25 IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__USBOTG_PWR IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \ - PAD_CTL_PKE | PAD_CTL_DSE_HIGH) -#define MX50_PAD_PWM2__DCDC_PWM IOMUX_PAD(0x308, 0x5C, 4, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__GPT_CMPOUT2 IOMUX_PAD(0x308, 0x5C, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_PWM2__ANY_PU_RST IOMUX_PAD(0x308, 0x5C, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_OWIRE__OWIRE IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, MX50_OWIRE_PAD_CTRL) -#define MX50_PAD_OWIRE__GPIO_6_26 IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__USBH1_OC IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, MX50_USB_PAD_CTRL) -#define MX50_PAD_OWIRE__SSI_EXT1_CLK IOMUX_PAD(0x30C, 0x60, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__EPDC_PWRIRQ IOMUX_PAD(0x30C, 0x60, 4, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_OWIRE__GPT_CMPOUT3 IOMUX_PAD(0x30C, 0x60, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPITO__EPITO IOMUX_PAD(0x310, 0x64, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__GPIO_6_27 IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__USBH1_PWR IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \ - PAD_CTL_PKE | PAD_CTL_DSE_HIGH) -#define MX50_PAD_EPITO__SSI_EXT2_CLK IOMUX_PAD(0x310, 0x64, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__TOG_EN IOMUX_PAD(0x310, 0x64, 4, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPITO__GPT_CLKIN IOMUX_PAD(0x310, 0x64, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_WDOG__WDOG IOMUX_PAD(0x314, 0x68, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_WDOG__GPIO_6_28 IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_WDOG__WDOG_RST IOMUX_PAD(0x314, 0x68, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_WDOG__XTAL32K IOMUX_PAD(0x314, 0x68, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SSI_TXFS__SSI_TXFS IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXFS__GPIO_6_0 IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SSI_TXC__SSI_TXC IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXC__GPIO_6_1 IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SSI_TXD__SSI_TXD IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXD__GPIO_6_2 IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_TXD__CSPI_RDY IOMUX_PAD(0x320, 0x74, 4, 0x6e8, 0, NO_PAD_CTRL) - -#define MX50_PAD_SSI_RXD__SSI_RXD IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXD__GPIO_6_3 IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXD__CSPI_SS3 IOMUX_PAD(0x324, 0x78, 4, 0x6f4, 0, MX50_CSPI_SS_PAD) - -#define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_SSI_RXC__AUD3_RXC IOMUX_PAD(0x32C, 0x80, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__GPIO_6_5 IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__UART5_RXD IOMUX_PAD(0x32C, 0x80, 2, 0x7e4, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_SSI_RXC__WEIM_D7 IOMUX_PAD(0x32C, 0x80, 3, 0x808, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__CSPI_SS1 IOMUX_PAD(0x32C, 0x80, 4, 0x6ec, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL) -#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL) - -#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL) - -#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x764, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x748, 0, MX50_SD_PAD_CTRL) - -#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL) - -#define MX50_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART2_RXD__GPIO_6_11 IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL) - -#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL) - -#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART2_RTS__GPIO_6_13 IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL) - -#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART3_TXD__SD2_WP IOMUX_PAD(0x350, 0xA4, 5, 0x744, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART3_TXD__WEIM_D12 IOMUX_PAD(0x350, 0xA4, 6, 0x81c, 0, NO_PAD_CTRL) - -#define MX50_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x354, 0xA8, 0, 0x7d4, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART3_RXD__GPIO_6_15 IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART3_RXD__SD1_D5 IOMUX_PAD(0x354, 0xA8, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART3_RXD__SD4_D1 IOMUX_PAD(0x354, 0xA8, 4, 0x754, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL) - -#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART4_TXD__WEIM_D14 IOMUX_PAD(0x358, 0xAC, 6, 0x824, 0, NO_PAD_CTRL) - -#define MX50_PAD_UART4_RXD__UART4_RXD IOMUX_PAD(0x35C, 0xB0, 0, 0x7dc, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART4_RXD__GPIO_6_17 IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_UART4_RXD__UART3_RTS IOMUX_PAD(0x35C, 0xB0, 2, 0x7d0, 1, MX50_UART_PAD_CTRL) -#define MX50_PAD_UART4_RXD__SD1_D7 IOMUX_PAD(0x35C, 0xB0, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART4_RXD__SD4_D3 IOMUX_PAD(0x35C, 0xB0, 4, 0x75c, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART4_RXD__SD1_LCTL IOMUX_PAD(0x35C, 0xB0, 5, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_UART4_RXD__WEIM_D15 IOMUX_PAD(0x35C, 0xB0, 6, 0x828, 0, NO_PAD_CTRL) - -#define MX50_PAD_CSPI_SCLK__CSPI_SCLK IOMUX_PAD(0x360, 0xB4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_CSPI_SCLK__GPIO_4_8 IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_CSPI_MOSI__GPIO_4_9 IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_CSPI_MISO__GPIO_4_10 IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_CSPI_SS0__GPIO_4_11 IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x370, 0xC4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12 IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY IOMUX_PAD(0x370, 0xC4, 2, 0x6e8, 1, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY IOMUX_PAD(0x370, 0xC4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__UART3_RTS IOMUX_PAD(0x370, 0xC4, 4, 0x7d0, 2, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE6 IOMUX_PAD(0x370, 0xC4, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SCLK__WEIM_D8 IOMUX_PAD(0x370, 0xC4, 7, 0x80c, 0, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x374, 0xC8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x378, 0xCC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__GPIO_4_14 IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 IOMUX_PAD(0x378, 0xCC, 2, 0x6f0, 1, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 IOMUX_PAD(0x378, 0xCC, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_MISO__UART4_RTS IOMUX_PAD(0x378, 0xCC, 4, 0x7d8, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE8 IOMUX_PAD(0x378, 0xCC, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_MISO__WEIM_D10 IOMUX_PAD(0x378, 0xCC, 7, 0x814, 0, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x37C, 0xD0, 0, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) -#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK IOMUX_PAD(0x380, 0xD4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16 IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR IOMUX_PAD(0x380, 0xD4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY IOMUX_PAD(0x380, 0xD4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__UART5_RTS IOMUX_PAD(0x380, 0xD4, 4, 0x7e0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK IOMUX_PAD(0x380, 0xD4, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__NANDF_CEN4 IOMUX_PAD(0x380, 0xD4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SCLK__WEIM_D8 IOMUX_PAD(0x380, 0xD4, 7, 0x80c, 1, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI IOMUX_PAD(0x384, 0xD8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) -#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x0, 0, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x73c, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL) - -#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 IOMUX_PAD(0x38C, 0xE0, 0, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI2_SS0__GPIO_4_19 IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS IOMUX_PAD(0x38C, 0xE0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__ECSPI1_SS3 IOMUX_PAD(0x38C, 0xE0, 3, 0x0, 0, MX50_CSPI_SS_PAD) -#define MX50_PAD_ECSPI2_SS0__UART5_RXD IOMUX_PAD(0x38C, 0xE0, 4, 0x7e4, 5, MX50_UART_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC IOMUX_PAD(0x38C, 0xE0, 5, 0x6f8, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__NANDF_CEN7 IOMUX_PAD(0x38C, 0xE0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_ECSPI2_SS0__WEIM_D11 IOMUX_PAD(0x38C, 0xE0, 7, 0x818, 1, NO_PAD_CTRL) - -#define MX50_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x390, 0xE4, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD1_CLK__GPIO_5_0 IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_CLK__CLKO IOMUX_PAD(0x390, 0xE4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x394, 0xE8, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD1_CMD__GPIO_5_1 IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_CMD__CLKO2 IOMUX_PAD(0x394, 0xE8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD1_D0__SD1_D0 IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD1_D0__GPIO_5_2 IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_D0__PLL1_BYP IOMUX_PAD(0x398, 0xEC, 7, 0x6dc, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD1_D1__SD1_D1 IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD1_D1__GPIO_5_3 IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_D1__PLL2_BYP IOMUX_PAD(0x39C, 0xF0, 7, 0x6e0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD1_D2__SD1_D2 IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD1_D2__GPIO_5_4 IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD1_D2__PLL3_BYP IOMUX_PAD(0x3A0, 0xF4, 7, 0x6e4, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD1_D3__SD1_D3 IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD1_D3__GPIO_5_5 IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x3A8, 0xFC, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_CLK__GPIO_5_6 IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CLK__MSHC_SCLK IOMUX_PAD(0x3A8, 0xFC, 2, 0x0, 0, MX50_SD_PAD_CTRL) - -#define MX50_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x3AC, 0x100, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_CMD__GPIO_5_7 IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CMD__MSHC_BS IOMUX_PAD(0x3AC, 0x100, 2, 0x0, 0, MX50_SD_PAD_CTRL) - -#define MX50_PAD_SD2_D0__SD2_D0 IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D0__GPIO_5_8 IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D0__MSHC_D0 IOMUX_PAD(0x3B0, 0x104, 2, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D0__KEY_COL4 IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D1__SD2_D1 IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D1__GPIO_5_9 IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D1__MSHC_D1 IOMUX_PAD(0x3B4, 0x108, 2, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D1__KEY_ROW4 IOMUX_PAD(0x3B4, 0x108, 3, 0x7a0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D2__SD2_D2 IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D2__GPIO_5_10 IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D2__MSHC_D2 IOMUX_PAD(0x3B8, 0x10C, 2, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D2__KEY_COL5 IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D3__SD2_D3 IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D3__GPIO_5_11 IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D3__MSHC_D3 IOMUX_PAD(0x3BC, 0x110, 2, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D3__KEY_ROW5 IOMUX_PAD(0x3BC, 0x110, 3, 0x7a4, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D4__SD2_D4 IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D4__GPIO_5_12 IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D4__AUD4_RXFS IOMUX_PAD(0x3C0, 0x114, 2, 0x6d0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D4__KEY_COL6 IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D4__WEIM_D0 IOMUX_PAD(0x3C0, 0x114, 4, 0x7ec, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D4__CCM_OUT0 IOMUX_PAD(0x3C0, 0x114, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D5__SD2_D5 IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D5__GPIO_5_13 IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D5__AUD4_RXC IOMUX_PAD(0x3C4, 0x118, 2, 0x6cc, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D5__KEY_ROW6 IOMUX_PAD(0x3C4, 0x118, 3, 0x7a8, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D5__WEIM_D1 IOMUX_PAD(0x3C4, 0x118, 4, 0x7f0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D5__CCM_OUT1 IOMUX_PAD(0x3C4, 0x118, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D6__SD2_D6 IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D6__GPIO_5_14 IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D6__AUD4_RXD IOMUX_PAD(0x3C8, 0x11C, 2, 0x6c4, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D6__KEY_COL7 IOMUX_PAD(0x3C8, 0x11C, 3, 0x79c, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D6__WEIM_D2 IOMUX_PAD(0x3C8, 0x11C, 4, 0x7f4, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D6__CCM_OUT2 IOMUX_PAD(0x3C8, 0x11C, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_D7__SD2_D7 IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_D7__GPIO_5_15 IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D7__AUD4_TXFS IOMUX_PAD(0x3CC, 0x120, 2, 0x6d8, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D7__KEY_ROW7 IOMUX_PAD(0x3CC, 0x120, 3, 0x7ac, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D7__WEIM_D3 IOMUX_PAD(0x3CC, 0x120, 4, 0x7f8, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_D7__CCM_STOP IOMUX_PAD(0x3CC, 0x120, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_WP__SD2_WP IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_WP__GPIO_5_16 IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_WP__AUD4_TXD IOMUX_PAD(0x3D0, 0x124, 2, 0x6c8, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_WP__WEIM_D4 IOMUX_PAD(0x3D0, 0x124, 4, 0x7fc, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_WP__CCM_WAIT IOMUX_PAD(0x3D0, 0x124, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD2_CD__SD2_CD IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD2_CD__GPIO_5_17 IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CD__AUD4_TXC IOMUX_PAD(0x3D4, 0x128, 2, 0x6d4, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CD__WEIM_D5 IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL) -#define MX50_PAD_SD2_CD__CCM_REF_EN IOMUX_PAD(0x3D4, 0x128, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x3D8, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x3DC, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B IOMUX_PAD(0x3E0, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1 IOMUX_PAD(0x3E4, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B IOMUX_PAD(0x3E8, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0 IOMUX_PAD(0x3EC, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS IOMUX_PAD(0x3F4, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD IOMUX_PAD(0x3F8, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB IOMUX_PAD(0x3FC, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI IOMUX_PAD(0x400, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK IOMUX_PAD(0x404, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO IOMUX_PAD(0x408, 0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D0__DISP_D0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D0__GPIO_2_0 IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D0__FEC_TXCLK IOMUX_PAD(0x40C, 0x12C, 2, 0x78c, 0, PAD_CTL_HYS | PAD_CTL_PKE) - -#define MX50_PAD_DISP_D1__DISP_D1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D1__GPIO_2_1 IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D1__FEC_RX_ER IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, PAD_CTL_HYS | PAD_CTL_PKE) -#define MX50_PAD_DISP_D1__WEIM_A17 IOMUX_PAD(0x410, 0x130, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D2__DISP_D2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D2__GPIO_2_2 IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, PAD_CTL_HYS | PAD_CTL_PKE) -#define MX50_PAD_DISP_D2__WEIM_A18 IOMUX_PAD(0x414, 0x134, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D3__DISP_D3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D3__GPIO_2_3 IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D3__FEC_RXD1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, PAD_CTL_HYS | PAD_CTL_PKE) -#define MX50_PAD_DISP_D3__WEIM_A19 IOMUX_PAD(0x418, 0x138, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D3__FEC_COL IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D4__DISP_D4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D4__GPIO_2_4 IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D4__FEC_RXD0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, PAD_CTL_HYS | PAD_CTL_PKE) -#define MX50_PAD_DISP_D4__WEIM_A20 IOMUX_PAD(0x41C, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D5__DISP_D5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D5__GPIO_2_5 IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_DISP_D5__WEIM_A21 IOMUX_PAD(0x420, 0x140, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D6__DISP_D6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D6__GPIO_2_6 IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D6__FEC_TXD1 IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_DISP_D6__WEIM_A22 IOMUX_PAD(0x424, 0x144, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D6__FEC_RX_CLK IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D7__DISP_D7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D7__GPIO_2_7 IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D7__FEC_TXD0 IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_DISP_D7__WEIM_A23 IOMUX_PAD(0x428, 0x148, 3, 0x0, 0, NO_PAD_CTRL) - - -#define MX50_PAD_DISP_WR__ELCDIF_WR IOMUX_PAD(0x42C, 0x14C, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_WR__GPIO_2_16 IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_WR__WEIM_A24 IOMUX_PAD(0x42C, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_RD__ELCDIF_RD IOMUX_PAD(0x430, 0x150, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_RD__GPIO_2_19 IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_CS__ELCDIF_CS IOMUX_PAD(0x438, 0x158, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_CS__GPIO_2_21 IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x6f8, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_CS__WEIM_A27 IOMUX_PAD(0x438, 0x158, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_CS__WEIM_CS3 IOMUX_PAD(0x438, 0x158, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_BUSY__GPIO_2_18 IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_BUSY__WEIM_CS3 IOMUX_PAD(0x43C, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_RESET__ELCDIF_RST IOMUX_PAD(0x440, 0x160, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_RESET__GPIO_2_20 IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_RESET__WEIM_CS3 IOMUX_PAD(0x440, 0x160, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_CMD__SD3_CMD IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_CMD__GPIO_5_18 IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_CMD__NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_CMD__SSP_CMD IOMUX_PAD(0x444, 0x164, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_CLK__SD3_CLK IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_CLK__GPIO_5_19 IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_CLK__NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_CLK__SSP_CLK IOMUX_PAD(0x448, 0x168, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D0__SD3_D0 IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D0__GPIO_5_20 IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D0__NANDF_D4 IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D0__SSP_D0 IOMUX_PAD(0x44C, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D0__PLL1_BYP IOMUX_PAD(0x44C, 0x16C, 7, 0x6dc, 1, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D1__SD3_D1 IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D1__GPIO_5_21 IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D1__NANDF_D5 IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D1__PLL2_BYP IOMUX_PAD(0x450, 0x170, 7, 0x6e0, 1, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D2__SD3_D2 IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D2__GPIO_5_22 IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D2__NANDF_D6 IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D2__SSP_D2 IOMUX_PAD(0x454, 0x174, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_D2__PLL3_BYP IOMUX_PAD(0x454, 0x174, 7, 0x6e4, 1, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D3__SD3_D3 IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D3__GPIO_5_23 IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D3__NANDF_D7 IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D3__SSP_D3 IOMUX_PAD(0x458, 0x178, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D4__SD3_D4 IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D4__GPIO_5_24 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D4__NANDF_D0 IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D4__SSP_D4 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D5__SD3_D5 IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D5__GPIO_5_25 IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D5__NANDF_D1 IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D5__SSP_D5 IOMUX_PAD(0x460, 0x180, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D6__SD3_D6 IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D6__GPIO_5_26 IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D6__NANDF_D2 IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D6__SSP_D6 IOMUX_PAD(0x464, 0x184, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_D7__SD3_D7 IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_D7__GPIO_5_27 IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_D7__NANDF_D3 IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_D7__SSP_D7 IOMUX_PAD(0x468, 0x188, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_SD3_WP__SD3_WP IOMUX_PAD(0x46C, 0x18C, 0, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_WP__GPIO_5_28 IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_SD3_WP__NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_SD3_WP__SSP_CD IOMUX_PAD(0x46C, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_SD3_WP__SD4_LCTL IOMUX_PAD(0x46C, 0x18C, 4, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_SD3_WP__WEIM_CS3 IOMUX_PAD(0x46C, 0x18C, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D8__DISP_D8 IOMUX_PAD(0x470, 0x190, 0, 0x71c, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D8__GPIO_2_8 IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D8__NANDF_CLE IOMUX_PAD(0x470, 0x190, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D8__SD1_LCTL IOMUX_PAD(0x470, 0x190, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D8__SD4_CMD IOMUX_PAD(0x470, 0x190, 4, 0x74c, 2, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D8__KEY_COL4 IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D8__FEC_TX_CLK IOMUX_PAD(0x470, 0x190, 6, 0x78c, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D9__DISP_D9 IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D9__GPIO_2_9 IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D9__NANDF_ALE IOMUX_PAD(0x474, 0x194, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D9__SD2_LCTL IOMUX_PAD(0x474, 0x194, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D9__SD4_CLK IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D9__KEY_ROW4 IOMUX_PAD(0x474, 0x194, 5, 0x7a0, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D9__FEC_RX_ER IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D10__DISP_D10 IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D10__GPIO_2_10 IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D10__NANDF_CEN0 IOMUX_PAD(0x478, 0x198, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D10__SD3_LCTL IOMUX_PAD(0x478, 0x198, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D10__SD4_D0 IOMUX_PAD(0x478, 0x198, 4, 0x750, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D10__KEY_COL5 IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D10__FEC_RX_DV IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D11__DISP_D11 IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D11__GPIO_2_11 IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D11__NANDF_CEN1 IOMUX_PAD(0x47C, 0x19C, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D11__SD4_D1 IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D11__KEY_ROW5 IOMUX_PAD(0x47C, 0x19C, 5, 0x7a4, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D11__FEC_RDAT1 IOMUX_PAD(0x47C, 0x19C, 6, 0x77c, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D12__DISP_D12 IOMUX_PAD(0x480, 0x1A0, 0, 0x72c, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D12__GPIO_2_12 IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D12__NANDF_CEN2 IOMUX_PAD(0x480, 0x1A0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D12__SD1_CD IOMUX_PAD(0x480, 0x1A0, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D12__SD4_D2 IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D12__KEY_COL6 IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D12__FEC_RDAT0 IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D13__DISP_D13 IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D13__GPIO_2_13 IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D13__NANDF_CEN3 IOMUX_PAD(0x484, 0x1A4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D13__SD3_CD IOMUX_PAD(0x484, 0x1A4, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D13__SD4_D3 IOMUX_PAD(0x484, 0x1A4, 4, 0x75c, 1, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D13__KEY_ROW6 IOMUX_PAD(0x484, 0x1A4, 5, 0x7a8, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D13__FEC_TX_EN IOMUX_PAD(0x484, 0x1A4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D14__DISP_D14 IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D14__GPIO_2_14 IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D14__NANDF_RDY0 IOMUX_PAD(0x488, 0x1A8, 2, 0x7b4, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D14__SD1_WP IOMUX_PAD(0x488, 0x1A8, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D14__SD4_WP IOMUX_PAD(0x488, 0x1A8, 4, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D14__KEY_COL7 IOMUX_PAD(0x488, 0x1A8, 5, 0x79c, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D14__FEC_TDAT1 IOMUX_PAD(0x488, 0x1A8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_DISP_D15__DISP_D15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_DISP_D15__GPIO_2_15 IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_DISP_D15__NANDF_DQS IOMUX_PAD(0x48C, 0x1AC, 2, 0x7b0, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D15__SD3_RST IOMUX_PAD(0x48C, 0x1AC, 3, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D15__SD4_CD IOMUX_PAD(0x48C, 0x1AC, 4, 0x0, 0, MX50_SD_PAD_CTRL) -#define MX50_PAD_DISP_D15__KEY_ROW7 IOMUX_PAD(0x48C, 0x1AC, 5, 0x7ac, 1, NO_PAD_CTRL) -#define MX50_PAD_DISP_D15__FEC_TDAT0 IOMUX_PAD(0x48C, 0x1AC, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D0__EPDC_D0 IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D0__GPIO_3_0 IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D0__WEIM_D0 IOMUX_PAD(0x54C, 0x1B0, 2, 0x7ec, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D0__ELCDIF_RS IOMUX_PAD(0x54C, 0x1B0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_D0__ELCDIF_PIXCLK IOMUX_PAD(0x54C, 0x1B0, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D1__EPDC_D1 IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D1__GPIO_3_1 IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D1__WEIM_D1 IOMUX_PAD(0x550, 0x1B4, 2, 0x7f0, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D1__ELCDIF_CS IOMUX_PAD(0x550, 0x1B4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_D1__ELCDIF_EN IOMUX_PAD(0x550, 0x1B4, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D2__EPDC_D2 IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D2__GPIO_3_2 IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D2__WEIM_D2 IOMUX_PAD(0x554, 0x1B8, 2, 0x7f4, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D2__ELCDIF_WR IOMUX_PAD(0x554, 0x1B8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC IOMUX_PAD(0x554, 0x1B8, 4, 0x73c, 2, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D3__EPDC_D3 IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D3__GPIO_3_3 IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D3__WEIM_D3 IOMUX_PAD(0x558, 0x1BC, 2, 0x7f8, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D3__ELCDIF_RD IOMUX_PAD(0x558, 0x1BC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC IOMUX_PAD(0x558, 0x1BC, 4, 0x6f8, 3, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D4__EPDC_D4 IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D4__GPIO_3_4 IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D4__WEIM_D4 IOMUX_PAD(0x55C, 0x1C0, 2, 0x7fc, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D5__EPDC_D5 IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D5__GPIO_3_5 IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D5__WEIM_D5 IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D6__EPDC_D6 IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D6__GPIO_3_6 IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D6__WEIM_D6 IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D7__EPDC_D7 IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D7__GPIO_3_7 IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D7__WEIM_D7 IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D8__EPDC_D8 IOMUX_PAD(0x56C, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D8__GPIO_3_8 IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D8__WEIM_D8 IOMUX_PAD(0x56C, 0x1D0, 2, 0x80c, 2, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D8__ELCDIF_D24 IOMUX_PAD(0x56C, 0x1D0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D10__WEIM_D10 IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D10__ELCDIF_D26 IOMUX_PAD(0x574, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D11__EPDC_D11 IOMUX_PAD(0x578, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D11__GPIO_3_11 IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D11__WEIM_D11 IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D11__ELCDIF_D27 IOMUX_PAD(0x578, 0x1DC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D12__EPDC_D12 IOMUX_PAD(0x57C, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D12__GPIO_3_12 IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D12__WEIM_D12 IOMUX_PAD(0x57C, 0x1E0, 2, 0x81c, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D12__ELCDIF_D28 IOMUX_PAD(0x57C, 0x1E0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D13__EPDC_D13 IOMUX_PAD(0x580, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D13__GPIO_3_13 IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D13__WEIM_D13 IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D13__ELCDIF_D29 IOMUX_PAD(0x580, 0x1E4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_D14__EPDC_D14 IOMUX_PAD(0x584, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D14__GPIO_3_14 IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D14__WEIM_D14 IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D14__ELCDIF_D30 IOMUX_PAD(0x584, 0x1E8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_D14__AUD6_TXD IOMUX_PAD(0x584, 0x1E8, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_D15__EPDC_D15 IOMUX_PAD(0x588, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D15__GPIO_3_15 IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D15__WEIM_D15 IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_D15__ELCDIF_D31 IOMUX_PAD(0x588, 0x1EC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_D15__AUD6_TXC IOMUX_PAD(0x588, 0x1EC, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__GPIO_3_16 IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__WEIM_D16 IOMUX_PAD(0x58C, 0x1F0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__ELCDIF_D16 IOMUX_PAD(0x58C, 0x1F0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_GDCLK__AUD6_TXFS IOMUX_PAD(0x58C, 0x1F0, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__GPIO_3_17 IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__WEIM_D17 IOMUX_PAD(0x590, 0x1F4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__ELCDIF_D17 IOMUX_PAD(0x590, 0x1F4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_GDSP__AUD6_RXD IOMUX_PAD(0x590, 0x1F4, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__GPIO_3_18 IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__WEIM_D18 IOMUX_PAD(0x594, 0x1F8, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__ELCDIF_D18 IOMUX_PAD(0x594, 0x1F8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_GDOE__AUD6_RXC IOMUX_PAD(0x594, 0x1F8, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__GPIO_3_19 IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__WEIM_D19 IOMUX_PAD(0x598, 0x1FC, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__ELCDIF_D19 IOMUX_PAD(0x598, 0x1FC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_GDRL__AUD6_RXFS IOMUX_PAD(0x598, 0x1FC, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__GPIO_3_20 IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__WEIM_D20 IOMUX_PAD(0x59C, 0x200, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__ELCDIF_D20 IOMUX_PAD(0x59C, 0x200, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLK__AUD5_TXD IOMUX_PAD(0x59C, 0x200, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDOEZ__EPDC_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21 IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__WEIM_D21 IOMUX_PAD(0x5A0, 0x204, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__ELCDIF_D21 IOMUX_PAD(0x5A0, 0x204, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDOEZ__AUD5_TXC IOMUX_PAD(0x5A0, 0x204, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDOED__EPDC_SDOED IOMUX_PAD(0x5A4, 0x208, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__GPIO_3_22 IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__WEIM_D22 IOMUX_PAD(0x5A4, 0x208, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__ELCDIF_D22 IOMUX_PAD(0x5A4, 0x208, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDOED__AUD5_TXFS IOMUX_PAD(0x5A4, 0x208, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__GPIO_3_23 IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__WEIM_D23 IOMUX_PAD(0x5A8, 0x20C, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__ELCDIF_D23 IOMUX_PAD(0x5A8, 0x20C, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDOE__AUD5_RXD IOMUX_PAD(0x5A8, 0x20C, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__GPIO_3_24 IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__WEIM_D24 IOMUX_PAD(0x5AC, 0x210, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__ELCDIF_D8 IOMUX_PAD(0x5AC, 0x210, 3, 0x71c, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDLE__AUD5_RXC IOMUX_PAD(0x5AC, 0x210, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCLKN__EPDC_SDCLKN IOMUX_PAD(0x5B0, 0x214, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25 IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__WEIM_D25 IOMUX_PAD(0x5B0, 0x214, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__ELCDIF_D9 IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDCLKN__AUD5_RXFS IOMUX_PAD(0x5B0, 0x214, 4, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__GPIO_3_26 IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__WEIM_D26 IOMUX_PAD(0x5B4, 0x218, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__ELCDIF_D10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_SDSHR__AUD4_TXD IOMUX_PAD(0x5B4, 0x218, 4, 0x6c8, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_PWRCOM__EPDC_PWRCOM IOMUX_PAD(0x5B8, 0x21C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27 IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__WEIM_D27 IOMUX_PAD(0x5B8, 0x21C, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__ELCDIF_D11 IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCOM__AUD4_TXC IOMUX_PAD(0x5B8, 0x21C, 4, 0x6d4, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT IOMUX_PAD(0x5BC, 0x220, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28 IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__WEIM_D28 IOMUX_PAD(0x5BC, 0x220, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_D12 IOMUX_PAD(0x5BC, 0x220, 3, 0x72c, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_PWRSTAT__AUD4_TXFS IOMUX_PAD(0x5BC, 0x220, 4, 0x6d8, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL0 IOMUX_PAD(0x5C0, 0x224, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29 IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__WEIM_D29 IOMUX_PAD(0x5C0, 0x224, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_D13 IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL0__AUD4_RXD IOMUX_PAD(0x5C0, 0x224, 4, 0x6c4, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL1 IOMUX_PAD(0x5C4, 0x228, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30 IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__WEIM_D30 IOMUX_PAD(0x5C4, 0x228, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_D14 IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL1__AUD4_RXC IOMUX_PAD(0x5C4, 0x228, 4, 0x6cc, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL2 IOMUX_PAD(0x5C8, 0x22C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31 IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__WEIM_D31 IOMUX_PAD(0x5C8, 0x22C, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_D15 IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, MX50_ELCDIF_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__AUD4_RXFS IOMUX_PAD(0x5C8, 0x22C, 4, 0x6d0, 1, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT0 IOMUX_PAD(0x5C8, 0x22C, 6, 0x7b8, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_PWRCTRL3__PWRCTRL3 IOMUX_PAD(0x5CC, 0x230, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20 IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL3__WEIM_EB2 IOMUX_PAD(0x5CC, 0x230, 2, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT1 IOMUX_PAD(0x5CC, 0x230, 6, 0x7bc, 1, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_VCOM0__EPDC_VCOM0 IOMUX_PAD(0x5D0, 0x234, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM0__GPIO_4_21 IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM0__WEIM_EB3 IOMUX_PAD(0x5D0, 0x234, 2, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_VCOM1__EPDC_VCOM1 IOMUX_PAD(0x5D4, 0x238, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM1__GPIO_4_22 IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_VCOM1__WEIM_CS3 IOMUX_PAD(0x5D4, 0x238, 2, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EPDC_BDR0__EPDC_BDR0 IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR0__GPIO_4_23 IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR0__ELCDIF_D7 IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_BDR1__EPDC_BDR1 IOMUX_PAD(0x5DC, 0x240, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR1__GPIO_4_24 IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_BDR1__ELCDIF_D6 IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE0__GPIO_4_25 IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE0__ELCDIF_D5 IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE1__GPIO_4_26 IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE1__ELCDIF_D4 IOMUX_PAD(0x5E4, 0x248, 2, 0x70c, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2 IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE2__GPIO_4_27 IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT3 IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCE3__EPDC_SDCE3 IOMUX_PAD(0x5EC, 0x250, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE3__GPIO_4_28 IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE3__ELCDIF_D2 IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCE4__EPDC_SDCE4 IOMUX_PAD(0x5F0, 0x254, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE4__GPIO_4_29 IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE4__ELCDIF_D1 IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EPDC_SDCE5__EPDC_SDCE5 IOMUX_PAD(0x5F4, 0x258, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE5__GPIO_4_30 IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EPDC_SDCE5__ELCDIF_D0 IOMUX_PAD(0x5F4, 0x258, 3, 0x6fc, 1, MX50_ELCDIF_PAD_CTRL) - -#define MX50_PAD_EIM_DA0__WEIM_A0 IOMUX_PAD(0x5F8, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA0__GPIO_1_0 IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA0__KEY_COL4 IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA1__WEIM_A1 IOMUX_PAD(0x5FC, 0x260, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA1__GPIO_1_1 IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA1__KEY_ROW4 IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, MX50_KEYPAD_CTRL) - -#define MX50_PAD_EIM_DA2__WEIM_A2 IOMUX_PAD(0x600, 0x264, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA2__GPIO_1_2 IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA2__KEY_COL5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA3__WEIM_A3 IOMUX_PAD(0x604, 0x268, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA3__GPIO_1_3 IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA3__KEY_ROW5 IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, MX50_KEYPAD_CTRL) - -#define MX50_PAD_EIM_DA4__WEIM_A4 IOMUX_PAD(0x608, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA4__GPIO_1_4 IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA4__KEY_COL6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA5__WEIM_A5 IOMUX_PAD(0x60C, 0x270, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA5__GPIO_1_5 IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA5__KEY_ROW6 IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, MX50_KEYPAD_CTRL) - -#define MX50_PAD_EIM_DA6__WEIM_A6 IOMUX_PAD(0x610, 0x274, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA6__GPIO_1_6 IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA6__KEY_COL7 IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA7__WEIM_A7 IOMUX_PAD(0x614, 0x278, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA7__GPIO_1_7 IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA7__KEY_ROW7 IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, MX50_KEYPAD_CTRL) - -#define MX50_PAD_EIM_DA8__WEIM_A8 IOMUX_PAD(0x618, 0x27C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA8__GPIO_1_8 IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA8__NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_EIM_DA9__WEIM_A9 IOMUX_PAD(0x61C, 0x280, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA9__GPIO_1_9 IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA9__NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_EIM_DA10__WEIM_A10 IOMUX_PAD(0x620, 0x284, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA10__GPIO_1_10 IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA10__NANDF_CE0 IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_EIM_DA11__WEIM_A11 IOMUX_PAD(0x624, 0x288, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA11__GPIO_1_11 IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA11__NANDF_CE1 IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, PAD_CTL_DSE_HIGH) - -#define MX50_PAD_EIM_DA12__WEIM_A12 IOMUX_PAD(0x628, 0x28C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA12__GPIO_1_12 IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA12__NANDF_CE2 IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PAD_EIM_DA12__EPDC_SDCE6 IOMUX_PAD(0x628, 0x28C, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA13__WEIM_A13 IOMUX_PAD(0x62C, 0x290, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA13__GPIO_1_13 IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA13__NANDF_CE3 IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, PAD_CTL_DSE_HIGH) -#define MX50_PIN_EIM_DA13__EPDC_SDCE7 IOMUX_PAD(0x62C, 0x290, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA14__WEIM_A14 IOMUX_PAD(0x630, 0x294, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA14__GPIO_1_14 IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA14__NANDF_READY IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, PAD_CTL_PKE | \ - PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) -#define MX50_PAD_EIM_DA14__EPDC_SDCE8 IOMUX_PAD(0x630, 0x294, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_DA15__WEIM_A15 IOMUX_PAD(0x634, 0x298, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_DA15__GPIO_1_15 IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PIN_EIM_DA15__NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, PAD_CTL_DSE_HIGH) -#define MX50_PAD_EIM_DA15__EPDC_SDCE9 IOMUX_PAD(0x634, 0x298, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_CS2__WEIM_CS2 IOMUX_PAD(0x638, 0x29C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS2__GPIO_1_16 IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS2__WEIM_A27 IOMUX_PAD(0x638, 0x29C, 2, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_CS1__WEIM_CS1 IOMUX_PAD(0x63C, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS1__GPIO_1_17 IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_CS0__WEIM_CS0 IOMUX_PAD(0x640, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CS0__GPIO_1_18 IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_EB0__WEIM_EB0 IOMUX_PAD(0x644, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_EB0__GPIO_1_19 IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_EB1__WEIM_EB1 IOMUX_PAD(0x648, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_EB1__GPIO_1_20 IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_WAIT__WEIM_WAIT IOMUX_PAD(0x64C, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_WAIT__GPIO_1_21 IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_BCLK__WEIM_BCLK IOMUX_PAD(0x650, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_BCLK__GPIO_1_22 IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_RDY__WEIM_RDY IOMUX_PAD(0x654, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_RDY__GPIO_1_23 IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_OE__WEIM_OE IOMUX_PAD(0x658, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_OE__GPIO_1_24 IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_RW__WEIM_RW IOMUX_PAD(0x65C, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_RW__GPIO_1_25 IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_LBA__WEIM_LBA IOMUX_PAD(0x660, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_LBA__GPIO_1_26 IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX50_PAD_EIM_CRE__WEIM_CRE IOMUX_PAD(0x664, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX50_PAD_EIM_CRE__GPIO_1_27 IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL) - -#endif /* __MACH_IOMUX_MX50_H__ */ diff --git a/arch/arm/mach-imx/iram.h b/arch/arm/mach-imx/iram.h deleted file mode 100644 index 022690c..0000000 --- a/arch/arm/mach-imx/iram.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#include <linux/errno.h> - -#ifdef CONFIG_IRAM_ALLOC - -int __init iram_init(unsigned long base, unsigned long size); -void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr); -void iram_free(unsigned long dma_addr, unsigned int size); - -#else - -static inline int __init iram_init(unsigned long base, unsigned long size) -{ - return -ENOMEM; -} - -static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr) -{ - return NULL; -} - -static inline void iram_free(unsigned long base, unsigned long size) {} - -#endif diff --git a/arch/arm/mach-imx/iram_alloc.c b/arch/arm/mach-imx/iram_alloc.c index 6c80424..e05cf40 100644 --- a/arch/arm/mach-imx/iram_alloc.c +++ b/arch/arm/mach-imx/iram_alloc.c @@ -22,8 +22,7 @@ #include <linux/module.h> #include <linux/spinlock.h> #include <linux/genalloc.h> - -#include "iram.h" +#include "linux/platform_data/imx-iram.h" static unsigned long iram_phys_base; static void __iomem *iram_virt_base; diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c deleted file mode 100644 index 2fdc9bf..0000000 --- a/arch/arm/mach-imx/lluart.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <asm/page.h> -#include <asm/sizes.h> -#include <asm/mach/map.h> - -#include "hardware.h" - -#define IMX6Q_UART1_BASE_ADDR 0x02020000 -#define IMX6Q_UART2_BASE_ADDR 0x021e8000 -#define IMX6Q_UART3_BASE_ADDR 0x021ec000 -#define IMX6Q_UART4_BASE_ADDR 0x021f0000 -#define IMX6Q_UART5_BASE_ADDR 0x021f4000 - -/* - * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion - * of IMX6Q_UART##n##_BASE_ADDR. - */ -#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR -#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) -#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT) - -static struct map_desc imx_lluart_desc = { -#ifdef CONFIG_DEBUG_IMX6Q_UART - .virtual = IMX_IO_P2V(IMX6Q_DEBUG_UART_BASE), - .pfn = __phys_to_pfn(IMX6Q_DEBUG_UART_BASE), - .length = 0x4000, - .type = MT_DEVICE, -#endif -}; - -void __init imx_lluart_map_io(void) -{ - if (imx_lluart_desc.virtual) - iotable_init(&imx_lluart_desc, 1); -} diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 8d3d06e..1786b2d 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -12,7 +12,6 @@ #include <linux/clk.h> #include <linux/clkdev.h> -#include <linux/cpuidle.h> #include <linux/delay.h> #include <linux/export.h> #include <linux/init.h> @@ -27,10 +26,10 @@ #include <linux/regmap.h> #include <linux/micrel_phy.h> #include <linux/mfd/syscon.h> -#include <asm/cpuidle.h> #include <asm/smp_twd.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> +#include <asm/mach/map.h> #include <asm/mach/time.h> #include <asm/system_misc.h> @@ -201,24 +200,20 @@ static void __init imx6q_init_machine(void) imx6q_1588_init(); } -static struct cpuidle_driver imx6q_cpuidle_driver = { - .name = "imx6q_cpuidle", - .owner = THIS_MODULE, - .en_core_tk_irqen = 1, - .states[0] = ARM_CPUIDLE_WFI_STATE, - .state_count = 1, -}; - static void __init imx6q_init_late(void) { - imx_cpuidle_init(&imx6q_cpuidle_driver); + /* + * WAIT mode is broken on TO 1.0 and 1.1, so there is no point + * to run cpuidle on them. + */ + if (imx6q_revision() > IMX_CHIP_REVISION_1_1) + imx6q_cpuidle_init(); } static void __init imx6q_map_io(void) { - imx_lluart_map_io(); + debug_ll_io_init(); imx_scu_map_io(); - imx6q_clock_map_io(); } static void __init imx6q_init_irq(void) diff --git a/arch/arm/mach-imx/mach-mx50_rdp.c b/arch/arm/mach-imx/mach-mx50_rdp.c deleted file mode 100644 index 8937902..0000000 --- a/arch/arm/mach-imx/mach-mx50_rdp.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "devices-imx50.h" -#include "hardware.h" -#include "iomux-mx50.h" - -#define FEC_EN IMX_GPIO_NR(6, 23) -#define FEC_RESET_B IMX_GPIO_NR(4, 12) - -static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = { - /* SD1 */ - MX50_PAD_ECSPI2_SS0__GPIO_4_19, - MX50_PAD_EIM_CRE__GPIO_1_27, - MX50_PAD_SD1_CMD__SD1_CMD, - - MX50_PAD_SD1_CLK__SD1_CLK, - MX50_PAD_SD1_D0__SD1_D0, - MX50_PAD_SD1_D1__SD1_D1, - MX50_PAD_SD1_D2__SD1_D2, - MX50_PAD_SD1_D3__SD1_D3, - - /* SD2 */ - MX50_PAD_SD2_CD__GPIO_5_17, - MX50_PAD_SD2_WP__GPIO_5_16, - MX50_PAD_SD2_CMD__SD2_CMD, - MX50_PAD_SD2_CLK__SD2_CLK, - MX50_PAD_SD2_D0__SD2_D0, - MX50_PAD_SD2_D1__SD2_D1, - MX50_PAD_SD2_D2__SD2_D2, - MX50_PAD_SD2_D3__SD2_D3, - MX50_PAD_SD2_D4__SD2_D4, - MX50_PAD_SD2_D5__SD2_D5, - MX50_PAD_SD2_D6__SD2_D6, - MX50_PAD_SD2_D7__SD2_D7, - - /* SD3 */ - MX50_PAD_SD3_CMD__SD3_CMD, - MX50_PAD_SD3_CLK__SD3_CLK, - MX50_PAD_SD3_D0__SD3_D0, - MX50_PAD_SD3_D1__SD3_D1, - MX50_PAD_SD3_D2__SD3_D2, - MX50_PAD_SD3_D3__SD3_D3, - MX50_PAD_SD3_D4__SD3_D4, - MX50_PAD_SD3_D5__SD3_D5, - MX50_PAD_SD3_D6__SD3_D6, - MX50_PAD_SD3_D7__SD3_D7, - - /* PWR_INT */ - MX50_PAD_ECSPI2_MISO__GPIO_4_18, - - /* UART pad setting */ - MX50_PAD_UART1_TXD__UART1_TXD, - MX50_PAD_UART1_RXD__UART1_RXD, - MX50_PAD_UART1_RTS__UART1_RTS, - MX50_PAD_UART2_TXD__UART2_TXD, - MX50_PAD_UART2_RXD__UART2_RXD, - MX50_PAD_UART2_CTS__UART2_CTS, - MX50_PAD_UART2_RTS__UART2_RTS, - - MX50_PAD_I2C1_SCL__I2C1_SCL, - MX50_PAD_I2C1_SDA__I2C1_SDA, - MX50_PAD_I2C2_SCL__I2C2_SCL, - MX50_PAD_I2C2_SDA__I2C2_SDA, - - MX50_PAD_EPITO__USBH1_PWR, - /* Need to comment below line if - * one needs to debug owire. - */ - MX50_PAD_OWIRE__USBH1_OC, - /* using gpio to control otg pwr */ - MX50_PAD_PWM2__GPIO_6_25, - MX50_PAD_I2C3_SCL__USBOTG_OC, - - MX50_PAD_SSI_RXC__FEC_MDIO, - MX50_PAD_SSI_RXFS__FEC_MDC, - MX50_PAD_DISP_D0__FEC_TXCLK, - MX50_PAD_DISP_D1__FEC_RX_ER, - MX50_PAD_DISP_D2__FEC_RX_DV, - MX50_PAD_DISP_D3__FEC_RXD1, - MX50_PAD_DISP_D4__FEC_RXD0, - MX50_PAD_DISP_D5__FEC_TX_EN, - MX50_PAD_DISP_D6__FEC_TXD1, - MX50_PAD_DISP_D7__FEC_TXD0, - MX50_PAD_I2C3_SDA__GPIO_6_23, - MX50_PAD_ECSPI1_SCLK__GPIO_4_12, - - MX50_PAD_CSPI_SS0__CSPI_SS0, - MX50_PAD_ECSPI1_MOSI__CSPI_SS1, - MX50_PAD_CSPI_MOSI__CSPI_MOSI, - MX50_PAD_CSPI_MISO__CSPI_MISO, - - /* SGTL500_OSC_EN */ - MX50_PAD_UART1_CTS__GPIO_6_8, - - /* SGTL_AMP_SHDN */ - MX50_PAD_UART3_RXD__GPIO_6_15, - - /* Keypad */ - MX50_PAD_KEY_COL0__KEY_COL0, - MX50_PAD_KEY_ROW0__KEY_ROW0, - MX50_PAD_KEY_COL1__KEY_COL1, - MX50_PAD_KEY_ROW1__KEY_ROW1, - MX50_PAD_KEY_COL2__KEY_COL2, - MX50_PAD_KEY_ROW2__KEY_ROW2, - MX50_PAD_KEY_COL3__KEY_COL3, - MX50_PAD_KEY_ROW3__KEY_ROW3, - MX50_PAD_EIM_DA0__KEY_COL4, - MX50_PAD_EIM_DA1__KEY_ROW4, - MX50_PAD_EIM_DA2__KEY_COL5, - MX50_PAD_EIM_DA3__KEY_ROW5, - MX50_PAD_EIM_DA4__KEY_COL6, - MX50_PAD_EIM_DA5__KEY_ROW6, - MX50_PAD_EIM_DA6__KEY_COL7, - MX50_PAD_EIM_DA7__KEY_ROW7, - /*EIM pads */ - MX50_PAD_EIM_DA8__GPIO_1_8, - MX50_PAD_EIM_DA9__GPIO_1_9, - MX50_PAD_EIM_DA10__GPIO_1_10, - MX50_PAD_EIM_DA11__GPIO_1_11, - MX50_PAD_EIM_DA12__GPIO_1_12, - MX50_PAD_EIM_DA13__GPIO_1_13, - MX50_PAD_EIM_DA14__GPIO_1_14, - MX50_PAD_EIM_DA15__GPIO_1_15, - MX50_PAD_EIM_CS2__GPIO_1_16, - MX50_PAD_EIM_CS1__GPIO_1_17, - MX50_PAD_EIM_CS0__GPIO_1_18, - MX50_PAD_EIM_EB0__GPIO_1_19, - MX50_PAD_EIM_EB1__GPIO_1_20, - MX50_PAD_EIM_WAIT__GPIO_1_21, - MX50_PAD_EIM_BCLK__GPIO_1_22, - MX50_PAD_EIM_RDY__GPIO_1_23, - MX50_PAD_EIM_OE__GPIO_1_24, -}; - -/* Serial ports */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct fec_platform_data fec_data __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static inline void mx50_rdp_fec_reset(void) -{ - gpio_request(FEC_EN, "fec-en"); - gpio_direction_output(FEC_EN, 0); - gpio_request(FEC_RESET_B, "fec-reset_b"); - gpio_direction_output(FEC_RESET_B, 0); - msleep(1); - gpio_set_value(FEC_RESET_B, 1); -} - -static const struct imxi2c_platform_data i2c_data __initconst = { - .bitrate = 100000, -}; - -/* - * Board specific initialization. - */ -static void __init mx50_rdp_board_init(void) -{ - imx50_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads, - ARRAY_SIZE(mx50_rdp_pads)); - - imx50_add_imx_uart(0, &uart_pdata); - imx50_add_imx_uart(1, &uart_pdata); - mx50_rdp_fec_reset(); - imx50_add_fec(&fec_data); - imx50_add_imx_i2c(0, &i2c_data); - imx50_add_imx_i2c(1, &i2c_data); - imx50_add_imx_i2c(2, &i2c_data); -} - -static void __init mx50_rdp_timer_init(void) -{ - mx50_clocks_init(32768, 24000000, 22579200); -} - -MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform") - .map_io = mx50_map_io, - .init_early = imx50_init_early, - .init_irq = mx50_init_irq, - .handle_irq = imx50_handle_irq, - .init_time = mx50_rdp_timer_init, - .init_machine = mx50_rdp_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c deleted file mode 100644 index 2d23651..0000000 --- a/arch/arm/mach-imx/mach-mx51_3ds.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> -#include <linux/gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "3ds_debugboard.h" -#include "common.h" -#include "devices-imx51.h" -#include "hardware.h" -#include "iomux-mx51.h" - -#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) - -static iomux_v3_cfg_t mx51_3ds_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - - /* UART2 */ - MX51_PAD_UART2_RXD__UART2_RXD, - MX51_PAD_UART2_TXD__UART2_TXD, - MX51_PAD_EIM_D25__UART2_CTS, - MX51_PAD_EIM_D26__UART2_RTS, - - /* UART3 */ - MX51_PAD_UART3_RXD__UART3_RXD, - MX51_PAD_UART3_TXD__UART3_TXD, - MX51_PAD_EIM_D24__UART3_CTS, - MX51_PAD_EIM_D27__UART3_RTS, - - /* CPLD PARENT IRQ PIN */ - MX51_PAD_GPIO1_6__GPIO1_6, - - /* KPP */ - MX51_PAD_KEY_ROW0__KEY_ROW0, - MX51_PAD_KEY_ROW1__KEY_ROW1, - MX51_PAD_KEY_ROW2__KEY_ROW2, - MX51_PAD_KEY_ROW3__KEY_ROW3, - MX51_PAD_KEY_COL0__KEY_COL0, - MX51_PAD_KEY_COL1__KEY_COL1, - MX51_PAD_KEY_COL2__KEY_COL2, - MX51_PAD_KEY_COL3__KEY_COL3, - MX51_PAD_KEY_COL4__KEY_COL4, - MX51_PAD_KEY_COL5__KEY_COL5, - - /* eCSPI2 */ - MX51_PAD_NANDF_RB2__ECSPI2_SCLK, - MX51_PAD_NANDF_RB3__ECSPI2_MISO, - MX51_PAD_NANDF_D15__ECSPI2_MOSI, - MX51_PAD_NANDF_D12__GPIO3_28, -}; - -/* Serial ports */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static int mx51_3ds_board_keymap[] = { - KEY(0, 0, KEY_1), - KEY(0, 1, KEY_2), - KEY(0, 2, KEY_3), - KEY(0, 3, KEY_F1), - KEY(0, 4, KEY_UP), - KEY(0, 5, KEY_F2), - - KEY(1, 0, KEY_4), - KEY(1, 1, KEY_5), - KEY(1, 2, KEY_6), - KEY(1, 3, KEY_LEFT), - KEY(1, 4, KEY_SELECT), - KEY(1, 5, KEY_RIGHT), - - KEY(2, 0, KEY_7), - KEY(2, 1, KEY_8), - KEY(2, 2, KEY_9), - KEY(2, 3, KEY_F3), - KEY(2, 4, KEY_DOWN), - KEY(2, 5, KEY_F4), - - KEY(3, 0, KEY_0), - KEY(3, 1, KEY_OK), - KEY(3, 2, KEY_ESC), - KEY(3, 3, KEY_ENTER), - KEY(3, 4, KEY_MENU), - KEY(3, 5, KEY_BACK) -}; - -static const struct matrix_keymap_data mx51_3ds_map_data __initconst = { - .keymap = mx51_3ds_board_keymap, - .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap), -}; - -static int mx51_3ds_spi2_cs[] = { - MXC_SPI_CS(0), - MX51_3DS_ECSPI2_CS, -}; - -static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = { - .chipselect = mx51_3ds_spi2_cs, - .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs), -}; - -static struct spi_board_info mx51_3ds_spi_nor_device[] = { - { - .modalias = "m25p80", - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 1, - .chip_select = 1, - .mode = SPI_MODE_0, - .platform_data = NULL,}, -}; - -/* - * Board specific initialization. - */ -static void __init mx51_3ds_init(void) -{ - imx51_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads, - ARRAY_SIZE(mx51_3ds_pads)); - - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_imx_uart(1, &uart_pdata); - imx51_add_imx_uart(2, &uart_pdata); - - imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata); - spi_register_board_info(mx51_3ds_spi_nor_device, - ARRAY_SIZE(mx51_3ds_spi_nor_device)); - - if (mxc_expio_init(MX51_CS5_BASE_ADDR, IMX_GPIO_NR(1, 6))) - printk(KERN_WARNING "Init of the debugboard failed, all " - "devices on the board are unusable.\n"); - - imx51_add_sdhci_esdhc_imx(0, NULL); - imx51_add_imx_keypad(&mx51_3ds_map_data); - imx51_add_imx2_wdt(0); -} - -static void __init mx51_3ds_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 0); -} - -MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .init_time = mx51_3ds_timer_init, - .init_machine = mx51_3ds_init, - .init_late = imx51_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index 79d71cf..cf34994 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -24,16 +24,6 @@ #include "iomux-v3.h" /* - * Define the MX50 memory map. - */ -static struct map_desc mx50_io_desc[] __initdata = { - imx_map_entry(MX50, TZIC, MT_DEVICE), - imx_map_entry(MX50, SPBA0, MT_DEVICE), - imx_map_entry(MX50, AIPS1, MT_DEVICE), - imx_map_entry(MX50, AIPS2, MT_DEVICE), -}; - -/* * Define the MX51 memory map. */ static struct map_desc mx51_io_desc[] __initdata = { @@ -59,11 +49,6 @@ static struct map_desc mx53_io_desc[] __initdata = { * system startup to create static physical to virtual memory mappings * for the IO modules. */ -void __init mx50_map_io(void) -{ - iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc)); -} - void __init mx51_map_io(void) { iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); @@ -74,13 +59,6 @@ void __init mx53_map_io(void) iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); } -void __init imx50_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX50); - mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); -} - /* * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by * the Freescale marketing division. However this did not remove the @@ -115,11 +93,6 @@ void __init imx53_init_early(void) mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); } -void __init mx50_init_irq(void) -{ - tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); -} - void __init mx51_init_irq(void) { tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); @@ -148,31 +121,10 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = { .script_addrs = &imx51_sdma_script, }; -static const struct resource imx50_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), -}; - static const struct resource imx51_audmux_res[] __initconst = { DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), }; -void __init imx50_soc_init(void) -{ - mxc_device_init(); - - /* i.mx50 has the i.mx35 type gpio */ - mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); - mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH); - mxc_register_gpio("imx35-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH); - mxc_register_gpio("imx35-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH); - mxc_register_gpio("imx35-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH); - mxc_register_gpio("imx35-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH); - - /* i.mx50 has the i.mx31 type audmux */ - platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res, - ARRAY_SIZE(imx50_audmux_res)); -} - void __init imx51_soc_init(void) { mxc_device_init(); diff --git a/arch/arm/mach-imx/mx50.h b/arch/arm/mach-imx/mx50.h deleted file mode 100644 index 09ac19c..0000000 --- a/arch/arm/mach-imx/mx50.h +++ /dev/null @@ -1,290 +0,0 @@ -#ifndef __MACH_MX50_H__ -#define __MACH_MX50_H__ - -/* - * IROM - */ -#define MX50_IROM_BASE_ADDR 0x0 -#define MX50_IROM_SIZE SZ_64K - -/* TZIC */ -#define MX50_TZIC_BASE_ADDR 0x0fffc000 -#define MX50_TZIC_SIZE SZ_16K - -/* - * IRAM - */ -#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */ -#define MX50_IRAM_PARTITIONS 16 -#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */ - -/* - * Databahn - */ -#define MX50_DATABAHN_BASE_ADDR 0x14000000 - -/* - * Graphics Memory of GPU - */ -#define MX50_GPU2D_BASE_ADDR 0x20000000 - -#define MX50_DEBUG_BASE_ADDR 0x40000000 -#define MX50_DEBUG_SIZE SZ_1M -#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000) -#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000) -#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000) -#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000) -#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000) -#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000) -#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000) -#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000) - -#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000) -#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000) -#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000) -#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000) -#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000) -#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000) -#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000) -#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000) -#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000) -#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000) -#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000) -#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000) -#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000) -#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000) - -/* - * SPBA global module enabled #0 - */ -#define MX50_SPBA0_BASE_ADDR 0x50000000 -#define MX50_SPBA0_SIZE SZ_1M - -#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000) -#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000) -#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000) -#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000) -#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000) -#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000) -#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000) - -/* - * AIPS 1 - */ -#define MX50_AIPS1_BASE_ADDR 0x53f00000 -#define MX50_AIPS1_SIZE SZ_1M - -#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000) -#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000) -#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000) -#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000) -#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000) -#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000) -#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000) -#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000) -#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000) -#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000) -#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000) -#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000) -#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000) -#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000) -#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000) -#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000) -#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000) -#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000) -#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000) -#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000) -#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000) -#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000) - -#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000) -#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000) - -/* - * AIPS 2 - */ -#define MX50_AIPS2_BASE_ADDR 0x63f00000 -#define MX50_AIPS2_SIZE SZ_1M - -#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000) -#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000) -#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000) -#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000) -#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000) -#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000) -#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000) -#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000) -#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000) -#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000) -#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000) -#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000) -#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000) -#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000) -#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000) -#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000) -#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000) - -/* - * Memory regions and CS - */ -#define MX50_CSD0_BASE_ADDR 0x70000000 -#define MX50_CSD1_BASE_ADDR 0xb0000000 -#define MX50_CS0_BASE_ADDR 0xf0000000 - -#define MX50_IO_P2V(x) IMX_IO_P2V(x) -#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x)) - -/* - * defines for SPBA modules - */ -#define MX50_SPBA_SDHC1 0x04 -#define MX50_SPBA_SDHC2 0x08 -#define MX50_SPBA_UART3 0x0c -#define MX50_SPBA_CSPI1 0x10 -#define MX50_SPBA_SSI2 0x14 -#define MX50_SPBA_SDHC3 0x20 -#define MX50_SPBA_SDHC4 0x24 -#define MX50_SPBA_SPDIF 0x28 -#define MX50_SPBA_ATA 0x30 -#define MX50_SPBA_SLIM 0x34 -#define MX50_SPBA_HSI2C 0x38 -#define MX50_SPBA_CTRL 0x3c - -/* - * DMA request assignments - */ -#define MX50_DMA_REQ_GPC 1 -#define MX50_DMA_REQ_ATA_UART4_RX 2 -#define MX50_DMA_REQ_ATA_UART4_TX 3 -#define MX50_DMA_REQ_CSPI1_RX 6 -#define MX50_DMA_REQ_CSPI1_TX 7 -#define MX50_DMA_REQ_CSPI2_RX 8 -#define MX50_DMA_REQ_CSPI2_TX 9 -#define MX50_DMA_REQ_I2C3_SDHC3 10 -#define MX50_DMA_REQ_SDHC4 11 -#define MX50_DMA_REQ_UART2_FIRI_RX 12 -#define MX50_DMA_REQ_UART2_FIRI_TX 13 -#define MX50_DMA_REQ_EXT0 14 -#define MX50_DMA_REQ_EXT1 15 -#define MX50_DMA_REQ_UART5_RX 16 -#define MX50_DMA_REQ_UART5_TX 17 -#define MX50_DMA_REQ_UART1_RX 18 -#define MX50_DMA_REQ_UART1_TX 19 -#define MX50_DMA_REQ_I2C1_SDHC1 20 -#define MX50_DMA_REQ_I2C2_SDHC2 21 -#define MX50_DMA_REQ_SSI2_RX2 22 -#define MX50_DMA_REQ_SSI2_TX2 23 -#define MX50_DMA_REQ_SSI2_RX1 24 -#define MX50_DMA_REQ_SSI2_TX1 25 -#define MX50_DMA_REQ_SSI1_RX2 26 -#define MX50_DMA_REQ_SSI1_TX2 27 -#define MX50_DMA_REQ_SSI1_RX1 28 -#define MX50_DMA_REQ_SSI1_TX1 29 -#define MX50_DMA_REQ_CSPI_RX 38 -#define MX50_DMA_REQ_CSPI_TX 39 -#define MX50_DMA_REQ_UART3_RX 42 -#define MX50_DMA_REQ_UART3_TX 43 - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1) -#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2) -#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3) -#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4) -#define MX50_INT_DAP (NR_IRQS_LEGACY + 5) -#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6) -#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7) -#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13) -#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14) -#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18) -#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19) -#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20) -#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21) -#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) -#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) -#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27) -#define MX50_INT_NIC (NR_IRQS_LEGACY + 28) -#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29) -#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30) -#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31) -#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33) -#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34) -#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35) -#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36) -#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37) -#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38) -#define MX50_INT_GPT (NR_IRQS_LEGACY + 39) -#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40) -#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) -#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) -#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) -#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) -#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) -#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) -#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) -#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) -#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) -#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) -#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) -#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) -#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) -#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) -#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) -#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) -#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58) -#define MX50_INT_KPP (NR_IRQS_LEGACY + 60) -#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61) -#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62) -#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63) -#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64) -#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65) -#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66) -#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67) -#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68) -#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69) -#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71) -#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72) -#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73) -#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74) -#define MX50_INT_SRC (NR_IRQS_LEGACY + 75) -#define MX50_INT_NM (NR_IRQS_LEGACY + 76) -#define MX50_INT_PMU (NR_IRQS_LEGACY + 77) -#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) -#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) -#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) -#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) -#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) -#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86) -#define MX50_INT_FEC (NR_IRQS_LEGACY + 87) -#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88) -#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) -#define MX50_INT_SJC (NR_IRQS_LEGACY + 90) -#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91) -#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92) -#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94) -#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97) -#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) -#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100) -#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102) -#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103) -#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104) -#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105) -#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106) -#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109) -#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110) -#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111) -#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112) -#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113) -#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114) -#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115) -#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116) -#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117) - -#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) -extern int mx50_revision(void); -#endif - -#endif /* ifndef __MACH_MX50_H__ */ diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index d782983..7dce17a 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -32,7 +32,6 @@ #define MXC_CPU_MX27 27 #define MXC_CPU_MX31 31 #define MXC_CPU_MX35 35 -#define MXC_CPU_MX50 50 #define MXC_CPU_MX51 51 #define MXC_CPU_MX53 53 @@ -126,18 +125,6 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx35() (0) #endif -#ifdef CONFIG_SOC_IMX50 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX50 -# endif -# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50) -#else -# define cpu_is_mx50() (0) -#endif - #ifdef CONFIG_SOC_IMX51 # ifdef mxc_cpu_type # undef mxc_cpu_type diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index d356931..7c0b03f 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -20,6 +20,8 @@ #include "common.h" #include "hardware.h" +#define SCU_STANDBY_ENABLE (1 << 5) + static void __iomem *scu_base; static struct map_desc scu_io_desc __initdata = { @@ -42,6 +44,14 @@ void __init imx_scu_map_io(void) scu_base = IMX_IO_ADDRESS(base); } +void imx_scu_standby_enable(void) +{ + u32 val = readl_relaxed(scu_base); + + val |= SCU_STANDBY_ENABLE; + writel_relaxed(val, scu_base); +} + static void __cpuinit imx_secondary_init(unsigned int cpu) { /* @@ -90,5 +100,6 @@ struct smp_operations imx_smp_ops __initdata = { .smp_boot_secondary = imx_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = imx_cpu_die, + .cpu_kill = imx_cpu_kill, #endif }; diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c index 2e063c2..f67fd7e 100644 --- a/arch/arm/mach-imx/pm-imx5.c +++ b/arch/arm/mach-imx/pm-imx5.c @@ -34,7 +34,7 @@ /* * set cpu low power mode before WFI instruction. This function is called - * mx5 because it can be used for mx50, mx51, and mx53. + * mx5 because it can be used for mx51, and mx53. */ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) { @@ -85,10 +85,7 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); - - /* Enable NEON SRPG for all but MX50TO1.0. */ - if (mx50_revision() != IMX_CHIP_REVISION_1_0) - __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); + __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); if (stop_mode) { empgc0 |= MXC_SRPGCR_PCR; diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index a17543d..ee42d20 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -41,6 +41,7 @@ static int imx6q_pm_enter(suspend_state_t state) cpu_suspend(0, imx6q_suspend_finish); imx_smp_prepare(); imx_gpc_post_resume(); + imx6q_set_lpm(WAIT_CLOCKED); break; default: return -EINVAL; diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index f017302..fea9131 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -152,7 +152,8 @@ static int v2_set_next_event(unsigned long evt, __raw_writel(tcmp, timer_base + V2_TCMP); - return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ? + return evt < 0x7fffffff && + (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ? -ETIME : 0; } @@ -256,7 +257,6 @@ static struct irqaction mxc_timer_irq = { static struct clock_event_device clockevent_mxc = { .name = "mxc_timer1", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .set_mode = mxc_set_mode, .set_next_event = mx1_2_set_next_event, .rating = 200, @@ -264,21 +264,13 @@ static struct clock_event_device clockevent_mxc = { static int __init mxc_clockevent_init(struct clk *timer_clk) { - unsigned int c = clk_get_rate(timer_clk); - if (timer_is_v2()) clockevent_mxc.set_next_event = v2_set_next_event; - clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, - clockevent_mxc.shift); - clockevent_mxc.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_mxc); - clockevent_mxc.min_delta_ns = - clockevent_delta2ns(0xff, &clockevent_mxc); - clockevent_mxc.cpumask = cpumask_of(0); - - clockevents_register_device(&clockevent_mxc); + clockevents_config_and_register(&clockevent_mxc, + clk_get_rate(timer_clk), + 0xff, 0xfffffffe); return 0; } diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index be50e79..e7fcea7 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@ -475,13 +475,12 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys) { int ret = 0; + if (!ap_syscon_base) + return -EINVAL; + if (nr == 0) { sys->mem_offset = PHYS_PCI_MEM_BASE; ret = pci_v3_setup_resources(sys); - /* Remap the Integrator system controller */ - ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); - if (!ap_syscon_base) - return -EINVAL; } return ret; @@ -497,6 +496,13 @@ void __init pci_v3_preinit(void) unsigned int temp; int ret; + /* Remap the Integrator system controller */ + ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); + if (!ap_syscon_base) { + pr_err("unable to remap the AP syscon for PCIv3\n"); + return; + } + pcibios_min_mem = 0x00100000; /* diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index f6ac695..1dbeb7c 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -519,22 +519,15 @@ static struct clock_event_device clockevent_ixp4xx = { .name = "ixp4xx timer1", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .rating = 200, - .shift = 24, .set_mode = ixp4xx_set_mode, .set_next_event = ixp4xx_set_next_event, }; static void __init ixp4xx_clockevent_init(void) { - clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC, - clockevent_ixp4xx.shift); - clockevent_ixp4xx.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx); - clockevent_ixp4xx.min_delta_ns = - clockevent_delta2ns(0xf, &clockevent_ixp4xx); clockevent_ixp4xx.cpumask = cpumask_of(0); - - clockevents_register_device(&clockevent_ixp4xx); + clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ, + 0xf, 0xfffffffe); } void ixp4xx_restart(char mode, const char *cmd) diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 8d2e5a9..d665309 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -19,7 +19,6 @@ obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o obj-$(CONFIG_MACH_T5325) += t5325-setup.o -obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o obj-$(CONFIG_MACH_ICONNECT_DT) += board-iconnect.o diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index d4af5c1..95cc04d 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -98,6 +98,8 @@ static void __init kirkwood_dt_init(void) /* Setup root of clk tree */ kirkwood_of_clk_init(); + kirkwood_cpuidle_init(); + #ifdef CONFIG_KEXEC kexec_reinit = kirkwood_enable_pcie; #endif diff --git a/arch/arm/mach-kirkwood/board-ns2.c b/arch/arm/mach-kirkwood/board-ns2.c index 8821720..f4632a8 100644 --- a/arch/arm/mach-kirkwood/board-ns2.c +++ b/arch/arm/mach-kirkwood/board-ns2.c @@ -18,47 +18,11 @@ #include <linux/gpio.h> #include <linux/of.h> #include "common.h" -#include "mpp.h" static struct mv643xx_eth_platform_data ns2_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; -static unsigned int ns2_mpp_config[] __initdata = { - MPP0_SPI_SCn, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, /* Fan speed (bit 1) */ - MPP8_TW0_SDA, - MPP9_TW0_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_GPO, /* Red led */ - MPP14_GPIO, /* USB fuse */ - MPP16_GPIO, /* SATA 0 power */ - MPP17_GPIO, /* SATA 1 power */ - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_SATA1_ACTn, - MPP21_SATA0_ACTn, - MPP22_GPIO, /* Fan speed (bit 0) */ - MPP23_GPIO, /* Fan power */ - MPP24_GPIO, /* USB mode select */ - MPP25_GPIO, /* Fan rotation fail */ - MPP26_GPIO, /* USB device vbus */ - MPP28_GPIO, /* USB enable host vbus */ - MPP29_GPIO, /* Blue led (slow register) */ - MPP30_GPIO, /* Blue led (command register) */ - MPP31_GPIO, /* Board power off */ - MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */ - MPP33_GPO, /* Fan speed (bit 2) */ - 0 -}; - #define NS2_GPIO_POWER_OFF 31 static void ns2_power_off(void) @@ -71,8 +35,6 @@ void __init ns2_init(void) /* * Basic setup. Needs to be called early. */ - kirkwood_mpp_conf(ns2_mpp_config); - if (of_machine_is_compatible("lacie,netspace_lite_v2") || of_machine_is_compatible("lacie,netspace_mini_v2")) ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index b5ad4df..49792a0 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -499,6 +499,28 @@ void __init kirkwood_wdt_init(void) orion_wdt_init(); } +/***************************************************************************** + * CPU idle + ****************************************************************************/ +static struct resource kirkwood_cpuidle_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = DDR_OPERATION_BASE, + .end = DDR_OPERATION_BASE + 3, + }, +}; + +static struct platform_device kirkwood_cpuidle = { + .name = "kirkwood_cpuidle", + .id = -1, + .resource = kirkwood_cpuidle_resource, + .num_resources = 1, +}; + +void __init kirkwood_cpuidle_init(void) +{ + platform_device_register(&kirkwood_cpuidle); +} /***************************************************************************** * Time handling @@ -667,6 +689,7 @@ void __init kirkwood_init(void) kirkwood_xor1_init(); kirkwood_crypto_init(); + kirkwood_cpuidle_init(); #ifdef CONFIG_KEXEC kexec_reinit = kirkwood_enable_pcie; #endif diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 283ab61..e956d02 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -50,6 +50,7 @@ void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay); void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *)); void kirkwood_audio_init(void); +void kirkwood_cpuidle_init(void); void kirkwood_restart(char, const char *); void kirkwood_clk_init(void); diff --git a/arch/arm/mach-kirkwood/cpuidle.c b/arch/arm/mach-kirkwood/cpuidle.c deleted file mode 100644 index f730467..0000000 --- a/arch/arm/mach-kirkwood/cpuidle.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * arch/arm/mach-kirkwood/cpuidle.c - * - * CPU idle Marvell Kirkwood SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * The cpu idle uses wait-for-interrupt and DDR self refresh in order - * to implement two idle states - - * #1 wait-for-interrupt - * #2 wait-for-interrupt and DDR self refresh - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/cpuidle.h> -#include <linux/io.h> -#include <linux/export.h> -#include <asm/proc-fns.h> -#include <asm/cpuidle.h> -#include <mach/kirkwood.h> - -#define KIRKWOOD_MAX_STATES 2 - -/* Actual code that puts the SoC in different idle states */ -static int kirkwood_enter_idle(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - writel(0x7, DDR_OPERATION_BASE); - cpu_do_idle(); - - return index; -} - -static struct cpuidle_driver kirkwood_idle_driver = { - .name = "kirkwood_idle", - .owner = THIS_MODULE, - .en_core_tk_irqen = 1, - .states[0] = ARM_CPUIDLE_WFI_STATE, - .states[1] = { - .enter = kirkwood_enter_idle, - .exit_latency = 10, - .target_residency = 100000, - .flags = CPUIDLE_FLAG_TIME_VALID, - .name = "DDR SR", - .desc = "WFI and DDR Self Refresh", - }, - .state_count = KIRKWOOD_MAX_STATES, -}; - -static DEFINE_PER_CPU(struct cpuidle_device, kirkwood_cpuidle_device); - -/* Initialize CPU idle by registering the idle states */ -static int kirkwood_init_cpuidle(void) -{ - struct cpuidle_device *device; - - device = &per_cpu(kirkwood_cpuidle_device, smp_processor_id()); - device->state_count = KIRKWOOD_MAX_STATES; - - cpuidle_register_driver(&kirkwood_idle_driver); - if (cpuidle_register_device(device)) { - pr_err("kirkwood_init_cpuidle: Failed registering\n"); - return -EIO; - } - return 0; -} - -device_initcall(kirkwood_init_cpuidle); diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index 041653a..a05563a 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -60,8 +60,9 @@ * Register Map */ #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000) +#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000) #define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500) -#define DDR_OPERATION_BASE (DDR_VIRT_BASE + 0x1418) +#define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418) #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000) #define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000) diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index a1c3ab6..d96ad4c 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -247,13 +247,9 @@ static struct hw_pci kirkwood_pci __initdata = { static void __init add_pcie_port(int index, void __iomem *base) { - pr_info("Kirkwood PCIe port %d: ", index); - - if (orion_pcie_link_up(base)) { - pr_info("link up\n"); - pcie_port_map[num_pcie_ports++] = index; - } else - pr_info("link down, ignoring\n"); + pcie_port_map[num_pcie_ports++] = index; + pr_info("Kirkwood PCIe port %d: link %s\n", index, + orion_pcie_link_up(base) ? "up" : "down"); } void __init kirkwood_pcie_init(unsigned int portmask) diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c index 88bd4ce..20eab63 100644 --- a/arch/arm/mach-lpc32xx/timer.c +++ b/arch/arm/mach-lpc32xx/timer.c @@ -70,7 +70,6 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode, static struct clock_event_device lpc32xx_clkevt = { .name = "lpc32xx_clkevt", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .rating = 300, .set_next_event = lpc32xx_clkevt_next_event, .set_mode = lpc32xx_clkevt_mode, @@ -141,14 +140,8 @@ void __init lpc32xx_timer_init(void) setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq); /* Setup the clockevent structure. */ - lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC, - lpc32xx_clkevt.shift); - lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1, - &lpc32xx_clkevt); - lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1, - &lpc32xx_clkevt) + 1; lpc32xx_clkevt.cpumask = cpumask_of(0); - clockevents_register_device(&lpc32xx_clkevt); + clockevents_config_and_register(&lpc32xx_clkevt, clkrate, 1, -1); /* Use timer1 as clock source. */ __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET, diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 936447c..86a18b3 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -141,7 +141,6 @@ static void timer_set_mode(enum clock_event_mode mode, static struct clock_event_device ckevt = { .name = "clockevent", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .rating = 200, .set_next_event = timer_set_next_event, .set_mode = timer_set_mode, @@ -198,15 +197,13 @@ void __init timer_init(int irq) setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE); - ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift); - ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt); - ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt); ckevt.cpumask = cpumask_of(0); setup_irq(irq, &timer_irq); clocksource_register_hz(&cksrc, CLOCK_TICK_RATE); - clockevents_register_device(&ckevt); + clockevents_config_and_register(&ckevt, CLOCK_TICK_RATE, + MIN_DELTA, MAX_DELTA); } #ifdef CONFIG_OF diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index dfc5067..2969027 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -143,13 +143,9 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt) evt->rating = msm_clockevent.rating; evt->set_mode = msm_timer_set_mode; evt->set_next_event = msm_timer_set_next_event; - evt->shift = msm_clockevent.shift; - evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift); - evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt); - evt->min_delta_ns = clockevent_delta2ns(4, evt); *__this_cpu_ptr(msm_evt.percpu_evt) = evt; - clockevents_register_device(evt); + clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000); enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING); return 0; } diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 5dcb369..99df4df 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -1,6 +1,8 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ -I$(srctree)/arch/arm/plat-orion/include +AFLAGS_coherency_ll.o := -Wa,-march=armv7-a + obj-y += system-controller.o obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c index 856f4c7..4210204 100644 --- a/arch/arm/mach-mxs/timer.c +++ b/arch/arm/mach-mxs/timer.c @@ -72,8 +72,9 @@ #define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14) #define BM_TIMROT_TIMCTRLn_IRQ (1 << 15) #define BP_TIMROT_TIMCTRLn_SELECT 0 -#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 -#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb +#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 +#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb +#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS 0xf static struct clock_event_device mxs_clockevent_device; static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED; @@ -195,7 +196,6 @@ static void mxs_set_mode(enum clock_event_mode mode, static struct clock_event_device mxs_clockevent_device = { .name = "mxs_timrot", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .set_mode = mxs_set_mode, .set_next_event = timrotv2_set_next_event, .rating = 200, @@ -203,25 +203,13 @@ static struct clock_event_device mxs_clockevent_device = { static int __init mxs_clockevent_init(struct clk *timer_clk) { - unsigned int c = clk_get_rate(timer_clk); - - mxs_clockevent_device.mult = - div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift); - mxs_clockevent_device.cpumask = cpumask_of(0); - if (timrot_is_v1()) { + if (timrot_is_v1()) mxs_clockevent_device.set_next_event = timrotv1_set_next_event; - mxs_clockevent_device.max_delta_ns = - clockevent_delta2ns(0xfffe, &mxs_clockevent_device); - mxs_clockevent_device.min_delta_ns = - clockevent_delta2ns(0xf, &mxs_clockevent_device); - } else { - mxs_clockevent_device.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device); - mxs_clockevent_device.min_delta_ns = - clockevent_delta2ns(0xf, &mxs_clockevent_device); - } - - clockevents_register_device(&mxs_clockevent_device); + mxs_clockevent_device.cpumask = cpumask_of(0); + clockevents_config_and_register(&mxs_clockevent_device, + clk_get_rate(timer_clk), + timrot_is_v1() ? 0xf : 0x2, + timrot_is_v1() ? 0xfffe : 0xfffffffe); return 0; } @@ -288,7 +276,7 @@ void __init mxs_timer_init(void) /* one for clock_event */ __raw_writel((timrot_is_v1() ? BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL : - BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) | + BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) | BM_TIMROT_TIMCTRLn_UPDATE | BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); @@ -296,7 +284,7 @@ void __init mxs_timer_init(void) /* another for clocksource */ __raw_writel((timrot_is_v1() ? BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL : - BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) | + BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) | BM_TIMROT_TIMCTRLn_RELOAD, mxs_timrot_base + HW_TIMROT_TIMCTRLn(1)); diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c index 0dee452..6df42e6 100644 --- a/arch/arm/mach-netx/time.c +++ b/arch/arm/mach-netx/time.c @@ -76,7 +76,6 @@ static int netx_set_next_event(unsigned long evt, static struct clock_event_device netx_clockevent = { .name = "netx-timer" __stringify(TIMER_CLOCKEVENT), - .shift = 32, .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_next_event = netx_set_next_event, .set_mode = netx_set_mode, @@ -140,14 +139,9 @@ void __init netx_timer_init(void) clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE), "netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up); - netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, - netx_clockevent.shift); - netx_clockevent.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &netx_clockevent); /* with max_delta_ns >= delta2ns(0x800) the system currently runs fine. * Adding some safety ... */ - netx_clockevent.min_delta_ns = - clockevent_delta2ns(0xa00, &netx_clockevent); netx_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&netx_clockevent); + clockevents_config_and_register(&netx_clockevent, CLOCK_TICK_RATE, + 0xa00, 0xfffffffe); } diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index 1d4512f..726ec23 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -145,7 +145,6 @@ static void omap_mpu_set_mode(enum clock_event_mode mode, static struct clock_event_device clockevent_mpu_timer1 = { .name = "mpu_timer1", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .set_next_event = omap_mpu_set_next_event, .set_mode = omap_mpu_set_mode, }; @@ -170,15 +169,9 @@ static __init void omap_init_mpu_timer(unsigned long rate) setup_irq(INT_TIMER1, &omap_mpu_timer1_irq); omap_mpu_timer_start(0, (rate / HZ) - 1, 1); - clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC, - clockevent_mpu_timer1.shift); - clockevent_mpu_timer1.max_delta_ns = - clockevent_delta2ns(-1, &clockevent_mpu_timer1); - clockevent_mpu_timer1.min_delta_ns = - clockevent_delta2ns(1, &clockevent_mpu_timer1); - clockevent_mpu_timer1.cpumask = cpumask_of(0); - clockevents_register_device(&clockevent_mpu_timer1); + clockevents_config_and_register(&clockevent_mpu_timer1, rate, + 1, -1); } diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c index 41152fa..0b74246 100644 --- a/arch/arm/mach-omap1/timer32k.c +++ b/arch/arm/mach-omap1/timer32k.c @@ -140,7 +140,6 @@ static void omap_32k_timer_set_mode(enum clock_event_mode mode, static struct clock_event_device clockevent_32k_timer = { .name = "32k-timer", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .set_next_event = omap_32k_timer_set_next_event, .set_mode = omap_32k_timer_set_mode, }; @@ -165,16 +164,9 @@ static __init void omap_init_32k_timer(void) { setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); - clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC, - NSEC_PER_SEC, - clockevent_32k_timer.shift); - clockevent_32k_timer.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer); - clockevent_32k_timer.min_delta_ns = - clockevent_delta2ns(1, &clockevent_32k_timer); - clockevent_32k_timer.cpumask = cpumask_of(0); - clockevents_register_device(&clockevent_32k_timer); + clockevents_config_and_register(&clockevent_32k_timer, + OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe); } /* diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c index af11dcd..a00d391 100644 --- a/arch/arm/mach-omap2/am35xx-emac.c +++ b/arch/arm/mach-omap2/am35xx-emac.c @@ -63,7 +63,7 @@ static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh, struct platform_device *pdev; pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len, - NULL, 0, false); + false); if (IS_ERR(pdev)) { WARN(1, "Can't build omap_device for %s:%s.\n", oh->class->name, oh->name); diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 22838fa..b623179 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -397,6 +397,12 @@ static struct omap_board_mux board_mux[] __initdata = { OMAP_PULL_ENA), OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), + /* UART2 - BT/FM/GPS shared transport */ + OMAP4_MUX(UART2_CTS, OMAP_PIN_INPUT | OMAP_MUX_MODE0), + OMAP4_MUX(UART2_RTS, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), + OMAP4_MUX(UART2_RX, OMAP_PIN_INPUT | OMAP_MUX_MODE0), + OMAP4_MUX(UART2_TX, OMAP_PIN_OUTPUT | OMAP_MUX_MODE0), + { .reg_offset = OMAP_MUX_TERMINATOR }, }; diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c index 7e5febe..0f0a97c 100644 --- a/arch/arm/mach-omap2/cclock2420_data.c +++ b/arch/arm/mach-omap2/cclock2420_data.c @@ -622,15 +622,10 @@ static struct clk_hw_omap gpios_fck_hw = { DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops); -static struct clk wu_l4_ick; - -DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm"); -DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops); - static struct clk gpios_ick; static const char *gpios_ick_parent_names[] = { - "wu_l4_ick", + "sys_ck", }; static struct clk_hw_omap gpios_ick_hw = { @@ -1682,13 +1677,6 @@ static struct clk_hw_omap wdt1_ick_hw = { DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk wdt1_osc_ck; - -static const struct clk_ops wdt1_osc_ck_ops = {}; - -DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL); -DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops); - static struct clk wdt3_fck; static struct clk_hw_omap wdt3_fck_hw = { @@ -1767,7 +1755,6 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), - CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X), CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), @@ -1797,7 +1784,6 @@ static struct omap_clk omap2420_clks[] = { /* L4 domain clocks */ CLK(NULL, "l4_ck", &l4_ck, CK_242X), CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), - CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X), /* virtual meta-group clock */ CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), /* general l4 interface ck, multi-parent functional clk */ @@ -1935,6 +1921,8 @@ int __init omap2420_clk_init(void) omap2_init_clk_hw_omap_clocks(c->lk.clk); } + omap2xxx_clkt_vps_late_init(); + omap2_clk_disable_autoidle_all(); omap2_clk_enable_init_clocks(enable_init_clks, diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c index eda079b..aed8f74 100644 --- a/arch/arm/mach-omap2/cclock2430_data.c +++ b/arch/arm/mach-omap2/cclock2430_data.c @@ -601,15 +601,10 @@ static struct clk_hw_omap gpios_fck_hw = { DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops); -static struct clk wu_l4_ick; - -DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm"); -DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops); - static struct clk gpios_ick; static const char *gpios_ick_parent_names[] = { - "wu_l4_ick", + "sys_ck", }; static struct clk_hw_omap gpios_ick_hw = { @@ -1811,13 +1806,6 @@ static struct clk_hw_omap wdt1_ick_hw = { DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); -static struct clk wdt1_osc_ck; - -static const struct clk_ops wdt1_osc_ck_ops = {}; - -DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL); -DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops); - static struct clk wdt4_fck; static struct clk_hw_omap wdt4_fck_hw = { @@ -1869,7 +1857,6 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), - CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X), CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), CLK(NULL, "emul_ck", &emul_ck, CK_243X), @@ -1898,7 +1885,6 @@ static struct omap_clk omap2430_clks[] = { /* L4 domain clocks */ CLK(NULL, "l4_ck", &l4_ck, CK_243X), CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), - CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X), /* virtual meta-group clock */ CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), /* general l4 interface ck, multi-parent functional clk */ @@ -2050,6 +2036,8 @@ int __init omap2430_clk_init(void) omap2_init_clk_hw_omap_clocks(c->lk.clk); } + omap2xxx_clkt_vps_late_init(); + omap2_clk_disable_autoidle_all(); omap2_clk_enable_init_clocks(enable_init_clks, diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c index 5789a5e..cebe2b3 100644 --- a/arch/arm/mach-omap2/cclock44xx_data.c +++ b/arch/arm/mach-omap2/cclock44xx_data.c @@ -16,6 +16,10 @@ * XXX Some of the ES1 clocks have been removed/changed; once support * is added for discriminating clocks by ES level, these should be added back * in. + * + * XXX All of the remaining MODULEMODE clock nodes should be removed + * once the drivers are updated to use pm_runtime or to use the appropriate + * upstream clock node for rate/parent selection. */ #include <linux/kernel.h> @@ -315,7 +319,7 @@ DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); -static const struct clk_ops dmic_fck_ops = { +static const struct clk_ops dpll_hsd_ops = { .enable = &omap2_dflt_clk_enable, .disable = &omap2_dflt_clk_disable, .is_enabled = &omap2_dflt_clk_is_enabled, @@ -325,6 +329,12 @@ static const struct clk_ops dmic_fck_ops = { .init = &omap2_init_clk_clkdm, }; +static const struct clk_ops func_dmic_abe_gfclk_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + static const char *dpll_core_m3x2_ck_parents[] = { "dpll_core_x2_ck", }; @@ -340,7 +350,7 @@ DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div, OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, OMAP4430_CM_DIV_M3_DPLL_CORE, OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, - dpll_core_m3x2_ck_parents, dmic_fck_ops); + dpll_core_m3x2_ck_parents, dpll_hsd_ops); DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE, @@ -547,7 +557,7 @@ DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div, OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, OMAP4430_CM_DIV_M3_DPLL_PER, OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, - dpll_per_m3x2_ck_parents, dmic_fck_ops); + dpll_per_m3x2_ck_parents, dpll_hsd_ops); DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_PER, @@ -749,10 +759,6 @@ DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0, OMAP4430_CM_L4SEC_AES2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0, - OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); - DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL); @@ -774,11 +780,6 @@ DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0, OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0, - OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); - static const char *dmic_sync_mux_ck_parents[] = { "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk", }; @@ -795,23 +796,13 @@ static const struct clksel func_dmic_abe_gfclk_sel[] = { { .parent = NULL }, }; -static const char *dmic_fck_parents[] = { +static const char *func_dmic_abe_gfclk_parents[] = { "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk", }; -/* Merged func_dmic_abe_gfclk into dmic */ -static struct clk dmic_fck; - -DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel, - OMAP4430_CM1_ABE_DMIC_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_MASK, - OMAP4430_CM1_ABE_DMIC_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - dmic_fck_parents, dmic_fck_ops); - -DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0, - OMAP4430_CM_TESLA_TESLA_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); +DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel, + OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK, + func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops); DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0, OMAP4430_CM_DSS_DSS_CLKCTRL, @@ -833,177 +824,57 @@ DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0, OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, - OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0, - OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0, - OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT, OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); -DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0, - OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, OMAP4430_CM_WKUP_GPIO1_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0, - OMAP4430_CM_WKUP_GPIO1_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0, - OMAP4430_CM_L4PER_GPIO2_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, OMAP4430_CM_L4PER_GPIO3_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0, - OMAP4430_CM_L4PER_GPIO3_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0, - OMAP4430_CM_L4PER_GPIO4_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0, - OMAP4430_CM_L4PER_GPIO5_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0, - OMAP4430_CM_L4PER_GPIO6_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0, - OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, - 0x0, NULL); - static const struct clksel sgx_clk_mux_sel[] = { { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -static const char *gpu_fck_parents[] = { +static const char *sgx_clk_mux_parents[] = { "dpll_core_m7x2_ck", "dpll_per_m7x2_ck", }; -/* Merged sgx_clk_mux into gpu */ -DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel, - OMAP4430_CM_GFX_GFX_CLKCTRL, - OMAP4430_CLKSEL_SGX_FCLK_MASK, - OMAP4430_CM_GFX_GFX_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - gpu_fck_parents, dmic_fck_ops); - -DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0, - OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); +DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel, + OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK, + sgx_clk_mux_parents, func_dmic_abe_gfclk_ops); DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT, OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); -DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0, - OMAP4430_CM_L4PER_I2C1_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0, - OMAP4430_CM_L4PER_I2C2_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0, - OMAP4430_CM_L4PER_I2C3_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0, - OMAP4430_CM_L4PER_I2C4_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0, - OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0, OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0, - OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0, - OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -static struct clk l3_instr_ick; - -static const char *l3_instr_ick_parent_names[] = { - "l3_div_ck", -}; - -static const struct clk_ops l3_instr_ick_ops = { - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .init = &omap2_init_clk_clkdm, -}; - -static struct clk_hw_omap l3_instr_ick_hw = { - .hw = { - .clk = &l3_instr_ick, - }, - .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, - .clkdm_name = "l3_instr_clkdm", -}; - -DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); - -static struct clk l3_main_3_ick; -static struct clk_hw_omap l3_main_3_ick_hw = { - .hw = { - .clk = &l3_main_3_ick, - }, - .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, - .clkdm_name = "l3_instr_clkdm", -}; - -DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); - DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, @@ -1016,17 +887,13 @@ static const struct clksel func_mcasp_abe_gfclk_sel[] = { { .parent = NULL }, }; -static const char *mcasp_fck_parents[] = { +static const char *func_mcasp_abe_gfclk_parents[] = { "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk", }; -/* Merged func_mcasp_abe_gfclk into mcasp */ -DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel, - OMAP4430_CM1_ABE_MCASP_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_MASK, - OMAP4430_CM1_ABE_MCASP_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - mcasp_fck_parents, dmic_fck_ops); +DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel, + OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK, + func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops); DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, @@ -1040,17 +907,14 @@ static const struct clksel func_mcbsp1_gfclk_sel[] = { { .parent = NULL }, }; -static const char *mcbsp1_fck_parents[] = { +static const char *func_mcbsp1_gfclk_parents[] = { "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk", }; -/* Merged func_mcbsp1_gfclk into mcbsp1 */ -DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel, - OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_MASK, - OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - mcbsp1_fck_parents, dmic_fck_ops); +DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents, + func_dmic_abe_gfclk_ops); DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, @@ -1064,17 +928,14 @@ static const struct clksel func_mcbsp2_gfclk_sel[] = { { .parent = NULL }, }; -static const char *mcbsp2_fck_parents[] = { +static const char *func_mcbsp2_gfclk_parents[] = { "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk", }; -/* Merged func_mcbsp2_gfclk into mcbsp2 */ -DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel, - OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_MASK, - OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - mcbsp2_fck_parents, dmic_fck_ops); +DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents, + func_dmic_abe_gfclk_ops); DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, @@ -1088,17 +949,14 @@ static const struct clksel func_mcbsp3_gfclk_sel[] = { { .parent = NULL }, }; -static const char *mcbsp3_fck_parents[] = { +static const char *func_mcbsp3_gfclk_parents[] = { "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk", }; -/* Merged func_mcbsp3_gfclk into mcbsp3 */ -DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel, - OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_MASK, - OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - mcbsp3_fck_parents, dmic_fck_ops); +DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents, + func_dmic_abe_gfclk_ops); static const char *mcbsp4_sync_mux_ck_parents[] = { "func_96m_fclk", "per_abe_nc_fclk", @@ -1115,37 +973,14 @@ static const struct clksel per_mcbsp4_gfclk_sel[] = { { .parent = NULL }, }; -static const char *mcbsp4_fck_parents[] = { +static const char *per_mcbsp4_gfclk_parents[] = { "mcbsp4_sync_mux_ck", "pad_clks_ck", }; -/* Merged per_mcbsp4_gfclk into mcbsp4 */ -DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel, - OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_24_24_MASK, - OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - mcbsp4_fck_parents, dmic_fck_ops); - -DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0, - OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); +DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel, + OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents, + func_dmic_abe_gfclk_ops); static const struct clksel hsmmc1_fclk_sel[] = { { .parent = &func_64m_fclk, .rates = div_1_0_rates }, @@ -1153,69 +988,22 @@ static const struct clksel hsmmc1_fclk_sel[] = { { .parent = NULL }, }; -static const char *mmc1_fck_parents[] = { +static const char *hsmmc1_fclk_parents[] = { "func_64m_fclk", "func_96m_fclk", }; -/* Merged hsmmc1_fclk into mmc1 */ -DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel, - OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK, - OMAP4430_CM_L3INIT_MMC1_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - mmc1_fck_parents, dmic_fck_ops); - -/* Merged hsmmc2_fclk into mmc2 */ -DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel, - OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, - OMAP4430_CM_L3INIT_MMC2_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - mmc1_fck_parents, dmic_fck_ops); - -DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0, - OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - -static struct clk ocp_wp_noc_ick; - -static struct clk_hw_omap ocp_wp_noc_ick_hw = { - .hw = { - .clk = &ocp_wp_noc_ick, - }, - .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, - .clkdm_name = "l3_instr_clkdm", -}; - -DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); +DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel, + OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK, + hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); -DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0, - OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, - 0x0, NULL); +DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel, + OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, + hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0, - OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, - 0x0, NULL); - DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0, OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL); @@ -1232,10 +1020,6 @@ DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0, OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0, - OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0, OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL); @@ -1249,10 +1033,6 @@ DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck", OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0, - OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); @@ -1271,52 +1051,35 @@ static const struct clksel dmt1_clk_mux_sel[] = { { .parent = NULL }, }; -/* Merged dmt1_clk_mux into timer1 */ -DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK, - OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); - -/* Merged cm2_dm10_mux into timer10 */ -DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - OMAP4430_CLKSEL_MASK, - OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); - -/* Merged cm2_dm11_mux into timer11 */ -DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - OMAP4430_CLKSEL_MASK, - OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); - -/* Merged cm2_dm2_mux into timer2 */ -DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - OMAP4430_CLKSEL_MASK, - OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); - -/* Merged cm2_dm3_mux into timer3 */ -DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - OMAP4430_CLKSEL_MASK, - OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); - -/* Merged cm2_dm4_mux into timer4 */ -DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - OMAP4430_CLKSEL_MASK, - OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); +DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK, + abe_dpll_bypass_clk_mux_ck_parents, + func_dmic_abe_gfclk_ops); + +DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK, + abe_dpll_bypass_clk_mux_ck_parents, + func_dmic_abe_gfclk_ops); + +DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK, + abe_dpll_bypass_clk_mux_ck_parents, + func_dmic_abe_gfclk_ops); + +DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK, + abe_dpll_bypass_clk_mux_ck_parents, + func_dmic_abe_gfclk_ops); + +DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK, + abe_dpll_bypass_clk_mux_ck_parents, + func_dmic_abe_gfclk_ops); + +DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK, + abe_dpll_bypass_clk_mux_ck_parents, + func_dmic_abe_gfclk_ops); static const struct clksel timer5_sync_mux_sel[] = { { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, @@ -1324,61 +1087,30 @@ static const struct clksel timer5_sync_mux_sel[] = { { .parent = NULL }, }; -static const char *timer5_fck_parents[] = { +static const char *timer5_sync_mux_parents[] = { "syc_clk_div_ck", "sys_32k_ck", }; -/* Merged timer5_sync_mux into timer5 */ -DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel, - OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK, - OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - timer5_fck_parents, dmic_fck_ops); - -/* Merged timer6_sync_mux into timer6 */ -DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel, - OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK, - OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - timer5_fck_parents, dmic_fck_ops); - -/* Merged timer7_sync_mux into timer7 */ -DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel, - OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK, - OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - timer5_fck_parents, dmic_fck_ops); - -/* Merged timer8_sync_mux into timer8 */ -DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel, - OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK, - OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - timer5_fck_parents, dmic_fck_ops); - -/* Merged cm2_dm9_mux into timer9 */ -DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - OMAP4430_CLKSEL_MASK, - OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, - abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); - -DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L4PER_UART1_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); +DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK, + timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); -DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L4PER_UART2_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); +DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK, + timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); -DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L4PER_UART3_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); +DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK, + timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); -DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L4PER_UART4_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); +DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK, + timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); + +DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK, + abe_dpll_bypass_clk_mux_ck_parents, + func_dmic_abe_gfclk_ops); static struct clk usb_host_fs_fck; @@ -1512,18 +1244,6 @@ DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0, OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); - /* Remaining optional clocks */ static const char *pmd_stm_clock_mux_ck_parents[] = { "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck", @@ -1774,106 +1494,61 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), - CLK(NULL, "aess_fck", &aess_fck, CK_443X), CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), - CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), - CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), - CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), + CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk, CK_443X), CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), CLK(NULL, "dss_fck", &dss_fck, CK_443X), CLK("omapdss_dss", "ick", &dss_fck, CK_443X), - CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), - CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), - CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), - CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), - CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), - CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), - CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), - CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), - CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), - CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), - CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), - CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), - CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X), + CLK(NULL, "sgx_clk_mux", &sgx_clk_mux, CK_443X), CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), - CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X), - CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X), - CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X), - CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X), - CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), - CLK(NULL, "iss_fck", &iss_fck, CK_443X), - CLK(NULL, "iva_fck", &iva_fck, CK_443X), - CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), - CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), - CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), - CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), + CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk, CK_443X), CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X), + CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk, CK_443X), CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X), + CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk, CK_443X), CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), - CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), + CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk, CK_443X), CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), - CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), - CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), - CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X), - CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X), - CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X), - CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X), - CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X), - CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X), - CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X), - CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X), - CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), - CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), - CLK(NULL, "rng_ick", &rng_ick, CK_443X), - CLK("omap_rng", "ick", &rng_ick, CK_443X), + CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X), + CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X), + CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X), CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), - CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), - CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), - CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), - CLK(NULL, "timer1_fck", &timer1_fck, CK_443X), - CLK(NULL, "timer10_fck", &timer10_fck, CK_443X), - CLK(NULL, "timer11_fck", &timer11_fck, CK_443X), - CLK(NULL, "timer2_fck", &timer2_fck, CK_443X), - CLK(NULL, "timer3_fck", &timer3_fck, CK_443X), - CLK(NULL, "timer4_fck", &timer4_fck, CK_443X), - CLK(NULL, "timer5_fck", &timer5_fck, CK_443X), - CLK(NULL, "timer6_fck", &timer6_fck, CK_443X), - CLK(NULL, "timer7_fck", &timer7_fck, CK_443X), - CLK(NULL, "timer8_fck", &timer8_fck, CK_443X), - CLK(NULL, "timer9_fck", &timer9_fck, CK_443X), - CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), - CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), - CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), - CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), + CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux, CK_443X), + CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux, CK_443X), + CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux, CK_443X), + CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux, CK_443X), + CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux, CK_443X), + CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux, CK_443X), + CLK(NULL, "timer5_sync_mux", &timer5_sync_mux, CK_443X), + CLK(NULL, "timer6_sync_mux", &timer6_sync_mux, CK_443X), + CLK(NULL, "timer7_sync_mux", &timer7_sync_mux, CK_443X), + CLK(NULL, "timer8_sync_mux", &timer8_sync_mux, CK_443X), + CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux, CK_443X), CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), @@ -1901,9 +1576,6 @@ static struct omap_clk omap44xx_clks[] = { CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), CLK(NULL, "usim_ck", &usim_ck, CK_443X), CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), - CLK(NULL, "usim_fck", &usim_fck, CK_443X), - CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X), - CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), @@ -1980,15 +1652,6 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), }; -static const char *enable_init_clks[] = { - "emif1_fck", - "emif2_fck", - "gpmc_ick", - "l3_instr_ick", - "l3_main_3_ick", - "ocp_wp_noc_ick", -}; - int __init omap4xxx_clk_init(void) { u32 cpu_clkflg; @@ -2019,21 +1682,17 @@ int __init omap4xxx_clk_init(void) omap2_clk_disable_autoidle_all(); - omap2_clk_enable_init_clocks(enable_init_clks, - ARRAY_SIZE(enable_init_clks)); - /* * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power * state when turning the ABE clock domain. Workaround this by * locking the ABE DPLL on boot. + * Lock the ABE DPLL in any case to avoid issues with audio. */ - if (cpu_is_omap446x()) { - rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck); - if (!rc) - rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ); - if (rc) - pr_err("%s: failed to configure ABE DPLL!\n", __func__); - } + rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck); + if (!rc) + rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ); + if (rc) + pr_err("%s: failed to configure ABE DPLL!\n", __func__); return 0; } diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 7faf82d..2da3b5e 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -92,8 +92,6 @@ static int _clkdm_register(struct clockdomain *clkdm) pwrdm_add_clkdm(pwrdm, clkdm); - spin_lock_init(&clkdm->lock); - pr_debug("clockdomain: registered %s\n", clkdm->name); return 0; @@ -122,7 +120,7 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm, return cd; } -/* +/** * _autodep_lookup - resolve autodep clkdm names to clkdm pointers; store * @autodep: struct clkdm_autodep * to resolve * @@ -154,88 +152,206 @@ static void _autodep_lookup(struct clkdm_autodep *autodep) autodep->clkdm.ptr = clkdm; } -/* - * _clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable - * @clkdm: struct clockdomain * +/** + * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms + * @clkdm: clockdomain that we are resolving dependencies for + * @clkdm_deps: ptr to array of struct clkdm_deps to resolve * - * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm' - * in hardware-supervised mode. Meant to be called from clock framework - * when a clock inside clockdomain 'clkdm' is enabled. No return value. + * Iterates through @clkdm_deps, looking up the struct clockdomain named by + * clkdm_name and storing the clockdomain pointer in the struct clkdm_dep. + * No return value. + */ +static void _resolve_clkdm_deps(struct clockdomain *clkdm, + struct clkdm_dep *clkdm_deps) +{ + struct clkdm_dep *cd; + + for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) { + if (cd->clkdm) + continue; + cd->clkdm = _clkdm_lookup(cd->clkdm_name); + + WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen", + clkdm->name, cd->clkdm_name); + } +} + +/** + * _clkdm_add_wkdep - add a wakeup dependency from clkdm2 to clkdm1 (lockless) + * @clkdm1: wake this struct clockdomain * up (dependent) + * @clkdm2: when this struct clockdomain * wakes up (source) * - * XXX autodeps are deprecated and should be removed at the earliest - * opportunity + * When the clockdomain represented by @clkdm2 wakes up, wake up + * @clkdm1. Implemented in hardware on the OMAP, this feature is + * designed to reduce wakeup latency of the dependent clockdomain @clkdm1. + * Returns -EINVAL if presented with invalid clockdomain pointers, + * -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or 0 upon + * success. */ -void _clkdm_add_autodeps(struct clockdomain *clkdm) +static int _clkdm_add_wkdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) { - struct clkdm_autodep *autodep; + struct clkdm_dep *cd; + int ret = 0; - if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS) - return; + if (!clkdm1 || !clkdm2) + return -EINVAL; - for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { - if (IS_ERR(autodep->clkdm.ptr)) - continue; + cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); + if (IS_ERR(cd)) + ret = PTR_ERR(cd); - pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n", - clkdm->name, autodep->clkdm.ptr->name); + if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep) + ret = -EINVAL; + + if (ret) { + pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n", + clkdm1->name, clkdm2->name); + return ret; + } + + cd->wkdep_usecount++; + if (cd->wkdep_usecount == 1) { + pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n", + clkdm1->name, clkdm2->name); - clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr); - clkdm_add_wkdep(clkdm, autodep->clkdm.ptr); + ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2); } + + return ret; } -/* - * _clkdm_add_autodeps - remove auto sleepdeps/wkdeps from clkdm - * @clkdm: struct clockdomain * +/** + * _clkdm_del_wkdep - remove a wakeup dep from clkdm2 to clkdm1 (lockless) + * @clkdm1: wake this struct clockdomain * up (dependent) + * @clkdm2: when this struct clockdomain * wakes up (source) * - * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm' - * in hardware-supervised mode. Meant to be called from clock framework - * when a clock inside clockdomain 'clkdm' is disabled. No return value. + * Remove a wakeup dependency causing @clkdm1 to wake up when @clkdm2 + * wakes up. Returns -EINVAL if presented with invalid clockdomain + * pointers, -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or + * 0 upon success. + */ +static int _clkdm_del_wkdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + struct clkdm_dep *cd; + int ret = 0; + + if (!clkdm1 || !clkdm2) + return -EINVAL; + + cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); + if (IS_ERR(cd)) + ret = PTR_ERR(cd); + + if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep) + ret = -EINVAL; + + if (ret) { + pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n", + clkdm1->name, clkdm2->name); + return ret; + } + + cd->wkdep_usecount--; + if (cd->wkdep_usecount == 0) { + pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n", + clkdm1->name, clkdm2->name); + + ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2); + } + + return ret; +} + +/** + * _clkdm_add_sleepdep - add a sleep dependency from clkdm2 to clkdm1 (lockless) + * @clkdm1: prevent this struct clockdomain * from sleeping (dependent) + * @clkdm2: when this struct clockdomain * is active (source) * - * XXX autodeps are deprecated and should be removed at the earliest - * opportunity + * Prevent @clkdm1 from automatically going inactive (and then to + * retention or off) if @clkdm2 is active. Returns -EINVAL if + * presented with invalid clockdomain pointers or called on a machine + * that does not support software-configurable hardware sleep + * dependencies, -ENOENT if the specified dependency cannot be set in + * hardware, or 0 upon success. */ -void _clkdm_del_autodeps(struct clockdomain *clkdm) +static int _clkdm_add_sleepdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) { - struct clkdm_autodep *autodep; + struct clkdm_dep *cd; + int ret = 0; - if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS) - return; + if (!clkdm1 || !clkdm2) + return -EINVAL; - for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { - if (IS_ERR(autodep->clkdm.ptr)) - continue; + cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); + if (IS_ERR(cd)) + ret = PTR_ERR(cd); - pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n", - clkdm->name, autodep->clkdm.ptr->name); + if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep) + ret = -EINVAL; - clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr); - clkdm_del_wkdep(clkdm, autodep->clkdm.ptr); + if (ret) { + pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n", + clkdm1->name, clkdm2->name); + return ret; + } + + cd->sleepdep_usecount++; + if (cd->sleepdep_usecount == 1) { + pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n", + clkdm1->name, clkdm2->name); + + ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2); } + + return ret; } /** - * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms - * @clkdm: clockdomain that we are resolving dependencies for - * @clkdm_deps: ptr to array of struct clkdm_deps to resolve + * _clkdm_del_sleepdep - remove a sleep dep from clkdm2 to clkdm1 (lockless) + * @clkdm1: prevent this struct clockdomain * from sleeping (dependent) + * @clkdm2: when this struct clockdomain * is active (source) * - * Iterates through @clkdm_deps, looking up the struct clockdomain named by - * clkdm_name and storing the clockdomain pointer in the struct clkdm_dep. - * No return value. + * Allow @clkdm1 to automatically go inactive (and then to retention or + * off), independent of the activity state of @clkdm2. Returns -EINVAL + * if presented with invalid clockdomain pointers or called on a machine + * that does not support software-configurable hardware sleep dependencies, + * -ENOENT if the specified dependency cannot be cleared in hardware, or + * 0 upon success. */ -static void _resolve_clkdm_deps(struct clockdomain *clkdm, - struct clkdm_dep *clkdm_deps) +static int _clkdm_del_sleepdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) { struct clkdm_dep *cd; + int ret = 0; - for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) { - if (cd->clkdm) - continue; - cd->clkdm = _clkdm_lookup(cd->clkdm_name); + if (!clkdm1 || !clkdm2) + return -EINVAL; - WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen", - clkdm->name, cd->clkdm_name); + cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); + if (IS_ERR(cd)) + ret = PTR_ERR(cd); + + if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep) + ret = -EINVAL; + + if (ret) { + pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n", + clkdm1->name, clkdm2->name); + return ret; } + + cd->sleepdep_usecount--; + if (cd->sleepdep_usecount == 0) { + pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n", + clkdm1->name, clkdm2->name); + + ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2); + } + + return ret; } /* Public functions */ @@ -456,30 +572,18 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm) int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) { struct clkdm_dep *cd; - int ret = 0; + int ret; if (!clkdm1 || !clkdm2) return -EINVAL; cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); if (IS_ERR(cd)) - ret = PTR_ERR(cd); + return PTR_ERR(cd); - if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep) - ret = -EINVAL; - - if (ret) { - pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n", - clkdm1->name, clkdm2->name); - return ret; - } - - if (atomic_inc_return(&cd->wkdep_usecount) == 1) { - pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n", - clkdm1->name, clkdm2->name); - - ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2); - } + pwrdm_lock(cd->clkdm->pwrdm.ptr); + ret = _clkdm_add_wkdep(clkdm1, clkdm2); + pwrdm_unlock(cd->clkdm->pwrdm.ptr); return ret; } @@ -497,30 +601,18 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) { struct clkdm_dep *cd; - int ret = 0; + int ret; if (!clkdm1 || !clkdm2) return -EINVAL; cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); if (IS_ERR(cd)) - ret = PTR_ERR(cd); + return PTR_ERR(cd); - if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep) - ret = -EINVAL; - - if (ret) { - pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n", - clkdm1->name, clkdm2->name); - return ret; - } - - if (atomic_dec_return(&cd->wkdep_usecount) == 0) { - pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n", - clkdm1->name, clkdm2->name); - - ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2); - } + pwrdm_lock(cd->clkdm->pwrdm.ptr); + ret = _clkdm_del_wkdep(clkdm1, clkdm2); + pwrdm_unlock(cd->clkdm->pwrdm.ptr); return ret; } @@ -560,7 +652,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) return ret; } - /* XXX It's faster to return the atomic wkdep_usecount */ + /* XXX It's faster to return the wkdep_usecount */ return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2); } @@ -600,30 +692,18 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) { struct clkdm_dep *cd; - int ret = 0; + int ret; if (!clkdm1 || !clkdm2) return -EINVAL; - cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); + cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); if (IS_ERR(cd)) - ret = PTR_ERR(cd); + return PTR_ERR(cd); - if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep) - ret = -EINVAL; - - if (ret) { - pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n", - clkdm1->name, clkdm2->name); - return ret; - } - - if (atomic_inc_return(&cd->sleepdep_usecount) == 1) { - pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n", - clkdm1->name, clkdm2->name); - - ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2); - } + pwrdm_lock(cd->clkdm->pwrdm.ptr); + ret = _clkdm_add_sleepdep(clkdm1, clkdm2); + pwrdm_unlock(cd->clkdm->pwrdm.ptr); return ret; } @@ -643,30 +723,18 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) { struct clkdm_dep *cd; - int ret = 0; + int ret; if (!clkdm1 || !clkdm2) return -EINVAL; - cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); + cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); if (IS_ERR(cd)) - ret = PTR_ERR(cd); + return PTR_ERR(cd); - if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep) - ret = -EINVAL; - - if (ret) { - pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n", - clkdm1->name, clkdm2->name); - return ret; - } - - if (atomic_dec_return(&cd->sleepdep_usecount) == 0) { - pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n", - clkdm1->name, clkdm2->name); - - ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2); - } + pwrdm_lock(cd->clkdm->pwrdm.ptr); + ret = _clkdm_del_sleepdep(clkdm1, clkdm2); + pwrdm_unlock(cd->clkdm->pwrdm.ptr); return ret; } @@ -708,7 +776,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) return ret; } - /* XXX It's faster to return the atomic sleepdep_usecount */ + /* XXX It's faster to return the sleepdep_usecount */ return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2); } @@ -734,18 +802,17 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) } /** - * clkdm_sleep - force clockdomain sleep transition + * clkdm_sleep_nolock - force clockdomain sleep transition (lockless) * @clkdm: struct clockdomain * * * Instruct the CM to force a sleep transition on the specified - * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if - * clockdomain does not support software-initiated sleep; 0 upon - * success. + * clockdomain @clkdm. Only for use by the powerdomain code. Returns + * -EINVAL if @clkdm is NULL or if clockdomain does not support + * software-initiated sleep; 0 upon success. */ -int clkdm_sleep(struct clockdomain *clkdm) +int clkdm_sleep_nolock(struct clockdomain *clkdm) { int ret; - unsigned long flags; if (!clkdm) return -EINVAL; @@ -761,26 +828,45 @@ int clkdm_sleep(struct clockdomain *clkdm) pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name); - spin_lock_irqsave(&clkdm->lock, flags); clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; ret = arch_clkdm->clkdm_sleep(clkdm); - spin_unlock_irqrestore(&clkdm->lock, flags); + ret |= pwrdm_state_switch_nolock(clkdm->pwrdm.ptr); + return ret; } /** - * clkdm_wakeup - force clockdomain wakeup transition + * clkdm_sleep - force clockdomain sleep transition * @clkdm: struct clockdomain * * - * Instruct the CM to force a wakeup transition on the specified - * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if the - * clockdomain does not support software-controlled wakeup; 0 upon + * Instruct the CM to force a sleep transition on the specified + * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if + * clockdomain does not support software-initiated sleep; 0 upon * success. */ -int clkdm_wakeup(struct clockdomain *clkdm) +int clkdm_sleep(struct clockdomain *clkdm) +{ + int ret; + + pwrdm_lock(clkdm->pwrdm.ptr); + ret = clkdm_sleep_nolock(clkdm); + pwrdm_unlock(clkdm->pwrdm.ptr); + + return ret; +} + +/** + * clkdm_wakeup_nolock - force clockdomain wakeup transition (lockless) + * @clkdm: struct clockdomain * + * + * Instruct the CM to force a wakeup transition on the specified + * clockdomain @clkdm. Only for use by the powerdomain code. Returns + * -EINVAL if @clkdm is NULL or if the clockdomain does not support + * software-controlled wakeup; 0 upon success. + */ +int clkdm_wakeup_nolock(struct clockdomain *clkdm) { int ret; - unsigned long flags; if (!clkdm) return -EINVAL; @@ -796,28 +882,46 @@ int clkdm_wakeup(struct clockdomain *clkdm) pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name); - spin_lock_irqsave(&clkdm->lock, flags); clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; ret = arch_clkdm->clkdm_wakeup(clkdm); - ret |= pwrdm_state_switch(clkdm->pwrdm.ptr); - spin_unlock_irqrestore(&clkdm->lock, flags); + ret |= pwrdm_state_switch_nolock(clkdm->pwrdm.ptr); + return ret; } /** - * clkdm_allow_idle - enable hwsup idle transitions for clkdm + * clkdm_wakeup - force clockdomain wakeup transition * @clkdm: struct clockdomain * * - * Allow the hardware to automatically switch the clockdomain @clkdm into - * active or idle states, as needed by downstream clocks. If the + * Instruct the CM to force a wakeup transition on the specified + * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if the + * clockdomain does not support software-controlled wakeup; 0 upon + * success. + */ +int clkdm_wakeup(struct clockdomain *clkdm) +{ + int ret; + + pwrdm_lock(clkdm->pwrdm.ptr); + ret = clkdm_wakeup_nolock(clkdm); + pwrdm_unlock(clkdm->pwrdm.ptr); + + return ret; +} + +/** + * clkdm_allow_idle_nolock - enable hwsup idle transitions for clkdm + * @clkdm: struct clockdomain * + * + * Allow the hardware to automatically switch the clockdomain @clkdm + * into active or idle states, as needed by downstream clocks. If the * clockdomain has any downstream clocks enabled in the clock * framework, wkdep/sleepdep autodependencies are added; this is so - * device drivers can read and write to the device. No return value. + * device drivers can read and write to the device. Only for use by + * the powerdomain code. No return value. */ -void clkdm_allow_idle(struct clockdomain *clkdm) +void clkdm_allow_idle_nolock(struct clockdomain *clkdm) { - unsigned long flags; - if (!clkdm) return; @@ -833,11 +937,26 @@ void clkdm_allow_idle(struct clockdomain *clkdm) pr_debug("clockdomain: enabling automatic idle transitions for %s\n", clkdm->name); - spin_lock_irqsave(&clkdm->lock, flags); clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED; arch_clkdm->clkdm_allow_idle(clkdm); - pwrdm_state_switch(clkdm->pwrdm.ptr); - spin_unlock_irqrestore(&clkdm->lock, flags); + pwrdm_state_switch_nolock(clkdm->pwrdm.ptr); +} + +/** + * clkdm_allow_idle - enable hwsup idle transitions for clkdm + * @clkdm: struct clockdomain * + * + * Allow the hardware to automatically switch the clockdomain @clkdm into + * active or idle states, as needed by downstream clocks. If the + * clockdomain has any downstream clocks enabled in the clock + * framework, wkdep/sleepdep autodependencies are added; this is so + * device drivers can read and write to the device. No return value. + */ +void clkdm_allow_idle(struct clockdomain *clkdm) +{ + pwrdm_lock(clkdm->pwrdm.ptr); + clkdm_allow_idle_nolock(clkdm); + pwrdm_unlock(clkdm->pwrdm.ptr); } /** @@ -847,12 +966,11 @@ void clkdm_allow_idle(struct clockdomain *clkdm) * Prevent the hardware from automatically switching the clockdomain * @clkdm into inactive or idle states. If the clockdomain has * downstream clocks enabled in the clock framework, wkdep/sleepdep - * autodependencies are removed. No return value. + * autodependencies are removed. Only for use by the powerdomain + * code. No return value. */ -void clkdm_deny_idle(struct clockdomain *clkdm) +void clkdm_deny_idle_nolock(struct clockdomain *clkdm) { - unsigned long flags; - if (!clkdm) return; @@ -868,11 +986,25 @@ void clkdm_deny_idle(struct clockdomain *clkdm) pr_debug("clockdomain: disabling automatic idle transitions for %s\n", clkdm->name); - spin_lock_irqsave(&clkdm->lock, flags); clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; arch_clkdm->clkdm_deny_idle(clkdm); - pwrdm_state_switch(clkdm->pwrdm.ptr); - spin_unlock_irqrestore(&clkdm->lock, flags); + pwrdm_state_switch_nolock(clkdm->pwrdm.ptr); +} + +/** + * clkdm_deny_idle - disable hwsup idle transitions for clkdm + * @clkdm: struct clockdomain * + * + * Prevent the hardware from automatically switching the clockdomain + * @clkdm into inactive or idle states. If the clockdomain has + * downstream clocks enabled in the clock framework, wkdep/sleepdep + * autodependencies are removed. No return value. + */ +void clkdm_deny_idle(struct clockdomain *clkdm) +{ + pwrdm_lock(clkdm->pwrdm.ptr); + clkdm_deny_idle_nolock(clkdm); + pwrdm_unlock(clkdm->pwrdm.ptr); } /** @@ -889,14 +1021,11 @@ void clkdm_deny_idle(struct clockdomain *clkdm) bool clkdm_in_hwsup(struct clockdomain *clkdm) { bool ret; - unsigned long flags; if (!clkdm) return false; - spin_lock_irqsave(&clkdm->lock, flags); ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false; - spin_unlock_irqrestore(&clkdm->lock, flags); return ret; } @@ -918,30 +1047,91 @@ bool clkdm_missing_idle_reporting(struct clockdomain *clkdm) return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false; } +/* Public autodep handling functions (deprecated) */ + +/** + * clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable + * @clkdm: struct clockdomain * + * + * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm' + * in hardware-supervised mode. Meant to be called from clock framework + * when a clock inside clockdomain 'clkdm' is enabled. No return value. + * + * XXX autodeps are deprecated and should be removed at the earliest + * opportunity + */ +void clkdm_add_autodeps(struct clockdomain *clkdm) +{ + struct clkdm_autodep *autodep; + + if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS) + return; + + for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { + if (IS_ERR(autodep->clkdm.ptr)) + continue; + + pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n", + clkdm->name, autodep->clkdm.ptr->name); + + _clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr); + _clkdm_add_wkdep(clkdm, autodep->clkdm.ptr); + } +} + +/** + * clkdm_del_autodeps - remove auto sleepdeps/wkdeps from clkdm + * @clkdm: struct clockdomain * + * + * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm' + * in hardware-supervised mode. Meant to be called from clock framework + * when a clock inside clockdomain 'clkdm' is disabled. No return value. + * + * XXX autodeps are deprecated and should be removed at the earliest + * opportunity + */ +void clkdm_del_autodeps(struct clockdomain *clkdm) +{ + struct clkdm_autodep *autodep; + + if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS) + return; + + for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { + if (IS_ERR(autodep->clkdm.ptr)) + continue; + + pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n", + clkdm->name, autodep->clkdm.ptr->name); + + _clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr); + _clkdm_del_wkdep(clkdm, autodep->clkdm.ptr); + } +} + /* Clockdomain-to-clock/hwmod framework interface code */ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) { - unsigned long flags; - if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable) return -EINVAL; - spin_lock_irqsave(&clkdm->lock, flags); + pwrdm_lock(clkdm->pwrdm.ptr); /* * For arch's with no autodeps, clkcm_clk_enable * should be called for every clock instance or hwmod that is * enabled, so the clkdm can be force woken up. */ - if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps) { - spin_unlock_irqrestore(&clkdm->lock, flags); + clkdm->usecount++; + if (clkdm->usecount > 1 && autodeps) { + pwrdm_unlock(clkdm->pwrdm.ptr); return 0; } arch_clkdm->clkdm_clk_enable(clkdm); - pwrdm_state_switch(clkdm->pwrdm.ptr); - spin_unlock_irqrestore(&clkdm->lock, flags); + pwrdm_state_switch_nolock(clkdm->pwrdm.ptr); + pwrdm_unlock(clkdm->pwrdm.ptr); pr_debug("clockdomain: %s: enabled\n", clkdm->name); @@ -990,36 +1180,34 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) */ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) { - unsigned long flags; - if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; - spin_lock_irqsave(&clkdm->lock, flags); + pwrdm_lock(clkdm->pwrdm.ptr); /* corner case: disabling unused clocks */ - if ((__clk_get_enable_count(clk) == 0) && - (atomic_read(&clkdm->usecount) == 0)) + if ((__clk_get_enable_count(clk) == 0) && clkdm->usecount == 0) goto ccd_exit; - if (atomic_read(&clkdm->usecount) == 0) { - spin_unlock_irqrestore(&clkdm->lock, flags); + if (clkdm->usecount == 0) { + pwrdm_unlock(clkdm->pwrdm.ptr); WARN_ON(1); /* underflow */ return -ERANGE; } - if (atomic_dec_return(&clkdm->usecount) > 0) { - spin_unlock_irqrestore(&clkdm->lock, flags); + clkdm->usecount--; + if (clkdm->usecount > 0) { + pwrdm_unlock(clkdm->pwrdm.ptr); return 0; } arch_clkdm->clkdm_clk_disable(clkdm); - pwrdm_state_switch(clkdm->pwrdm.ptr); + pwrdm_state_switch_nolock(clkdm->pwrdm.ptr); pr_debug("clockdomain: %s: disabled\n", clkdm->name); ccd_exit: - spin_unlock_irqrestore(&clkdm->lock, flags); + pwrdm_unlock(clkdm->pwrdm.ptr); return 0; } @@ -1072,8 +1260,6 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh) */ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) { - unsigned long flags; - /* The clkdm attribute does not exist yet prior OMAP4 */ if (cpu_is_omap24xx() || cpu_is_omap34xx()) return 0; @@ -1086,22 +1272,23 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; - spin_lock_irqsave(&clkdm->lock, flags); + pwrdm_lock(clkdm->pwrdm.ptr); - if (atomic_read(&clkdm->usecount) == 0) { - spin_unlock_irqrestore(&clkdm->lock, flags); + if (clkdm->usecount == 0) { + pwrdm_unlock(clkdm->pwrdm.ptr); WARN_ON(1); /* underflow */ return -ERANGE; } - if (atomic_dec_return(&clkdm->usecount) > 0) { - spin_unlock_irqrestore(&clkdm->lock, flags); + clkdm->usecount--; + if (clkdm->usecount > 0) { + pwrdm_unlock(clkdm->pwrdm.ptr); return 0; } arch_clkdm->clkdm_clk_disable(clkdm); - pwrdm_state_switch(clkdm->pwrdm.ptr); - spin_unlock_irqrestore(&clkdm->lock, flags); + pwrdm_state_switch_nolock(clkdm->pwrdm.ptr); + pwrdm_unlock(clkdm->pwrdm.ptr); pr_debug("clockdomain: %s: disabled\n", clkdm->name); diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index bc42446..2da3765 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -15,7 +15,6 @@ #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H #include <linux/init.h> -#include <linux/spinlock.h> #include "powerdomain.h" #include "clock.h" @@ -92,8 +91,8 @@ struct clkdm_autodep { struct clkdm_dep { const char *clkdm_name; struct clockdomain *clkdm; - atomic_t wkdep_usecount; - atomic_t sleepdep_usecount; + s16 wkdep_usecount; + s16 sleepdep_usecount; }; /* Possible flags for struct clockdomain._flags */ @@ -137,9 +136,8 @@ struct clockdomain { const u16 clkdm_offs; struct clkdm_dep *wkdep_srcs; struct clkdm_dep *sleepdep_srcs; - atomic_t usecount; + int usecount; struct list_head node; - spinlock_t lock; }; /** @@ -196,12 +194,16 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); +void clkdm_allow_idle_nolock(struct clockdomain *clkdm); void clkdm_allow_idle(struct clockdomain *clkdm); +void clkdm_deny_idle_nolock(struct clockdomain *clkdm); void clkdm_deny_idle(struct clockdomain *clkdm); bool clkdm_in_hwsup(struct clockdomain *clkdm); bool clkdm_missing_idle_reporting(struct clockdomain *clkdm); +int clkdm_wakeup_nolock(struct clockdomain *clkdm); int clkdm_wakeup(struct clockdomain *clkdm); +int clkdm_sleep_nolock(struct clockdomain *clkdm); int clkdm_sleep(struct clockdomain *clkdm); int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); @@ -214,8 +216,9 @@ extern void __init omap243x_clockdomains_init(void); extern void __init omap3xxx_clockdomains_init(void); extern void __init am33xx_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void); -extern void _clkdm_add_autodeps(struct clockdomain *clkdm); -extern void _clkdm_del_autodeps(struct clockdomain *clkdm); + +extern void clkdm_add_autodeps(struct clockdomain *clkdm); +extern void clkdm_del_autodeps(struct clockdomain *clkdm); extern struct clkdm_ops omap2_clkdm_operations; extern struct clkdm_ops omap3_clkdm_operations; diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c index db65069..6774a53 100644 --- a/arch/arm/mach-omap2/cm2xxx.c +++ b/arch/arm/mach-omap2/cm2xxx.c @@ -273,9 +273,6 @@ int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm) { - if (atomic_read(&clkdm->usecount) > 0) - _clkdm_add_autodeps(clkdm); - omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); } @@ -284,9 +281,6 @@ static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm) { omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); - - if (atomic_read(&clkdm->usecount) > 0) - _clkdm_del_autodeps(clkdm); } static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm) @@ -298,18 +292,8 @@ static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm) hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); - - if (hwsup) { - /* Disable HW transitions when we are changing deps */ - omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - _clkdm_add_autodeps(clkdm); - omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - } else { - if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) - omap2xxx_clkdm_wakeup(clkdm); - } + if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) + omap2xxx_clkdm_wakeup(clkdm); return 0; } @@ -324,17 +308,8 @@ static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm) hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); - if (hwsup) { - /* Disable HW transitions when we are changing deps */ - omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - _clkdm_del_autodeps(clkdm); - omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - } else { - if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) - omap2xxx_clkdm_sleep(clkdm); - } + if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_SLEEP) + omap2xxx_clkdm_sleep(clkdm); return 0; } diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c index c2086f2..9061c30 100644 --- a/arch/arm/mach-omap2/cm3xxx.c +++ b/arch/arm/mach-omap2/cm3xxx.c @@ -186,7 +186,7 @@ static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) continue; /* only happens if data is erroneous */ mask |= 1 << cd->clkdm->dep_bit; - atomic_set(&cd->sleepdep_usecount, 0); + cd->sleepdep_usecount = 0; } omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, OMAP3430_CM_SLEEPDEP); @@ -209,8 +209,8 @@ static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm) static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm) { - if (atomic_read(&clkdm->usecount) > 0) - _clkdm_add_autodeps(clkdm); + if (clkdm->usecount > 0) + clkdm_add_autodeps(clkdm); omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); @@ -221,8 +221,8 @@ static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm) omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); - if (atomic_read(&clkdm->usecount) > 0) - _clkdm_del_autodeps(clkdm); + if (clkdm->usecount > 0) + clkdm_del_autodeps(clkdm); } static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm) @@ -250,7 +250,7 @@ static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm) /* Disable HW transitions when we are changing deps */ omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); - _clkdm_add_autodeps(clkdm); + clkdm_add_autodeps(clkdm); omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); } else { @@ -287,7 +287,7 @@ static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm) /* Disable HW transitions when we are changing deps */ omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); - _clkdm_del_autodeps(clkdm); + clkdm_del_autodeps(clkdm); omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, clkdm->clktrctrl_mask); } else { diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index 7f9a464..f0290f5 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -393,7 +393,7 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) continue; /* only happens if data is erroneous */ mask |= 1 << cd->clkdm->dep_bit; - atomic_set(&cd->wkdep_usecount, 0); + cd->wkdep_usecount = 0; } omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition, diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 22590db..80392fc 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -36,40 +36,66 @@ /* Mach specific information to be recorded in the C-state driver_data */ struct omap3_idle_statedata { - u32 mpu_state; - u32 core_state; + u8 mpu_state; + u8 core_state; + u8 per_min_state; + u8 flags; }; static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; +/* + * Possible flag bits for struct omap3_idle_statedata.flags: + * + * OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go + * inactive. This in turn prevents the MPU DPLL from entering autoidle + * mode, so wakeup latency is greatly reduced, at the cost of additional + * energy consumption. This also prevents the CORE clockdomain from + * entering idle. + */ +#define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE BIT(0) + +/* + * Prevent PER OFF if CORE is not in RETention or OFF as this would + * disable PER wakeups completely. + */ static struct omap3_idle_statedata omap3_idle_data[] = { { .mpu_state = PWRDM_POWER_ON, .core_state = PWRDM_POWER_ON, + /* In C1 do not allow PER state lower than CORE state */ + .per_min_state = PWRDM_POWER_ON, + .flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE, }, { .mpu_state = PWRDM_POWER_ON, .core_state = PWRDM_POWER_ON, + .per_min_state = PWRDM_POWER_RET, }, { .mpu_state = PWRDM_POWER_RET, .core_state = PWRDM_POWER_ON, + .per_min_state = PWRDM_POWER_RET, }, { .mpu_state = PWRDM_POWER_OFF, .core_state = PWRDM_POWER_ON, + .per_min_state = PWRDM_POWER_RET, }, { .mpu_state = PWRDM_POWER_RET, .core_state = PWRDM_POWER_RET, + .per_min_state = PWRDM_POWER_OFF, }, { .mpu_state = PWRDM_POWER_OFF, .core_state = PWRDM_POWER_RET, + .per_min_state = PWRDM_POWER_OFF, }, { .mpu_state = PWRDM_POWER_OFF, .core_state = PWRDM_POWER_OFF, + .per_min_state = PWRDM_POWER_OFF, }, }; @@ -80,27 +106,25 @@ static int __omap3_enter_idle(struct cpuidle_device *dev, int index) { struct omap3_idle_statedata *cx = &omap3_idle_data[index]; - u32 mpu_state = cx->mpu_state, core_state = cx->core_state; local_fiq_disable(); - pwrdm_set_next_pwrst(mpu_pd, mpu_state); - pwrdm_set_next_pwrst(core_pd, core_state); - if (omap_irq_pending() || need_resched()) goto return_sleep_time; /* Deny idle for C1 */ - if (index == 0) { + if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) { clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]); - clkdm_deny_idle(core_pd->pwrdm_clkdms[0]); + } else { + pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state); + pwrdm_set_next_pwrst(core_pd, cx->core_state); } /* * Call idle CPU PM enter notifier chain so that * VFP context is saved. */ - if (mpu_state == PWRDM_POWER_OFF) + if (cx->mpu_state == PWRDM_POWER_OFF) cpu_pm_enter(); /* Execute ARM wfi */ @@ -110,17 +134,15 @@ static int __omap3_enter_idle(struct cpuidle_device *dev, * Call idle CPU PM enter notifier chain to restore * VFP context. */ - if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF) + if (cx->mpu_state == PWRDM_POWER_OFF && + pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF) cpu_pm_exit(); /* Re-allow idle for C1 */ - if (index == 0) { + if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]); - clkdm_allow_idle(core_pd->pwrdm_clkdms[0]); - } return_sleep_time: - local_fiq_enable(); return index; @@ -185,7 +207,7 @@ static int next_valid_state(struct cpuidle_device *dev, * Start search from the next (lower) state. */ for (idx = index - 1; idx >= 0; idx--) { - cx = &omap3_idle_data[idx]; + cx = &omap3_idle_data[idx]; if ((cx->mpu_state >= mpu_deepest_state) && (cx->core_state >= core_deepest_state)) { next_index = idx; @@ -209,10 +231,9 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - int new_state_idx; - u32 core_next_state, per_next_state = 0, per_saved_state = 0; + int new_state_idx, ret; + u8 per_next_state, per_saved_state; struct omap3_idle_statedata *cx; - int ret; /* * Use only C1 if CAM is active. @@ -233,25 +254,13 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, /* Program PER state */ cx = &omap3_idle_data[new_state_idx]; - core_next_state = cx->core_state; - per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); - if (new_state_idx == 0) { - /* In C1 do not allow PER state lower than CORE state */ - if (per_next_state < core_next_state) - per_next_state = core_next_state; - } else { - /* - * Prevent PER OFF if CORE is not in RETention or OFF as this - * would disable PER wakeups completely. - */ - if ((per_next_state == PWRDM_POWER_OFF) && - (core_next_state > PWRDM_POWER_RET)) - per_next_state = PWRDM_POWER_RET; - } - /* Are we changing PER target state? */ - if (per_next_state != per_saved_state) + per_next_state = pwrdm_read_next_pwrst(per_pd); + per_saved_state = per_next_state; + if (per_next_state < cx->per_min_state) { + per_next_state = cx->per_min_state; pwrdm_set_next_pwrst(per_pd, per_next_state); + } ret = omap3_enter_idle(dev, drv, new_state_idx); diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 5e304d0..d8a0cc3 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -61,8 +61,7 @@ static int __init omap3_l3_init(void) if (!oh) pr_err("could not look up %s\n", oh_name); - pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0, - NULL, 0, 0); + pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0); WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); @@ -96,8 +95,7 @@ static int __init omap4_l3_init(void) pr_err("could not look up %s\n", oh_name); } - pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, - 0, NULL, 0, 0); + pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, 0); WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); @@ -273,7 +271,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data keypad_data = sdp4430_keypad_data; pdev = omap_device_build(name, id, oh, keypad_data, - sizeof(struct omap4_keypad_platform_data), NULL, 0, 0); + sizeof(struct omap4_keypad_platform_data)); if (IS_ERR(pdev)) { WARN(1, "Can't build omap_device for %s:%s.\n", @@ -297,7 +295,7 @@ static inline void __init omap_init_mbox(void) return; } - pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0); + pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0); WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n", __func__, PTR_ERR(pdev)); } @@ -337,7 +335,7 @@ static void __init omap_init_mcpdm(void) return; } - pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0); + pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0); WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n"); } #else @@ -358,7 +356,7 @@ static void __init omap_init_dmic(void) return; } - pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0); + pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0); WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n"); } #else @@ -384,8 +382,7 @@ static void __init omap_init_hdmi_audio(void) return; } - pdev = omap_device_build("omap-hdmi-audio-dai", - -1, oh, NULL, 0, NULL, 0, 0); + pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0, 0); WARN(IS_ERR(pdev), "Can't build omap_device for omap-hdmi-audio-dai.\n"); @@ -429,8 +426,7 @@ static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused) } spi_num++; - pdev = omap_device_build(name, spi_num, oh, pdata, - sizeof(*pdata), NULL, 0, 0); + pdev = omap_device_build(name, spi_num, oh, pdata, sizeof(*pdata)); WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n", name, oh->name); kfree(pdata); @@ -460,7 +456,7 @@ static void omap_init_rng(void) if (!oh) return; - pdev = omap_device_build("omap_rng", -1, oh, NULL, 0, NULL, 0, 0); + pdev = omap_device_build("omap_rng", -1, oh, NULL, 0); WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n"); } @@ -639,7 +635,7 @@ static int count_ocp2scp_devices(struct omap_ocp2scp_dev *ocp2scp_dev) return cnt; } -static void omap_init_ocp2scp(void) +static void __init omap_init_ocp2scp(void) { struct omap_hwmod *oh; struct platform_device *pdev; @@ -689,8 +685,7 @@ static void omap_init_ocp2scp(void) pdata->dev_cnt = dev_cnt; - pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata), NULL, - 0, false); + pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata)); if (IS_ERR(pdev)) { pr_err("Could not build omap_device for %s %s\n", name, oh_name); diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index cc75aaf..ff37be1 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -226,7 +226,7 @@ static struct platform_device *create_dss_pdev(const char *pdev_name, dev_set_name(&pdev->dev, "%s", pdev->name); ohs[0] = oh; - od = omap_device_alloc(pdev, ohs, 1, NULL, 0); + od = omap_device_alloc(pdev, ohs, 1); if (IS_ERR(od)) { pr_err("Could not alloc omap_device for %s\n", pdev_name); r = -ENOMEM; diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 612b982..491c5c8 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -248,7 +248,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) p->errata = configure_dma_errata(); - pdev = omap_device_build(name, 0, oh, p, sizeof(*p), NULL, 0, 0); + pdev = omap_device_build(name, 0, oh, p, sizeof(*p)); kfree(p); if (IS_ERR(pdev)) { pr_err("%s: Can't build omap_device for %s:%s.\n", diff --git a/arch/arm/mach-omap2/drm.c b/arch/arm/mach-omap2/drm.c index 4c7566c..4d8d1a5 100644 --- a/arch/arm/mach-omap2/drm.c +++ b/arch/arm/mach-omap2/drm.c @@ -25,6 +25,7 @@ #include <linux/dma-mapping.h> #include <linux/platform_data/omap_drm.h> +#include "soc.h" #include "omap_device.h" #include "omap_hwmod.h" @@ -50,13 +51,12 @@ static int __init omap_init_drm(void) oh = omap_hwmod_lookup("dmm"); if (oh) { - pdev = omap_device_build(oh->name, -1, oh, NULL, 0, NULL, 0, - false); + pdev = omap_device_build(oh->name, -1, oh, NULL, 0); WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", oh->name); } - platform_data.omaprev = GET_OMAP_REVISION(); + platform_data.omaprev = GET_OMAP_TYPE; return platform_device_register(&omap_drm_device); diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c index 399acab..482ade1 100644 --- a/arch/arm/mach-omap2/gpio.c +++ b/arch/arm/mach-omap2/gpio.c @@ -131,8 +131,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pwrdm = omap_hwmod_get_pwrdm(oh); pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm); - pdev = omap_device_build(name, id - 1, oh, pdata, - sizeof(*pdata), NULL, 0, false); + pdev = omap_device_build(name, id - 1, oh, pdata, sizeof(*pdata)); kfree(pdata); if (IS_ERR(pdev)) { diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 8033cb7..bc07833 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -1220,7 +1220,7 @@ static int __init omap_gpmc_init(void) return -ENODEV; } - pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0); + pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0); WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c index ab7bf18..b7aa8ba 100644 --- a/arch/arm/mach-omap2/hdq1w.c +++ b/arch/arm/mach-omap2/hdq1w.c @@ -87,7 +87,7 @@ static int __init omap_init_hdq(void) if (!oh) return 0; - pdev = omap_device_build(devname, id, oh, NULL, 0, NULL, 0, 0); + pdev = omap_device_build(devname, id, oh, NULL, 0); WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", devname, oh->name); diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 4a96433..2ef1f87 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -522,7 +522,7 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo, } dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); - od = omap_device_alloc(pdev, ohs, 1, NULL, 0); + od = omap_device_alloc(pdev, ohs, 1); if (IS_ERR(od)) { pr_err("Could not allocate od for %s\n", name); goto put_pdev; diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c index 1df9b5f..c368890 100644 --- a/arch/arm/mach-omap2/hwspinlock.c +++ b/arch/arm/mach-omap2/hwspinlock.c @@ -46,8 +46,7 @@ static int __init hwspinlocks_init(void) return -EINVAL; pdev = omap_device_build(dev_name, 0, oh, &omap_hwspinlock_pdata, - sizeof(struct hwspinlock_pdata), - NULL, 0, false); + sizeof(struct hwspinlock_pdata)); if (IS_ERR(pdev)) { pr_err("Can't build omap_device for %s:%s\n", dev_name, oh_name); diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c index b9074dd..c11a23f 100644 --- a/arch/arm/mach-omap2/i2c.c +++ b/arch/arm/mach-omap2/i2c.c @@ -178,8 +178,7 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata, if (cpu_is_omap34xx()) pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; pdev = omap_device_build(name, bus_id, oh, pdata, - sizeof(struct omap_i2c_bus_platform_data), - NULL, 0, 0); + sizeof(struct omap_i2c_bus_platform_data)); WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name); return PTR_RET(pdev); diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index df49f2a..4535804 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -101,7 +101,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) count++; } pdev = omap_device_build_ss(name, id, oh_device, count, pdata, - sizeof(*pdata), NULL, 0, false); + sizeof(*pdata)); kfree(pdata); if (IS_ERR(pdev)) { pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c index aafdd4c..c52d8b4 100644 --- a/arch/arm/mach-omap2/msdi.c +++ b/arch/arm/mach-omap2/msdi.c @@ -150,7 +150,7 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) return; } pdev = omap_device_build(dev_name, id, oh, mmc_data[0], - sizeof(struct omap_mmc_platform_data), NULL, 0, 0); + sizeof(struct omap_mmc_platform_data)); if (IS_ERR(pdev)) WARN(1, "Can'd build omap_device for %s:%s.\n", dev_name, oh->name); diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index 6da4f7a..f7f38c7 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -41,8 +41,7 @@ static int __init omap_iommu_dev_init(struct omap_hwmod *oh, void *unused) pdata->deassert_reset = omap_device_deassert_hardreset; } - pdev = omap_device_build("omap-iommu", i, oh, pdata, sizeof(*pdata), - NULL, 0, 0); + pdev = omap_device_build("omap-iommu", i, oh, pdata, sizeof(*pdata)); kfree(pdata); diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index aac46bf..8bcb64b 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -87,37 +87,6 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr) } /* - * Set the CPUx powerdomain's previous power state - */ -static inline void set_cpu_next_pwrst(unsigned int cpu_id, - unsigned int power_state) -{ - struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); - - pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); -} - -/* - * Read CPU's previous power state - */ -static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id) -{ - struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); - - return pwrdm_read_prev_pwrst(pm_info->pwrdm); -} - -/* - * Clear the CPUx powerdomain's previous power state - */ -static inline void clear_cpu_prev_pwrst(unsigned int cpu_id) -{ - struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); - - pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); -} - -/* * Store the SCU power status value to scratchpad memory */ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state) @@ -230,6 +199,7 @@ static void save_l2x0_context(void) */ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) { + struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu); unsigned int save_state = 0; unsigned int wakeup_cpu; @@ -268,7 +238,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) save_state = 2; cpu_clear_prev_logic_pwrst(cpu); - set_cpu_next_pwrst(cpu, power_state); + pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume)); scu_pwrst_prepare(cpu, power_state); l2x0_pwrst_prepare(cpu, save_state); @@ -286,7 +256,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) * domain transition */ wakeup_cpu = smp_processor_id(); - set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON); + pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); pwrdm_post_transition(NULL); @@ -300,8 +270,8 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) */ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) { - unsigned int cpu_state = 0; struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu); + unsigned int cpu_state = 0; if (omap_rev() == OMAP4430_REV_ES1_0) return -ENXIO; @@ -309,8 +279,8 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) if (power_state == PWRDM_POWER_OFF) cpu_state = 1; - clear_cpu_prev_pwrst(cpu); - set_cpu_next_pwrst(cpu, power_state); + pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); + pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup)); scu_pwrst_prepare(cpu, power_state); @@ -321,7 +291,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) */ omap4_finish_suspend(cpu_state); - set_cpu_next_pwrst(cpu, PWRDM_POWER_ON); + pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); return 0; } diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 3616779..d972721 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -215,7 +215,7 @@ static void __init omap4_smp_init_cpus(void) * Currently we can't call ioremap here because * SoC detection won't work until after init_early. */ - scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE); + scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base()); BUG_ON(!scu_base); ncores = scu_get_core_count(scu_base); } else if (cpu_id == CPU_CORTEX_A15) { diff --git a/arch/arm/mach-omap2/omap44xx.h b/arch/arm/mach-omap2/omap44xx.h index 43b927b..8a515bb 100644 --- a/arch/arm/mach-omap2/omap44xx.h +++ b/arch/arm/mach-omap2/omap44xx.h @@ -40,7 +40,6 @@ #define OMAP44XX_GIC_DIST_BASE 0x48241000 #define OMAP44XX_GIC_CPU_BASE 0x48240100 #define OMAP44XX_IRQ_GIC_START 32 -#define OMAP44XX_SCU_BASE 0x48240000 #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 #define OMAP44XX_L2CACHE_BASE 0x48242000 #define OMAP44XX_WKUPGEN_BASE 0x48281000 diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index e065daa..6ee3ad3 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -17,68 +17,15 @@ * to control power management and interconnect properties of their * devices. * - * In the medium- to long-term, this code should either be - * a) implemented via arch-specific pointers in platform_data - * or - * b) implemented as a proper omap_bus/omap_device in Linux, no more - * platform_data func pointers + * In the medium- to long-term, this code should be implemented as a + * proper omap_bus/omap_device in Linux, no more platform_data func + * pointers * * - * Guidelines for usage by driver authors: - * - * 1. These functions are intended to be used by device drivers via - * function pointers in struct platform_data. As an example, - * omap_device_enable() should be passed to the driver as - * - * struct foo_driver_platform_data { - * ... - * int (*device_enable)(struct platform_device *pdev); - * ... - * } - * - * Note that the generic "device_enable" name is used, rather than - * "omap_device_enable". This is so other architectures can pass in their - * own enable/disable functions here. - * - * This should be populated during device setup: - * - * ... - * pdata->device_enable = omap_device_enable; - * ... - * - * 2. Drivers should first check to ensure the function pointer is not null - * before calling it, as in: - * - * if (pdata->device_enable) - * pdata->device_enable(pdev); - * - * This allows other architectures that don't use similar device_enable()/ - * device_shutdown() functions to execute normally. - * - * ... - * - * Suggested usage by device drivers: - * - * During device initialization: - * device_enable() - * - * During device idle: - * (save remaining device context if necessary) - * device_idle(); - * - * During device resume: - * device_enable(); - * (restore context if necessary) - * - * During device shutdown: - * device_shutdown() - * (device must be reinitialized at this point to use it again) - * */ #undef DEBUG #include <linux/kernel.h> -#include <linux/export.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/err.h> @@ -92,155 +39,8 @@ #include "omap_device.h" #include "omap_hwmod.h" -/* These parameters are passed to _omap_device_{de,}activate() */ -#define USE_WAKEUP_LAT 0 -#define IGNORE_WAKEUP_LAT 1 - -static int omap_early_device_register(struct platform_device *pdev); - -static struct omap_device_pm_latency omap_default_latency[] = { - { - .deactivate_func = omap_device_idle_hwmods, - .activate_func = omap_device_enable_hwmods, - .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, - } -}; - /* Private functions */ -/** - * _omap_device_activate - increase device readiness - * @od: struct omap_device * - * @ignore_lat: increase to latency target (0) or full readiness (1)? - * - * Increase readiness of omap_device @od (thus decreasing device - * wakeup latency, but consuming more power). If @ignore_lat is - * IGNORE_WAKEUP_LAT, make the omap_device fully active. Otherwise, - * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup - * latency is greater than the requested maximum wakeup latency, step - * backwards in the omap_device_pm_latency table to ensure the - * device's maximum wakeup latency is less than or equal to the - * requested maximum wakeup latency. Returns 0. - */ -static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) -{ - struct timespec a, b, c; - - dev_dbg(&od->pdev->dev, "omap_device: activating\n"); - - while (od->pm_lat_level > 0) { - struct omap_device_pm_latency *odpl; - unsigned long long act_lat = 0; - - od->pm_lat_level--; - - odpl = od->pm_lats + od->pm_lat_level; - - if (!ignore_lat && - (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit)) - break; - - read_persistent_clock(&a); - - /* XXX check return code */ - odpl->activate_func(od); - - read_persistent_clock(&b); - - c = timespec_sub(b, a); - act_lat = timespec_to_ns(&c); - - dev_dbg(&od->pdev->dev, - "omap_device: pm_lat %d: activate: elapsed time %llu nsec\n", - od->pm_lat_level, act_lat); - - if (act_lat > odpl->activate_lat) { - odpl->activate_lat_worst = act_lat; - if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { - odpl->activate_lat = act_lat; - dev_dbg(&od->pdev->dev, - "new worst case activate latency %d: %llu\n", - od->pm_lat_level, act_lat); - } else - dev_warn(&od->pdev->dev, - "activate latency %d higher than expected. (%llu > %d)\n", - od->pm_lat_level, act_lat, - odpl->activate_lat); - } - - od->dev_wakeup_lat -= odpl->activate_lat; - } - - return 0; -} - -/** - * _omap_device_deactivate - decrease device readiness - * @od: struct omap_device * - * @ignore_lat: decrease to latency target (0) or full inactivity (1)? - * - * Decrease readiness of omap_device @od (thus increasing device - * wakeup latency, but conserving power). If @ignore_lat is - * IGNORE_WAKEUP_LAT, make the omap_device fully inactive. Otherwise, - * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup - * latency is less than the requested maximum wakeup latency, step - * forwards in the omap_device_pm_latency table to ensure the device's - * maximum wakeup latency is less than or equal to the requested - * maximum wakeup latency. Returns 0. - */ -static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) -{ - struct timespec a, b, c; - - dev_dbg(&od->pdev->dev, "omap_device: deactivating\n"); - - while (od->pm_lat_level < od->pm_lats_cnt) { - struct omap_device_pm_latency *odpl; - unsigned long long deact_lat = 0; - - odpl = od->pm_lats + od->pm_lat_level; - - if (!ignore_lat && - ((od->dev_wakeup_lat + odpl->activate_lat) > - od->_dev_wakeup_lat_limit)) - break; - - read_persistent_clock(&a); - - /* XXX check return code */ - odpl->deactivate_func(od); - - read_persistent_clock(&b); - - c = timespec_sub(b, a); - deact_lat = timespec_to_ns(&c); - - dev_dbg(&od->pdev->dev, - "omap_device: pm_lat %d: deactivate: elapsed time %llu nsec\n", - od->pm_lat_level, deact_lat); - - if (deact_lat > odpl->deactivate_lat) { - odpl->deactivate_lat_worst = deact_lat; - if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) { - odpl->deactivate_lat = deact_lat; - dev_dbg(&od->pdev->dev, - "new worst case deactivate latency %d: %llu\n", - od->pm_lat_level, deact_lat); - } else - dev_warn(&od->pdev->dev, - "deactivate latency %d higher than expected. (%llu > %d)\n", - od->pm_lat_level, deact_lat, - odpl->deactivate_lat); - } - - od->dev_wakeup_lat += odpl->activate_lat; - - od->pm_lat_level++; - } - - return 0; -} - static void _add_clkdev(struct omap_device *od, const char *clk_alias, const char *clk_name) { @@ -315,9 +115,6 @@ static void _add_hwmod_clocks_clkdev(struct omap_device *od, * @oh: ptr to the single omap_hwmod that backs this omap_device * @pdata: platform_data ptr to associate with the platform_device * @pdata_len: amount of memory pointed to by @pdata - * @pm_lats: pointer to a omap_device_pm_latency array for this device - * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats - * @is_early_device: should the device be registered as an early device or not * * Function for building an omap_device already registered from device-tree * @@ -356,7 +153,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev) hwmods[i] = oh; } - od = omap_device_alloc(pdev, hwmods, oh_cnt, NULL, 0); + od = omap_device_alloc(pdev, hwmods, oh_cnt); if (!od) { dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n", oh_name); @@ -407,6 +204,39 @@ static int _omap_device_notifier_call(struct notifier_block *nb, return NOTIFY_DONE; } +/** + * _omap_device_enable_hwmods - call omap_hwmod_enable() on all hwmods + * @od: struct omap_device *od + * + * Enable all underlying hwmods. Returns 0. + */ +static int _omap_device_enable_hwmods(struct omap_device *od) +{ + int i; + + for (i = 0; i < od->hwmods_cnt; i++) + omap_hwmod_enable(od->hwmods[i]); + + /* XXX pass along return value here? */ + return 0; +} + +/** + * _omap_device_idle_hwmods - call omap_hwmod_idle() on all hwmods + * @od: struct omap_device *od + * + * Idle all underlying hwmods. Returns 0. + */ +static int _omap_device_idle_hwmods(struct omap_device *od) +{ + int i; + + for (i = 0; i < od->hwmods_cnt; i++) + omap_hwmod_idle(od->hwmods[i]); + + /* XXX pass along return value here? */ + return 0; +} /* Public functions for use by core code */ @@ -526,18 +356,14 @@ static int _od_fill_dma_resources(struct omap_device *od, * @oh: ptr to the single omap_hwmod that backs this omap_device * @pdata: platform_data ptr to associate with the platform_device * @pdata_len: amount of memory pointed to by @pdata - * @pm_lats: pointer to a omap_device_pm_latency array for this device - * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats * * Convenience function for allocating an omap_device structure and filling - * hwmods, resources and pm_latency attributes. + * hwmods, and resources. * * Returns an struct omap_device pointer or ERR_PTR() on error; */ struct omap_device *omap_device_alloc(struct platform_device *pdev, - struct omap_hwmod **ohs, int oh_cnt, - struct omap_device_pm_latency *pm_lats, - int pm_lats_cnt) + struct omap_hwmod **ohs, int oh_cnt) { int ret = -ENOMEM; struct omap_device *od; @@ -626,18 +452,6 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev, goto oda_exit3; have_everything: - if (!pm_lats) { - pm_lats = omap_default_latency; - pm_lats_cnt = ARRAY_SIZE(omap_default_latency); - } - - od->pm_lats_cnt = pm_lats_cnt; - od->pm_lats = kmemdup(pm_lats, - sizeof(struct omap_device_pm_latency) * pm_lats_cnt, - GFP_KERNEL); - if (!od->pm_lats) - goto oda_exit3; - pdev->archdata.od = od; for (i = 0; i < oh_cnt; i++) { @@ -663,7 +477,6 @@ void omap_device_delete(struct omap_device *od) return; od->pdev->archdata.od = NULL; - kfree(od->pm_lats); kfree(od->hwmods); kfree(od); } @@ -675,9 +488,6 @@ void omap_device_delete(struct omap_device *od) * @oh: ptr to the single omap_hwmod that backs this omap_device * @pdata: platform_data ptr to associate with the platform_device * @pdata_len: amount of memory pointed to by @pdata - * @pm_lats: pointer to a omap_device_pm_latency array for this device - * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats - * @is_early_device: should the device be registered as an early device or not * * Convenience function for building and registering a single * omap_device record, which in turn builds and registers a @@ -685,11 +495,10 @@ void omap_device_delete(struct omap_device *od) * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise, * passes along the return value of omap_device_build_ss(). */ -struct platform_device __init *omap_device_build(const char *pdev_name, int pdev_id, - struct omap_hwmod *oh, void *pdata, - int pdata_len, - struct omap_device_pm_latency *pm_lats, - int pm_lats_cnt, int is_early_device) +struct platform_device __init *omap_device_build(const char *pdev_name, + int pdev_id, + struct omap_hwmod *oh, + void *pdata, int pdata_len) { struct omap_hwmod *ohs[] = { oh }; @@ -697,8 +506,7 @@ struct platform_device __init *omap_device_build(const char *pdev_name, int pdev return ERR_PTR(-EINVAL); return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata, - pdata_len, pm_lats, pm_lats_cnt, - is_early_device); + pdata_len); } /** @@ -708,9 +516,6 @@ struct platform_device __init *omap_device_build(const char *pdev_name, int pdev * @oh: ptr to the single omap_hwmod that backs this omap_device * @pdata: platform_data ptr to associate with the platform_device * @pdata_len: amount of memory pointed to by @pdata - * @pm_lats: pointer to a omap_device_pm_latency array for this device - * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats - * @is_early_device: should the device be registered as an early device or not * * Convenience function for building and registering an omap_device * subsystem record. Subsystem records consist of multiple @@ -718,11 +523,11 @@ struct platform_device __init *omap_device_build(const char *pdev_name, int pdev * platform_device record. Returns an ERR_PTR() on error, or passes * along the return value of omap_device_register(). */ -struct platform_device __init *omap_device_build_ss(const char *pdev_name, int pdev_id, - struct omap_hwmod **ohs, int oh_cnt, - void *pdata, int pdata_len, - struct omap_device_pm_latency *pm_lats, - int pm_lats_cnt, int is_early_device) +struct platform_device __init *omap_device_build_ss(const char *pdev_name, + int pdev_id, + struct omap_hwmod **ohs, + int oh_cnt, void *pdata, + int pdata_len) { int ret = -ENOMEM; struct platform_device *pdev; @@ -746,7 +551,7 @@ struct platform_device __init *omap_device_build_ss(const char *pdev_name, int p else dev_set_name(&pdev->dev, "%s", pdev->name); - od = omap_device_alloc(pdev, ohs, oh_cnt, pm_lats, pm_lats_cnt); + od = omap_device_alloc(pdev, ohs, oh_cnt); if (IS_ERR(od)) goto odbs_exit1; @@ -754,10 +559,7 @@ struct platform_device __init *omap_device_build_ss(const char *pdev_name, int p if (ret) goto odbs_exit2; - if (is_early_device) - ret = omap_early_device_register(pdev); - else - ret = omap_device_register(pdev); + ret = omap_device_register(pdev); if (ret) goto odbs_exit2; @@ -774,24 +576,6 @@ odbs_exit: return ERR_PTR(ret); } -/** - * omap_early_device_register - register an omap_device as an early platform - * device. - * @od: struct omap_device * to register - * - * Register the omap_device structure. This currently just calls - * platform_early_add_device() on the underlying platform_device. - * Returns 0 by default. - */ -static int __init omap_early_device_register(struct platform_device *pdev) -{ - struct platform_device *devices[1]; - - devices[0] = pdev; - early_platform_add_devices(devices, 1); - return 0; -} - #ifdef CONFIG_PM_RUNTIME static int _od_runtime_suspend(struct device *dev) { @@ -902,10 +686,9 @@ int omap_device_register(struct platform_device *pdev) * to be accessible and ready to operate. This generally involves * enabling clocks, setting SYSCONFIG registers; and in the future may * involve remuxing pins. Device drivers should call this function - * (through platform_data function pointers) where they would normally - * enable clocks, etc. Returns -EINVAL if called when the omap_device - * is already enabled, or passes along the return value of - * _omap_device_activate(). + * indirectly via pm_runtime_get*(). Returns -EINVAL if called when + * the omap_device is already enabled, or passes along the return + * value of _omap_device_enable_hwmods(). */ int omap_device_enable(struct platform_device *pdev) { @@ -921,14 +704,8 @@ int omap_device_enable(struct platform_device *pdev) return -EINVAL; } - /* Enable everything if we're enabling this device from scratch */ - if (od->_state == OMAP_DEVICE_STATE_UNKNOWN) - od->pm_lat_level = od->pm_lats_cnt; - - ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT); + ret = _omap_device_enable_hwmods(od); - od->dev_wakeup_lat = 0; - od->_dev_wakeup_lat_limit = UINT_MAX; od->_state = OMAP_DEVICE_STATE_ENABLED; return ret; @@ -938,14 +715,10 @@ int omap_device_enable(struct platform_device *pdev) * omap_device_idle - idle an omap_device * @od: struct omap_device * to idle * - * Idle omap_device @od by calling as many .deactivate_func() entries - * in the omap_device's pm_lats table as is possible without exceeding - * the device's maximum wakeup latency limit, pm_lat_limit. Device - * drivers should call this function (through platform_data function - * pointers) where they would normally disable clocks after operations - * complete, etc.. Returns -EINVAL if the omap_device is not + * Idle omap_device @od. Device drivers call this function indirectly + * via pm_runtime_put*(). Returns -EINVAL if the omap_device is not * currently enabled, or passes along the return value of - * _omap_device_deactivate(). + * _omap_device_idle_hwmods(). */ int omap_device_idle(struct platform_device *pdev) { @@ -961,7 +734,7 @@ int omap_device_idle(struct platform_device *pdev) return -EINVAL; } - ret = _omap_device_deactivate(od, USE_WAKEUP_LAT); + ret = _omap_device_idle_hwmods(od); od->_state = OMAP_DEVICE_STATE_IDLE; @@ -969,42 +742,6 @@ int omap_device_idle(struct platform_device *pdev) } /** - * omap_device_shutdown - shut down an omap_device - * @od: struct omap_device * to shut down - * - * Shut down omap_device @od by calling all .deactivate_func() entries - * in the omap_device's pm_lats table and then shutting down all of - * the underlying omap_hwmods. Used when a device is being "removed" - * or a device driver is being unloaded. Returns -EINVAL if the - * omap_device is not currently enabled or idle, or passes along the - * return value of _omap_device_deactivate(). - */ -int omap_device_shutdown(struct platform_device *pdev) -{ - int ret, i; - struct omap_device *od; - - od = to_omap_device(pdev); - - if (od->_state != OMAP_DEVICE_STATE_ENABLED && - od->_state != OMAP_DEVICE_STATE_IDLE) { - dev_warn(&pdev->dev, - "omap_device: %s() called from invalid state %d\n", - __func__, od->_state); - return -EINVAL; - } - - ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT); - - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_shutdown(od->hwmods[i]); - - od->_state = OMAP_DEVICE_STATE_SHUTDOWN; - - return ret; -} - -/** * omap_device_assert_hardreset - set a device's hardreset line * @pdev: struct platform_device * to reset * @name: const char * name of the reset line @@ -1060,86 +797,6 @@ int omap_device_deassert_hardreset(struct platform_device *pdev, } /** - * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim - * @od: struct omap_device * - * - * When a device's maximum wakeup latency limit changes, call some of - * the .activate_func or .deactivate_func function pointers in the - * omap_device's pm_lats array to ensure that the device's maximum - * wakeup latency is less than or equal to the new latency limit. - * Intended to be called by OMAP PM code whenever a device's maximum - * wakeup latency limit changes (e.g., via - * omap_pm_set_dev_wakeup_lat()). Returns 0 if nothing needs to be - * done (e.g., if the omap_device is not currently idle, or if the - * wakeup latency is already current with the new limit) or passes - * along the return value of _omap_device_deactivate() or - * _omap_device_activate(). - */ -int omap_device_align_pm_lat(struct platform_device *pdev, - u32 new_wakeup_lat_limit) -{ - int ret = -EINVAL; - struct omap_device *od; - - od = to_omap_device(pdev); - - if (new_wakeup_lat_limit == od->dev_wakeup_lat) - return 0; - - od->_dev_wakeup_lat_limit = new_wakeup_lat_limit; - - if (od->_state != OMAP_DEVICE_STATE_IDLE) - return 0; - else if (new_wakeup_lat_limit > od->dev_wakeup_lat) - ret = _omap_device_deactivate(od, USE_WAKEUP_LAT); - else if (new_wakeup_lat_limit < od->dev_wakeup_lat) - ret = _omap_device_activate(od, USE_WAKEUP_LAT); - - return ret; -} - -/** - * omap_device_get_pwrdm - return the powerdomain * associated with @od - * @od: struct omap_device * - * - * Return the powerdomain associated with the first underlying - * omap_hwmod for this omap_device. Intended for use by core OMAP PM - * code. Returns NULL on error or a struct powerdomain * upon - * success. - */ -struct powerdomain *omap_device_get_pwrdm(struct omap_device *od) -{ - /* - * XXX Assumes that all omap_hwmod powerdomains are identical. - * This may not necessarily be true. There should be a sanity - * check in here to WARN() if any difference appears. - */ - if (!od->hwmods_cnt) - return NULL; - - return omap_hwmod_get_pwrdm(od->hwmods[0]); -} - -/** - * omap_device_get_mpu_rt_va - return the MPU's virtual addr for the hwmod base - * @od: struct omap_device * - * - * Return the MPU's virtual address for the base of the hwmod, from - * the ioremap() that the hwmod code does. Only valid if there is one - * hwmod associated with this device. Returns NULL if there are zero - * or more than one hwmods associated with this omap_device; - * otherwise, passes along the return value from - * omap_hwmod_get_mpu_rt_va(). - */ -void __iomem *omap_device_get_rt_va(struct omap_device *od) -{ - if (od->hwmods_cnt != 1) - return NULL; - - return omap_hwmod_get_mpu_rt_va(od->hwmods[0]); -} - -/** * omap_device_get_by_hwmod_name() - convert a hwmod name to * device pointer. * @oh_name: name of the hwmod device @@ -1173,82 +830,6 @@ struct device *omap_device_get_by_hwmod_name(const char *oh_name) return &oh->od->pdev->dev; } -EXPORT_SYMBOL(omap_device_get_by_hwmod_name); - -/* - * Public functions intended for use in omap_device_pm_latency - * .activate_func and .deactivate_func function pointers - */ - -/** - * omap_device_enable_hwmods - call omap_hwmod_enable() on all hwmods - * @od: struct omap_device *od - * - * Enable all underlying hwmods. Returns 0. - */ -int omap_device_enable_hwmods(struct omap_device *od) -{ - int i; - - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_enable(od->hwmods[i]); - - /* XXX pass along return value here? */ - return 0; -} - -/** - * omap_device_idle_hwmods - call omap_hwmod_idle() on all hwmods - * @od: struct omap_device *od - * - * Idle all underlying hwmods. Returns 0. - */ -int omap_device_idle_hwmods(struct omap_device *od) -{ - int i; - - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_idle(od->hwmods[i]); - - /* XXX pass along return value here? */ - return 0; -} - -/** - * omap_device_disable_clocks - disable all main and interface clocks - * @od: struct omap_device *od - * - * Disable the main functional clock and interface clock for all of the - * omap_hwmods associated with the omap_device. Returns 0. - */ -int omap_device_disable_clocks(struct omap_device *od) -{ - int i; - - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_disable_clocks(od->hwmods[i]); - - /* XXX pass along return value here? */ - return 0; -} - -/** - * omap_device_enable_clocks - enable all main and interface clocks - * @od: struct omap_device *od - * - * Enable the main functional clock and interface clock for all of the - * omap_hwmods associated with the omap_device. Returns 0. - */ -int omap_device_enable_clocks(struct omap_device *od) -{ - int i; - - for (i = 0; i < od->hwmods_cnt; i++) - omap_hwmod_enable_clocks(od->hwmods[i]); - - /* XXX pass along return value here? */ - return 0; -} static struct notifier_block platform_nb = { .notifier_call = _omap_device_notifier_call, diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h index 0933c59..044c31d 100644 --- a/arch/arm/mach-omap2/omap_device.h +++ b/arch/arm/mach-omap2/omap_device.h @@ -13,20 +13,12 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Eventually this type of functionality should either be - * a) implemented via arch-specific pointers in platform_device - * or - * b) implemented as a proper omap_bus/omap_device in Linux, no more - * platform_device + * This type of functionality should be implemented as a proper + * omap_bus/omap_device in Linux. * * omap_device differs from omap_hwmod in that it includes external * (e.g., board- and system-level) integration details. omap_hwmod * stores hardware data that is invariant for a given OMAP chip. - * - * To do: - * - GPIO integration - * - regulator integration - * */ #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H @@ -45,19 +37,14 @@ extern struct dev_pm_domain omap_device_pm_domain; #define OMAP_DEVICE_STATE_SHUTDOWN 3 /* omap_device.flags values */ -#define OMAP_DEVICE_SUSPENDED BIT(0) -#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1) +#define OMAP_DEVICE_SUSPENDED BIT(0) +#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1) /** * struct omap_device - omap_device wrapper for platform_devices * @pdev: platform_device * @hwmods: (one .. many per omap_device) * @hwmods_cnt: ARRAY_SIZE() of @hwmods - * @pm_lats: ptr to an omap_device_pm_latency table - * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats - * @pm_lat_level: array index of the last odpl entry executed - -1 if never - * @dev_wakeup_lat: dev wakeup latency in nanoseconds - * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM * @_state: one of OMAP_DEVICE_STATE_* (see above) * @flags: device flags * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h> @@ -71,12 +58,7 @@ extern struct dev_pm_domain omap_device_pm_domain; struct omap_device { struct platform_device *pdev; struct omap_hwmod **hwmods; - struct omap_device_pm_latency *pm_lats; - u32 dev_wakeup_lat; - u32 _dev_wakeup_lat_limit; unsigned long _driver_status; - u8 pm_lats_cnt; - s8 pm_lat_level; u8 hwmods_cnt; u8 _state; u8 flags; @@ -86,36 +68,25 @@ struct omap_device { int omap_device_enable(struct platform_device *pdev); int omap_device_idle(struct platform_device *pdev); -int omap_device_shutdown(struct platform_device *pdev); /* Core code interface */ struct platform_device *omap_device_build(const char *pdev_name, int pdev_id, - struct omap_hwmod *oh, void *pdata, - int pdata_len, - struct omap_device_pm_latency *pm_lats, - int pm_lats_cnt, int is_early_device); + struct omap_hwmod *oh, void *pdata, + int pdata_len); struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id, struct omap_hwmod **oh, int oh_cnt, - void *pdata, int pdata_len, - struct omap_device_pm_latency *pm_lats, - int pm_lats_cnt, int is_early_device); + void *pdata, int pdata_len); struct omap_device *omap_device_alloc(struct platform_device *pdev, - struct omap_hwmod **ohs, int oh_cnt, - struct omap_device_pm_latency *pm_lats, - int pm_lats_cnt); + struct omap_hwmod **ohs, int oh_cnt); void omap_device_delete(struct omap_device *od); int omap_device_register(struct platform_device *pdev); -void __iomem *omap_device_get_rt_va(struct omap_device *od); struct device *omap_device_get_by_hwmod_name(const char *oh_name); /* OMAP PM interface */ -int omap_device_align_pm_lat(struct platform_device *pdev, - u32 new_wakeup_lat_limit); -struct powerdomain *omap_device_get_pwrdm(struct omap_device *od); int omap_device_get_context_loss_count(struct platform_device *pdev); /* Other */ @@ -124,40 +95,6 @@ int omap_device_assert_hardreset(struct platform_device *pdev, const char *name); int omap_device_deassert_hardreset(struct platform_device *pdev, const char *name); -int omap_device_idle_hwmods(struct omap_device *od); -int omap_device_enable_hwmods(struct omap_device *od); - -int omap_device_disable_clocks(struct omap_device *od); -int omap_device_enable_clocks(struct omap_device *od); - -/* - * Entries should be kept in latency order ascending - * - * deact_lat is the maximum number of microseconds required to complete - * deactivate_func() at the device's slowest OPP. - * - * act_lat is the maximum number of microseconds required to complete - * activate_func() at the device's slowest OPP. - * - * This will result in some suboptimal power management decisions at fast - * OPPs, but avoids having to recompute all device power management decisions - * if the system shifts from a fast OPP to a slow OPP (in order to meet - * latency requirements). - * - * XXX should deactivate_func/activate_func() take platform_device pointers - * rather than omap_device pointers? - */ -struct omap_device_pm_latency { - u32 deactivate_lat; - u32 deactivate_lat_worst; - int (*deactivate_func)(struct omap_device *od); - u32 activate_lat; - u32 activate_lat_worst; - int (*activate_func)(struct omap_device *od); - u32 flags; -}; - -#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1) /* Get omap_device pointer from platform_device pointer */ static inline struct omap_device *to_omap_device(struct platform_device *pdev) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 4653efb..6804d47 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -139,6 +139,8 @@ #include <linux/slab.h> #include <linux/bootmem.h> +#include <asm/system_misc.h> + #include "clock.h" #include "omap_hwmod.h" @@ -2134,6 +2136,8 @@ static int _enable(struct omap_hwmod *oh) _enable_clocks(oh); if (soc_ops.enable_module) soc_ops.enable_module(oh); + if (oh->flags & HWMOD_BLOCK_WFI) + disable_hlt(); if (soc_ops.update_context_lost) soc_ops.update_context_lost(oh); @@ -2195,6 +2199,8 @@ static int _idle(struct omap_hwmod *oh) _idle_sysc(oh); _del_initiator_dep(oh, mpu_oh); + if (oh->flags & HWMOD_BLOCK_WFI) + enable_hlt(); if (soc_ops.disable_module) soc_ops.disable_module(oh); @@ -2303,6 +2309,8 @@ static int _shutdown(struct omap_hwmod *oh) if (oh->_state == _HWMOD_STATE_ENABLED) { _del_initiator_dep(oh, mpu_oh); /* XXX what about the other system initiators here? dma, dsp */ + if (oh->flags & HWMOD_BLOCK_WFI) + enable_hlt(); if (soc_ops.disable_module) soc_ops.disable_module(oh); _disable_clocks(oh); diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 3ae852a..80c00e7 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -451,6 +451,14 @@ struct omap_hwmod_omap4_prcm { * enabled. This prevents the hwmod code from being able to * enable and reset the IP block early. XXX Eventually it should * be possible to query the clock framework for this information. + * HWMOD_BLOCK_WFI: Some OMAP peripherals apparently don't work + * correctly if the MPU is allowed to go idle while the + * peripherals are active. This is apparently true for the I2C on + * OMAP2420, and also the EMAC on AM3517/3505. It's unlikely that + * this is really true -- we're probably not configuring something + * correctly, or this is being abused to deal with some PM latency + * issues -- but we're currently suffering from a shortage of + * folks who are able to track these issues down properly. */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -462,6 +470,7 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7) #define HWMOD_16BIT_REG (1 << 8) #define HWMOD_EXT_OPT_MAIN_CLK (1 << 9) +#define HWMOD_BLOCK_WFI (1 << 10) /* * omap_hwmod._int_flags definitions diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index b5efe58..6a764af 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -121,7 +121,12 @@ static struct omap_hwmod omap2420_i2c1_hwmod = { }, .class = &i2c_class, .dev_attr = &i2c_dev_attr, - .flags = HWMOD_16BIT_REG, + /* + * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state + * while a transfer is active seems to cause the I2C block to + * timeout. Why? Good question." + */ + .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI), }; /* I2C2 */ diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 129d508..a1849a8 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -616,7 +616,7 @@ static struct omap_hwmod omap44xx_dmic_hwmod = { .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_dmic_irqs, .sdma_reqs = omap44xx_dmic_sdma_reqs, - .main_clk = "dmic_fck", + .main_clk = "func_dmic_abe_gfclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, @@ -1161,7 +1161,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { .class = &omap44xx_gpio_hwmod_class, .clkdm_name = "l4_wkup_clkdm", .mpu_irqs = omap44xx_gpio1_irqs, - .main_clk = "gpio1_ick", + .main_clk = "l4_wkup_clk_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, @@ -1190,7 +1190,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio2_irqs, - .main_clk = "gpio2_ick", + .main_clk = "l4_div_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, @@ -1219,7 +1219,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio3_irqs, - .main_clk = "gpio3_ick", + .main_clk = "l4_div_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, @@ -1248,7 +1248,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio4_irqs, - .main_clk = "gpio4_ick", + .main_clk = "l4_div_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, @@ -1277,7 +1277,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio5_irqs, - .main_clk = "gpio5_ick", + .main_clk = "l4_div_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, @@ -1306,7 +1306,7 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { .clkdm_name = "l4_per_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio6_irqs, - .main_clk = "gpio6_ick", + .main_clk = "l4_div_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, @@ -1405,7 +1405,7 @@ static struct omap_hwmod omap44xx_gpu_hwmod = { .class = &omap44xx_gpu_hwmod_class, .clkdm_name = "l3_gfx_clkdm", .mpu_irqs = omap44xx_gpu_irqs, - .main_clk = "gpu_fck", + .main_clk = "sgx_clk_mux", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, @@ -1446,7 +1446,7 @@ static struct omap_hwmod omap44xx_hdq1w_hwmod = { .clkdm_name = "l4_per_clkdm", .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ .mpu_irqs = omap44xx_hdq1w_irqs, - .main_clk = "hdq1w_fck", + .main_clk = "func_12m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, @@ -1550,7 +1550,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_i2c1_irqs, .sdma_reqs = omap44xx_i2c1_sdma_reqs, - .main_clk = "i2c1_fck", + .main_clk = "func_96m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, @@ -1580,7 +1580,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_i2c2_irqs, .sdma_reqs = omap44xx_i2c2_sdma_reqs, - .main_clk = "i2c2_fck", + .main_clk = "func_96m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, @@ -1610,7 +1610,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_i2c3_irqs, .sdma_reqs = omap44xx_i2c3_sdma_reqs, - .main_clk = "i2c3_fck", + .main_clk = "func_96m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, @@ -1640,7 +1640,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_i2c4_irqs, .sdma_reqs = omap44xx_i2c4_sdma_reqs, - .main_clk = "i2c4_fck", + .main_clk = "func_96m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, @@ -1743,7 +1743,7 @@ static struct omap_hwmod omap44xx_iss_hwmod = { .clkdm_name = "iss_clkdm", .mpu_irqs = omap44xx_iss_irqs, .sdma_reqs = omap44xx_iss_sdma_reqs, - .main_clk = "iss_fck", + .main_clk = "ducati_clk_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, @@ -1785,7 +1785,7 @@ static struct omap_hwmod omap44xx_iva_hwmod = { .mpu_irqs = omap44xx_iva_irqs, .rst_lines = omap44xx_iva_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), - .main_clk = "iva_fck", + .main_clk = "dpll_iva_m5x2_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, @@ -1829,7 +1829,7 @@ static struct omap_hwmod omap44xx_kbd_hwmod = { .class = &omap44xx_kbd_hwmod_class, .clkdm_name = "l4_wkup_clkdm", .mpu_irqs = omap44xx_kbd_irqs, - .main_clk = "kbd_fck", + .main_clk = "sys_32k_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, @@ -1920,7 +1920,7 @@ static struct omap_hwmod omap44xx_mcasp_hwmod = { .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_mcasp_irqs, .sdma_reqs = omap44xx_mcasp_sdma_reqs, - .main_clk = "mcasp_fck", + .main_clk = "func_mcasp_abe_gfclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, @@ -1972,7 +1972,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_mcbsp1_irqs, .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, - .main_clk = "mcbsp1_fck", + .main_clk = "func_mcbsp1_gfclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, @@ -2007,7 +2007,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_mcbsp2_irqs, .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, - .main_clk = "mcbsp2_fck", + .main_clk = "func_mcbsp2_gfclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, @@ -2042,7 +2042,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_mcbsp3_irqs, .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, - .main_clk = "mcbsp3_fck", + .main_clk = "func_mcbsp3_gfclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, @@ -2077,7 +2077,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_mcbsp4_irqs, .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, - .main_clk = "mcbsp4_fck", + .main_clk = "per_mcbsp4_gfclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, @@ -2132,11 +2132,15 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { * currently reset very early during boot, before I2C is * available, so it doesn't seem that we have any choice in * the kernel other than to avoid resetting it. + * + * Also, McPDM needs to be configured to NO_IDLE mode when it + * is in used otherwise vital clocks will be gated which + * results 'slow motion' audio playback. */ - .flags = HWMOD_EXT_OPT_MAIN_CLK, + .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, .mpu_irqs = omap44xx_mcpdm_irqs, .sdma_reqs = omap44xx_mcpdm_sdma_reqs, - .main_clk = "mcpdm_fck", + .main_clk = "pad_clks_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, @@ -2197,7 +2201,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_mcspi1_irqs, .sdma_reqs = omap44xx_mcspi1_sdma_reqs, - .main_clk = "mcspi1_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, @@ -2233,7 +2237,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_mcspi2_irqs, .sdma_reqs = omap44xx_mcspi2_sdma_reqs, - .main_clk = "mcspi2_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, @@ -2269,7 +2273,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_mcspi3_irqs, .sdma_reqs = omap44xx_mcspi3_sdma_reqs, - .main_clk = "mcspi3_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, @@ -2303,7 +2307,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_mcspi4_irqs, .sdma_reqs = omap44xx_mcspi4_sdma_reqs, - .main_clk = "mcspi4_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, @@ -2359,7 +2363,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { .clkdm_name = "l3_init_clkdm", .mpu_irqs = omap44xx_mmc1_irqs, .sdma_reqs = omap44xx_mmc1_sdma_reqs, - .main_clk = "mmc1_fck", + .main_clk = "hsmmc1_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, @@ -2388,7 +2392,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { .clkdm_name = "l3_init_clkdm", .mpu_irqs = omap44xx_mmc2_irqs, .sdma_reqs = omap44xx_mmc2_sdma_reqs, - .main_clk = "mmc2_fck", + .main_clk = "hsmmc2_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, @@ -2416,7 +2420,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_mmc3_irqs, .sdma_reqs = omap44xx_mmc3_sdma_reqs, - .main_clk = "mmc3_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, @@ -2444,7 +2448,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_mmc4_irqs, .sdma_reqs = omap44xx_mmc4_sdma_reqs, - .main_clk = "mmc4_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, @@ -2472,7 +2476,7 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_mmc5_irqs, .sdma_reqs = omap44xx_mmc5_sdma_reqs, - .main_clk = "mmc5_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, @@ -2721,7 +2725,7 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { .name = "ocp2scp_usb_phy", .class = &omap44xx_ocp2scp_hwmod_class, .clkdm_name = "l3_init_clkdm", - .main_clk = "ocp2scp_usb_phy_phy_48m", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, @@ -3158,7 +3162,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { .clkdm_name = "l4_wkup_clkdm", .flags = HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_timer1_irqs, - .main_clk = "timer1_fck", + .main_clk = "dmt1_clk_mux", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, @@ -3181,7 +3185,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { .clkdm_name = "l4_per_clkdm", .flags = HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_timer2_irqs, - .main_clk = "timer2_fck", + .main_clk = "cm2_dm2_mux", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, @@ -3202,7 +3206,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { .class = &omap44xx_timer_hwmod_class, .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_timer3_irqs, - .main_clk = "timer3_fck", + .main_clk = "cm2_dm3_mux", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, @@ -3223,7 +3227,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { .class = &omap44xx_timer_hwmod_class, .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_timer4_irqs, - .main_clk = "timer4_fck", + .main_clk = "cm2_dm4_mux", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, @@ -3244,7 +3248,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { .class = &omap44xx_timer_hwmod_class, .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_timer5_irqs, - .main_clk = "timer5_fck", + .main_clk = "timer5_sync_mux", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, @@ -3266,8 +3270,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { .class = &omap44xx_timer_hwmod_class, .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_timer6_irqs, - - .main_clk = "timer6_fck", + .main_clk = "timer6_sync_mux", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, @@ -3289,7 +3292,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { .class = &omap44xx_timer_hwmod_class, .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_timer7_irqs, - .main_clk = "timer7_fck", + .main_clk = "timer7_sync_mux", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, @@ -3311,7 +3314,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { .class = &omap44xx_timer_hwmod_class, .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_timer8_irqs, - .main_clk = "timer8_fck", + .main_clk = "timer8_sync_mux", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, @@ -3333,7 +3336,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { .class = &omap44xx_timer_hwmod_class, .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_timer9_irqs, - .main_clk = "timer9_fck", + .main_clk = "cm2_dm9_mux", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, @@ -3356,7 +3359,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { .clkdm_name = "l4_per_clkdm", .flags = HWMOD_SET_DEFAULT_CLOCKACT, .mpu_irqs = omap44xx_timer10_irqs, - .main_clk = "timer10_fck", + .main_clk = "cm2_dm10_mux", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, @@ -3378,7 +3381,7 @@ static struct omap_hwmod omap44xx_timer11_hwmod = { .class = &omap44xx_timer_hwmod_class, .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_timer11_irqs, - .main_clk = "timer11_fck", + .main_clk = "cm2_dm11_mux", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, @@ -3429,7 +3432,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_uart1_irqs, .sdma_reqs = omap44xx_uart1_sdma_reqs, - .main_clk = "uart1_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, @@ -3457,7 +3460,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_uart2_irqs, .sdma_reqs = omap44xx_uart2_sdma_reqs, - .main_clk = "uart2_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, @@ -3486,7 +3489,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_uart3_irqs, .sdma_reqs = omap44xx_uart3_sdma_reqs, - .main_clk = "uart3_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, @@ -3514,7 +3517,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_uart4_irqs, .sdma_reqs = omap44xx_uart4_sdma_reqs, - .main_clk = "uart4_fck", + .main_clk = "func_48m_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, @@ -3793,7 +3796,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { .class = &omap44xx_wd_timer_hwmod_class, .clkdm_name = "l4_wkup_clkdm", .mpu_irqs = omap44xx_wd_timer2_irqs, - .main_clk = "wd_timer2_fck", + .main_clk = "sys_32k_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, @@ -3814,7 +3817,7 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { .class = &omap44xx_wd_timer_hwmod_class, .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_wd_timer3_irqs, - .main_clk = "wd_timer3_fck", + .main_clk = "sys_32k_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index e2c291f..6db89ae 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -83,10 +83,8 @@ static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user) strncmp(clkdm->name, "dpll", 4) == 0) return 0; - seq_printf(s, "%s->%s (%d)", clkdm->name, - clkdm->pwrdm.ptr->name, - atomic_read(&clkdm->usecount)); - seq_printf(s, "\n"); + seq_printf(s, "%s->%s (%d)\n", clkdm->name, clkdm->pwrdm.ptr->name, + clkdm->usecount); return 0; } diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index f4b3143..9a9be3c 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -32,8 +32,6 @@ #include "pm.h" #include "twl-common.h" -static struct omap_device_pm_latency *pm_lats; - /* * omap_pm_suspend: points to a function that does the SoC-specific * suspend work @@ -82,7 +80,7 @@ static int __init _init_omap_device(char *name) __func__, name)) return -ENODEV; - pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false); + pdev = omap_device_build(oh->name, 0, oh, NULL, 0); if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n", __func__, name)) return -ENODEV; @@ -108,80 +106,19 @@ static void __init omap2_init_processor_devices(void) } } -/* Types of sleep_switch used in omap_set_pwrdm_state */ -#define FORCEWAKEUP_SWITCH 0 -#define LOWPOWERSTATE_SWITCH 1 - int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) { + /* XXX The usecount test is racy */ if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) && !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)) clkdm_allow_idle(clkdm); else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && - atomic_read(&clkdm->usecount) == 0) + clkdm->usecount == 0) clkdm_sleep(clkdm); return 0; } /* - * This sets pwrdm state (other than mpu & core. Currently only ON & - * RET are supported. - */ -int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 pwrst) -{ - u8 curr_pwrst, next_pwrst; - int sleep_switch = -1, ret = 0, hwsup = 0; - - if (!pwrdm || IS_ERR(pwrdm)) - return -EINVAL; - - while (!(pwrdm->pwrsts & (1 << pwrst))) { - if (pwrst == PWRDM_POWER_OFF) - return ret; - pwrst--; - } - - next_pwrst = pwrdm_read_next_pwrst(pwrdm); - if (next_pwrst == pwrst) - return ret; - - curr_pwrst = pwrdm_read_pwrst(pwrdm); - if (curr_pwrst < PWRDM_POWER_ON) { - if ((curr_pwrst > pwrst) && - (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) { - sleep_switch = LOWPOWERSTATE_SWITCH; - } else { - hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]); - clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); - sleep_switch = FORCEWAKEUP_SWITCH; - } - } - - ret = pwrdm_set_next_pwrst(pwrdm, pwrst); - if (ret) - pr_err("%s: unable to set power state of powerdomain: %s\n", - __func__, pwrdm->name); - - switch (sleep_switch) { - case FORCEWAKEUP_SWITCH: - if (hwsup) - clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); - else - clkdm_sleep(pwrdm->pwrdm_clkdms[0]); - break; - case LOWPOWERSTATE_SWITCH: - pwrdm_set_lowpwrstchange(pwrdm); - pwrdm_wait_transition(pwrdm); - pwrdm_state_switch(pwrdm); - break; - } - - return ret; -} - - - -/* * This API is to be called during init to set the various voltage * domains to the voltage as per the opp table. Typically we boot up * at the nominal voltage. So this function finds out the rate of diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index c22503b..7bdd22a 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -33,7 +33,6 @@ static inline int omap4_idle_init(void) extern void *omap3_secure_ram_storage; extern void omap3_pm_off_mode_enable(int); extern void omap_sram_idle(void); -extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused); extern int (*omap_pm_suspend)(void); diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index c333fa6..b2a4df6 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -90,11 +90,7 @@ static int omap2_enter_full_retention(void) omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); - /* - * Set MPU powerdomain's next power state to RETENTION; - * preserve logic state during retention - */ - pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); + pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); /* Workaround to kill USB */ @@ -137,15 +133,10 @@ no_sleep: /* Mask future PRCM-to-MPU interrupts */ omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); - return 0; -} - -static int omap2_i2c_active(void) -{ - u32 l; + pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); + pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON); - l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK); + return 0; } static int sti_console_enabled; @@ -172,11 +163,6 @@ static int omap2_allow_mpu_retention(void) static void omap2_enter_mpu_retention(void) { - /* Putting MPU into the WFI state while a transfer is active - * seems to cause the I2C block to timeout. Why? Good question. */ - if (omap2_i2c_active()) - return; - /* The peripherals seem not to be able to wake up the MPU when * it is in retention mode. */ if (omap2_allow_mpu_retention()) { @@ -186,17 +172,16 @@ static void omap2_enter_mpu_retention(void) omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); /* Try to enter MPU retention */ - omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | - OMAP_LOGICRETSTATE_MASK, - MPU_MOD, OMAP2_PM_PWSTCTRL); + pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); + } else { /* Block MPU retention */ - - omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, - OMAP2_PM_PWSTCTRL); + pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); } omap2_sram_idle(); + + pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); } static int omap2_can_sleep(void) @@ -251,25 +236,17 @@ static void __init prcm_setup_regs(void) for (i = 0; i < num_mem_banks; i++) pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET); - /* Set CORE powerdomain's next power state to RETENTION */ - pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); + pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET); - /* - * Set MPU powerdomain's next power state to RETENTION; - * preserve logic state during retention - */ pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); - pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); /* Force-power down DSP, GFX powerdomains */ pwrdm = clkdm_get_pwrdm(dsp_clkdm); pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); - clkdm_sleep(dsp_clkdm); pwrdm = clkdm_get_pwrdm(gfx_clkdm); pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); - clkdm_sleep(gfx_clkdm); /* Enable hardware-supervised idle for all clkdms */ clkdm_for_each(omap_pm_clkdms_setup, NULL); diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c index eb78ae7..0ef4d6a 100644 --- a/arch/arm/mach-omap2/pmu.c +++ b/arch/arm/mach-omap2/pmu.c @@ -48,8 +48,7 @@ static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[]) } } - omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0, - NULL, 0, 0); + omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0); WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n", dev_name); diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index dea62a9..8e61d80 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -19,6 +19,7 @@ #include <linux/list.h> #include <linux/errno.h> #include <linux/string.h> +#include <linux/spinlock.h> #include <trace/events/power.h> #include "cm2xxx_3xxx.h" @@ -42,6 +43,16 @@ enum { PWRDM_STATE_PREV, }; +/* + * Types of sleep_switch used internally in omap_set_pwrdm_state() + * and its associated static functions + * + * XXX Better documentation is needed here + */ +#define ALREADYACTIVE_SWITCH 0 +#define FORCEWAKEUP_SWITCH 1 +#define LOWPOWERSTATE_SWITCH 2 +#define ERROR_SWITCH 3 /* pwrdm_list contains all registered struct powerdomains */ static LIST_HEAD(pwrdm_list); @@ -101,6 +112,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm) pwrdm->voltdm.ptr = voltdm; INIT_LIST_HEAD(&pwrdm->voltdm_node); voltdm_add_pwrdm(voltdm, pwrdm); + spin_lock_init(&pwrdm->_lock); list_add(&pwrdm->node, &pwrdm_list); @@ -112,7 +124,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm) for (i = 0; i < pwrdm->banks; i++) pwrdm->ret_mem_off_counter[i] = 0; - pwrdm_wait_transition(pwrdm); + arch_pwrdm->pwrdm_wait_transition(pwrdm); pwrdm->state = pwrdm_read_pwrst(pwrdm); pwrdm->state_counter[pwrdm->state] = 1; @@ -143,7 +155,7 @@ static void _update_logic_membank_counters(struct powerdomain *pwrdm) static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) { - int prev, state, trace_state = 0; + int prev, next, state, trace_state = 0; if (pwrdm == NULL) return -EINVAL; @@ -164,9 +176,10 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) * If the power domain did not hit the desired state, * generate a trace event with both the desired and hit states */ - if (state != prev) { + next = pwrdm_read_next_pwrst(pwrdm); + if (next != prev) { trace_state = (PWRDM_TRACE_STATES_FLAG | - ((state & OMAP_POWERSTATE_MASK) << 8) | + ((next & OMAP_POWERSTATE_MASK) << 8) | ((prev & OMAP_POWERSTATE_MASK) << 0)); trace_power_domain_target(pwrdm->name, trace_state, smp_processor_id()); @@ -199,6 +212,80 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused) return 0; } +/** + * _pwrdm_save_clkdm_state_and_activate - prepare for power state change + * @pwrdm: struct powerdomain * to operate on + * @curr_pwrst: current power state of @pwrdm + * @pwrst: power state to switch to + * @hwsup: ptr to a bool to return whether the clkdm is hardware-supervised + * + * Determine whether the powerdomain needs to be turned on before + * attempting to switch power states. Called by + * omap_set_pwrdm_state(). NOTE that if the powerdomain contains + * multiple clockdomains, this code assumes that the first clockdomain + * supports software-supervised wakeup mode - potentially a problem. + * Returns the power state switch mode currently in use (see the + * "Types of sleep_switch" comment above). + */ +static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm, + u8 curr_pwrst, u8 pwrst, + bool *hwsup) +{ + u8 sleep_switch; + + if (curr_pwrst < 0) { + WARN_ON(1); + sleep_switch = ERROR_SWITCH; + } else if (curr_pwrst < PWRDM_POWER_ON) { + if (curr_pwrst > pwrst && + pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE && + arch_pwrdm->pwrdm_set_lowpwrstchange) { + sleep_switch = LOWPOWERSTATE_SWITCH; + } else { + *hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]); + clkdm_wakeup_nolock(pwrdm->pwrdm_clkdms[0]); + sleep_switch = FORCEWAKEUP_SWITCH; + } + } else { + sleep_switch = ALREADYACTIVE_SWITCH; + } + + return sleep_switch; +} + +/** + * _pwrdm_restore_clkdm_state - restore the clkdm hwsup state after pwrst change + * @pwrdm: struct powerdomain * to operate on + * @sleep_switch: return value from _pwrdm_save_clkdm_state_and_activate() + * @hwsup: should @pwrdm's first clockdomain be set to hardware-supervised mode? + * + * Restore the clockdomain state perturbed by + * _pwrdm_save_clkdm_state_and_activate(), and call the power state + * bookkeeping code. Called by omap_set_pwrdm_state(). NOTE that if + * the powerdomain contains multiple clockdomains, this assumes that + * the first associated clockdomain supports either + * hardware-supervised idle control in the register, or + * software-supervised sleep. No return value. + */ +static void _pwrdm_restore_clkdm_state(struct powerdomain *pwrdm, + u8 sleep_switch, bool hwsup) +{ + switch (sleep_switch) { + case FORCEWAKEUP_SWITCH: + if (hwsup) + clkdm_allow_idle_nolock(pwrdm->pwrdm_clkdms[0]); + else + clkdm_sleep_nolock(pwrdm->pwrdm_clkdms[0]); + break; + case LOWPOWERSTATE_SWITCH: + if (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE && + arch_pwrdm->pwrdm_set_lowpwrstchange) + arch_pwrdm->pwrdm_set_lowpwrstchange(pwrdm); + pwrdm_state_switch_nolock(pwrdm); + break; + } +} + /* Public functions */ /** @@ -275,6 +362,30 @@ int pwrdm_complete_init(void) } /** + * pwrdm_lock - acquire a Linux spinlock on a powerdomain + * @pwrdm: struct powerdomain * to lock + * + * Acquire the powerdomain spinlock on @pwrdm. No return value. + */ +void pwrdm_lock(struct powerdomain *pwrdm) + __acquires(&pwrdm->_lock) +{ + spin_lock_irqsave(&pwrdm->_lock, pwrdm->_lock_flags); +} + +/** + * pwrdm_unlock - release a Linux spinlock on a powerdomain + * @pwrdm: struct powerdomain * to unlock + * + * Release the powerdomain spinlock on @pwrdm. No return value. + */ +void pwrdm_unlock(struct powerdomain *pwrdm) + __releases(&pwrdm->_lock) +{ + spin_unlock_irqrestore(&pwrdm->_lock, pwrdm->_lock_flags); +} + +/** * pwrdm_lookup - look up a powerdomain by name, return a pointer * @name: name of powerdomain * @@ -920,65 +1031,27 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm) return (pwrdm && pwrdm->flags & PWRDM_HAS_HDWR_SAR) ? 1 : 0; } -/** - * pwrdm_set_lowpwrstchange - Request a low power state change - * @pwrdm: struct powerdomain * - * - * Allows a powerdomain to transtion to a lower power sleep state - * from an existing sleep state without waking up the powerdomain. - * Returns -EINVAL if the powerdomain pointer is null or if the - * powerdomain does not support LOWPOWERSTATECHANGE, or returns 0 - * upon success. - */ -int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) -{ - int ret = -EINVAL; - - if (!pwrdm) - return -EINVAL; - - if (!(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) - return -EINVAL; - - pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n", - pwrdm->name); - - if (arch_pwrdm && arch_pwrdm->pwrdm_set_lowpwrstchange) - ret = arch_pwrdm->pwrdm_set_lowpwrstchange(pwrdm); - - return ret; -} - -/** - * pwrdm_wait_transition - wait for powerdomain power transition to finish - * @pwrdm: struct powerdomain * to wait for - * - * If the powerdomain @pwrdm is in the process of a state transition, - * spin until it completes the power transition, or until an iteration - * bailout value is reached. Returns -EINVAL if the powerdomain - * pointer is null, -EAGAIN if the bailout value was reached, or - * returns 0 upon success. - */ -int pwrdm_wait_transition(struct powerdomain *pwrdm) +int pwrdm_state_switch_nolock(struct powerdomain *pwrdm) { - int ret = -EINVAL; + int ret; - if (!pwrdm) + if (!pwrdm || !arch_pwrdm) return -EINVAL; - if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition) - ret = arch_pwrdm->pwrdm_wait_transition(pwrdm); + ret = arch_pwrdm->pwrdm_wait_transition(pwrdm); + if (!ret) + ret = _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW); return ret; } -int pwrdm_state_switch(struct powerdomain *pwrdm) +int __deprecated pwrdm_state_switch(struct powerdomain *pwrdm) { int ret; - ret = pwrdm_wait_transition(pwrdm); - if (!ret) - ret = _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW); + pwrdm_lock(pwrdm); + ret = pwrdm_state_switch_nolock(pwrdm); + pwrdm_unlock(pwrdm); return ret; } @@ -1004,6 +1077,61 @@ int pwrdm_post_transition(struct powerdomain *pwrdm) } /** + * omap_set_pwrdm_state - change a powerdomain's current power state + * @pwrdm: struct powerdomain * to change the power state of + * @pwrst: power state to change to + * + * Change the current hardware power state of the powerdomain + * represented by @pwrdm to the power state represented by @pwrst. + * Returns -EINVAL if @pwrdm is null or invalid or if the + * powerdomain's current power state could not be read, or returns 0 + * upon success or if @pwrdm does not support @pwrst or any + * lower-power state. XXX Should not return 0 if the @pwrdm does not + * support @pwrst or any lower-power state: this should be an error. + */ +int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) +{ + u8 curr_pwrst, next_pwrst, sleep_switch; + int ret = 0; + bool hwsup = false; + + if (!pwrdm || IS_ERR(pwrdm)) + return -EINVAL; + + while (!(pwrdm->pwrsts & (1 << pwrst))) { + if (pwrst == PWRDM_POWER_OFF) + return ret; + pwrst--; + } + + pwrdm_lock(pwrdm); + + curr_pwrst = pwrdm_read_pwrst(pwrdm); + next_pwrst = pwrdm_read_next_pwrst(pwrdm); + if (curr_pwrst == pwrst && next_pwrst == pwrst) + goto osps_out; + + sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst, + pwrst, &hwsup); + if (sleep_switch == ERROR_SWITCH) { + ret = -EINVAL; + goto osps_out; + } + + ret = pwrdm_set_next_pwrst(pwrdm, pwrst); + if (ret) + pr_err("%s: unable to set power state of powerdomain: %s\n", + __func__, pwrdm->name); + + _pwrdm_restore_clkdm_state(pwrdm, sleep_switch, hwsup); + +osps_out: + pwrdm_unlock(pwrdm); + + return ret; +} + +/** * pwrdm_get_context_loss_count - get powerdomain's context loss count * @pwrdm: struct powerdomain * to wait for * diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 5277d56eb..140c360 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -19,8 +19,7 @@ #include <linux/types.h> #include <linux/list.h> - -#include <linux/atomic.h> +#include <linux/spinlock.h> #include "voltage.h" @@ -44,18 +43,20 @@ #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON) -/* Powerdomain flags */ -#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ -#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits - * in MEM bank 1 position. This is - * true for OMAP3430 - */ -#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* - * support to transition from a - * sleep state to a lower sleep - * state without waking up the - * powerdomain - */ +/* + * Powerdomain flags (struct powerdomain.flags) + * + * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support + * + * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM + * bank 1 position. This is true for OMAP3430 + * + * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state + * to a lower sleep state without waking up the powerdomain + */ +#define PWRDM_HAS_HDWR_SAR BIT(0) +#define PWRDM_HAS_MPU_QUIRK BIT(1) +#define PWRDM_HAS_LOWPOWERSTATECHANGE BIT(2) /* * Number of memory banks that are power-controllable. On OMAP4430, the @@ -103,6 +104,8 @@ struct powerdomain; * @state_counter: * @timer: * @state_timer: + * @_lock: spinlock used to serialize powerdomain and some clockdomain ops + * @_lock_flags: stored flags when @_lock is taken * * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. */ @@ -127,7 +130,8 @@ struct powerdomain { unsigned state_counter[PWRDM_MAX_PWRSTS]; unsigned ret_logic_off_counter; unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; - + spinlock_t _lock; + unsigned long _lock_flags; const u8 pwrstctrl_offs; const u8 pwrstst_offs; const u32 logicretstate_mask; @@ -162,6 +166,16 @@ struct powerdomain { * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep * @pwrdm_wait_transition: Wait for a pd state transition to complete + * + * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family + * chips, a powerdomain's power state is not allowed to directly + * transition from one low-power state (e.g., CSWR) to another + * low-power state (e.g., OFF) without first waking up the + * powerdomain. This wastes energy. So OMAP4 chips support the + * ability to transition a powerdomain power state directly from one + * low-power state to another. The function pointed to by + * @pwrdm_set_lowpwrstchange is intended to configure the OMAP4 + * hardware powerdomain state machine to enable this feature. */ struct pwrdm_ops { int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); @@ -225,15 +239,15 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); -int pwrdm_wait_transition(struct powerdomain *pwrdm); - +int pwrdm_state_switch_nolock(struct powerdomain *pwrdm); int pwrdm_state_switch(struct powerdomain *pwrdm); int pwrdm_pre_transition(struct powerdomain *pwrdm); int pwrdm_post_transition(struct powerdomain *pwrdm); -int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); int pwrdm_get_context_loss_count(struct powerdomain *pwrdm); bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm); +extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state); + extern void omap242x_powerdomains_init(void); extern void omap243x_powerdomains_init(void); extern void omap3xxx_powerdomains_init(void); @@ -253,5 +267,7 @@ extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); extern struct powerdomain wkup_omap2_pwrdm; extern struct powerdomain gfx_omap2_pwrdm; +extern void pwrdm_lock(struct powerdomain *pwrdm); +extern void pwrdm_unlock(struct powerdomain *pwrdm); #endif diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c index d3a5399..7b946f1 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c @@ -54,12 +54,12 @@ struct powerdomain gfx_omap2_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; struct powerdomain wkup_omap2_pwrdm = { .name = "wkup_pwrdm", .prcm_offs = WKUP_MOD, .pwrsts = PWRSTS_ON, - .voltdm = { .name = "wakeup" }, + .voltdm = { .name = "wakeup" }, }; diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c index ba520d4..578eef8 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c @@ -38,7 +38,7 @@ static struct powerdomain dsp_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain mpu_24xx_pwrdm = { @@ -53,13 +53,14 @@ static struct powerdomain mpu_24xx_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain core_24xx_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 3, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ @@ -71,7 +72,7 @@ static struct powerdomain core_24xx_pwrdm = { [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; @@ -93,7 +94,7 @@ static struct powerdomain mdm_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; /* diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index 8b23d23..f0e14e9 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -50,7 +50,7 @@ static struct powerdomain iva2_pwrdm = { [2] = PWRSTS_OFF_ON, [3] = PWRSTS_ON, }, - .voltdm = { .name = "mpu_iva" }, + .voltdm = { .name = "mpu_iva" }, }; static struct powerdomain mpu_3xxx_pwrdm = { @@ -66,7 +66,7 @@ static struct powerdomain mpu_3xxx_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_OFF_ON, }, - .voltdm = { .name = "mpu_iva" }, + .voltdm = { .name = "mpu_iva" }, }; static struct powerdomain mpu_am35x_pwrdm = { @@ -82,7 +82,7 @@ static struct powerdomain mpu_am35x_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, }, - .voltdm = { .name = "mpu_iva" }, + .voltdm = { .name = "mpu_iva" }, }; /* @@ -109,7 +109,7 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain core_3xxx_es3_1_pwrdm = { @@ -131,7 +131,7 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = { [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain core_am35x_pwrdm = { @@ -148,7 +148,7 @@ static struct powerdomain core_am35x_pwrdm = { [0] = PWRSTS_ON, /* MEM1ONSTATE */ [1] = PWRSTS_ON, /* MEM2ONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain dss_pwrdm = { @@ -163,7 +163,7 @@ static struct powerdomain dss_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain dss_am35x_pwrdm = { @@ -178,7 +178,7 @@ static struct powerdomain dss_am35x_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; /* @@ -199,7 +199,7 @@ static struct powerdomain sgx_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain sgx_am35x_pwrdm = { @@ -214,7 +214,7 @@ static struct powerdomain sgx_am35x_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain cam_pwrdm = { @@ -229,7 +229,7 @@ static struct powerdomain cam_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain per_pwrdm = { @@ -244,7 +244,7 @@ static struct powerdomain per_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain per_am35x_pwrdm = { @@ -259,13 +259,13 @@ static struct powerdomain per_am35x_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain emu_pwrdm = { .name = "emu_pwrdm", .prcm_offs = OMAP3430_EMU_MOD, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain neon_pwrdm = { @@ -273,7 +273,7 @@ static struct powerdomain neon_pwrdm = { .prcm_offs = OMAP3430_NEON_MOD, .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_RET, - .voltdm = { .name = "mpu_iva" }, + .voltdm = { .name = "mpu_iva" }, }; static struct powerdomain neon_am35x_pwrdm = { @@ -281,7 +281,7 @@ static struct powerdomain neon_am35x_pwrdm = { .prcm_offs = OMAP3430_NEON_MOD, .pwrsts = PWRSTS_ON, .pwrsts_logic_ret = PWRSTS_ON, - .voltdm = { .name = "mpu_iva" }, + .voltdm = { .name = "mpu_iva" }, }; static struct powerdomain usbhost_pwrdm = { @@ -303,37 +303,37 @@ static struct powerdomain usbhost_pwrdm = { .pwrsts_mem_on = { [0] = PWRSTS_ON, /* MEMONSTATE */ }, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain dpll1_pwrdm = { .name = "dpll1_pwrdm", .prcm_offs = MPU_MOD, - .voltdm = { .name = "mpu_iva" }, + .voltdm = { .name = "mpu_iva" }, }; static struct powerdomain dpll2_pwrdm = { .name = "dpll2_pwrdm", .prcm_offs = OMAP3430_IVA2_MOD, - .voltdm = { .name = "mpu_iva" }, + .voltdm = { .name = "mpu_iva" }, }; static struct powerdomain dpll3_pwrdm = { .name = "dpll3_pwrdm", .prcm_offs = PLL_MOD, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain dpll4_pwrdm = { .name = "dpll4_pwrdm", .prcm_offs = PLL_MOD, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; static struct powerdomain dpll5_pwrdm = { .name = "dpll5_pwrdm", .prcm_offs = PLL_MOD, - .voltdm = { .name = "core" }, + .voltdm = { .name = "core" }, }; /* As powerdomains are added or removed above, this list must also be changed */ diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index a3e121f..947f6ad 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -210,6 +210,7 @@ int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1, PM_WKDEP, (1 << clkdm2->dep_bit)); } +/* XXX Caller must hold the clkdm's powerdomain lock */ int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm) { struct clkdm_dep *cd; @@ -221,7 +222,7 @@ int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm) /* PRM accesses are slow, so minimize them */ mask |= 1 << cd->clkdm->dep_bit; - atomic_set(&cd->wkdep_usecount, 0); + cd->wkdep_usecount = 0; } omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 04fdbc4..d01c373 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -316,8 +316,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, if (WARN_ON(!oh)) return; - pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size, - NULL, 0, false); + pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size); if (IS_ERR(pdev)) { WARN(1, "Could not build omap_device for %s: %s.\n", name, oh->name); diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index b9753fe..bb829e0 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -152,8 +152,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user) sr_data->enable_on_init = sr_enable_on_init; - pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data), - NULL, 0, 0); + pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data), 0); if (IS_ERR(pdev)) pr_warning("%s: Could not build omap_device for %s: %s.\n\n", __func__, name, oh->name); diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 5975a42..6d1f7b1 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -131,7 +131,6 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode, static struct clock_event_device clockevent_gpt = { .name = "gp_timer", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .rating = 300, .set_next_event = omap2_gp_timer_set_next_event, .set_mode = omap2_gp_timer_set_mode, @@ -165,15 +164,11 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, struct device_node *np; for_each_matching_node(np, match) { - if (!of_device_is_available(np)) { - of_node_put(np); + if (!of_device_is_available(np)) continue; - } - if (property && !of_get_property(np, property, NULL)) { - of_node_put(np); + if (property && !of_get_property(np, property, NULL)) continue; - } of_add_property(np, &device_disabled); return np; @@ -340,17 +335,11 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); - clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, - clockevent_gpt.shift); - clockevent_gpt.max_delta_ns = - clockevent_delta2ns(0xffffffff, &clockevent_gpt); - clockevent_gpt.min_delta_ns = - clockevent_delta2ns(3, &clockevent_gpt); - /* Timer internal resynch latency. */ - clockevent_gpt.cpumask = cpu_possible_mask; clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); - clockevents_register_device(&clockevent_gpt); + clockevents_config_and_register(&clockevent_gpt, clkev.rate, + 3, /* Timer internal resynch latency */ + 0xffffffff); pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", gptimer_id, clkev.rate); @@ -694,8 +683,7 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) pdata->timer_errata = omap_dm_timer_get_errata(); pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; - pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), - NULL, 0, 0); + pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata)); if (IS_ERR(pdev)) { pr_err("%s: Can't build omap_device for %s: %s.\n", diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index 2e44e8a..99f04de 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -42,14 +42,6 @@ static struct usbtll_omap_platform_data usbtll_data; static struct ehci_hcd_omap_platform_data ehci_data; static struct ohci_hcd_omap_platform_data ohci_data; -static struct omap_device_pm_latency omap_uhhtll_latency[] = { - { - .deactivate_func = omap_device_idle_hwmods, - .activate_func = omap_device_enable_hwmods, - .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, - }, -}; - /* MUX settings for EHCI pins */ /* * setup_ehci_io_mux - initialize IO pad mux for USBHOST @@ -530,9 +522,7 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata) } pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm, - &usbtll_data, sizeof(usbtll_data), - omap_uhhtll_latency, - ARRAY_SIZE(omap_uhhtll_latency), false); + &usbtll_data, sizeof(usbtll_data)); if (IS_ERR(pdev)) { pr_err("Could not build hwmod device %s\n", USBHS_TLL_HWMODNAME); @@ -540,9 +530,7 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata) } pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm, - &usbhs_data, sizeof(usbhs_data), - omap_uhhtll_latency, - ARRAY_SIZE(omap_uhhtll_latency), false); + &usbhs_data, sizeof(usbhs_data)); if (IS_ERR(pdev)) { pr_err("Could not build hwmod devices %s\n", USBHS_UHH_HWMODNAME); diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 7b33b37..8c4de27 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -102,7 +102,7 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data) return; pdev = omap_device_build(name, bus_id, oh, &musb_plat, - sizeof(musb_plat), NULL, 0, false); + sizeof(musb_plat)); if (IS_ERR(pdev)) { pr_err("Could not build omap_device for %s %s\n", name, oh_name); diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c index 7c2b4ed..910243f 100644 --- a/arch/arm/mach-omap2/wd_timer.c +++ b/arch/arm/mach-omap2/wd_timer.c @@ -124,8 +124,7 @@ static int __init omap_init_wdt(void) pdata.read_reset_sources = prm_read_reset_sources; pdev = omap_device_build(dev_name, id, oh, &pdata, - sizeof(struct omap_wd_timer_platform_data), - NULL, 0, 0); + sizeof(struct omap_wd_timer_platform_data)); WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", dev_name, oh->name); return 0; diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig index 558ccfb..4f7379f 100644 --- a/arch/arm/mach-prima2/Kconfig +++ b/arch/arm/mach-prima2/Kconfig @@ -11,6 +11,16 @@ config ARCH_PRIMA2 help Support for CSR SiRFSoC ARM Cortex A9 Platform +config ARCH_MARCO + bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform" + default y + select ARM_GIC + select CPU_V7 + select HAVE_SMP + select SMP_ON_UP + help + Support for CSR SiRFSoC ARM Cortex A9 Platform + endmenu config SIRF_IRQ diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index fc9ce22..bfe360c 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -1,4 +1,3 @@ -obj-y := timer.o obj-y += rstc.o obj-y += common.o obj-y += rtciobrg.o @@ -6,3 +5,7 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_CACHE_L2X0) += l2x0.o obj-$(CONFIG_SUSPEND) += pm.o sleep.o obj-$(CONFIG_SIRF_IRQ) += irq.o +obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o +obj-$(CONFIG_ARCH_MARCO) += timer-marco.o diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index ed3570e..2d57aa4 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c @@ -8,6 +8,7 @@ #include <linux/init.h> #include <linux/kernel.h> +#include <linux/irqchip.h> #include <asm/sizes.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -30,6 +31,12 @@ void __init sirfsoc_init_late(void) sirfsoc_pm_init(); } +static __init void sirfsoc_map_io(void) +{ + sirfsoc_map_lluart(); + sirfsoc_map_scu(); +} + #ifdef CONFIG_ARCH_PRIMA2 static const char *prima2_dt_match[] __initdata = { "sirf,prima2", @@ -38,9 +45,12 @@ static const char *prima2_dt_match[] __initdata = { DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song <baohua.song@csr.com> */ - .map_io = sirfsoc_map_lluart, + .map_io = sirfsoc_map_io, .init_irq = sirfsoc_of_irq_init, - .init_time = sirfsoc_timer_init, + .init_time = sirfsoc_prima2_timer_init, +#ifdef CONFIG_MULTI_IRQ_HANDLER + .handle_irq = sirfsoc_handle_irq, +#endif .dma_zone_size = SZ_256M, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, @@ -48,3 +58,22 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") .restart = sirfsoc_restart, MACHINE_END #endif + +#ifdef CONFIG_ARCH_MARCO +static const char *marco_dt_match[] __initdata = { + "sirf,marco", + NULL +}; + +DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)") + /* Maintainer: Barry Song <baohua.song@csr.com> */ + .smp = smp_ops(sirfsoc_smp_ops), + .map_io = sirfsoc_map_io, + .init_irq = irqchip_init, + .init_time = sirfsoc_marco_timer_init, + .init_machine = sirfsoc_mach_init, + .init_late = sirfsoc_init_late, + .dt_compat = marco_dt_match, + .restart = sirfsoc_restart, +MACHINE_END +#endif diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h index 9c75f12..b7c26b6 100644 --- a/arch/arm/mach-prima2/common.h +++ b/arch/arm/mach-prima2/common.h @@ -11,12 +11,19 @@ #include <linux/init.h> #include <asm/mach/time.h> +#include <asm/exception.h> -extern void sirfsoc_timer_init(void); +extern void sirfsoc_prima2_timer_init(void); +extern void sirfsoc_marco_timer_init(void); + +extern struct smp_operations sirfsoc_smp_ops; +extern void sirfsoc_secondary_startup(void); +extern void sirfsoc_cpu_die(unsigned int cpu); extern void __init sirfsoc_of_irq_init(void); extern void __init sirfsoc_of_clk_init(void); extern void sirfsoc_restart(char, const char *); +extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs); #ifndef CONFIG_DEBUG_LL static inline void sirfsoc_map_lluart(void) {} @@ -24,6 +31,12 @@ static inline void sirfsoc_map_lluart(void) {} extern void __init sirfsoc_map_lluart(void); #endif +#ifndef CONFIG_SMP +static inline void sirfsoc_map_scu(void) {} +#else +extern void sirfsoc_map_scu(void); +#endif + #ifdef CONFIG_SUSPEND extern int sirfsoc_pm_init(void); #else diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S new file mode 100644 index 0000000..ada82d0 --- /dev/null +++ b/arch/arm/mach-prima2/headsmp.S @@ -0,0 +1,80 @@ +/* + * Entry of the second core for CSR Marco dual-core SMP SoCs + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/linkage.h> +#include <linux/init.h> + + __CPUINIT + +/* + * Cold boot and hardware reset show different behaviour, + * system will be always panic if we warm-reset the board + * Here we invalidate L1 of CPU1 to make sure there isn't + * uninitialized data written into memory later + */ +ENTRY(v7_invalidate_l1) + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: subs r3, r3, #1 @ Temp-- + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) + mcr p15, 0, r5, c7, c6, 2 + bgt 2b + cmp r2, #0 + bgt 1b + dsb + isb + mov pc, lr +ENDPROC(v7_invalidate_l1) + +/* + * SIRFSOC specific entry point for secondary CPUs. This provides + * a "holding pen" into which all secondary cores are held until we're + * ready for them to initialise. + */ +ENTRY(sirfsoc_secondary_startup) + bl v7_invalidate_l1 + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup +ENDPROC(sirfsoc_secondary_startup) + + .align +1: .long . + .long pen_release diff --git a/arch/arm/mach-prima2/hotplug.c b/arch/arm/mach-prima2/hotplug.c new file mode 100644 index 0000000..f4b17cb --- /dev/null +++ b/arch/arm/mach-prima2/hotplug.c @@ -0,0 +1,41 @@ +/* + * CPU hotplug support for CSR Marco dual-core SMP SoCs + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/smp.h> + +#include <asm/cacheflush.h> +#include <asm/smp_plat.h> + +static inline void platform_do_lowpower(unsigned int cpu) +{ + flush_cache_all(); + + /* we put the platform to just WFI */ + for (;;) { + __asm__ __volatile__("dsb\n\t" "wfi\n\t" + : : : "memory"); + if (pen_release == cpu_logical_map(cpu)) { + /* + * OK, proper wakeup, we're done + */ + break; + } + } +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void __ref sirfsoc_cpu_die(unsigned int cpu) +{ + platform_do_lowpower(cpu); +} diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h index f6014a0..b778a0f 100644 --- a/arch/arm/mach-prima2/include/mach/irqs.h +++ b/arch/arm/mach-prima2/include/mach/irqs.h @@ -10,8 +10,8 @@ #define __ASM_ARCH_IRQS_H #define SIRFSOC_INTENAL_IRQ_START 0 -#define SIRFSOC_INTENAL_IRQ_END 59 +#define SIRFSOC_INTENAL_IRQ_END 127 #define SIRFSOC_GPIO_IRQ_START (SIRFSOC_INTENAL_IRQ_END + 1) -#define NR_IRQS 220 +#define NR_IRQS 288 #endif diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/mach-prima2/include/mach/uart.h index c98b4d5..c10510d 100644 --- a/arch/arm/mach-prima2/include/mach/uart.h +++ b/arch/arm/mach-prima2/include/mach/uart.h @@ -10,7 +10,13 @@ #define __MACH_PRIMA2_SIRFSOC_UART_H /* UART-1: used as serial debug port */ +#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) #define SIRFSOC_UART1_PA_BASE 0xb0060000 +#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1) +#define SIRFSOC_UART1_PA_BASE 0xcc060000 +#else +#define SIRFSOC_UART1_PA_BASE 0 +#endif #define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000) #define SIRFSOC_UART1_SIZE SZ_4K diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h index 0c898fc..15f3edc 100644 --- a/arch/arm/mach-prima2/include/mach/uncompress.h +++ b/arch/arm/mach-prima2/include/mach/uncompress.h @@ -25,6 +25,9 @@ static __inline__ void putc(char c) * during kernel decompression, all mappings are flat: * virt_addr == phys_addr */ + if (!SIRFSOC_UART1_PA_BASE) + return; + while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS) & SIRFSOC_UART1_TXFIFO_FULL) barrier(); diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c index 7dee917..6c0f3e9 100644 --- a/arch/arm/mach-prima2/irq.c +++ b/arch/arm/mach-prima2/irq.c @@ -9,17 +9,19 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/irq.h> -#include <mach/hardware.h> -#include <asm/mach/irq.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/irqdomain.h> #include <linux/syscore_ops.h> +#include <asm/mach/irq.h> +#include <asm/exception.h> +#include <mach/hardware.h> #define SIRFSOC_INT_RISC_MASK0 0x0018 #define SIRFSOC_INT_RISC_MASK1 0x001C #define SIRFSOC_INT_RISC_LEVEL0 0x0020 #define SIRFSOC_INT_RISC_LEVEL1 0x0024 +#define SIRFSOC_INIT_IRQ_ID 0x0038 void __iomem *sirfsoc_intc_base; @@ -52,6 +54,16 @@ static __init void sirfsoc_irq_init(void) writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); } +asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs) +{ + u32 irqstat, irqnr; + + irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID); + irqnr = irqstat & 0xff; + + handle_IRQ(irqnr, regs); +} + static struct of_device_id intc_ids[] = { { .compatible = "sirf,prima2-intc" }, {}, diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c index c998377..cbcbe9c 100644 --- a/arch/arm/mach-prima2/l2x0.c +++ b/arch/arm/mach-prima2/l2x0.c @@ -11,19 +11,38 @@ #include <linux/of.h> #include <asm/hardware/cache-l2x0.h> -static struct of_device_id prima2_l2x0_ids[] = { - { .compatible = "sirf,prima2-pl310-cache" }, +struct l2x0_aux +{ + u32 val; + u32 mask; +}; + +static struct l2x0_aux prima2_l2x0_aux __initconst = { + .val = 2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT, + .mask = 0, +}; + +static struct l2x0_aux marco_l2x0_aux __initconst = { + .val = (2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | + (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT), + .mask = L2X0_AUX_CTRL_MASK, +}; + +static struct of_device_id sirf_l2x0_ids[] __initconst = { + { .compatible = "sirf,prima2-pl310-cache", .data = &prima2_l2x0_aux, }, + { .compatible = "sirf,marco-pl310-cache", .data = &marco_l2x0_aux, }, {}, }; static int __init sirfsoc_l2x0_init(void) { struct device_node *np; + const struct l2x0_aux *aux; - np = of_find_matching_node(NULL, prima2_l2x0_ids); + np = of_find_matching_node(NULL, sirf_l2x0_ids); if (np) { - pr_info("Initializing prima2 L2 cache\n"); - return l2x0_of_init(0x40000, 0); + aux = of_match_node(sirf_l2x0_ids, np)->data; + return l2x0_of_init(aux->val, aux->mask); } return 0; diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c new file mode 100644 index 0000000..4b78831 --- /dev/null +++ b/arch/arm/mach-prima2/platsmp.c @@ -0,0 +1,157 @@ +/* + * plat smp support for CSR Marco dual-core SMP SoCs + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/init.h> +#include <linux/smp.h> +#include <linux/delay.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/irqchip/arm-gic.h> +#include <asm/page.h> +#include <asm/mach/map.h> +#include <asm/smp_plat.h> +#include <asm/smp_scu.h> +#include <asm/cacheflush.h> +#include <asm/cputype.h> +#include <mach/map.h> + +#include "common.h" + +static void __iomem *scu_base; +static void __iomem *rsc_base; + +static DEFINE_SPINLOCK(boot_lock); + +static struct map_desc scu_io_desc __initdata = { + .length = SZ_4K, + .type = MT_DEVICE, +}; + +void __init sirfsoc_map_scu(void) +{ + unsigned long base; + + /* Get SCU base */ + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); + + scu_io_desc.virtual = SIRFSOC_VA(base); + scu_io_desc.pfn = __phys_to_pfn(base); + iotable_init(&scu_io_desc, 1); + + scu_base = (void __iomem *)SIRFSOC_VA(base); +} + +static void __cpuinit sirfsoc_secondary_init(unsigned int cpu) +{ + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + pen_release = -1; + smp_wmb(); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +static struct of_device_id rsc_ids[] = { + { .compatible = "sirf,marco-rsc" }, + {}, +}; + +static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + struct device_node *np; + + np = of_find_matching_node(NULL, rsc_ids); + if (!np) + return -ENODEV; + + rsc_base = of_iomap(np, 0); + if (!rsc_base) + return -ENOMEM; + + /* + * write the address of secondary startup into the sram register + * at offset 0x2C, then write the magic number 0x3CAF5D62 to the + * RSC register at offset 0x28, which is what boot rom code is + * waiting for. This would wake up the secondary core from WFE + */ +#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C + __raw_writel(virt_to_phys(sirfsoc_secondary_startup), + rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET); + +#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28 + __raw_writel(0x3CAF5D62, + rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET); + + /* make sure write buffer is drained */ + mb(); + + spin_lock(&boot_lock); + + /* + * The secondary processor is waiting to be released from + * the holding pen - release it, then wait for it to flag + * that it has been released by resetting pen_release. + * + * Note that "pen_release" is the hardware CPU ID, whereas + * "cpu" is Linux's internal ID. + */ + pen_release = cpu_logical_map(cpu); + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + + /* + * Send the secondary CPU SEV, thereby causing the boot monitor to read + * the JUMPADDR and WAKEMAGIC, and branch to the address found there. + */ + dsb_sev(); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + smp_rmb(); + if (pen_release == -1) + break; + + udelay(10); + } + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} + +static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus) +{ + scu_enable(scu_base); +} + +struct smp_operations sirfsoc_smp_ops __initdata = { + .smp_prepare_cpus = sirfsoc_smp_prepare_cpus, + .smp_secondary_init = sirfsoc_secondary_init, + .smp_boot_secondary = sirfsoc_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = sirfsoc_cpu_die, +#endif +}; diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c index 762adb7..435019c 100644 --- a/arch/arm/mach-prima2/rstc.c +++ b/arch/arm/mach-prima2/rstc.c @@ -19,6 +19,7 @@ static DEFINE_MUTEX(rstc_lock); static struct of_device_id rstc_ids[] = { { .compatible = "sirf,prima2-rstc" }, + { .compatible = "sirf,marco-rstc" }, {}, }; @@ -42,27 +43,37 @@ early_initcall(sirfsoc_of_rstc_init); int sirfsoc_reset_device(struct device *dev) { - const unsigned int *prop = of_get_property(dev->of_node, "reset-bit", NULL); - unsigned int reset_bit; + u32 reset_bit; - if (!prop) - return -ENODEV; - - reset_bit = be32_to_cpup(prop); + if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit)) + return -EINVAL; mutex_lock(&rstc_lock); - /* - * Writing 1 to this bit resets corresponding block. Writing 0 to this - * bit de-asserts reset signal of the corresponding block. - * datasheet doesn't require explicit delay between the set and clear - * of reset bit. it could be shorter if tests pass. - */ - writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit, - sirfsoc_rstc_base + (reset_bit / 32) * 4); - msleep(10); - writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit, - sirfsoc_rstc_base + (reset_bit / 32) * 4); + if (of_device_is_compatible(dev->of_node, "sirf,prima2-rstc")) { + /* + * Writing 1 to this bit resets corresponding block. Writing 0 to this + * bit de-asserts reset signal of the corresponding block. + * datasheet doesn't require explicit delay between the set and clear + * of reset bit. it could be shorter if tests pass. + */ + writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit, + sirfsoc_rstc_base + (reset_bit / 32) * 4); + msleep(10); + writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit, + sirfsoc_rstc_base + (reset_bit / 32) * 4); + } else { + /* + * For MARCO and POLO + * Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR + * register de-asserts reset signal of the corresponding block. + * datasheet doesn't require explicit delay between the set and clear + * of reset bit. it could be shorter if tests pass. + */ + writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8); + msleep(10); + writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4); + } mutex_unlock(&rstc_lock); diff --git a/arch/arm/mach-prima2/rtciobrg.c b/arch/arm/mach-prima2/rtciobrg.c index 5573536..9f2da2e 100644 --- a/arch/arm/mach-prima2/rtciobrg.c +++ b/arch/arm/mach-prima2/rtciobrg.c @@ -104,6 +104,7 @@ EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel); static const struct of_device_id rtciobrg_ids[] = { { .compatible = "sirf,prima2-rtciobg" }, + { .compatible = "sirf,marco-rtciobg" }, {} }; diff --git a/arch/arm/mach-prima2/timer-marco.c b/arch/arm/mach-prima2/timer-marco.c new file mode 100644 index 0000000..f4eea2e --- /dev/null +++ b/arch/arm/mach-prima2/timer-marco.c @@ -0,0 +1,316 @@ +/* + * System timer for CSR SiRFprimaII + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/clockchips.h> +#include <linux/clocksource.h> +#include <linux/bitops.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <linux/slab.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> +#include <asm/sched_clock.h> +#include <asm/localtimer.h> +#include <asm/mach/time.h> + +#include "common.h" + +#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000 +#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004 +#define SIRFSOC_TIMER_MATCH_0 0x0018 +#define SIRFSOC_TIMER_MATCH_1 0x001c +#define SIRFSOC_TIMER_COUNTER_0 0x0048 +#define SIRFSOC_TIMER_COUNTER_1 0x004c +#define SIRFSOC_TIMER_INTR_STATUS 0x0060 +#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064 +#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068 +#define SIRFSOC_TIMER_64COUNTER_LO 0x006c +#define SIRFSOC_TIMER_64COUNTER_HI 0x0070 +#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074 +#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078 +#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c +#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080 + +#define SIRFSOC_TIMER_REG_CNT 6 + +static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = { + SIRFSOC_TIMER_WATCHDOG_EN, + SIRFSOC_TIMER_32COUNTER_0_CTRL, + SIRFSOC_TIMER_32COUNTER_1_CTRL, + SIRFSOC_TIMER_64COUNTER_CTRL, + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO, + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI, +}; + +static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; + +static void __iomem *sirfsoc_timer_base; +static void __init sirfsoc_of_timer_map(void); + +/* disable count and interrupt */ +static inline void sirfsoc_timer_count_disable(int idx) +{ + writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7, + sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx); +} + +/* enable count and interrupt */ +static inline void sirfsoc_timer_count_enable(int idx) +{ + writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7, + sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx); +} + +/* timer interrupt handler */ +static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *ce = dev_id; + int cpu = smp_processor_id(); + + /* clear timer interrupt */ + writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); + + if (ce->mode == CLOCK_EVT_MODE_ONESHOT) + sirfsoc_timer_count_disable(cpu); + + ce->event_handler(ce); + + return IRQ_HANDLED; +} + +/* read 64-bit timer counter */ +static cycle_t sirfsoc_timer_read(struct clocksource *cs) +{ + u64 cycles; + + writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | + BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); + + cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI); + cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO); + + return cycles; +} + +static int sirfsoc_timer_set_next_event(unsigned long delta, + struct clock_event_device *ce) +{ + int cpu = smp_processor_id(); + + writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 + + 4 * cpu); + writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 + + 4 * cpu); + + /* enable the tick */ + sirfsoc_timer_count_enable(cpu); + + return 0; +} + +static void sirfsoc_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *ce) +{ + switch (mode) { + case CLOCK_EVT_MODE_ONESHOT: + /* enable in set_next_event */ + break; + default: + break; + } + + sirfsoc_timer_count_disable(smp_processor_id()); +} + +static void sirfsoc_clocksource_suspend(struct clocksource *cs) +{ + int i; + + for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) + sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); +} + +static void sirfsoc_clocksource_resume(struct clocksource *cs) +{ + int i; + + for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++) + writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); + + writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], + sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO); + writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], + sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI); + + writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | + BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); +} + +static struct clock_event_device sirfsoc_clockevent = { + .name = "sirfsoc_clockevent", + .rating = 200, + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_mode = sirfsoc_timer_set_mode, + .set_next_event = sirfsoc_timer_set_next_event, +}; + +static struct clocksource sirfsoc_clocksource = { + .name = "sirfsoc_clocksource", + .rating = 200, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .read = sirfsoc_timer_read, + .suspend = sirfsoc_clocksource_suspend, + .resume = sirfsoc_clocksource_resume, +}; + +static struct irqaction sirfsoc_timer_irq = { + .name = "sirfsoc_timer0", + .flags = IRQF_TIMER | IRQF_NOBALANCING, + .handler = sirfsoc_timer_interrupt, + .dev_id = &sirfsoc_clockevent, +}; + +#ifdef CONFIG_LOCAL_TIMERS + +static struct irqaction sirfsoc_timer1_irq = { + .name = "sirfsoc_timer1", + .flags = IRQF_TIMER | IRQF_NOBALANCING, + .handler = sirfsoc_timer_interrupt, +}; + +static int __cpuinit sirfsoc_local_timer_setup(struct clock_event_device *ce) +{ + /* Use existing clock_event for cpu 0 */ + if (!smp_processor_id()) + return 0; + + ce->irq = sirfsoc_timer1_irq.irq; + ce->name = "local_timer"; + ce->features = sirfsoc_clockevent.features; + ce->rating = sirfsoc_clockevent.rating; + ce->set_mode = sirfsoc_timer_set_mode; + ce->set_next_event = sirfsoc_timer_set_next_event; + ce->shift = sirfsoc_clockevent.shift; + ce->mult = sirfsoc_clockevent.mult; + ce->max_delta_ns = sirfsoc_clockevent.max_delta_ns; + ce->min_delta_ns = sirfsoc_clockevent.min_delta_ns; + + sirfsoc_timer1_irq.dev_id = ce; + BUG_ON(setup_irq(ce->irq, &sirfsoc_timer1_irq)); + irq_set_affinity(sirfsoc_timer1_irq.irq, cpumask_of(1)); + + clockevents_register_device(ce); + return 0; +} + +static void sirfsoc_local_timer_stop(struct clock_event_device *ce) +{ + sirfsoc_timer_count_disable(1); + + remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq); +} + +static struct local_timer_ops sirfsoc_local_timer_ops __cpuinitdata = { + .setup = sirfsoc_local_timer_setup, + .stop = sirfsoc_local_timer_stop, +}; +#endif /* CONFIG_LOCAL_TIMERS */ + +static void __init sirfsoc_clockevent_init(void) +{ + clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60); + + sirfsoc_clockevent.max_delta_ns = + clockevent_delta2ns(-2, &sirfsoc_clockevent); + sirfsoc_clockevent.min_delta_ns = + clockevent_delta2ns(2, &sirfsoc_clockevent); + + sirfsoc_clockevent.cpumask = cpumask_of(0); + clockevents_register_device(&sirfsoc_clockevent); +#ifdef CONFIG_LOCAL_TIMERS + local_timer_register(&sirfsoc_local_timer_ops); +#endif +} + +/* initialize the kernel jiffy timer source */ +void __init sirfsoc_marco_timer_init(void) +{ + unsigned long rate; + u32 timer_div; + struct clk *clk; + + /* initialize clocking early, we want to set the OS timer */ + sirfsoc_of_clk_init(); + + /* timer's input clock is io clock */ + clk = clk_get_sys("io", NULL); + + BUG_ON(IS_ERR(clk)); + rate = clk_get_rate(clk); + + BUG_ON(rate < CLOCK_TICK_RATE); + BUG_ON(rate % CLOCK_TICK_RATE); + + sirfsoc_of_timer_map(); + + /* Initialize the timer dividers */ + timer_div = rate / CLOCK_TICK_RATE - 1; + writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); + writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL); + writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL); + + /* Initialize timer counters to 0 */ + writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO); + writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI); + writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | + BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); + writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0); + writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1); + + /* Clear all interrupts */ + writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); + + BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); + + BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); + + sirfsoc_clockevent_init(); +} + +static struct of_device_id timer_ids[] = { + { .compatible = "sirf,marco-tick" }, + {}, +}; + +static void __init sirfsoc_of_timer_map(void) +{ + struct device_node *np; + + np = of_find_matching_node(NULL, timer_ids); + if (!np) + return; + sirfsoc_timer_base = of_iomap(np, 0); + if (!sirfsoc_timer_base) + panic("unable to map timer cpu registers\n"); + + sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0); + if (!sirfsoc_timer_irq.irq) + panic("No irq passed for timer0 via DT\n"); + +#ifdef CONFIG_LOCAL_TIMERS + sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1); + if (!sirfsoc_timer1_irq.irq) + panic("No irq passed for timer1 via DT\n"); +#endif + + of_node_put(np); +} diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer-prima2.c index 8c732a5..6da584f 100644 --- a/arch/arm/mach-prima2/timer.c +++ b/arch/arm/mach-prima2/timer-prima2.c @@ -175,19 +175,13 @@ static u32 notrace sirfsoc_read_sched_clock(void) static void __init sirfsoc_clockevent_init(void) { - clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60); - - sirfsoc_clockevent.max_delta_ns = - clockevent_delta2ns(-2, &sirfsoc_clockevent); - sirfsoc_clockevent.min_delta_ns = - clockevent_delta2ns(2, &sirfsoc_clockevent); - sirfsoc_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&sirfsoc_clockevent); + clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE, + 2, -2); } /* initialize the kernel jiffy timer source */ -void __init sirfsoc_timer_init(void) +void __init sirfsoc_prima2_timer_init(void) { unsigned long rate; struct clk *clk; @@ -226,14 +220,14 @@ static struct of_device_id timer_ids[] = { {}, }; -void __init sirfsoc_of_timer_map(void) +static void __init sirfsoc_of_timer_map(void) { struct device_node *np; const unsigned int *intspec; np = of_find_matching_node(NULL, timer_ids); if (!np) - panic("unable to find compatible timer node in dtb\n"); + return; sirfsoc_timer_base = of_iomap(np, 0); if (!sirfsoc_timer_base) panic("unable to map timer cpu registers\n"); diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h index a611ad3..b6132aa 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h @@ -463,6 +463,9 @@ GPIO76_LCD_PCLK, \ GPIO77_LCD_BIAS +/* these enable a work-around for a hw bug in pxa27x during ac97 warm reset */ +#define GPIO113_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO113, AF0, DEFAULT) +#define GPIO95_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO95, AF0, DEFAULT) extern int keypad_set_wake(unsigned int on); #endif /* __ASM_ARCH_MFP_PXA27X_H */ diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 8047ee0..616cb87 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -47,9 +47,9 @@ void pxa27x_clear_otgph(void) EXPORT_SYMBOL(pxa27x_clear_otgph); static unsigned long ac97_reset_config[] = { - GPIO113_GPIO, + GPIO113_AC97_nRESET_GPIO_HIGH, GPIO113_AC97_nRESET, - GPIO95_GPIO, + GPIO95_AC97_nRESET_GPIO_HIGH, GPIO95_AC97_nRESET, }; diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index bea19a0..8f1ee92 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -151,16 +151,12 @@ void __init pxa_timer_init(void) setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate); - clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4); - ckevt_pxa_osmr0.max_delta_ns = - clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); - ckevt_pxa_osmr0.min_delta_ns = - clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1; ckevt_pxa_osmr0.cpumask = cpumask_of(0); setup_irq(IRQ_OST0, &pxa_ost0_irq); clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32, clocksource_mmio_readl_up); - clockevents_register_device(&ckevt_pxa_osmr0); + clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate, + MIN_OSCR_DELTA * 2, 0x7fffffff); } diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c index 553059f..755c0bb 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c @@ -47,7 +47,7 @@ static struct spi_board_info wm1253_devs[] = { .bus_num = 0, .chip_select = 0, .mode = SPI_MODE_0, - .irq = S3C_EINT(5), + .irq = S3C_EINT(4), .controller_data = &wm0010_spi_csinfo, .platform_data = &wm0010_pdata, }, diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c index 7feb426..d2e1a16 100644 --- a/arch/arm/mach-s3c64xx/pm.c +++ b/arch/arm/mach-s3c64xx/pm.c @@ -338,8 +338,10 @@ int __init s3c64xx_pm_init(void) for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++) pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false); +#ifdef CONFIG_S3C_DEV_FB if (dev_get_platdata(&s3c_device_fb.dev)) pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev); +#endif return 0; } diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index 934db63..a59a13a 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -124,16 +124,12 @@ void __init sa1100_timer_init(void) setup_sched_clock(sa1100_read_sched_clock, 32, 3686400); - clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4); - ckevt_sa1100_osmr0.max_delta_ns = - clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0); - ckevt_sa1100_osmr0.min_delta_ns = - clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1; ckevt_sa1100_osmr0.cpumask = cpumask_of(0); setup_irq(IRQ_OST0, &sa1100_timer_irq); clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up); - clockevents_register_device(&ckevt_sa1100_osmr0); + clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400, + MIN_OSCR_DELTA * 2, 0x7fffffff); } diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index b202c12..96001fd 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S @@ -16,54 +16,6 @@ __CPUINIT -/* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks! - * - * The secondary kernel init calls v7_flush_dcache_all before it enables - * the L1; however, the L1 comes out of reset in an undefined state, so - * the clean + invalidate performed by v7_flush_dcache_all causes a bunch - * of cache lines with uninitialized data and uninitialized tags to get - * written out to memory, which does really unpleasant things to the main - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * - * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs - * to be called for both secondary cores startup and primary core resume - * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. - */ -ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) - mcr p15, 0, r5, c7, c6, 2 - bgt 2b - cmp r2, #0 - bgt 1b - dsb - isb - mov pc, lr -ENDPROC(v7_invalidate_l1) - ENTRY(shmobile_invalidate_start) bl v7_invalidate_l1 b secondary_startup diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 9941caa..315edff 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -20,7 +20,7 @@ #ifndef __MACH_CORE_H #define __MACH_CORE_H -extern void secondary_startup(void); +extern void socfpga_secondary_startup(void); extern void __iomem *socfpga_scu_base_addr; extern void socfpga_init_clocks(void); @@ -29,6 +29,8 @@ extern void socfpga_sysmgr_init(void); extern struct smp_operations socfpga_smp_ops; extern char secondary_trampoline, secondary_trampoline_end; +extern unsigned long cpu1start_addr; + #define SOCFPGA_SCU_VIRT_BASE 0xfffec000 #endif diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S index f09b128..9004bfb 100644 --- a/arch/arm/mach-socfpga/headsmp.S +++ b/arch/arm/mach-socfpga/headsmp.S @@ -13,13 +13,21 @@ __CPUINIT .arch armv7-a -#define CPU1_START_ADDR 0xffd08010 - ENTRY(secondary_trampoline) - movw r0, #:lower16:CPU1_START_ADDR - movt r0, #:upper16:CPU1_START_ADDR + movw r2, #:lower16:cpu1start_addr + movt r2, #:upper16:cpu1start_addr + + /* The socfpga VT cannot handle a 0xC0000000 page offset when loading + the cpu1start_addr, we bit clear it. Tested on HW and VT. */ + bic r2, r2, #0x40000000 + ldr r0, [r2] ldr r1, [r0] bx r1 ENTRY(secondary_trampoline_end) + +ENTRY(socfpga_secondary_startup) + bl v7_invalidate_l1 + b secondary_startup +ENDPROC(socfpga_secondary_startup) diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index 4e9e69d..84c60fa 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c @@ -47,16 +47,19 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct { int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; - memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); + if (cpu1start_addr) { + memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); - __raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10)); + __raw_writel(virt_to_phys(socfpga_secondary_startup), + (sys_manager_base_addr + (cpu1start_addr & 0x000000ff))); - flush_cache_all(); - smp_wmb(); - outer_clean_range(0, trampoline_size); + flush_cache_all(); + smp_wmb(); + outer_clean_range(0, trampoline_size); - /* This will release CPU #1 out of reset.*/ - __raw_writel(0, rst_manager_base_addr + 0x10); + /* This will release CPU #1 out of reset.*/ + __raw_writel(0, rst_manager_base_addr + 0x10); + } return 0; } diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 27d6846..1042c02 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -29,6 +29,7 @@ void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); void __iomem *sys_manager_base_addr; void __iomem *rst_manager_base_addr; +unsigned long cpu1start_addr; static struct map_desc scu_io_desc __initdata = { .virtual = SOCFPGA_SCU_VIRT_BASE, @@ -67,6 +68,11 @@ void __init socfpga_sysmgr_init(void) struct device_node *np; np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr"); + + if (of_property_read_u32(np, "cpu1-start-addr", + (u32 *) &cpu1start_addr)) + pr_err("SMP: Need cpu1-start-addr in device tree.\n"); + sys_manager_base_addr = of_iomap(np, 0); np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); @@ -93,7 +99,6 @@ static void __init socfpga_cyclone5_init(void) static const char *altera_dt_match[] = { "altr,socfpga", - "altr,socfpga-cyclone5", NULL }; diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index b442f15..d1c4893 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -4,11 +4,11 @@ comment "NVIDIA Tegra options" config ARCH_TEGRA_2x_SOC bool "Enable support for Tegra20 family" - select ARCH_REQUIRE_GPIOLIB + select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP select ARM_ERRATA_720789 - select ARM_ERRATA_742230 + select ARM_ERRATA_742230 if SMP select ARM_ERRATA_751472 - select ARM_ERRATA_754327 + select ARM_ERRATA_754327 if SMP select ARM_ERRATA_764369 if SMP select ARM_GIC select CPU_FREQ_TABLE if CPU_FREQ @@ -26,7 +26,6 @@ config ARCH_TEGRA_2x_SOC config ARCH_TEGRA_3x_SOC bool "Enable support for Tegra30 family" - select ARCH_REQUIRE_GPIOLIB select ARM_ERRATA_743622 select ARM_ERRATA_751472 select ARM_ERRATA_754322 @@ -44,6 +43,18 @@ config ARCH_TEGRA_3x_SOC Support for NVIDIA Tegra T30 processor family, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller +config ARCH_TEGRA_114_SOC + bool "Enable support for Tegra114 family" + select ARM_ARCH_TIMER + select ARM_GIC + select ARM_L1_CACHE_SHIFT_6 + select CPU_V7 + select PINCTRL + select PINCTRL_TEGRA114 + help + Support for NVIDIA Tegra T114 processor family, based on the + ARM CortexA15MP CPU + config TEGRA_PCI bool "PCI Express support" depends on ARCH_TEGRA_2x_SOC diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 0979e8b..f6b46ae 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,39 +1,38 @@ obj-y += common.o obj-y += io.o obj-y += irq.o -obj-y += clock.o -obj-y += timer.o obj-y += fuse.o obj-y += pmc.o obj-y += flowctrl.o obj-y += powergate.o obj-y += apbio.o obj-y += pm.o +obj-y += reset.o +obj-y += reset-handler.o +obj-y += sleep.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o -obj-$(CONFIG_CPU_IDLE) += sleep.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o endif -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o endif obj-$(CONFIG_SMP) += platsmp.o headsmp.o -obj-$(CONFIG_SMP) += reset.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o obj-$(CONFIG_TEGRA_PCI) += pcie.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o +obj-$(CONFIG_ARCH_TEGRA_114_SOC) += board-dt-tegra114.o +ifeq ($(CONFIG_CPU_IDLE),y) +obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o +endif obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-harmony-pcie.o diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c index d091675..d7aa52e 100644 --- a/arch/arm/mach-tegra/apbio.c +++ b/arch/arm/mach-tegra/apbio.c @@ -38,7 +38,7 @@ static void tegra_apb_writel_direct(u32 value, unsigned long offset); static struct dma_chan *tegra_apb_dma_chan; static struct dma_slave_config dma_sconfig; -bool tegra_apb_dma_init(void) +static bool tegra_apb_dma_init(void) { dma_cap_mask_t mask; diff --git a/arch/arm/mach-tegra/board-dt-tegra114.c b/arch/arm/mach-tegra/board-dt-tegra114.c new file mode 100644 index 0000000..085d636 --- /dev/null +++ b/arch/arm/mach-tegra/board-dt-tegra114.c @@ -0,0 +1,46 @@ +/* + * NVIDIA Tegra114 device tree board support + * + * Copyright (C) 2013 NVIDIA Corporation + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/clocksource.h> + +#include <asm/mach/arch.h> + +#include "board.h" +#include "common.h" + +static void __init tegra114_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char * const tegra114_dt_board_compat[] = { + "nvidia,tegra114", + NULL, +}; + +DT_MACHINE_START(TEGRA114_DT, "NVIDIA Tegra114 (Flattened Device Tree)") + .smp = smp_ops(tegra_smp_ops), + .map_io = tegra_map_common_io, + .init_early = tegra114_init_early, + .init_irq = tegra_dt_init_irq, + .init_time = clocksource_of_init, + .init_machine = tegra114_dt_init, + .init_late = tegra_init_late, + .restart = tegra_assert_system_reset, + .dt_compat = tegra114_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c index 5ed81bab..a0edf25 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c @@ -15,6 +15,7 @@ * */ +#include <linux/clocksource.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> @@ -39,99 +40,45 @@ #include <asm/setup.h> #include "board.h" -#include "clock.h" #include "common.h" #include "iomap.h" -struct tegra_ehci_platform_data tegra_ehci1_pdata = { +static struct tegra_ehci_platform_data tegra_ehci1_pdata = { .operating_mode = TEGRA_USB_OTG, .power_down_on_bus_suspend = 1, .vbus_gpio = -1, }; -struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { +static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { .reset_gpio = -1, .clk = "cdev2", }; -struct tegra_ehci_platform_data tegra_ehci2_pdata = { +static struct tegra_ehci_platform_data tegra_ehci2_pdata = { .phy_config = &tegra_ehci2_ulpi_phy_config, .operating_mode = TEGRA_USB_HOST, .power_down_on_bus_suspend = 1, .vbus_gpio = -1, }; -struct tegra_ehci_platform_data tegra_ehci3_pdata = { +static struct tegra_ehci_platform_data tegra_ehci3_pdata = { .operating_mode = TEGRA_USB_HOST, .power_down_on_bus_suspend = 1, .vbus_gpio = -1, }; -struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra20-das", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0", +static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5000000, "tegra-ehci.0", &tegra_ehci1_pdata), - OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1", + OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5004000, "tegra-ehci.1", &tegra_ehci2_pdata), - OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2", + OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5008000, "tegra-ehci.2", &tegra_ehci3_pdata), - OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL), {} }; -static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { - /* name parent rate enabled */ - { "uarta", "pll_p", 216000000, true }, - { "uartd", "pll_p", 216000000, true }, - { "usbd", "clk_m", 12000000, false }, - { "usb2", "clk_m", 12000000, false }, - { "usb3", "clk_m", 12000000, false }, - { "pll_a", "pll_p_out1", 56448000, true }, - { "pll_a_out0", "pll_a", 11289600, true }, - { "cdev1", NULL, 0, true }, - { "blink", "clk_32k", 32768, true }, - { "i2s1", "pll_a_out0", 11289600, false}, - { "i2s2", "pll_a_out0", 11289600, false}, - { "sdmmc1", "pll_p", 48000000, false}, - { "sdmmc3", "pll_p", 48000000, false}, - { "sdmmc4", "pll_p", 48000000, false}, - { "spi", "pll_p", 20000000, false }, - { "sbc1", "pll_p", 100000000, false }, - { "sbc2", "pll_p", 100000000, false }, - { "sbc3", "pll_p", 100000000, false }, - { "sbc4", "pll_p", 100000000, false }, - { "host1x", "pll_c", 150000000, false }, - { "disp1", "pll_p", 600000000, false }, - { "disp2", "pll_p", 600000000, false }, - { NULL, NULL, 0, 0}, -}; - static void __init tegra_dt_init(void) { - tegra_clk_init_from_table(tegra_dt_clk_init_table); - /* * Finished with the static registrations now; fill in the missing * devices @@ -200,7 +147,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)") .smp = smp_ops(tegra_smp_ops), .init_early = tegra20_init_early, .init_irq = tegra_dt_init_irq, - .init_time = tegra_init_timer, + .init_time = clocksource_of_init, .init_machine = tegra_dt_init, .init_late = tegra_dt_init_late, .restart = tegra_assert_system_reset, diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c index 12dc2dd..bf68567 100644 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ b/arch/arm/mach-tegra/board-dt-tegra30.c @@ -23,6 +23,7 @@ * */ +#include <linux/clocksource.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/of_address.h> @@ -33,72 +34,12 @@ #include <asm/mach/arch.h> #include "board.h" -#include "clock.h" #include "common.h" #include "iomap.h" -struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL), - {} -}; - -static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { - /* name parent rate enabled */ - { "uarta", "pll_p", 408000000, true }, - { "pll_a", "pll_p_out1", 564480000, true }, - { "pll_a_out0", "pll_a", 11289600, true }, - { "extern1", "pll_a_out0", 0, true }, - { "clk_out_1", "extern1", 0, true }, - { "blink", "clk_32k", 32768, true }, - { "i2s0", "pll_a_out0", 11289600, false}, - { "i2s1", "pll_a_out0", 11289600, false}, - { "i2s2", "pll_a_out0", 11289600, false}, - { "i2s3", "pll_a_out0", 11289600, false}, - { "i2s4", "pll_a_out0", 11289600, false}, - { "sdmmc1", "pll_p", 48000000, false}, - { "sdmmc3", "pll_p", 48000000, false}, - { "sdmmc4", "pll_p", 48000000, false}, - { "sbc1", "pll_p", 100000000, false}, - { "sbc2", "pll_p", 100000000, false}, - { "sbc3", "pll_p", 100000000, false}, - { "sbc4", "pll_p", 100000000, false}, - { "sbc5", "pll_p", 100000000, false}, - { "sbc6", "pll_p", 100000000, false}, - { "host1x", "pll_c", 150000000, false}, - { "disp1", "pll_p", 600000000, false}, - { "disp2", "pll_p", 600000000, false}, - { NULL, NULL, 0, 0}, -}; - static void __init tegra30_dt_init(void) { - tegra_clk_init_from_table(tegra_dt_clk_init_table); - - of_platform_populate(NULL, of_default_bus_match_table, - tegra30_auxdata_lookup, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char *tegra30_dt_board_compat[] = { @@ -111,7 +52,7 @@ DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)") .map_io = tegra_map_common_io, .init_early = tegra30_init_early, .init_irq = tegra_dt_init_irq, - .init_time = tegra_init_timer, + .init_time = clocksource_of_init, .init_machine = tegra30_dt_init, .init_late = tegra_init_late, .restart = tegra_assert_system_reset, diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 744cdd2..86851c8 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -1,6 +1,7 @@ /* * arch/arm/mach-tegra/board.h * + * Copyright (c) 2013 NVIDIA Corporation. All rights reserved. * Copyright (C) 2010 Google, Inc. * * Author: @@ -27,6 +28,7 @@ void tegra_assert_system_reset(char mode, const char *cmd); void __init tegra20_init_early(void); void __init tegra30_init_early(void); +void __init tegra114_init_early(void); void __init tegra_map_common_io(void); void __init tegra_init_irq(void); void __init tegra_dt_init_irq(void); @@ -55,5 +57,4 @@ static inline int harmony_pcie_init(void) { return 0; } void __init tegra_paz00_wifikill_init(void); -extern void tegra_init_timer(void); #endif diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c deleted file mode 100644 index 867bf8b..0000000 --- a/arch/arm/mach-tegra/clock.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * - * Copyright (C) 2010 Google, Inc. - * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved. - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/init.h> -#include <linux/list.h> -#include <linux/module.h> -#include <linux/sched.h> -#include <linux/seq_file.h> -#include <linux/slab.h> - -#include "board.h" -#include "clock.h" -#include "tegra_cpu_car.h" - -/* Global data of Tegra CPU CAR ops */ -struct tegra_cpu_car_ops *tegra_cpu_car_ops; - -/* - * Locking: - * - * An additional mutex, clock_list_lock, is used to protect the list of all - * clocks. - * - */ -static DEFINE_MUTEX(clock_list_lock); -static LIST_HEAD(clocks); - -void tegra_clk_add(struct clk *clk) -{ - struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk)); - - mutex_lock(&clock_list_lock); - list_add(&c->node, &clocks); - mutex_unlock(&clock_list_lock); -} - -struct clk *tegra_get_clock_by_name(const char *name) -{ - struct clk_tegra *c; - struct clk *ret = NULL; - mutex_lock(&clock_list_lock); - list_for_each_entry(c, &clocks, node) { - if (strcmp(__clk_get_name(c->hw.clk), name) == 0) { - ret = c->hw.clk; - break; - } - } - mutex_unlock(&clock_list_lock); - return ret; -} - -static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table) -{ - struct clk *c; - struct clk *p; - struct clk *parent; - - int ret = 0; - - c = tegra_get_clock_by_name(table->name); - - if (!c) { - pr_warn("Unable to initialize clock %s\n", - table->name); - return -ENODEV; - } - - parent = clk_get_parent(c); - - if (table->parent) { - p = tegra_get_clock_by_name(table->parent); - if (!p) { - pr_warn("Unable to find parent %s of clock %s\n", - table->parent, table->name); - return -ENODEV; - } - - if (parent != p) { - ret = clk_set_parent(c, p); - if (ret) { - pr_warn("Unable to set parent %s of clock %s: %d\n", - table->parent, table->name, ret); - return -EINVAL; - } - } - } - - if (table->rate && table->rate != clk_get_rate(c)) { - ret = clk_set_rate(c, table->rate); - if (ret) { - pr_warn("Unable to set clock %s to rate %lu: %d\n", - table->name, table->rate, ret); - return -EINVAL; - } - } - - if (table->enabled) { - ret = clk_prepare_enable(c); - if (ret) { - pr_warn("Unable to enable clock %s: %d\n", - table->name, ret); - return -EINVAL; - } - } - - return 0; -} - -void tegra_clk_init_from_table(struct tegra_clk_init_table *table) -{ - for (; table->name; table++) - tegra_clk_init_one_from_table(table); -} - -void tegra_periph_reset_deassert(struct clk *c) -{ - struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c)); - BUG_ON(!clk->reset); - clk->reset(__clk_get_hw(c), false); -} -EXPORT_SYMBOL(tegra_periph_reset_deassert); - -void tegra_periph_reset_assert(struct clk *c) -{ - struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c)); - BUG_ON(!clk->reset); - clk->reset(__clk_get_hw(c), true); -} -EXPORT_SYMBOL(tegra_periph_reset_assert); - -/* Several extended clock configuration bits (e.g., clock routing, clock - * phase control) are included in PLL and peripheral clock source - * registers. */ -int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) -{ - int ret = 0; - struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c)); - - if (!clk->clk_cfg_ex) { - ret = -ENOSYS; - goto out; - } - ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting); - -out: - return ret; -} diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h deleted file mode 100644 index 2aa37f5..0000000 --- a/arch/arm/mach-tegra/clock.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/clock.h - * - * Copyright (C) 2010 Google, Inc. - * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved. - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_CLOCK_H -#define __MACH_TEGRA_CLOCK_H - -#include <linux/clk-provider.h> -#include <linux/clkdev.h> -#include <linux/list.h> - -#include <mach/clk.h> - -#define DIV_BUS (1 << 0) -#define DIV_U71 (1 << 1) -#define DIV_U71_FIXED (1 << 2) -#define DIV_2 (1 << 3) -#define DIV_U16 (1 << 4) -#define PLL_FIXED (1 << 5) -#define PLL_HAS_CPCON (1 << 6) -#define MUX (1 << 7) -#define PLLD (1 << 8) -#define PERIPH_NO_RESET (1 << 9) -#define PERIPH_NO_ENB (1 << 10) -#define PERIPH_EMC_ENB (1 << 11) -#define PERIPH_MANUAL_RESET (1 << 12) -#define PLL_ALT_MISC_REG (1 << 13) -#define PLLU (1 << 14) -#define PLLX (1 << 15) -#define MUX_PWM (1 << 16) -#define MUX8 (1 << 17) -#define DIV_U71_UART (1 << 18) -#define MUX_CLK_OUT (1 << 19) -#define PLLM (1 << 20) -#define DIV_U71_INT (1 << 21) -#define DIV_U71_IDLE (1 << 22) -#define ENABLE_ON_INIT (1 << 28) -#define PERIPH_ON_APB (1 << 29) - -struct clk_tegra; -#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw) - -struct clk_mux_sel { - struct clk *input; - u32 value; -}; - -struct clk_pll_freq_table { - unsigned long input_rate; - unsigned long output_rate; - u16 n; - u16 m; - u8 p; - u8 cpcon; -}; - -enum clk_state { - UNINITIALIZED = 0, - ON, - OFF, -}; - -struct clk_tegra { - /* node for master clocks list */ - struct list_head node; /* node for list of all clocks */ - struct clk_lookup lookup; - struct clk_hw hw; - - bool set; - unsigned long fixed_rate; - unsigned long max_rate; - unsigned long min_rate; - u32 flags; - const char *name; - - enum clk_state state; - u32 div; - u32 mul; - - u32 reg; - u32 reg_shift; - - struct list_head shared_bus_list; - - union { - struct { - unsigned int clk_num; - } periph; - struct { - unsigned long input_min; - unsigned long input_max; - unsigned long cf_min; - unsigned long cf_max; - unsigned long vco_min; - unsigned long vco_max; - const struct clk_pll_freq_table *freq_table; - int lock_delay; - unsigned long fixed_rate; - } pll; - struct { - u32 sel; - u32 reg_mask; - } mux; - struct { - struct clk *main; - struct clk *backup; - } cpu; - struct { - struct list_head node; - bool enabled; - unsigned long rate; - } shared_bus_user; - } u; - - void (*reset)(struct clk_hw *, bool); - int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32); -}; - -struct clk_duplicate { - const char *name; - struct clk_lookup lookup; -}; - -struct tegra_clk_init_table { - const char *name; - const char *parent; - unsigned long rate; - bool enabled; -}; - -void tegra_clk_add(struct clk *c); -void tegra2_init_clocks(void); -void tegra30_init_clocks(void); -struct clk *tegra_get_clock_by_name(const char *name); -void tegra_clk_init_from_table(struct tegra_clk_init_table *table); - -#endif diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 3599959..5449a3f 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -1,6 +1,7 @@ /* * arch/arm/mach-tegra/common.c * + * Copyright (c) 2013 NVIDIA Corporation. All rights reserved. * Copyright (C) 2010 Google, Inc. * * Author: @@ -22,13 +23,13 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/irqchip.h> +#include <linux/clk/tegra.h> #include <asm/hardware/cache-l2x0.h> #include <mach/powergate.h> #include "board.h" -#include "clock.h" #include "common.h" #include "fuse.h" #include "iomap.h" @@ -36,6 +37,7 @@ #include "apbio.h" #include "sleep.h" #include "pm.h" +#include "reset.h" /* * Storage for debug-macro.S's state. @@ -58,6 +60,7 @@ u32 tegra_uart_config[4] = { #ifdef CONFIG_OF void __init tegra_dt_init_irq(void) { + tegra_clocks_init(); tegra_init_irq(); irqchip_init(); } @@ -73,43 +76,6 @@ void tegra_assert_system_reset(char mode, const char *cmd) writel_relaxed(reg, reset); } -#ifdef CONFIG_ARCH_TEGRA_2x_SOC -static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { - /* name parent rate enabled */ - { "clk_m", NULL, 0, true }, - { "pll_p", "clk_m", 216000000, true }, - { "pll_p_out1", "pll_p", 28800000, true }, - { "pll_p_out2", "pll_p", 48000000, true }, - { "pll_p_out3", "pll_p", 72000000, true }, - { "pll_p_out4", "pll_p", 24000000, true }, - { "pll_c", "clk_m", 600000000, true }, - { "pll_c_out1", "pll_c", 120000000, true }, - { "sclk", "pll_c_out1", 120000000, true }, - { "hclk", "sclk", 120000000, true }, - { "pclk", "hclk", 60000000, true }, - { "csite", NULL, 0, true }, - { "emc", NULL, 0, true }, - { "cpu", NULL, 0, true }, - { NULL, NULL, 0, 0}, -}; -#endif - -#ifdef CONFIG_ARCH_TEGRA_3x_SOC -static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { - /* name parent rate enabled */ - { "clk_m", NULL, 0, true }, - { "pll_p", "pll_ref", 408000000, true }, - { "pll_p_out1", "pll_p", 9600000, true }, - { "pll_p_out4", "pll_p", 102000000, true }, - { "sclk", "pll_p_out4", 102000000, true }, - { "hclk", "sclk", 102000000, true }, - { "pclk", "hclk", 51000000, true }, - { "csite", NULL, 0, true }, - { NULL, NULL, 0, 0}, -}; -#endif - - static void __init tegra_init_cache(void) { #ifdef CONFIG_CACHE_L2X0 @@ -128,33 +94,39 @@ static void __init tegra_init_cache(void) } -#ifdef CONFIG_ARCH_TEGRA_2x_SOC -void __init tegra20_init_early(void) +static void __init tegra_init_early(void) { + tegra_cpu_reset_handler_init(); tegra_apb_io_init(); tegra_init_fuse(); - tegra2_init_clocks(); - tegra_clk_init_from_table(tegra20_clk_init_table); tegra_init_cache(); tegra_pmc_init(); tegra_powergate_init(); +} + +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +void __init tegra20_init_early(void) +{ + tegra_init_early(); tegra20_hotplug_init(); } #endif + #ifdef CONFIG_ARCH_TEGRA_3x_SOC void __init tegra30_init_early(void) { - tegra_apb_io_init(); - tegra_init_fuse(); - tegra30_init_clocks(); - tegra_clk_init_from_table(tegra30_clk_init_table); - tegra_init_cache(); - tegra_pmc_init(); - tegra_powergate_init(); + tegra_init_early(); tegra30_hotplug_init(); } #endif +#ifdef CONFIG_ARCH_TEGRA_114_SOC +void __init tegra114_init_early(void) +{ + tegra_init_early(); +} +#endif + void __init tegra_init_late(void) { tegra_powergate_debugfs_init(); diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h index 02f71b4..32f8eb3 100644 --- a/arch/arm/mach-tegra/common.h +++ b/arch/arm/mach-tegra/common.h @@ -1,4 +1,5 @@ extern struct smp_operations tegra_smp_ops; +extern int tegra_cpu_kill(unsigned int cpu); extern void tegra_cpu_die(unsigned int cpu); extern int tegra_cpu_disable(unsigned int cpu); diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c index a74d3c7..ebffed6 100644 --- a/arch/arm/mach-tegra/cpu-tegra.c +++ b/arch/arm/mach-tegra/cpu-tegra.c @@ -214,24 +214,6 @@ static int tegra_cpu_init(struct cpufreq_policy *policy) if (policy->cpu >= NUM_CPUS) return -EINVAL; - cpu_clk = clk_get_sys(NULL, "cpu"); - if (IS_ERR(cpu_clk)) - return PTR_ERR(cpu_clk); - - pll_x_clk = clk_get_sys(NULL, "pll_x"); - if (IS_ERR(pll_x_clk)) - return PTR_ERR(pll_x_clk); - - pll_p_clk = clk_get_sys(NULL, "pll_p"); - if (IS_ERR(pll_p_clk)) - return PTR_ERR(pll_p_clk); - - emc_clk = clk_get_sys("cpu", "emc"); - if (IS_ERR(emc_clk)) { - clk_put(cpu_clk); - return PTR_ERR(emc_clk); - } - clk_prepare_enable(emc_clk); clk_prepare_enable(cpu_clk); @@ -256,8 +238,6 @@ static int tegra_cpu_exit(struct cpufreq_policy *policy) { cpufreq_frequency_table_cpuinfo(policy, freq_table); clk_disable_unprepare(emc_clk); - clk_put(emc_clk); - clk_put(cpu_clk); return 0; } @@ -278,12 +258,32 @@ static struct cpufreq_driver tegra_cpufreq_driver = { static int __init tegra_cpufreq_init(void) { + cpu_clk = clk_get_sys(NULL, "cpu"); + if (IS_ERR(cpu_clk)) + return PTR_ERR(cpu_clk); + + pll_x_clk = clk_get_sys(NULL, "pll_x"); + if (IS_ERR(pll_x_clk)) + return PTR_ERR(pll_x_clk); + + pll_p_clk = clk_get_sys(NULL, "pll_p_cclk"); + if (IS_ERR(pll_p_clk)) + return PTR_ERR(pll_p_clk); + + emc_clk = clk_get_sys("cpu", "emc"); + if (IS_ERR(emc_clk)) { + clk_put(cpu_clk); + return PTR_ERR(emc_clk); + } + return cpufreq_register_driver(&tegra_cpufreq_driver); } static void __exit tegra_cpufreq_exit(void) { cpufreq_unregister_driver(&tegra_cpufreq_driver); + clk_put(emc_clk); + clk_put(cpu_clk); } diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c new file mode 100644 index 0000000..0f4e8c4 --- /dev/null +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/cpuidle.h> + +#include <asm/cpuidle.h> + +static struct cpuidle_driver tegra_idle_driver = { + .name = "tegra_idle", + .owner = THIS_MODULE, + .en_core_tk_irqen = 1, + .state_count = 1, + .states = { + [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), + }, +}; + +static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device); + +int __init tegra114_cpuidle_init(void) +{ + int ret; + unsigned int cpu; + struct cpuidle_device *dev; + struct cpuidle_driver *drv = &tegra_idle_driver; + + ret = cpuidle_register_driver(&tegra_idle_driver); + if (ret) { + pr_err("CPUidle driver registration failed\n"); + return ret; + } + + for_each_possible_cpu(cpu) { + dev = &per_cpu(tegra_idle_device, cpu); + dev->cpu = cpu; + + dev->state_count = drv->state_count; + ret = cpuidle_register_device(dev); + if (ret) { + pr_err("CPU%u: CPUidle device registration failed\n", + cpu); + return ret; + } + } + return 0; +} diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index d32e8b0..825ced4 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c @@ -22,21 +22,199 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/cpuidle.h> +#include <linux/cpu_pm.h> +#include <linux/clockchips.h> +#include <linux/clk/tegra.h> #include <asm/cpuidle.h> +#include <asm/proc-fns.h> +#include <asm/suspend.h> +#include <asm/smp_plat.h> + +#include "pm.h" +#include "sleep.h" +#include "iomap.h" +#include "irq.h" +#include "flowctrl.h" + +#ifdef CONFIG_PM_SLEEP +static bool abort_flag; +static atomic_t abort_barrier; +static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index); +#endif + +static struct cpuidle_state tegra_idle_states[] = { + [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), +#ifdef CONFIG_PM_SLEEP + [1] = { + .enter = tegra20_idle_lp2_coupled, + .exit_latency = 5000, + .target_residency = 10000, + .power_usage = 0, + .flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_COUPLED, + .name = "powered-down", + .desc = "CPU power gated", + }, +#endif +}; static struct cpuidle_driver tegra_idle_driver = { .name = "tegra_idle", .owner = THIS_MODULE, .en_core_tk_irqen = 1, - .state_count = 1, - .states = { - [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), - }, }; static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device); +#ifdef CONFIG_PM_SLEEP +#ifdef CONFIG_SMP +static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); + +static int tegra20_reset_sleeping_cpu_1(void) +{ + int ret = 0; + + tegra_pen_lock(); + + if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE) + tegra20_cpu_shutdown(1); + else + ret = -EINVAL; + + tegra_pen_unlock(); + + return ret; +} + +static void tegra20_wake_cpu1_from_reset(void) +{ + tegra_pen_lock(); + + tegra20_cpu_clear_resettable(); + + /* enable cpu clock on cpu */ + tegra_enable_cpu_clock(1); + + /* take the CPU out of reset */ + tegra_cpu_out_of_reset(1); + + /* unhalt the cpu */ + flowctrl_write_cpu_halt(1, 0); + + tegra_pen_unlock(); +} + +static int tegra20_reset_cpu_1(void) +{ + if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1()) + return 0; + + tegra20_wake_cpu1_from_reset(); + return -EBUSY; +} +#else +static inline void tegra20_wake_cpu1_from_reset(void) +{ +} + +static inline int tegra20_reset_cpu_1(void) +{ + return 0; +} +#endif + +static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + struct cpuidle_state *state = &drv->states[index]; + u32 cpu_on_time = state->exit_latency; + u32 cpu_off_time = state->target_residency - state->exit_latency; + + while (tegra20_cpu_is_resettable_soon()) + cpu_relax(); + + if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready()) + return false; + + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); + + tegra_idle_lp2_last(cpu_on_time, cpu_off_time); + + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); + + if (cpu_online(1)) + tegra20_wake_cpu1_from_reset(); + + return true; +} + +#ifdef CONFIG_SMP +static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); + + cpu_suspend(0, tegra20_sleep_cpu_secondary_finish); + + tegra20_cpu_clear_resettable(); + + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); + + return true; +} +#else +static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + return true; +} +#endif + +static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) +{ + u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu; + bool entered_lp2 = false; + + if (tegra_pending_sgi()) + ACCESS_ONCE(abort_flag) = true; + + cpuidle_coupled_parallel_barrier(dev, &abort_barrier); + + if (abort_flag) { + cpuidle_coupled_parallel_barrier(dev, &abort_barrier); + abort_flag = false; /* clean flag for next coming */ + return -EINTR; + } + + local_fiq_disable(); + + tegra_set_cpu_in_lp2(cpu); + cpu_pm_enter(); + + if (cpu == 0) + entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index); + else + entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index); + + cpu_pm_exit(); + tegra_clear_cpu_in_lp2(cpu); + + local_fiq_enable(); + + smp_rmb(); + + return entered_lp2 ? index : 0; +} +#endif + int __init tegra20_cpuidle_init(void) { int ret; @@ -44,6 +222,14 @@ int __init tegra20_cpuidle_init(void) struct cpuidle_device *dev; struct cpuidle_driver *drv = &tegra_idle_driver; +#ifdef CONFIG_PM_SLEEP + tegra_tear_down_cpu = tegra20_tear_down_cpu; +#endif + + drv->state_count = ARRAY_SIZE(tegra_idle_states); + memcpy(drv->states, tegra_idle_states, + drv->state_count * sizeof(drv->states[0])); + ret = cpuidle_register_driver(&tegra_idle_driver); if (ret) { pr_err("CPUidle driver registration failed\n"); @@ -53,6 +239,9 @@ int __init tegra20_cpuidle_init(void) for_each_possible_cpu(cpu) { dev = &per_cpu(tegra_idle_device, cpu); dev->cpu = cpu; +#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED + dev->coupled_cpus = *cpu_possible_mask; +#endif dev->state_count = drv->state_count; ret = cpuidle_register_device(dev); diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index 5e8cbf5..8b50cf4 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c @@ -24,6 +24,7 @@ #include <linux/cpuidle.h> #include <linux/cpu_pm.h> #include <linux/clockchips.h> +#include <linux/clk/tegra.h> #include <asm/cpuidle.h> #include <asm/proc-fns.h> @@ -32,7 +33,6 @@ #include "pm.h" #include "sleep.h" -#include "tegra_cpu_car.h" #ifdef CONFIG_PM_SLEEP static int tegra30_idle_lp2(struct cpuidle_device *dev, @@ -121,9 +121,9 @@ static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, } #endif -static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) +static int tegra30_idle_lp2(struct cpuidle_device *dev, + struct cpuidle_driver *drv, + int index) { u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu; bool entered_lp2 = false; diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index d065139..4b744c4 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -38,6 +38,9 @@ static int __init tegra_cpuidle_init(void) case TEGRA30: ret = tegra30_cpuidle_init(); break; + case TEGRA114: + ret = tegra114_cpuidle_init(); + break; default: ret = -ENODEV; break; diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h index 496204d..d733f75d 100644 --- a/arch/arm/mach-tegra/cpuidle.h +++ b/arch/arm/mach-tegra/cpuidle.h @@ -29,4 +29,10 @@ int tegra30_cpuidle_init(void); static inline int tegra30_cpuidle_init(void) { return -ENODEV; } #endif +#ifdef CONFIG_ARCH_TEGRA_114_SOC +int tegra114_cpuidle_init(void); +#else +static inline int tegra114_cpuidle_init(void) { return -ENODEV; } +#endif + #endif diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index a2250dd..b477ef3 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c @@ -25,15 +25,16 @@ #include "flowctrl.h" #include "iomap.h" +#include "fuse.h" -u8 flowctrl_offset_halt_cpu[] = { +static u8 flowctrl_offset_halt_cpu[] = { FLOW_CTRL_HALT_CPU0_EVENTS, FLOW_CTRL_HALT_CPU1_EVENTS, FLOW_CTRL_HALT_CPU1_EVENTS + 8, FLOW_CTRL_HALT_CPU1_EVENTS + 16, }; -u8 flowctrl_offset_cpu_csr[] = { +static u8 flowctrl_offset_cpu_csr[] = { FLOW_CTRL_CPU0_CSR, FLOW_CTRL_CPU1_CSR, FLOW_CTRL_CPU1_CSR + 8, @@ -75,11 +76,26 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid) int i; reg = flowctrl_read_cpu_csr(cpuid); - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */ + switch (tegra_chip_id) { + case TEGRA20: + /* clear wfe bitmap */ + reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; + /* clear wfi bitmap */ + reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; + /* pwr gating on wfe */ + reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; + break; + case TEGRA30: + /* clear wfe bitmap */ + reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; + /* clear wfi bitmap */ + reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; + /* pwr gating on wfi */ + reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; + break; + } reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ - reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; /* pwr gating on wfi */ reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ flowctrl_write_cpu_csr(cpuid, reg); @@ -99,8 +115,20 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid) /* Disable powergating via flow controller for CPU0 */ reg = flowctrl_read_cpu_csr(cpuid); - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */ - reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */ + switch (tegra_chip_id) { + case TEGRA20: + /* clear wfe bitmap */ + reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; + /* clear wfi bitmap */ + reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; + break; + case TEGRA30: + /* clear wfe bitmap */ + reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; + /* clear wfi bitmap */ + reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; + break; + } reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */ reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */ reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h index 0798dec..67eab56 100644 --- a/arch/arm/mach-tegra/flowctrl.h +++ b/arch/arm/mach-tegra/flowctrl.h @@ -34,6 +34,10 @@ #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 #define FLOW_CTRL_CPU1_CSR 0x18 +#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4) +#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4) +#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0 + #define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8) #define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4) #define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8) diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index 8121742..f7db078 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -20,6 +20,7 @@ #include <linux/kernel.h> #include <linux/io.h> #include <linux/export.h> +#include <linux/tegra-soc.h> #include "fuse.h" #include "iomap.h" @@ -105,6 +106,11 @@ static void tegra_get_process_id(void) tegra_core_process_id = (reg >> 12) & 3; } +u32 tegra_read_chipid(void) +{ + return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); +} + void tegra_init_fuse(void) { u32 id; @@ -119,7 +125,7 @@ void tegra_init_fuse(void) reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; - id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); + id = tegra_read_chipid(); tegra_chip_id = (id >> 8) & 0xff; switch (tegra_chip_id) { diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h index ff1383d..da78434 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h @@ -37,6 +37,7 @@ enum tegra_revision { #define TEGRA20 0x20 #define TEGRA30 0x30 +#define TEGRA114 0x35 extern int tegra_sku_id; extern int tegra_cpu_process_id; diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 4a317fa..fd473f2 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -1,66 +1,9 @@ #include <linux/linkage.h> #include <linux/init.h> -#include <asm/cache.h> -#include <asm/asm-offsets.h> -#include <asm/hardware/cache-l2x0.h> - -#include "flowctrl.h" -#include "iomap.h" -#include "reset.h" #include "sleep.h" -#define APB_MISC_GP_HIDREV 0x804 -#define PMC_SCRATCH41 0x140 - -#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) - .section ".text.head", "ax" - __CPUINIT - -/* - * Tegra specific entry point for secondary CPUs. - * The secondary kernel init calls v7_flush_dcache_all before it enables - * the L1; however, the L1 comes out of reset in an undefined state, so - * the clean + invalidate performed by v7_flush_dcache_all causes a bunch - * of cache lines with uninitialized data and uninitialized tags to get - * written out to memory, which does really unpleasant things to the main - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - */ -ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) - mcr p15, 0, r5, c7, c6, 2 - bgt 2b - cmp r2, #0 - bgt 1b - dsb - isb - mov pc, lr -ENDPROC(v7_invalidate_l1) - ENTRY(tegra_secondary_startup) bl v7_invalidate_l1 @@ -69,210 +12,3 @@ ENTRY(tegra_secondary_startup) mcr p14, 0, r0, c7, c12, 6 b secondary_startup ENDPROC(tegra_secondary_startup) - -#ifdef CONFIG_PM_SLEEP -/* - * tegra_resume - * - * CPU boot vector when restarting the a CPU following - * an LP2 transition. Also branched to by LP0 and LP1 resume after - * re-enabling sdram. - */ -ENTRY(tegra_resume) - bl v7_invalidate_l1 - /* Enable coresight */ - mov32 r0, 0xC5ACCE55 - mcr p14, 0, r0, c7, c12, 6 - - cpu_id r0 - cmp r0, #0 @ CPU0? - bne cpu_resume @ no - -#ifdef CONFIG_ARCH_TEGRA_3x_SOC - /* Are we on Tegra20? */ - mov32 r6, TEGRA_APB_MISC_BASE - ldr r0, [r6, #APB_MISC_GP_HIDREV] - and r0, r0, #0xff00 - cmp r0, #(0x20 << 8) - beq 1f @ Yes - /* Clear the flow controller flags for this CPU. */ - mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR - ldr r1, [r2] - /* Clear event & intr flag */ - orr r1, r1, \ - #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG - movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps - bic r1, r1, r0 - str r1, [r2] -1: -#endif - -#ifdef CONFIG_HAVE_ARM_SCU - /* enable SCU */ - mov32 r0, TEGRA_ARM_PERIF_BASE - ldr r1, [r0] - orr r1, r1, #1 - str r1, [r0] -#endif - - /* L2 cache resume & re-enable */ - l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr - - b cpu_resume -ENDPROC(tegra_resume) -#endif - -#ifdef CONFIG_CACHE_L2X0 - .globl l2x0_saved_regs_addr -l2x0_saved_regs_addr: - .long 0 -#endif - - .align L1_CACHE_SHIFT -ENTRY(__tegra_cpu_reset_handler_start) - -/* - * __tegra_cpu_reset_handler: - * - * Common handler for all CPU reset events. - * - * Register usage within the reset handler: - * - * R7 = CPU present (to the OS) mask - * R8 = CPU in LP1 state mask - * R9 = CPU in LP2 state mask - * R10 = CPU number - * R11 = CPU mask - * R12 = pointer to reset handler data - * - * NOTE: This code is copied to IRAM. All code and data accesses - * must be position-independent. - */ - - .align L1_CACHE_SHIFT -ENTRY(__tegra_cpu_reset_handler) - - cpsid aif, 0x13 @ SVC mode, interrupts disabled - mrc p15, 0, r10, c0, c0, 5 @ MPIDR - and r10, r10, #0x3 @ R10 = CPU number - mov r11, #1 - mov r11, r11, lsl r10 @ R11 = CPU mask - adr r12, __tegra_cpu_reset_handler_data - -#ifdef CONFIG_SMP - /* Does the OS know about this CPU? */ - ldr r7, [r12, #RESET_DATA(MASK_PRESENT)] - tst r7, r11 @ if !present - bleq __die @ CPU not present (to OS) -#endif - -#ifdef CONFIG_ARCH_TEGRA_2x_SOC - /* Are we on Tegra20? */ - mov32 r6, TEGRA_APB_MISC_BASE - ldr r0, [r6, #APB_MISC_GP_HIDREV] - and r0, r0, #0xff00 - cmp r0, #(0x20 << 8) - bne 1f - /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ - mov32 r6, TEGRA_PMC_BASE - mov r0, #0 - cmp r10, #0 - strne r0, [r6, #PMC_SCRATCH41] -1: -#endif - - /* Waking up from LP2? */ - ldr r9, [r12, #RESET_DATA(MASK_LP2)] - tst r9, r11 @ if in_lp2 - beq __is_not_lp2 - ldr lr, [r12, #RESET_DATA(STARTUP_LP2)] - cmp lr, #0 - bleq __die @ no LP2 startup handler - bx lr - -__is_not_lp2: - -#ifdef CONFIG_SMP - /* - * Can only be secondary boot (initial or hotplug) but CPU 0 - * cannot be here. - */ - cmp r10, #0 - bleq __die @ CPU0 cannot be here - ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)] - cmp lr, #0 - bleq __die @ no secondary startup handler - bx lr -#endif - -/* - * We don't know why the CPU reset. Just kill it. - * The LR register will contain the address we died at + 4. - */ - -__die: - sub lr, lr, #4 - mov32 r7, TEGRA_PMC_BASE - str lr, [r7, #PMC_SCRATCH41] - - mov32 r7, TEGRA_CLK_RESET_BASE - - /* Are we on Tegra20? */ - mov32 r6, TEGRA_APB_MISC_BASE - ldr r0, [r6, #APB_MISC_GP_HIDREV] - and r0, r0, #0xff00 - cmp r0, #(0x20 << 8) - bne 1f - -#ifdef CONFIG_ARCH_TEGRA_2x_SOC - mov32 r0, 0x1111 - mov r1, r0, lsl r10 - str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET -#endif -1: -#ifdef CONFIG_ARCH_TEGRA_3x_SOC - mov32 r6, TEGRA_FLOW_CTRL_BASE - - cmp r10, #0 - moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS - moveq r2, #FLOW_CTRL_CPU0_CSR - movne r1, r10, lsl #3 - addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8) - addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8) - - /* Clear CPU "event" and "interrupt" flags and power gate - it when halting but not before it is in the "WFI" state. */ - ldr r0, [r6, +r2] - orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG - orr r0, r0, #FLOW_CTRL_CSR_ENABLE - str r0, [r6, +r2] - - /* Unconditionally halt this CPU */ - mov r0, #FLOW_CTRL_WAITEVENT - str r0, [r6, +r1] - ldr r0, [r6, +r1] @ memory barrier - - dsb - isb - wfi @ CPU should be power gated here - - /* If the CPU didn't power gate above just kill it's clock. */ - - mov r0, r11, lsl #8 - str r0, [r7, #348] @ CLK_CPU_CMPLX_SET -#endif - - /* If the CPU still isn't dead, just spin here. */ - b . -ENDPROC(__tegra_cpu_reset_handler) - - .align L1_CACHE_SHIFT - .type __tegra_cpu_reset_handler_data, %object - .globl __tegra_cpu_reset_handler_data -__tegra_cpu_reset_handler_data: - .rept TEGRA_RESET_DATA_SIZE - .long 0 - .endr - .align L1_CACHE_SHIFT - -ENTRY(__tegra_cpu_reset_handler_end) diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index dca5141..a599f6e 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c @@ -10,15 +10,26 @@ */ #include <linux/kernel.h> #include <linux/smp.h> +#include <linux/clk/tegra.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> #include "sleep.h" -#include "tegra_cpu_car.h" static void (*tegra_hotplug_shutdown)(void); +int tegra_cpu_kill(unsigned cpu) +{ + cpu = cpu_logical_map(cpu); + + /* Clock gate the CPU */ + tegra_wait_cpu_in_reset(cpu); + tegra_disable_cpu_clock(cpu); + + return 1; +} + /* * platform-specific code to shutdown a CPU * @@ -26,18 +37,12 @@ static void (*tegra_hotplug_shutdown)(void); */ void __ref tegra_cpu_die(unsigned int cpu) { - cpu = cpu_logical_map(cpu); - - /* Flush the L1 data cache. */ - flush_cache_all(); + /* Clean L1 data cache */ + tegra_disable_clean_inv_dcache(); /* Shut down the current CPU. */ tegra_hotplug_shutdown(); - /* Clock gate the CPU */ - tegra_wait_cpu_in_reset(cpu); - tegra_disable_cpu_clock(cpu); - /* Should never return here. */ BUG(); } diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h deleted file mode 100644 index 95f3a54..0000000 --- a/arch/arm/mach-tegra/include/mach/clk.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/clk.h - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Erik Gilling <konkers@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_CLK_H -#define __MACH_CLK_H - -struct clk; - -enum tegra_clk_ex_param { - TEGRA_CLK_VI_INP_SEL, - TEGRA_CLK_DTV_INVERT, - TEGRA_CLK_NAND_PAD_DIV2_ENB, - TEGRA_CLK_PLLD_CSI_OUT_ENB, - TEGRA_CLK_PLLD_DSI_OUT_ENB, - TEGRA_CLK_PLLD_MIPI_MUX_SEL, -}; - -void tegra_periph_reset_deassert(struct clk *c); -void tegra_periph_reset_assert(struct clk *c); - -#ifndef CONFIG_COMMON_CLK -unsigned long clk_get_rate_all_locked(struct clk *c); -#endif - -void tegra2_sdmmc_tap_delay(struct clk *c, int delay); -int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting); - -#endif diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h index db8be51..399fbca 100644 --- a/arch/arm/mach-tegra/iomap.h +++ b/arch/arm/mach-tegra/iomap.h @@ -240,15 +240,6 @@ #define TEGRA_CSITE_BASE 0x70040000 #define TEGRA_CSITE_SIZE SZ_256K -#define TEGRA_USB_BASE 0xC5000000 -#define TEGRA_USB_SIZE SZ_16K - -#define TEGRA_USB2_BASE 0xC5004000 -#define TEGRA_USB2_SIZE SZ_16K - -#define TEGRA_USB3_BASE 0xC5008000 -#define TEGRA_USB3_SIZE SZ_16K - #define TEGRA_SDMMC1_BASE 0xC8000000 #define TEGRA_SDMMC1_SIZE SZ_512 diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 2ff2128..1952e82 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -44,6 +44,8 @@ #define FIRST_LEGACY_IRQ 32 +#define SGI_MASK 0xFFFF + static int num_ictlrs; static void __iomem *ictlr_reg_base[] = { @@ -54,6 +56,19 @@ static void __iomem *ictlr_reg_base[] = { IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE), }; +bool tegra_pending_sgi(void) +{ + u32 pending_set; + void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE); + + pending_set = readl_relaxed(distbase + GIC_DIST_PENDING_SET); + + if (pending_set & SGI_MASK) + return true; + + return false; +} + static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg) { void __iomem *base; diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h new file mode 100644 index 0000000..5142649 --- /dev/null +++ b/arch/arm/mach-tegra/irq.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __TEGRA_IRQ_H +#define __TEGRA_IRQ_H + +bool tegra_pending_sgi(void); + +#endif diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index bffcd64..b60165f 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -33,11 +33,11 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/export.h> +#include <linux/clk/tegra.h> #include <asm/sizes.h> #include <asm/mach/pci.h> -#include <mach/clk.h> #include <mach/powergate.h> #include "board.h" diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 18d7290..2c6b3d5 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -19,24 +19,25 @@ #include <linux/smp.h> #include <linux/io.h> #include <linux/irqchip/arm-gic.h> +#include <linux/clk/tegra.h> #include <asm/cacheflush.h> #include <asm/mach-types.h> #include <asm/smp_scu.h> +#include <asm/smp_plat.h> #include <mach/powergate.h> #include "fuse.h" #include "flowctrl.h" #include "reset.h" -#include "tegra_cpu_car.h" #include "common.h" #include "iomap.h" extern void tegra_secondary_startup(void); -static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); +static cpumask_t tegra_cpu_init_mask; #define EVP_CPU_RESET_VECTOR \ (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) @@ -50,6 +51,7 @@ static void __cpuinit tegra_secondary_init(unsigned int cpu) */ gic_secondary_init(0); + cpumask_set_cpu(cpu, &tegra_cpu_init_mask); } static int tegra20_power_up_cpu(unsigned int cpu) @@ -72,14 +74,42 @@ static int tegra30_power_up_cpu(unsigned int cpu) if (pwrgateid < 0) return pwrgateid; - /* If this is the first boot, toggle powergates directly. */ + /* + * The power up sequence of cold boot CPU and warm boot CPU + * was different. + * + * For warm boot CPU that was resumed from CPU hotplug, the + * power will be resumed automatically after un-halting the + * flow controller of the warm boot CPU. We need to wait for + * the confirmaiton that the CPU is powered then removing + * the IO clamps. + * For cold boot CPU, do not wait. After the cold boot CPU be + * booted, it will run to tegra_secondary_init() and set + * tegra_cpu_init_mask which influences what tegra30_power_up_cpu() + * next time around. + */ + if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { + timeout = jiffies + msecs_to_jiffies(50); + do { + if (!tegra_powergate_is_powered(pwrgateid)) + goto remove_clamps; + udelay(10); + } while (time_before(jiffies, timeout)); + } + + /* + * The power status of the cold boot CPU is power gated as + * default. To power up the cold boot CPU, the power should + * be un-gated by un-toggling the power gate register + * manually. + */ if (!tegra_powergate_is_powered(pwrgateid)) { ret = tegra_powergate_power_on(pwrgateid); if (ret) return ret; /* Wait for the power to come up. */ - timeout = jiffies + 10*HZ; + timeout = jiffies + msecs_to_jiffies(100); while (tegra_powergate_is_powered(pwrgateid)) { if (time_after(jiffies, timeout)) return -ETIMEDOUT; @@ -87,6 +117,7 @@ static int tegra30_power_up_cpu(unsigned int cpu) } } +remove_clamps: /* CPU partition is powered. Enable the CPU clock. */ tegra_enable_cpu_clock(cpu); udelay(10); @@ -105,6 +136,8 @@ static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct * { int status; + cpu = cpu_logical_map(cpu); + /* * Force the CPU into reset. The CPU must remain in reset when the * flow controller state is cleared (which will cause the flow @@ -143,36 +176,21 @@ done: return status; } -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -static void __init tegra_smp_init_cpus(void) -{ - unsigned int i, ncores = scu_get_core_count(scu_base); - - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; - } - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); -} - static void __init tegra_smp_prepare_cpus(unsigned int max_cpus) { - tegra_cpu_reset_handler_init(); - scu_enable(scu_base); + /* Always mark the boot CPU (CPU0) as initialized. */ + cpumask_set_cpu(0, &tegra_cpu_init_mask); + + if (scu_a9_has_base()) + scu_enable(IO_ADDRESS(scu_a9_get_base())); } struct smp_operations tegra_smp_ops __initdata = { - .smp_init_cpus = tegra_smp_init_cpus, .smp_prepare_cpus = tegra_smp_prepare_cpus, .smp_secondary_init = tegra_secondary_init, .smp_boot_secondary = tegra_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU + .cpu_kill = tegra_cpu_kill, .cpu_die = tegra_cpu_die, .cpu_disable = tegra_cpu_disable, #endif diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 1b11707..523604d 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -24,6 +24,7 @@ #include <linux/cpu_pm.h> #include <linux/clk.h> #include <linux/err.h> +#include <linux/clk/tegra.h> #include <asm/smp_plat.h> #include <asm/cacheflush.h> @@ -35,8 +36,8 @@ #include "iomap.h" #include "reset.h" #include "flowctrl.h" +#include "fuse.h" #include "sleep.h" -#include "tegra_cpu_car.h" #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ @@ -148,7 +149,7 @@ static void suspend_cpu_complex(void) save_cpu_arch_register(); } -void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id) +void tegra_clear_cpu_in_lp2(int phy_cpu_id) { u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; @@ -160,7 +161,7 @@ void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id) spin_unlock(&tegra_lp2_lock); } -bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id) +bool tegra_set_cpu_in_lp2(int phy_cpu_id) { bool last_cpu = false; cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; @@ -173,6 +174,8 @@ bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id) if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) last_cpu = true; + else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1) + tegra20_cpu_set_resettable_soon(); spin_unlock(&tegra_lp2_lock); return last_cpu; diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 2cc1185..c6bc8f8 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -26,8 +26,8 @@ #include <linux/io.h> #include <linux/seq_file.h> #include <linux/spinlock.h> +#include <linux/clk/tegra.h> -#include <mach/clk.h> #include <mach/powergate.h> #include "fuse.h" diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S new file mode 100644 index 0000000..54382ce --- /dev/null +++ b/arch/arm/mach-tegra/reset-handler.S @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/linkage.h> +#include <linux/init.h> + +#include <asm/cache.h> +#include <asm/asm-offsets.h> +#include <asm/hardware/cache-l2x0.h> + +#include "flowctrl.h" +#include "iomap.h" +#include "reset.h" +#include "sleep.h" + +#define APB_MISC_GP_HIDREV 0x804 +#define PMC_SCRATCH41 0x140 + +#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) + +#ifdef CONFIG_PM_SLEEP +/* + * tegra_resume + * + * CPU boot vector when restarting the a CPU following + * an LP2 transition. Also branched to by LP0 and LP1 resume after + * re-enabling sdram. + */ +ENTRY(tegra_resume) + bl v7_invalidate_l1 + /* Enable coresight */ + mov32 r0, 0xC5ACCE55 + mcr p14, 0, r0, c7, c12, 6 + + cpu_id r0 + cmp r0, #0 @ CPU0? + bne cpu_resume @ no + +#ifdef CONFIG_ARCH_TEGRA_3x_SOC + /* Are we on Tegra20? */ + mov32 r6, TEGRA_APB_MISC_BASE + ldr r0, [r6, #APB_MISC_GP_HIDREV] + and r0, r0, #0xff00 + cmp r0, #(0x20 << 8) + beq 1f @ Yes + /* Clear the flow controller flags for this CPU. */ + mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR + ldr r1, [r2] + /* Clear event & intr flag */ + orr r1, r1, \ + #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG + movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps + bic r1, r1, r0 + str r1, [r2] +1: +#endif + +#ifdef CONFIG_HAVE_ARM_SCU + /* enable SCU */ + mov32 r0, TEGRA_ARM_PERIF_BASE + ldr r1, [r0] + orr r1, r1, #1 + str r1, [r0] +#endif + + /* L2 cache resume & re-enable */ + l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr + + b cpu_resume +ENDPROC(tegra_resume) +#endif + +#ifdef CONFIG_CACHE_L2X0 + .globl l2x0_saved_regs_addr +l2x0_saved_regs_addr: + .long 0 +#endif + + .align L1_CACHE_SHIFT +ENTRY(__tegra_cpu_reset_handler_start) + +/* + * __tegra_cpu_reset_handler: + * + * Common handler for all CPU reset events. + * + * Register usage within the reset handler: + * + * R7 = CPU present (to the OS) mask + * R8 = CPU in LP1 state mask + * R9 = CPU in LP2 state mask + * R10 = CPU number + * R11 = CPU mask + * R12 = pointer to reset handler data + * + * NOTE: This code is copied to IRAM. All code and data accesses + * must be position-independent. + */ + + .align L1_CACHE_SHIFT +ENTRY(__tegra_cpu_reset_handler) + + cpsid aif, 0x13 @ SVC mode, interrupts disabled + mrc p15, 0, r10, c0, c0, 5 @ MPIDR + and r10, r10, #0x3 @ R10 = CPU number + mov r11, #1 + mov r11, r11, lsl r10 @ R11 = CPU mask + adr r12, __tegra_cpu_reset_handler_data + +#ifdef CONFIG_SMP + /* Does the OS know about this CPU? */ + ldr r7, [r12, #RESET_DATA(MASK_PRESENT)] + tst r7, r11 @ if !present + bleq __die @ CPU not present (to OS) +#endif + +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + /* Are we on Tegra20? */ + mov32 r6, TEGRA_APB_MISC_BASE + ldr r0, [r6, #APB_MISC_GP_HIDREV] + and r0, r0, #0xff00 + cmp r0, #(0x20 << 8) + bne 1f + /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ + mov32 r6, TEGRA_PMC_BASE + mov r0, #0 + cmp r10, #0 + strne r0, [r6, #PMC_SCRATCH41] +1: +#endif + + /* Waking up from LP2? */ + ldr r9, [r12, #RESET_DATA(MASK_LP2)] + tst r9, r11 @ if in_lp2 + beq __is_not_lp2 + ldr lr, [r12, #RESET_DATA(STARTUP_LP2)] + cmp lr, #0 + bleq __die @ no LP2 startup handler + bx lr + +__is_not_lp2: + +#ifdef CONFIG_SMP + /* + * Can only be secondary boot (initial or hotplug) but CPU 0 + * cannot be here. + */ + cmp r10, #0 + bleq __die @ CPU0 cannot be here + ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)] + cmp lr, #0 + bleq __die @ no secondary startup handler + bx lr +#endif + +/* + * We don't know why the CPU reset. Just kill it. + * The LR register will contain the address we died at + 4. + */ + +__die: + sub lr, lr, #4 + mov32 r7, TEGRA_PMC_BASE + str lr, [r7, #PMC_SCRATCH41] + + mov32 r7, TEGRA_CLK_RESET_BASE + + /* Are we on Tegra20? */ + mov32 r6, TEGRA_APB_MISC_BASE + ldr r0, [r6, #APB_MISC_GP_HIDREV] + and r0, r0, #0xff00 + cmp r0, #(0x20 << 8) + bne 1f + +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + mov32 r0, 0x1111 + mov r1, r0, lsl r10 + str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET +#endif +1: +#ifdef CONFIG_ARCH_TEGRA_3x_SOC + mov32 r6, TEGRA_FLOW_CTRL_BASE + + cmp r10, #0 + moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS + moveq r2, #FLOW_CTRL_CPU0_CSR + movne r1, r10, lsl #3 + addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8) + addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8) + + /* Clear CPU "event" and "interrupt" flags and power gate + it when halting but not before it is in the "WFI" state. */ + ldr r0, [r6, +r2] + orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG + orr r0, r0, #FLOW_CTRL_CSR_ENABLE + str r0, [r6, +r2] + + /* Unconditionally halt this CPU */ + mov r0, #FLOW_CTRL_WAITEVENT + str r0, [r6, +r1] + ldr r0, [r6, +r1] @ memory barrier + + dsb + isb + wfi @ CPU should be power gated here + + /* If the CPU didn't power gate above just kill it's clock. */ + + mov r0, r11, lsl #8 + str r0, [r7, #348] @ CLK_CPU_CMPLX_SET +#endif + + /* If the CPU still isn't dead, just spin here. */ + b . +ENDPROC(__tegra_cpu_reset_handler) + + .align L1_CACHE_SHIFT + .type __tegra_cpu_reset_handler_data, %object + .globl __tegra_cpu_reset_handler_data +__tegra_cpu_reset_handler_data: + .rept TEGRA_RESET_DATA_SIZE + .long 0 + .endr + .align L1_CACHE_SHIFT + +ENTRY(__tegra_cpu_reset_handler_end) diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 3fd89ec..1ac434e 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -75,7 +75,7 @@ void __init tegra_cpu_reset_handler_init(void) #ifdef CONFIG_SMP __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = - *((u32 *)cpu_present_mask); + *((u32 *)cpu_possible_mask); __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = virt_to_phys((void *)tegra_secondary_startup); #endif diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index 72ce709..9f6bfaf 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -21,6 +21,8 @@ #include <linux/linkage.h> #include <asm/assembler.h> +#include <asm/proc-fns.h> +#include <asm/cp15.h> #include "sleep.h" #include "flowctrl.h" @@ -33,9 +35,6 @@ * should never return */ ENTRY(tegra20_hotplug_shutdown) - /* Turn off SMP coherency */ - exit_smp r4, r5 - /* Put this CPU down */ cpu_id r0 bl tegra20_cpu_shutdown @@ -58,6 +57,9 @@ ENDPROC(tegra20_hotplug_shutdown) ENTRY(tegra20_cpu_shutdown) cmp r0, #0 moveq pc, lr @ must not be called for CPU 0 + mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41 + mov r12, #CPU_RESETTABLE + str r12, [r1] cpu_to_halt_reg r1, r0 ldr r3, =TEGRA_FLOW_CTRL_VIRT @@ -78,3 +80,198 @@ ENTRY(tegra20_cpu_shutdown) mov pc, lr ENDPROC(tegra20_cpu_shutdown) #endif + +#ifdef CONFIG_PM_SLEEP +/* + * tegra_pen_lock + * + * spinlock implementation with no atomic test-and-set and no coherence + * using Peterson's algorithm on strongly-ordered registers + * used to synchronize a cpu waking up from wfi with entering lp2 on idle + * + * The reference link of Peterson's algorithm: + * http://en.wikipedia.org/wiki/Peterson's_algorithm + * + * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm) + * on cpu 0: + * r2 = flag[0] (in SCRATCH38) + * r3 = flag[1] (in SCRATCH39) + * on cpu1: + * r2 = flag[1] (in SCRATCH39) + * r3 = flag[0] (in SCRATCH38) + * + * must be called with MMU on + * corrupts r0-r3, r12 + */ +ENTRY(tegra_pen_lock) + mov32 r3, TEGRA_PMC_VIRT + cpu_id r0 + add r1, r3, #PMC_SCRATCH37 + cmp r0, #0 + addeq r2, r3, #PMC_SCRATCH38 + addeq r3, r3, #PMC_SCRATCH39 + addne r2, r3, #PMC_SCRATCH39 + addne r3, r3, #PMC_SCRATCH38 + + mov r12, #1 + str r12, [r2] @ flag[cpu] = 1 + dsb + str r12, [r1] @ !turn = cpu +1: dsb + ldr r12, [r3] + cmp r12, #1 @ flag[!cpu] == 1? + ldreq r12, [r1] + cmpeq r12, r0 @ !turn == cpu? + beq 1b @ while !turn == cpu && flag[!cpu] == 1 + + mov pc, lr @ locked +ENDPROC(tegra_pen_lock) + +ENTRY(tegra_pen_unlock) + dsb + mov32 r3, TEGRA_PMC_VIRT + cpu_id r0 + cmp r0, #0 + addeq r2, r3, #PMC_SCRATCH38 + addne r2, r3, #PMC_SCRATCH39 + mov r12, #0 + str r12, [r2] + mov pc, lr +ENDPROC(tegra_pen_unlock) + +/* + * tegra20_cpu_clear_resettable(void) + * + * Called to clear the "resettable soon" flag in PMC_SCRATCH41 when + * it is expected that the secondary CPU will be idle soon. + */ +ENTRY(tegra20_cpu_clear_resettable) + mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41 + mov r12, #CPU_NOT_RESETTABLE + str r12, [r1] + mov pc, lr +ENDPROC(tegra20_cpu_clear_resettable) + +/* + * tegra20_cpu_set_resettable_soon(void) + * + * Called to set the "resettable soon" flag in PMC_SCRATCH41 when + * it is expected that the secondary CPU will be idle soon. + */ +ENTRY(tegra20_cpu_set_resettable_soon) + mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41 + mov r12, #CPU_RESETTABLE_SOON + str r12, [r1] + mov pc, lr +ENDPROC(tegra20_cpu_set_resettable_soon) + +/* + * tegra20_cpu_is_resettable_soon(void) + * + * Returns true if the "resettable soon" flag in PMC_SCRATCH41 has been + * set because it is expected that the secondary CPU will be idle soon. + */ +ENTRY(tegra20_cpu_is_resettable_soon) + mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41 + ldr r12, [r1] + cmp r12, #CPU_RESETTABLE_SOON + moveq r0, #1 + movne r0, #0 + mov pc, lr +ENDPROC(tegra20_cpu_is_resettable_soon) + +/* + * tegra20_sleep_cpu_secondary_finish(unsigned long v2p) + * + * Enters WFI on secondary CPU by exiting coherency. + */ +ENTRY(tegra20_sleep_cpu_secondary_finish) + stmfd sp!, {r4-r11, lr} + + mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency + + /* Flush and disable the L1 data cache */ + bl tegra_disable_clean_inv_dcache + + mov32 r0, TEGRA_PMC_VIRT + PMC_SCRATCH41 + mov r3, #CPU_RESETTABLE + str r3, [r0] + + bl cpu_do_idle + + /* + * cpu may be reset while in wfi, which will return through + * tegra_resume to cpu_resume + * or interrupt may wake wfi, which will return here + * cpu state is unchanged - MMU is on, cache is on, coherency + * is off, and the data cache is off + * + * r11 contains the original actlr + */ + + bl tegra_pen_lock + + mov32 r3, TEGRA_PMC_VIRT + add r0, r3, #PMC_SCRATCH41 + mov r3, #CPU_NOT_RESETTABLE + str r3, [r0] + + bl tegra_pen_unlock + + /* Re-enable the data cache */ + mrc p15, 0, r10, c1, c0, 0 + orr r10, r10, #CR_C + mcr p15, 0, r10, c1, c0, 0 + isb + + mcr p15, 0, r11, c1, c0, 1 @ reenable coherency + + /* Invalidate the TLBs & BTAC */ + mov r1, #0 + mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs + mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC + dsb + isb + + /* the cpu was running with coherency disabled, + * caches may be out of date */ + bl v7_flush_kern_cache_louis + + ldmfd sp!, {r4 - r11, pc} +ENDPROC(tegra20_sleep_cpu_secondary_finish) + +/* + * tegra20_tear_down_cpu + * + * Switches the CPU cluster to PLL-P and enters sleep. + */ +ENTRY(tegra20_tear_down_cpu) + bl tegra_switch_cpu_to_pllp + b tegra20_enter_sleep +ENDPROC(tegra20_tear_down_cpu) + +/* + * tegra20_enter_sleep + * + * uses flow controller to enter sleep state + * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1 + * executes from SDRAM with target state is LP2 + */ +tegra20_enter_sleep: + mov32 r6, TEGRA_FLOW_CTRL_BASE + + mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT + orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ + cpu_id r1 + cpu_to_halt_reg r1, r1 + str r0, [r6, r1] + dsb + ldr r0, [r6, r1] /* memory barrier */ + +halted: + dsb + wfe /* CPU should be power gated here */ + isb + b halted + +#endif diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 562a8e7..63a15bd 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -32,9 +32,6 @@ * Should never return. */ ENTRY(tegra30_hotplug_shutdown) - /* Turn off SMP coherency */ - exit_smp r4, r5 - /* Powergate this CPU */ mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN bl tegra30_cpu_shutdown diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 26afa7c..364d845 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -34,7 +34,10 @@ #include "flowctrl.h" #include "sleep.h" -#ifdef CONFIG_PM_SLEEP +#define CLK_RESET_CCLK_BURST 0x20 +#define CLK_RESET_CCLK_DIVIDER 0x24 + +#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) /* * tegra_disable_clean_inv_dcache * @@ -60,7 +63,9 @@ ENTRY(tegra_disable_clean_inv_dcache) ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc} ENDPROC(tegra_disable_clean_inv_dcache) +#endif +#ifdef CONFIG_PM_SLEEP /* * tegra_sleep_cpu_finish(unsigned long v2p) * @@ -108,4 +113,20 @@ ENTRY(tegra_shut_off_mmu) mov pc, r0 ENDPROC(tegra_shut_off_mmu) .popsection + +/* + * tegra_switch_cpu_to_pllp + * + * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp + */ +ENTRY(tegra_switch_cpu_to_pllp) + /* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */ + mov32 r5, TEGRA_CLK_RESET_BASE + mov r0, #(2 << 28) @ burst policy = run mode + orr r0, r0, #(4 << 4) @ use PLLP in run mode burst + str r0, [r5, #CLK_RESET_CCLK_BURST] + mov r0, #0 + str r0, [r5, #CLK_RESET_CCLK_DIVIDER] + mov pc, lr +ENDPROC(tegra_switch_cpu_to_pllp) #endif diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 9821ee7..4ffae54 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -25,6 +25,19 @@ + IO_PPSB_VIRT) #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \ + IO_PPSB_VIRT) +#define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT) + +/* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */ +#define PMC_SCRATCH37 0x130 +#define PMC_SCRATCH38 0x134 +#define PMC_SCRATCH39 0x138 +#define PMC_SCRATCH41 0x140 + +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +#define CPU_RESETTABLE 2 +#define CPU_RESETTABLE_SOON 1 +#define CPU_NOT_RESETTABLE 0 +#endif #ifdef __ASSEMBLY__ /* returns the offset of the flow controller halt register for a cpu */ @@ -104,8 +117,11 @@ exit_l2_resume: .endm #endif /* CONFIG_CACHE_L2X0 */ #else +void tegra_pen_lock(void); +void tegra_pen_unlock(void); void tegra_resume(void); int tegra_sleep_cpu_finish(unsigned long); +void tegra_disable_clean_inv_dcache(void); #ifdef CONFIG_HOTPLUG_CPU void tegra20_hotplug_init(void); @@ -115,6 +131,17 @@ static inline void tegra20_hotplug_init(void) {} static inline void tegra30_hotplug_init(void) {} #endif +void tegra20_cpu_shutdown(int cpu); +int tegra20_cpu_is_resettable_soon(void); +void tegra20_cpu_clear_resettable(void); +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +void tegra20_cpu_set_resettable_soon(void); +#else +static inline void tegra20_cpu_set_resettable_soon(void) {} +#endif + +int tegra20_sleep_cpu_secondary_finish(unsigned long); +void tegra20_tear_down_cpu(void); int tegra30_sleep_cpu_secondary_finish(unsigned long); void tegra30_tear_down_cpu(void); diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c deleted file mode 100644 index 4eb6bc8..0000000 --- a/arch/arm/mach-tegra/tegra20_clocks.c +++ /dev/null @@ -1,1623 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra20_clocks.c - * - * Copyright (C) 2010 Google, Inc. - * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/list.h> -#include <linux/spinlock.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/clkdev.h> -#include <linux/clk.h> - -#include "clock.h" -#include "fuse.h" -#include "iomap.h" -#include "tegra2_emc.h" -#include "tegra_cpu_car.h" - -#define RST_DEVICES 0x004 -#define RST_DEVICES_SET 0x300 -#define RST_DEVICES_CLR 0x304 -#define RST_DEVICES_NUM 3 - -#define CLK_OUT_ENB 0x010 -#define CLK_OUT_ENB_SET 0x320 -#define CLK_OUT_ENB_CLR 0x324 -#define CLK_OUT_ENB_NUM 3 - -#define CLK_MASK_ARM 0x44 -#define MISC_CLK_ENB 0x48 - -#define OSC_CTRL 0x50 -#define OSC_CTRL_OSC_FREQ_MASK (3<<30) -#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) -#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) -#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) -#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) -#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) - -#define OSC_FREQ_DET 0x58 -#define OSC_FREQ_DET_TRIG (1<<31) - -#define OSC_FREQ_DET_STATUS 0x5C -#define OSC_FREQ_DET_BUSY (1<<31) -#define OSC_FREQ_DET_CNT_MASK 0xFFFF - -#define PERIPH_CLK_SOURCE_I2S1 0x100 -#define PERIPH_CLK_SOURCE_EMC 0x19c -#define PERIPH_CLK_SOURCE_OSC 0x1fc -#define PERIPH_CLK_SOURCE_NUM \ - ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4) - -#define PERIPH_CLK_SOURCE_MASK (3<<30) -#define PERIPH_CLK_SOURCE_SHIFT 30 -#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28) -#define PERIPH_CLK_SOURCE_PWM_SHIFT 28 -#define PERIPH_CLK_SOURCE_ENABLE (1<<28) -#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF -#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF -#define PERIPH_CLK_SOURCE_DIV_SHIFT 0 - -#define SDMMC_CLK_INT_FB_SEL (1 << 23) -#define SDMMC_CLK_INT_FB_DLY_SHIFT 16 -#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT) - -#define PLL_BASE 0x0 -#define PLL_BASE_BYPASS (1<<31) -#define PLL_BASE_ENABLE (1<<30) -#define PLL_BASE_REF_ENABLE (1<<29) -#define PLL_BASE_OVERRIDE (1<<28) -#define PLL_BASE_DIVP_MASK (0x7<<20) -#define PLL_BASE_DIVP_SHIFT 20 -#define PLL_BASE_DIVN_MASK (0x3FF<<8) -#define PLL_BASE_DIVN_SHIFT 8 -#define PLL_BASE_DIVM_MASK (0x1F) -#define PLL_BASE_DIVM_SHIFT 0 - -#define PLL_OUT_RATIO_MASK (0xFF<<8) -#define PLL_OUT_RATIO_SHIFT 8 -#define PLL_OUT_OVERRIDE (1<<2) -#define PLL_OUT_CLKEN (1<<1) -#define PLL_OUT_RESET_DISABLE (1<<0) - -#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) - -#define PLL_MISC_DCCON_SHIFT 20 -#define PLL_MISC_CPCON_SHIFT 8 -#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT) -#define PLL_MISC_LFCON_SHIFT 4 -#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT) -#define PLL_MISC_VCOCON_SHIFT 0 -#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT) - -#define PLLU_BASE_POST_DIV (1<<20) - -#define PLLD_MISC_CLKENABLE (1<<30) -#define PLLD_MISC_DIV_RST (1<<23) -#define PLLD_MISC_DCCON_SHIFT 12 - -#define PLLE_MISC_READY (1 << 15) - -#define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4) -#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8) -#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32)) - -#define SUPER_CLK_MUX 0x00 -#define SUPER_STATE_SHIFT 28 -#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT) -#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT) -#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT) -#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT) -#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT) -#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT) -#define SUPER_SOURCE_MASK 0xF -#define SUPER_FIQ_SOURCE_SHIFT 12 -#define SUPER_IRQ_SOURCE_SHIFT 8 -#define SUPER_RUN_SOURCE_SHIFT 4 -#define SUPER_IDLE_SOURCE_SHIFT 0 - -#define SUPER_CLK_DIVIDER 0x04 - -#define BUS_CLK_DISABLE (1<<3) -#define BUS_CLK_DIV_MASK 0x3 - -#define PMC_CTRL 0x0 - #define PMC_CTRL_BLINK_ENB (1 << 7) - -#define PMC_DPD_PADS_ORIDE 0x1c - #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20) - -#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0 -#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff -#define PMC_BLINK_TIMER_ENB (1 << 15) -#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16 -#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff - -/* Tegra CPU clock and reset control regs */ -#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c -#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 -#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 - -#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) -#define CPU_RESET(cpu) (0x1111ul << (cpu)) - -static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); -static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); - -/* - * Some clocks share a register with other clocks. Any clock op that - * non-atomically modifies a register used by another clock must lock - * clock_register_lock first. - */ -static DEFINE_SPINLOCK(clock_register_lock); - -/* - * Some peripheral clocks share an enable bit, so refcount the enable bits - * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U - */ -static int tegra_periph_clk_enable_refcount[3 * 32]; - -#define clk_writel(value, reg) \ - __raw_writel(value, reg_clk_base + (reg)) -#define clk_readl(reg) \ - __raw_readl(reg_clk_base + (reg)) -#define pmc_writel(value, reg) \ - __raw_writel(value, reg_pmc_base + (reg)) -#define pmc_readl(reg) \ - __raw_readl(reg_pmc_base + (reg)) - -static unsigned long clk_measure_input_freq(void) -{ - u32 clock_autodetect; - clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); - do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY); - clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS); - if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) { - return 12000000; - } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) { - return 13000000; - } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) { - return 19200000; - } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) { - return 26000000; - } else { - pr_err("%s: Unexpected clock autodetect value %d", - __func__, clock_autodetect); - BUG(); - return 0; - } -} - -static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate) -{ - s64 divider_u71 = parent_rate * 2; - divider_u71 += rate - 1; - do_div(divider_u71, rate); - - if (divider_u71 - 2 < 0) - return 0; - - if (divider_u71 - 2 > 255) - return -EINVAL; - - return divider_u71 - 2; -} - -static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate) -{ - s64 divider_u16; - - divider_u16 = parent_rate; - divider_u16 += rate - 1; - do_div(divider_u16, rate); - - if (divider_u16 - 1 < 0) - return 0; - - if (divider_u16 - 1 > 0xFFFF) - return -EINVAL; - - return divider_u16 - 1; -} - -static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - return to_clk_tegra(hw)->fixed_rate; -} - -struct clk_ops tegra_clk_32k_ops = { - .recalc_rate = tegra_clk_fixed_recalc_rate, -}; - -/* clk_m functions */ -static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw, - unsigned long prate) -{ - if (!to_clk_tegra(hw)->fixed_rate) - to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq(); - return to_clk_tegra(hw)->fixed_rate; -} - -static void tegra20_clk_m_init(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 osc_ctrl = clk_readl(OSC_CTRL); - u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK; - - switch (c->fixed_rate) { - case 12000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; - break; - case 13000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; - break; - case 19200000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ; - break; - case 26000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; - break; - default: - BUG(); - } - clk_writel(auto_clock_control, OSC_CTRL); -} - -struct clk_ops tegra_clk_m_ops = { - .init = tegra20_clk_m_init, - .recalc_rate = tegra20_clk_m_recalc_rate, -}; - -/* super clock functions */ -/* "super clocks" on tegra have two-stage muxes and a clock skipping - * super divider. We will ignore the clock skipping divider, since we - * can't lower the voltage when using the clock skip, but we can if we - * lower the PLL frequency. - */ -static int tegra20_super_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - val = clk_readl(c->reg + SUPER_CLK_MUX); - BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && - ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); - c->state = ON; - return c->state; -} - -static int tegra20_super_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - clk_writel(0, c->reg + SUPER_CLK_DIVIDER); - return 0; -} - -static void tegra20_super_clk_disable(struct clk_hw *hw) -{ - pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); - - /* oops - don't disable the CPU clock! */ - BUG(); -} - -static u8 tegra20_super_clk_get_parent(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - int val = clk_readl(c->reg + SUPER_CLK_MUX); - int source; - int shift; - - BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && - ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); - shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? - SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; - source = (val >> shift) & SUPER_SOURCE_MASK; - return source; -} - -static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg + SUPER_CLK_MUX); - int shift; - - BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && - ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); - shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? - SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; - val &= ~(SUPER_SOURCE_MASK << shift); - val |= index << shift; - - clk_writel(val, c->reg); - - return 0; -} - -/* FIX ME: Need to switch parents to change the source PLL rate */ -static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw, - unsigned long prate) -{ - return prate; -} - -static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - return *prate; -} - -static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - return 0; -} - -struct clk_ops tegra_super_ops = { - .is_enabled = tegra20_super_clk_is_enabled, - .enable = tegra20_super_clk_enable, - .disable = tegra20_super_clk_disable, - .set_parent = tegra20_super_clk_set_parent, - .get_parent = tegra20_super_clk_get_parent, - .set_rate = tegra20_super_clk_set_rate, - .round_rate = tegra20_super_clk_round_rate, - .recalc_rate = tegra20_super_clk_recalc_rate, -}; - -static unsigned long tegra20_twd_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u64 rate = parent_rate; - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - - return rate; -} - -struct clk_ops tegra_twd_ops = { - .recalc_rate = tegra20_twd_clk_recalc_rate, -}; - -static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw) -{ - return 0; -} - -struct clk_ops tegra_cop_ops = { - .get_parent = tegra20_cop_clk_get_parent, -}; - -/* virtual cop clock functions. Used to acquire the fake 'cop' clock to - * reset the COP block (i.e. AVP) */ -void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert) -{ - unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR; - - pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert"); - clk_writel(1 << 1, reg); -} - -/* bus clock functions */ -static int tegra20_bus_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - - c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; - return c->state; -} - -static int tegra20_bus_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long flags; - u32 val; - - spin_lock_irqsave(&clock_register_lock, flags); - - val = clk_readl(c->reg); - val &= ~(BUS_CLK_DISABLE << c->reg_shift); - clk_writel(val, c->reg); - - spin_unlock_irqrestore(&clock_register_lock, flags); - - return 0; -} - -static void tegra20_bus_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long flags; - u32 val; - - spin_lock_irqsave(&clock_register_lock, flags); - - val = clk_readl(c->reg); - val |= BUS_CLK_DISABLE << c->reg_shift; - clk_writel(val, c->reg); - - spin_unlock_irqrestore(&clock_register_lock, flags); -} - -static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw, - unsigned long prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - u64 rate = prate; - - c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; - c->mul = 1; - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - return rate; -} - -static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - int ret = -EINVAL; - unsigned long flags; - u32 val; - int i; - - spin_lock_irqsave(&clock_register_lock, flags); - - val = clk_readl(c->reg); - for (i = 1; i <= 4; i++) { - if (rate == parent_rate / i) { - val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); - val |= (i - 1) << c->reg_shift; - clk_writel(val, c->reg); - c->div = i; - c->mul = 1; - ret = 0; - break; - } - } - - spin_unlock_irqrestore(&clock_register_lock, flags); - - return ret; -} - -static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - unsigned long parent_rate = *prate; - s64 divider; - - if (rate >= parent_rate) - return rate; - - divider = parent_rate; - divider += rate - 1; - do_div(divider, rate); - - if (divider < 0) - return divider; - - if (divider > 4) - divider = 4; - do_div(parent_rate, divider); - - return parent_rate; -} - -struct clk_ops tegra_bus_ops = { - .is_enabled = tegra20_bus_clk_is_enabled, - .enable = tegra20_bus_clk_enable, - .disable = tegra20_bus_clk_disable, - .set_rate = tegra20_bus_clk_set_rate, - .round_rate = tegra20_bus_clk_round_rate, - .recalc_rate = tegra20_bus_clk_recalc_rate, -}; - -/* Blink output functions */ -static int tegra20_blink_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - val = pmc_readl(PMC_CTRL); - c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; - return c->state; -} - -static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw, - unsigned long prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u64 rate = prate; - u32 val; - - c->mul = 1; - val = pmc_readl(c->reg); - - if (val & PMC_BLINK_TIMER_ENB) { - unsigned int on_off; - - on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) & - PMC_BLINK_TIMER_DATA_ON_MASK; - val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT; - val &= PMC_BLINK_TIMER_DATA_OFF_MASK; - on_off += val; - /* each tick in the blink timer is 4 32KHz clocks */ - c->div = on_off * 4; - } else { - c->div = 1; - } - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - return rate; -} - -static int tegra20_blink_clk_enable(struct clk_hw *hw) -{ - u32 val; - - val = pmc_readl(PMC_DPD_PADS_ORIDE); - pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); - - val = pmc_readl(PMC_CTRL); - pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL); - - return 0; -} - -static void tegra20_blink_clk_disable(struct clk_hw *hw) -{ - u32 val; - - val = pmc_readl(PMC_CTRL); - pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL); - - val = pmc_readl(PMC_DPD_PADS_ORIDE); - pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); -} - -static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - if (rate >= parent_rate) { - c->div = 1; - pmc_writel(0, c->reg); - } else { - unsigned int on_off; - u32 val; - - on_off = DIV_ROUND_UP(parent_rate / 8, rate); - c->div = on_off * 8; - - val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) << - PMC_BLINK_TIMER_DATA_ON_SHIFT; - on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK; - on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT; - val |= on_off; - val |= PMC_BLINK_TIMER_ENB; - pmc_writel(val, c->reg); - } - - return 0; -} - -static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - int div; - int mul; - long round_rate = *prate; - - mul = 1; - - if (rate >= *prate) { - div = 1; - } else { - div = DIV_ROUND_UP(*prate / 8, rate); - div *= 8; - } - - round_rate *= mul; - round_rate += div - 1; - do_div(round_rate, div); - - return round_rate; -} - -struct clk_ops tegra_blink_clk_ops = { - .is_enabled = tegra20_blink_clk_is_enabled, - .enable = tegra20_blink_clk_enable, - .disable = tegra20_blink_clk_disable, - .set_rate = tegra20_blink_clk_set_rate, - .round_rate = tegra20_blink_clk_round_rate, - .recalc_rate = tegra20_blink_clk_recalc_rate, -}; - -/* PLL Functions */ -static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c) -{ - udelay(c->u.pll.lock_delay); - return 0; -} - -static int tegra20_pll_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg + PLL_BASE); - - c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; - return c->state; -} - -static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw, - unsigned long prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg + PLL_BASE); - u64 rate = prate; - - if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { - const struct clk_pll_freq_table *sel; - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { - if (sel->input_rate == prate && - sel->output_rate == c->u.pll.fixed_rate) { - c->mul = sel->n; - c->div = sel->m * sel->p; - break; - } - } - pr_err("Clock %s has unknown fixed frequency\n", - __clk_get_name(hw->clk)); - BUG(); - } else if (val & PLL_BASE_BYPASS) { - c->mul = 1; - c->div = 1; - } else { - c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; - c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; - if (c->flags & PLLU) - c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2; - else - c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1; - } - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - return rate; -} - -static int tegra20_pll_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); - - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLL_BASE_BYPASS; - val |= PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - tegra20_pll_clk_wait_for_lock(c); - - return 0; -} - -static void tegra20_pll_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); - - val = clk_readl(c->reg); - val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); - clk_writel(val, c->reg); -} - -static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long input_rate = parent_rate; - const struct clk_pll_freq_table *sel; - u32 val; - - pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate); - - if (c->flags & PLL_FIXED) { - int ret = 0; - if (rate != c->u.pll.fixed_rate) { - pr_err("%s: Can not change %s fixed rate %lu to %lu\n", - __func__, __clk_get_name(hw->clk), - c->u.pll.fixed_rate, rate); - ret = -EINVAL; - } - return ret; - } - - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { - if (sel->input_rate == input_rate && sel->output_rate == rate) { - c->mul = sel->n; - c->div = sel->m * sel->p; - - val = clk_readl(c->reg + PLL_BASE); - if (c->flags & PLL_FIXED) - val |= PLL_BASE_OVERRIDE; - val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK | - PLL_BASE_DIVM_MASK); - val |= (sel->m << PLL_BASE_DIVM_SHIFT) | - (sel->n << PLL_BASE_DIVN_SHIFT); - BUG_ON(sel->p < 1 || sel->p > 2); - if (c->flags & PLLU) { - if (sel->p == 1) - val |= PLLU_BASE_POST_DIV; - } else { - if (sel->p == 2) - val |= 1 << PLL_BASE_DIVP_SHIFT; - } - clk_writel(val, c->reg + PLL_BASE); - - if (c->flags & PLL_HAS_CPCON) { - val = clk_readl(c->reg + PLL_MISC(c)); - val &= ~PLL_MISC_CPCON_MASK; - val |= sel->cpcon << PLL_MISC_CPCON_SHIFT; - clk_writel(val, c->reg + PLL_MISC(c)); - } - - if (c->state == ON) - tegra20_pll_clk_enable(hw); - return 0; - } - } - return -EINVAL; -} - -static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - const struct clk_pll_freq_table *sel; - unsigned long input_rate = *prate; - u64 output_rate = *prate; - int mul; - int div; - - if (c->flags & PLL_FIXED) - return c->u.pll.fixed_rate; - - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) - if (sel->input_rate == input_rate && sel->output_rate == rate) { - mul = sel->n; - div = sel->m * sel->p; - break; - } - - if (sel->input_rate == 0) - return -EINVAL; - - output_rate *= mul; - output_rate += div - 1; /* round up */ - do_div(output_rate, div); - - return output_rate; -} - -struct clk_ops tegra_pll_ops = { - .is_enabled = tegra20_pll_clk_is_enabled, - .enable = tegra20_pll_clk_enable, - .disable = tegra20_pll_clk_disable, - .set_rate = tegra20_pll_clk_set_rate, - .recalc_rate = tegra20_pll_clk_recalc_rate, - .round_rate = tegra20_pll_clk_round_rate, -}; - -static void tegra20_pllx_clk_init(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - if (tegra_sku_id == 7) - c->max_rate = 750000000; -} - -struct clk_ops tegra_pllx_ops = { - .init = tegra20_pllx_clk_init, - .is_enabled = tegra20_pll_clk_is_enabled, - .enable = tegra20_pll_clk_enable, - .disable = tegra20_pll_clk_disable, - .set_rate = tegra20_pll_clk_set_rate, - .recalc_rate = tegra20_pll_clk_recalc_rate, - .round_rate = tegra20_pll_clk_round_rate, -}; - -static int tegra20_plle_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); - - mdelay(1); - - val = clk_readl(c->reg + PLL_BASE); - if (!(val & PLLE_MISC_READY)) - return -EBUSY; - - val = clk_readl(c->reg + PLL_BASE); - val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS; - clk_writel(val, c->reg + PLL_BASE); - - return 0; -} - -struct clk_ops tegra_plle_ops = { - .is_enabled = tegra20_pll_clk_is_enabled, - .enable = tegra20_plle_clk_enable, - .set_rate = tegra20_pll_clk_set_rate, - .recalc_rate = tegra20_pll_clk_recalc_rate, - .round_rate = tegra20_pll_clk_round_rate, -}; - -/* Clock divider ops */ -static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - - val >>= c->reg_shift; - c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; - if (!(val & PLL_OUT_RESET_DISABLE)) - c->state = OFF; - return c->state; -} - -static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw, - unsigned long prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u64 rate = prate; - u32 val = clk_readl(c->reg); - u32 divu71; - - val >>= c->reg_shift; - - if (c->flags & DIV_U71) { - divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; - c->div = (divu71 + 2); - c->mul = 2; - } else if (c->flags & DIV_2) { - c->div = 2; - c->mul = 1; - } else { - c->div = 1; - c->mul = 1; - } - - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - - return rate; -} - -static int tegra20_pll_div_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long flags; - u32 new_val; - u32 val; - - pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk)); - - if (c->flags & DIV_U71) { - spin_lock_irqsave(&clock_register_lock, flags); - val = clk_readl(c->reg); - new_val = val >> c->reg_shift; - new_val &= 0xFFFF; - - new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; - - val &= ~(0xFFFF << c->reg_shift); - val |= new_val << c->reg_shift; - clk_writel(val, c->reg); - spin_unlock_irqrestore(&clock_register_lock, flags); - return 0; - } else if (c->flags & DIV_2) { - BUG_ON(!(c->flags & PLLD)); - spin_lock_irqsave(&clock_register_lock, flags); - val = clk_readl(c->reg); - val &= ~PLLD_MISC_DIV_RST; - clk_writel(val, c->reg); - spin_unlock_irqrestore(&clock_register_lock, flags); - return 0; - } - return -EINVAL; -} - -static void tegra20_pll_div_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long flags; - u32 new_val; - u32 val; - - pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk)); - - if (c->flags & DIV_U71) { - spin_lock_irqsave(&clock_register_lock, flags); - val = clk_readl(c->reg); - new_val = val >> c->reg_shift; - new_val &= 0xFFFF; - - new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE); - - val &= ~(0xFFFF << c->reg_shift); - val |= new_val << c->reg_shift; - clk_writel(val, c->reg); - spin_unlock_irqrestore(&clock_register_lock, flags); - } else if (c->flags & DIV_2) { - BUG_ON(!(c->flags & PLLD)); - spin_lock_irqsave(&clock_register_lock, flags); - val = clk_readl(c->reg); - val |= PLLD_MISC_DIV_RST; - clk_writel(val, c->reg); - spin_unlock_irqrestore(&clock_register_lock, flags); - } -} - -static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long flags; - int divider_u71; - u32 new_val; - u32 val; - - pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate); - - if (c->flags & DIV_U71) { - divider_u71 = clk_div71_get_divider(parent_rate, rate); - if (divider_u71 >= 0) { - spin_lock_irqsave(&clock_register_lock, flags); - val = clk_readl(c->reg); - new_val = val >> c->reg_shift; - new_val &= 0xFFFF; - if (c->flags & DIV_U71_FIXED) - new_val |= PLL_OUT_OVERRIDE; - new_val &= ~PLL_OUT_RATIO_MASK; - new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT; - - val &= ~(0xFFFF << c->reg_shift); - val |= new_val << c->reg_shift; - clk_writel(val, c->reg); - c->div = divider_u71 + 2; - c->mul = 2; - spin_unlock_irqrestore(&clock_register_lock, flags); - return 0; - } - } else if (c->flags & DIV_2) { - if (parent_rate == rate * 2) - return 0; - } - return -EINVAL; -} - -static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long parent_rate = *prate; - int divider; - - pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate); - - if (c->flags & DIV_U71) { - divider = clk_div71_get_divider(parent_rate, rate); - if (divider < 0) - return divider; - return DIV_ROUND_UP(parent_rate * 2, divider + 2); - } else if (c->flags & DIV_2) { - return DIV_ROUND_UP(parent_rate, 2); - } - return -EINVAL; -} - -struct clk_ops tegra_pll_div_ops = { - .is_enabled = tegra20_pll_div_clk_is_enabled, - .enable = tegra20_pll_div_clk_enable, - .disable = tegra20_pll_div_clk_disable, - .set_rate = tegra20_pll_div_clk_set_rate, - .round_rate = tegra20_pll_div_clk_round_rate, - .recalc_rate = tegra20_pll_div_clk_recalc_rate, -}; - -/* Periph clk ops */ - -static int tegra20_periph_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - c->state = ON; - - if (!c->u.periph.clk_num) - goto out; - - if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & - PERIPH_CLK_TO_ENB_BIT(c))) - c->state = OFF; - - if (!(c->flags & PERIPH_NO_RESET)) - if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) & - PERIPH_CLK_TO_ENB_BIT(c)) - c->state = OFF; - -out: - return c->state; -} - -static int tegra20_periph_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long flags; - u32 val; - - pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); - - if (!c->u.periph.clk_num) - return 0; - - tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; - if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) - return 0; - - spin_lock_irqsave(&clock_register_lock, flags); - - clk_writel(PERIPH_CLK_TO_ENB_BIT(c), - CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); - if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) - clk_writel(PERIPH_CLK_TO_ENB_BIT(c), - RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); - if (c->flags & PERIPH_EMC_ENB) { - /* The EMC peripheral clock has 2 extra enable bits */ - /* FIXME: Do they need to be disabled? */ - val = clk_readl(c->reg); - val |= 0x3 << 24; - clk_writel(val, c->reg); - } - - spin_unlock_irqrestore(&clock_register_lock, flags); - - return 0; -} - -static void tegra20_periph_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long flags; - - pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); - - if (!c->u.periph.clk_num) - return; - - tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; - - if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0) - return; - - spin_lock_irqsave(&clock_register_lock, flags); - - clk_writel(PERIPH_CLK_TO_ENB_BIT(c), - CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); - - spin_unlock_irqrestore(&clock_register_lock, flags); -} - -void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR; - - pr_debug("%s %s on clock %s\n", __func__, - assert ? "assert" : "deassert", __clk_get_name(hw->clk)); - - BUG_ON(!c->u.periph.clk_num); - - if (!(c->flags & PERIPH_NO_RESET)) - clk_writel(PERIPH_CLK_TO_ENB_BIT(c), - base + PERIPH_CLK_TO_ENB_SET_REG(c)); -} - -static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - u32 mask; - u32 shift; - - pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index); - - if (c->flags & MUX_PWM) { - shift = PERIPH_CLK_SOURCE_PWM_SHIFT; - mask = PERIPH_CLK_SOURCE_PWM_MASK; - } else { - shift = PERIPH_CLK_SOURCE_SHIFT; - mask = PERIPH_CLK_SOURCE_MASK; - } - - val = clk_readl(c->reg); - val &= ~mask; - val |= (index) << shift; - - clk_writel(val, c->reg); - - return 0; -} - -static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - u32 mask; - u32 shift; - - if (c->flags & MUX_PWM) { - shift = PERIPH_CLK_SOURCE_PWM_SHIFT; - mask = PERIPH_CLK_SOURCE_PWM_MASK; - } else { - shift = PERIPH_CLK_SOURCE_SHIFT; - mask = PERIPH_CLK_SOURCE_MASK; - } - - if (c->flags & MUX) - return (val & mask) >> shift; - else - return 0; -} - -static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw, - unsigned long prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long rate = prate; - u32 val = clk_readl(c->reg); - - if (c->flags & DIV_U71) { - u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; - c->div = divu71 + 2; - c->mul = 2; - } else if (c->flags & DIV_U16) { - u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; - c->div = divu16 + 1; - c->mul = 1; - } else { - c->div = 1; - c->mul = 1; - return rate; - } - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - - return rate; -} - -static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - int divider; - - val = clk_readl(c->reg); - - if (c->flags & DIV_U71) { - divider = clk_div71_get_divider(parent_rate, rate); - - if (divider >= 0) { - val = clk_readl(c->reg); - val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK; - val |= divider; - clk_writel(val, c->reg); - c->div = divider + 2; - c->mul = 2; - return 0; - } - } else if (c->flags & DIV_U16) { - divider = clk_div16_get_divider(parent_rate, rate); - if (divider >= 0) { - val = clk_readl(c->reg); - val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; - val |= divider; - clk_writel(val, c->reg); - c->div = divider + 1; - c->mul = 1; - return 0; - } - } else if (parent_rate <= rate) { - c->div = 1; - c->mul = 1; - return 0; - } - - return -EINVAL; -} - -static long tegra20_periph_clk_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk)); - int divider; - - pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate); - - if (prate) - parent_rate = *prate; - - if (c->flags & DIV_U71) { - divider = clk_div71_get_divider(parent_rate, rate); - if (divider < 0) - return divider; - - return DIV_ROUND_UP(parent_rate * 2, divider + 2); - } else if (c->flags & DIV_U16) { - divider = clk_div16_get_divider(parent_rate, rate); - if (divider < 0) - return divider; - return DIV_ROUND_UP(parent_rate, divider + 1); - } - return -EINVAL; -} - -struct clk_ops tegra_periph_clk_ops = { - .is_enabled = tegra20_periph_clk_is_enabled, - .enable = tegra20_periph_clk_enable, - .disable = tegra20_periph_clk_disable, - .set_parent = tegra20_periph_clk_set_parent, - .get_parent = tegra20_periph_clk_get_parent, - .set_rate = tegra20_periph_clk_set_rate, - .round_rate = tegra20_periph_clk_round_rate, - .recalc_rate = tegra20_periph_clk_recalc_rate, -}; - -/* External memory controller clock ops */ -static void tegra20_emc_clk_init(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - c->max_rate = __clk_get_rate(hw->clk); -} - -static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - long emc_rate; - long clk_rate; - - /* - * The slowest entry in the EMC clock table that is at least as - * fast as rate. - */ - emc_rate = tegra_emc_round_rate(rate); - if (emc_rate < 0) - return c->max_rate; - - /* - * The fastest rate the PLL will generate that is at most the - * requested rate. - */ - clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL); - - /* - * If this fails, and emc_rate > clk_rate, it's because the maximum - * rate in the EMC tables is larger than the maximum rate of the EMC - * clock. The EMC clock's max rate is the rate it was running when the - * kernel booted. Such a mismatch is probably due to using the wrong - * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25. - */ - WARN_ONCE(emc_rate != clk_rate, - "emc_rate %ld != clk_rate %ld", - emc_rate, clk_rate); - - return emc_rate; -} - -static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - int ret; - - /* - * The Tegra2 memory controller has an interlock with the clock - * block that allows memory shadowed registers to be updated, - * and then transfer them to the main registers at the same - * time as the clock update without glitches. - */ - ret = tegra_emc_set_rate(rate); - if (ret < 0) - return ret; - - ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate); - udelay(1); - - return ret; -} - -struct clk_ops tegra_emc_clk_ops = { - .init = tegra20_emc_clk_init, - .is_enabled = tegra20_periph_clk_is_enabled, - .enable = tegra20_periph_clk_enable, - .disable = tegra20_periph_clk_disable, - .set_parent = tegra20_periph_clk_set_parent, - .get_parent = tegra20_periph_clk_get_parent, - .set_rate = tegra20_emc_clk_set_rate, - .round_rate = tegra20_emc_clk_round_rate, - .recalc_rate = tegra20_periph_clk_recalc_rate, -}; - -/* Clock doubler ops */ -static int tegra20_clk_double_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - c->state = ON; - - if (!c->u.periph.clk_num) - goto out; - - if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & - PERIPH_CLK_TO_ENB_BIT(c))) - c->state = OFF; - -out: - return c->state; -}; - -static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw, - unsigned long prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u64 rate = prate; - - c->mul = 2; - c->div = 1; - - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - - return rate; -} - -static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - unsigned long output_rate = *prate; - - do_div(output_rate, 2); - return output_rate; -} - -static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - if (rate != 2 * parent_rate) - return -EINVAL; - return 0; -} - -struct clk_ops tegra_clk_double_ops = { - .is_enabled = tegra20_clk_double_is_enabled, - .enable = tegra20_periph_clk_enable, - .disable = tegra20_periph_clk_disable, - .set_rate = tegra20_clk_double_set_rate, - .recalc_rate = tegra20_clk_double_recalc_rate, - .round_rate = tegra20_clk_double_round_rate, -}; - -/* Audio sync clock ops */ -static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - - c->state = (val & (1<<4)) ? OFF : ON; - return c->state; -} - -static int tegra20_audio_sync_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - clk_writel(0, c->reg); - return 0; -} - -static void tegra20_audio_sync_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - clk_writel(1, c->reg); -} - -static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - int source; - - source = val & 0xf; - return source; -} - -static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - val = clk_readl(c->reg); - val &= ~0xf; - val |= index; - - clk_writel(val, c->reg); - - return 0; -} - -struct clk_ops tegra_audio_sync_clk_ops = { - .is_enabled = tegra20_audio_sync_clk_is_enabled, - .enable = tegra20_audio_sync_clk_enable, - .disable = tegra20_audio_sync_clk_disable, - .set_parent = tegra20_audio_sync_clk_set_parent, - .get_parent = tegra20_audio_sync_clk_get_parent, -}; - -/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */ - -static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - /* We could un-tristate the cdev1 or cdev2 pingroup here; this is - * currently done in the pinmux code. */ - c->state = ON; - - BUG_ON(!c->u.periph.clk_num); - - if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & - PERIPH_CLK_TO_ENB_BIT(c))) - c->state = OFF; - return c->state; -} - -static int tegra20_cdev_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - BUG_ON(!c->u.periph.clk_num); - - clk_writel(PERIPH_CLK_TO_ENB_BIT(c), - CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); - return 0; -} - -static void tegra20_cdev_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - BUG_ON(!c->u.periph.clk_num); - - clk_writel(PERIPH_CLK_TO_ENB_BIT(c), - CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); -} - -static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw, - unsigned long prate) -{ - return to_clk_tegra(hw)->fixed_rate; -} - -struct clk_ops tegra_cdev_clk_ops = { - .is_enabled = tegra20_cdev_clk_is_enabled, - .enable = tegra20_cdev_clk_enable, - .disable = tegra20_cdev_clk_disable, - .recalc_rate = tegra20_cdev_recalc_rate, -}; - -/* Tegra20 CPU clock and reset control functions */ -static void tegra20_wait_cpu_in_reset(u32 cpu) -{ - unsigned int reg; - - do { - reg = readl(reg_clk_base + - TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); - cpu_relax(); - } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ - - return; -} - -static void tegra20_put_cpu_in_reset(u32 cpu) -{ - writel(CPU_RESET(cpu), - reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); - dmb(); -} - -static void tegra20_cpu_out_of_reset(u32 cpu) -{ - writel(CPU_RESET(cpu), - reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); - wmb(); -} - -static void tegra20_enable_cpu_clock(u32 cpu) -{ - unsigned int reg; - - reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); - writel(reg & ~CPU_CLOCK(cpu), - reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); - barrier(); - reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); -} - -static void tegra20_disable_cpu_clock(u32 cpu) -{ - unsigned int reg; - - reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); - writel(reg | CPU_CLOCK(cpu), - reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); -} - -static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { - .wait_for_reset = tegra20_wait_cpu_in_reset, - .put_in_reset = tegra20_put_cpu_in_reset, - .out_of_reset = tegra20_cpu_out_of_reset, - .enable_clock = tegra20_enable_cpu_clock, - .disable_clock = tegra20_disable_cpu_clock, -}; - -void __init tegra20_cpu_car_ops_init(void) -{ - tegra_cpu_car_ops = &tegra20_cpu_car_ops; -} diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h deleted file mode 100644 index 8bfd31b..0000000 --- a/arch/arm/mach-tegra/tegra20_clocks.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __MACH_TEGRA20_CLOCK_H -#define __MACH_TEGRA20_CLOCK_H - -extern struct clk_ops tegra_clk_32k_ops; -extern struct clk_ops tegra_pll_ops; -extern struct clk_ops tegra_clk_m_ops; -extern struct clk_ops tegra_pll_div_ops; -extern struct clk_ops tegra_pllx_ops; -extern struct clk_ops tegra_plle_ops; -extern struct clk_ops tegra_clk_double_ops; -extern struct clk_ops tegra_cdev_clk_ops; -extern struct clk_ops tegra_audio_sync_clk_ops; -extern struct clk_ops tegra_super_ops; -extern struct clk_ops tegra_cpu_ops; -extern struct clk_ops tegra_twd_ops; -extern struct clk_ops tegra_cop_ops; -extern struct clk_ops tegra_bus_ops; -extern struct clk_ops tegra_blink_clk_ops; -extern struct clk_ops tegra_emc_clk_ops; -extern struct clk_ops tegra_periph_clk_ops; -extern struct clk_ops tegra_clk_shared_bus_ops; - -void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert); -void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert); - -#endif diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c deleted file mode 100644 index a23a073..0000000 --- a/arch/arm/mach-tegra/tegra20_clocks_data.c +++ /dev/null @@ -1,1143 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra2_clocks.c - * - * Copyright (C) 2010 Google, Inc. - * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved. - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/clk-private.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/list.h> -#include <linux/spinlock.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/clk.h> - -#include "clock.h" -#include "fuse.h" -#include "tegra2_emc.h" -#include "tegra20_clocks.h" -#include "tegra_cpu_car.h" - -/* Clock definitions */ - -#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \ - _parent_names, _parents, _parent) \ - static struct clk tegra_##_name = { \ - .hw = &tegra_##_name##_hw.hw, \ - .name = #_name, \ - .rate = _rate, \ - .ops = _ops, \ - .flags = _flags, \ - .parent_names = _parent_names, \ - .parents = _parents, \ - .num_parents = ARRAY_SIZE(_parent_names), \ - .parent = _parent, \ - }; - -static struct clk tegra_clk_32k; -static struct clk_tegra tegra_clk_32k_hw = { - .hw = { - .clk = &tegra_clk_32k, - }, - .fixed_rate = 32768, -}; - -static struct clk tegra_clk_32k = { - .name = "clk_32k", - .rate = 32768, - .ops = &tegra_clk_32k_ops, - .hw = &tegra_clk_32k_hw.hw, - .flags = CLK_IS_ROOT, -}; - -static struct clk tegra_clk_m; -static struct clk_tegra tegra_clk_m_hw = { - .hw = { - .clk = &tegra_clk_m, - }, - .flags = ENABLE_ON_INIT, - .reg = 0x1fc, - .reg_shift = 28, - .max_rate = 26000000, - .fixed_rate = 0, -}; - -static struct clk tegra_clk_m = { - .name = "clk_m", - .ops = &tegra_clk_m_ops, - .hw = &tegra_clk_m_hw.hw, - .flags = CLK_IS_ROOT, -}; - -#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \ - _input_max, _cf_min, _cf_max, _vco_min, \ - _vco_max, _freq_table, _lock_delay, _ops, \ - _fixed_rate, _parent) \ - static const char *tegra_##_name##_parent_names[] = { \ - #_parent, \ - }; \ - static struct clk *tegra_##_name##_parents[] = { \ - &tegra_##_parent, \ - }; \ - static struct clk tegra_##_name; \ - static struct clk_tegra tegra_##_name##_hw = { \ - .hw = { \ - .clk = &tegra_##_name, \ - }, \ - .flags = _flags, \ - .reg = _reg, \ - .max_rate = _max_rate, \ - .u.pll = { \ - .input_min = _input_min, \ - .input_max = _input_max, \ - .cf_min = _cf_min, \ - .cf_max = _cf_max, \ - .vco_min = _vco_min, \ - .vco_max = _vco_max, \ - .freq_table = _freq_table, \ - .lock_delay = _lock_delay, \ - .fixed_rate = _fixed_rate, \ - }, \ - }; \ - static struct clk tegra_##_name = { \ - .name = #_name, \ - .ops = &_ops, \ - .hw = &tegra_##_name##_hw.hw, \ - .parent = &tegra_##_parent, \ - .parent_names = tegra_##_name##_parent_names, \ - .parents = tegra_##_name##_parents, \ - .num_parents = 1, \ - }; - -#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \ - _max_rate, _ops, _parent, _clk_flags) \ - static const char *tegra_##_name##_parent_names[] = { \ - #_parent, \ - }; \ - static struct clk *tegra_##_name##_parents[] = { \ - &tegra_##_parent, \ - }; \ - static struct clk tegra_##_name; \ - static struct clk_tegra tegra_##_name##_hw = { \ - .hw = { \ - .clk = &tegra_##_name, \ - }, \ - .flags = _flags, \ - .reg = _reg, \ - .max_rate = _max_rate, \ - .reg_shift = _reg_shift, \ - }; \ - static struct clk tegra_##_name = { \ - .name = #_name, \ - .ops = &tegra_pll_div_ops, \ - .hw = &tegra_##_name##_hw.hw, \ - .parent = &tegra_##_parent, \ - .parent_names = tegra_##_name##_parent_names, \ - .parents = tegra_##_name##_parents, \ - .num_parents = 1, \ - .flags = _clk_flags, \ - }; - - -static struct clk_pll_freq_table tegra_pll_s_freq_table[] = { - {32768, 12000000, 366, 1, 1, 0}, - {32768, 13000000, 397, 1, 1, 0}, - {32768, 19200000, 586, 1, 1, 0}, - {32768, 26000000, 793, 1, 1, 0}, - {0, 0, 0, 0, 0, 0}, -}; - -DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0, - 0, 12000000, 26000000, tegra_pll_s_freq_table, 300, - tegra_pll_ops, 0, clk_32k); - -static struct clk_pll_freq_table tegra_pll_c_freq_table[] = { - { 12000000, 600000000, 600, 12, 1, 8 }, - { 13000000, 600000000, 600, 13, 1, 8 }, - { 19200000, 600000000, 500, 16, 1, 6 }, - { 26000000, 600000000, 600, 26, 1, 8 }, - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000, - 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300, - tegra_pll_ops, 0, clk_m); - -DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000, - tegra_pll_div_ops, pll_c, 0); - -static struct clk_pll_freq_table tegra_pll_m_freq_table[] = { - { 12000000, 666000000, 666, 12, 1, 8}, - { 13000000, 666000000, 666, 13, 1, 8}, - { 19200000, 666000000, 555, 16, 1, 8}, - { 26000000, 666000000, 666, 26, 1, 8}, - { 12000000, 600000000, 600, 12, 1, 8}, - { 13000000, 600000000, 600, 13, 1, 8}, - { 19200000, 600000000, 375, 12, 1, 6}, - { 26000000, 600000000, 600, 26, 1, 8}, - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000, - 6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300, - tegra_pll_ops, 0, clk_m); - -DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000, - tegra_pll_div_ops, pll_m, 0); - -static struct clk_pll_freq_table tegra_pll_p_freq_table[] = { - { 12000000, 216000000, 432, 12, 2, 8}, - { 13000000, 216000000, 432, 13, 2, 8}, - { 19200000, 216000000, 90, 4, 2, 1}, - { 26000000, 216000000, 432, 26, 2, 8}, - { 12000000, 432000000, 432, 12, 1, 8}, - { 13000000, 432000000, 432, 13, 1, 8}, - { 19200000, 432000000, 90, 4, 1, 1}, - { 26000000, 432000000, 432, 26, 1, 8}, - { 0, 0, 0, 0, 0, 0 }, -}; - - -DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000, - 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000, - tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m); - -DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0, - 432000000, tegra_pll_div_ops, pll_p, 0); -DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16, - 432000000, tegra_pll_div_ops, pll_p, 0); -DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0, - 432000000, tegra_pll_div_ops, pll_p, 0); -DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16, - 432000000, tegra_pll_div_ops, pll_p, 0); - -static struct clk_pll_freq_table tegra_pll_a_freq_table[] = { - { 28800000, 56448000, 49, 25, 1, 1}, - { 28800000, 73728000, 64, 25, 1, 1}, - { 28800000, 24000000, 5, 6, 1, 1}, - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000, - 6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300, - tegra_pll_ops, 0, pll_p_out1); - -DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000, - tegra_pll_div_ops, pll_a, 0); - -static struct clk_pll_freq_table tegra_pll_d_freq_table[] = { - { 12000000, 216000000, 216, 12, 1, 4}, - { 13000000, 216000000, 216, 13, 1, 4}, - { 19200000, 216000000, 135, 12, 1, 3}, - { 26000000, 216000000, 216, 26, 1, 4}, - - { 12000000, 297000000, 99, 4, 1, 4 }, - { 12000000, 339000000, 113, 4, 1, 4 }, - - { 12000000, 594000000, 594, 12, 1, 8}, - { 13000000, 594000000, 594, 13, 1, 8}, - { 19200000, 594000000, 495, 16, 1, 8}, - { 26000000, 594000000, 594, 26, 1, 8}, - - { 12000000, 616000000, 616, 12, 1, 8}, - - { 12000000, 1000000000, 1000, 12, 1, 12}, - { 13000000, 1000000000, 1000, 13, 1, 12}, - { 19200000, 1000000000, 625, 12, 1, 8}, - { 26000000, 1000000000, 1000, 26, 1, 12}, - - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000, - 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table, - 1000, tegra_pll_ops, 0, clk_m); - -DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, - tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT); - -static struct clk_pll_freq_table tegra_pll_u_freq_table[] = { - { 12000000, 480000000, 960, 12, 2, 0}, - { 13000000, 480000000, 960, 13, 2, 0}, - { 19200000, 480000000, 200, 4, 2, 0}, - { 26000000, 480000000, 960, 26, 2, 0}, - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000, - 48000000, 960000000, tegra_pll_u_freq_table, 1000, - tegra_pll_ops, 0, clk_m); - -static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { - /* 1 GHz */ - { 12000000, 1000000000, 1000, 12, 1, 12}, - { 13000000, 1000000000, 1000, 13, 1, 12}, - { 19200000, 1000000000, 625, 12, 1, 8}, - { 26000000, 1000000000, 1000, 26, 1, 12}, - - /* 912 MHz */ - { 12000000, 912000000, 912, 12, 1, 12}, - { 13000000, 912000000, 912, 13, 1, 12}, - { 19200000, 912000000, 760, 16, 1, 8}, - { 26000000, 912000000, 912, 26, 1, 12}, - - /* 816 MHz */ - { 12000000, 816000000, 816, 12, 1, 12}, - { 13000000, 816000000, 816, 13, 1, 12}, - { 19200000, 816000000, 680, 16, 1, 8}, - { 26000000, 816000000, 816, 26, 1, 12}, - - /* 760 MHz */ - { 12000000, 760000000, 760, 12, 1, 12}, - { 13000000, 760000000, 760, 13, 1, 12}, - { 19200000, 760000000, 950, 24, 1, 8}, - { 26000000, 760000000, 760, 26, 1, 12}, - - /* 750 MHz */ - { 12000000, 750000000, 750, 12, 1, 12}, - { 13000000, 750000000, 750, 13, 1, 12}, - { 19200000, 750000000, 625, 16, 1, 8}, - { 26000000, 750000000, 750, 26, 1, 12}, - - /* 608 MHz */ - { 12000000, 608000000, 608, 12, 1, 12}, - { 13000000, 608000000, 608, 13, 1, 12}, - { 19200000, 608000000, 380, 12, 1, 8}, - { 26000000, 608000000, 608, 26, 1, 12}, - - /* 456 MHz */ - { 12000000, 456000000, 456, 12, 1, 12}, - { 13000000, 456000000, 456, 13, 1, 12}, - { 19200000, 456000000, 380, 16, 1, 8}, - { 26000000, 456000000, 456, 26, 1, 12}, - - /* 312 MHz */ - { 12000000, 312000000, 312, 12, 1, 12}, - { 13000000, 312000000, 312, 13, 1, 12}, - { 19200000, 312000000, 260, 16, 1, 8}, - { 26000000, 312000000, 312, 26, 1, 12}, - - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000, - 31000000, 1000000, 6000000, 20000000, 1200000000, - tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m); - -static struct clk_pll_freq_table tegra_pll_e_freq_table[] = { - { 12000000, 100000000, 200, 24, 1, 0 }, - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0, - 0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m); - -static const char *tegra_common_parent_names[] = { - "clk_m", -}; - -static struct clk *tegra_common_parents[] = { - &tegra_clk_m, -}; - -static struct clk tegra_clk_d; -static struct clk_tegra tegra_clk_d_hw = { - .hw = { - .clk = &tegra_clk_d, - }, - .flags = PERIPH_NO_RESET, - .reg = 0x34, - .reg_shift = 12, - .max_rate = 52000000, - .u.periph = { - .clk_num = 90, - }, -}; - -static struct clk tegra_clk_d = { - .name = "clk_d", - .hw = &tegra_clk_d_hw.hw, - .ops = &tegra_clk_double_ops, - .parent = &tegra_clk_m, - .parent_names = tegra_common_parent_names, - .parents = tegra_common_parents, - .num_parents = ARRAY_SIZE(tegra_common_parent_names), -}; - -static struct clk tegra_cdev1; -static struct clk_tegra tegra_cdev1_hw = { - .hw = { - .clk = &tegra_cdev1, - }, - .fixed_rate = 26000000, - .u.periph = { - .clk_num = 94, - }, -}; -static struct clk tegra_cdev1 = { - .name = "cdev1", - .hw = &tegra_cdev1_hw.hw, - .ops = &tegra_cdev_clk_ops, - .flags = CLK_IS_ROOT, -}; - -/* dap_mclk2, belongs to the cdev2 pingroup. */ -static struct clk tegra_cdev2; -static struct clk_tegra tegra_cdev2_hw = { - .hw = { - .clk = &tegra_cdev2, - }, - .fixed_rate = 26000000, - .u.periph = { - .clk_num = 93, - }, -}; -static struct clk tegra_cdev2 = { - .name = "cdev2", - .hw = &tegra_cdev2_hw.hw, - .ops = &tegra_cdev_clk_ops, - .flags = CLK_IS_ROOT, -}; - -/* initialized before peripheral clocks */ -static struct clk_mux_sel mux_audio_sync_clk[8+1]; -static const struct audio_sources { - const char *name; - int value; -} mux_audio_sync_clk_sources[] = { - { .name = "spdif_in", .value = 0 }, - { .name = "i2s1", .value = 1 }, - { .name = "i2s2", .value = 2 }, - { .name = "pll_a_out0", .value = 4 }, -#if 0 /* FIXME: not implemented */ - { .name = "ac97", .value = 3 }, - { .name = "ext_audio_clk2", .value = 5 }, - { .name = "ext_audio_clk1", .value = 6 }, - { .name = "ext_vimclk", .value = 7 }, -#endif - { NULL, 0 } -}; - -static const char *audio_parent_names[] = { - "spdif_in", - "i2s1", - "i2s2", - "dummy", - "pll_a_out0", - "dummy", - "dummy", - "dummy", -}; - -static struct clk *audio_parents[] = { - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, -}; - -static struct clk tegra_audio; -static struct clk_tegra tegra_audio_hw = { - .hw = { - .clk = &tegra_audio, - }, - .reg = 0x38, - .max_rate = 73728000, -}; -DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names, - audio_parents, NULL); - -static const char *audio_2x_parent_names[] = { - "audio", -}; - -static struct clk *audio_2x_parents[] = { - &tegra_audio, -}; - -static struct clk tegra_audio_2x; -static struct clk_tegra tegra_audio_2x_hw = { - .hw = { - .clk = &tegra_audio_2x, - }, - .flags = PERIPH_NO_RESET, - .max_rate = 48000000, - .reg = 0x34, - .reg_shift = 8, - .u.periph = { - .clk_num = 89, - }, -}; -DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names, - audio_2x_parents, &tegra_audio); - -static struct clk_lookup tegra_audio_clk_lookups[] = { - { .con_id = "audio", .clk = &tegra_audio }, - { .con_id = "audio_2x", .clk = &tegra_audio_2x } -}; - -/* This is called after peripheral clocks are initialized, as the - * audio_sync clock depends on some of the peripheral clocks. - */ - -static void init_audio_sync_clock_mux(void) -{ - int i; - struct clk_mux_sel *sel = mux_audio_sync_clk; - const struct audio_sources *src = mux_audio_sync_clk_sources; - struct clk_lookup *lookup; - - for (i = 0; src->name; i++, sel++, src++) { - sel->input = tegra_get_clock_by_name(src->name); - if (!sel->input) - pr_err("%s: could not find clk %s\n", __func__, - src->name); - audio_parents[src->value] = sel->input; - sel->value = src->value; - } - - lookup = tegra_audio_clk_lookups; - for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) { - struct clk *c = lookup->clk; - struct clk_tegra *clk = to_clk_tegra(c->hw); - __clk_init(NULL, c); - INIT_LIST_HEAD(&clk->shared_bus_list); - clk->lookup.con_id = lookup->con_id; - clk->lookup.clk = c; - clkdev_add(&clk->lookup); - tegra_clk_add(c); - } -} - -static const char *mux_cclk[] = { - "clk_m", - "pll_c", - "clk_32k", - "pll_m", - "pll_p", - "pll_p_out4", - "pll_p_out3", - "clk_d", - "pll_x", -}; - - -static struct clk *mux_cclk_p[] = { - &tegra_clk_m, - &tegra_pll_c, - &tegra_clk_32k, - &tegra_pll_m, - &tegra_pll_p, - &tegra_pll_p_out4, - &tegra_pll_p_out3, - &tegra_clk_d, - &tegra_pll_x, -}; - -static const char *mux_sclk[] = { - "clk_m", - "pll_c_out1", - "pll_p_out4", - "pllp_p_out3", - "pll_p_out2", - "clk_d", - "clk_32k", - "pll_m_out1", -}; - -static struct clk *mux_sclk_p[] = { - &tegra_clk_m, - &tegra_pll_c_out1, - &tegra_pll_p_out4, - &tegra_pll_p_out3, - &tegra_pll_p_out2, - &tegra_clk_d, - &tegra_clk_32k, - &tegra_pll_m_out1, -}; - -static struct clk tegra_cclk; -static struct clk_tegra tegra_cclk_hw = { - .hw = { - .clk = &tegra_cclk, - }, - .reg = 0x20, - .max_rate = 1000000000, -}; -DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk, - mux_cclk_p, NULL); - -static const char *mux_twd[] = { - "cclk", -}; - -static struct clk *mux_twd_p[] = { - &tegra_cclk, -}; - -static struct clk tegra_clk_twd; -static struct clk_tegra tegra_clk_twd_hw = { - .hw = { - .clk = &tegra_clk_twd, - }, - .max_rate = 1000000000, - .mul = 1, - .div = 4, -}; - -static struct clk tegra_clk_twd = { - .name = "twd", - .ops = &tegra_twd_ops, - .hw = &tegra_clk_twd_hw.hw, - .parent = &tegra_cclk, - .parent_names = mux_twd, - .parents = mux_twd_p, - .num_parents = ARRAY_SIZE(mux_twd), -}; - -static struct clk tegra_sclk; -static struct clk_tegra tegra_sclk_hw = { - .hw = { - .clk = &tegra_sclk, - }, - .reg = 0x28, - .max_rate = 240000000, - .min_rate = 120000000, -}; -DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk, - mux_sclk_p, NULL); - -static const char *tegra_cop_parent_names[] = { - "tegra_sclk", -}; - -static struct clk *tegra_cop_parents[] = { - &tegra_sclk, -}; - -static struct clk tegra_cop; -static struct clk_tegra tegra_cop_hw = { - .hw = { - .clk = &tegra_cop, - }, - .max_rate = 240000000, - .reset = &tegra2_cop_clk_reset, -}; -DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT, - tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk); - -static const char *tegra_hclk_parent_names[] = { - "tegra_sclk", -}; - -static struct clk *tegra_hclk_parents[] = { - &tegra_sclk, -}; - -static struct clk tegra_hclk; -static struct clk_tegra tegra_hclk_hw = { - .hw = { - .clk = &tegra_hclk, - }, - .flags = DIV_BUS, - .reg = 0x30, - .reg_shift = 4, - .max_rate = 240000000, -}; -DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names, - tegra_hclk_parents, &tegra_sclk); - -static const char *tegra_pclk_parent_names[] = { - "tegra_hclk", -}; - -static struct clk *tegra_pclk_parents[] = { - &tegra_hclk, -}; - -static struct clk tegra_pclk; -static struct clk_tegra tegra_pclk_hw = { - .hw = { - .clk = &tegra_pclk, - }, - .flags = DIV_BUS, - .reg = 0x30, - .reg_shift = 0, - .max_rate = 120000000, -}; -DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names, - tegra_pclk_parents, &tegra_hclk); - -static const char *tegra_blink_parent_names[] = { - "clk_32k", -}; - -static struct clk *tegra_blink_parents[] = { - &tegra_clk_32k, -}; - -static struct clk tegra_blink; -static struct clk_tegra tegra_blink_hw = { - .hw = { - .clk = &tegra_blink, - }, - .reg = 0x40, - .max_rate = 32768, -}; -DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names, - tegra_blink_parents, &tegra_clk_32k); - -static const char *mux_pllm_pllc_pllp_plla[] = { - "pll_m", - "pll_c", - "pll_p", - "pll_a_out0", -}; - -static struct clk *mux_pllm_pllc_pllp_plla_p[] = { - &tegra_pll_m, - &tegra_pll_c, - &tegra_pll_p, - &tegra_pll_a_out0, -}; - -static const char *mux_pllm_pllc_pllp_clkm[] = { - "pll_m", - "pll_c", - "pll_p", - "clk_m", -}; - -static struct clk *mux_pllm_pllc_pllp_clkm_p[] = { - &tegra_pll_m, - &tegra_pll_c, - &tegra_pll_p, - &tegra_clk_m, -}; - -static const char *mux_pllp_pllc_pllm_clkm[] = { - "pll_p", - "pll_c", - "pll_m", - "clk_m", -}; - -static struct clk *mux_pllp_pllc_pllm_clkm_p[] = { - &tegra_pll_p, - &tegra_pll_c, - &tegra_pll_m, - &tegra_clk_m, -}; - -static const char *mux_pllaout0_audio2x_pllp_clkm[] = { - "pll_a_out0", - "audio_2x", - "pll_p", - "clk_m", -}; - -static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = { - &tegra_pll_a_out0, - &tegra_audio_2x, - &tegra_pll_p, - &tegra_clk_m, -}; - -static const char *mux_pllp_plld_pllc_clkm[] = { - "pllp", - "pll_d_out0", - "pll_c", - "clk_m", -}; - -static struct clk *mux_pllp_plld_pllc_clkm_p[] = { - &tegra_pll_p, - &tegra_pll_d_out0, - &tegra_pll_c, - &tegra_clk_m, -}; - -static const char *mux_pllp_pllc_audio_clkm_clk32[] = { - "pll_p", - "pll_c", - "audio", - "clk_m", - "clk_32k", -}; - -static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = { - &tegra_pll_p, - &tegra_pll_c, - &tegra_audio, - &tegra_clk_m, - &tegra_clk_32k, -}; - -static const char *mux_pllp_pllc_pllm[] = { - "pll_p", - "pll_c", - "pll_m" -}; - -static struct clk *mux_pllp_pllc_pllm_p[] = { - &tegra_pll_p, - &tegra_pll_c, - &tegra_pll_m, -}; - -static const char *mux_clk_m[] = { - "clk_m", -}; - -static struct clk *mux_clk_m_p[] = { - &tegra_clk_m, -}; - -static const char *mux_pllp_out3[] = { - "pll_p_out3", -}; - -static struct clk *mux_pllp_out3_p[] = { - &tegra_pll_p_out3, -}; - -static const char *mux_plld[] = { - "pll_d", -}; - -static struct clk *mux_plld_p[] = { - &tegra_pll_d, -}; - -static const char *mux_clk_32k[] = { - "clk_32k", -}; - -static struct clk *mux_clk_32k_p[] = { - &tegra_clk_32k, -}; - -static const char *mux_pclk[] = { - "pclk", -}; - -static struct clk *mux_pclk_p[] = { - &tegra_pclk, -}; - -static struct clk tegra_emc; -static struct clk_tegra tegra_emc_hw = { - .hw = { - .clk = &tegra_emc, - }, - .reg = 0x19c, - .max_rate = 800000000, - .flags = MUX | DIV_U71 | PERIPH_EMC_ENB, - .reset = &tegra2_periph_clk_reset, - .u.periph = { - .clk_num = 57, - }, -}; -DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm, - mux_pllm_pllc_pllp_clkm_p, NULL); - -#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \ - _max, _inputs, _flags) \ - static struct clk tegra_##_name; \ - static struct clk_tegra tegra_##_name##_hw = { \ - .hw = { \ - .clk = &tegra_##_name, \ - }, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .reg = _reg, \ - .flags = _flags, \ - .max_rate = _max, \ - .u.periph = { \ - .clk_num = _clk_num, \ - }, \ - .reset = tegra2_periph_clk_reset, \ - }; \ - static struct clk tegra_##_name = { \ - .name = #_name, \ - .ops = &tegra_periph_clk_ops, \ - .hw = &tegra_##_name##_hw.hw, \ - .parent_names = _inputs, \ - .parents = _inputs##_p, \ - .num_parents = ARRAY_SIZE(_inputs), \ - }; - -PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0); -PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET); -PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0); -PERIPH_CLK(i2s1, "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71); -PERIPH_CLK(i2s2, "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71); -PERIPH_CLK(spdif_out, "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71); -PERIPH_CLK(spdif_in, "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71); -PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM); -PERIPH_CLK(spi, "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(xio, "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(twc, "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(ide, "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */ -PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ -PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ -PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ -PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ -PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ -PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0); -PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0); -PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0); -PERIPH_CLK(vde, "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage and process_id */ -PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */ -/* FIXME: what is la? */ -PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */ -PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ -PERIPH_CLK(i2c1, "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16); -PERIPH_CLK(i2c2, "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16); -PERIPH_CLK(i2c3, "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16); -PERIPH_CLK(dvc, "tegra-i2c.3", "div-clk", 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16); -PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX); -PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX); -PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX); -PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX); -PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX); -PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */ -PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */ -PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */ -PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */ -PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */ -PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */ -PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */ -PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */ -PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */ -PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */ -PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */ -PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */ -PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */ -PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */ -PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */ -PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */ -PERIPH_CLK(dsi, "dsi", NULL, 48, 0, 500000000, mux_plld, 0); /* scales with voltage */ -PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0); -PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */ -PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET); -PERIPH_CLK(pex, NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET); -PERIPH_CLK(afi, NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET); -PERIPH_CLK(pcie_xclk, NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET); - -static struct clk *tegra_list_clks[] = { - &tegra_apbdma, - &tegra_rtc, - &tegra_timer, - &tegra_i2s1, - &tegra_i2s2, - &tegra_spdif_out, - &tegra_spdif_in, - &tegra_pwm, - &tegra_spi, - &tegra_xio, - &tegra_twc, - &tegra_sbc1, - &tegra_sbc2, - &tegra_sbc3, - &tegra_sbc4, - &tegra_ide, - &tegra_ndflash, - &tegra_vfir, - &tegra_sdmmc1, - &tegra_sdmmc2, - &tegra_sdmmc3, - &tegra_sdmmc4, - &tegra_vcp, - &tegra_bsea, - &tegra_bsev, - &tegra_vde, - &tegra_csite, - &tegra_la, - &tegra_owr, - &tegra_nor, - &tegra_mipi, - &tegra_i2c1, - &tegra_i2c2, - &tegra_i2c3, - &tegra_dvc, - &tegra_uarta, - &tegra_uartb, - &tegra_uartc, - &tegra_uartd, - &tegra_uarte, - &tegra_3d, - &tegra_2d, - &tegra_vi, - &tegra_vi_sensor, - &tegra_epp, - &tegra_mpe, - &tegra_host1x, - &tegra_cve, - &tegra_tvo, - &tegra_hdmi, - &tegra_tvdac, - &tegra_disp1, - &tegra_disp2, - &tegra_usbd, - &tegra_usb2, - &tegra_usb3, - &tegra_dsi, - &tegra_csi, - &tegra_isp, - &tegra_csus, - &tegra_pex, - &tegra_afi, - &tegra_pcie_xclk, -}; - -#define CLK_DUPLICATE(_name, _dev, _con) \ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - } - -/* Some clocks may be used by different drivers depending on the board - * configuration. List those here to register them twice in the clock lookup - * table under two names. - */ -static struct clk_duplicate tegra_clk_duplicates[] = { - CLK_DUPLICATE("uarta", "serial8250.0", NULL), - CLK_DUPLICATE("uartb", "serial8250.1", NULL), - CLK_DUPLICATE("uartc", "serial8250.2", NULL), - CLK_DUPLICATE("uartd", "serial8250.3", NULL), - CLK_DUPLICATE("uarte", "serial8250.4", NULL), - CLK_DUPLICATE("usbd", "utmip-pad", NULL), - CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), - CLK_DUPLICATE("usbd", "tegra-otg", NULL), - CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"), - CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"), - CLK_DUPLICATE("epp", "tegra_grhost", "epp"), - CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"), - CLK_DUPLICATE("cop", "tegra-avp", "cop"), - CLK_DUPLICATE("vde", "tegra-aes", "vde"), - CLK_DUPLICATE("cclk", NULL, "cpu"), - CLK_DUPLICATE("twd", "smp_twd", NULL), - CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"), - CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"), - CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"), - CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"), - CLK_DUPLICATE("pll_p", "tegradc.0", "parent"), - CLK_DUPLICATE("pll_p", "tegradc.1", "parent"), - CLK_DUPLICATE("pll_d_out0", "hdmi", "parent"), -}; - -#define CLK(dev, con, ck) \ - { \ - .dev_id = dev, \ - .con_id = con, \ - .clk = ck, \ - } - -static struct clk *tegra_ptr_clks[] = { - &tegra_clk_32k, - &tegra_pll_s, - &tegra_clk_m, - &tegra_pll_m, - &tegra_pll_m_out1, - &tegra_pll_c, - &tegra_pll_c_out1, - &tegra_pll_p, - &tegra_pll_p_out1, - &tegra_pll_p_out2, - &tegra_pll_p_out3, - &tegra_pll_p_out4, - &tegra_pll_a, - &tegra_pll_a_out0, - &tegra_pll_d, - &tegra_pll_d_out0, - &tegra_pll_u, - &tegra_pll_x, - &tegra_pll_e, - &tegra_cclk, - &tegra_clk_twd, - &tegra_sclk, - &tegra_hclk, - &tegra_pclk, - &tegra_clk_d, - &tegra_cdev1, - &tegra_cdev2, - &tegra_blink, - &tegra_cop, - &tegra_emc, -}; - -static void tegra2_init_one_clock(struct clk *c) -{ - struct clk_tegra *clk = to_clk_tegra(c->hw); - int ret; - - ret = __clk_init(NULL, c); - if (ret) - pr_err("clk init failed %s\n", __clk_get_name(c)); - - INIT_LIST_HEAD(&clk->shared_bus_list); - if (!clk->lookup.dev_id && !clk->lookup.con_id) - clk->lookup.con_id = c->name; - clk->lookup.clk = c; - clkdev_add(&clk->lookup); - tegra_clk_add(c); -} - -void __init tegra2_init_clocks(void) -{ - int i; - struct clk *c; - - for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++) - tegra2_init_one_clock(tegra_ptr_clks[i]); - - for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) - tegra2_init_one_clock(tegra_list_clks[i]); - - for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { - c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); - if (!c) { - pr_err("%s: Unknown duplicate clock %s\n", __func__, - tegra_clk_duplicates[i].name); - continue; - } - - tegra_clk_duplicates[i].lookup.clk = c; - clkdev_add(&tegra_clk_duplicates[i].lookup); - } - - init_audio_sync_clock_mux(); - tegra20_cpu_car_ops_init(); -} diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c deleted file mode 100644 index d714777..0000000 --- a/arch/arm/mach-tegra/tegra30_clocks.c +++ /dev/null @@ -1,2506 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra30_clocks.c - * - * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/list.h> -#include <linux/spinlock.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/cpufreq.h> -#include <linux/syscore_ops.h> - -#include <asm/clkdev.h> - -#include <mach/powergate.h> - -#include "clock.h" -#include "fuse.h" -#include "iomap.h" -#include "tegra_cpu_car.h" - -#define USE_PLL_LOCK_BITS 0 - -#define RST_DEVICES_L 0x004 -#define RST_DEVICES_H 0x008 -#define RST_DEVICES_U 0x00C -#define RST_DEVICES_V 0x358 -#define RST_DEVICES_W 0x35C -#define RST_DEVICES_SET_L 0x300 -#define RST_DEVICES_CLR_L 0x304 -#define RST_DEVICES_SET_V 0x430 -#define RST_DEVICES_CLR_V 0x434 -#define RST_DEVICES_NUM 5 - -#define CLK_OUT_ENB_L 0x010 -#define CLK_OUT_ENB_H 0x014 -#define CLK_OUT_ENB_U 0x018 -#define CLK_OUT_ENB_V 0x360 -#define CLK_OUT_ENB_W 0x364 -#define CLK_OUT_ENB_SET_L 0x320 -#define CLK_OUT_ENB_CLR_L 0x324 -#define CLK_OUT_ENB_SET_V 0x440 -#define CLK_OUT_ENB_CLR_V 0x444 -#define CLK_OUT_ENB_NUM 5 - -#define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1) -#define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1) - -#define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32)) -#define PERIPH_CLK_TO_RST_REG(c) \ - periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4) -#define PERIPH_CLK_TO_RST_SET_REG(c) \ - periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8) -#define PERIPH_CLK_TO_RST_CLR_REG(c) \ - periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8) - -#define PERIPH_CLK_TO_ENB_REG(c) \ - periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4) -#define PERIPH_CLK_TO_ENB_SET_REG(c) \ - periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8) -#define PERIPH_CLK_TO_ENB_CLR_REG(c) \ - periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8) - -#define CLK_MASK_ARM 0x44 -#define MISC_CLK_ENB 0x48 - -#define OSC_CTRL 0x50 -#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) -#define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28) -#define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28) -#define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28) -#define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28) -#define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28) -#define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28) -#define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28) -#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) - -#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) -#define OSC_CTRL_PLL_REF_DIV_1 (0<<26) -#define OSC_CTRL_PLL_REF_DIV_2 (1<<26) -#define OSC_CTRL_PLL_REF_DIV_4 (2<<26) - -#define OSC_FREQ_DET 0x58 -#define OSC_FREQ_DET_TRIG (1<<31) - -#define OSC_FREQ_DET_STATUS 0x5C -#define OSC_FREQ_DET_BUSY (1<<31) -#define OSC_FREQ_DET_CNT_MASK 0xFFFF - -#define PERIPH_CLK_SOURCE_I2S1 0x100 -#define PERIPH_CLK_SOURCE_EMC 0x19c -#define PERIPH_CLK_SOURCE_OSC 0x1fc -#define PERIPH_CLK_SOURCE_NUM1 \ - ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4) - -#define PERIPH_CLK_SOURCE_G3D2 0x3b0 -#define PERIPH_CLK_SOURCE_SE 0x42c -#define PERIPH_CLK_SOURCE_NUM2 \ - ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1) - -#define AUDIO_DLY_CLK 0x49c -#define AUDIO_SYNC_CLK_SPDIF 0x4b4 -#define PERIPH_CLK_SOURCE_NUM3 \ - ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1) - -#define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \ - PERIPH_CLK_SOURCE_NUM2 + \ - PERIPH_CLK_SOURCE_NUM3) - -#define CPU_SOFTRST_CTRL 0x380 - -#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF -#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF -#define PERIPH_CLK_SOURCE_DIV_SHIFT 0 -#define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8 -#define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50 -#define PERIPH_CLK_UART_DIV_ENB (1<<24) -#define PERIPH_CLK_VI_SEL_EX_SHIFT 24 -#define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT) -#define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8) -#define PERIPH_CLK_DTV_POLARITY_INV (1<<25) - -#define AUDIO_SYNC_SOURCE_MASK 0x0F -#define AUDIO_SYNC_DISABLE_BIT 0x10 -#define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4) - -#define PLL_BASE 0x0 -#define PLL_BASE_BYPASS (1<<31) -#define PLL_BASE_ENABLE (1<<30) -#define PLL_BASE_REF_ENABLE (1<<29) -#define PLL_BASE_OVERRIDE (1<<28) -#define PLL_BASE_LOCK (1<<27) -#define PLL_BASE_DIVP_MASK (0x7<<20) -#define PLL_BASE_DIVP_SHIFT 20 -#define PLL_BASE_DIVN_MASK (0x3FF<<8) -#define PLL_BASE_DIVN_SHIFT 8 -#define PLL_BASE_DIVM_MASK (0x1F) -#define PLL_BASE_DIVM_SHIFT 0 - -#define PLL_OUT_RATIO_MASK (0xFF<<8) -#define PLL_OUT_RATIO_SHIFT 8 -#define PLL_OUT_OVERRIDE (1<<2) -#define PLL_OUT_CLKEN (1<<1) -#define PLL_OUT_RESET_DISABLE (1<<0) - -#define PLL_MISC(c) \ - (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) -#define PLL_MISC_LOCK_ENABLE(c) \ - (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18)) - -#define PLL_MISC_DCCON_SHIFT 20 -#define PLL_MISC_CPCON_SHIFT 8 -#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT) -#define PLL_MISC_LFCON_SHIFT 4 -#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT) -#define PLL_MISC_VCOCON_SHIFT 0 -#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT) -#define PLLD_MISC_CLKENABLE (1<<30) - -#define PLLU_BASE_POST_DIV (1<<20) - -#define PLLD_BASE_DSIB_MUX_SHIFT 25 -#define PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT) -#define PLLD_BASE_CSI_CLKENABLE (1<<26) -#define PLLD_MISC_DSI_CLKENABLE (1<<30) -#define PLLD_MISC_DIV_RST (1<<23) -#define PLLD_MISC_DCCON_SHIFT 12 - -#define PLLDU_LFCON_SET_DIVN 600 - -/* FIXME: OUT_OF_TABLE_CPCON per pll */ -#define OUT_OF_TABLE_CPCON 0x8 - -#define SUPER_CLK_MUX 0x00 -#define SUPER_STATE_SHIFT 28 -#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT) -#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT) -#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT) -#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT) -#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT) -#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT) -#define SUPER_LP_DIV2_BYPASS (0x1 << 16) -#define SUPER_SOURCE_MASK 0xF -#define SUPER_FIQ_SOURCE_SHIFT 12 -#define SUPER_IRQ_SOURCE_SHIFT 8 -#define SUPER_RUN_SOURCE_SHIFT 4 -#define SUPER_IDLE_SOURCE_SHIFT 0 - -#define SUPER_CLK_DIVIDER 0x04 -#define SUPER_CLOCK_DIV_U71_SHIFT 16 -#define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT) -/* guarantees safe cpu backup */ -#define SUPER_CLOCK_DIV_U71_MIN 0x2 - -#define BUS_CLK_DISABLE (1<<3) -#define BUS_CLK_DIV_MASK 0x3 - -#define PMC_CTRL 0x0 - #define PMC_CTRL_BLINK_ENB (1 << 7) - -#define PMC_DPD_PADS_ORIDE 0x1c - #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20) - -#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0 -#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff -#define PMC_BLINK_TIMER_ENB (1 << 15) -#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16 -#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff - -#define PMC_PLLP_WB0_OVERRIDE 0xf8 -#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12) - -#define UTMIP_PLL_CFG2 0x488 -#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) -#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) -#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) -#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) -#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) - -#define UTMIP_PLL_CFG1 0x484 -#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) -#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) -#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14) -#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12) -#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16) - -#define PLLE_BASE_CML_ENABLE (1<<31) -#define PLLE_BASE_ENABLE (1<<30) -#define PLLE_BASE_DIVCML_SHIFT 24 -#define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT) -#define PLLE_BASE_DIVP_SHIFT 16 -#define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT) -#define PLLE_BASE_DIVN_SHIFT 8 -#define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT) -#define PLLE_BASE_DIVM_SHIFT 0 -#define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT) -#define PLLE_BASE_DIV_MASK \ - (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \ - PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK) -#define PLLE_BASE_DIV(m, n, p, cml) \ - (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \ - ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT)) - -#define PLLE_MISC_SETUP_BASE_SHIFT 16 -#define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT) -#define PLLE_MISC_READY (1<<15) -#define PLLE_MISC_LOCK (1<<11) -#define PLLE_MISC_LOCK_ENABLE (1<<9) -#define PLLE_MISC_SETUP_EX_SHIFT 2 -#define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT) -#define PLLE_MISC_SETUP_MASK \ - (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK) -#define PLLE_MISC_SETUP_VALUE \ - ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT)) - -#define PLLE_SS_CTRL 0x68 -#define PLLE_SS_INCINTRV_SHIFT 24 -#define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT) -#define PLLE_SS_INC_SHIFT 16 -#define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT) -#define PLLE_SS_MAX_SHIFT 0 -#define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT) -#define PLLE_SS_COEFFICIENTS_MASK \ - (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK) -#define PLLE_SS_COEFFICIENTS_12MHZ \ - ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \ - (0x24<<PLLE_SS_MAX_SHIFT)) -#define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10)) - -#define PLLE_AUX 0x48c -#define PLLE_AUX_PLLP_SEL (1<<2) -#define PLLE_AUX_CML_SATA_ENABLE (1<<1) -#define PLLE_AUX_CML_PCIE_ENABLE (1<<0) - -#define PMC_SATA_PWRGT 0x1ac -#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5) -#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4) - -#define ROUND_DIVIDER_UP 0 -#define ROUND_DIVIDER_DOWN 1 - -/* FIXME: recommended safety delay after lock is detected */ -#define PLL_POST_LOCK_DELAY 100 - -/* Tegra CPU clock and reset control regs */ -#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c -#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 -#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 -#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c -#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 - -#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) -#define CPU_RESET(cpu) (0x1111ul << (cpu)) - -#define CLK_RESET_CCLK_BURST 0x20 -#define CLK_RESET_CCLK_DIVIDER 0x24 -#define CLK_RESET_PLLX_BASE 0xe0 -#define CLK_RESET_PLLX_MISC 0xe4 - -#define CLK_RESET_SOURCE_CSITE 0x1d4 - -#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28 -#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4 -#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0 -#define CLK_RESET_CCLK_IDLE_POLICY 1 -#define CLK_RESET_CCLK_RUN_POLICY 2 -#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8 - -#ifdef CONFIG_PM_SLEEP -static struct cpu_clk_suspend_context { - u32 pllx_misc; - u32 pllx_base; - - u32 cpu_burst; - u32 clk_csite_src; - u32 cclk_divider; -} tegra30_cpu_clk_sctx; -#endif - -/** -* Structure defining the fields for USB UTMI clocks Parameters. -*/ -struct utmi_clk_param { - /* Oscillator Frequency in KHz */ - u32 osc_frequency; - /* UTMIP PLL Enable Delay Count */ - u8 enable_delay_count; - /* UTMIP PLL Stable count */ - u8 stable_count; - /* UTMIP PLL Active delay count */ - u8 active_delay_count; - /* UTMIP PLL Xtal frequency count */ - u8 xtal_freq_count; -}; - -static const struct utmi_clk_param utmi_parameters[] = { - { - .osc_frequency = 13000000, - .enable_delay_count = 0x02, - .stable_count = 0x33, - .active_delay_count = 0x05, - .xtal_freq_count = 0x7F - }, - { - .osc_frequency = 19200000, - .enable_delay_count = 0x03, - .stable_count = 0x4B, - .active_delay_count = 0x06, - .xtal_freq_count = 0xBB}, - { - .osc_frequency = 12000000, - .enable_delay_count = 0x02, - .stable_count = 0x2F, - .active_delay_count = 0x04, - .xtal_freq_count = 0x76 - }, - { - .osc_frequency = 26000000, - .enable_delay_count = 0x04, - .stable_count = 0x66, - .active_delay_count = 0x09, - .xtal_freq_count = 0xFE - }, - { - .osc_frequency = 16800000, - .enable_delay_count = 0x03, - .stable_count = 0x41, - .active_delay_count = 0x0A, - .xtal_freq_count = 0xA4 - }, -}; - -static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); -static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); -static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE); - -#define MISC_GP_HIDREV 0x804 - -/* - * Some peripheral clocks share an enable bit, so refcount the enable bits - * in registers CLK_ENABLE_L, ... CLK_ENABLE_W - */ -static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32]; - -#define clk_writel(value, reg) \ - __raw_writel(value, reg_clk_base + (reg)) -#define clk_readl(reg) \ - __raw_readl(reg_clk_base + (reg)) -#define pmc_writel(value, reg) \ - __raw_writel(value, reg_pmc_base + (reg)) -#define pmc_readl(reg) \ - __raw_readl(reg_pmc_base + (reg)) -#define chipid_readl() \ - __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV) - -#define clk_writel_delay(value, reg) \ - do { \ - __raw_writel((value), reg_clk_base + (reg)); \ - udelay(2); \ - } while (0) - -static inline int clk_set_div(struct clk_tegra *c, u32 n) -{ - struct clk *clk = c->hw.clk; - - return clk_set_rate(clk, - (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n); -} - -static inline u32 periph_clk_to_reg( - struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs) -{ - u32 reg = c->u.periph.clk_num / 32; - BUG_ON(reg >= RST_DEVICES_NUM); - if (reg < 3) - reg = reg_L + (reg * offs); - else - reg = reg_V + ((reg - 3) * offs); - return reg; -} - -static unsigned long clk_measure_input_freq(void) -{ - u32 clock_autodetect; - clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); - do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY); - clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS); - if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) { - return 12000000; - } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) { - return 13000000; - } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) { - return 19200000; - } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) { - return 26000000; - } else if (clock_autodetect >= 1025 - 3 && clock_autodetect <= 1025 + 3) { - return 16800000; - } else if (clock_autodetect >= 2344 - 3 && clock_autodetect <= 2344 + 3) { - return 38400000; - } else if (clock_autodetect >= 2928 - 3 && clock_autodetect <= 2928 + 3) { - return 48000000; - } else { - pr_err("%s: Unexpected clock autodetect value %d", __func__, - clock_autodetect); - BUG(); - return 0; - } -} - -static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate, - u32 flags, u32 round_mode) -{ - s64 divider_u71 = parent_rate; - if (!rate) - return -EINVAL; - - if (!(flags & DIV_U71_INT)) - divider_u71 *= 2; - if (round_mode == ROUND_DIVIDER_UP) - divider_u71 += rate - 1; - do_div(divider_u71, rate); - if (flags & DIV_U71_INT) - divider_u71 *= 2; - - if (divider_u71 - 2 < 0) - return 0; - - if (divider_u71 - 2 > 255) - return -EINVAL; - - return divider_u71 - 2; -} - -static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate) -{ - s64 divider_u16; - - divider_u16 = parent_rate; - if (!rate) - return -EINVAL; - divider_u16 += rate - 1; - do_div(divider_u16, rate); - - if (divider_u16 - 1 < 0) - return 0; - - if (divider_u16 - 1 > 0xFFFF) - return -EINVAL; - - return divider_u16 - 1; -} - -static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - return to_clk_tegra(hw)->fixed_rate; -} - -struct clk_ops tegra30_clk_32k_ops = { - .recalc_rate = tegra30_clk_fixed_recalc_rate, -}; - -/* clk_m functions */ -static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - if (!to_clk_tegra(hw)->fixed_rate) - to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq(); - return to_clk_tegra(hw)->fixed_rate; -} - -static void tegra30_clk_m_init(struct clk_hw *hw) -{ - u32 osc_ctrl = clk_readl(OSC_CTRL); - u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK; - u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; - - switch (to_clk_tegra(hw)->fixed_rate) { - case 12000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - break; - case 13000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - break; - case 19200000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - break; - case 26000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - break; - case 16800000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); - break; - case 38400000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2); - break; - case 48000000: - auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ; - BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); - break; - default: - pr_err("%s: Unexpected clock rate %ld", __func__, - to_clk_tegra(hw)->fixed_rate); - BUG(); - } - clk_writel(auto_clock_control, OSC_CTRL); -} - -struct clk_ops tegra30_clk_m_ops = { - .init = tegra30_clk_m_init, - .recalc_rate = tegra30_clk_m_recalc_rate, -}; - -static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u64 rate = parent_rate; - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - - return rate; -} - -struct clk_ops tegra_clk_m_div_ops = { - .recalc_rate = tegra30_clk_m_div_recalc_rate, -}; - -/* PLL reference divider functions */ -static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long rate = parent_rate; - u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK; - - switch (pll_ref_div) { - case OSC_CTRL_PLL_REF_DIV_1: - c->div = 1; - break; - case OSC_CTRL_PLL_REF_DIV_2: - c->div = 2; - break; - case OSC_CTRL_PLL_REF_DIV_4: - c->div = 4; - break; - default: - pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div); - BUG(); - } - c->mul = 1; - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - - return rate; -} - -struct clk_ops tegra_pll_ref_ops = { - .recalc_rate = tegra30_pll_ref_recalc_rate, -}; - -/* super clock functions */ -/* "super clocks" on tegra30 have two-stage muxes, fractional 7.1 divider and - * clock skipping super divider. We will ignore the clock skipping divider, - * since we can't lower the voltage when using the clock skip, but we can if - * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock - * only when its parent is a fixed rate PLL, since we can't change PLL rate - * in this case. - */ -static void tegra30_super_clk_init(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - struct clk_tegra *p = - to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk))); - - c->state = ON; - if (c->flags & DIV_U71) { - /* Init safe 7.1 divider value (does not affect PLLX path) */ - clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT, - c->reg + SUPER_CLK_DIVIDER); - c->mul = 2; - c->div = 2; - if (!(p->flags & PLLX)) - c->div += SUPER_CLOCK_DIV_U71_MIN; - } else - clk_writel(0, c->reg + SUPER_CLK_DIVIDER); -} - -static u8 tegra30_super_clk_get_parent(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - int source; - int shift; - - val = clk_readl(c->reg + SUPER_CLK_MUX); - BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && - ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); - shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? - SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; - source = (val >> shift) & SUPER_SOURCE_MASK; - if (c->flags & DIV_2) - source |= val & SUPER_LP_DIV2_BYPASS; - - return source; -} - -static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index) -{ - struct clk_tegra *c = to_clk_tegra(hw); - struct clk_tegra *p = - to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk))); - u32 val; - int shift; - - val = clk_readl(c->reg + SUPER_CLK_MUX); - BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && - ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); - shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? - SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; - - /* For LP mode super-clock switch between PLLX direct - and divided-by-2 outputs is allowed only when other - than PLLX clock source is current parent */ - if ((c->flags & DIV_2) && (p->flags & PLLX) && - ((index ^ val) & SUPER_LP_DIV2_BYPASS)) { - if (p->flags & PLLX) - return -EINVAL; - val ^= SUPER_LP_DIV2_BYPASS; - clk_writel_delay(val, c->reg); - } - val &= ~(SUPER_SOURCE_MASK << shift); - val |= (index & SUPER_SOURCE_MASK) << shift; - - /* 7.1 divider for CPU super-clock does not affect - PLLX path */ - if (c->flags & DIV_U71) { - u32 div = 0; - if (!(p->flags & PLLX)) { - div = clk_readl(c->reg + - SUPER_CLK_DIVIDER); - div &= SUPER_CLOCK_DIV_U71_MASK; - div >>= SUPER_CLOCK_DIV_U71_SHIFT; - } - c->div = div + 2; - c->mul = 2; - } - clk_writel_delay(val, c->reg); - - return 0; -} - -/* - * Do not use super clocks "skippers", since dividing using a clock skipper - * does not allow the voltage to be scaled down. Instead adjust the rate of - * the parent clock. This requires that the parent of a super clock have no - * other children, otherwise the rate will change underneath the other - * children. Special case: if fixed rate PLL is CPU super clock parent the - * rate of this PLL can't be changed, and it has many other children. In - * this case use 7.1 fractional divider to adjust the super clock rate. - */ -static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - struct clk *parent = __clk_get_parent(hw->clk); - struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent)); - - if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) { - int div = clk_div71_get_divider(parent_rate, - rate, c->flags, ROUND_DIVIDER_DOWN); - div = max(div, SUPER_CLOCK_DIV_U71_MIN); - - clk_writel(div << SUPER_CLOCK_DIV_U71_SHIFT, - c->reg + SUPER_CLK_DIVIDER); - c->div = div + 2; - c->mul = 2; - return 0; - } - return 0; -} - -static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u64 rate = parent_rate; - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - - return rate; -} - -static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - struct clk *parent = __clk_get_parent(hw->clk); - struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent)); - int mul = 2; - int div; - - if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) { - div = clk_div71_get_divider(*prate, - rate, c->flags, ROUND_DIVIDER_DOWN); - div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2; - rate = *prate * mul; - rate += div - 1; /* round up */ - do_div(rate, c->div); - - return rate; - } - return *prate; -} - -struct clk_ops tegra30_super_ops = { - .init = tegra30_super_clk_init, - .set_parent = tegra30_super_clk_set_parent, - .get_parent = tegra30_super_clk_get_parent, - .recalc_rate = tegra30_super_clk_recalc_rate, - .round_rate = tegra30_super_clk_round_rate, - .set_rate = tegra30_super_clk_set_rate, -}; - -static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u64 rate = parent_rate; - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - - return rate; -} - -struct clk_ops tegra30_twd_ops = { - .recalc_rate = tegra30_twd_clk_recalc_rate, -}; - -/* bus clock functions */ -static int tegra30_bus_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - - c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; - return c->state; -} - -static int tegra30_bus_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - val = clk_readl(c->reg); - val &= ~(BUS_CLK_DISABLE << c->reg_shift); - clk_writel(val, c->reg); - - return 0; -} - -static void tegra30_bus_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - val = clk_readl(c->reg); - val |= BUS_CLK_DISABLE << c->reg_shift; - clk_writel(val, c->reg); -} - -static unsigned long tegra30_bus_clk_recalc_rate(struct clk_hw *hw, - unsigned long prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - u64 rate = prate; - - c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; - c->mul = 1; - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - return rate; -} - -static int tegra30_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - int ret = -EINVAL; - u32 val; - int i; - - val = clk_readl(c->reg); - for (i = 1; i <= 4; i++) { - if (rate == parent_rate / i) { - val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); - val |= (i - 1) << c->reg_shift; - clk_writel(val, c->reg); - c->div = i; - c->mul = 1; - ret = 0; - break; - } - } - - return ret; -} - -static long tegra30_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - unsigned long parent_rate = *prate; - s64 divider; - - if (rate >= parent_rate) - return parent_rate; - - divider = parent_rate; - divider += rate - 1; - do_div(divider, rate); - - if (divider < 0) - return divider; - - if (divider > 4) - divider = 4; - do_div(parent_rate, divider); - - return parent_rate; -} - -struct clk_ops tegra30_bus_ops = { - .is_enabled = tegra30_bus_clk_is_enabled, - .enable = tegra30_bus_clk_enable, - .disable = tegra30_bus_clk_disable, - .set_rate = tegra30_bus_clk_set_rate, - .round_rate = tegra30_bus_clk_round_rate, - .recalc_rate = tegra30_bus_clk_recalc_rate, -}; - -/* Blink output functions */ -static int tegra30_blink_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - val = pmc_readl(PMC_CTRL); - c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; - return c->state; -} - -static int tegra30_blink_clk_enable(struct clk_hw *hw) -{ - u32 val; - - val = pmc_readl(PMC_DPD_PADS_ORIDE); - pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); - - val = pmc_readl(PMC_CTRL); - pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL); - - return 0; -} - -static void tegra30_blink_clk_disable(struct clk_hw *hw) -{ - u32 val; - - val = pmc_readl(PMC_CTRL); - pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL); - - val = pmc_readl(PMC_DPD_PADS_ORIDE); - pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); -} - -static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - if (rate >= parent_rate) { - c->div = 1; - pmc_writel(0, c->reg); - } else { - unsigned int on_off; - u32 val; - - on_off = DIV_ROUND_UP(parent_rate / 8, rate); - c->div = on_off * 8; - - val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) << - PMC_BLINK_TIMER_DATA_ON_SHIFT; - on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK; - on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT; - val |= on_off; - val |= PMC_BLINK_TIMER_ENB; - pmc_writel(val, c->reg); - } - - return 0; -} - -static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u64 rate = parent_rate; - u32 val; - u32 mul; - u32 div; - u32 on_off; - - mul = 1; - val = pmc_readl(c->reg); - - if (val & PMC_BLINK_TIMER_ENB) { - on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) & - PMC_BLINK_TIMER_DATA_ON_MASK; - val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT; - val &= PMC_BLINK_TIMER_DATA_OFF_MASK; - on_off += val; - /* each tick in the blink timer is 4 32KHz clocks */ - div = on_off * 4; - } else { - div = 1; - } - - if (mul != 0 && div != 0) { - rate *= mul; - rate += div - 1; /* round up */ - do_div(rate, div); - } - return rate; -} - -static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - int div; - int mul; - long round_rate = *prate; - - mul = 1; - - if (rate >= *prate) { - div = 1; - } else { - div = DIV_ROUND_UP(*prate / 8, rate); - div *= 8; - } - - round_rate *= mul; - round_rate += div - 1; - do_div(round_rate, div); - - return round_rate; -} - -struct clk_ops tegra30_blink_clk_ops = { - .is_enabled = tegra30_blink_clk_is_enabled, - .enable = tegra30_blink_clk_enable, - .disable = tegra30_blink_clk_disable, - .recalc_rate = tegra30_blink_clk_recalc_rate, - .round_rate = tegra30_blink_clk_round_rate, - .set_rate = tegra30_blink_clk_set_rate, -}; - -static void tegra30_utmi_param_configure(struct clk_hw *hw) -{ - unsigned long main_rate = - __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk))); - u32 reg; - int i; - - for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { - if (main_rate == utmi_parameters[i].osc_frequency) - break; - } - - if (i >= ARRAY_SIZE(utmi_parameters)) { - pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate); - return; - } - - reg = clk_readl(UTMIP_PLL_CFG2); - - /* Program UTMIP PLL stable and active counts */ - /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ - reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); - reg |= UTMIP_PLL_CFG2_STABLE_COUNT( - utmi_parameters[i].stable_count); - - reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); - - reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( - utmi_parameters[i].active_delay_count); - - /* Remove power downs from UTMIP PLL control bits */ - reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; - reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; - reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; - - clk_writel(reg, UTMIP_PLL_CFG2); - - /* Program UTMIP PLL delay and oscillator frequency counts */ - reg = clk_readl(UTMIP_PLL_CFG1); - reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); - - reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( - utmi_parameters[i].enable_delay_count); - - reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); - reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( - utmi_parameters[i].xtal_freq_count); - - /* Remove power downs from UTMIP PLL control bits */ - reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; - reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; - reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; - - clk_writel(reg, UTMIP_PLL_CFG1); -} - -/* PLL Functions */ -static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg, - u32 lock_bit) -{ - int ret = 0; - -#if USE_PLL_LOCK_BITS - int i; - for (i = 0; i < c->u.pll.lock_delay; i++) { - if (clk_readl(lock_reg) & lock_bit) { - udelay(PLL_POST_LOCK_DELAY); - return 0; - } - udelay(2); /* timeout = 2 * lock time */ - } - pr_err("Timed out waiting for lock bit on pll %s", - __clk_get_name(hw->clk)); - ret = -1; -#else - udelay(c->u.pll.lock_delay); -#endif - return ret; -} - -static int tegra30_pll_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg + PLL_BASE); - - c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; - return c->state; -} - -static void tegra30_pll_clk_init(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - if (c->flags & PLLU) - tegra30_utmi_param_configure(hw); -} - -static int tegra30_pll_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); - -#if USE_PLL_LOCK_BITS - val = clk_readl(c->reg + PLL_MISC(c)); - val |= PLL_MISC_LOCK_ENABLE(c); - clk_writel(val, c->reg + PLL_MISC(c)); -#endif - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLL_BASE_BYPASS; - val |= PLL_BASE_ENABLE; - clk_writel(val, c->reg + PLL_BASE); - - if (c->flags & PLLM) { - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; - pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); - } - - tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK); - - return 0; -} - -static void tegra30_pll_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); - - val = clk_readl(c->reg); - val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); - clk_writel(val, c->reg); - - if (c->flags & PLLM) { - val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); - val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; - pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); - } -} - -static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val, p_div, old_base; - unsigned long input_rate; - const struct clk_pll_freq_table *sel; - struct clk_pll_freq_table cfg; - - if (c->flags & PLL_FIXED) { - int ret = 0; - if (rate != c->u.pll.fixed_rate) { - pr_err("%s: Can not change %s fixed rate %lu to %lu\n", - __func__, __clk_get_name(hw->clk), - c->u.pll.fixed_rate, rate); - ret = -EINVAL; - } - return ret; - } - - if (c->flags & PLLM) { - if (rate != __clk_get_rate(hw->clk)) { - pr_err("%s: Can not change memory %s rate in flight\n", - __func__, __clk_get_name(hw->clk)); - return -EINVAL; - } - } - - p_div = 0; - input_rate = parent_rate; - - /* Check if the target rate is tabulated */ - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { - if (sel->input_rate == input_rate && sel->output_rate == rate) { - if (c->flags & PLLU) { - BUG_ON(sel->p < 1 || sel->p > 2); - if (sel->p == 1) - p_div = PLLU_BASE_POST_DIV; - } else { - BUG_ON(sel->p < 1); - for (val = sel->p; val > 1; val >>= 1) - p_div++; - p_div <<= PLL_BASE_DIVP_SHIFT; - } - break; - } - } - - /* Configure out-of-table rate */ - if (sel->input_rate == 0) { - unsigned long cfreq; - BUG_ON(c->flags & PLLU); - sel = &cfg; - - switch (input_rate) { - case 12000000: - case 26000000: - cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; - break; - case 13000000: - cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; - break; - case 16800000: - case 19200000: - cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; - break; - default: - pr_err("%s: Unexpected reference rate %lu\n", - __func__, input_rate); - BUG(); - } - - /* Raise VCO to guarantee 0.5% accuracy */ - for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq; - cfg.output_rate <<= 1) - p_div++; - - cfg.p = 0x1 << p_div; - cfg.m = input_rate / cfreq; - cfg.n = cfg.output_rate / cfreq; - cfg.cpcon = OUT_OF_TABLE_CPCON; - - if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) || - (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) || - (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) || - (cfg.output_rate > c->u.pll.vco_max)) { - pr_err("%s: Failed to set %s out-of-table rate %lu\n", - __func__, __clk_get_name(hw->clk), rate); - return -EINVAL; - } - p_div <<= PLL_BASE_DIVP_SHIFT; - } - - c->mul = sel->n; - c->div = sel->m * sel->p; - - old_base = val = clk_readl(c->reg + PLL_BASE); - val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK | - ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK)); - val |= (sel->m << PLL_BASE_DIVM_SHIFT) | - (sel->n << PLL_BASE_DIVN_SHIFT) | p_div; - if (val == old_base) - return 0; - - if (c->state == ON) { - tegra30_pll_clk_disable(hw); - val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); - } - clk_writel(val, c->reg + PLL_BASE); - - if (c->flags & PLL_HAS_CPCON) { - val = clk_readl(c->reg + PLL_MISC(c)); - val &= ~PLL_MISC_CPCON_MASK; - val |= sel->cpcon << PLL_MISC_CPCON_SHIFT; - if (c->flags & (PLLU | PLLD)) { - val &= ~PLL_MISC_LFCON_MASK; - if (sel->n >= PLLDU_LFCON_SET_DIVN) - val |= 0x1 << PLL_MISC_LFCON_SHIFT; - } else if (c->flags & (PLLX | PLLM)) { - val &= ~(0x1 << PLL_MISC_DCCON_SHIFT); - if (rate >= (c->u.pll.vco_max >> 1)) - val |= 0x1 << PLL_MISC_DCCON_SHIFT; - } - clk_writel(val, c->reg + PLL_MISC(c)); - } - - if (c->state == ON) - tegra30_pll_clk_enable(hw); - - c->u.pll.fixed_rate = rate; - - return 0; -} - -static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long input_rate = *prate; - u64 output_rate = *prate; - const struct clk_pll_freq_table *sel; - struct clk_pll_freq_table cfg; - int mul; - int div; - u32 p_div; - u32 val; - - if (c->flags & PLL_FIXED) - return c->u.pll.fixed_rate; - - if (c->flags & PLLM) - return __clk_get_rate(hw->clk); - - p_div = 0; - /* Check if the target rate is tabulated */ - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { - if (sel->input_rate == input_rate && sel->output_rate == rate) { - if (c->flags & PLLU) { - BUG_ON(sel->p < 1 || sel->p > 2); - if (sel->p == 1) - p_div = PLLU_BASE_POST_DIV; - } else { - BUG_ON(sel->p < 1); - for (val = sel->p; val > 1; val >>= 1) - p_div++; - p_div <<= PLL_BASE_DIVP_SHIFT; - } - break; - } - } - - if (sel->input_rate == 0) { - unsigned long cfreq; - BUG_ON(c->flags & PLLU); - sel = &cfg; - - switch (input_rate) { - case 12000000: - case 26000000: - cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; - break; - case 13000000: - cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; - break; - case 16800000: - case 19200000: - cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; - break; - default: - pr_err("%s: Unexpected reference rate %lu\n", - __func__, input_rate); - BUG(); - } - - /* Raise VCO to guarantee 0.5% accuracy */ - for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq; - cfg.output_rate <<= 1) - p_div++; - - cfg.p = 0x1 << p_div; - cfg.m = input_rate / cfreq; - cfg.n = cfg.output_rate / cfreq; - } - - mul = sel->n; - div = sel->m * sel->p; - - output_rate *= mul; - output_rate += div - 1; /* round up */ - do_div(output_rate, div); - - return output_rate; -} - -static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u64 rate = parent_rate; - u32 val = clk_readl(c->reg + PLL_BASE); - - if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { - const struct clk_pll_freq_table *sel; - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { - if (sel->input_rate == parent_rate && - sel->output_rate == c->u.pll.fixed_rate) { - c->mul = sel->n; - c->div = sel->m * sel->p; - break; - } - } - pr_err("Clock %s has unknown fixed frequency\n", - __clk_get_name(hw->clk)); - BUG(); - } else if (val & PLL_BASE_BYPASS) { - c->mul = 1; - c->div = 1; - } else { - c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; - c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; - if (c->flags & PLLU) - c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2; - else - c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >> - PLL_BASE_DIVP_SHIFT)); - } - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - - return rate; -} - -struct clk_ops tegra30_pll_ops = { - .is_enabled = tegra30_pll_clk_is_enabled, - .init = tegra30_pll_clk_init, - .enable = tegra30_pll_clk_enable, - .disable = tegra30_pll_clk_disable, - .recalc_rate = tegra30_pll_recalc_rate, - .round_rate = tegra30_pll_round_rate, - .set_rate = tegra30_pll_clk_set_rate, -}; - -int tegra30_plld_clk_cfg_ex(struct clk_hw *hw, - enum tegra_clk_ex_param p, u32 setting) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val, mask, reg; - - switch (p) { - case TEGRA_CLK_PLLD_CSI_OUT_ENB: - mask = PLLD_BASE_CSI_CLKENABLE; - reg = c->reg + PLL_BASE; - break; - case TEGRA_CLK_PLLD_DSI_OUT_ENB: - mask = PLLD_MISC_DSI_CLKENABLE; - reg = c->reg + PLL_MISC(c); - break; - case TEGRA_CLK_PLLD_MIPI_MUX_SEL: - if (!(c->flags & PLL_ALT_MISC_REG)) { - mask = PLLD_BASE_DSIB_MUX_MASK; - reg = c->reg + PLL_BASE; - break; - } - /* fall through - error since PLLD2 does not have MUX_SEL control */ - default: - return -EINVAL; - } - - val = clk_readl(reg); - if (setting) - val |= mask; - else - val &= ~mask; - clk_writel(val, reg); - return 0; -} - -static int tegra30_plle_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - val = clk_readl(c->reg + PLL_BASE); - c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF; - return c->state; -} - -static void tegra30_plle_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - val = clk_readl(c->reg + PLL_BASE); - val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); - clk_writel(val, c->reg + PLL_BASE); -} - -static void tegra30_plle_training(struct clk_tegra *c) -{ - u32 val; - - /* PLLE is already disabled, and setup cleared; - * create falling edge on PLLE IDDQ input */ - val = pmc_readl(PMC_SATA_PWRGT); - val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; - pmc_writel(val, PMC_SATA_PWRGT); - - val = pmc_readl(PMC_SATA_PWRGT); - val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; - pmc_writel(val, PMC_SATA_PWRGT); - - val = pmc_readl(PMC_SATA_PWRGT); - val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; - pmc_writel(val, PMC_SATA_PWRGT); - - do { - val = clk_readl(c->reg + PLL_MISC(c)); - } while (!(val & PLLE_MISC_READY)); -} - -static int tegra30_plle_configure(struct clk_hw *hw, bool force_training) -{ - struct clk_tegra *c = to_clk_tegra(hw); - struct clk *parent = __clk_get_parent(hw->clk); - const struct clk_pll_freq_table *sel; - u32 val; - - unsigned long rate = c->u.pll.fixed_rate; - unsigned long input_rate = __clk_get_rate(parent); - - for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { - if (sel->input_rate == input_rate && sel->output_rate == rate) - break; - } - - if (sel->input_rate == 0) - return -ENOSYS; - - /* disable PLLE, clear setup fiels */ - tegra30_plle_clk_disable(hw); - - val = clk_readl(c->reg + PLL_MISC(c)); - val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); - clk_writel(val, c->reg + PLL_MISC(c)); - - /* training */ - val = clk_readl(c->reg + PLL_MISC(c)); - if (force_training || (!(val & PLLE_MISC_READY))) - tegra30_plle_training(c); - - /* configure dividers, setup, disable SS */ - val = clk_readl(c->reg + PLL_BASE); - val &= ~PLLE_BASE_DIV_MASK; - val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon); - clk_writel(val, c->reg + PLL_BASE); - c->mul = sel->n; - c->div = sel->m * sel->p; - - val = clk_readl(c->reg + PLL_MISC(c)); - val |= PLLE_MISC_SETUP_VALUE; - val |= PLLE_MISC_LOCK_ENABLE; - clk_writel(val, c->reg + PLL_MISC(c)); - - val = clk_readl(PLLE_SS_CTRL); - val |= PLLE_SS_DISABLE; - clk_writel(val, PLLE_SS_CTRL); - - /* enable and lock PLLE*/ - val = clk_readl(c->reg + PLL_BASE); - val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); - clk_writel(val, c->reg + PLL_BASE); - - tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK); - - return 0; -} - -static int tegra30_plle_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - return tegra30_plle_configure(hw, !c->set); -} - -static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long rate = parent_rate; - u32 val; - - val = clk_readl(c->reg + PLL_BASE); - c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT; - c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT; - c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT; - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - return rate; -} - -struct clk_ops tegra30_plle_ops = { - .is_enabled = tegra30_plle_clk_is_enabled, - .enable = tegra30_plle_clk_enable, - .disable = tegra30_plle_clk_disable, - .recalc_rate = tegra30_plle_clk_recalc_rate, -}; - -/* Clock divider ops */ -static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - if (c->flags & DIV_U71) { - u32 val = clk_readl(c->reg); - val >>= c->reg_shift; - c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; - if (!(val & PLL_OUT_RESET_DISABLE)) - c->state = OFF; - } else { - c->state = ON; - } - return c->state; -} - -static int tegra30_pll_div_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - u32 new_val; - - pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk)); - if (c->flags & DIV_U71) { - val = clk_readl(c->reg); - new_val = val >> c->reg_shift; - new_val &= 0xFFFF; - - new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; - - val &= ~(0xFFFF << c->reg_shift); - val |= new_val << c->reg_shift; - clk_writel_delay(val, c->reg); - return 0; - } else if (c->flags & DIV_2) { - return 0; - } - return -EINVAL; -} - -static void tegra30_pll_div_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - u32 new_val; - - pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk)); - if (c->flags & DIV_U71) { - val = clk_readl(c->reg); - new_val = val >> c->reg_shift; - new_val &= 0xFFFF; - - new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE); - - val &= ~(0xFFFF << c->reg_shift); - val |= new_val << c->reg_shift; - clk_writel_delay(val, c->reg); - } -} - -static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - u32 new_val; - int divider_u71; - - if (c->flags & DIV_U71) { - divider_u71 = clk_div71_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider_u71 >= 0) { - val = clk_readl(c->reg); - new_val = val >> c->reg_shift; - new_val &= 0xFFFF; - if (c->flags & DIV_U71_FIXED) - new_val |= PLL_OUT_OVERRIDE; - new_val &= ~PLL_OUT_RATIO_MASK; - new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT; - - val &= ~(0xFFFF << c->reg_shift); - val |= new_val << c->reg_shift; - clk_writel_delay(val, c->reg); - c->div = divider_u71 + 2; - c->mul = 2; - c->fixed_rate = rate; - return 0; - } - } else if (c->flags & DIV_2) { - c->fixed_rate = rate; - return 0; - } - - return -EINVAL; -} - -static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u64 rate = parent_rate; - - if (c->flags & DIV_U71) { - u32 divu71; - u32 val = clk_readl(c->reg); - val >>= c->reg_shift; - - divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; - c->div = (divu71 + 2); - c->mul = 2; - } else if (c->flags & DIV_2) { - if (c->flags & (PLLD | PLLX)) { - c->div = 2; - c->mul = 1; - } else - BUG(); - } else { - c->div = 1; - c->mul = 1; - } - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - - return rate; -} - -static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk)); - int divider; - - if (prate) - parent_rate = *prate; - - if (c->flags & DIV_U71) { - divider = clk_div71_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider < 0) - return divider; - return DIV_ROUND_UP(parent_rate * 2, divider + 2); - } else if (c->flags & DIV_2) { - *prate = rate * 2; - return rate; - } - - return -EINVAL; -} - -struct clk_ops tegra30_pll_div_ops = { - .is_enabled = tegra30_pll_div_clk_is_enabled, - .enable = tegra30_pll_div_clk_enable, - .disable = tegra30_pll_div_clk_disable, - .set_rate = tegra30_pll_div_clk_set_rate, - .recalc_rate = tegra30_pll_div_clk_recalc_rate, - .round_rate = tegra30_pll_div_clk_round_rate, -}; - -/* Periph clk ops */ -static inline u32 periph_clk_source_mask(struct clk_tegra *c) -{ - if (c->flags & MUX8) - return 7 << 29; - else if (c->flags & MUX_PWM) - return 3 << 28; - else if (c->flags & MUX_CLK_OUT) - return 3 << (c->u.periph.clk_num + 4); - else if (c->flags & PLLD) - return PLLD_BASE_DSIB_MUX_MASK; - else - return 3 << 30; -} - -static inline u32 periph_clk_source_shift(struct clk_tegra *c) -{ - if (c->flags & MUX8) - return 29; - else if (c->flags & MUX_PWM) - return 28; - else if (c->flags & MUX_CLK_OUT) - return c->u.periph.clk_num + 4; - else if (c->flags & PLLD) - return PLLD_BASE_DSIB_MUX_SHIFT; - else - return 30; -} - -static int tegra30_periph_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - c->state = ON; - if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) - c->state = OFF; - if (!(c->flags & PERIPH_NO_RESET)) - if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) - c->state = OFF; - return c->state; -} - -static int tegra30_periph_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; - if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) - return 0; - - clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c)); - if (!(c->flags & PERIPH_NO_RESET) && - !(c->flags & PERIPH_MANUAL_RESET)) { - if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & - PERIPH_CLK_TO_BIT(c)) { - udelay(5); /* reset propagation delay */ - clk_writel(PERIPH_CLK_TO_BIT(c), - PERIPH_CLK_TO_RST_CLR_REG(c)); - } - } - return 0; -} - -static void tegra30_periph_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long val; - - tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; - - if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0) - return; - - /* If peripheral is in the APB bus then read the APB bus to - * flush the write operation in apb bus. This will avoid the - * peripheral access after disabling clock*/ - if (c->flags & PERIPH_ON_APB) - val = chipid_readl(); - - clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c)); -} - -void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long val; - - if (!(c->flags & PERIPH_NO_RESET)) { - if (assert) { - /* If peripheral is in the APB bus then read the APB - * bus to flush the write operation in apb bus. This - * will avoid the peripheral access after disabling - * clock */ - if (c->flags & PERIPH_ON_APB) - val = chipid_readl(); - - clk_writel(PERIPH_CLK_TO_BIT(c), - PERIPH_CLK_TO_RST_SET_REG(c)); - } else - clk_writel(PERIPH_CLK_TO_BIT(c), - PERIPH_CLK_TO_RST_CLR_REG(c)); - } -} - -static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - if (!(c->flags & MUX)) - return (index == 0) ? 0 : (-EINVAL); - - val = clk_readl(c->reg); - val &= ~periph_clk_source_mask(c); - val |= (index << periph_clk_source_shift(c)); - clk_writel_delay(val, c->reg); - return 0; -} - -static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - int source = (val & periph_clk_source_mask(c)) >> - periph_clk_source_shift(c); - - if (!(c->flags & MUX)) - return 0; - - return source; -} - -static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - int divider; - - if (c->flags & DIV_U71) { - divider = clk_div71_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider >= 0) { - val = clk_readl(c->reg); - val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK; - val |= divider; - if (c->flags & DIV_U71_UART) { - if (divider) - val |= PERIPH_CLK_UART_DIV_ENB; - else - val &= ~PERIPH_CLK_UART_DIV_ENB; - } - clk_writel_delay(val, c->reg); - c->div = divider + 2; - c->mul = 2; - return 0; - } - } else if (c->flags & DIV_U16) { - divider = clk_div16_get_divider(parent_rate, rate); - if (divider >= 0) { - val = clk_readl(c->reg); - val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; - val |= divider; - clk_writel_delay(val, c->reg); - c->div = divider + 1; - c->mul = 1; - return 0; - } - } else if (parent_rate <= rate) { - c->div = 1; - c->mul = 1; - return 0; - } - return -EINVAL; -} - -static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk)); - int divider; - - if (prate) - parent_rate = *prate; - - if (c->flags & DIV_U71) { - divider = clk_div71_get_divider( - parent_rate, rate, c->flags, ROUND_DIVIDER_UP); - if (divider < 0) - return divider; - - return DIV_ROUND_UP(parent_rate * 2, divider + 2); - } else if (c->flags & DIV_U16) { - divider = clk_div16_get_divider(parent_rate, rate); - if (divider < 0) - return divider; - return DIV_ROUND_UP(parent_rate, divider + 1); - } - return -EINVAL; -} - -static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u64 rate = parent_rate; - u32 val = clk_readl(c->reg); - - if (c->flags & DIV_U71) { - u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; - if ((c->flags & DIV_U71_UART) && - (!(val & PERIPH_CLK_UART_DIV_ENB))) { - divu71 = 0; - } - if (c->flags & DIV_U71_IDLE) { - val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK << - PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); - val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL << - PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); - clk_writel(val, c->reg); - } - c->div = divu71 + 2; - c->mul = 2; - } else if (c->flags & DIV_U16) { - u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; - c->div = divu16 + 1; - c->mul = 1; - } else { - c->div = 1; - c->mul = 1; - } - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - return rate; -} - -struct clk_ops tegra30_periph_clk_ops = { - .is_enabled = tegra30_periph_clk_is_enabled, - .enable = tegra30_periph_clk_enable, - .disable = tegra30_periph_clk_disable, - .set_parent = tegra30_periph_clk_set_parent, - .get_parent = tegra30_periph_clk_get_parent, - .set_rate = tegra30_periph_clk_set_rate, - .round_rate = tegra30_periph_clk_round_rate, - .recalc_rate = tegra30_periph_clk_recalc_rate, -}; - -static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index) -{ - struct clk *d = clk_get_sys(NULL, "pll_d"); - /* The DSIB parent selection bit is in PLLD base register */ - tegra_clk_cfg_ex( - d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index); - - return 0; -} - -struct clk_ops tegra30_dsib_clk_ops = { - .is_enabled = tegra30_periph_clk_is_enabled, - .enable = &tegra30_periph_clk_enable, - .disable = &tegra30_periph_clk_disable, - .set_parent = &tegra30_dsib_clk_set_parent, - .get_parent = &tegra30_periph_clk_get_parent, - .set_rate = &tegra30_periph_clk_set_rate, - .round_rate = &tegra30_periph_clk_round_rate, - .recalc_rate = &tegra30_periph_clk_recalc_rate, -}; - -/* Periph extended clock configuration ops */ -int tegra30_vi_clk_cfg_ex(struct clk_hw *hw, - enum tegra_clk_ex_param p, u32 setting) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - if (p == TEGRA_CLK_VI_INP_SEL) { - u32 val = clk_readl(c->reg); - val &= ~PERIPH_CLK_VI_SEL_EX_MASK; - val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) & - PERIPH_CLK_VI_SEL_EX_MASK; - clk_writel(val, c->reg); - return 0; - } - return -EINVAL; -} - -int tegra30_nand_clk_cfg_ex(struct clk_hw *hw, - enum tegra_clk_ex_param p, u32 setting) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) { - u32 val = clk_readl(c->reg); - if (setting) - val |= PERIPH_CLK_NAND_DIV_EX_ENB; - else - val &= ~PERIPH_CLK_NAND_DIV_EX_ENB; - clk_writel(val, c->reg); - return 0; - } - return -EINVAL; -} - -int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw, - enum tegra_clk_ex_param p, u32 setting) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - if (p == TEGRA_CLK_DTV_INVERT) { - u32 val = clk_readl(c->reg); - if (setting) - val |= PERIPH_CLK_DTV_POLARITY_INV; - else - val &= ~PERIPH_CLK_DTV_POLARITY_INV; - clk_writel(val, c->reg); - return 0; - } - return -EINVAL; -} - -/* Output clock ops */ - -static DEFINE_SPINLOCK(clk_out_lock); - -static int tegra30_clk_out_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = pmc_readl(c->reg); - - c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF; - c->mul = 1; - c->div = 1; - return c->state; -} - -static int tegra30_clk_out_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - unsigned long flags; - - spin_lock_irqsave(&clk_out_lock, flags); - val = pmc_readl(c->reg); - val |= (0x1 << c->u.periph.clk_num); - pmc_writel(val, c->reg); - spin_unlock_irqrestore(&clk_out_lock, flags); - - return 0; -} - -static void tegra30_clk_out_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - unsigned long flags; - - spin_lock_irqsave(&clk_out_lock, flags); - val = pmc_readl(c->reg); - val &= ~(0x1 << c->u.periph.clk_num); - pmc_writel(val, c->reg); - spin_unlock_irqrestore(&clk_out_lock, flags); -} - -static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - unsigned long flags; - - spin_lock_irqsave(&clk_out_lock, flags); - val = pmc_readl(c->reg); - val &= ~periph_clk_source_mask(c); - val |= (index << periph_clk_source_shift(c)); - pmc_writel(val, c->reg); - spin_unlock_irqrestore(&clk_out_lock, flags); - - return 0; -} - -static u8 tegra30_clk_out_get_parent(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = pmc_readl(c->reg); - int source; - - source = (val & periph_clk_source_mask(c)) >> - periph_clk_source_shift(c); - return source; -} - -struct clk_ops tegra_clk_out_ops = { - .is_enabled = tegra30_clk_out_is_enabled, - .enable = tegra30_clk_out_enable, - .disable = tegra30_clk_out_disable, - .set_parent = tegra30_clk_out_set_parent, - .get_parent = tegra30_clk_out_get_parent, - .recalc_rate = tegra30_clk_fixed_recalc_rate, -}; - -/* Clock doubler ops */ -static int tegra30_clk_double_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - c->state = ON; - if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) - c->state = OFF; - return c->state; -}; - -static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - if (rate == parent_rate) { - val = clk_readl(c->reg) | (0x1 << c->reg_shift); - clk_writel(val, c->reg); - c->mul = 1; - c->div = 1; - return 0; - } else if (rate == 2 * parent_rate) { - val = clk_readl(c->reg) & (~(0x1 << c->reg_shift)); - clk_writel(val, c->reg); - c->mul = 2; - c->div = 1; - return 0; - } - return -EINVAL; -} - -static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u64 rate = parent_rate; - - u32 val = clk_readl(c->reg); - c->mul = val & (0x1 << c->reg_shift) ? 1 : 2; - c->div = 1; - - if (c->mul != 0 && c->div != 0) { - rate *= c->mul; - rate += c->div - 1; /* round up */ - do_div(rate, c->div); - } - - return rate; -} - -static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - unsigned long output_rate = *prate; - - do_div(output_rate, 2); - return output_rate; -} - -struct clk_ops tegra30_clk_double_ops = { - .is_enabled = tegra30_clk_double_is_enabled, - .enable = tegra30_periph_clk_enable, - .disable = tegra30_periph_clk_disable, - .recalc_rate = tegra30_clk_double_recalc_rate, - .round_rate = tegra30_clk_double_round_rate, - .set_rate = tegra30_clk_double_set_rate, -}; - -/* Audio sync clock ops */ -struct clk_ops tegra_sync_source_ops = { - .recalc_rate = tegra30_clk_fixed_recalc_rate, -}; - -static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON; - return c->state; -} - -static int tegra30_audio_sync_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg); - return 0; -} - -static void tegra30_audio_sync_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg); -} - -static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val; - - val = clk_readl(c->reg); - val &= ~AUDIO_SYNC_SOURCE_MASK; - val |= index; - - clk_writel(val, c->reg); - return 0; -} - -static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - int source; - - source = val & AUDIO_SYNC_SOURCE_MASK; - return source; -} - -struct clk_ops tegra30_audio_sync_clk_ops = { - .is_enabled = tegra30_audio_sync_clk_is_enabled, - .enable = tegra30_audio_sync_clk_enable, - .disable = tegra30_audio_sync_clk_disable, - .set_parent = tegra30_audio_sync_clk_set_parent, - .get_parent = tegra30_audio_sync_clk_get_parent, - .recalc_rate = tegra30_clk_fixed_recalc_rate, -}; - -/* cml0 (pcie), and cml1 (sata) clock ops */ -static int tegra30_cml_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - u32 val = clk_readl(c->reg); - c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF; - return c->state; -} - -static int tegra30_cml_clk_enable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - u32 val = clk_readl(c->reg); - val |= (0x1 << c->u.periph.clk_num); - clk_writel(val, c->reg); - - return 0; -} - -static void tegra30_cml_clk_disable(struct clk_hw *hw) -{ - struct clk_tegra *c = to_clk_tegra(hw); - - u32 val = clk_readl(c->reg); - val &= ~(0x1 << c->u.periph.clk_num); - clk_writel(val, c->reg); -} - -struct clk_ops tegra_cml_clk_ops = { - .is_enabled = tegra30_cml_clk_is_enabled, - .enable = tegra30_cml_clk_enable, - .disable = tegra30_cml_clk_disable, - .recalc_rate = tegra30_clk_fixed_recalc_rate, -}; - -struct clk_ops tegra_pciex_clk_ops = { - .recalc_rate = tegra30_clk_fixed_recalc_rate, -}; - -/* Tegra30 CPU clock and reset control functions */ -static void tegra30_wait_cpu_in_reset(u32 cpu) -{ - unsigned int reg; - - do { - reg = readl(reg_clk_base + - TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); - cpu_relax(); - } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ - - return; -} - -static void tegra30_put_cpu_in_reset(u32 cpu) -{ - writel(CPU_RESET(cpu), - reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); - dmb(); -} - -static void tegra30_cpu_out_of_reset(u32 cpu) -{ - writel(CPU_RESET(cpu), - reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); - wmb(); -} - -static void tegra30_enable_cpu_clock(u32 cpu) -{ - unsigned int reg; - - writel(CPU_CLOCK(cpu), - reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); - reg = readl(reg_clk_base + - TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); -} - -static void tegra30_disable_cpu_clock(u32 cpu) -{ - - unsigned int reg; - - reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); - writel(reg | CPU_CLOCK(cpu), - reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); -} - -#ifdef CONFIG_PM_SLEEP -static bool tegra30_cpu_rail_off_ready(void) -{ - unsigned int cpu_rst_status; - int cpu_pwr_status; - - cpu_rst_status = readl(reg_clk_base + - TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); - cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) || - tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) || - tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3); - - if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status) - return false; - - return true; -} - -static void tegra30_cpu_clock_suspend(void) -{ - /* switch coresite to clk_m, save off original source */ - tegra30_cpu_clk_sctx.clk_csite_src = - readl(reg_clk_base + CLK_RESET_SOURCE_CSITE); - writel(3<<30, reg_clk_base + CLK_RESET_SOURCE_CSITE); - - tegra30_cpu_clk_sctx.cpu_burst = - readl(reg_clk_base + CLK_RESET_CCLK_BURST); - tegra30_cpu_clk_sctx.pllx_base = - readl(reg_clk_base + CLK_RESET_PLLX_BASE); - tegra30_cpu_clk_sctx.pllx_misc = - readl(reg_clk_base + CLK_RESET_PLLX_MISC); - tegra30_cpu_clk_sctx.cclk_divider = - readl(reg_clk_base + CLK_RESET_CCLK_DIVIDER); -} - -static void tegra30_cpu_clock_resume(void) -{ - unsigned int reg, policy; - - /* Is CPU complex already running on PLLX? */ - reg = readl(reg_clk_base + CLK_RESET_CCLK_BURST); - policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF; - - if (policy == CLK_RESET_CCLK_IDLE_POLICY) - reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF; - else if (policy == CLK_RESET_CCLK_RUN_POLICY) - reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF; - else - BUG(); - - if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) { - /* restore PLLX settings if CPU is on different PLL */ - writel(tegra30_cpu_clk_sctx.pllx_misc, - reg_clk_base + CLK_RESET_PLLX_MISC); - writel(tegra30_cpu_clk_sctx.pllx_base, - reg_clk_base + CLK_RESET_PLLX_BASE); - - /* wait for PLL stabilization if PLLX was enabled */ - if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30)) - udelay(300); - } - - /* - * Restore original burst policy setting for calls resulting from CPU - * LP2 in idle or system suspend. - */ - writel(tegra30_cpu_clk_sctx.cclk_divider, - reg_clk_base + CLK_RESET_CCLK_DIVIDER); - writel(tegra30_cpu_clk_sctx.cpu_burst, - reg_clk_base + CLK_RESET_CCLK_BURST); - - writel(tegra30_cpu_clk_sctx.clk_csite_src, - reg_clk_base + CLK_RESET_SOURCE_CSITE); -} -#endif - -static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { - .wait_for_reset = tegra30_wait_cpu_in_reset, - .put_in_reset = tegra30_put_cpu_in_reset, - .out_of_reset = tegra30_cpu_out_of_reset, - .enable_clock = tegra30_enable_cpu_clock, - .disable_clock = tegra30_disable_cpu_clock, -#ifdef CONFIG_PM_SLEEP - .rail_off_ready = tegra30_cpu_rail_off_ready, - .suspend = tegra30_cpu_clock_suspend, - .resume = tegra30_cpu_clock_resume, -#endif -}; - -void __init tegra30_cpu_car_ops_init(void) -{ - tegra_cpu_car_ops = &tegra30_cpu_car_ops; -} diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h deleted file mode 100644 index 7a34adb..0000000 --- a/arch/arm/mach-tegra/tegra30_clocks.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __MACH_TEGRA30_CLOCK_H -#define __MACH_TEGRA30_CLOCK_H - -extern struct clk_ops tegra30_clk_32k_ops; -extern struct clk_ops tegra30_clk_m_ops; -extern struct clk_ops tegra_clk_m_div_ops; -extern struct clk_ops tegra_pll_ref_ops; -extern struct clk_ops tegra30_pll_ops; -extern struct clk_ops tegra30_pll_div_ops; -extern struct clk_ops tegra_plld_ops; -extern struct clk_ops tegra30_plle_ops; -extern struct clk_ops tegra_cml_clk_ops; -extern struct clk_ops tegra_pciex_clk_ops; -extern struct clk_ops tegra_sync_source_ops; -extern struct clk_ops tegra30_audio_sync_clk_ops; -extern struct clk_ops tegra30_clk_double_ops; -extern struct clk_ops tegra_clk_out_ops; -extern struct clk_ops tegra30_super_ops; -extern struct clk_ops tegra30_blink_clk_ops; -extern struct clk_ops tegra30_twd_ops; -extern struct clk_ops tegra30_bus_ops; -extern struct clk_ops tegra30_periph_clk_ops; -extern struct clk_ops tegra30_dsib_clk_ops; -extern struct clk_ops tegra_nand_clk_ops; -extern struct clk_ops tegra_vi_clk_ops; -extern struct clk_ops tegra_dtv_clk_ops; -extern struct clk_ops tegra_clk_shared_bus_ops; - -int tegra30_plld_clk_cfg_ex(struct clk_hw *hw, - enum tegra_clk_ex_param p, u32 setting); -void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert); -int tegra30_vi_clk_cfg_ex(struct clk_hw *hw, - enum tegra_clk_ex_param p, u32 setting); -int tegra30_nand_clk_cfg_ex(struct clk_hw *hw, - enum tegra_clk_ex_param p, u32 setting); -int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw, - enum tegra_clk_ex_param p, u32 setting); -#endif diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c deleted file mode 100644 index 6942c7a..0000000 --- a/arch/arm/mach-tegra/tegra30_clocks_data.c +++ /dev/null @@ -1,1425 +0,0 @@ -/* - * arch/arm/mach-tegra/tegra30_clocks.c - * - * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - */ - -#include <linux/clk-private.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/list.h> -#include <linux/spinlock.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/cpufreq.h> - -#include "clock.h" -#include "fuse.h" -#include "tegra30_clocks.h" -#include "tegra_cpu_car.h" - -#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \ - _parent_names, _parents, _parent) \ - static struct clk tegra_##_name = { \ - .hw = &tegra_##_name##_hw.hw, \ - .name = #_name, \ - .rate = _rate, \ - .ops = _ops, \ - .flags = _flags, \ - .parent_names = _parent_names, \ - .parents = _parents, \ - .num_parents = ARRAY_SIZE(_parent_names), \ - .parent = _parent, \ - }; - -static struct clk tegra_clk_32k; -static struct clk_tegra tegra_clk_32k_hw = { - .hw = { - .clk = &tegra_clk_32k, - }, - .fixed_rate = 32768, -}; -static struct clk tegra_clk_32k = { - .name = "clk_32k", - .hw = &tegra_clk_32k_hw.hw, - .ops = &tegra30_clk_32k_ops, - .flags = CLK_IS_ROOT, -}; - -static struct clk tegra_clk_m; -static struct clk_tegra tegra_clk_m_hw = { - .hw = { - .clk = &tegra_clk_m, - }, - .flags = ENABLE_ON_INIT, - .reg = 0x1fc, - .reg_shift = 28, - .max_rate = 48000000, -}; -static struct clk tegra_clk_m = { - .name = "clk_m", - .hw = &tegra_clk_m_hw.hw, - .ops = &tegra30_clk_m_ops, - .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED, -}; - -static const char *clk_m_div_parent_names[] = { - "clk_m", -}; - -static struct clk *clk_m_div_parents[] = { - &tegra_clk_m, -}; - -static struct clk tegra_clk_m_div2; -static struct clk_tegra tegra_clk_m_div2_hw = { - .hw = { - .clk = &tegra_clk_m_div2, - }, - .mul = 1, - .div = 2, - .max_rate = 24000000, -}; -DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0, - clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m); - -static struct clk tegra_clk_m_div4; -static struct clk_tegra tegra_clk_m_div4_hw = { - .hw = { - .clk = &tegra_clk_m_div4, - }, - .mul = 1, - .div = 4, - .max_rate = 12000000, -}; -DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0, - clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m); - -static struct clk tegra_pll_ref; -static struct clk_tegra tegra_pll_ref_hw = { - .hw = { - .clk = &tegra_pll_ref, - }, - .flags = ENABLE_ON_INIT, - .max_rate = 26000000, -}; -DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names, - clk_m_div_parents, &tegra_clk_m); - -#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \ - _input_max, _cf_min, _cf_max, _vco_min, \ - _vco_max, _freq_table, _lock_delay, _ops, \ - _fixed_rate, _clk_cfg_ex, _parent) \ - static struct clk tegra_##_name; \ - static const char *_name##_parent_names[] = { \ - #_parent, \ - }; \ - static struct clk *_name##_parents[] = { \ - &tegra_##_parent, \ - }; \ - static struct clk_tegra tegra_##_name##_hw = { \ - .hw = { \ - .clk = &tegra_##_name, \ - }, \ - .flags = _flags, \ - .reg = _reg, \ - .max_rate = _max_rate, \ - .u.pll = { \ - .input_min = _input_min, \ - .input_max = _input_max, \ - .cf_min = _cf_min, \ - .cf_max = _cf_max, \ - .vco_min = _vco_min, \ - .vco_max = _vco_max, \ - .freq_table = _freq_table, \ - .lock_delay = _lock_delay, \ - .fixed_rate = _fixed_rate, \ - }, \ - .clk_cfg_ex = _clk_cfg_ex, \ - }; \ - DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED, \ - _name##_parent_names, _name##_parents, \ - &tegra_##_parent); - -#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \ - _max_rate, _ops, _parent, _clk_flags) \ - static const char *_name##_parent_names[] = { \ - #_parent, \ - }; \ - static struct clk *_name##_parents[] = { \ - &tegra_##_parent, \ - }; \ - static struct clk tegra_##_name; \ - static struct clk_tegra tegra_##_name##_hw = { \ - .hw = { \ - .clk = &tegra_##_name, \ - }, \ - .flags = _flags, \ - .reg = _reg, \ - .max_rate = _max_rate, \ - .reg_shift = _reg_shift, \ - }; \ - DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops, \ - _clk_flags, _name##_parent_names, \ - _name##_parents, &tegra_##_parent); - -static struct clk_pll_freq_table tegra_pll_c_freq_table[] = { - { 12000000, 1040000000, 520, 6, 1, 8}, - { 13000000, 1040000000, 480, 6, 1, 8}, - { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */ - { 19200000, 1040000000, 325, 6, 1, 6}, - { 26000000, 1040000000, 520, 13, 1, 8}, - - { 12000000, 832000000, 416, 6, 1, 8}, - { 13000000, 832000000, 832, 13, 1, 8}, - { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */ - { 19200000, 832000000, 260, 6, 1, 8}, - { 26000000, 832000000, 416, 13, 1, 8}, - - { 12000000, 624000000, 624, 12, 1, 8}, - { 13000000, 624000000, 624, 13, 1, 8}, - { 16800000, 600000000, 520, 14, 1, 8}, - { 19200000, 624000000, 520, 16, 1, 8}, - { 26000000, 624000000, 624, 26, 1, 8}, - - { 12000000, 600000000, 600, 12, 1, 8}, - { 13000000, 600000000, 600, 13, 1, 8}, - { 16800000, 600000000, 500, 14, 1, 8}, - { 19200000, 600000000, 375, 12, 1, 6}, - { 26000000, 600000000, 600, 26, 1, 8}, - - { 12000000, 520000000, 520, 12, 1, 8}, - { 13000000, 520000000, 520, 13, 1, 8}, - { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */ - { 19200000, 520000000, 325, 12, 1, 6}, - { 26000000, 520000000, 520, 26, 1, 8}, - - { 12000000, 416000000, 416, 12, 1, 8}, - { 13000000, 416000000, 416, 13, 1, 8}, - { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */ - { 19200000, 416000000, 260, 12, 1, 6}, - { 26000000, 416000000, 416, 26, 1, 8}, - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000, - 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300, - tegra30_pll_ops, 0, NULL, pll_ref); - -DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000, - tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED); - -static struct clk_pll_freq_table tegra_pll_m_freq_table[] = { - { 12000000, 666000000, 666, 12, 1, 8}, - { 13000000, 666000000, 666, 13, 1, 8}, - { 16800000, 666000000, 555, 14, 1, 8}, - { 19200000, 666000000, 555, 16, 1, 8}, - { 26000000, 666000000, 666, 26, 1, 8}, - { 12000000, 600000000, 600, 12, 1, 8}, - { 13000000, 600000000, 600, 13, 1, 8}, - { 16800000, 600000000, 500, 14, 1, 8}, - { 19200000, 600000000, 375, 12, 1, 6}, - { 26000000, 600000000, 600, 26, 1, 8}, - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000, - 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table, - 300, tegra30_pll_ops, 0, NULL, pll_ref); - -DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000, - tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED); - -static struct clk_pll_freq_table tegra_pll_p_freq_table[] = { - { 12000000, 216000000, 432, 12, 2, 8}, - { 13000000, 216000000, 432, 13, 2, 8}, - { 16800000, 216000000, 360, 14, 2, 8}, - { 19200000, 216000000, 360, 16, 2, 8}, - { 26000000, 216000000, 432, 26, 2, 8}, - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000, - 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000, - tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL, - pll_ref); - -DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, - 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED); -DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, - 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED); -DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, - 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED); -DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, - 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED); - -static struct clk_pll_freq_table tegra_pll_a_freq_table[] = { - { 9600000, 564480000, 294, 5, 1, 4}, - { 9600000, 552960000, 288, 5, 1, 4}, - { 9600000, 24000000, 5, 2, 1, 1}, - - { 28800000, 56448000, 49, 25, 1, 1}, - { 28800000, 73728000, 64, 25, 1, 1}, - { 28800000, 24000000, 5, 6, 1, 1}, - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000, - 6000000, 20000000, 1400000000, tegra_pll_a_freq_table, - 300, tegra30_pll_ops, 0, NULL, pll_p_out1); - -DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops, - pll_a, CLK_IGNORE_UNUSED); - -static struct clk_pll_freq_table tegra_pll_d_freq_table[] = { - { 12000000, 216000000, 216, 12, 1, 4}, - { 13000000, 216000000, 216, 13, 1, 4}, - { 16800000, 216000000, 180, 14, 1, 4}, - { 19200000, 216000000, 180, 16, 1, 4}, - { 26000000, 216000000, 216, 26, 1, 4}, - - { 12000000, 594000000, 594, 12, 1, 8}, - { 13000000, 594000000, 594, 13, 1, 8}, - { 16800000, 594000000, 495, 14, 1, 8}, - { 19200000, 594000000, 495, 16, 1, 8}, - { 26000000, 594000000, 594, 26, 1, 8}, - - { 12000000, 1000000000, 1000, 12, 1, 12}, - { 13000000, 1000000000, 1000, 13, 1, 12}, - { 19200000, 1000000000, 625, 12, 1, 8}, - { 26000000, 1000000000, 1000, 26, 1, 12}, - - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000, - 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table, - 1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref); - -DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops, - pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED); - -DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000, - 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000, - tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL, - pll_ref); - -DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops, - pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED); - -static struct clk_pll_freq_table tegra_pll_u_freq_table[] = { - { 12000000, 480000000, 960, 12, 2, 12}, - { 13000000, 480000000, 960, 13, 2, 12}, - { 16800000, 480000000, 400, 7, 2, 5}, - { 19200000, 480000000, 200, 4, 2, 3}, - { 26000000, 480000000, 960, 26, 2, 12}, - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000, - 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table, - 1000, tegra30_pll_ops, 0, NULL, pll_ref); - -static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { - /* 1.7 GHz */ - { 12000000, 1700000000, 850, 6, 1, 8}, - { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */ - { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */ - { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */ - { 26000000, 1700000000, 850, 13, 1, 8}, - - /* 1.6 GHz */ - { 12000000, 1600000000, 800, 6, 1, 8}, - { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */ - { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */ - { 19200000, 1600000000, 500, 6, 1, 8}, - { 26000000, 1600000000, 800, 13, 1, 8}, - - /* 1.5 GHz */ - { 12000000, 1500000000, 750, 6, 1, 8}, - { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */ - { 16800000, 1500000000, 625, 7, 1, 8}, - { 19200000, 1500000000, 625, 8, 1, 8}, - { 26000000, 1500000000, 750, 13, 1, 8}, - - /* 1.4 GHz */ - { 12000000, 1400000000, 700, 6, 1, 8}, - { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */ - { 16800000, 1400000000, 1000, 12, 1, 8}, - { 19200000, 1400000000, 875, 12, 1, 8}, - { 26000000, 1400000000, 700, 13, 1, 8}, - - /* 1.3 GHz */ - { 12000000, 1300000000, 975, 9, 1, 8}, - { 13000000, 1300000000, 1000, 10, 1, 8}, - { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */ - { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */ - { 26000000, 1300000000, 650, 13, 1, 8}, - - /* 1.2 GHz */ - { 12000000, 1200000000, 1000, 10, 1, 8}, - { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */ - { 16800000, 1200000000, 1000, 14, 1, 8}, - { 19200000, 1200000000, 1000, 16, 1, 8}, - { 26000000, 1200000000, 600, 13, 1, 8}, - - /* 1.1 GHz */ - { 12000000, 1100000000, 825, 9, 1, 8}, - { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */ - { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */ - { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */ - { 26000000, 1100000000, 550, 13, 1, 8}, - - /* 1 GHz */ - { 12000000, 1000000000, 1000, 12, 1, 8}, - { 13000000, 1000000000, 1000, 13, 1, 8}, - { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */ - { 19200000, 1000000000, 625, 12, 1, 8}, - { 26000000, 1000000000, 1000, 26, 1, 8}, - - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000, - 2000000, 31000000, 1000000, 6000000, 20000000, 1700000000, - tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref); - -DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops, - pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED); - -static struct clk_pll_freq_table tegra_pll_e_freq_table[] = { - /* PLLE special case: use cpcon field to store cml divider value */ - { 12000000, 100000000, 150, 1, 18, 11}, - { 216000000, 100000000, 200, 18, 24, 13}, - { 0, 0, 0, 0, 0, 0 }, -}; - -DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000, - 12000000, 12000000, 1200000000, 2400000000U, - tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL, - pll_ref); - -static const char *mux_plle[] = { - "pll_e", -}; - -static struct clk *mux_plle_p[] = { - &tegra_pll_e, -}; - -static struct clk tegra_cml0; -static struct clk_tegra tegra_cml0_hw = { - .hw = { - .clk = &tegra_cml0, - }, - .reg = 0x48c, - .fixed_rate = 100000000, - .u.periph = { - .clk_num = 0, - }, -}; -DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle, - mux_plle_p, &tegra_pll_e); - -static struct clk tegra_cml1; -static struct clk_tegra tegra_cml1_hw = { - .hw = { - .clk = &tegra_cml1, - }, - .reg = 0x48c, - .fixed_rate = 100000000, - .u.periph = { - .clk_num = 1, - }, -}; -DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle, - mux_plle_p, &tegra_pll_e); - -static struct clk tegra_pciex; -static struct clk_tegra tegra_pciex_hw = { - .hw = { - .clk = &tegra_pciex, - }, - .reg = 0x48c, - .fixed_rate = 100000000, - .reset = tegra30_periph_clk_reset, - .u.periph = { - .clk_num = 74, - }, -}; -DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle, - mux_plle_p, &tegra_pll_e); - -#define SYNC_SOURCE(_name) \ - static struct clk tegra_##_name##_sync; \ - static struct clk_tegra tegra_##_name##_sync_hw = { \ - .hw = { \ - .clk = &tegra_##_name##_sync, \ - }, \ - .max_rate = 24000000, \ - .fixed_rate = 24000000, \ - }; \ - static struct clk tegra_##_name##_sync = { \ - .name = #_name "_sync", \ - .hw = &tegra_##_name##_sync_hw.hw, \ - .ops = &tegra_sync_source_ops, \ - .flags = CLK_IS_ROOT, \ - }; - -SYNC_SOURCE(spdif_in); -SYNC_SOURCE(i2s0); -SYNC_SOURCE(i2s1); -SYNC_SOURCE(i2s2); -SYNC_SOURCE(i2s3); -SYNC_SOURCE(i2s4); -SYNC_SOURCE(vimclk); - -static struct clk *tegra_sync_source_list[] = { - &tegra_spdif_in_sync, - &tegra_i2s0_sync, - &tegra_i2s1_sync, - &tegra_i2s2_sync, - &tegra_i2s3_sync, - &tegra_i2s4_sync, - &tegra_vimclk_sync, -}; - -static const char *mux_audio_sync_clk[] = { - "spdif_in_sync", - "i2s0_sync", - "i2s1_sync", - "i2s2_sync", - "i2s3_sync", - "i2s4_sync", - "vimclk_sync", -}; - -#define AUDIO_SYNC_CLK(_name, _index) \ - static struct clk tegra_##_name; \ - static struct clk_tegra tegra_##_name##_hw = { \ - .hw = { \ - .clk = &tegra_##_name, \ - }, \ - .max_rate = 24000000, \ - .reg = 0x4A0 + (_index) * 4, \ - }; \ - static struct clk tegra_##_name = { \ - .name = #_name, \ - .ops = &tegra30_audio_sync_clk_ops, \ - .hw = &tegra_##_name##_hw.hw, \ - .parent_names = mux_audio_sync_clk, \ - .parents = tegra_sync_source_list, \ - .num_parents = ARRAY_SIZE(mux_audio_sync_clk), \ - }; - -AUDIO_SYNC_CLK(audio0, 0); -AUDIO_SYNC_CLK(audio1, 1); -AUDIO_SYNC_CLK(audio2, 2); -AUDIO_SYNC_CLK(audio3, 3); -AUDIO_SYNC_CLK(audio4, 4); -AUDIO_SYNC_CLK(audio5, 5); - -static struct clk *tegra_clk_audio_list[] = { - &tegra_audio0, - &tegra_audio1, - &tegra_audio2, - &tegra_audio3, - &tegra_audio4, - &tegra_audio5, /* SPDIF */ -}; - -#define AUDIO_SYNC_2X_CLK(_name, _index) \ - static const char *_name##_parent_names[] = { \ - "tegra_" #_name, \ - }; \ - static struct clk *_name##_parents[] = { \ - &tegra_##_name, \ - }; \ - static struct clk tegra_##_name##_2x; \ - static struct clk_tegra tegra_##_name##_2x_hw = { \ - .hw = { \ - .clk = &tegra_##_name##_2x, \ - }, \ - .flags = PERIPH_NO_RESET, \ - .max_rate = 48000000, \ - .reg = 0x49C, \ - .reg_shift = 24 + (_index), \ - .u.periph = { \ - .clk_num = 113 + (_index), \ - }, \ - }; \ - static struct clk tegra_##_name##_2x = { \ - .name = #_name "_2x", \ - .ops = &tegra30_clk_double_ops, \ - .hw = &tegra_##_name##_2x_hw.hw, \ - .parent_names = _name##_parent_names, \ - .parents = _name##_parents, \ - .parent = &tegra_##_name, \ - .num_parents = 1, \ - }; - -AUDIO_SYNC_2X_CLK(audio0, 0); -AUDIO_SYNC_2X_CLK(audio1, 1); -AUDIO_SYNC_2X_CLK(audio2, 2); -AUDIO_SYNC_2X_CLK(audio3, 3); -AUDIO_SYNC_2X_CLK(audio4, 4); -AUDIO_SYNC_2X_CLK(audio5, 5); /* SPDIF */ - -static struct clk *tegra_clk_audio_2x_list[] = { - &tegra_audio0_2x, - &tegra_audio1_2x, - &tegra_audio2_2x, - &tegra_audio3_2x, - &tegra_audio4_2x, - &tegra_audio5_2x, /* SPDIF */ -}; - -#define MUX_I2S_SPDIF(_id) \ -static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { \ - "pll_a_out0", \ - #_id "_2x", \ - "pll_p", \ - "clk_m", \ -}; \ -static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = { \ - &tegra_pll_a_out0, \ - &tegra_##_id##_2x, \ - &tegra_pll_p, \ - &tegra_clk_m, \ -}; - -MUX_I2S_SPDIF(audio0); -MUX_I2S_SPDIF(audio1); -MUX_I2S_SPDIF(audio2); -MUX_I2S_SPDIF(audio3); -MUX_I2S_SPDIF(audio4); -MUX_I2S_SPDIF(audio5); /* SPDIF */ - -static struct clk tegra_extern1; -static struct clk tegra_extern2; -static struct clk tegra_extern3; - -/* External clock outputs (through PMC) */ -#define MUX_EXTERN_OUT(_id) \ -static const char *mux_clkm_clkm2_clkm4_extern##_id[] = { \ - "clk_m", \ - "clk_m_div2", \ - "clk_m_div4", \ - "extern" #_id, \ -}; \ -static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = { \ - &tegra_clk_m, \ - &tegra_clk_m_div2, \ - &tegra_clk_m_div4, \ - &tegra_extern##_id, \ -}; - -MUX_EXTERN_OUT(1); -MUX_EXTERN_OUT(2); -MUX_EXTERN_OUT(3); - -#define CLK_OUT_CLK(_name, _index) \ - static struct clk tegra_##_name; \ - static struct clk_tegra tegra_##_name##_hw = { \ - .hw = { \ - .clk = &tegra_##_name, \ - }, \ - .lookup = { \ - .dev_id = #_name, \ - .con_id = "extern" #_index, \ - }, \ - .flags = MUX_CLK_OUT, \ - .fixed_rate = 216000000, \ - .reg = 0x1a8, \ - .u.periph = { \ - .clk_num = (_index - 1) * 8 + 2, \ - }, \ - }; \ - static struct clk tegra_##_name = { \ - .name = #_name, \ - .ops = &tegra_clk_out_ops, \ - .hw = &tegra_##_name##_hw.hw, \ - .parent_names = mux_clkm_clkm2_clkm4_extern##_index, \ - .parents = mux_clkm_clkm2_clkm4_extern##_index##_p, \ - .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\ - }; - -CLK_OUT_CLK(clk_out_1, 1); -CLK_OUT_CLK(clk_out_2, 2); -CLK_OUT_CLK(clk_out_3, 3); - -static struct clk *tegra_clk_out_list[] = { - &tegra_clk_out_1, - &tegra_clk_out_2, - &tegra_clk_out_3, -}; - -static const char *mux_sclk[] = { - "clk_m", - "pll_c_out1", - "pll_p_out4", - "pll_p_out3", - "pll_p_out2", - "dummy", - "clk_32k", - "pll_m_out1", -}; - -static struct clk *mux_sclk_p[] = { - &tegra_clk_m, - &tegra_pll_c_out1, - &tegra_pll_p_out4, - &tegra_pll_p_out3, - &tegra_pll_p_out2, - NULL, - &tegra_clk_32k, - &tegra_pll_m_out1, -}; - -static struct clk tegra_clk_sclk; -static struct clk_tegra tegra_clk_sclk_hw = { - .hw = { - .clk = &tegra_clk_sclk, - }, - .reg = 0x28, - .max_rate = 334000000, - .min_rate = 40000000, -}; - -static struct clk tegra_clk_sclk = { - .name = "sclk", - .ops = &tegra30_super_ops, - .hw = &tegra_clk_sclk_hw.hw, - .parent_names = mux_sclk, - .parents = mux_sclk_p, - .num_parents = ARRAY_SIZE(mux_sclk), -}; - -static const char *tegra_hclk_parent_names[] = { - "tegra_sclk", -}; - -static struct clk *tegra_hclk_parents[] = { - &tegra_clk_sclk, -}; - -static struct clk tegra_hclk; -static struct clk_tegra tegra_hclk_hw = { - .hw = { - .clk = &tegra_hclk, - }, - .flags = DIV_BUS, - .reg = 0x30, - .reg_shift = 4, - .max_rate = 378000000, - .min_rate = 12000000, -}; -DEFINE_CLK_TEGRA(hclk, 0, &tegra30_bus_ops, 0, tegra_hclk_parent_names, - tegra_hclk_parents, &tegra_clk_sclk); - -static const char *tegra_pclk_parent_names[] = { - "tegra_hclk", -}; - -static struct clk *tegra_pclk_parents[] = { - &tegra_hclk, -}; - -static struct clk tegra_pclk; -static struct clk_tegra tegra_pclk_hw = { - .hw = { - .clk = &tegra_pclk, - }, - .flags = DIV_BUS, - .reg = 0x30, - .reg_shift = 0, - .max_rate = 167000000, - .min_rate = 12000000, -}; -DEFINE_CLK_TEGRA(pclk, 0, &tegra30_bus_ops, 0, tegra_pclk_parent_names, - tegra_pclk_parents, &tegra_hclk); - -static const char *mux_blink[] = { - "clk_32k", -}; - -static struct clk *mux_blink_p[] = { - &tegra_clk_32k, -}; - -static struct clk tegra_clk_blink; -static struct clk_tegra tegra_clk_blink_hw = { - .hw = { - .clk = &tegra_clk_blink, - }, - .reg = 0x40, - .max_rate = 32768, -}; -static struct clk tegra_clk_blink = { - .name = "blink", - .ops = &tegra30_blink_clk_ops, - .hw = &tegra_clk_blink_hw.hw, - .parent = &tegra_clk_32k, - .parent_names = mux_blink, - .parents = mux_blink_p, - .num_parents = ARRAY_SIZE(mux_blink), -}; - -static const char *mux_pllm_pllc_pllp_plla[] = { - "pll_m", - "pll_c", - "pll_p", - "pll_a_out0", -}; - -static const char *mux_pllp_pllc_pllm_clkm[] = { - "pll_p", - "pll_c", - "pll_m", - "clk_m", -}; - -static const char *mux_pllp_clkm[] = { - "pll_p", - "dummy", - "dummy", - "clk_m", -}; - -static const char *mux_pllp_plld_pllc_clkm[] = { - "pll_p", - "pll_d_out0", - "pll_c", - "clk_m", -}; - -static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { - "pll_p", - "pll_m", - "pll_d_out0", - "pll_a_out0", - "pll_c", - "pll_d2_out0", - "clk_m", -}; - -static const char *mux_plla_pllc_pllp_clkm[] = { - "pll_a_out0", - "dummy", - "pll_p", - "clk_m" -}; - -static const char *mux_pllp_pllc_clk32_clkm[] = { - "pll_p", - "pll_c", - "clk_32k", - "clk_m", -}; - -static const char *mux_pllp_pllc_clkm_clk32[] = { - "pll_p", - "pll_c", - "clk_m", - "clk_32k", -}; - -static const char *mux_pllp_pllc_pllm[] = { - "pll_p", - "pll_c", - "pll_m", -}; - -static const char *mux_clk_m[] = { - "clk_m", -}; - -static const char *mux_pllp_out3[] = { - "pll_p_out3", -}; - -static const char *mux_plld_out0[] = { - "pll_d_out0", -}; - -static const char *mux_plld_out0_plld2_out0[] = { - "pll_d_out0", - "pll_d2_out0", -}; - -static const char *mux_clk_32k[] = { - "clk_32k", -}; - -static const char *mux_plla_clk32_pllp_clkm_plle[] = { - "pll_a_out0", - "clk_32k", - "pll_p", - "clk_m", - "pll_e", -}; - -static const char *mux_cclk_g[] = { - "clk_m", - "pll_c", - "clk_32k", - "pll_m", - "pll_p", - "pll_p_out4", - "pll_p_out3", - "dummy", - "pll_x", -}; - -static struct clk *mux_pllm_pllc_pllp_plla_p[] = { - &tegra_pll_m, - &tegra_pll_c, - &tegra_pll_p, - &tegra_pll_a_out0, -}; - -static struct clk *mux_pllp_pllc_pllm_clkm_p[] = { - &tegra_pll_p, - &tegra_pll_c, - &tegra_pll_m, - &tegra_clk_m, -}; - -static struct clk *mux_pllp_clkm_p[] = { - &tegra_pll_p, - NULL, - NULL, - &tegra_clk_m, -}; - -static struct clk *mux_pllp_plld_pllc_clkm_p[] = { - &tegra_pll_p, - &tegra_pll_d_out0, - &tegra_pll_c, - &tegra_clk_m, -}; - -static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = { - &tegra_pll_p, - &tegra_pll_m, - &tegra_pll_d_out0, - &tegra_pll_a_out0, - &tegra_pll_c, - &tegra_pll_d2_out0, - &tegra_clk_m, -}; - -static struct clk *mux_plla_pllc_pllp_clkm_p[] = { - &tegra_pll_a_out0, - NULL, - &tegra_pll_p, - &tegra_clk_m, -}; - -static struct clk *mux_pllp_pllc_clk32_clkm_p[] = { - &tegra_pll_p, - &tegra_pll_c, - &tegra_clk_32k, - &tegra_clk_m, -}; - -static struct clk *mux_pllp_pllc_clkm_clk32_p[] = { - &tegra_pll_p, - &tegra_pll_c, - &tegra_clk_m, - &tegra_clk_32k, -}; - -static struct clk *mux_pllp_pllc_pllm_p[] = { - &tegra_pll_p, - &tegra_pll_c, - &tegra_pll_m, -}; - -static struct clk *mux_clk_m_p[] = { - &tegra_clk_m, -}; - -static struct clk *mux_pllp_out3_p[] = { - &tegra_pll_p_out3, -}; - -static struct clk *mux_plld_out0_p[] = { - &tegra_pll_d_out0, -}; - -static struct clk *mux_plld_out0_plld2_out0_p[] = { - &tegra_pll_d_out0, - &tegra_pll_d2_out0, -}; - -static struct clk *mux_clk_32k_p[] = { - &tegra_clk_32k, -}; - -static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = { - &tegra_pll_a_out0, - &tegra_clk_32k, - &tegra_pll_p, - &tegra_clk_m, - &tegra_pll_e, -}; - -static struct clk *mux_cclk_g_p[] = { - &tegra_clk_m, - &tegra_pll_c, - &tegra_clk_32k, - &tegra_pll_m, - &tegra_pll_p, - &tegra_pll_p_out4, - &tegra_pll_p_out3, - NULL, - &tegra_pll_x, -}; - -static struct clk tegra_clk_cclk_g; -static struct clk_tegra tegra_clk_cclk_g_hw = { - .hw = { - .clk = &tegra_clk_cclk_g, - }, - .flags = DIV_U71 | DIV_U71_INT, - .reg = 0x368, - .max_rate = 1700000000, -}; -static struct clk tegra_clk_cclk_g = { - .name = "cclk_g", - .ops = &tegra30_super_ops, - .hw = &tegra_clk_cclk_g_hw.hw, - .parent_names = mux_cclk_g, - .parents = mux_cclk_g_p, - .num_parents = ARRAY_SIZE(mux_cclk_g), -}; - -static const char *mux_twd[] = { - "cclk_g", -}; - -static struct clk *mux_twd_p[] = { - &tegra_clk_cclk_g, -}; - -static struct clk tegra30_clk_twd; -static struct clk_tegra tegra30_clk_twd_hw = { - .hw = { - .clk = &tegra30_clk_twd, - }, - .max_rate = 1400000000, - .mul = 1, - .div = 2, -}; - -static struct clk tegra30_clk_twd = { - .name = "twd", - .ops = &tegra30_twd_ops, - .hw = &tegra30_clk_twd_hw.hw, - .parent = &tegra_clk_cclk_g, - .parent_names = mux_twd, - .parents = mux_twd_p, - .num_parents = ARRAY_SIZE(mux_twd), -}; - -#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \ - _max, _inputs, _flags) \ - static struct clk tegra_##_name; \ - static struct clk_tegra tegra_##_name##_hw = { \ - .hw = { \ - .clk = &tegra_##_name, \ - }, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - .reg = _reg, \ - .flags = _flags, \ - .max_rate = _max, \ - .u.periph = { \ - .clk_num = _clk_num, \ - }, \ - .reset = &tegra30_periph_clk_reset, \ - }; \ - static struct clk tegra_##_name = { \ - .name = #_name, \ - .ops = &tegra30_periph_clk_ops, \ - .hw = &tegra_##_name##_hw.hw, \ - .parent_names = _inputs, \ - .parents = _inputs##_p, \ - .num_parents = ARRAY_SIZE(_inputs), \ - }; - -PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0); -PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB); -PERIPH_CLK(kbc, "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB); -PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0); -PERIPH_CLK(kfuse, "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0); -PERIPH_CLK(fuse, "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB); -PERIPH_CLK(fuse_burn, "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB); -PERIPH_CLK(apbif, "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0); -PERIPH_CLK(i2s0, "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(i2s1, "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(i2s2, "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(i2s3, "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(i2s4, "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(spdif_out, "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio5_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(spdif_in, "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(d_audio, "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71); -PERIPH_CLK(dam0, "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71); -PERIPH_CLK(dam1, "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71); -PERIPH_CLK(dam2, "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71); -PERIPH_CLK(hda, "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(hda2codec_2x, "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(hda2hdmi, "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0); -PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(sbc5, "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(sbc6, "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(sata_oob, "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(sata, "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(sata_cold, "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0); -PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(ndspeed, "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ -PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ -PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ -PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ -PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0); -PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0); -PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0); -PERIPH_CLK(vde, "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT); -PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */ -PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); -PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */ -PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */ -PERIPH_CLK(i2c1, "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); -PERIPH_CLK(i2c2, "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); -PERIPH_CLK(i2c3, "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); -PERIPH_CLK(i2c4, "tegra-i2c.3", "div-clk", 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); -PERIPH_CLK(i2c5, "tegra-i2c.4", "div-clk", 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); -PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB); -PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB); -PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB); -PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB); -PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB); -PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT); -PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET); -PERIPH_CLK(3d2, "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET); -PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE); -PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET); -PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT); -PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT); -PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT); -PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */ -PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */ -PERIPH_CLK(dtv, "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0); -PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71); -PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */ -PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8); -PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8); -PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */ -PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */ -PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */ -PERIPH_CLK(dsia, "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0); -PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0); -PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */ -PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET); -PERIPH_CLK(tsensor, "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71); -PERIPH_CLK(actmon, "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71); -PERIPH_CLK(extern1, "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71); -PERIPH_CLK(extern2, "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71); -PERIPH_CLK(extern3, "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71); -PERIPH_CLK(i2cslow, "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB); -PERIPH_CLK(pcie, "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0); -PERIPH_CLK(afi, "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0); -PERIPH_CLK(se, "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT); - -static struct clk tegra_dsib; -static struct clk_tegra tegra_dsib_hw = { - .hw = { - .clk = &tegra_dsib, - }, - .lookup = { - .dev_id = "tegradc.1", - .con_id = "dsib", - }, - .reg = 0xd0, - .flags = MUX | PLLD, - .max_rate = 500000000, - .u.periph = { - .clk_num = 82, - }, - .reset = &tegra30_periph_clk_reset, -}; -static struct clk tegra_dsib = { - .name = "dsib", - .ops = &tegra30_dsib_clk_ops, - .hw = &tegra_dsib_hw.hw, - .parent_names = mux_plld_out0_plld2_out0, - .parents = mux_plld_out0_plld2_out0_p, - .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0), -}; - -struct clk *tegra_list_clks[] = { - &tegra_apbdma, - &tegra_rtc, - &tegra_kbc, - &tegra_timer, - &tegra_kfuse, - &tegra_fuse, - &tegra_fuse_burn, - &tegra_apbif, - &tegra_i2s0, - &tegra_i2s1, - &tegra_i2s2, - &tegra_i2s3, - &tegra_i2s4, - &tegra_spdif_out, - &tegra_spdif_in, - &tegra_pwm, - &tegra_d_audio, - &tegra_dam0, - &tegra_dam1, - &tegra_dam2, - &tegra_hda, - &tegra_hda2codec_2x, - &tegra_hda2hdmi, - &tegra_sbc1, - &tegra_sbc2, - &tegra_sbc3, - &tegra_sbc4, - &tegra_sbc5, - &tegra_sbc6, - &tegra_sata_oob, - &tegra_sata, - &tegra_sata_cold, - &tegra_ndflash, - &tegra_ndspeed, - &tegra_vfir, - &tegra_sdmmc1, - &tegra_sdmmc2, - &tegra_sdmmc3, - &tegra_sdmmc4, - &tegra_vcp, - &tegra_bsea, - &tegra_bsev, - &tegra_vde, - &tegra_csite, - &tegra_la, - &tegra_owr, - &tegra_nor, - &tegra_mipi, - &tegra_i2c1, - &tegra_i2c2, - &tegra_i2c3, - &tegra_i2c4, - &tegra_i2c5, - &tegra_uarta, - &tegra_uartb, - &tegra_uartc, - &tegra_uartd, - &tegra_uarte, - &tegra_vi, - &tegra_3d, - &tegra_3d2, - &tegra_2d, - &tegra_vi_sensor, - &tegra_epp, - &tegra_mpe, - &tegra_host1x, - &tegra_cve, - &tegra_tvo, - &tegra_dtv, - &tegra_hdmi, - &tegra_tvdac, - &tegra_disp1, - &tegra_disp2, - &tegra_usbd, - &tegra_usb2, - &tegra_usb3, - &tegra_dsia, - &tegra_dsib, - &tegra_csi, - &tegra_isp, - &tegra_csus, - &tegra_tsensor, - &tegra_actmon, - &tegra_extern1, - &tegra_extern2, - &tegra_extern3, - &tegra_i2cslow, - &tegra_pcie, - &tegra_afi, - &tegra_se, -}; - -#define CLK_DUPLICATE(_name, _dev, _con) \ - { \ - .name = _name, \ - .lookup = { \ - .dev_id = _dev, \ - .con_id = _con, \ - }, \ - } - -/* Some clocks may be used by different drivers depending on the board - * configuration. List those here to register them twice in the clock lookup - * table under two names. - */ -struct clk_duplicate tegra_clk_duplicates[] = { - CLK_DUPLICATE("uarta", "serial8250.0", NULL), - CLK_DUPLICATE("uartb", "serial8250.1", NULL), - CLK_DUPLICATE("uartc", "serial8250.2", NULL), - CLK_DUPLICATE("uartd", "serial8250.3", NULL), - CLK_DUPLICATE("uarte", "serial8250.4", NULL), - CLK_DUPLICATE("usbd", "utmip-pad", NULL), - CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), - CLK_DUPLICATE("usbd", "tegra-otg", NULL), - CLK_DUPLICATE("dsib", "tegradc.0", "dsib"), - CLK_DUPLICATE("dsia", "tegradc.1", "dsia"), - CLK_DUPLICATE("bsev", "tegra-avp", "bsev"), - CLK_DUPLICATE("bsev", "nvavp", "bsev"), - CLK_DUPLICATE("vde", "tegra-aes", "vde"), - CLK_DUPLICATE("bsea", "tegra-aes", "bsea"), - CLK_DUPLICATE("bsea", "nvavp", "bsea"), - CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL), - CLK_DUPLICATE("cml0", "tegra_pcie", "cml"), - CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"), - CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL), - CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL), - CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL), - CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL), - CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL), - CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL), - CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL), - CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL), - CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL), - CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL), - CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL), - CLK_DUPLICATE("twd", "smp_twd", NULL), - CLK_DUPLICATE("vcp", "nvavp", "vcp"), - CLK_DUPLICATE("i2s0", NULL, "i2s0"), - CLK_DUPLICATE("i2s1", NULL, "i2s1"), - CLK_DUPLICATE("i2s2", NULL, "i2s2"), - CLK_DUPLICATE("i2s3", NULL, "i2s3"), - CLK_DUPLICATE("i2s4", NULL, "i2s4"), - CLK_DUPLICATE("dam0", NULL, "dam0"), - CLK_DUPLICATE("dam1", NULL, "dam1"), - CLK_DUPLICATE("dam2", NULL, "dam2"), - CLK_DUPLICATE("spdif_in", NULL, "spdif_in"), - CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"), - CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"), - CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"), - CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"), - CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"), - CLK_DUPLICATE("pll_p", "tegradc.0", "parent"), - CLK_DUPLICATE("pll_p", "tegradc.1", "parent"), - CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"), -}; - -struct clk *tegra_ptr_clks[] = { - &tegra_clk_32k, - &tegra_clk_m, - &tegra_clk_m_div2, - &tegra_clk_m_div4, - &tegra_pll_ref, - &tegra_pll_m, - &tegra_pll_m_out1, - &tegra_pll_c, - &tegra_pll_c_out1, - &tegra_pll_p, - &tegra_pll_p_out1, - &tegra_pll_p_out2, - &tegra_pll_p_out3, - &tegra_pll_p_out4, - &tegra_pll_a, - &tegra_pll_a_out0, - &tegra_pll_d, - &tegra_pll_d_out0, - &tegra_pll_d2, - &tegra_pll_d2_out0, - &tegra_pll_u, - &tegra_pll_x, - &tegra_pll_x_out0, - &tegra_pll_e, - &tegra_clk_cclk_g, - &tegra_cml0, - &tegra_cml1, - &tegra_pciex, - &tegra_clk_sclk, - &tegra_hclk, - &tegra_pclk, - &tegra_clk_blink, - &tegra30_clk_twd, -}; - -static void tegra30_init_one_clock(struct clk *c) -{ - struct clk_tegra *clk = to_clk_tegra(c->hw); - __clk_init(NULL, c); - INIT_LIST_HEAD(&clk->shared_bus_list); - if (!clk->lookup.dev_id && !clk->lookup.con_id) - clk->lookup.con_id = c->name; - clk->lookup.clk = c; - clkdev_add(&clk->lookup); - tegra_clk_add(c); -} - -void __init tegra30_init_clocks(void) -{ - int i; - struct clk *c; - - for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++) - tegra30_init_one_clock(tegra_ptr_clks[i]); - - for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) - tegra30_init_one_clock(tegra_list_clks[i]); - - for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { - c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); - if (!c) { - pr_err("%s: Unknown duplicate clock %s\n", __func__, - tegra_clk_duplicates[i].name); - continue; - } - - tegra_clk_duplicates[i].lookup.clk = c; - clkdev_add(&tegra_clk_duplicates[i].lookup); - } - - for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++) - tegra30_init_one_clock(tegra_sync_source_list[i]); - for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++) - tegra30_init_one_clock(tegra_clk_audio_list[i]); - for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++) - tegra30_init_one_clock(tegra_clk_audio_2x_list[i]); - - for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) - tegra30_init_one_clock(tegra_clk_out_list[i]); - - tegra30_cpu_car_ops_init(); -} diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h deleted file mode 100644 index 9764d31..0000000 --- a/arch/arm/mach-tegra/tegra_cpu_car.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __MACH_TEGRA_CPU_CAR_H -#define __MACH_TEGRA_CPU_CAR_H - -/* - * Tegra CPU clock and reset control ops - * - * wait_for_reset: - * keep waiting until the CPU in reset state - * put_in_reset: - * put the CPU in reset state - * out_of_reset: - * release the CPU from reset state - * enable_clock: - * CPU clock un-gate - * disable_clock: - * CPU clock gate - * rail_off_ready: - * CPU is ready for rail off - * suspend: - * save the clock settings when CPU go into low-power state - * resume: - * restore the clock settings when CPU exit low-power state - */ -struct tegra_cpu_car_ops { - void (*wait_for_reset)(u32 cpu); - void (*put_in_reset)(u32 cpu); - void (*out_of_reset)(u32 cpu); - void (*enable_clock)(u32 cpu); - void (*disable_clock)(u32 cpu); -#ifdef CONFIG_PM_SLEEP - bool (*rail_off_ready)(void); - void (*suspend)(void); - void (*resume)(void); -#endif -}; - -extern struct tegra_cpu_car_ops *tegra_cpu_car_ops; - -static inline void tegra_wait_cpu_in_reset(u32 cpu) -{ - if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset)) - return; - - tegra_cpu_car_ops->wait_for_reset(cpu); -} - -static inline void tegra_put_cpu_in_reset(u32 cpu) -{ - if (WARN_ON(!tegra_cpu_car_ops->put_in_reset)) - return; - - tegra_cpu_car_ops->put_in_reset(cpu); -} - -static inline void tegra_cpu_out_of_reset(u32 cpu) -{ - if (WARN_ON(!tegra_cpu_car_ops->out_of_reset)) - return; - - tegra_cpu_car_ops->out_of_reset(cpu); -} - -static inline void tegra_enable_cpu_clock(u32 cpu) -{ - if (WARN_ON(!tegra_cpu_car_ops->enable_clock)) - return; - - tegra_cpu_car_ops->enable_clock(cpu); -} - -static inline void tegra_disable_cpu_clock(u32 cpu) -{ - if (WARN_ON(!tegra_cpu_car_ops->disable_clock)) - return; - - tegra_cpu_car_ops->disable_clock(cpu); -} - -#ifdef CONFIG_PM_SLEEP -static inline bool tegra_cpu_rail_off_ready(void) -{ - if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready)) - return false; - - return tegra_cpu_car_ops->rail_off_ready(); -} - -static inline void tegra_cpu_clock_suspend(void) -{ - if (WARN_ON(!tegra_cpu_car_ops->suspend)) - return; - - tegra_cpu_car_ops->suspend(); -} - -static inline void tegra_cpu_clock_resume(void) -{ - if (WARN_ON(!tegra_cpu_car_ops->resume)) - return; - - tegra_cpu_car_ops->resume(); -} -#endif - -void tegra20_cpu_car_ops_init(void); -void tegra30_cpu_car_ops_init(void); - -#endif /* __MACH_TEGRA_CPU_CAR_H */ diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c deleted file mode 100644 index b0036e5..0000000 --- a/arch/arm/mach-tegra/timer.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * arch/arch/mach-tegra/timer.c - * - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/init.h> -#include <linux/err.h> -#include <linux/time.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/clockchips.h> -#include <linux/clocksource.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> - -#include <asm/mach/time.h> -#include <asm/smp_twd.h> -#include <asm/sched_clock.h> - -#include "board.h" - -#define RTC_SECONDS 0x08 -#define RTC_SHADOW_SECONDS 0x0c -#define RTC_MILLISECONDS 0x10 - -#define TIMERUS_CNTR_1US 0x10 -#define TIMERUS_USEC_CFG 0x14 -#define TIMERUS_CNTR_FREEZE 0x4c - -#define TIMER1_BASE 0x0 -#define TIMER2_BASE 0x8 -#define TIMER3_BASE 0x50 -#define TIMER4_BASE 0x58 - -#define TIMER_PTV 0x0 -#define TIMER_PCR 0x4 - -static void __iomem *timer_reg_base; -static void __iomem *rtc_base; - -static struct timespec persistent_ts; -static u64 persistent_ms, last_persistent_ms; - -#define timer_writel(value, reg) \ - __raw_writel(value, timer_reg_base + (reg)) -#define timer_readl(reg) \ - __raw_readl(timer_reg_base + (reg)) - -static int tegra_timer_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - u32 reg; - - reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); - - return 0; -} - -static void tegra_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - u32 reg; - - timer_writel(0, TIMER3_BASE + TIMER_PTV); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - reg = 0xC0000000 | ((1000000/HZ)-1); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); - break; - case CLOCK_EVT_MODE_ONESHOT: - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_RESUME: - break; - } -} - -static struct clock_event_device tegra_clockevent = { - .name = "timer0", - .rating = 300, - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .set_next_event = tegra_timer_set_next_event, - .set_mode = tegra_timer_set_mode, -}; - -static u32 notrace tegra_read_sched_clock(void) -{ - return timer_readl(TIMERUS_CNTR_1US); -} - -/* - * tegra_rtc_read - Reads the Tegra RTC registers - * Care must be taken that this funciton is not called while the - * tegra_rtc driver could be executing to avoid race conditions - * on the RTC shadow register - */ -static u64 tegra_rtc_read_ms(void) -{ - u32 ms = readl(rtc_base + RTC_MILLISECONDS); - u32 s = readl(rtc_base + RTC_SHADOW_SECONDS); - return (u64)s * MSEC_PER_SEC + ms; -} - -/* - * tegra_read_persistent_clock - Return time from a persistent clock. - * - * Reads the time from a source which isn't disabled during PM, the - * 32k sync timer. Convert the cycles elapsed since last read into - * nsecs and adds to a monotonically increasing timespec. - * Care must be taken that this funciton is not called while the - * tegra_rtc driver could be executing to avoid race conditions - * on the RTC shadow register - */ -static void tegra_read_persistent_clock(struct timespec *ts) -{ - u64 delta; - struct timespec *tsp = &persistent_ts; - - last_persistent_ms = persistent_ms; - persistent_ms = tegra_rtc_read_ms(); - delta = persistent_ms - last_persistent_ms; - - timespec_add_ns(tsp, delta * NSEC_PER_MSEC); - *ts = *tsp; -} - -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = (struct clock_event_device *)dev_id; - timer_writel(1<<30, TIMER3_BASE + TIMER_PCR); - evt->event_handler(evt); - return IRQ_HANDLED; -} - -static struct irqaction tegra_timer_irq = { - .name = "timer0", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH, - .handler = tegra_timer_interrupt, - .dev_id = &tegra_clockevent, -}; - -static const struct of_device_id timer_match[] __initconst = { - { .compatible = "nvidia,tegra20-timer" }, - {} -}; - -static const struct of_device_id rtc_match[] __initconst = { - { .compatible = "nvidia,tegra20-rtc" }, - {} -}; - -void __init tegra_init_timer(void) -{ - struct device_node *np; - struct clk *clk; - unsigned long rate; - int ret; - - np = of_find_matching_node(NULL, timer_match); - if (!np) { - pr_err("Failed to find timer DT node\n"); - BUG(); - } - - timer_reg_base = of_iomap(np, 0); - if (!timer_reg_base) { - pr_err("Can't map timer registers"); - BUG(); - } - - tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); - if (tegra_timer_irq.irq <= 0) { - pr_err("Failed to map timer IRQ\n"); - BUG(); - } - - clk = clk_get_sys("timer", NULL); - if (IS_ERR(clk)) { - pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); - rate = 12000000; - } else { - clk_prepare_enable(clk); - rate = clk_get_rate(clk); - } - - of_node_put(np); - - np = of_find_matching_node(NULL, rtc_match); - if (!np) { - pr_err("Failed to find RTC DT node\n"); - BUG(); - } - - rtc_base = of_iomap(np, 0); - if (!rtc_base) { - pr_err("Can't map RTC registers"); - BUG(); - } - - /* - * rtc registers are used by read_persistent_clock, keep the rtc clock - * enabled - */ - clk = clk_get_sys("rtc-tegra", NULL); - if (IS_ERR(clk)) - pr_warn("Unable to get rtc-tegra clock\n"); - else - clk_prepare_enable(clk); - - of_node_put(np); - - switch (rate) { - case 12000000: - timer_writel(0x000b, TIMERUS_USEC_CFG); - break; - case 13000000: - timer_writel(0x000c, TIMERUS_USEC_CFG); - break; - case 19200000: - timer_writel(0x045f, TIMERUS_USEC_CFG); - break; - case 26000000: - timer_writel(0x0019, TIMERUS_USEC_CFG); - break; - default: - WARN(1, "Unknown clock rate"); - } - - setup_sched_clock(tegra_read_sched_clock, 32, 1000000); - - if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { - pr_err("Failed to register clocksource\n"); - BUG(); - } - - ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); - if (ret) { - pr_err("Failed to register timer IRQ: %d\n", ret); - BUG(); - } - - clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5); - tegra_clockevent.max_delta_ns = - clockevent_delta2ns(0x1fffffff, &tegra_clockevent); - tegra_clockevent.min_delta_ns = - clockevent_delta2ns(0x1, &tegra_clockevent); - tegra_clockevent.cpumask = cpu_all_mask; - tegra_clockevent.irq = tegra_timer_irq.irq; - clockevents_register_device(&tegra_clockevent); -#ifdef CONFIG_HAVE_ARM_TWD - twd_local_timer_of_register(); -#endif - register_persistent_clock(NULL, tegra_read_persistent_clock); -} - -#ifdef CONFIG_PM -static u32 usec_config; - -void tegra_timer_suspend(void) -{ - usec_config = timer_readl(TIMERUS_USEC_CFG); -} - -void tegra_timer_resume(void) -{ - timer_writel(usec_config, TIMERUS_USEC_CFG); -} -#endif diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig index 2ed0b7d..c0b1c60 100644 --- a/arch/arm/mach-vt8500/Kconfig +++ b/arch/arm/mach-vt8500/Kconfig @@ -1,12 +1,34 @@ config ARCH_VT8500 - bool "VIA/WonderMedia 85xx" if ARCH_MULTI_V5 - default ARCH_VT8500_SINGLE + bool select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP - select CPU_ARM926T select GENERIC_CLOCKEVENTS select GENERIC_GPIO select HAVE_CLK + select VT8500_TIMER help Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. + +config ARCH_WM8505 + bool "VIA/Wondermedia 85xx and WM8650" + depends on ARCH_MULTI_V5 + select ARCH_VT8500 + select CPU_ARM926T + help + +config ARCH_WM8750 + bool "WonderMedia WM8750" + depends on ARCH_MULTI_V6 + select ARCH_VT8500 + select CPU_V6 + help + Support for WonderMedia WM8750 System-on-Chip. + +config ARCH_WM8850 + bool "WonderMedia WM8850" + depends on ARCH_MULTI_V7 + select ARCH_VT8500 + select CPU_V7 + help + Support for WonderMedia WM8850 System-on-Chip. diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile index e035251..92ceb24 100644 --- a/arch/arm/mach-vt8500/Makefile +++ b/arch/arm/mach-vt8500/Makefile @@ -1 +1 @@ -obj-$(CONFIG_ARCH_VT8500) += irq.o timer.o vt8500.o +obj-$(CONFIG_ARCH_VT8500) += irq.o vt8500.o diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h index 6f2b843..77611a6 100644 --- a/arch/arm/mach-vt8500/common.h +++ b/arch/arm/mach-vt8500/common.h @@ -18,7 +18,6 @@ #include <linux/of.h> -void __init vt8500_timer_init(void); int __init vt8500_irq_init(struct device_node *node, struct device_node *parent); diff --git a/arch/arm/mach-vt8500/include/mach/timex.h b/arch/arm/mach-vt8500/include/mach/timex.h deleted file mode 100644 index 8487e4c..0000000 --- a/arch/arm/mach-vt8500/include/mach/timex.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * arch/arm/mach-vt8500/include/mach/timex.h - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef MACH_TIMEX_H -#define MACH_TIMEX_H - -#define CLOCK_TICK_RATE (3000000) - -#endif /* MACH_TIMEX_H */ diff --git a/arch/arm/mach-vt8500/include/mach/uncompress.h b/arch/arm/mach-vt8500/include/mach/uncompress.h deleted file mode 100644 index e6e81fd..0000000 --- a/arch/arm/mach-vt8500/include/mach/uncompress.h +++ /dev/null @@ -1,37 +0,0 @@ -/* arch/arm/mach-vt8500/include/mach/uncompress.h - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * Based on arch/arm/mach-dove/include/mach/uncompress.h - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#define UART0_PHYS 0xd8200000 -#define UART0_ADDR(x) *(volatile unsigned char *)(UART0_PHYS + x) - -static void putc(const char c) -{ - while (UART0_ADDR(0x1c) & 0x2) - /* Tx busy, wait and poll */; - - UART0_ADDR(0) = c; -} - -static void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c deleted file mode 100644 index 3dd21a4..0000000 --- a/arch/arm/mach-vt8500/timer.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * arch/arm/mach-vt8500/timer.c - * - * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* - * This file is copied and modified from the original timer.c provided by - * Alexey Charkov. Minor changes have been made for Device Tree Support. - */ - -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/interrupt.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> -#include <linux/delay.h> -#include <asm/mach/time.h> - -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> - -#define VT8500_TIMER_OFFSET 0x0100 -#define VT8500_TIMER_HZ 3000000 -#define TIMER_MATCH_VAL 0x0000 -#define TIMER_COUNT_VAL 0x0010 -#define TIMER_STATUS_VAL 0x0014 -#define TIMER_IER_VAL 0x001c /* interrupt enable */ -#define TIMER_CTRL_VAL 0x0020 -#define TIMER_AS_VAL 0x0024 /* access status */ -#define TIMER_COUNT_R_ACTIVE (1 << 5) /* not ready for read */ -#define TIMER_COUNT_W_ACTIVE (1 << 4) /* not ready for write */ -#define TIMER_MATCH_W_ACTIVE (1 << 0) /* not ready for write */ - -#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) - -static void __iomem *regbase; - -static cycle_t vt8500_timer_read(struct clocksource *cs) -{ - int loops = msecs_to_loops(10); - writel(3, regbase + TIMER_CTRL_VAL); - while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE) - && --loops) - cpu_relax(); - return readl(regbase + TIMER_COUNT_VAL); -} - -static struct clocksource clocksource = { - .name = "vt8500_timer", - .rating = 200, - .read = vt8500_timer_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static int vt8500_timer_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - int loops = msecs_to_loops(10); - cycle_t alarm = clocksource.read(&clocksource) + cycles; - while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE) - && --loops) - cpu_relax(); - writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); - - if ((signed)(alarm - clocksource.read(&clocksource)) <= 16) - return -ETIME; - - writel(1, regbase + TIMER_IER_VAL); - - return 0; -} - -static void vt8500_timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - switch (mode) { - case CLOCK_EVT_MODE_RESUME: - case CLOCK_EVT_MODE_PERIODIC: - break; - case CLOCK_EVT_MODE_ONESHOT: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - writel(readl(regbase + TIMER_CTRL_VAL) | 1, - regbase + TIMER_CTRL_VAL); - writel(0, regbase + TIMER_IER_VAL); - break; - } -} - -static struct clock_event_device clockevent = { - .name = "vt8500_timer", - .features = CLOCK_EVT_FEAT_ONESHOT, - .rating = 200, - .set_next_event = vt8500_timer_set_next_event, - .set_mode = vt8500_timer_set_mode, -}; - -static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = dev_id; - writel(0xf, regbase + TIMER_STATUS_VAL); - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction irq = { - .name = "vt8500_timer", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = vt8500_timer_interrupt, - .dev_id = &clockevent, -}; - -static struct of_device_id vt8500_timer_ids[] = { - { .compatible = "via,vt8500-timer" }, - { } -}; - -void __init vt8500_timer_init(void) -{ - struct device_node *np; - int timer_irq; - - np = of_find_matching_node(NULL, vt8500_timer_ids); - if (!np) { - pr_err("%s: Timer description missing from Device Tree\n", - __func__); - return; - } - regbase = of_iomap(np, 0); - if (!regbase) { - pr_err("%s: Missing iobase description in Device Tree\n", - __func__); - of_node_put(np); - return; - } - timer_irq = irq_of_parse_and_map(np, 0); - if (!timer_irq) { - pr_err("%s: Missing irq description in Device Tree\n", - __func__); - of_node_put(np); - return; - } - - writel(1, regbase + TIMER_CTRL_VAL); - writel(0xf, regbase + TIMER_STATUS_VAL); - writel(~0, regbase + TIMER_MATCH_VAL); - - if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ)) - pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n", - __func__, clocksource.name); - - clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4); - - /* copy-pasted from mach-msm; no idea */ - clockevent.max_delta_ns = - clockevent_delta2ns(0xf0000000, &clockevent); - clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent); - clockevent.cpumask = cpumask_of(0); - - if (setup_irq(timer_irq, &irq)) - pr_err("%s: setup_irq failed for %s\n", __func__, - clockevent.name); - clockevents_register_device(&clockevent); -} - diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c index d5b9c66..6141868 100644 --- a/arch/arm/mach-vt8500/vt8500.c +++ b/arch/arm/mach-vt8500/vt8500.c @@ -20,6 +20,7 @@ #include <linux/io.h> #include <linux/pm.h> +#include <linux/vt8500_timer.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -179,6 +180,8 @@ static const char * const vt8500_dt_compat[] = { "via,vt8500", "wm,wm8650", "wm,wm8505", + "wm,wm8750", + "wm,wm8850", }; DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)") diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c index d9c3d6b..30fbca8 100644 --- a/arch/arm/mach-w90x900/time.c +++ b/arch/arm/mach-w90x900/time.c @@ -91,7 +91,6 @@ static int nuc900_clockevent_setnextevent(unsigned long evt, static struct clock_event_device nuc900_clockevent_device = { .name = "nuc900-timer0", - .shift = 32, .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_mode = nuc900_clockevent_setmode, .set_next_event = nuc900_clockevent_setnextevent, @@ -133,15 +132,10 @@ static void __init nuc900_clockevents_init(void) __raw_writel(RESETINT, REG_TISR); setup_irq(IRQ_TIMER0, &nuc900_timer0_irq); - nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC, - nuc900_clockevent_device.shift); - nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff, - &nuc900_clockevent_device); - nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf, - &nuc900_clockevent_device); nuc900_clockevent_device.cpumask = cpumask_of(0); - clockevents_register_device(&nuc900_clockevent_device); + clockevents_config_and_register(&nuc900_clockevent_device, rate, + 0xf, 0xffffffff); } static void __init nuc900_clocksource_init(void) diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 7539ec2..15451ee 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -19,6 +19,52 @@ #include "proc-macros.S" /* + * The secondary kernel init calls v7_flush_dcache_all before it enables + * the L1; however, the L1 comes out of reset in an undefined state, so + * the clean + invalidate performed by v7_flush_dcache_all causes a bunch + * of cache lines with uninitialized data and uninitialized tags to get + * written out to memory, which does really unpleasant things to the main + * processor. We fix this by performing an invalidate, rather than a + * clean + invalidate, before jumping into the kernel. + * + * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs + * to be called for both secondary cores startup and primary core resume + * procedures. + */ +ENTRY(v7_invalidate_l1) + mov r0, #0 + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: subs r3, r3, #1 @ Temp-- + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) + mcr p15, 0, r5, c7, c6, 2 + bgt 2b + cmp r2, #0 + bgt 1b + dsb + isb + mov pc, lr +ENDPROC(v7_invalidate_l1) + +/* * v7_flush_icache_all() * * Flush the whole I-cache. diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 6b2fb87..076c26d 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -774,25 +774,27 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset, size_t size, enum dma_data_direction dir, void (*op)(const void *, size_t, int)) { + unsigned long pfn; + size_t left = size; + + pfn = page_to_pfn(page) + offset / PAGE_SIZE; + offset %= PAGE_SIZE; + /* * A single sg entry may refer to multiple physically contiguous * pages. But we still need to process highmem pages individually. * If highmem is not configured then the bulk of this loop gets * optimized out. */ - size_t left = size; do { size_t len = left; void *vaddr; + page = pfn_to_page(pfn); + if (PageHighMem(page)) { - if (len + offset > PAGE_SIZE) { - if (offset >= PAGE_SIZE) { - page += offset / PAGE_SIZE; - offset %= PAGE_SIZE; - } + if (len + offset > PAGE_SIZE) len = PAGE_SIZE - offset; - } vaddr = kmap_high_get(page); if (vaddr) { vaddr += offset; @@ -809,7 +811,7 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset, op(vaddr, len, dir); } offset = 0; - page++; + pfn++; left -= len; } while (left); } diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 9f06102..ce328c7 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -283,7 +283,7 @@ static struct mem_type mem_types[] = { }, [MT_MEMORY_SO] = { .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | - L_PTE_MT_UNCACHED, + L_PTE_MT_UNCACHED | L_PTE_XN, .prot_l1 = PMD_TYPE_TABLE, .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | PMD_SECT_UNCACHED | PMD_SECT_XN, diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index cbfbbe4..837a2d5 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -156,14 +156,9 @@ void __init iop_init_time(unsigned long tick_rate) write_tmr0(timer_ctl & ~IOP_TMR_EN); write_tisr(1); setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); - clockevents_calc_mult_shift(&iop_clockevent, - tick_rate, IOP_MIN_RANGE); - iop_clockevent.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &iop_clockevent); - iop_clockevent.min_delta_ns = - clockevent_delta2ns(0xf, &iop_clockevent); iop_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&iop_clockevent); + clockevents_config_and_register(&iop_clockevent, tick_rate, + 0xf, 0xfffffffe); /* * Set up free-running clocksource timer 1. diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c index e686fe76..7310bcf 100644 --- a/arch/arm/plat-orion/mpp.c +++ b/arch/arm/plat-orion/mpp.c @@ -49,7 +49,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, "number (%u)\n", num); continue; } - if (variant_mask & !(*mpp_list & variant_mask)) { + if (variant_mask && !(*mpp_list & variant_mask)) { printk(KERN_WARNING "orion_mpp_conf: requested MPP%u config " "unavailable on this hardware\n", num); diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 0f4fa86..5d5ac0f 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -156,7 +156,6 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) static struct clock_event_device orion_clkevt = { .name = "orion_tick", .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .shift = 32, .rating = 300, .set_next_event = orion_clkevt_next_event, .set_mode = orion_clkevt_mode, @@ -221,9 +220,6 @@ orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask, * Setup clockevent timer (interrupt-driven). */ setup_irq(irq, &orion_timer_irq); - orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); - orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt); - orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt); orion_clkevt.cpumask = cpumask_of(0); - clockevents_register_device(&orion_clkevt); + clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe); } diff --git a/arch/arm/plat-samsung/s5p-time.c b/arch/arm/plat-samsung/s5p-time.c index dabede4..e92510c 100644 --- a/arch/arm/plat-samsung/s5p-time.c +++ b/arch/arm/plat-samsung/s5p-time.c @@ -274,15 +274,8 @@ static void __init s5p_clockevent_init(void) clock_rate = clk_get_rate(tin_event); clock_count_per_tick = clock_rate / HZ; - clockevents_calc_mult_shift(&time_event_device, - clock_rate, S5PTIMER_MIN_RANGE); - time_event_device.max_delta_ns = - clockevent_delta2ns(-1, &time_event_device); - time_event_device.min_delta_ns = - clockevent_delta2ns(1, &time_event_device); - time_event_device.cpumask = cpumask_of(0); - clockevents_register_device(&time_event_device); + clockevents_config_and_register(&time_event_device, clock_rate, 1, -1); irq_number = timer_source.event_id + IRQ_TIMER0; setup_irq(irq_number, &s5p_clock_event_irq); diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c index 03321af..bd5c53c 100644 --- a/arch/arm/plat-spear/time.c +++ b/arch/arm/plat-spear/time.c @@ -186,15 +186,9 @@ static void __init spear_clockevent_init(int irq) tick_rate = clk_get_rate(gpt_clk); tick_rate >>= CTRL_PRESCALER16; - clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE); - - clkevt.max_delta_ns = clockevent_delta2ns(0xfff0, - &clkevt); - clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt); - clkevt.cpumask = cpumask_of(0); - clockevents_register_device(&clkevt); + clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0); setup_irq(irq, &spear_timer_irq); } diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S index dd703ef..b178d44 100644 --- a/arch/arm/plat-versatile/headsmp.S +++ b/arch/arm/plat-versatile/headsmp.S @@ -20,7 +20,7 @@ */ ENTRY(versatile_secondary_startup) mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #15 + bic r0, #0xff000000 adr r4, 1f ldmia r4, {r5, r6} sub r4, r4, r5 diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S index cc926c9..323ce1a 100644 --- a/arch/arm/vfp/entry.S +++ b/arch/arm/vfp/entry.S @@ -22,7 +22,7 @@ @ IRQs disabled. @ ENTRY(do_vfp) -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPT_COUNT ldr r4, [r10, #TI_PREEMPT] @ get preempt count add r11, r4, #1 @ increment it str r11, [r10, #TI_PREEMPT] @@ -35,7 +35,7 @@ ENTRY(do_vfp) ENDPROC(do_vfp) ENTRY(vfp_null_entry) -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPT_COUNT get_thread_info r10 ldr r4, [r10, #TI_PREEMPT] @ get preempt count sub r11, r4, #1 @ decrement it @@ -53,7 +53,7 @@ ENDPROC(vfp_null_entry) __INIT ENTRY(vfp_testing_entry) -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPT_COUNT get_thread_info r10 ldr r4, [r10, #TI_PREEMPT] @ get preempt count sub r11, r4, #1 @ decrement it diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index ea0349f..dd5e56f 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -168,7 +168,7 @@ vfp_hw_state_valid: @ else it's one 32-bit instruction, so @ always subtract 4 from the following @ instruction address. -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPT_COUNT get_thread_info r10 ldr r4, [r10, #TI_PREEMPT] @ get preempt count sub r11, r4, #1 @ decrement it @@ -192,7 +192,7 @@ look_for_VFP_exceptions: @ not recognised by VFP DBGSTR "not VFP" -#ifdef CONFIG_PREEMPT +#ifdef CONFIG_PREEMPT_COUNT get_thread_info r10 ldr r4, [r10, #TI_PREEMPT] @ get preempt count sub r11, r4, #1 @ decrement it |
