diff options
Diffstat (limited to 'arch/arm/plat-omap')
43 files changed, 3241 insertions, 553 deletions
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 9dd68fa..efe85d0 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -23,6 +23,11 @@ config ARCH_OMAP3 select CPU_V7 select COMMON_CLKDEV +config ARCH_OMAP4 + bool "TI OMAP4" + select CPU_V7 + select ARM_GIC + endchoice comment "OMAP Feature Selections" @@ -40,7 +45,6 @@ config OMAP_DEBUG_LEDS config OMAP_DEBUG_POWERDOMAIN bool "Emit debug messages from powerdomain layer" depends on ARCH_OMAP2 || ARCH_OMAP3 - default n help Say Y here if you want to compile in powerdomain layer debugging messages for OMAP2/3. These messages can @@ -52,7 +56,6 @@ config OMAP_DEBUG_POWERDOMAIN config OMAP_DEBUG_CLOCKDOMAIN bool "Emit debug messages from clockdomain layer" depends on ARCH_OMAP2 || ARCH_OMAP3 - default n help Say Y here if you want to compile in clockdomain layer debugging messages for OMAP2/3. These messages can @@ -110,11 +113,13 @@ config OMAP_MCBSP config OMAP_MBOX_FWK tristate "Mailbox framework support" depends on ARCH_OMAP - default n help Say Y here if you want to use OMAP Mailbox framework support for DSP, IVA1.0 and IVA2 in OMAP1/2/3. +config OMAP_IOMMU + tristate + choice prompt "System timer" default OMAP_MPU_TIMER @@ -128,13 +133,13 @@ config OMAP_MPU_TIMER config OMAP_32K_TIMER bool "Use 32KHz timer" - depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX + depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4 help Select this option if you want to enable the OMAP 32KHz timer. This timer saves power compared to the OMAP_MPU_TIMER, and has support for no tick during idle. The 32KHz timer provides less intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is - currently only available for OMAP16XX, 24XX and 34XX. + currently only available for OMAP16XX, 24XX, 34XX and OMAP4. endchoice @@ -149,7 +154,7 @@ config OMAP_32K_TIMER_HZ config OMAP_DM_TIMER bool "Use dual-mode timer" - depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX + depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4 help Select this option if you want to use OMAP Dual-Mode timers. @@ -171,7 +176,7 @@ endchoice config OMAP_SERIAL_WAKE bool "Enable wake-up events for serial ports" - depends on OMAP_MUX + depends on ARCH_OMAP1 && OMAP_MUX default y help Select this option if you want to have your system wake up diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 04a100c..a832795 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -13,6 +13,7 @@ obj- := obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o +obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o obj-$(CONFIG_CPU_FREQ) += cpu-omap.o obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 29efc27..e8c327a 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -36,10 +36,40 @@ static struct clk_functions *arch_clock; * Standard clock functions defined in include/linux/clk.h *-------------------------------------------------------------------------*/ +/* This functions is moved to arch/arm/common/clkdev.c. For OMAP4 since + * clock framework is not up , it is defined here to avoid rework in + * every driver. Also dummy prcm reset function is added */ + +/* Dummy hooks only for OMAP4.For rest OMAPs, common clkdev is used */ +#if defined(CONFIG_ARCH_OMAP4) +struct clk *clk_get(struct device *dev, const char *id) +{ + return NULL; +} +EXPORT_SYMBOL(clk_get); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); + +void omap2_clk_prepare_for_reboot(void) +{ +} +EXPORT_SYMBOL(omap2_clk_prepare_for_reboot); + +void omap_prcm_arch_reset(char mode) +{ +} +EXPORT_SYMBOL(omap_prcm_arch_reset); +#endif int clk_enable(struct clk *clk) { unsigned long flags; int ret = 0; + if (cpu_is_omap44xx()) + /* OMAP4 clk framework not supported yet */ + return 0; if (clk == NULL || IS_ERR(clk)) return -EINVAL; @@ -140,6 +170,9 @@ int clk_set_parent(struct clk *clk, struct clk *parent) unsigned long flags; int ret = -EINVAL; + if (cpu_is_omap44xx()) + /* OMAP4 clk framework not supported yet */ + return 0; if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent)) return ret; @@ -240,13 +273,13 @@ void recalculate_root_clocks(void) } /** - * clk_init_one - initialize any fields in the struct clk before clk init + * clk_preinit - initialize any fields in the struct clk before clk init * @clk: struct clk * to initialize * * Initialize any struct clk fields needed before normal clk initialization * can run. No return value. */ -void clk_init_one(struct clk *clk) +void clk_preinit(struct clk *clk) { INIT_LIST_HEAD(&clk->children); } diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 433021f..ebcf0064 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -2,6 +2,10 @@ * linux/arch/arm/plat-omap/common.c * * Code common to all OMAP machines. + * The file is created by Tony Lindgren <tony@atomide.com> + * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -11,7 +15,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/delay.h> -#include <linux/pm.h> #include <linux/console.h> #include <linux/serial.h> #include <linux/tty.h> @@ -175,25 +178,70 @@ console_initcall(omap_add_serial_console); * but systems won't necessarily want to spend resources that way. */ -#if defined(CONFIG_ARCH_OMAP16XX) -#define TIMER_32K_SYNCHRONIZED 0xfffbc410 -#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) -#define TIMER_32K_SYNCHRONIZED (OMAP2_32KSYNCT_BASE + 0x10) -#endif +#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410 -#ifdef TIMER_32K_SYNCHRONIZED +#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) #include <linux/clocksource.h> -static cycle_t omap_32k_read(struct clocksource *cs) +#ifdef CONFIG_ARCH_OMAP16XX +static cycle_t omap16xx_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED); +} +#else +#define omap16xx_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP2420 +static cycle_t omap2420_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10); +} +#else +#define omap2420_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP2430 +static cycle_t omap2430_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10); +} +#else +#define omap2430_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP34XX +static cycle_t omap34xx_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10); +} +#else +#define omap34xx_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP4 +static cycle_t omap44xx_32k_read(struct clocksource *cs) { - return omap_readl(TIMER_32K_SYNCHRONIZED); + return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10); +} +#else +#define omap44xx_32k_read NULL +#endif + +/* + * Kernel assumes that sched_clock can be called early but may not have + * things ready yet. + */ +static cycle_t omap_32k_read_dummy(struct clocksource *cs) +{ + return 0; } static struct clocksource clocksource_32k = { .name = "32k_counter", .rating = 250, - .read = omap_32k_read, + .read = omap_32k_read_dummy, .mask = CLOCKSOURCE_MASK(32), .shift = 10, .flags = CLOCK_SOURCE_IS_CONTINUOUS, @@ -207,7 +255,7 @@ unsigned long long sched_clock(void) { unsigned long long ret; - ret = (unsigned long long)omap_32k_read(&clocksource_32k); + ret = (unsigned long long)clocksource_32k.read(&clocksource_32k); ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift; return ret; } @@ -220,6 +268,19 @@ static int __init omap_init_clocksource_32k(void) if (cpu_is_omap16xx() || cpu_class_is_omap2()) { struct clk *sync_32k_ick; + if (cpu_is_omap16xx()) + clocksource_32k.read = omap16xx_32k_read; + else if (cpu_is_omap2420()) + clocksource_32k.read = omap2420_32k_read; + else if (cpu_is_omap2430()) + clocksource_32k.read = omap2430_32k_read; + else if (cpu_is_omap34xx()) + clocksource_32k.read = omap34xx_32k_read; + else if (cpu_is_omap44xx()) + clocksource_32k.read = omap44xx_32k_read; + else + return -ENODEV; + sync_32k_ick = clk_get(NULL, "omap_32ksync_ick"); if (sync_32k_ick) clk_enable(sync_32k_ick); @@ -234,15 +295,13 @@ static int __init omap_init_clocksource_32k(void) } arch_initcall(omap_init_clocksource_32k); -#endif /* TIMER_32K_SYNCHRONIZED */ +#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */ /* Global address base setup code */ #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) -static struct omap_globals *omap2_globals; - -static void __init __omap2_set_globals(void) +static void __init __omap2_set_globals(struct omap_globals *omap2_globals) { omap2_set_globals_tap(omap2_globals); omap2_set_globals_sdrc(omap2_globals); @@ -266,8 +325,7 @@ static struct omap_globals omap242x_globals = { void __init omap2_set_globals_242x(void) { - omap2_globals = &omap242x_globals; - __omap2_set_globals(); + __omap2_set_globals(&omap242x_globals); } #endif @@ -285,8 +343,7 @@ static struct omap_globals omap243x_globals = { void __init omap2_set_globals_243x(void) { - omap2_globals = &omap243x_globals; - __omap2_set_globals(); + __omap2_set_globals(&omap243x_globals); } #endif @@ -304,8 +361,23 @@ static struct omap_globals omap343x_globals = { void __init omap2_set_globals_343x(void) { - omap2_globals = &omap343x_globals; - __omap2_set_globals(); + __omap2_set_globals(&omap343x_globals); +} +#endif + +#if defined(CONFIG_ARCH_OMAP4) +static struct omap_globals omap4_globals = { + .class = OMAP443X_CLASS, + .tap = OMAP2_IO_ADDRESS(0x4830a000), + .ctrl = OMAP2_IO_ADDRESS(OMAP443X_CTRL_BASE), + .prm = OMAP2_IO_ADDRESS(OMAP4430_PRM_BASE), + .cm = OMAP2_IO_ADDRESS(OMAP4430_CM_BASE), +}; + +void __init omap2_set_globals_443x(void) +{ + omap2_set_globals_tap(&omap4_globals); + omap2_set_globals_control(&omap4_globals); } #endif diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 87fb7ff..a64b692 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -311,6 +311,8 @@ static void omap_init_wdt(void) wdt_resources[0].start = 0x49016000; /* WDT2 */ else if (cpu_is_omap343x()) wdt_resources[0].start = 0x48314000; /* WDT2 */ + else if (cpu_is_omap44xx()) + wdt_resources[0].start = 0x4a314000; else return; diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 7fc8c04..def14ec 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -10,6 +10,9 @@ * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * * Support functions for the OMAP internal DMA channels. * * This program is free software; you can redistribute it and/or modify @@ -310,41 +313,62 @@ EXPORT_SYMBOL(omap_set_dma_transfer_params); void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) { - u16 w; - BUG_ON(omap_dma_in_1510_mode()); - if (cpu_class_is_omap2()) { - REVISIT_24XX(); - return; - } + if (cpu_class_is_omap1()) { + u16 w; - w = dma_read(CCR2(lch)); - w &= ~0x03; + w = dma_read(CCR2(lch)); + w &= ~0x03; - switch (mode) { - case OMAP_DMA_CONSTANT_FILL: - w |= 0x01; - break; - case OMAP_DMA_TRANSPARENT_COPY: - w |= 0x02; - break; - case OMAP_DMA_COLOR_DIS: - break; - default: - BUG(); + switch (mode) { + case OMAP_DMA_CONSTANT_FILL: + w |= 0x01; + break; + case OMAP_DMA_TRANSPARENT_COPY: + w |= 0x02; + break; + case OMAP_DMA_COLOR_DIS: + break; + default: + BUG(); + } + dma_write(w, CCR2(lch)); + + w = dma_read(LCH_CTRL(lch)); + w &= ~0x0f; + /* Default is channel type 2D */ + if (mode) { + dma_write((u16)color, COLOR_L(lch)); + dma_write((u16)(color >> 16), COLOR_U(lch)); + w |= 1; /* Channel type G */ + } + dma_write(w, LCH_CTRL(lch)); } - dma_write(w, CCR2(lch)); - w = dma_read(LCH_CTRL(lch)); - w &= ~0x0f; - /* Default is channel type 2D */ - if (mode) { - dma_write((u16)color, COLOR_L(lch)); - dma_write((u16)(color >> 16), COLOR_U(lch)); - w |= 1; /* Channel type G */ + if (cpu_class_is_omap2()) { + u32 val; + + val = dma_read(CCR(lch)); + val &= ~((1 << 17) | (1 << 16)); + + switch (mode) { + case OMAP_DMA_CONSTANT_FILL: + val |= 1 << 16; + break; + case OMAP_DMA_TRANSPARENT_COPY: + val |= 1 << 17; + break; + case OMAP_DMA_COLOR_DIS: + break; + default: + BUG(); + } + dma_write(val, CCR(lch)); + + color &= 0xffffff; + dma_write(color, COLOR(lch)); } - dma_write(w, LCH_CTRL(lch)); } EXPORT_SYMBOL(omap_set_dma_color_mode); @@ -851,7 +875,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio, } l = dma_read(CCR(lch)); l &= ~((1 << 6) | (1 << 26)); - if (cpu_is_omap2430() || cpu_is_omap34xx()) + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); else l |= ((read_prio & 0x1) << 6); @@ -1199,7 +1223,7 @@ static void create_dma_lch_chain(int lch_head, int lch_queue) * Failure: -EINVAL/-ENOMEM */ int omap_request_dma_chain(int dev_id, const char *dev_name, - void (*callback) (int chain_id, u16 ch_status, + void (*callback) (int lch, u16 ch_status, void *data), int *chain_id, int no_of_chans, int chain_mode, struct omap_dma_channel_params params) @@ -1823,7 +1847,8 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) #define omap1_dma_irq_handler NULL #endif -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) static int omap2_dma_handle_ch(int ch) { @@ -2318,6 +2343,9 @@ static int __init omap_init_dma(void) } else if (cpu_is_omap34xx()) { omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE); dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; + } else if (cpu_is_omap44xx()) { + omap_dma_base = IO_ADDRESS(OMAP44XX_DMA4_BASE); + dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; } else { pr_err("DMA init failed for unsupported omap\n"); return -ENODEV; @@ -2416,12 +2444,18 @@ static int __init omap_init_dma(void) } } - if (cpu_is_omap2430() || cpu_is_omap34xx()) + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, DMA_DEFAULT_FIFO_DEPTH, 0); - if (cpu_class_is_omap2()) - setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq); + if (cpu_class_is_omap2()) { + int irq; + if (cpu_is_omap44xx()) + irq = INT_44XX_SDMA_IRQ0; + else + irq = INT_24XX_SDMA_IRQ0; + setup_irq(irq, &omap24xx_dma_irq); + } /* FIXME: Update LCD DMA to work on 24xx */ if (cpu_class_is_omap1()) { diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 55bb996..7f50b61 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -7,6 +7,9 @@ * OMAP2 support by Juha Yrjola * API improvements and OMAP2 clock framework support by Timo Teras * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -150,7 +153,8 @@ struct omap_dm_timer { unsigned long phys_base; int irq; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) struct clk *iclk, *fclk; #endif void __iomem *io_base; @@ -169,6 +173,9 @@ struct omap_dm_timer { #define omap3_dm_timers NULL #define omap3_dm_source_names NULL #define omap3_dm_source_clocks NULL +#define omap4_dm_timers NULL +#define omap4_dm_source_names NULL +#define omap4_dm_source_clocks NULL static struct omap_dm_timer omap1_dm_timers[] = { { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, @@ -191,6 +198,9 @@ static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers); #define omap3_dm_timers NULL #define omap3_dm_source_names NULL #define omap3_dm_source_clocks NULL +#define omap4_dm_timers NULL +#define omap4_dm_source_names NULL +#define omap4_dm_source_clocks NULL static struct omap_dm_timer omap2_dm_timers[] = { { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, @@ -214,7 +224,7 @@ static const char *omap2_dm_source_names[] __initdata = { NULL }; -static struct clk **omap2_dm_source_clocks[3]; +static struct clk *omap2_dm_source_clocks[3]; static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers); #elif defined(CONFIG_ARCH_OMAP3) @@ -225,6 +235,9 @@ static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers); #define omap2_dm_timers NULL #define omap2_dm_source_names NULL #define omap2_dm_source_clocks NULL +#define omap4_dm_timers NULL +#define omap4_dm_source_names NULL +#define omap4_dm_source_clocks NULL static struct omap_dm_timer omap3_dm_timers[] = { { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 }, @@ -247,9 +260,43 @@ static const char *omap3_dm_source_names[] __initdata = { NULL }; -static struct clk **omap3_dm_source_clocks[2]; +static struct clk *omap3_dm_source_clocks[2]; static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers); +#elif defined(CONFIG_ARCH_OMAP4) + +#define omap_dm_clk_enable(x) clk_enable(x) +#define omap_dm_clk_disable(x) clk_disable(x) +#define omap1_dm_timers NULL +#define omap2_dm_timers NULL +#define omap2_dm_source_names NULL +#define omap2_dm_source_clocks NULL +#define omap3_dm_timers NULL +#define omap3_dm_source_names NULL +#define omap3_dm_source_clocks NULL + +static struct omap_dm_timer omap4_dm_timers[] = { + { .phys_base = 0x4a318000, .irq = INT_44XX_GPTIMER1 }, + { .phys_base = 0x48032000, .irq = INT_44XX_GPTIMER2 }, + { .phys_base = 0x48034000, .irq = INT_44XX_GPTIMER3 }, + { .phys_base = 0x48036000, .irq = INT_44XX_GPTIMER4 }, + { .phys_base = 0x40138000, .irq = INT_44XX_GPTIMER5 }, + { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER6 }, + { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER7 }, + { .phys_base = 0x4013e000, .irq = INT_44XX_GPTIMER8 }, + { .phys_base = 0x4803e000, .irq = INT_44XX_GPTIMER9 }, + { .phys_base = 0x48086000, .irq = INT_44XX_GPTIMER10 }, + { .phys_base = 0x48088000, .irq = INT_44XX_GPTIMER11 }, + { .phys_base = 0x4a320000, .irq = INT_44XX_GPTIMER12 }, +}; +static const char *omap4_dm_source_names[] __initdata = { + "sys_ck", + "omap_32k_fck", + NULL +}; +static struct clk *omap4_dm_source_clocks[2]; +static const int dm_timer_count = ARRAY_SIZE(omap4_dm_timers); + #else #error OMAP architecture not supported! @@ -257,7 +304,7 @@ static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers); #endif static struct omap_dm_timer *dm_timers; -static char **dm_source_names; +static const char **dm_source_names; static struct clk **dm_source_clocks; static spinlock_t dm_timer_lock; @@ -459,7 +506,8 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) } EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); -#elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3) +#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) { @@ -705,12 +753,16 @@ int __init omap_dm_timer_init(void) dm_timers = omap1_dm_timers; else if (cpu_is_omap24xx()) { dm_timers = omap2_dm_timers; - dm_source_names = (char **)omap2_dm_source_names; - dm_source_clocks = (struct clk **)omap2_dm_source_clocks; + dm_source_names = omap2_dm_source_names; + dm_source_clocks = omap2_dm_source_clocks; } else if (cpu_is_omap34xx()) { dm_timers = omap3_dm_timers; - dm_source_names = (char **)omap3_dm_source_names; - dm_source_clocks = (struct clk **)omap3_dm_source_clocks; + dm_source_names = omap3_dm_source_names; + dm_source_clocks = omap3_dm_source_clocks; + } else if (cpu_is_omap44xx()) { + dm_timers = omap4_dm_timers; + dm_source_names = omap4_dm_source_names; + dm_source_clocks = omap4_dm_source_clocks; } if (cpu_class_is_omap2()) @@ -723,7 +775,8 @@ int __init omap_dm_timer_init(void) for (i = 0; i < dm_timer_count; i++) { timer = &dm_timers[i]; timer->io_base = IO_ADDRESS(timer->phys_base); -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) if (cpu_class_is_omap2()) { char clk_name[16]; sprintf(clk_name, "gpt%d_ick", i + 1); diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index ee0b21f..7fd89ba 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -6,6 +6,9 @@ * Copyright (C) 2003-2005 Nokia Corporation * Written by Juha Yrjölä <juha.yrjola@nokia.com> * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -146,6 +149,16 @@ #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000) #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000) +/* + * OMAP44XX specific GPIO registers + */ +#define OMAP44XX_GPIO1_BASE IO_ADDRESS(0x4a310000) +#define OMAP44XX_GPIO2_BASE IO_ADDRESS(0x48055000) +#define OMAP44XX_GPIO3_BASE IO_ADDRESS(0x48057000) +#define OMAP44XX_GPIO4_BASE IO_ADDRESS(0x48059000) +#define OMAP44XX_GPIO5_BASE IO_ADDRESS(0x4805B000) +#define OMAP44XX_GPIO6_BASE IO_ADDRESS(0x4805D000) + #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE) struct gpio_bank { @@ -153,11 +166,13 @@ struct gpio_bank { u16 irq; u16 virtual_irq_start; int method; -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ + defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) u32 suspend_wakeup; u32 saved_wakeup; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) u32 non_wakeup_gpios; u32 enabled_non_wakeup_gpios; @@ -251,6 +266,24 @@ static struct gpio_bank gpio_bank_34xx[6] = { #endif +#ifdef CONFIG_ARCH_OMAP4 +static struct gpio_bank gpio_bank_44xx[6] = { + { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \ + METHOD_GPIO_24XX }, + { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \ + METHOD_GPIO_24XX }, + { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \ + METHOD_GPIO_24XX }, + { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \ + METHOD_GPIO_24XX }, + { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \ + METHOD_GPIO_24XX }, + { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \ + METHOD_GPIO_24XX }, +}; + +#endif + static struct gpio_bank *gpio_bank; static int gpio_bank_count; @@ -273,7 +306,7 @@ static inline struct gpio_bank *get_gpio_bank(int gpio) } if (cpu_is_omap24xx()) return &gpio_bank[gpio >> 5]; - if (cpu_is_omap34xx()) + if (cpu_is_omap34xx() || cpu_is_omap44xx()) return &gpio_bank[gpio >> 5]; BUG(); return NULL; @@ -285,7 +318,7 @@ static inline int get_gpio_index(int gpio) return gpio & 0x1f; if (cpu_is_omap24xx()) return gpio & 0x1f; - if (cpu_is_omap34xx()) + if (cpu_is_omap34xx() || cpu_is_omap44xx()) return gpio & 0x1f; return gpio & 0x0f; } @@ -307,7 +340,7 @@ static inline int gpio_valid(int gpio) return 0; if (cpu_is_omap24xx() && gpio < 128) return 0; - if (cpu_is_omap34xx() && gpio < 192) + if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) return 0; return -1; } @@ -353,7 +386,8 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) reg += OMAP850_GPIO_DIR_CONTROL; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) case METHOD_GPIO_24XX: reg += OMAP24XX_GPIO_OE; break; @@ -425,7 +459,8 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) l &= ~(1 << gpio); break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) case METHOD_GPIO_24XX: if (enable) reg += OMAP24XX_GPIO_SETDATAOUT; @@ -476,7 +511,8 @@ static int __omap_get_gpio_datain(int gpio) reg += OMAP850_GPIO_DATA_INPUT; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) case METHOD_GPIO_24XX: reg += OMAP24XX_GPIO_DATAIN; break; @@ -520,7 +556,7 @@ void omap_set_gpio_debounce(int gpio, int enable) else goto done; - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { if (enable) clk_enable(bank->dbck); else @@ -550,7 +586,8 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time) } EXPORT_SYMBOL(omap_set_gpio_debounce_time); -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) { @@ -660,7 +697,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) goto bad; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) case METHOD_GPIO_24XX: set_24xx_gpio_triggering(bank, gpio, trigger); break; @@ -745,7 +783,8 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) reg += OMAP850_GPIO_INT_STATUS; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) case METHOD_GPIO_24XX: reg += OMAP24XX_GPIO_IRQSTATUS1; break; @@ -814,7 +853,8 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) inv = 1; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) case METHOD_GPIO_24XX: reg += OMAP24XX_GPIO_IRQENABLE1; mask = 0xffffffff; @@ -887,7 +927,8 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab l |= gpio_mask; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) case METHOD_GPIO_24XX: if (enable) reg += OMAP24XX_GPIO_SETIRQENABLE1; @@ -932,7 +973,8 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) spin_unlock_irqrestore(&bank->lock, flags); return 0; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) case METHOD_GPIO_24XX: if (bank->non_wakeup_gpios & (1 << gpio)) { printk(KERN_ERR "Unable to modify wakeup on " @@ -1017,7 +1059,8 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) __raw_writel(1 << offset, reg); } #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) if (bank->method == METHOD_GPIO_24XX) { /* Disable wake-up during idle for dynamic tick */ void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; @@ -1069,7 +1112,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) if (bank->method == METHOD_GPIO_850) isr_reg = bank->base + OMAP850_GPIO_INT_STATUS; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) if (bank->method == METHOD_GPIO_24XX) isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; #endif @@ -1346,7 +1390,7 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset) /*---------------------------------------------------------------------*/ static int initialized; -#if !defined(CONFIG_ARCH_OMAP3) +#if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)) static struct clk * gpio_ick; #endif @@ -1359,7 +1403,7 @@ static struct clk * gpio5_ick; static struct clk * gpio5_fck; #endif -#if defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; #endif @@ -1419,8 +1463,8 @@ static int __init _omap_gpio_init(void) } #endif -#if defined(CONFIG_ARCH_OMAP3) - if (cpu_is_omap34xx()) { +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { sprintf(clk_name, "gpio%d_ick", i + 1); gpio_iclks[i] = clk_get(NULL, clk_name); @@ -1497,6 +1541,17 @@ static int __init _omap_gpio_init(void) (rev >> 4) & 0x0f, rev & 0x0f); } #endif +#ifdef CONFIG_ARCH_OMAP4 + if (cpu_is_omap44xx()) { + int rev; + + gpio_bank_count = OMAP34XX_NR_GPIOS; + gpio_bank = gpio_bank_44xx; + rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); + printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n", + (rev >> 4) & 0x0f, rev & 0x0f); + } +#endif for (i = 0; i < gpio_bank_count; i++) { int j, gpio_count = 16; @@ -1520,7 +1575,8 @@ static int __init _omap_gpio_init(void) gpio_count = 32; /* 730 has 32-bit GPIOs */ } -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) if (bank->method == METHOD_GPIO_24XX) { static const u32 non_wakeup_gpios[] = { 0xe203ffc0, 0x08700040 @@ -1577,7 +1633,7 @@ static int __init _omap_gpio_init(void) set_irq_chained_handler(bank->irq, gpio_irq_handler); set_irq_data(bank->irq, bank); - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() || cpu_is_omap44xx()) { sprintf(clk_name, "gpio%d_dbck", i + 1); bank->dbck = clk_get(NULL, clk_name); if (IS_ERR(bank->dbck)) @@ -1599,7 +1655,8 @@ static int __init _omap_gpio_init(void) return 0; } -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ + defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) { int i; @@ -1622,7 +1679,8 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) case METHOD_GPIO_24XX: wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; @@ -1663,7 +1721,8 @@ static int omap_gpio_resume(struct sys_device *dev) wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; break; #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) case METHOD_GPIO_24XX: wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; @@ -1695,7 +1754,8 @@ static struct sys_device omap_gpio_device = { #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) static int workaround_enabled; @@ -1711,7 +1771,8 @@ void omap2_gpio_prepare_for_retention(void) if (!(bank->enabled_non_wakeup_gpios)) continue; -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); @@ -1720,7 +1781,8 @@ void omap2_gpio_prepare_for_retention(void) bank->saved_risingdetect = l2; l1 &= ~bank->enabled_non_wakeup_gpios; l2 &= ~bank->enabled_non_wakeup_gpios; -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); #endif @@ -1745,7 +1807,8 @@ void omap2_gpio_resume_after_retention(void) if (!(bank->enabled_non_wakeup_gpios)) continue; -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) __raw_writel(bank->saved_fallingdetect, bank->base + OMAP24XX_GPIO_FALLINGDETECT); __raw_writel(bank->saved_risingdetect, @@ -1755,14 +1818,16 @@ void omap2_gpio_resume_after_retention(void) * state. If so, generate an IRQ by software. This is * horribly racy, but it's the best we can do to work around * this silicon bug. */ -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); #endif l ^= bank->saved_datain; l &= bank->non_wakeup_gpios; if (l) { u32 old0, old1; -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); @@ -1798,7 +1863,8 @@ static int __init omap_gpio_sysinit(void) mpuio_init(); -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ + defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) if (cpu_is_omap16xx() || cpu_class_is_omap2()) { if (ret == 0) { ret = sysdev_class_register(&omap_gpio_sysclass); @@ -1887,7 +1953,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) irqstat = irq_desc[irq].status; #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ - defined(CONFIG_ARCH_OMAP34XX) + defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) if (is_in && ((bank->suspend_wakeup & mask) || irqstat & IRQ_TYPE_SENSE_MASK)) { char *trigger = NULL; diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index a303071..8b84839 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c @@ -5,7 +5,7 @@ * * Copyright (C) 2007 Nokia Corporation. * - * Contact: Jarkko Nikula <jarkko.nikula@nokia.com> + * Contact: Jarkko Nikula <jhnikula@gmail.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index 073a2c5..f9f65e1 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h @@ -22,7 +22,8 @@ struct clkops { void (*disable)(struct clk *); }; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) struct clksel_rate { u32 val; @@ -51,7 +52,7 @@ struct dpll_data { u8 max_divider; u32 max_tolerance; u16 max_multiplier; -# if defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) u8 modes; void __iomem *autoidle_reg; void __iomem *idlest_reg; @@ -83,7 +84,8 @@ struct clk { void (*init)(struct clk *); __u8 enable_bit; __s8 usecount; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) u8 fixed_div; void __iomem *clksel_reg; u32 clksel_mask; @@ -119,7 +121,7 @@ struct clk_functions { extern unsigned int mpurate; extern int clk_init(struct clk_functions *custom_clocks); -extern void clk_init_one(struct clk *clk); +extern void clk_preinit(struct clk *clk); extern int clk_register(struct clk *clk); extern void clk_reparent(struct clk *child, struct clk *parent); extern void clk_unregister(struct clk *clk); diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h index 0ecf36d..fdeab42 100644 --- a/arch/arm/plat-omap/include/mach/common.h +++ b/arch/arm/plat-omap/include/mach/common.h @@ -33,8 +33,6 @@ struct sys_timer; extern void omap_map_common_io(void); extern struct sys_timer omap_timer; -extern void omap_serial_init(void); -extern void omap_serial_enable_clocks(int enable); #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) extern int omap_register_i2c_bus(int bus_id, u32 clkrate, struct i2c_board_info const *info, @@ -62,6 +60,7 @@ struct omap_globals { void omap2_set_globals_242x(void); void omap2_set_globals_243x(void); void omap2_set_globals_343x(void); +void omap2_set_globals_443x(void); /* These get called from omap2_set_globals_xxxx(), do not call these */ void omap2_set_globals_tap(struct omap_globals *); diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h index 269147f..8140dbc 100644 --- a/arch/arm/plat-omap/include/mach/control.h +++ b/arch/arm/plat-omap/include/mach/control.h @@ -1,9 +1,9 @@ /* * arch/arm/plat-omap/include/mach/control.h * - * OMAP2/3 System Control Module definitions + * OMAP2/3/4 System Control Module definitions * - * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2009 Texas Instruments, Inc. * Copyright (C) 2007-2008 Nokia Corporation * * Written by Paul Walmsley @@ -144,6 +144,10 @@ #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0) #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) +/* 34xx D2D idle-related pins, handled by PM core */ +#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 +#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 + /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. @@ -189,8 +193,18 @@ #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) #define OMAP2_PBIASLITEVMODE0 (1 << 0) +/* CONTROL_IVA2_BOOTMOD bits */ +#define OMAP3_IVA2_BOOTMOD_SHIFT 0 +#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) +#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) + +/* CONTROL_PADCONF_X bits */ +#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) +#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) + #ifndef __ASSEMBLY__ -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) extern void __iomem *omap_ctrl_base_get(void); extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h index 98b1442..fc60c4e 100644 --- a/arch/arm/plat-omap/include/mach/cpu.h +++ b/arch/arm/plat-omap/include/mach/cpu.h @@ -5,8 +5,12 @@ * * Copyright (C) 2004, 2008 Nokia Corporation * + * Copyright (C) 2009 Texas Instruments. + * * Written by Tony Lindgren <tony.lindgren@nokia.com> * + * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -155,6 +159,8 @@ IS_OMAP_SUBCLASS(343x, 0x343) #define cpu_is_omap243x() 0 #define cpu_is_omap34xx() 0 #define cpu_is_omap343x() 0 +#define cpu_is_omap44xx() 0 +#define cpu_is_omap443x() 0 #if defined(MULTI_OMAP1) # if defined(CONFIG_ARCH_OMAP730) @@ -348,12 +354,21 @@ IS_OMAP_TYPE(3430, 0x3430) # define cpu_is_omap3430() is_omap3430() #endif +# if defined(CONFIG_ARCH_OMAP4) +# undef cpu_is_omap44xx +# undef cpu_is_omap443x +# define cpu_is_omap44xx() 1 +# define cpu_is_omap443x() 1 +# endif + /* Macros to detect if we have OMAP1 or OMAP2 */ #define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ cpu_is_omap16xx()) -#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx()) +#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \ + cpu_is_omap44xx()) -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) /* Various silicon revisions for omap2 */ #define OMAP242X_CLASS 0x24200024 @@ -370,6 +385,8 @@ IS_OMAP_TYPE(3430, 0x3430) #define OMAP3430_REV_ES3_0 0x34303034 #define OMAP3430_REV_ES3_1 0x34304034 +#define OMAP443X_CLASS 0x44300034 + /* * omap_chip bits * diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S index 1b11f5c..ac24050 100644 --- a/arch/arm/plat-omap/include/mach/debug-macro.S +++ b/arch/arm/plat-omap/include/mach/debug-macro.S @@ -36,7 +36,7 @@ add \rx, \rx, #0x00004000 @ UART 3 #endif -#elif CONFIG_ARCH_OMAP3 +#elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) moveq \rx, #0x48000000 @ physical base address movne \rx, #0xd8000000 @ virtual base orr \rx, \rx, #0x0006a000 diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h index 54fe966..8c1eae8 100644 --- a/arch/arm/plat-omap/include/mach/dma.h +++ b/arch/arm/plat-omap/include/mach/dma.h @@ -48,6 +48,7 @@ /* Hardware registers for omap2 and omap3 */ #define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000) #define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000) +#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000) #define OMAP_DMA4_REVISION 0x00 #define OMAP_DMA4_GCR 0x78 @@ -144,6 +145,7 @@ #define OMAP_DMA4_CSSA_U(n) 0 #define OMAP_DMA4_CDSA_L(n) 0 #define OMAP_DMA4_CDSA_U(n) 0 +#define OMAP1_DMA_COLOR(n) 0 /*----------------------------------------------------------------------------*/ @@ -531,7 +533,7 @@ extern int omap_get_dma_index(int lch, int *ei, int *fi); /* Chaining APIs */ #ifndef CONFIG_ARCH_OMAP1 extern int omap_request_dma_chain(int dev_id, const char *dev_name, - void (*callback) (int chain_id, u16 ch_status, + void (*callback) (int lch, u16 ch_status, void *data), int *chain_id, int no_of_chans, int chain_mode, diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S index 2276f89..56426ed 100644 --- a/arch/arm/plat-omap/include/mach/entry-macro.S +++ b/arch/arm/plat-omap/include/mach/entry-macro.S @@ -3,6 +3,9 @@ * * Low-level IRQ helper macros for OMAP-based platforms * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. @@ -10,6 +13,7 @@ #include <mach/hardware.h> #include <mach/io.h> #include <mach/irqs.h> +#include <asm/hardware/gic.h> #if defined(CONFIG_ARCH_OMAP1) @@ -56,15 +60,21 @@ .endm #endif -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ + defined(CONFIG_ARCH_OMAP4) -#if defined(CONFIG_ARCH_OMAP24XX) #include <mach/omap24xx.h> -#endif -#if defined(CONFIG_ARCH_OMAP34XX) #include <mach/omap34xx.h> -#endif +/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */ +#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) +#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) +#elif defined(CONFIG_ARCH_OMAP34XX) +#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE) +#endif +#if defined(CONFIG_ARCH_OMAP4) +#include <mach/omap44xx.h> +#endif #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ #define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ @@ -77,6 +87,7 @@ .macro arch_ret_to_user, tmp1, tmp2 .endm +#ifndef CONFIG_ARCH_OMAP4 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \base, =OMAP2_VA_IC_BASE ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ @@ -92,6 +103,68 @@ and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ .endm +#else + /* + * The interrupt numbering scheme is defined in the + * interrupt controller spec. To wit: + * + * Interrupts 0-15 are IPI + * 16-28 are reserved + * 29-31 are local. We allow 30 to be used for the watchdog. + * 32-1020 are global + * 1021-1022 are reserved + * 1023 is "spurious" (no interrupt) + * + * For now, we ignore all local interrupts so only return an + * interrupt if it's between 30 and 1020. The test_for_ipi + * routine below will pick up on IPIs. + * A simple read from the controller will tell us the number + * of the highest priority enabled interrupt. + * We then just need to check whether it is in the + * valid range for an IRQ (30-1020 inclusive). + */ + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =OMAP44XX_VA_GIC_CPU_BASE + ldr \irqstat, [\base, #GIC_CPU_INTACK] + + ldr \tmp, =1021 + + bic \irqnr, \irqstat, #0x1c00 + + cmp \irqnr, #29 + cmpcc \irqnr, \irqnr + cmpne \irqnr, \tmp + cmpcs \irqnr, \irqnr + .endm + + /* We assume that irqstat (the raw value of the IRQ acknowledge + * register) is preserved from the macro above. + * If there is an IPI, we immediately signal end of interrupt + * on the controller, since this requires the original irqstat + * value which we won't easily be able to recreate later. + */ + + .macro test_for_ipi, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #16 + it cc + strcc \irqstat, [\base, #GIC_CPU_EOI] + it cs + cmpcs \irqnr, \irqnr + .endm + + /* As above, this assumes that irqstat and base are preserved */ + + .macro test_for_ltirq, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + mov \tmp, #0 + cmp \irqnr, #29 + itt eq + moveq \tmp, #1 + streq \irqstat, [\base, #GIC_CPU_EOI] + cmp \tmp, #0 + .endm +#endif .macro irq_prio_table .endm diff --git a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h b/arch/arm/plat-omap/include/mach/gpmc-smc91x.h new file mode 100644 index 0000000..b64fbee --- /dev/null +++ b/arch/arm/plat-omap/include/mach/gpmc-smc91x.h @@ -0,0 +1,42 @@ +/* + * arch/arm/plat-omap/include/mach/gpmc-smc91x.h + * + * Copyright (C) 2009 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__ + +#define GPMC_TIMINGS_SMC91C96 (1 << 4) +#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */ +#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */ +#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */ + +struct omap_smc91x_platform_data { + int cs; + int gpio_irq; + int gpio_pwrdwn; + int gpio_reset; + int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */ + u32 flags; + int (*retime)(void); +}; + +#if defined(CONFIG_SMC91X) || \ + defined(CONFIG_SMC91X_MODULE) + +extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d); + +#else + +#define board_smc91x_data NULL + +static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d) +{ +} + +#endif +#endif diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h index 3dc423e..26c1fbf 100644 --- a/arch/arm/plat-omap/include/mach/hardware.h +++ b/arch/arm/plat-omap/include/mach/hardware.h @@ -285,5 +285,6 @@ #include "omap16xx.h" #include "omap24xx.h" #include "omap34xx.h" +#include "omap44xx.h" #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/arch/arm/plat-omap/include/mach/hwa742.h b/arch/arm/plat-omap/include/mach/hwa742.h index 577f492..886248d 100644 --- a/arch/arm/plat-omap/include/mach/hwa742.h +++ b/arch/arm/plat-omap/include/mach/hwa742.h @@ -2,10 +2,6 @@ #define _HWA742_H struct hwa742_platform_data { - void (*power_up)(struct device *dev); - void (*power_down)(struct device *dev); - unsigned long (*get_clock_rate)(struct device *dev); - unsigned te_connected:1; }; diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h index 0610d7e..3b28147 100644 --- a/arch/arm/plat-omap/include/mach/io.h +++ b/arch/arm/plat-omap/include/mach/io.h @@ -6,6 +6,9 @@ * Copied from arch/arm/mach-sa1100/include/mach/io.h * Copyright (C) 1997-1999 Russell King * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -157,6 +160,40 @@ #define DSP_MMU_34XX_VIRT 0xe2000000 #define DSP_MMU_34XX_SIZE SZ_4K + +#elif defined(CONFIG_ARCH_OMAP4) +/* We map both L3 and L4 on OMAP4 */ +#define L3_44XX_PHYS L3_44XX_BASE +#define L3_44XX_VIRT 0xd4000000 +#define L3_44XX_SIZE SZ_1M + +#define L4_44XX_PHYS L4_44XX_BASE +#define L4_44XX_VIRT 0xda000000 +#define L4_44XX_SIZE SZ_4M + + +#define L4_WK_44XX_PHYS L4_WK_44XX_BASE +#define L4_WK_44XX_VIRT 0xda300000 +#define L4_WK_44XX_SIZE SZ_1M + +#define L4_PER_44XX_PHYS L4_PER_44XX_BASE +#define L4_PER_44XX_VIRT 0xd8000000 +#define L4_PER_44XX_SIZE SZ_4M + +#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE +#define L4_EMU_44XX_VIRT 0xe4000000 +#define L4_EMU_44XX_SIZE SZ_64M + +#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE +#define OMAP44XX_GPMC_VIRT 0xe0000000 +#define OMAP44XX_GPMC_SIZE SZ_1M + + +#define IO_OFFSET 0x90000000 +#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ +#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ +#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ + #endif #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/mach/iommu.h new file mode 100644 index 0000000..769b00b --- /dev/null +++ b/arch/arm/plat-omap/include/mach/iommu.h @@ -0,0 +1,168 @@ +/* + * omap iommu: main structures + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_IOMMU_H +#define __MACH_IOMMU_H + +struct iotlb_entry { + u32 da; + u32 pa; + u32 pgsz, prsvd, valid; + union { + u16 ap; + struct { + u32 endian, elsz, mixed; + }; + }; +}; + +struct iommu { + const char *name; + struct module *owner; + struct clk *clk; + void __iomem *regbase; + struct device *dev; + + unsigned int refcount; + struct mutex iommu_lock; /* global for this whole object */ + + /* + * We don't change iopgd for a situation like pgd for a task, + * but share it globally for each iommu. + */ + u32 *iopgd; + spinlock_t page_table_lock; /* protect iopgd */ + + int nr_tlb_entries; + + struct list_head mmap; + struct mutex mmap_lock; /* protect mmap */ + + int (*isr)(struct iommu *obj); + + void *ctx; /* iommu context: registres saved area */ +}; + +struct cr_regs { + union { + struct { + u16 cam_l; + u16 cam_h; + }; + u32 cam; + }; + union { + struct { + u16 ram_l; + u16 ram_h; + }; + u32 ram; + }; +}; + +struct iotlb_lock { + short base; + short vict; +}; + +/* architecture specific functions */ +struct iommu_functions { + unsigned long version; + + int (*enable)(struct iommu *obj); + void (*disable)(struct iommu *obj); + u32 (*fault_isr)(struct iommu *obj, u32 *ra); + + void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr); + void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr); + + struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e); + int (*cr_valid)(struct cr_regs *cr); + u32 (*cr_to_virt)(struct cr_regs *cr); + void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e); + ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf); + + u32 (*get_pte_attr)(struct iotlb_entry *e); + + void (*save_ctx)(struct iommu *obj); + void (*restore_ctx)(struct iommu *obj); + ssize_t (*dump_ctx)(struct iommu *obj, char *buf); +}; + +struct iommu_platform_data { + const char *name; + const char *clk_name; + const int nr_tlb_entries; +}; + +#if defined(CONFIG_ARCH_OMAP1) +#error "iommu for this processor not implemented yet" +#else +#include <mach/iommu2.h> +#endif + +/* + * utilities for super page(16MB, 1MB, 64KB and 4KB) + */ + +#define iopgsz_max(bytes) \ + (((bytes) >= SZ_16M) ? SZ_16M : \ + ((bytes) >= SZ_1M) ? SZ_1M : \ + ((bytes) >= SZ_64K) ? SZ_64K : \ + ((bytes) >= SZ_4K) ? SZ_4K : 0) + +#define bytes_to_iopgsz(bytes) \ + (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \ + ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \ + ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \ + ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1) + +#define iopgsz_to_bytes(iopgsz) \ + (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \ + ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \ + ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \ + ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0) + +#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0) + +/* + * global functions + */ +extern u32 iommu_arch_version(void); + +extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e); +extern u32 iotlb_cr_to_virt(struct cr_regs *cr); + +extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e); +extern void flush_iotlb_page(struct iommu *obj, u32 da); +extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); +extern void flush_iotlb_all(struct iommu *obj); + +extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); +extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); + +extern struct iommu *iommu_get(const char *name); +extern void iommu_put(struct iommu *obj); + +extern void iommu_save_ctx(struct iommu *obj); +extern void iommu_restore_ctx(struct iommu *obj); + +extern int install_iommu_arch(const struct iommu_functions *ops); +extern void uninstall_iommu_arch(const struct iommu_functions *ops); + +extern int foreach_iommu_device(void *data, + int (*fn)(struct device *, void *)); + +extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf); +extern size_t dump_tlb_entries(struct iommu *obj, char *buf); + +#endif /* __MACH_IOMMU_H */ diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/mach/iommu2.h new file mode 100644 index 0000000..10ad05f --- /dev/null +++ b/arch/arm/plat-omap/include/mach/iommu2.h @@ -0,0 +1,96 @@ +/* + * omap iommu: omap2 architecture specific definitions + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_IOMMU2_H +#define __MACH_IOMMU2_H + +#include <linux/io.h> + +/* + * MMU Register offsets + */ +#define MMU_REVISION 0x00 +#define MMU_SYSCONFIG 0x10 +#define MMU_SYSSTATUS 0x14 +#define MMU_IRQSTATUS 0x18 +#define MMU_IRQENABLE 0x1c +#define MMU_WALKING_ST 0x40 +#define MMU_CNTL 0x44 +#define MMU_FAULT_AD 0x48 +#define MMU_TTB 0x4c +#define MMU_LOCK 0x50 +#define MMU_LD_TLB 0x54 +#define MMU_CAM 0x58 +#define MMU_RAM 0x5c +#define MMU_GFLUSH 0x60 +#define MMU_FLUSH_ENTRY 0x64 +#define MMU_READ_CAM 0x68 +#define MMU_READ_RAM 0x6c +#define MMU_EMU_FAULT_AD 0x70 + +#define MMU_REG_SIZE 256 + +/* + * MMU Register bit definitions + */ +#define MMU_LOCK_BASE_SHIFT 10 +#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) +#define MMU_LOCK_BASE(x) \ + ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) + +#define MMU_LOCK_VICT_SHIFT 4 +#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) +#define MMU_LOCK_VICT(x) \ + ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) + +#define MMU_CAM_VATAG_SHIFT 12 +#define MMU_CAM_VATAG_MASK \ + ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT) +#define MMU_CAM_P (1 << 3) +#define MMU_CAM_V (1 << 2) +#define MMU_CAM_PGSZ_MASK 3 +#define MMU_CAM_PGSZ_1M (0 << 0) +#define MMU_CAM_PGSZ_64K (1 << 0) +#define MMU_CAM_PGSZ_4K (2 << 0) +#define MMU_CAM_PGSZ_16M (3 << 0) + +#define MMU_RAM_PADDR_SHIFT 12 +#define MMU_RAM_PADDR_MASK \ + ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT) +#define MMU_RAM_ENDIAN_SHIFT 9 +#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT) +#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT) +#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT) +#define MMU_RAM_ELSZ_SHIFT 7 +#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_MIXED_SHIFT 6 +#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT) +#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK + +/* + * register accessors + */ +static inline u32 iommu_read_reg(struct iommu *obj, size_t offs) +{ + return __raw_readl(obj->regbase + offs); +} + +static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs) +{ + __raw_writel(val, obj->regbase + offs); +} + +#endif /* __MACH_IOMMU2_H */ diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/mach/iovmm.h new file mode 100644 index 0000000..bdc7ce5 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/iovmm.h @@ -0,0 +1,94 @@ +/* + * omap iommu: simple virtual address space management + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IOMMU_MMAP_H +#define __IOMMU_MMAP_H + +struct iovm_struct { + struct iommu *iommu; /* iommu object which this belongs to */ + u32 da_start; /* area definition */ + u32 da_end; + u32 flags; /* IOVMF_: see below */ + struct list_head list; /* linked in ascending order */ + const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */ + void *va; /* mpu side mapped address */ +}; + +/* + * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma) + * + * lower 16 bit is used for h/w and upper 16 bit is for s/w. + */ +#define IOVMF_SW_SHIFT 16 +#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT) +#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1) +#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL + +/* + * iovma: h/w flags derived from cam and ram attribute + */ +#define IOVMF_CAM_MASK (~((1 << 10) - 1)) +#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK) + +#define IOVMF_PGSZ_MASK (3 << 0) +#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M +#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K +#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K +#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M + +#define IOVMF_ENDIAN_MASK (1 << 9) +#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG +#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE + +#define IOVMF_ELSZ_MASK (3 << 7) +#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8 +#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16 +#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32 +#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE + +#define IOVMF_MIXED_MASK (1 << 6) +#define IOVMF_MIXED MMU_RAM_MIXED + +/* + * iovma: s/w flags, used for mapping and umapping internally. + */ +#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT) +#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT) +#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT) + +/* "superpages" is supported just with physically linear pages */ +#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT)) +#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT)) +#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT)) + +#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT)) +#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT)) +#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT)) + + +extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da); +extern u32 iommu_vmap(struct iommu *obj, u32 da, + const struct sg_table *sgt, u32 flags); +extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da); +extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, + u32 flags); +extern void iommu_vfree(struct iommu *obj, const u32 da); +extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes, + u32 flags); +extern void iommu_kunmap(struct iommu *obj, u32 da); +extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, + u32 flags); +extern void iommu_kfree(struct iommu *obj, u32 da); + +extern void *da_to_va(struct iommu *obj, u32 da); + +#endif /* __IOMMU_MMAP_H */ diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h index 7f57ee6..fb7cb77 100644 --- a/arch/arm/plat-omap/include/mach/irqs.h +++ b/arch/arm/plat-omap/include/mach/irqs.h @@ -4,6 +4,9 @@ * Copyright (C) Greg Lonnon 2001 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -422,6 +425,94 @@ #define INT_34XX_BENCH_MPU_EMUL 3 + +#define IRQ_GIC_START 32 +#define INT_44XX_LOCALTIMER_IRQ 29 +#define INT_44XX_LOCALWDT_IRQ 30 + +#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START) +#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START) +#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START) +#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START) +#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START) +#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START) +#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START) +#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START) +#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START) +#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START) +#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START) +#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START) +#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START) +#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START) +#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START) +#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START) +#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START) +#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START) +#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START) +#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START) +#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START) +#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START) +#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START) +#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START) +#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START) +#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START) +#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START) +#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START) +#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START) +#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START) +#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START) +#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START) +#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START) +#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START) +#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START) +#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START) +#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START) +#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START) +#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START) +#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START) +#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START) +#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START) +#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START) +#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START) + +#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START) +#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START) +#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START) +#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START) +#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START) +#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START) +#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START) + +#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START) +#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START) +#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START) +#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START) +#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START) +#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START) +#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START) +#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START) +#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START) +#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START) +#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START) +#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START) +#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START) +#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START) +#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START) +#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START) +#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START) + + /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and * 16 MPUIO lines */ #define OMAP_MAX_GPIO_LINES 192 @@ -467,6 +558,7 @@ #ifndef __ASSEMBLY__ extern void omap_init_irq(void); +extern int omap_irq_pending(void); #endif #include <mach/hardware.h> diff --git a/arch/arm/plat-omap/include/mach/keypad.h b/arch/arm/plat-omap/include/mach/keypad.h index 232923a..45ea3ae 100644 --- a/arch/arm/plat-omap/include/mach/keypad.h +++ b/arch/arm/plat-omap/include/mach/keypad.h @@ -33,7 +33,11 @@ struct omap_kp_platform_data { #define GROUP_3 (3 << 16) #define GROUP_MASK GROUP_3 +#define KEY_PERSISTENT 0x00800000 +#define KEYNUM_MASK 0x00EFFFFF #define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val)) +#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \ + KEY_PERSISTENT) #endif diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h index 99ed564..9ad41dc 100644 --- a/arch/arm/plat-omap/include/mach/memory.h +++ b/arch/arm/plat-omap/include/mach/memory.h @@ -38,7 +38,8 @@ */ #if defined(CONFIG_ARCH_OMAP1) #define PHYS_OFFSET UL(0x10000000) -#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ + defined(CONFIG_ARCH_OMAP4) #define PHYS_OFFSET UL(0x80000000) #endif diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/mach/omap24xx.h index 24335d4..696edfc 100644 --- a/arch/arm/plat-omap/include/mach/omap24xx.h +++ b/arch/arm/plat-omap/include/mach/omap24xx.h @@ -85,23 +85,5 @@ #define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) #define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) -#if defined(CONFIG_ARCH_OMAP2420) - -#define OMAP2_32KSYNCT_BASE OMAP2420_32KSYNCT_BASE -#define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE -#define OMAP2_CM_BASE OMAP2420_CM_BASE -#define OMAP2_PRM_BASE OMAP2420_PRM_BASE -#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) - -#elif defined(CONFIG_ARCH_OMAP2430) - -#define OMAP2_32KSYNCT_BASE OMAP2430_32KSYNCT_BASE -#define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE -#define OMAP2_CM_BASE OMAP2430_CM_BASE -#define OMAP2_PRM_BASE OMAP2430_PRM_BASE -#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) - -#endif - #endif /* __ASM_ARCH_OMAP24XX_H */ diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/mach/omap34xx.h index ab64015..f8d186a 100644 --- a/arch/arm/plat-omap/include/mach/omap34xx.h +++ b/arch/arm/plat-omap/include/mach/omap34xx.h @@ -31,13 +31,9 @@ #define L4_34XX_BASE 0x48000000 #define L4_WK_34XX_BASE 0x48300000 -#define L4_WK_OMAP_BASE L4_WK_34XX_BASE #define L4_PER_34XX_BASE 0x49000000 -#define L4_PER_OMAP_BASE L4_PER_34XX_BASE #define L4_EMU_34XX_BASE 0x54000000 -#define L4_EMU_BASE L4_EMU_34XX_BASE #define L3_34XX_BASE 0x68000000 -#define L3_OMAP_BASE L3_34XX_BASE #define OMAP3430_32KSYNCT_BASE 0x48320000 #define OMAP3430_CM_BASE 0x48004800 @@ -83,15 +79,6 @@ #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) -#if defined(CONFIG_ARCH_OMAP3430) - -#define OMAP2_32KSYNCT_BASE OMAP3430_32KSYNCT_BASE -#define OMAP2_CM_BASE OMAP3430_CM_BASE -#define OMAP2_PRM_BASE OMAP3430_PRM_BASE -#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE) - -#endif - #define OMAP34XX_DSP_BASE 0x58000000 #define OMAP34XX_DSP_MEM_BASE (OMAP34XX_DSP_BASE + 0x0) #define OMAP34XX_DSP_IPI_BASE (OMAP34XX_DSP_BASE + 0x1000000) diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/mach/omap44xx.h new file mode 100644 index 0000000..15dec7f --- /dev/null +++ b/arch/arm/plat-omap/include/mach/omap44xx.h @@ -0,0 +1,46 @@ +/*: + * Address mappings and base address for OMAP4 interconnects + * and peripherals. + * + * Copyright (C) 2009 Texas Instruments + * + * Author: Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARCH_OMAP44XX_H +#define __ASM_ARCH_OMAP44XX_H + +/* + * Please place only base defines here and put the rest in device + * specific headers. + */ +#define L4_44XX_BASE 0x4a000000 +#define L4_WK_44XX_BASE 0x4a300000 +#define L4_PER_44XX_BASE 0x48000000 +#define L4_EMU_44XX_BASE 0x54000000 +#define L3_44XX_BASE 0x44000000 +#define OMAP4430_32KSYNCT_BASE 0x4a304000 +#define OMAP4430_CM_BASE 0x4a004000 +#define OMAP4430_PRM_BASE 0x48306000 +#define OMAP44XX_GPMC_BASE 0x50000000 +#define OMAP443X_SCM_BASE 0x4a002000 +#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE +#define OMAP44XX_IC_BASE 0x48200000 +#define OMAP44XX_IVA_INTC_BASE 0x40000000 +#define IRQ_SIR_IRQ 0x0040 +#define OMAP44XX_GIC_DIST_BASE 0x48241000 +#define OMAP44XX_GIC_CPU_BASE 0x48240100 +#define OMAP44XX_VA_GIC_CPU_BASE IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) +#define OMAP44XX_SCU_BASE 0x48240000 +#define OMAP44XX_VA_SCU_BASE IO_ADDRESS(OMAP44XX_SCU_BASE) +#define OMAP44XX_LOCAL_TWD_BASE 0x48240600 +#define OMAP44XX_VA_LOCAL_TWD_BASE IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE) +#define OMAP44XX_LOCAL_TWD_SIZE 0x00000100 +#define OMAP44XX_WKUPGEN_BASE 0x48281000 +#define OMAP44XX_VA_WKUPGEN_BASE IO_ADDRESS(OMAP44XX_WKUPGEN_BASE) + +#endif /* __ASM_ARCH_OMAP44XX_H */ + diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/mach/onenand.h index 4649d30..72f433d 100644 --- a/arch/arm/plat-omap/include/mach/onenand.h +++ b/arch/arm/plat-omap/include/mach/onenand.h @@ -9,8 +9,12 @@ * published by the Free Software Foundation. */ +#include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#define ONENAND_SYNC_READ (1 << 0) +#define ONENAND_SYNC_READWRITE (1 << 1) + struct omap_onenand_platform_data { int cs; int gpio_irq; @@ -18,8 +22,22 @@ struct omap_onenand_platform_data { int nr_parts; int (*onenand_setup)(void __iomem *, int freq); int dma_channel; + u8 flags; }; -int omap2_onenand_rephase(void); - #define ONENAND_MAX_PARTITIONS 8 + +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) + +extern void gpmc_onenand_init(struct omap_onenand_platform_data *d); + +#else + +#define board_onenand_data NULL + +static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d) +{ +} + +#endif diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h deleted file mode 100644 index ce6ee79..0000000 --- a/arch/arm/plat-omap/include/mach/pm.h +++ /dev/null @@ -1,345 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/pm.h - * - * Header file for OMAP Power Management Routines - * - * Author: MontaVista Software, Inc. - * support@mvista.com - * - * Copyright 2002 MontaVista Software Inc. - * - * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP_PM_H -#define __ASM_ARCH_OMAP_PM_H - -/* - * ---------------------------------------------------------------------------- - * Register and offset definitions to be used in PM assembler code - * ---------------------------------------------------------------------------- - */ -#define CLKGEN_REG_ASM_BASE IO_ADDRESS(0xfffece00) -#define ARM_IDLECT1_ASM_OFFSET 0x04 -#define ARM_IDLECT2_ASM_OFFSET 0x08 - -#define TCMIF_ASM_BASE IO_ADDRESS(0xfffecc00) -#define EMIFS_CONFIG_ASM_OFFSET 0x0c -#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20 - -/* - * ---------------------------------------------------------------------------- - * Power management bitmasks - * ---------------------------------------------------------------------------- - */ -#define IDLE_WAIT_CYCLES 0x00000fff -#define PERIPHERAL_ENABLE 0x2 - -#define SELF_REFRESH_MODE 0x0c000001 -#define IDLE_EMIFS_REQUEST 0xc -#define MODEM_32K_EN 0x1 -#define PER_EN 0x1 - -#define CPU_SUSPEND_SIZE 200 -#define ULPD_LOW_PWR_EN 0x0001 -#define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010 -#define ULPD_SETUP_ANALOG_CELL_3_VAL 0 -#define ULPD_POWER_CTRL_REG_VAL 0x0219 - -#define DSP_IDLE_DELAY 10 -#define DSP_IDLE 0x0040 -#define DSP_RST 0x0004 -#define DSP_ENABLE 0x0002 -#define SUFFICIENT_DSP_RESET_TIME 1000 -#define DEFAULT_MPUI_CONFIG 0x05cf -#define ENABLE_XORCLK 0x2 -#define DSP_CLOCK_ENABLE 0x2000 -#define DSP_IDLE_MODE 0x2 -#define TC_IDLE_REQUEST (0x0000000c) - -#define IRQ_LEVEL2 (1<<0) -#define IRQ_KEYBOARD (1<<1) -#define IRQ_UART2 (1<<15) - -#define PDE_BIT 0x08 -#define PWD_EN_BIT 0x04 -#define EN_PERCK_BIT 0x04 - -#define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7 -#define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5 -#define OMAP1510_IDLE_LOOP_REQUEST 0x0c00 -#define OMAP1510_IDLE_CLOCK_DOMAINS 0x2 - -/* Both big sleep and deep sleep use same values. Difference is in ULPD. */ -#define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7 -#define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7 -#define OMAP1610_IDLECT3_VAL 0x3f -#define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c -#define OMAP1610_IDLECT3 0xfffece24 -#define OMAP1610_IDLE_LOOP_REQUEST 0x0400 - -#define OMAP730_IDLECT1_SLEEP_VAL 0x16c7 -#define OMAP730_IDLECT2_SLEEP_VAL 0x09c7 -#define OMAP730_IDLECT3_VAL 0x3f -#define OMAP730_IDLECT3 0xfffece24 -#define OMAP730_IDLE_LOOP_REQUEST 0x0C00 - -#if !defined(CONFIG_ARCH_OMAP730) && \ - !defined(CONFIG_ARCH_OMAP15XX) && \ - !defined(CONFIG_ARCH_OMAP16XX) && \ - !defined(CONFIG_ARCH_OMAP24XX) -#warning "Power management for this processor not implemented yet" -#endif - -#ifndef __ASSEMBLER__ - -#include <linux/clk.h> - -extern void prevent_idle_sleep(void); -extern void allow_idle_sleep(void); - -extern void omap_pm_idle(void); -extern void omap_pm_suspend(void); -extern void omap730_cpu_suspend(unsigned short, unsigned short); -extern void omap1510_cpu_suspend(unsigned short, unsigned short); -extern void omap1610_cpu_suspend(unsigned short, unsigned short); -extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl, - void __iomem *sdrc_power); -extern void omap730_idle_loop_suspend(void); -extern void omap1510_idle_loop_suspend(void); -extern void omap1610_idle_loop_suspend(void); -extern void omap24xx_idle_loop_suspend(void); - -extern unsigned int omap730_cpu_suspend_sz; -extern unsigned int omap1510_cpu_suspend_sz; -extern unsigned int omap1610_cpu_suspend_sz; -extern unsigned int omap24xx_cpu_suspend_sz; -extern unsigned int omap730_idle_loop_suspend_sz; -extern unsigned int omap1510_idle_loop_suspend_sz; -extern unsigned int omap1610_idle_loop_suspend_sz; -extern unsigned int omap24xx_idle_loop_suspend_sz; - -#ifdef CONFIG_OMAP_SERIAL_WAKE -extern void omap_serial_wake_trigger(int enable); -#else -#define omap_serial_wakeup_init() {} -#define omap_serial_wake_trigger(x) {} -#endif /* CONFIG_OMAP_SERIAL_WAKE */ - -#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x) -#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x)) -#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] - -#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x) -#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x)) -#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] - -#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x) -#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) -#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] - -#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x) -#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x)) -#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] - -#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) -#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) -#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] - -#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x) -#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x)) -#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] - -#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x -#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] -#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] - -/* - * List of global OMAP registers to preserve. - * More ones like CP and general purpose register values are preserved - * with the stack pointer in sleep.S. - */ - -enum arm_save_state { - ARM_SLEEP_SAVE_START = 0, - /* - * MPU control registers 32 bits - */ - ARM_SLEEP_SAVE_ARM_CKCTL, - ARM_SLEEP_SAVE_ARM_IDLECT1, - ARM_SLEEP_SAVE_ARM_IDLECT2, - ARM_SLEEP_SAVE_ARM_IDLECT3, - ARM_SLEEP_SAVE_ARM_EWUPCT, - ARM_SLEEP_SAVE_ARM_RSTCT1, - ARM_SLEEP_SAVE_ARM_RSTCT2, - ARM_SLEEP_SAVE_ARM_SYSST, - ARM_SLEEP_SAVE_SIZE -}; - -enum dsp_save_state { - DSP_SLEEP_SAVE_START = 0, - /* - * DSP registers 16 bits - */ - DSP_SLEEP_SAVE_DSP_IDLECT2, - DSP_SLEEP_SAVE_SIZE -}; - -enum ulpd_save_state { - ULPD_SLEEP_SAVE_START = 0, - /* - * ULPD registers 16 bits - */ - ULPD_SLEEP_SAVE_ULPD_IT_STATUS, - ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL, - ULPD_SLEEP_SAVE_ULPD_SOFT_REQ, - ULPD_SLEEP_SAVE_ULPD_STATUS_REQ, - ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL, - ULPD_SLEEP_SAVE_ULPD_POWER_CTRL, - ULPD_SLEEP_SAVE_SIZE -}; - -enum mpui1510_save_state { - MPUI1510_SLEEP_SAVE_START = 0, - /* - * MPUI registers 32 bits - */ - MPUI1510_SLEEP_SAVE_MPUI_CTRL, - MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, - MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG, - MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS, - MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, - MPUI1510_SLEEP_SAVE_EMIFS_CONFIG, - MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR, - MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR, -#if defined(CONFIG_ARCH_OMAP15XX) - MPUI1510_SLEEP_SAVE_SIZE -#else - MPUI1510_SLEEP_SAVE_SIZE = 0 -#endif -}; - -enum mpui730_save_state { - MPUI730_SLEEP_SAVE_START = 0, - /* - * MPUI registers 32 bits - */ - MPUI730_SLEEP_SAVE_MPUI_CTRL, - MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, - MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG, - MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS, - MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, - MPUI730_SLEEP_SAVE_EMIFS_CONFIG, - MPUI730_SLEEP_SAVE_OMAP_IH1_MIR, - MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR, - MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR, -#if defined(CONFIG_ARCH_OMAP730) - MPUI730_SLEEP_SAVE_SIZE -#else - MPUI730_SLEEP_SAVE_SIZE = 0 -#endif -}; - -enum mpui1610_save_state { - MPUI1610_SLEEP_SAVE_START = 0, - /* - * MPUI registers 32 bits - */ - MPUI1610_SLEEP_SAVE_MPUI_CTRL, - MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, - MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG, - MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS, - MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, - MPUI1610_SLEEP_SAVE_EMIFS_CONFIG, - MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR, - MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR, - MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR, - MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR, - MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR, -#if defined(CONFIG_ARCH_OMAP16XX) - MPUI1610_SLEEP_SAVE_SIZE -#else - MPUI1610_SLEEP_SAVE_SIZE = 0 -#endif -}; - -enum omap24xx_save_state { - OMAP24XX_SLEEP_SAVE_START = 0, - OMAP24XX_SLEEP_SAVE_INTC_MIR0, - OMAP24XX_SLEEP_SAVE_INTC_MIR1, - OMAP24XX_SLEEP_SAVE_INTC_MIR2, - - OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU, - OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE, - OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX, - OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP, - OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM, - - OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU, - OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE, - OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX, - OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP, - OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM, - - OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE, - OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE, - OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE, - OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE, - OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX, - OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP, - OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN, - OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP, - OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM, - - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP, - OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM, - - OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE, - OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE, - OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE, - OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE, - OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE, - OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE, - OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1, - OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1, - OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1, - OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1, - OMAP24XX_SLEEP_SAVE_GPIO3_OE, - OMAP24XX_SLEEP_SAVE_GPIO4_OE, - OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT, - OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT, - OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2, - OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX, - OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX, - OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0, - OMAP24XX_SLEEP_SAVE_SIZE -}; - -#endif /* ASSEMBLER */ -#endif /* __ASM_ARCH_OMAP_PM_H */ diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h index 8a676a0..13abd02 100644 --- a/arch/arm/plat-omap/include/mach/serial.h +++ b/arch/arm/plat-omap/include/mach/serial.h @@ -1,5 +1,8 @@ /* - * arch/arm/plat-omap/include/mach/serial.h + * arch/arm/plat-omap/include/mach/serial.h + * + * Copyright (C) 2009 Texas Instruments + * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com> * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -15,19 +18,28 @@ #define OMAP_UART1_BASE 0xfffb0000 #define OMAP_UART2_BASE 0xfffb0800 #define OMAP_UART3_BASE 0xfffb9800 +#define OMAP_MAX_NR_PORTS 3 #elif defined(CONFIG_ARCH_OMAP2) /* OMAP2 serial ports */ #define OMAP_UART1_BASE 0x4806a000 #define OMAP_UART2_BASE 0x4806c000 #define OMAP_UART3_BASE 0x4806e000 +#define OMAP_MAX_NR_PORTS 3 #elif defined(CONFIG_ARCH_OMAP3) /* OMAP3 serial ports */ #define OMAP_UART1_BASE 0x4806a000 #define OMAP_UART2_BASE 0x4806c000 #define OMAP_UART3_BASE 0x49020000 +#define OMAP_MAX_NR_PORTS 3 +#elif defined(CONFIG_ARCH_OMAP4) +/* OMAP4 serial ports */ +#define OMAP_UART1_BASE 0x4806a000 +#define OMAP_UART2_BASE 0x4806c000 +#define OMAP_UART3_BASE 0x48020000 +#define OMAP_UART4_BASE 0x4806e000 +#define OMAP_MAX_NR_PORTS 4 #endif -#define OMAP_MAX_NR_PORTS 3 #define OMAP1510_BASE_BAUD (12000000/16) #define OMAP16XX_BASE_BAUD (48000000/16) #define OMAP24XX_BASE_BAUD (48000000/16) @@ -40,4 +52,13 @@ __ret; \ }) +#ifndef __ASSEMBLER__ +extern void omap_serial_init(void); +extern int omap_uart_can_sleep(void); +extern void omap_uart_check_wakeup(void); +extern void omap_uart_prepare_suspend(void); +extern void omap_uart_prepare_idle(int num); +extern void omap_uart_resume_idle(int num); +#endif + #endif diff --git a/arch/arm/plat-omap/include/mach/smp.h b/arch/arm/plat-omap/include/mach/smp.h new file mode 100644 index 0000000..dcaa8fd --- /dev/null +++ b/arch/arm/plat-omap/include/mach/smp.h @@ -0,0 +1,51 @@ +/* + * OMAP4 machine specific smp.h + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * Author: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Interface functions needed for the SMP. This file is based on arm + * realview smp platform. + * Copyright (c) 2003 ARM Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef OMAP_ARCH_SMP_H +#define OMAP_ARCH_SMP_H + +#include <asm/hardware/gic.h> + +/* + * set_event() is used to wake up secondary core from wfe using sev. ROM + * code puts the second core into wfe(standby). + * + */ +#define set_event() __asm__ __volatile__ ("sev" : : : "memory") + +/* Needed for secondary core boot */ +extern void omap_secondary_startup(void); + +/* + * We use Soft IRQ1 as the IPI + */ +static inline void smp_cross_call(const struct cpumask *mask) +{ + gic_raise_softirq(mask, 1); +} + +/* + * Read MPIDR: Multiprocessor affinity register + */ +#define hard_smp_processor_id() \ + ({ \ + unsigned int cpunum; \ + __asm__("mrc p15, 0, %0, c0, c0, 5" \ + : "=r" (cpunum)); \ + cpunum &= 0x0F; \ + }) + +#endif diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h index ab35d62..dca7c16 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/mach/sram.h @@ -23,7 +23,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, - u32 sdrc_actim_ctrlb, u32 m2); + u32 sdrc_actim_ctrlb, u32 m2, + u32 unlock_dll); /* Do not use these */ extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); @@ -60,7 +61,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, - u32 sdrc_actim_ctrlb, u32 m2); + u32 sdrc_actim_ctrlb, u32 m2, + u32 unlock_dll); extern unsigned long omap3_sram_configure_core_dpll_sz; #endif diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h index 69f0cee..f337e17 100644 --- a/arch/arm/plat-omap/include/mach/usb.h +++ b/arch/arm/plat-omap/include/mach/usb.h @@ -27,13 +27,7 @@ #define UDC_BASE OMAP2_UDC_BASE #define OMAP_OHCI_BASE OMAP2_OHCI_BASE -#ifdef CONFIG_USB_MUSB_SOC extern void usb_musb_init(void); -#else -static inline void usb_musb_init(void) -{ -} -#endif #endif diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/plat-omap/include/mach/vmalloc.h index dc104cd..b97dfaf 100644 --- a/arch/arm/plat-omap/include/mach/vmalloc.h +++ b/arch/arm/plat-omap/include/mach/vmalloc.h @@ -17,5 +17,5 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) +#define VMALLOC_END (PAGE_OFFSET + 0x18000000) diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c index af326ef..9b42d72 100644 --- a/arch/arm/plat-omap/io.c +++ b/arch/arm/plat-omap/io.c @@ -1,3 +1,14 @@ +/* + * Common io.c file + * This file is created by Russell King <rmk+kernel@arm.linux.org.uk> + * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ #include <linux/module.h> #include <linux/io.h> #include <linux/mm.h> @@ -7,6 +18,7 @@ #include <mach/omap16xx.h> #include <mach/omap24xx.h> #include <mach/omap34xx.h> +#include <mach/omap44xx.h> #define BETWEEN(p,st,sz) ((p) >= (st) && (p) < ((st) + (sz))) #define XLATE(p,pst,vst) ((void __iomem *)((p) - (pst) + (vst))) @@ -92,7 +104,22 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT); } #endif - +#ifdef CONFIG_ARCH_OMAP4 + if (cpu_is_omap44xx()) { + if (BETWEEN(p, L3_44XX_PHYS, L3_44XX_SIZE)) + return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT); + if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE)) + return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT); + if (BETWEEN(p, L4_WK_44XX_PHYS, L4_WK_44XX_SIZE)) + return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT); + if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE)) + return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT); + if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE)) + return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT); + if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE)) + return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT); + } +#endif return __arm_ioremap(p, size, type); } EXPORT_SYMBOL(omap_ioremap); diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c new file mode 100644 index 0000000..4cf449f --- /dev/null +++ b/arch/arm/plat-omap/iommu.c @@ -0,0 +1,996 @@ +/* + * omap iommu: tlb and pagetable primitives + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, + * Paul Mundt and Toshihiro Kobayashi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/clk.h> +#include <linux/platform_device.h> + +#include <asm/cacheflush.h> + +#include <mach/iommu.h> + +#include "iopgtable.h" + +/* accommodate the difference between omap1 and omap2/3 */ +static const struct iommu_functions *arch_iommu; + +static struct platform_driver omap_iommu_driver; +static struct kmem_cache *iopte_cachep; + +/** + * install_iommu_arch - Install archtecure specific iommu functions + * @ops: a pointer to architecture specific iommu functions + * + * There are several kind of iommu algorithm(tlb, pagetable) among + * omap series. This interface installs such an iommu algorighm. + **/ +int install_iommu_arch(const struct iommu_functions *ops) +{ + if (arch_iommu) + return -EBUSY; + + arch_iommu = ops; + return 0; +} +EXPORT_SYMBOL_GPL(install_iommu_arch); + +/** + * uninstall_iommu_arch - Uninstall archtecure specific iommu functions + * @ops: a pointer to architecture specific iommu functions + * + * This interface uninstalls the iommu algorighm installed previously. + **/ +void uninstall_iommu_arch(const struct iommu_functions *ops) +{ + if (arch_iommu != ops) + pr_err("%s: not your arch\n", __func__); + + arch_iommu = NULL; +} +EXPORT_SYMBOL_GPL(uninstall_iommu_arch); + +/** + * iommu_save_ctx - Save registers for pm off-mode support + * @obj: target iommu + **/ +void iommu_save_ctx(struct iommu *obj) +{ + arch_iommu->save_ctx(obj); +} +EXPORT_SYMBOL_GPL(iommu_save_ctx); + +/** + * iommu_restore_ctx - Restore registers for pm off-mode support + * @obj: target iommu + **/ +void iommu_restore_ctx(struct iommu *obj) +{ + arch_iommu->restore_ctx(obj); +} +EXPORT_SYMBOL_GPL(iommu_restore_ctx); + +/** + * iommu_arch_version - Return running iommu arch version + **/ +u32 iommu_arch_version(void) +{ + return arch_iommu->version; +} +EXPORT_SYMBOL_GPL(iommu_arch_version); + +static int iommu_enable(struct iommu *obj) +{ + int err; + + if (!obj) + return -EINVAL; + + clk_enable(obj->clk); + + err = arch_iommu->enable(obj); + + clk_disable(obj->clk); + return err; +} + +static void iommu_disable(struct iommu *obj) +{ + if (!obj) + return; + + clk_enable(obj->clk); + + arch_iommu->disable(obj); + + clk_disable(obj->clk); +} + +/* + * TLB operations + */ +void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) +{ + BUG_ON(!cr || !e); + + arch_iommu->cr_to_e(cr, e); +} +EXPORT_SYMBOL_GPL(iotlb_cr_to_e); + +static inline int iotlb_cr_valid(struct cr_regs *cr) +{ + if (!cr) + return -EINVAL; + + return arch_iommu->cr_valid(cr); +} + +static inline struct cr_regs *iotlb_alloc_cr(struct iommu *obj, + struct iotlb_entry *e) +{ + if (!e) + return NULL; + + return arch_iommu->alloc_cr(obj, e); +} + +u32 iotlb_cr_to_virt(struct cr_regs *cr) +{ + return arch_iommu->cr_to_virt(cr); +} +EXPORT_SYMBOL_GPL(iotlb_cr_to_virt); + +static u32 get_iopte_attr(struct iotlb_entry *e) +{ + return arch_iommu->get_pte_attr(e); +} + +static u32 iommu_report_fault(struct iommu *obj, u32 *da) +{ + return arch_iommu->fault_isr(obj, da); +} + +static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l) +{ + u32 val; + + val = iommu_read_reg(obj, MMU_LOCK); + + l->base = MMU_LOCK_BASE(val); + l->vict = MMU_LOCK_VICT(val); + + BUG_ON(l->base != 0); /* Currently no preservation is used */ +} + +static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l) +{ + u32 val; + + BUG_ON(l->base != 0); /* Currently no preservation is used */ + + val = (l->base << MMU_LOCK_BASE_SHIFT); + val |= (l->vict << MMU_LOCK_VICT_SHIFT); + + iommu_write_reg(obj, val, MMU_LOCK); +} + +static void iotlb_read_cr(struct iommu *obj, struct cr_regs *cr) +{ + arch_iommu->tlb_read_cr(obj, cr); +} + +static void iotlb_load_cr(struct iommu *obj, struct cr_regs *cr) +{ + arch_iommu->tlb_load_cr(obj, cr); + + iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); + iommu_write_reg(obj, 1, MMU_LD_TLB); +} + +/** + * iotlb_dump_cr - Dump an iommu tlb entry into buf + * @obj: target iommu + * @cr: contents of cam and ram register + * @buf: output buffer + **/ +static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr, + char *buf) +{ + BUG_ON(!cr || !buf); + + return arch_iommu->dump_cr(obj, cr, buf); +} + +/** + * load_iotlb_entry - Set an iommu tlb entry + * @obj: target iommu + * @e: an iommu tlb entry info + **/ +int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) +{ + int i; + int err = 0; + struct iotlb_lock l; + struct cr_regs *cr; + + if (!obj || !obj->nr_tlb_entries || !e) + return -EINVAL; + + clk_enable(obj->clk); + + for (i = 0; i < obj->nr_tlb_entries; i++) { + struct cr_regs tmp; + + iotlb_lock_get(obj, &l); + l.vict = i; + iotlb_lock_set(obj, &l); + iotlb_read_cr(obj, &tmp); + if (!iotlb_cr_valid(&tmp)) + break; + } + + if (i == obj->nr_tlb_entries) { + dev_dbg(obj->dev, "%s: full: no entry\n", __func__); + err = -EBUSY; + goto out; + } + + cr = iotlb_alloc_cr(obj, e); + if (IS_ERR(cr)) { + clk_disable(obj->clk); + return PTR_ERR(cr); + } + + iotlb_load_cr(obj, cr); + kfree(cr); + + /* increment victim for next tlb load */ + if (++l.vict == obj->nr_tlb_entries) + l.vict = 0; + iotlb_lock_set(obj, &l); +out: + clk_disable(obj->clk); + return err; +} +EXPORT_SYMBOL_GPL(load_iotlb_entry); + +/** + * flush_iotlb_page - Clear an iommu tlb entry + * @obj: target iommu + * @da: iommu device virtual address + * + * Clear an iommu tlb entry which includes 'da' address. + **/ +void flush_iotlb_page(struct iommu *obj, u32 da) +{ + struct iotlb_lock l; + int i; + + clk_enable(obj->clk); + + for (i = 0; i < obj->nr_tlb_entries; i++) { + struct cr_regs cr; + u32 start; + size_t bytes; + + iotlb_lock_get(obj, &l); + l.vict = i; + iotlb_lock_set(obj, &l); + iotlb_read_cr(obj, &cr); + if (!iotlb_cr_valid(&cr)) + continue; + + start = iotlb_cr_to_virt(&cr); + bytes = iopgsz_to_bytes(cr.cam & 3); + + if ((start <= da) && (da < start + bytes)) { + dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", + __func__, start, da, bytes); + + iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); + } + } + clk_disable(obj->clk); + + if (i == obj->nr_tlb_entries) + dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); +} +EXPORT_SYMBOL_GPL(flush_iotlb_page); + +/** + * flush_iotlb_range - Clear an iommu tlb entries + * @obj: target iommu + * @start: iommu device virtual address(start) + * @end: iommu device virtual address(end) + * + * Clear an iommu tlb entry which includes 'da' address. + **/ +void flush_iotlb_range(struct iommu *obj, u32 start, u32 end) +{ + u32 da = start; + + while (da < end) { + flush_iotlb_page(obj, da); + /* FIXME: Optimize for multiple page size */ + da += IOPTE_SIZE; + } +} +EXPORT_SYMBOL_GPL(flush_iotlb_range); + +/** + * flush_iotlb_all - Clear all iommu tlb entries + * @obj: target iommu + **/ +void flush_iotlb_all(struct iommu *obj) +{ + struct iotlb_lock l; + + clk_enable(obj->clk); + + l.base = 0; + l.vict = 0; + iotlb_lock_set(obj, &l); + + iommu_write_reg(obj, 1, MMU_GFLUSH); + + clk_disable(obj->clk); +} +EXPORT_SYMBOL_GPL(flush_iotlb_all); + +#if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) + +ssize_t iommu_dump_ctx(struct iommu *obj, char *buf) +{ + ssize_t bytes; + + if (!obj || !buf) + return -EINVAL; + + clk_enable(obj->clk); + + bytes = arch_iommu->dump_ctx(obj, buf); + + clk_disable(obj->clk); + + return bytes; +} +EXPORT_SYMBOL_GPL(iommu_dump_ctx); + +static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs) +{ + int i; + struct iotlb_lock saved, l; + struct cr_regs *p = crs; + + clk_enable(obj->clk); + + iotlb_lock_get(obj, &saved); + memcpy(&l, &saved, sizeof(saved)); + + for (i = 0; i < obj->nr_tlb_entries; i++) { + struct cr_regs tmp; + + iotlb_lock_get(obj, &l); + l.vict = i; + iotlb_lock_set(obj, &l); + iotlb_read_cr(obj, &tmp); + if (!iotlb_cr_valid(&tmp)) + continue; + + *p++ = tmp; + } + iotlb_lock_set(obj, &saved); + clk_disable(obj->clk); + + return p - crs; +} + +/** + * dump_tlb_entries - dump cr arrays to given buffer + * @obj: target iommu + * @buf: output buffer + **/ +size_t dump_tlb_entries(struct iommu *obj, char *buf) +{ + int i, n; + struct cr_regs *cr; + char *p = buf; + + cr = kcalloc(obj->nr_tlb_entries, sizeof(*cr), GFP_KERNEL); + if (!cr) + return 0; + + n = __dump_tlb_entries(obj, cr); + for (i = 0; i < n; i++) + p += iotlb_dump_cr(obj, cr + i, p); + kfree(cr); + + return p - buf; +} +EXPORT_SYMBOL_GPL(dump_tlb_entries); + +int foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) +{ + return driver_for_each_device(&omap_iommu_driver.driver, + NULL, data, fn); +} +EXPORT_SYMBOL_GPL(foreach_iommu_device); + +#endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ + +/* + * H/W pagetable operations + */ +static void flush_iopgd_range(u32 *first, u32 *last) +{ + /* FIXME: L2 cache should be taken care of if it exists */ + do { + asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" + : : "r" (first)); + first += L1_CACHE_BYTES / sizeof(*first); + } while (first <= last); +} + +static void flush_iopte_range(u32 *first, u32 *last) +{ + /* FIXME: L2 cache should be taken care of if it exists */ + do { + asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" + : : "r" (first)); + first += L1_CACHE_BYTES / sizeof(*first); + } while (first <= last); +} + +static void iopte_free(u32 *iopte) +{ + /* Note: freed iopte's must be clean ready for re-use */ + kmem_cache_free(iopte_cachep, iopte); +} + +static u32 *iopte_alloc(struct iommu *obj, u32 *iopgd, u32 da) +{ + u32 *iopte; + + /* a table has already existed */ + if (*iopgd) + goto pte_ready; + + /* + * do the allocation outside the page table lock + */ + spin_unlock(&obj->page_table_lock); + iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); + spin_lock(&obj->page_table_lock); + + if (!*iopgd) { + if (!iopte) + return ERR_PTR(-ENOMEM); + + *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; + flush_iopgd_range(iopgd, iopgd); + + dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); + } else { + /* We raced, free the reduniovant table */ + iopte_free(iopte); + } + +pte_ready: + iopte = iopte_offset(iopgd, da); + + dev_vdbg(obj->dev, + "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", + __func__, da, iopgd, *iopgd, iopte, *iopte); + + return iopte; +} + +static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot) +{ + u32 *iopgd = iopgd_offset(obj, da); + + *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; + flush_iopgd_range(iopgd, iopgd); + return 0; +} + +static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot) +{ + u32 *iopgd = iopgd_offset(obj, da); + int i; + + for (i = 0; i < 16; i++) + *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; + flush_iopgd_range(iopgd, iopgd + 15); + return 0; +} + +static int iopte_alloc_page(struct iommu *obj, u32 da, u32 pa, u32 prot) +{ + u32 *iopgd = iopgd_offset(obj, da); + u32 *iopte = iopte_alloc(obj, iopgd, da); + + if (IS_ERR(iopte)) + return PTR_ERR(iopte); + + *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; + flush_iopte_range(iopte, iopte); + + dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", + __func__, da, pa, iopte, *iopte); + + return 0; +} + +static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot) +{ + u32 *iopgd = iopgd_offset(obj, da); + u32 *iopte = iopte_alloc(obj, iopgd, da); + int i; + + if (IS_ERR(iopte)) + return PTR_ERR(iopte); + + for (i = 0; i < 16; i++) + *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; + flush_iopte_range(iopte, iopte + 15); + return 0; +} + +static int iopgtable_store_entry_core(struct iommu *obj, struct iotlb_entry *e) +{ + int (*fn)(struct iommu *, u32, u32, u32); + u32 prot; + int err; + + if (!obj || !e) + return -EINVAL; + + switch (e->pgsz) { + case MMU_CAM_PGSZ_16M: + fn = iopgd_alloc_super; + break; + case MMU_CAM_PGSZ_1M: + fn = iopgd_alloc_section; + break; + case MMU_CAM_PGSZ_64K: + fn = iopte_alloc_large; + break; + case MMU_CAM_PGSZ_4K: + fn = iopte_alloc_page; + break; + default: + fn = NULL; + BUG(); + break; + } + + prot = get_iopte_attr(e); + + spin_lock(&obj->page_table_lock); + err = fn(obj, e->da, e->pa, prot); + spin_unlock(&obj->page_table_lock); + + return err; +} + +/** + * iopgtable_store_entry - Make an iommu pte entry + * @obj: target iommu + * @e: an iommu tlb entry info + **/ +int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e) +{ + int err; + + flush_iotlb_page(obj, e->da); + err = iopgtable_store_entry_core(obj, e); +#ifdef PREFETCH_IOTLB + if (!err) + load_iotlb_entry(obj, e); +#endif + return err; +} +EXPORT_SYMBOL_GPL(iopgtable_store_entry); + +/** + * iopgtable_lookup_entry - Lookup an iommu pte entry + * @obj: target iommu + * @da: iommu device virtual address + * @ppgd: iommu pgd entry pointer to be returned + * @ppte: iommu pte entry pointer to be returned + **/ +void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte) +{ + u32 *iopgd, *iopte = NULL; + + iopgd = iopgd_offset(obj, da); + if (!*iopgd) + goto out; + + if (*iopgd & IOPGD_TABLE) + iopte = iopte_offset(iopgd, da); +out: + *ppgd = iopgd; + *ppte = iopte; +} +EXPORT_SYMBOL_GPL(iopgtable_lookup_entry); + +static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) +{ + size_t bytes; + u32 *iopgd = iopgd_offset(obj, da); + int nent = 1; + + if (!*iopgd) + return 0; + + if (*iopgd & IOPGD_TABLE) { + int i; + u32 *iopte = iopte_offset(iopgd, da); + + bytes = IOPTE_SIZE; + if (*iopte & IOPTE_LARGE) { + nent *= 16; + /* rewind to the 1st entry */ + iopte = (u32 *)((u32)iopte & IOLARGE_MASK); + } + bytes *= nent; + memset(iopte, 0, nent * sizeof(*iopte)); + flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); + + /* + * do table walk to check if this table is necessary or not + */ + iopte = iopte_offset(iopgd, 0); + for (i = 0; i < PTRS_PER_IOPTE; i++) + if (iopte[i]) + goto out; + + iopte_free(iopte); + nent = 1; /* for the next L1 entry */ + } else { + bytes = IOPGD_SIZE; + if (*iopgd & IOPGD_SUPER) { + nent *= 16; + /* rewind to the 1st entry */ + iopgd = (u32 *)((u32)iopgd & IOSUPER_MASK); + } + bytes *= nent; + } + memset(iopgd, 0, nent * sizeof(*iopgd)); + flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); +out: + return bytes; +} + +/** + * iopgtable_clear_entry - Remove an iommu pte entry + * @obj: target iommu + * @da: iommu device virtual address + **/ +size_t iopgtable_clear_entry(struct iommu *obj, u32 da) +{ + size_t bytes; + + spin_lock(&obj->page_table_lock); + + bytes = iopgtable_clear_entry_core(obj, da); + flush_iotlb_page(obj, da); + + spin_unlock(&obj->page_table_lock); + + return bytes; +} +EXPORT_SYMBOL_GPL(iopgtable_clear_entry); + +static void iopgtable_clear_entry_all(struct iommu *obj) +{ + int i; + + spin_lock(&obj->page_table_lock); + + for (i = 0; i < PTRS_PER_IOPGD; i++) { + u32 da; + u32 *iopgd; + + da = i << IOPGD_SHIFT; + iopgd = iopgd_offset(obj, da); + + if (!*iopgd) + continue; + + if (*iopgd & IOPGD_TABLE) + iopte_free(iopte_offset(iopgd, 0)); + + *iopgd = 0; + flush_iopgd_range(iopgd, iopgd); + } + + flush_iotlb_all(obj); + + spin_unlock(&obj->page_table_lock); +} + +/* + * Device IOMMU generic operations + */ +static irqreturn_t iommu_fault_handler(int irq, void *data) +{ + u32 stat, da; + u32 *iopgd, *iopte; + int err = -EIO; + struct iommu *obj = data; + + if (!obj->refcount) + return IRQ_NONE; + + /* Dynamic loading TLB or PTE */ + if (obj->isr) + err = obj->isr(obj); + + if (!err) + return IRQ_HANDLED; + + clk_enable(obj->clk); + stat = iommu_report_fault(obj, &da); + clk_disable(obj->clk); + if (!stat) + return IRQ_HANDLED; + + iopgd = iopgd_offset(obj, da); + + if (!(*iopgd & IOPGD_TABLE)) { + dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__, + da, iopgd, *iopgd); + return IRQ_NONE; + } + + iopte = iopte_offset(iopgd, da); + + dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", + __func__, da, iopgd, *iopgd, iopte, *iopte); + + return IRQ_NONE; +} + +static int device_match_by_alias(struct device *dev, void *data) +{ + struct iommu *obj = to_iommu(dev); + const char *name = data; + + pr_debug("%s: %s %s\n", __func__, obj->name, name); + + return strcmp(obj->name, name) == 0; +} + +/** + * iommu_get - Get iommu handler + * @name: target iommu name + **/ +struct iommu *iommu_get(const char *name) +{ + int err = -ENOMEM; + struct device *dev; + struct iommu *obj; + + dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, + device_match_by_alias); + if (!dev) + return ERR_PTR(-ENODEV); + + obj = to_iommu(dev); + + mutex_lock(&obj->iommu_lock); + + if (obj->refcount++ == 0) { + err = iommu_enable(obj); + if (err) + goto err_enable; + flush_iotlb_all(obj); + } + + if (!try_module_get(obj->owner)) + goto err_module; + + mutex_unlock(&obj->iommu_lock); + + dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); + return obj; + +err_module: + if (obj->refcount == 1) + iommu_disable(obj); +err_enable: + obj->refcount--; + mutex_unlock(&obj->iommu_lock); + return ERR_PTR(err); +} +EXPORT_SYMBOL_GPL(iommu_get); + +/** + * iommu_put - Put back iommu handler + * @obj: target iommu + **/ +void iommu_put(struct iommu *obj) +{ + if (!obj && IS_ERR(obj)) + return; + + mutex_lock(&obj->iommu_lock); + + if (--obj->refcount == 0) + iommu_disable(obj); + + module_put(obj->owner); + + mutex_unlock(&obj->iommu_lock); + + dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); +} +EXPORT_SYMBOL_GPL(iommu_put); + +/* + * OMAP Device MMU(IOMMU) detection + */ +static int __devinit omap_iommu_probe(struct platform_device *pdev) +{ + int err = -ENODEV; + void *p; + int irq; + struct iommu *obj; + struct resource *res; + struct iommu_platform_data *pdata = pdev->dev.platform_data; + + if (pdev->num_resources != 2) + return -EINVAL; + + obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); + if (!obj) + return -ENOMEM; + + obj->clk = clk_get(&pdev->dev, pdata->clk_name); + if (IS_ERR(obj->clk)) + goto err_clk; + + obj->nr_tlb_entries = pdata->nr_tlb_entries; + obj->name = pdata->name; + obj->dev = &pdev->dev; + obj->ctx = (void *)obj + sizeof(*obj); + + mutex_init(&obj->iommu_lock); + mutex_init(&obj->mmap_lock); + spin_lock_init(&obj->page_table_lock); + INIT_LIST_HEAD(&obj->mmap); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + err = -ENODEV; + goto err_mem; + } + obj->regbase = ioremap(res->start, resource_size(res)); + if (!obj->regbase) { + err = -ENOMEM; + goto err_mem; + } + + res = request_mem_region(res->start, resource_size(res), + dev_name(&pdev->dev)); + if (!res) { + err = -EIO; + goto err_mem; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + err = -ENODEV; + goto err_irq; + } + err = request_irq(irq, iommu_fault_handler, IRQF_SHARED, + dev_name(&pdev->dev), obj); + if (err < 0) + goto err_irq; + platform_set_drvdata(pdev, obj); + + p = (void *)__get_free_pages(GFP_KERNEL, get_order(IOPGD_TABLE_SIZE)); + if (!p) { + err = -ENOMEM; + goto err_pgd; + } + memset(p, 0, IOPGD_TABLE_SIZE); + clean_dcache_area(p, IOPGD_TABLE_SIZE); + obj->iopgd = p; + + BUG_ON(!IS_ALIGNED((unsigned long)obj->iopgd, IOPGD_TABLE_SIZE)); + + dev_info(&pdev->dev, "%s registered\n", obj->name); + return 0; + +err_pgd: + free_irq(irq, obj); +err_irq: + release_mem_region(res->start, resource_size(res)); + iounmap(obj->regbase); +err_mem: + clk_put(obj->clk); +err_clk: + kfree(obj); + return err; +} + +static int __devexit omap_iommu_remove(struct platform_device *pdev) +{ + int irq; + struct resource *res; + struct iommu *obj = platform_get_drvdata(pdev); + + platform_set_drvdata(pdev, NULL); + + iopgtable_clear_entry_all(obj); + free_pages((unsigned long)obj->iopgd, get_order(IOPGD_TABLE_SIZE)); + + irq = platform_get_irq(pdev, 0); + free_irq(irq, obj); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, resource_size(res)); + iounmap(obj->regbase); + + clk_put(obj->clk); + dev_info(&pdev->dev, "%s removed\n", obj->name); + kfree(obj); + return 0; +} + +static struct platform_driver omap_iommu_driver = { + .probe = omap_iommu_probe, + .remove = __devexit_p(omap_iommu_remove), + .driver = { + .name = "omap-iommu", + }, +}; + +static void iopte_cachep_ctor(void *iopte) +{ + clean_dcache_area(iopte, IOPTE_TABLE_SIZE); +} + +static int __init omap_iommu_init(void) +{ + struct kmem_cache *p; + const unsigned long flags = SLAB_HWCACHE_ALIGN; + size_t align = 1 << 10; /* L2 pagetable alignement */ + + p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, + iopte_cachep_ctor); + if (!p) + return -ENOMEM; + iopte_cachep = p; + + return platform_driver_register(&omap_iommu_driver); +} +module_init(omap_iommu_init); + +static void __exit omap_iommu_exit(void) +{ + kmem_cache_destroy(iopte_cachep); + + platform_driver_unregister(&omap_iommu_driver); +} +module_exit(omap_iommu_exit); + +MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); +MODULE_ALIAS("platform:omap-iommu"); +MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h new file mode 100644 index 0000000..37dac43 --- /dev/null +++ b/arch/arm/plat-omap/iopgtable.h @@ -0,0 +1,72 @@ +/* + * omap iommu: pagetable definitions + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PLAT_OMAP_IOMMU_H +#define __PLAT_OMAP_IOMMU_H + +#define IOPGD_SHIFT 20 +#define IOPGD_SIZE (1 << IOPGD_SHIFT) +#define IOPGD_MASK (~(IOPGD_SIZE - 1)) +#define IOSECTION_MASK IOPGD_MASK +#define PTRS_PER_IOPGD (1 << (32 - IOPGD_SHIFT)) +#define IOPGD_TABLE_SIZE (PTRS_PER_IOPGD * sizeof(u32)) + +#define IOSUPER_SIZE (IOPGD_SIZE << 4) +#define IOSUPER_MASK (~(IOSUPER_SIZE - 1)) + +#define IOPTE_SHIFT 12 +#define IOPTE_SIZE (1 << IOPTE_SHIFT) +#define IOPTE_MASK (~(IOPTE_SIZE - 1)) +#define IOPAGE_MASK IOPTE_MASK +#define PTRS_PER_IOPTE (1 << (IOPGD_SHIFT - IOPTE_SHIFT)) +#define IOPTE_TABLE_SIZE (PTRS_PER_IOPTE * sizeof(u32)) + +#define IOLARGE_SIZE (IOPTE_SIZE << 4) +#define IOLARGE_MASK (~(IOLARGE_SIZE - 1)) + +#define IOPGD_TABLE (1 << 0) +#define IOPGD_SECTION (2 << 0) +#define IOPGD_SUPER (1 << 18 | 2 << 0) + +#define IOPTE_SMALL (2 << 0) +#define IOPTE_LARGE (1 << 0) + +#define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1)) +#define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da)) + +#define iopte_paddr(iopgd) (*iopgd & ~((1 << 10) - 1)) +#define iopte_vaddr(iopgd) ((u32 *)phys_to_virt(iopte_paddr(iopgd))) + +#define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1)) +#define iopte_offset(iopgd, da) (iopte_vaddr(iopgd) + iopte_index(da)) + +static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, + u32 flags) +{ + memset(e, 0, sizeof(*e)); + + e->da = da; + e->pa = pa; + e->valid = 1; + /* FIXME: add OMAP1 support */ + e->pgsz = flags & MMU_CAM_PGSZ_MASK; + e->endian = flags & MMU_RAM_ENDIAN_MASK; + e->elsz = flags & MMU_RAM_ELSZ_MASK; + e->mixed = flags & MMU_RAM_MIXED_MASK; + + return iopgsz_to_bytes(e->pgsz); +} + +#define to_iommu(dev) \ + (struct iommu *)platform_get_drvdata(to_platform_device(dev)) + +#endif /* __PLAT_OMAP_IOMMU_H */ diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c new file mode 100644 index 0000000..2fce2c1 --- /dev/null +++ b/arch/arm/plat-omap/iovmm.c @@ -0,0 +1,896 @@ +/* + * omap iommu: simple virtual address space management + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/vmalloc.h> +#include <linux/device.h> +#include <linux/scatterlist.h> + +#include <asm/cacheflush.h> +#include <asm/mach/map.h> + +#include <mach/iommu.h> +#include <mach/iovmm.h> + +#include "iopgtable.h" + +/* + * A device driver needs to create address mappings between: + * + * - iommu/device address + * - physical address + * - mpu virtual address + * + * There are 4 possible patterns for them: + * + * |iova/ mapping iommu_ page + * | da pa va (d)-(p)-(v) function type + * --------------------------------------------------------------------------- + * 1 | c c c 1 - 1 - 1 _kmap() / _kunmap() s + * 2 | c c,a c 1 - 1 - 1 _kmalloc()/ _kfree() s + * 3 | c d c 1 - n - 1 _vmap() / _vunmap() s + * 4 | c d,a c 1 - n - 1 _vmalloc()/ _vfree() n* + * + * + * 'iova': device iommu virtual address + * 'da': alias of 'iova' + * 'pa': physical address + * 'va': mpu virtual address + * + * 'c': contiguous memory area + * 'd': dicontiguous memory area + * 'a': anonymous memory allocation + * '()': optional feature + * + * 'n': a normal page(4KB) size is used. + * 's': multiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used. + * + * '*': not yet, but feasible. + */ + +static struct kmem_cache *iovm_area_cachep; + +/* return total bytes of sg buffers */ +static size_t sgtable_len(const struct sg_table *sgt) +{ + unsigned int i, total = 0; + struct scatterlist *sg; + + if (!sgt) + return 0; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + size_t bytes; + + bytes = sg_dma_len(sg); + + if (!iopgsz_ok(bytes)) { + pr_err("%s: sg[%d] not iommu pagesize(%x)\n", + __func__, i, bytes); + return 0; + } + + total += bytes; + } + + return total; +} +#define sgtable_ok(x) (!!sgtable_len(x)) + +/* + * calculate the optimal number sg elements from total bytes based on + * iommu superpages + */ +static unsigned int sgtable_nents(size_t bytes) +{ + int i; + unsigned int nr_entries; + const unsigned long pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, }; + + if (!IS_ALIGNED(bytes, PAGE_SIZE)) { + pr_err("%s: wrong size %08x\n", __func__, bytes); + return 0; + } + + nr_entries = 0; + for (i = 0; i < ARRAY_SIZE(pagesize); i++) { + if (bytes >= pagesize[i]) { + nr_entries += (bytes / pagesize[i]); + bytes %= pagesize[i]; + } + } + BUG_ON(bytes); + + return nr_entries; +} + +/* allocate and initialize sg_table header(a kind of 'superblock') */ +static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags) +{ + unsigned int nr_entries; + int err; + struct sg_table *sgt; + + if (!bytes) + return ERR_PTR(-EINVAL); + + if (!IS_ALIGNED(bytes, PAGE_SIZE)) + return ERR_PTR(-EINVAL); + + /* FIXME: IOVMF_DA_FIXED should support 'superpages' */ + if ((flags & IOVMF_LINEAR) && (flags & IOVMF_DA_ANON)) { + nr_entries = sgtable_nents(bytes); + if (!nr_entries) + return ERR_PTR(-EINVAL); + } else + nr_entries = bytes / PAGE_SIZE; + + sgt = kzalloc(sizeof(*sgt), GFP_KERNEL); + if (!sgt) + return ERR_PTR(-ENOMEM); + + err = sg_alloc_table(sgt, nr_entries, GFP_KERNEL); + if (err) + return ERR_PTR(err); + + pr_debug("%s: sgt:%p(%d entries)\n", __func__, sgt, nr_entries); + + return sgt; +} + +/* free sg_table header(a kind of superblock) */ +static void sgtable_free(struct sg_table *sgt) +{ + if (!sgt) + return; + + sg_free_table(sgt); + kfree(sgt); + + pr_debug("%s: sgt:%p\n", __func__, sgt); +} + +/* map 'sglist' to a contiguous mpu virtual area and return 'va' */ +static void *vmap_sg(const struct sg_table *sgt) +{ + u32 va; + size_t total; + unsigned int i; + struct scatterlist *sg; + struct vm_struct *new; + const struct mem_type *mtype; + + mtype = get_mem_type(MT_DEVICE); + if (!mtype) + return ERR_PTR(-EINVAL); + + total = sgtable_len(sgt); + if (!total) + return ERR_PTR(-EINVAL); + + new = __get_vm_area(total, VM_IOREMAP, VMALLOC_START, VMALLOC_END); + if (!new) + return ERR_PTR(-ENOMEM); + va = (u32)new->addr; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + size_t bytes; + u32 pa; + int err; + + pa = sg_phys(sg); + bytes = sg_dma_len(sg); + + BUG_ON(bytes != PAGE_SIZE); + + err = ioremap_page(va, pa, mtype); + if (err) + goto err_out; + + va += bytes; + } + + flush_cache_vmap(new->addr, total); + return new->addr; + +err_out: + WARN_ON(1); /* FIXME: cleanup some mpu mappings */ + vunmap(new->addr); + return ERR_PTR(-EAGAIN); +} + +static inline void vunmap_sg(const void *va) +{ + vunmap(va); +} + +static struct iovm_struct *__find_iovm_area(struct iommu *obj, const u32 da) +{ + struct iovm_struct *tmp; + + list_for_each_entry(tmp, &obj->mmap, list) { + if ((da >= tmp->da_start) && (da < tmp->da_end)) { + size_t len; + + len = tmp->da_end - tmp->da_start; + + dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n", + __func__, tmp->da_start, da, tmp->da_end, len, + tmp->flags); + + return tmp; + } + } + + return NULL; +} + +/** + * find_iovm_area - find iovma which includes @da + * @da: iommu device virtual address + * + * Find the existing iovma starting at @da + */ +struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da) +{ + struct iovm_struct *area; + + mutex_lock(&obj->mmap_lock); + area = __find_iovm_area(obj, da); + mutex_unlock(&obj->mmap_lock); + + return area; +} +EXPORT_SYMBOL_GPL(find_iovm_area); + +/* + * This finds the hole(area) which fits the requested address and len + * in iovmas mmap, and returns the new allocated iovma. + */ +static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da, + size_t bytes, u32 flags) +{ + struct iovm_struct *new, *tmp; + u32 start, prev_end, alignement; + + if (!obj || !bytes) + return ERR_PTR(-EINVAL); + + start = da; + alignement = PAGE_SIZE; + + if (flags & IOVMF_DA_ANON) { + /* + * Reserve the first page for NULL + */ + start = PAGE_SIZE; + if (flags & IOVMF_LINEAR) + alignement = iopgsz_max(bytes); + start = roundup(start, alignement); + } + + tmp = NULL; + if (list_empty(&obj->mmap)) + goto found; + + prev_end = 0; + list_for_each_entry(tmp, &obj->mmap, list) { + + if ((prev_end <= start) && (start + bytes < tmp->da_start)) + goto found; + + if (flags & IOVMF_DA_ANON) + start = roundup(tmp->da_end, alignement); + + prev_end = tmp->da_end; + } + + if ((start >= prev_end) && (ULONG_MAX - start >= bytes)) + goto found; + + dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n", + __func__, da, bytes, flags); + + return ERR_PTR(-EINVAL); + +found: + new = kmem_cache_zalloc(iovm_area_cachep, GFP_KERNEL); + if (!new) + return ERR_PTR(-ENOMEM); + + new->iommu = obj; + new->da_start = start; + new->da_end = start + bytes; + new->flags = flags; + + /* + * keep ascending order of iovmas + */ + if (tmp) + list_add_tail(&new->list, &tmp->list); + else + list_add(&new->list, &obj->mmap); + + dev_dbg(obj->dev, "%s: found %08x-%08x-%08x(%x) %08x\n", + __func__, new->da_start, start, new->da_end, bytes, flags); + + return new; +} + +static void free_iovm_area(struct iommu *obj, struct iovm_struct *area) +{ + size_t bytes; + + BUG_ON(!obj || !area); + + bytes = area->da_end - area->da_start; + + dev_dbg(obj->dev, "%s: %08x-%08x(%x) %08x\n", + __func__, area->da_start, area->da_end, bytes, area->flags); + + list_del(&area->list); + kmem_cache_free(iovm_area_cachep, area); +} + +/** + * da_to_va - convert (d) to (v) + * @obj: objective iommu + * @da: iommu device virtual address + * @va: mpu virtual address + * + * Returns mpu virtual addr which corresponds to a given device virtual addr + */ +void *da_to_va(struct iommu *obj, u32 da) +{ + void *va = NULL; + struct iovm_struct *area; + + mutex_lock(&obj->mmap_lock); + + area = __find_iovm_area(obj, da); + if (!area) { + dev_dbg(obj->dev, "%s: no da area(%08x)\n", __func__, da); + goto out; + } + va = area->va; + mutex_unlock(&obj->mmap_lock); +out: + return va; +} +EXPORT_SYMBOL_GPL(da_to_va); + +static void sgtable_fill_vmalloc(struct sg_table *sgt, void *_va) +{ + unsigned int i; + struct scatterlist *sg; + void *va = _va; + void *va_end; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + struct page *pg; + const size_t bytes = PAGE_SIZE; + + /* + * iommu 'superpage' isn't supported with 'iommu_vmalloc()' + */ + pg = vmalloc_to_page(va); + BUG_ON(!pg); + sg_set_page(sg, pg, bytes, 0); + + va += bytes; + } + + va_end = _va + PAGE_SIZE * i; + flush_cache_vmap(_va, va_end); +} + +static inline void sgtable_drain_vmalloc(struct sg_table *sgt) +{ + /* + * Actually this is not necessary at all, just exists for + * consistency of the code readibility. + */ + BUG_ON(!sgt); +} + +static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len) +{ + unsigned int i; + struct scatterlist *sg; + void *va; + + va = phys_to_virt(pa); + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + size_t bytes; + + bytes = iopgsz_max(len); + + BUG_ON(!iopgsz_ok(bytes)); + + sg_set_buf(sg, phys_to_virt(pa), bytes); + /* + * 'pa' is cotinuous(linear). + */ + pa += bytes; + len -= bytes; + } + BUG_ON(len); + + clean_dcache_area(va, len); +} + +static inline void sgtable_drain_kmalloc(struct sg_table *sgt) +{ + /* + * Actually this is not necessary at all, just exists for + * consistency of the code readibility + */ + BUG_ON(!sgt); +} + +/* create 'da' <-> 'pa' mapping from 'sgt' */ +static int map_iovm_area(struct iommu *obj, struct iovm_struct *new, + const struct sg_table *sgt, u32 flags) +{ + int err; + unsigned int i, j; + struct scatterlist *sg; + u32 da = new->da_start; + + if (!obj || !new || !sgt) + return -EINVAL; + + BUG_ON(!sgtable_ok(sgt)); + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + u32 pa; + int pgsz; + size_t bytes; + struct iotlb_entry e; + + pa = sg_phys(sg); + bytes = sg_dma_len(sg); + + flags &= ~IOVMF_PGSZ_MASK; + pgsz = bytes_to_iopgsz(bytes); + if (pgsz < 0) + goto err_out; + flags |= pgsz; + + pr_debug("%s: [%d] %08x %08x(%x)\n", __func__, + i, da, pa, bytes); + + iotlb_init_entry(&e, da, pa, flags); + err = iopgtable_store_entry(obj, &e); + if (err) + goto err_out; + + da += bytes; + } + return 0; + +err_out: + da = new->da_start; + + for_each_sg(sgt->sgl, sg, i, j) { + size_t bytes; + + bytes = iopgtable_clear_entry(obj, da); + + BUG_ON(!iopgsz_ok(bytes)); + + da += bytes; + } + return err; +} + +/* release 'da' <-> 'pa' mapping */ +static void unmap_iovm_area(struct iommu *obj, struct iovm_struct *area) +{ + u32 start; + size_t total = area->da_end - area->da_start; + + BUG_ON((!total) || !IS_ALIGNED(total, PAGE_SIZE)); + + start = area->da_start; + while (total > 0) { + size_t bytes; + + bytes = iopgtable_clear_entry(obj, start); + if (bytes == 0) + bytes = PAGE_SIZE; + else + dev_dbg(obj->dev, "%s: unmap %08x(%x) %08x\n", + __func__, start, bytes, area->flags); + + BUG_ON(!IS_ALIGNED(bytes, PAGE_SIZE)); + + total -= bytes; + start += bytes; + } + BUG_ON(total); +} + +/* template function for all unmapping */ +static struct sg_table *unmap_vm_area(struct iommu *obj, const u32 da, + void (*fn)(const void *), u32 flags) +{ + struct sg_table *sgt = NULL; + struct iovm_struct *area; + + if (!IS_ALIGNED(da, PAGE_SIZE)) { + dev_err(obj->dev, "%s: alignment err(%08x)\n", __func__, da); + return NULL; + } + + mutex_lock(&obj->mmap_lock); + + area = __find_iovm_area(obj, da); + if (!area) { + dev_dbg(obj->dev, "%s: no da area(%08x)\n", __func__, da); + goto out; + } + + if ((area->flags & flags) != flags) { + dev_err(obj->dev, "%s: wrong flags(%08x)\n", __func__, + area->flags); + goto out; + } + sgt = (struct sg_table *)area->sgt; + + unmap_iovm_area(obj, area); + + fn(area->va); + + dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n", __func__, + area->da_start, da, area->da_end, + area->da_end - area->da_start, area->flags); + + free_iovm_area(obj, area); +out: + mutex_unlock(&obj->mmap_lock); + + return sgt; +} + +static u32 map_iommu_region(struct iommu *obj, u32 da, + const struct sg_table *sgt, void *va, size_t bytes, u32 flags) +{ + int err = -ENOMEM; + struct iovm_struct *new; + + mutex_lock(&obj->mmap_lock); + + new = alloc_iovm_area(obj, da, bytes, flags); + if (IS_ERR(new)) { + err = PTR_ERR(new); + goto err_alloc_iovma; + } + new->va = va; + new->sgt = sgt; + + if (map_iovm_area(obj, new, sgt, new->flags)) + goto err_map; + + mutex_unlock(&obj->mmap_lock); + + dev_dbg(obj->dev, "%s: da:%08x(%x) flags:%08x va:%p\n", + __func__, new->da_start, bytes, new->flags, va); + + return new->da_start; + +err_map: + free_iovm_area(obj, new); +err_alloc_iovma: + mutex_unlock(&obj->mmap_lock); + return err; +} + +static inline u32 __iommu_vmap(struct iommu *obj, u32 da, + const struct sg_table *sgt, void *va, size_t bytes, u32 flags) +{ + return map_iommu_region(obj, da, sgt, va, bytes, flags); +} + +/** + * iommu_vmap - (d)-(p)-(v) address mapper + * @obj: objective iommu + * @sgt: address of scatter gather table + * @flags: iovma and page property + * + * Creates 1-n-1 mapping with given @sgt and returns @da. + * All @sgt element must be io page size aligned. + */ +u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt, + u32 flags) +{ + size_t bytes; + void *va; + + if (!obj || !obj->dev || !sgt) + return -EINVAL; + + bytes = sgtable_len(sgt); + if (!bytes) + return -EINVAL; + bytes = PAGE_ALIGN(bytes); + + va = vmap_sg(sgt); + if (IS_ERR(va)) + return PTR_ERR(va); + + flags &= IOVMF_HW_MASK; + flags |= IOVMF_DISCONT; + flags |= IOVMF_MMIO; + flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); + + da = __iommu_vmap(obj, da, sgt, va, bytes, flags); + if (IS_ERR_VALUE(da)) + vunmap_sg(va); + + return da; +} +EXPORT_SYMBOL_GPL(iommu_vmap); + +/** + * iommu_vunmap - release virtual mapping obtained by 'iommu_vmap()' + * @obj: objective iommu + * @da: iommu device virtual address + * + * Free the iommu virtually contiguous memory area starting at + * @da, which was returned by 'iommu_vmap()'. + */ +struct sg_table *iommu_vunmap(struct iommu *obj, u32 da) +{ + struct sg_table *sgt; + /* + * 'sgt' is allocated before 'iommu_vmalloc()' is called. + * Just returns 'sgt' to the caller to free + */ + sgt = unmap_vm_area(obj, da, vunmap_sg, IOVMF_DISCONT | IOVMF_MMIO); + if (!sgt) + dev_dbg(obj->dev, "%s: No sgt\n", __func__); + return sgt; +} +EXPORT_SYMBOL_GPL(iommu_vunmap); + +/** + * iommu_vmalloc - (d)-(p)-(v) address allocator and mapper + * @obj: objective iommu + * @da: contiguous iommu virtual memory + * @bytes: allocation size + * @flags: iovma and page property + * + * Allocate @bytes linearly and creates 1-n-1 mapping and returns + * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set. + */ +u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags) +{ + void *va; + struct sg_table *sgt; + + if (!obj || !obj->dev || !bytes) + return -EINVAL; + + bytes = PAGE_ALIGN(bytes); + + va = vmalloc(bytes); + if (!va) + return -ENOMEM; + + sgt = sgtable_alloc(bytes, flags); + if (IS_ERR(sgt)) { + da = PTR_ERR(sgt); + goto err_sgt_alloc; + } + sgtable_fill_vmalloc(sgt, va); + + flags &= IOVMF_HW_MASK; + flags |= IOVMF_DISCONT; + flags |= IOVMF_ALLOC; + flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); + + da = __iommu_vmap(obj, da, sgt, va, bytes, flags); + if (IS_ERR_VALUE(da)) + goto err_iommu_vmap; + + return da; + +err_iommu_vmap: + sgtable_drain_vmalloc(sgt); + sgtable_free(sgt); +err_sgt_alloc: + vfree(va); + return da; +} +EXPORT_SYMBOL_GPL(iommu_vmalloc); + +/** + * iommu_vfree - release memory allocated by 'iommu_vmalloc()' + * @obj: objective iommu + * @da: iommu device virtual address + * + * Frees the iommu virtually continuous memory area starting at + * @da, as obtained from 'iommu_vmalloc()'. + */ +void iommu_vfree(struct iommu *obj, const u32 da) +{ + struct sg_table *sgt; + + sgt = unmap_vm_area(obj, da, vfree, IOVMF_DISCONT | IOVMF_ALLOC); + if (!sgt) + dev_dbg(obj->dev, "%s: No sgt\n", __func__); + sgtable_free(sgt); +} +EXPORT_SYMBOL_GPL(iommu_vfree); + +static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va, + size_t bytes, u32 flags) +{ + struct sg_table *sgt; + + sgt = sgtable_alloc(bytes, flags); + if (IS_ERR(sgt)) + return PTR_ERR(sgt); + + sgtable_fill_kmalloc(sgt, pa, bytes); + + da = map_iommu_region(obj, da, sgt, va, bytes, flags); + if (IS_ERR_VALUE(da)) { + sgtable_drain_kmalloc(sgt); + sgtable_free(sgt); + } + + return da; +} + +/** + * iommu_kmap - (d)-(p)-(v) address mapper + * @obj: objective iommu + * @da: contiguous iommu virtual memory + * @pa: contiguous physical memory + * @flags: iovma and page property + * + * Creates 1-1-1 mapping and returns @da again, which can be + * adjusted if 'IOVMF_DA_ANON' is set. + */ +u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes, + u32 flags) +{ + void *va; + + if (!obj || !obj->dev || !bytes) + return -EINVAL; + + bytes = PAGE_ALIGN(bytes); + + va = ioremap(pa, bytes); + if (!va) + return -ENOMEM; + + flags &= IOVMF_HW_MASK; + flags |= IOVMF_LINEAR; + flags |= IOVMF_MMIO; + flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); + + da = __iommu_kmap(obj, da, pa, va, bytes, flags); + if (IS_ERR_VALUE(da)) + iounmap(va); + + return da; +} +EXPORT_SYMBOL_GPL(iommu_kmap); + +/** + * iommu_kunmap - release virtual mapping obtained by 'iommu_kmap()' + * @obj: objective iommu + * @da: iommu device virtual address + * + * Frees the iommu virtually contiguous memory area starting at + * @da, which was passed to and was returned by'iommu_kmap()'. + */ +void iommu_kunmap(struct iommu *obj, u32 da) +{ + struct sg_table *sgt; + typedef void (*func_t)(const void *); + + sgt = unmap_vm_area(obj, da, (func_t)__iounmap, + IOVMF_LINEAR | IOVMF_MMIO); + if (!sgt) + dev_dbg(obj->dev, "%s: No sgt\n", __func__); + sgtable_free(sgt); +} +EXPORT_SYMBOL_GPL(iommu_kunmap); + +/** + * iommu_kmalloc - (d)-(p)-(v) address allocator and mapper + * @obj: objective iommu + * @da: contiguous iommu virtual memory + * @bytes: bytes for allocation + * @flags: iovma and page property + * + * Allocate @bytes linearly and creates 1-1-1 mapping and returns + * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set. + */ +u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags) +{ + void *va; + u32 pa; + + if (!obj || !obj->dev || !bytes) + return -EINVAL; + + bytes = PAGE_ALIGN(bytes); + + va = kmalloc(bytes, GFP_KERNEL | GFP_DMA); + if (!va) + return -ENOMEM; + pa = virt_to_phys(va); + + flags &= IOVMF_HW_MASK; + flags |= IOVMF_LINEAR; + flags |= IOVMF_ALLOC; + flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); + + da = __iommu_kmap(obj, da, pa, va, bytes, flags); + if (IS_ERR_VALUE(da)) + kfree(va); + + return da; +} +EXPORT_SYMBOL_GPL(iommu_kmalloc); + +/** + * iommu_kfree - release virtual mapping obtained by 'iommu_kmalloc()' + * @obj: objective iommu + * @da: iommu device virtual address + * + * Frees the iommu virtually contiguous memory area starting at + * @da, which was passed to and was returned by'iommu_kmalloc()'. + */ +void iommu_kfree(struct iommu *obj, u32 da) +{ + struct sg_table *sgt; + + sgt = unmap_vm_area(obj, da, kfree, IOVMF_LINEAR | IOVMF_ALLOC); + if (!sgt) + dev_dbg(obj->dev, "%s: No sgt\n", __func__); + sgtable_free(sgt); +} +EXPORT_SYMBOL_GPL(iommu_kfree); + + +static int __init iovmm_init(void) +{ + const unsigned long flags = SLAB_HWCACHE_ALIGN; + struct kmem_cache *p; + + p = kmem_cache_create("iovm_area_cache", sizeof(struct iovm_struct), 0, + flags, NULL); + if (!p) + return -ENOMEM; + iovm_area_cachep = p; + + return 0; +} +module_init(iovmm_init); + +static void __exit iovmm_exit(void) +{ + kmem_cache_destroy(iovm_area_cachep); +} +module_exit(iovmm_exit); + +MODULE_DESCRIPTION("omap iommu: simple virtual address space management"); +MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 28b0a82..efa0e01 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -91,11 +91,20 @@ static void omap_mcbsp_dump_reg(u8 id) static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) { struct omap_mcbsp *mcbsp_tx = dev_id; + u16 irqst_spcr2; - dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", - OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2)); + irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2); + dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2); - complete(&mcbsp_tx->tx_irq_completion); + if (irqst_spcr2 & XSYNC_ERR) { + dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n", + irqst_spcr2); + /* Writing zero to XSYNC_ERR clears the IRQ */ + OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2, + irqst_spcr2 & ~(XSYNC_ERR)); + } else { + complete(&mcbsp_tx->tx_irq_completion); + } return IRQ_HANDLED; } @@ -103,11 +112,20 @@ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id) { struct omap_mcbsp *mcbsp_rx = dev_id; + u16 irqst_spcr1; - dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", - OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2)); + irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1); + dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1); - complete(&mcbsp_rx->rx_irq_completion); + if (irqst_spcr1 & RSYNC_ERR) { + dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n", + irqst_spcr1); + /* Writing zero to RSYNC_ERR clears the IRQ */ + OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1, + irqst_spcr1 & ~(RSYNC_ERR)); + } else { + complete(&mcbsp_rx->tx_irq_completion); + } return IRQ_HANDLED; } diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c index 80b040f..8d329fb 100644 --- a/arch/arm/plat-omap/mux.c +++ b/arch/arm/plat-omap/mux.c @@ -54,6 +54,9 @@ int __init_or_module omap_cfg_reg(const unsigned long index) { struct pin_config *reg; + if (cpu_is_omap44xx()) + return 0; + if (mux_cfg == NULL) { printk(KERN_ERR "Pin mux table not initialized\n"); return -ENODEV; diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index fa5297d..a5b9bcd 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -6,6 +6,9 @@ * Copyright (C) 2005 Nokia Corporation * Written by Tony Lindgren <tony@atomide.com> * + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -38,12 +41,14 @@ #define OMAP1_SRAM_VA VMALLOC_END #define OMAP2_SRAM_PA 0x40200000 #define OMAP2_SRAM_PUB_PA 0x4020f800 -#define OMAP2_SRAM_VA VMALLOC_END -#define OMAP2_SRAM_PUB_VA (VMALLOC_END + 0x800) +#define OMAP2_SRAM_VA 0xe3000000 +#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800) #define OMAP3_SRAM_PA 0x40200000 #define OMAP3_SRAM_VA 0xd7000000 #define OMAP3_SRAM_PUB_PA 0x40208000 #define OMAP3_SRAM_PUB_VA 0xd7008000 +#define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/ +#define OMAP4_SRAM_VA 0xd7000000 /*0xd70f0000*/ #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) #define SRAM_BOOTLOADER_SZ 0x00 @@ -87,6 +92,10 @@ static int is_sram_locked(void) { int type = 0; + if (cpu_is_omap44xx()) + /* Not yet supported */ + return 0; + if (cpu_is_omap242x()) type = omap_rev() & OMAP2_DEVICETYPE_MASK; @@ -135,6 +144,10 @@ void __init omap_detect_sram(void) omap_sram_base = OMAP3_SRAM_VA; omap_sram_start = OMAP3_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ + } else if (cpu_is_omap44xx()) { + omap_sram_base = OMAP4_SRAM_VA; + omap_sram_start = OMAP4_SRAM_PA; + omap_sram_size = 0x8000; /* 32K */ } else { omap_sram_base = OMAP2_SRAM_VA; omap_sram_start = OMAP2_SRAM_PA; @@ -201,8 +214,23 @@ void __init omap_map_sram(void) base = OMAP3_SRAM_PA; base = ROUND_DOWN(base, PAGE_SIZE); omap_sram_io_desc[0].pfn = __phys_to_pfn(base); + + /* + * SRAM must be marked as non-cached on OMAP3 since the + * CORE DPLL M2 divider change code (in SRAM) runs with the + * SDRAM controller disabled, and if it is marked cached, + * the ARM may attempt to write cache lines back to SDRAM + * which will cause the system to hang. + */ + omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED; } + if (cpu_is_omap44xx()) { + omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA; + base = OMAP4_SRAM_PA; + base = ROUND_DOWN(base, PAGE_SIZE); + omap_sram_io_desc[0].pfn = __phys_to_pfn(base); + } omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */ iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); @@ -242,20 +270,13 @@ void * omap_sram_push(void * start, unsigned long size) return (void *)omap_sram_ceil; } -static void omap_sram_error(void) -{ - panic("Uninitialized SRAM function\n"); -} - #ifdef CONFIG_ARCH_OMAP1 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) { - if (!_omap_sram_reprogram_clock) - omap_sram_error(); - + BUG_ON(!_omap_sram_reprogram_clock); _omap_sram_reprogram_clock(dpllctl, ckctl); } @@ -280,9 +301,7 @@ static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, u32 base_cs, u32 force_unlock) { - if (!_omap2_sram_ddr_init) - omap_sram_error(); - + BUG_ON(!_omap2_sram_ddr_init); _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl, base_cs, force_unlock); } @@ -292,9 +311,7 @@ static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val, void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type) { - if (!_omap2_sram_reprogram_sdrc) - omap_sram_error(); - + BUG_ON(!_omap2_sram_reprogram_sdrc); _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type); } @@ -302,9 +319,7 @@ static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) { - if (!_omap2_set_prcm) - omap_sram_error(); - + BUG_ON(!_omap2_set_prcm); return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); } #endif @@ -356,16 +371,15 @@ static inline int omap243x_sram_init(void) static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, - u32 m2); + u32 m2, u32 unlock_dll); u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, - u32 sdrc_actim_ctrlb, u32 m2) + u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll) { - if (!_omap3_sram_configure_core_dpll) - omap_sram_error(); - + BUG_ON(!_omap3_sram_configure_core_dpll); return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, sdrc_actim_ctrla, - sdrc_actim_ctrlb, m2); + sdrc_actim_ctrlb, m2, + unlock_dll); } /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ @@ -406,6 +420,8 @@ int __init omap_sram_init(void) omap243x_sram_init(); else if (cpu_is_omap34xx()) omap34xx_sram_init(); + else if (cpu_is_omap44xx()) + omap34xx_sram_init(); /* FIXME: */ return 0; } |
