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-rw-r--r--arch/arm/mm/cache-v7.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 6136e68..dc18d81 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -96,7 +96,7 @@ ENDPROC(v7_flush_dcache_all)
* Flush the entire cache system.
* The data cache flush is now achieved using atomic clean / invalidates
* working outwards from L1 cache. This is done using Set/Way based cache
- * maintainance instructions.
+ * maintenance instructions.
* The instruction cache can still be invalidated back to the point of
* unification in a single instruction.
*
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