diff options
Diffstat (limited to 'arch/arm/mach-zynq/slcr.c')
| -rw-r--r-- | arch/arm/mach-zynq/slcr.c | 45 |
1 files changed, 17 insertions, 28 deletions
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index 50d008d..1836d5a 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -14,32 +14,21 @@ * 02139, USA. */ -#include <linux/export.h> #include <linux/io.h> -#include <linux/fs.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> #include <linux/of_address.h> -#include <linux/uaccess.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/string.h> #include <linux/clk/zynq.h> #include "common.h" -#define SLCR_UNLOCK_MAGIC 0xDF0D -#define SLCR_UNLOCK 0x8 /* SCLR unlock register */ - +/* register offsets */ +#define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */ #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ +#define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */ +#define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */ +#define SLCR_UNLOCK_MAGIC 0xDF0D #define SLCR_A9_CPU_CLKSTOP 0x10 #define SLCR_A9_CPU_RST 0x1 -#define SLCR_A9_CPU_RST_CTRL 0x244 /* CPU Software Reset Control */ -#define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */ - void __iomem *zynq_slcr_base; /** @@ -54,15 +43,15 @@ void zynq_slcr_system_reset(void) * Note that this seems to require raw i/o * functions or there's a lockup? */ - writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); + writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET); /* * Clear 0x0F000000 bits of reboot status register to workaround * the FSBL not loading the bitstream after soft-reboot * This is a temporary solution until we know more. */ - reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS); - writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS); + reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); + writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET); } @@ -72,11 +61,11 @@ void zynq_slcr_system_reset(void) */ void zynq_slcr_cpu_start(int cpu) { - /* enable CPUn */ - writel(SLCR_A9_CPU_CLKSTOP << cpu, - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); - /* enable CLK for CPUn */ - writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + reg &= ~(SLCR_A9_CPU_RST << cpu); + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); } /** @@ -85,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu) */ void zynq_slcr_cpu_stop(int cpu) { - /* stop CLK and reset CPUn */ - writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu, - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); + u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); + reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; + writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); } /** @@ -113,7 +102,7 @@ int __init zynq_slcr_init(void) } /* unlock the SLCR so that registers can be changed */ - writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); + writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET); pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); |
