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-rw-r--r--arch/arm/mach-omap2/clock.c13
-rw-r--r--arch/arm/mach-omap2/serial.c2
2 files changed, 3 insertions, 12 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 588adb5..d9af436 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -1160,8 +1160,8 @@ int __init omap2_clk_init(void)
clk_enable(&sync_32k_ick);
clk_enable(&omapctrl_ick);
- /* Force the APLLs active during bootup to avoid disabling and
- * enabling them unnecessarily. */
+ /* Force the APLLs always active. The clocks are idled
+ * automatically by hardware. */
clk_enable(&apll96_ck);
clk_enable(&apll54_ck);
@@ -1174,12 +1174,3 @@ int __init omap2_clk_init(void)
return 0;
}
-
-static int __init omap2_disable_aplls(void)
-{
- clk_disable(&apll96_ck);
- clk_disable(&apll54_ck);
-
- return 0;
-}
-late_initcall(omap2_disable_aplls);
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index aaa5589..e9c367f 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -84,7 +84,7 @@ static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
serial_write_reg(p, UART_OMAP_MDR1, 0x07);
serial_write_reg(p, UART_OMAP_SCR, 0x08);
serial_write_reg(p, UART_OMAP_MDR1, 0x00);
- serial_write_reg(p, UART_OMAP_SYSC, 0x01);
+ serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
}
void __init omap_serial_init()
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