diff options
Diffstat (limited to 'arch/arm/mach-omap2/id.c')
| -rw-r--r-- | arch/arm/mach-omap2/id.c | 305 |
1 files changed, 133 insertions, 172 deletions
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index bf45ff3..b0f8e7d 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -22,40 +22,15 @@ #include <mach/control.h> #include <mach/cpu.h> -static u32 class; -static void __iomem *tap_base; -static u16 tap_prod_id; - -#define OMAP_TAP_IDCODE 0x0204 -#define OMAP_TAP_DIE_ID_0 0x0218 -#define OMAP_TAP_DIE_ID_1 0x021C -#define OMAP_TAP_DIE_ID_2 0x0220 -#define OMAP_TAP_DIE_ID_3 0x0224 - -/* system_rev fields for OMAP2 processors: - * CPU id bits [31:16], - * CPU device type [15:12], (unprg,normal,POP) - * CPU revision [11:08] - * CPU class bits [07:00] - */ - -struct omap_id { - u16 hawkeye; /* Silicon type (Hawkeye id) */ - u8 dev; /* Device type from production_id reg */ - u32 type; /* combined type id copied to system_rev */ -}; +static struct omap_chip_id omap_chip; +static unsigned int omap_revision; -/* Register values to detect the OMAP version */ -static struct omap_id omap_ids[] __initdata = { - { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 }, - { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 }, - { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 }, - { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 }, - { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 }, - { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 }, -}; -static struct omap_chip_id omap_chip; +unsigned int omap_rev(void) +{ + return omap_revision; +} +EXPORT_SYMBOL(omap_rev); /** * omap_chip_is - test whether currently running OMAP matches a chip type @@ -70,135 +45,41 @@ int omap_chip_is(struct omap_chip_id oci) } EXPORT_SYMBOL(omap_chip_is); -static u32 __init read_tap_reg(int reg) -{ - unsigned int regval = 0; - u32 cpuid; - - /* Reading the IDCODE register on 3430 ES1 results in a - * data abort as the register is not exposed on the OCP - * Hence reading the Cortex Rev - */ - cpuid = read_cpuid(CPUID_ID); - - /* If the processor type is Cortex-A8 and the revision is 0x0 - * it means its Cortex r0p0 which is 3430 ES1 - */ - if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) { - - if (reg == tap_prod_id) { - regval = 0x000F00F0; - goto out; - } - - switch (reg) { - case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break; - /* Making DevType as 0xF in ES1 to differ from ES2 */ - case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break; - case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break; - case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break; - case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break; - } - } else - regval = __raw_readl(tap_base + reg); - -out: - return regval; - -} +/*----------------------------------------------------------------------------*/ -/* - * _set_system_rev - set the system_rev global based on current OMAP chip type - * - * Set the system_rev global. This is primarily used by the cpu_is_omapxxxx() - * macros. - */ -static void __init _set_system_rev(u32 type, u8 rev) -{ - u32 i, ctrl_status; - - /* - * system_rev encoding is as follows - * system_rev & 0xff000000 -> Omap Class (24xx/34xx) - * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x) - * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430) - * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 ) - * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD ) - * system_rev & 0x000000c0 -> IDCODE revision[6:7] - * system_rev & 0x0000003f -> sys_boot[0:5] - */ - /* Embedding the ES revision info in type field */ - system_rev = type; - /* Also add IDCODE revision info only two lower bits */ - system_rev |= ((rev & 0x3) << 6); - - /* Add in the device type and sys_boot fields (see above) */ - if (cpu_is_omap24xx()) { - i = OMAP24XX_CONTROL_STATUS; - } else if (cpu_is_omap343x()) { - i = OMAP343X_CONTROL_STATUS; - } else { - printk(KERN_ERR "id: unknown CPU type\n"); - BUG(); - } - ctrl_status = omap_ctrl_readl(i); - system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK | - OMAP2_SYSBOOT_4_MASK | - OMAP2_SYSBOOT_3_MASK | - OMAP2_SYSBOOT_2_MASK | - OMAP2_SYSBOOT_1_MASK | - OMAP2_SYSBOOT_0_MASK)); - system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK); -} - - -/* - * _set_omap_chip - set the omap_chip global based on OMAP chip type - * - * Build the omap_chip bits. This variable is used by powerdomain and - * clockdomain code to indicate whether structures are applicable for - * the current OMAP chip type by ANDing it against a 'platform' bitfield - * in the structure. - */ -static void __init _set_omap_chip(void) -{ - if (cpu_is_omap343x()) { - - omap_chip.oc = CHIP_IS_OMAP3430; - if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) - omap_chip.oc |= CHIP_IS_OMAP3430ES1; - else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) - omap_chip.oc |= CHIP_IS_OMAP3430ES2; - - } else if (cpu_is_omap243x()) { - - /* Currently only supports 2430ES2.1 and 2430-all */ - omap_chip.oc |= CHIP_IS_OMAP2430; - - } else if (cpu_is_omap242x()) { - - /* Currently only supports 2420ES2.1.1 and 2420-all */ - omap_chip.oc |= CHIP_IS_OMAP2420; +#define OMAP_TAP_IDCODE 0x0204 +#define OMAP_TAP_DIE_ID_0 0x0218 +#define OMAP_TAP_DIE_ID_1 0x021C +#define OMAP_TAP_DIE_ID_2 0x0220 +#define OMAP_TAP_DIE_ID_3 0x0224 - } else { +#define read_tap_reg(reg) __raw_readl(tap_base + (reg)) - /* Current CPU not supported by this code. */ - printk(KERN_WARNING "OMAP chip type code does not yet support " - "this CPU type.\n"); - WARN_ON(1); +struct omap_id { + u16 hawkeye; /* Silicon type (Hawkeye id) */ + u8 dev; /* Device type from production_id reg */ + u32 type; /* Combined type id copied to omap_revision */ +}; - } +/* Register values to detect the OMAP version */ +static struct omap_id omap_ids[] __initdata = { + { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, + { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, + { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, + { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, + { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, + { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, +}; -} +static void __iomem *tap_base; +static u16 tap_prod_id; -void __init omap2_check_revision(void) +void __init omap24xx_check_revision(void) { int i, j; - u32 idcode; - u32 prod_id; + u32 idcode, prod_id; u16 hawkeye; - u8 dev_type; - u8 rev; + u8 dev_type, rev; idcode = read_tap_reg(OMAP_TAP_IDCODE); prod_id = read_tap_reg(tap_prod_id); @@ -220,18 +101,6 @@ void __init omap2_check_revision(void) pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", prod_id, dev_type); - /* - * Detection for 34xx ES2.0 and above can be done with just - * hawkeye and rev. See TRM 1.5.2 Device Identification. - * Note that rev cannot be used directly as ES1.0 uses value 0. - */ - if (hawkeye == 0xb7ae) { - system_rev = 0x34300000 | ((1 + rev) << 12); - pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev); - _set_omap_chip(); - return; - } - /* Check hawkeye ids */ for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { if (hawkeye == omap_ids[i].hawkeye) @@ -255,23 +124,115 @@ void __init omap2_check_revision(void) j = i; } - _set_system_rev(omap_ids[j].type, rev); + pr_info("OMAP%04x", omap_rev() >> 16); + if ((omap_rev() >> 8) & 0x0f) + pr_info("ES%x", (omap_rev() >> 12) & 0xf); + pr_info("\n"); +} - _set_omap_chip(); +void __init omap34xx_check_revision(void) +{ + u32 cpuid, idcode; + u16 hawkeye; + u8 rev; + char *rev_name = "ES1.0"; - pr_info("OMAP%04x", system_rev >> 16); - if ((system_rev >> 8) & 0x0f) - pr_info("ES%x", (system_rev >> 12) & 0xf); - pr_info("\n"); + /* + * We cannot access revision registers on ES1.0. + * If the processor type is Cortex-A8 and the revision is 0x0 + * it means its Cortex r0p0 which is 3430 ES1.0. + */ + cpuid = read_cpuid(CPUID_ID); + if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { + omap_revision = OMAP3430_REV_ES1_0; + goto out; + } + /* + * Detection for 34xx ES2.0 and above can be done with just + * hawkeye and rev. See TRM 1.5.2 Device Identification. + * Note that rev does not map directly to our defined processor + * revision numbers as ES1.0 uses value 0. + */ + idcode = read_tap_reg(OMAP_TAP_IDCODE); + hawkeye = (idcode >> 12) & 0xffff; + rev = (idcode >> 28) & 0xff; + + if (hawkeye == 0xb7ae) { + switch (rev) { + case 0: + omap_revision = OMAP3430_REV_ES2_0; + rev_name = "ES2.0"; + break; + case 2: + omap_revision = OMAP3430_REV_ES2_1; + rev_name = "ES2.1"; + break; + case 3: + omap_revision = OMAP3430_REV_ES3_0; + rev_name = "ES3.0"; + break; + default: + /* Use the latest known revision as default */ + omap_revision = OMAP3430_REV_ES3_0; + rev_name = "Unknown revision\n"; + } + } + +out: + pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); } +/* + * Try to detect the exact revision of the omap we're running on + */ +void __init omap2_check_revision(void) +{ + /* + * At this point we have an idea about the processor revision set + * earlier with omap2_set_globals_tap(). + */ + if (cpu_is_omap24xx()) + omap24xx_check_revision(); + else if (cpu_is_omap34xx()) + omap34xx_check_revision(); + else + pr_err("OMAP revision unknown, please fix!\n"); + + /* + * OK, now we know the exact revision. Initialize omap_chip bits + * for powerdowmain and clockdomain code. + */ + if (cpu_is_omap243x()) { + /* Currently only supports 2430ES2.1 and 2430-all */ + omap_chip.oc |= CHIP_IS_OMAP2430; + } else if (cpu_is_omap242x()) { + /* Currently only supports 2420ES2.1.1 and 2420-all */ + omap_chip.oc |= CHIP_IS_OMAP2420; + } else if (cpu_is_omap343x()) { + omap_chip.oc = CHIP_IS_OMAP3430; + if (omap_rev() == OMAP3430_REV_ES1_0) + omap_chip.oc |= CHIP_IS_OMAP3430ES1; + else if (omap_rev() > OMAP3430_REV_ES1_0) + omap_chip.oc |= CHIP_IS_OMAP3430ES2; + } else { + pr_err("Uninitialized omap_chip, please fix!\n"); + } +} + +/* + * Set up things for map_io and processor detection later on. Gets called + * pretty much first thing from board init. For multi-omap, this gets + * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to + * detect the exact revision later on in omap2_detect_revision() once map_io + * is done. + */ void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) { - class = omap2_globals->class; + omap_revision = omap2_globals->class; tap_base = omap2_globals->tap; - if (class == 0x3430) + if (cpu_is_omap34xx()) tap_prod_id = 0x0210; else tap_prod_id = 0x0208; |
