diff options
Diffstat (limited to 'arch/arm/mach-mx2/devices.c')
| -rw-r--r-- | arch/arm/mach-mx2/devices.c | 332 |
1 files changed, 225 insertions, 107 deletions
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index a0f1b36..50199af 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -40,45 +40,87 @@ #include "devices.h" /* - * Resource definition for the MXC IrDA + * SPI master controller + * + * - i.MX1: 2 channel (slighly different register setting) + * - i.MX21: 2 channel + * - i.MX27: 3 channel */ -static struct resource mxc_irda_resources[] = { - [0] = { - .start = UART3_BASE_ADDR, - .end = UART3_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, +static struct resource mxc_spi_resources0[] = { + { + .start = CSPI1_BASE_ADDR, + .end = CSPI1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_CSPI1, + .end = MXC_INT_CSPI1, + .flags = IORESOURCE_IRQ, }, - [1] = { - .start = MXC_INT_UART3, - .end = MXC_INT_UART3, - .flags = IORESOURCE_IRQ, +}; + +static struct resource mxc_spi_resources1[] = { + { + .start = CSPI2_BASE_ADDR, + .end = CSPI2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_CSPI2, + .end = MXC_INT_CSPI2, + .flags = IORESOURCE_IRQ, }, }; -/* Platform Data for MXC IrDA */ -struct platform_device mxc_irda_device = { - .name = "mxc_irda", +#ifdef CONFIG_MACH_MX27 +static struct resource mxc_spi_resources2[] = { + { + .start = CSPI3_BASE_ADDR, + .end = CSPI3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_CSPI3, + .end = MXC_INT_CSPI3, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + +struct platform_device mxc_spi_device0 = { + .name = "spi_imx", .id = 0, - .num_resources = ARRAY_SIZE(mxc_irda_resources), - .resource = mxc_irda_resources, + .num_resources = ARRAY_SIZE(mxc_spi_resources0), + .resource = mxc_spi_resources0, +}; + +struct platform_device mxc_spi_device1 = { + .name = "spi_imx", + .id = 1, + .num_resources = ARRAY_SIZE(mxc_spi_resources1), + .resource = mxc_spi_resources1, +}; + +#ifdef CONFIG_MACH_MX27 +struct platform_device mxc_spi_device2 = { + .name = "spi_imx", + .id = 2, + .num_resources = ARRAY_SIZE(mxc_spi_resources2), + .resource = mxc_spi_resources2, }; +#endif /* * General Purpose Timer - * - i.MX1: 2 timer (slighly different register handling) - * - i.MX21: 3 timer - * - i.MX27: 6 timer + * - i.MX21: 3 timers + * - i.MX27: 6 timers */ /* We use gpt0 as system timer, so do not add a device for this one */ static struct resource timer1_resources[] = { - [0] = { + { .start = GPT2_BASE_ADDR, .end = GPT2_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM - }, - [1] = { + .flags = IORESOURCE_MEM, + }, { .start = MXC_INT_GPT2, .end = MXC_INT_GPT2, .flags = IORESOURCE_IRQ, @@ -89,16 +131,15 @@ struct platform_device mxc_gpt1 = { .name = "imx_gpt", .id = 1, .num_resources = ARRAY_SIZE(timer1_resources), - .resource = timer1_resources + .resource = timer1_resources, }; static struct resource timer2_resources[] = { - [0] = { + { .start = GPT3_BASE_ADDR, .end = GPT3_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM - }, - [1] = { + .flags = IORESOURCE_MEM, + }, { .start = MXC_INT_GPT3, .end = MXC_INT_GPT3, .flags = IORESOURCE_IRQ, @@ -109,17 +150,16 @@ struct platform_device mxc_gpt2 = { .name = "imx_gpt", .id = 2, .num_resources = ARRAY_SIZE(timer2_resources), - .resource = timer2_resources + .resource = timer2_resources, }; #ifdef CONFIG_MACH_MX27 static struct resource timer3_resources[] = { - [0] = { + { .start = GPT4_BASE_ADDR, .end = GPT4_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM - }, - [1] = { + .flags = IORESOURCE_MEM, + }, { .start = MXC_INT_GPT4, .end = MXC_INT_GPT4, .flags = IORESOURCE_IRQ, @@ -130,16 +170,15 @@ struct platform_device mxc_gpt3 = { .name = "imx_gpt", .id = 3, .num_resources = ARRAY_SIZE(timer3_resources), - .resource = timer3_resources + .resource = timer3_resources, }; static struct resource timer4_resources[] = { - [0] = { + { .start = GPT5_BASE_ADDR, .end = GPT5_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM - }, - [1] = { + .flags = IORESOURCE_MEM, + }, { .start = MXC_INT_GPT5, .end = MXC_INT_GPT5, .flags = IORESOURCE_IRQ, @@ -150,16 +189,15 @@ struct platform_device mxc_gpt4 = { .name = "imx_gpt", .id = 4, .num_resources = ARRAY_SIZE(timer4_resources), - .resource = timer4_resources + .resource = timer4_resources, }; static struct resource timer5_resources[] = { - [0] = { + { .start = GPT6_BASE_ADDR, .end = GPT6_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM - }, - [1] = { + .flags = IORESOURCE_MEM, + }, { .start = MXC_INT_GPT6, .end = MXC_INT_GPT6, .flags = IORESOURCE_IRQ, @@ -170,7 +208,7 @@ struct platform_device mxc_gpt5 = { .name = "imx_gpt", .id = 5, .num_resources = ARRAY_SIZE(timer5_resources), - .resource = timer5_resources + .resource = timer5_resources, }; #endif @@ -214,11 +252,11 @@ static struct resource mxc_nand_resources[] = { { .start = NFC_BASE_ADDR, .end = NFC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM + .flags = IORESOURCE_MEM, }, { .start = MXC_INT_NANDFC, .end = MXC_INT_NANDFC, - .flags = IORESOURCE_IRQ + .flags = IORESOURCE_IRQ, }, }; @@ -240,8 +278,7 @@ static struct resource mxc_fb[] = { .start = LCDC_BASE_ADDR, .end = LCDC_BASE_ADDR + 0xFFF, .flags = IORESOURCE_MEM, - }, - { + }, { .start = MXC_INT_LCDC, .end = MXC_INT_LCDC, .flags = IORESOURCE_IRQ, @@ -264,11 +301,11 @@ static struct resource mxc_fec_resources[] = { { .start = FEC_BASE_ADDR, .end = FEC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM + .flags = IORESOURCE_MEM, }, { .start = MXC_INT_FEC, .end = MXC_INT_FEC, - .flags = IORESOURCE_IRQ + .flags = IORESOURCE_IRQ, }, }; @@ -281,15 +318,14 @@ struct platform_device mxc_fec_device = { #endif static struct resource mxc_i2c_1_resources[] = { - [0] = { + { .start = I2C_BASE_ADDR, .end = I2C_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM - }, - [1] = { + .flags = IORESOURCE_MEM, + }, { .start = MXC_INT_I2C, .end = MXC_INT_I2C, - .flags = IORESOURCE_IRQ + .flags = IORESOURCE_IRQ, } }; @@ -297,20 +333,19 @@ struct platform_device mxc_i2c_device0 = { .name = "imx-i2c", .id = 0, .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), - .resource = mxc_i2c_1_resources + .resource = mxc_i2c_1_resources, }; #ifdef CONFIG_MACH_MX27 static struct resource mxc_i2c_2_resources[] = { - [0] = { + { .start = I2C2_BASE_ADDR, .end = I2C2_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM - }, - [1] = { + .flags = IORESOURCE_MEM, + }, { .start = MXC_INT_I2C2, .end = MXC_INT_I2C2, - .flags = IORESOURCE_IRQ + .flags = IORESOURCE_IRQ, } }; @@ -318,17 +353,16 @@ struct platform_device mxc_i2c_device1 = { .name = "imx-i2c", .id = 1, .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), - .resource = mxc_i2c_2_resources + .resource = mxc_i2c_2_resources, }; #endif static struct resource mxc_pwm_resources[] = { - [0] = { + { .start = PWM_BASE_ADDR, .end = PWM_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM - }, - [1] = { + .flags = IORESOURCE_MEM, + }, { .start = MXC_INT_PWM, .end = MXC_INT_PWM, .flags = IORESOURCE_IRQ, @@ -339,28 +373,26 @@ struct platform_device mxc_pwm_device = { .name = "mxc_pwm", .id = 0, .num_resources = ARRAY_SIZE(mxc_pwm_resources), - .resource = mxc_pwm_resources + .resource = mxc_pwm_resources, }; /* * Resource definition for the MXC SDHC */ static struct resource mxc_sdhc1_resources[] = { - [0] = { - .start = SDHC1_BASE_ADDR, - .end = SDHC1_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = MXC_INT_SDHC1, - .end = MXC_INT_SDHC1, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = DMA_REQ_SDHC1, - .end = DMA_REQ_SDHC1, - .flags = IORESOURCE_DMA - }, + { + .start = SDHC1_BASE_ADDR, + .end = SDHC1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_SDHC1, + .end = MXC_INT_SDHC1, + .flags = IORESOURCE_IRQ, + }, { + .start = DMA_REQ_SDHC1, + .end = DMA_REQ_SDHC1, + .flags = IORESOURCE_DMA, + }, }; static u64 mxc_sdhc1_dmamask = 0xffffffffUL; @@ -377,21 +409,19 @@ struct platform_device mxc_sdhc_device0 = { }; static struct resource mxc_sdhc2_resources[] = { - [0] = { - .start = SDHC2_BASE_ADDR, - .end = SDHC2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = MXC_INT_SDHC2, - .end = MXC_INT_SDHC2, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = DMA_REQ_SDHC2, - .end = DMA_REQ_SDHC2, - .flags = IORESOURCE_DMA - }, + { + .start = SDHC2_BASE_ADDR, + .end = SDHC2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_SDHC2, + .end = MXC_INT_SDHC2, + .flags = IORESOURCE_IRQ, + }, { + .start = DMA_REQ_SDHC2, + .end = DMA_REQ_SDHC2, + .flags = IORESOURCE_DMA, + }, }; static u64 mxc_sdhc2_dmamask = 0xffffffffUL; @@ -407,35 +437,123 @@ struct platform_device mxc_sdhc_device1 = { .resource = mxc_sdhc2_resources, }; +#ifdef CONFIG_MACH_MX27 +static struct resource otg_resources[] = { + { + .start = OTG_BASE_ADDR, + .end = OTG_BASE_ADDR + 0x1ff, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_USB3, + .end = MXC_INT_USB3, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 otg_dmamask = 0xffffffffUL; + +/* OTG gadget device */ +struct platform_device mxc_otg_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .dma_mask = &otg_dmamask, + .coherent_dma_mask = 0xffffffffUL, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +/* OTG host */ +struct platform_device mxc_otg_host = { + .name = "mxc-ehci", + .id = 0, + .dev = { + .coherent_dma_mask = 0xffffffff, + .dma_mask = &otg_dmamask, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +/* USB host 1 */ + +static u64 usbh1_dmamask = 0xffffffffUL; + +static struct resource mxc_usbh1_resources[] = { + { + .start = OTG_BASE_ADDR + 0x200, + .end = OTG_BASE_ADDR + 0x3ff, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_USB1, + .end = MXC_INT_USB1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_usbh1 = { + .name = "mxc-ehci", + .id = 1, + .dev = { + .coherent_dma_mask = 0xffffffff, + .dma_mask = &usbh1_dmamask, + }, + .resource = mxc_usbh1_resources, + .num_resources = ARRAY_SIZE(mxc_usbh1_resources), +}; + +/* USB host 2 */ +static u64 usbh2_dmamask = 0xffffffffUL; + +static struct resource mxc_usbh2_resources[] = { + { + .start = OTG_BASE_ADDR + 0x400, + .end = OTG_BASE_ADDR + 0x5ff, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_USB2, + .end = MXC_INT_USB2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_usbh2 = { + .name = "mxc-ehci", + .id = 2, + .dev = { + .coherent_dma_mask = 0xffffffff, + .dma_mask = &usbh2_dmamask, + }, + .resource = mxc_usbh2_resources, + .num_resources = ARRAY_SIZE(mxc_usbh2_resources), +}; +#endif + /* GPIO port description */ static struct mxc_gpio_port imx_gpio_ports[] = { - [0] = { + { .chip.label = "gpio-0", .irq = MXC_INT_GPIO, .base = IO_ADDRESS(GPIO_BASE_ADDR), .virtual_irq_start = MXC_GPIO_IRQ_START, - }, - [1] = { + }, { .chip.label = "gpio-1", .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, - [2] = { + }, { .chip.label = "gpio-2", .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - }, - [3] = { + }, { .chip.label = "gpio-3", .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), .virtual_irq_start = MXC_GPIO_IRQ_START + 96, - }, - [4] = { + }, { .chip.label = "gpio-4", .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), .virtual_irq_start = MXC_GPIO_IRQ_START + 128, - }, - [5] = { + }, { .chip.label = "gpio-5", .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), .virtual_irq_start = MXC_GPIO_IRQ_START + 160, |
