diff options
Diffstat (limited to 'arch/arm/mach-kirkwood')
| -rw-r--r-- | arch/arm/mach-kirkwood/board-dt.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-kirkwood/common.c | 26 | ||||
| -rw-r--r-- | arch/arm/mach-kirkwood/pcie.c | 40 |
3 files changed, 43 insertions, 24 deletions
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 6e122ed..682b7ac 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -87,6 +87,7 @@ static void __init kirkwood_dt_init(void) */ writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); + BUG_ON(mvebu_mbus_dt_init()); kirkwood_setup_wins(); kirkwood_l2_init(); diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 1663de0..1767611 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -37,6 +37,12 @@ #include <linux/platform_data/dma-mv_xor.h> #include "common.h" +/* These can go away once Kirkwood uses the mvebu-mbus DT binding */ +#define KIRKWOOD_MBUS_NAND_TARGET 0x01 +#define KIRKWOOD_MBUS_NAND_ATTR 0x2f +#define KIRKWOOD_MBUS_SRAM_TARGET 0x03 +#define KIRKWOOD_MBUS_SRAM_ATTR 0x01 + /***************************************************************************** * I/O Address Mapping ****************************************************************************/ @@ -528,10 +534,6 @@ void __init kirkwood_cpuidle_init(void) void __init kirkwood_init_early(void) { orion_time_set_base(TIMER_VIRT_BASE); - - mvebu_mbus_init("marvell,kirkwood-mbus", - BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, - DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ); } int kirkwood_tclk; @@ -666,10 +668,14 @@ char * __init kirkwood_id(void) void __init kirkwood_setup_wins(void) { - mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE, - KIRKWOOD_NAND_MEM_SIZE); - mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE, - KIRKWOOD_SRAM_SIZE); + mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_NAND_TARGET, + KIRKWOOD_MBUS_NAND_ATTR, + KIRKWOOD_NAND_MEM_PHYS_BASE, + KIRKWOOD_NAND_MEM_SIZE); + mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_SRAM_TARGET, + KIRKWOOD_MBUS_SRAM_ATTR, + KIRKWOOD_SRAM_PHYS_BASE, + KIRKWOOD_SRAM_SIZE); } void __init kirkwood_l2_init(void) @@ -697,6 +703,10 @@ void __init kirkwood_init(void) */ writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); + BUG_ON(mvebu_mbus_init("marvell,kirkwood-mbus", + BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, + DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ)); + kirkwood_setup_wins(); kirkwood_l2_init(); diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index ddcb09f..12d86f3 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -20,6 +20,16 @@ #include <mach/bridge-regs.h> #include "common.h" +/* These can go away once Kirkwood uses the mvebu-mbus DT binding */ +#define KIRKWOOD_MBUS_PCIE0_MEM_TARGET 0x4 +#define KIRKWOOD_MBUS_PCIE0_MEM_ATTR 0xe8 +#define KIRKWOOD_MBUS_PCIE0_IO_TARGET 0x4 +#define KIRKWOOD_MBUS_PCIE0_IO_ATTR 0xe0 +#define KIRKWOOD_MBUS_PCIE1_MEM_TARGET 0x4 +#define KIRKWOOD_MBUS_PCIE1_MEM_ATTR 0xd8 +#define KIRKWOOD_MBUS_PCIE1_IO_TARGET 0x4 +#define KIRKWOOD_MBUS_PCIE1_IO_ATTR 0xd0 + static void kirkwood_enable_pcie_clk(const char *port) { struct clk *clk; @@ -254,26 +264,24 @@ static void __init add_pcie_port(int index, void __iomem *base) void __init kirkwood_pcie_init(unsigned int portmask) { - mvebu_mbus_add_window_remap_flags("pcie0.0", + mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE0_IO_TARGET, + KIRKWOOD_MBUS_PCIE0_IO_ATTR, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, - KIRKWOOD_PCIE_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pcie0.0", - KIRKWOOD_PCIE_MEM_PHYS_BASE, - KIRKWOOD_PCIE_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); - mvebu_mbus_add_window_remap_flags("pcie1.0", + KIRKWOOD_PCIE_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE0_MEM_TARGET, + KIRKWOOD_MBUS_PCIE0_MEM_ATTR, + KIRKWOOD_PCIE_MEM_PHYS_BASE, + KIRKWOOD_PCIE_MEM_SIZE); + mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE1_IO_TARGET, + KIRKWOOD_MBUS_PCIE1_IO_ATTR, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, - KIRKWOOD_PCIE1_IO_BUS_BASE, - MVEBU_MBUS_PCI_IO); - mvebu_mbus_add_window_remap_flags("pcie1.0", - KIRKWOOD_PCIE1_MEM_PHYS_BASE, - KIRKWOOD_PCIE1_MEM_SIZE, - MVEBU_MBUS_NO_REMAP, - MVEBU_MBUS_PCI_MEM); + KIRKWOOD_PCIE1_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE1_MEM_TARGET, + KIRKWOOD_MBUS_PCIE1_MEM_ATTR, + KIRKWOOD_PCIE1_MEM_PHYS_BASE, + KIRKWOOD_PCIE1_MEM_SIZE); vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE; |
