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-rw-r--r--arch/arm/mach-exynos4/clock.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 0d59be3..e21952d 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -111,6 +111,11 @@ struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1",
};
+static struct clk dummy_apb_pclk = {
+ .name = "apb_pclk",
+ .id = -1,
+};
+
static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
@@ -503,12 +508,12 @@ static struct clk init_clocks_off[] = {
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
}, {
- .name = "pdma",
+ .name = "dma",
.devname = "s3c-pl330.0",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 0),
}, {
- .name = "pdma",
+ .name = "dma",
.devname = "s3c-pl330.1",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 1),
@@ -1281,6 +1286,11 @@ void __init exynos4_register_clocks(void)
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+<<<<<<< HEAD
register_syscore_ops(&exynos4_clock_syscore_ops);
+=======
+ s3c24xx_register_clock(&dummy_apb_pclk);
+
+>>>>>>> 4598fc2c94b68740e0269db03c98a1e7ad5af773
s3c_pwmclk_init();
}
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