summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-exynos/include
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-exynos/include')
-rw-r--r--arch/arm/mach-exynos/include/mach/debug-macro.S39
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h18
-rw-r--r--arch/arm/mach-exynos/include/mach/pm-core.h9
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h107
4 files changed, 123 insertions, 50 deletions
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
deleted file mode 100644
index e0c86ea..0000000
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* pull in the relevant register and map files. */
-
-#include <mach/map.h>
-
- /* note, for the boot process to work we have to keep the UART
- * virtual address aligned to an 1MiB boundary for the L1
- * mapping the head code makes. We keep the UART virtual address
- * aligned and add in the offset when we load the value here.
- */
-
- .macro addruart, rp, rv, tmp
- mrc p15, 0, \tmp, c0, c0, 0
- and \tmp, \tmp, #0xf0
- teq \tmp, #0xf0 @@ A15
- ldreq \rp, =EXYNOS5_PA_UART
- movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
- ldr \rv, =S3C_VA_UART
-#if CONFIG_DEBUG_S3C_UART != 0
- add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
- add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
-#endif
- .endm
-
-#define fifo_full fifo_full_s5pv210
-#define fifo_level fifo_level_s5pv210
-
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index c0e75d8..c72f59d 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -126,7 +126,7 @@
#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMU IRQ_SPI(110)
+#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
@@ -134,6 +134,11 @@
#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
+#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2)
+#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
+#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
+#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
+
#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4)
#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4)
@@ -166,7 +171,10 @@
#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
-#define EXYNOS4_MAX_COMBINER_NR 16
+#define EXYNOS4210_MAX_COMBINER_NR 16
+#define EXYNOS4212_MAX_COMBINER_NR 18
+#define EXYNOS4412_MAX_COMBINER_NR 20
+#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR
#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
@@ -231,7 +239,6 @@
#define IRQ_TC EXYNOS4_IRQ_PEN0
#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
-#define IRQ_PMU EXYNOS4_IRQ_PMU
#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
@@ -460,7 +467,10 @@
#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
/* Set the default NR_IRQS */
+#define EXYNOS_NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
-#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+#ifndef CONFIG_SPARSE_IRQ
+#define NR_IRQS EXYNOS_NR_IRQS
+#endif
#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index a67ecfa..7dbbfec 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -27,13 +27,8 @@ static inline void s3c_pm_debug_init_uart(void)
static inline void s3c_pm_arch_prepare_irqs(void)
{
- unsigned int tmp;
- tmp = __raw_readl(S5P_WAKEUP_MASK);
- tmp &= ~(1 << 31);
- __raw_writel(tmp, S5P_WAKEUP_MASK);
-
- __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
- __raw_writel(s3c_irqwake_eintmask & 0xFFFFFFFE, S5P_EINT_WAKEUP_MASK);
+ __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
+ __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
}
static inline void s3c_pm_arch_stop_clocks(void)
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 20fbbdd..d36ad76 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -256,6 +256,113 @@
#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
+/* For EXYNOS5250 */
+
+#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
+#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
+#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
+#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
+#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
+#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
+#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
+#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
+
+#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020)
+#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024)
+
+#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
+#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
+
+#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
+
+#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
+
+#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
+#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
+#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
+#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
+#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
+#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
+#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
+
+#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
+#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
+#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
+#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
+#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
+#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
+#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
+#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
+#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
+#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
+#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
+
+#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
+#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
+#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
+#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
+#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
+#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
+#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
+
+#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
+#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
+#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
+#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
+#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
+#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
+#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
+#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
+#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
+#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
+#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
+#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
+#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
+#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
+#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
+#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
+#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
+
+#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
+#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
+#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
+#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
+#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
+#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
+#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
+#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
+#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
+#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
+#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
+#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
+#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
+
+#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
+#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
+#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
+
+#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
+
+#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
+
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
+
+#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
+#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
+#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
+#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
+#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
+#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
+#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
+#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
+
+#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
+#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
+#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
+#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
+#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
+#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
+
/* Compatibility defines and inclusion */
#include <mach/regs-pmu.h>
OpenPOWER on IntegriCloud