diff options
Diffstat (limited to 'arch/arm/boot')
35 files changed, 1551 insertions, 139 deletions
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index 5df26a9..fc871e7 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile @@ -59,9 +59,11 @@ $(obj)/zImage: $(obj)/compressed/vmlinux FORCE endif +targets += $(dtb-y) + # Rule to build device tree blobs -$(obj)/%.dtb: $(src)/dts/%.dts - $(call cmd,dtc) +$(obj)/%.dtb: $(src)/dts/%.dts FORCE + $(call if_changed_dep,dtc) $(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y)) diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 21f56ff..cf0a64c 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -126,7 +126,8 @@ ccflags-y := -fpic -fno-builtin -I$(obj) asflags-y := -Wa,-march=all # Supply kernel BSS size to the decompressor via a linker symbol. -KBSS_SZ = $(shell size $(obj)/../../../../vmlinux | awk 'END{print $$3}') +KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \ + awk 'END{print $$3}') LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ) # Supply ZRELADDR to the decompressor via a linker symbol. ifneq ($(CONFIG_AUTO_ZRELADDR),y) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index c2effc9..c5d6025 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -659,6 +659,7 @@ __armv7_mmu_cache_on: mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer mcrne p15, 0, r1, c3, c0, 0 @ load domain access control #endif + mcr p15, 0, r0, c7, c5, 4 @ ISB mcr p15, 0, r0, c1, c0, 0 @ load control register mrc p15, 0, r0, c1, c0, 0 @ and read it back mov r0, #0 diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index aeef042..07603b8 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -114,6 +114,13 @@ atmel,use-dma-tx; status = "disabled"; }; + + macb0: ethernet@fffc4000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xfffc4000 0x100>; + interrupts = <21>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index db6a452..fffa005 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -101,6 +101,13 @@ atmel,use-dma-tx; status = "disabled"; }; + + macb0: ethernet@fffbc000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xfffbc000 0x100>; + interrupts = <25>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 85b34f59..a387e77 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -30,6 +30,11 @@ usart1: serial@fff90000 { status = "okay"; }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + }; }; }; }; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts new file mode 100644 index 0000000..b8c4763 --- /dev/null +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -0,0 +1,137 @@ +/* + * Samsung's Exynos4210 based Origen board device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Device tree source file for Insignal's Origen board which is based on + * Samsung's Exynos4210 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos4210.dtsi" + +/ { + model = "Insignal Origen evaluation board based on Exynos4210"; + compatible = "insignal,origen", "samsung,exynos4210"; + + memory { + reg = <0x40000000 0x40000000>; + }; + + chosen { + bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; + }; + + sdhci@12530000 { + samsung,sdhci-bus-width = <4>; + linux,mmc_cap_4_bit_data; + samsung,sdhci-cd-internal; + gpio-cd = <&gpk2 2 2 3 3>; + gpios = <&gpk2 0 2 0 3>, + <&gpk2 1 2 0 3>, + <&gpk2 3 2 3 3>, + <&gpk2 4 2 3 3>, + <&gpk2 5 2 3 3>, + <&gpk2 6 2 3 3>; + }; + + sdhci@12510000 { + samsung,sdhci-bus-width = <4>; + linux,mmc_cap_4_bit_data; + samsung,sdhci-cd-internal; + gpio-cd = <&gpk0 2 2 3 3>; + gpios = <&gpk0 0 2 0 3>, + <&gpk0 1 2 0 3>, + <&gpk0 3 2 3 3>, + <&gpk0 4 2 3 3>, + <&gpk0 5 2 3 3>, + <&gpk0 6 2 3 3>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + up { + label = "Up"; + gpios = <&gpx2 0 0 0 2>; + linux,code = <103>; + }; + + down { + label = "Down"; + gpios = <&gpx2 1 0 0 2>; + linux,code = <108>; + }; + + back { + label = "Back"; + gpios = <&gpx1 7 0 0 2>; + linux,code = <158>; + }; + + home { + label = "Home"; + gpios = <&gpx1 6 0 0 2>; + linux,code = <102>; + }; + + menu { + label = "Menu"; + gpios = <&gpx1 5 0 0 2>; + linux,code = <139>; + }; + }; + + keypad@100A0000 { + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + i2c@13860000 { + status = "disabled"; + }; + + i2c@13870000 { + status = "disabled"; + }; + + i2c@13880000 { + status = "disabled"; + }; + + i2c@13890000 { + status = "disabled"; + }; + + i2c@138A0000 { + status = "disabled"; + }; + + i2c@138B0000 { + status = "disabled"; + }; + + i2c@138C0000 { + status = "disabled"; + }; + + i2c@138D0000 { + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts new file mode 100644 index 0000000..27afc8e --- /dev/null +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -0,0 +1,182 @@ +/* + * Samsung's Exynos4210 based SMDKV310 board device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Device tree source file for Samsung's SMDKV310 board which is based on + * Samsung's Exynos4210 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos4210.dtsi" + +/ { + model = "Samsung smdkv310 evaluation board based on Exynos4210"; + compatible = "samsung,smdkv310", "samsung,exynos4210"; + + memory { + reg = <0x40000000 0x80000000>; + }; + + chosen { + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; + }; + + sdhci@12530000 { + samsung,sdhci-bus-width = <4>; + linux,mmc_cap_4_bit_data; + samsung,sdhci-cd-internal; + gpio-cd = <&gpk2 2 2 3 3>; + gpios = <&gpk2 0 2 0 3>, + <&gpk2 1 2 0 3>, + <&gpk2 3 2 3 3>, + <&gpk2 4 2 3 3>, + <&gpk2 5 2 3 3>, + <&gpk2 6 2 3 3>; + }; + + keypad@100A0000 { + samsung,keypad-num-rows = <2>; + samsung,keypad-num-columns = <8>; + linux,keypad-no-autorepeat; + linux,keypad-wakeup; + + row-gpios = <&gpx2 0 3 3 0>, + <&gpx2 1 3 3 0>; + + col-gpios = <&gpx1 0 3 0 0>, + <&gpx1 1 3 0 0>, + <&gpx1 2 3 0 0>, + <&gpx1 3 3 0 0>, + <&gpx1 4 3 0 0>, + <&gpx1 5 3 0 0>, + <&gpx1 6 3 0 0>, + <&gpx1 7 3 0 0>; + + key_1 { + keypad,row = <0>; + keypad,column = <3>; + linux,code = <2>; + }; + + key_2 { + keypad,row = <0>; + keypad,column = <4>; + linux,code = <3>; + }; + + key_3 { + keypad,row = <0>; + keypad,column = <5>; + linux,code = <4>; + }; + + key_4 { + keypad,row = <0>; + keypad,column = <6>; + linux,code = <5>; + }; + + key_5 { + keypad,row = <0>; + keypad,column = <7>; + linux,code = <6>; + }; + + key_a { + keypad,row = <1>; + keypad,column = <3>; + linux,code = <30>; + }; + + key_b { + keypad,row = <1>; + keypad,column = <4>; + linux,code = <48>; + }; + + key_c { + keypad,row = <1>; + keypad,column = <5>; + linux,code = <46>; + }; + + key_d { + keypad,row = <1>; + keypad,column = <6>; + linux,code = <32>; + }; + + key_e { + keypad,row = <1>; + keypad,column = <7>; + linux,code = <18>; + }; + }; + + i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + gpios = <&gpd1 0 2 3 0>, + <&gpd1 1 2 3 0>; + + eeprom@50 { + compatible = "samsung,24ad0xd1"; + reg = <0x50>; + }; + + eeprom@52 { + compatible = "samsung,24ad0xd1"; + reg = <0x52>; + }; + }; + + sdhci@12510000 { + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + i2c@13870000 { + status = "disabled"; + }; + + i2c@13880000 { + status = "disabled"; + }; + + i2c@13890000 { + status = "disabled"; + }; + + i2c@138A0000 { + status = "disabled"; + }; + + i2c@138B0000 { + status = "disabled"; + }; + + i2c@138C0000 { + status = "disabled"; + }; + + i2c@138D0000 { + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi new file mode 100644 index 0000000..63d7578 --- /dev/null +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -0,0 +1,397 @@ +/* + * Samsung's Exynos4210 SoC device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/include/ "skeleton.dtsi" + +/ { + compatible = "samsung,exynos4210"; + interrupt-parent = <&gic>; + + gic:interrupt-controller@10490000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10490000 0x1000>, <0x10480000 0x100>; + }; + + watchdog@10060000 { + compatible = "samsung,s3c2410-wdt"; + reg = <0x10060000 0x100>; + interrupts = <0 43 0>; + }; + + rtc@10070000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x10070000 0x100>; + interrupts = <0 44 0>, <0 45 0>; + }; + + keypad@100A0000 { + compatible = "samsung,s5pv210-keypad"; + reg = <0x100A0000 0x100>; + interrupts = <0 109 0>; + }; + + sdhci@12510000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12510000 0x100>; + interrupts = <0 73 0>; + }; + + sdhci@12520000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12520000 0x100>; + interrupts = <0 74 0>; + }; + + sdhci@12530000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12530000 0x100>; + interrupts = <0 75 0>; + }; + + sdhci@12540000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12540000 0x100>; + interrupts = <0 76 0>; + }; + + serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x100>; + interrupts = <0 52 0>; + }; + + serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x100>; + interrupts = <0 53 0>; + }; + + serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = <0 54 0>; + }; + + serial@13830000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13830000 0x100>; + interrupts = <0 55 0>; + }; + + i2c@13860000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = <0 58 0>; + }; + + i2c@13870000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = <0 59 0>; + }; + + i2c@13880000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = <0 60 0>; + }; + + i2c@13890000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = <0 61 0>; + }; + + i2c@138A0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138A0000 0x100>; + interrupts = <0 62 0>; + }; + + i2c@138B0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138B0000 0x100>; + interrupts = <0 63 0>; + }; + + i2c@138C0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138C0000 0x100>; + interrupts = <0 64 0>; + }; + + i2c@138D0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138D0000 0x100>; + interrupts = <0 65 0>; + }; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = <0 35 0>; + }; + + pdma1: pdma@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = <0 36 0>; + }; + }; + + gpio-controllers { + #address-cells = <1>; + #size-cells = <1>; + gpio-controller; + ranges; + + gpa0: gpio-controller@11400000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400000 0x20>; + #gpio-cells = <4>; + }; + + gpa1: gpio-controller@11400020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400020 0x20>; + #gpio-cells = <4>; + }; + + gpb: gpio-controller@11400040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400040 0x20>; + #gpio-cells = <4>; + }; + + gpc0: gpio-controller@11400060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400060 0x20>; + #gpio-cells = <4>; + }; + + gpc1: gpio-controller@11400080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400080 0x20>; + #gpio-cells = <4>; + }; + + gpd0: gpio-controller@114000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000A0 0x20>; + #gpio-cells = <4>; + }; + + gpd1: gpio-controller@114000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000C0 0x20>; + #gpio-cells = <4>; + }; + + gpe0: gpio-controller@114000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000E0 0x20>; + #gpio-cells = <4>; + }; + + gpe1: gpio-controller@11400100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400100 0x20>; + #gpio-cells = <4>; + }; + + gpe2: gpio-controller@11400120 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400120 0x20>; + #gpio-cells = <4>; + }; + + gpe3: gpio-controller@11400140 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400140 0x20>; + #gpio-cells = <4>; + }; + + gpe4: gpio-controller@11400160 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400160 0x20>; + #gpio-cells = <4>; + }; + + gpf0: gpio-controller@11400180 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400180 0x20>; + #gpio-cells = <4>; + }; + + gpf1: gpio-controller@114001A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001A0 0x20>; + #gpio-cells = <4>; + }; + + gpf2: gpio-controller@114001C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001C0 0x20>; + #gpio-cells = <4>; + }; + + gpf3: gpio-controller@114001E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001E0 0x20>; + #gpio-cells = <4>; + }; + + gpj0: gpio-controller@11000000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000000 0x20>; + #gpio-cells = <4>; + }; + + gpj1: gpio-controller@11000020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000020 0x20>; + #gpio-cells = <4>; + }; + + gpk0: gpio-controller@11000040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000040 0x20>; + #gpio-cells = <4>; + }; + + gpk1: gpio-controller@11000060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000060 0x20>; + #gpio-cells = <4>; + }; + + gpk2: gpio-controller@11000080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000080 0x20>; + #gpio-cells = <4>; + }; + + gpk3: gpio-controller@110000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110000A0 0x20>; + #gpio-cells = <4>; + }; + + gpl0: gpio-controller@110000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110000C0 0x20>; + #gpio-cells = <4>; + }; + + gpl1: gpio-controller@110000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110000E0 0x20>; + #gpio-cells = <4>; + }; + + gpl2: gpio-controller@11000100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000100 0x20>; + #gpio-cells = <4>; + }; + + gpy0: gpio-controller@11000120 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000120 0x20>; + #gpio-cells = <4>; + }; + + gpy1: gpio-controller@11000140 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000140 0x20>; + #gpio-cells = <4>; + }; + + gpy2: gpio-controller@11000160 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000160 0x20>; + #gpio-cells = <4>; + }; + + gpy3: gpio-controller@11000180 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000180 0x20>; + #gpio-cells = <4>; + }; + + gpy4: gpio-controller@110001A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110001A0 0x20>; + #gpio-cells = <4>; + }; + + gpy5: gpio-controller@110001C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110001C0 0x20>; + #gpio-cells = <4>; + }; + + gpy6: gpio-controller@110001E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x110001E0 0x20>; + #gpio-cells = <4>; + }; + + gpx0: gpio-controller@11000C00 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C00 0x20>; + #gpio-cells = <4>; + }; + + gpx1: gpio-controller@11000C20 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C20 0x20>; + #gpio-cells = <4>; + }; + + gpx2: gpio-controller@11000C40 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C40 0x20>; + #gpio-cells = <4>; + }; + + gpx3: gpio-controller@11000C60 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11000C60 0x20>; + #gpio-cells = <4>; + }; + + gpz: gpio-controller@03860000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x03860000 0x20>; + #gpio-cells = <4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index aeb1a75..305635b 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -194,5 +194,17 @@ reg = <0xfff3d000 0x1000>; interrupts = <0 92 4>; }; + + ethernet@fff50000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff50000 0x1000>; + interrupts = <0 77 4 0 78 4 0 79 4>; + }; + + ethernet@fff51000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff51000 0x1000>; + interrupts = <0 80 4 0 81 4 0 82 4>; + }; }; }; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index f8766af..564cb8c 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -35,20 +35,19 @@ }; esdhc@70008000 { /* ESDHC2 */ - cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */ - wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */ + cd-gpios = <&gpio1 6 0>; + wp-gpios = <&gpio1 5 0>; status = "okay"; }; - uart2: uart@7000c000 { /* UART3 */ + uart3: uart@7000c000 { fsl,uart-has-rtscts; status = "okay"; }; ecspi@70010000 { /* ECSPI1 */ fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */ - <&gpio3 25 0>; /* GPIO4_25 */ + cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; status = "okay"; pmic: mc13892@0 { @@ -57,7 +56,7 @@ compatible = "fsl,mc13892"; spi-max-frequency = <6000000>; reg = <0>; - mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */ + mc13xxx-irq-gpios = <&gpio1 8 0>; fsl,mc13xxx-uses-regulator; }; @@ -91,12 +90,12 @@ reg = <0x73fa8000 0x4000>; }; - uart0: uart@73fbc000 { + uart1: uart@73fbc000 { fsl,uart-has-rtscts; status = "okay"; }; - uart1: uart@73fc0000 { + uart2: uart@73fc0000 { status = "okay"; }; }; @@ -127,7 +126,7 @@ power { label = "Power Button"; - gpios = <&gpio1 21 0>; + gpios = <&gpio2 21 0>; linux,code = <116>; /* KEY_POWER */ gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 327ab8e..6663986 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -14,9 +14,9 @@ / { aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; }; tzic: tz-interrupt-controller@e0000000 { @@ -86,7 +86,7 @@ status = "disabled"; }; - uart2: uart@7000c000 { /* UART3 */ + uart3: uart@7000c000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x7000c000 0x4000>; interrupts = <33>; @@ -117,7 +117,7 @@ }; }; - gpio0: gpio@73f84000 { /* GPIO1 */ + gpio1: gpio@73f84000 { compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; reg = <0x73f84000 0x4000>; interrupts = <50 51>; @@ -127,7 +127,7 @@ #interrupt-cells = <1>; }; - gpio1: gpio@73f88000 { /* GPIO2 */ + gpio2: gpio@73f88000 { compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; reg = <0x73f88000 0x4000>; interrupts = <52 53>; @@ -137,7 +137,7 @@ #interrupt-cells = <1>; }; - gpio2: gpio@73f8c000 { /* GPIO3 */ + gpio3: gpio@73f8c000 { compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; reg = <0x73f8c000 0x4000>; interrupts = <54 55>; @@ -147,7 +147,7 @@ #interrupt-cells = <1>; }; - gpio3: gpio@73f90000 { /* GPIO4 */ + gpio4: gpio@73f90000 { compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; reg = <0x73f90000 0x4000>; interrupts = <56 57>; @@ -171,14 +171,14 @@ status = "disabled"; }; - uart0: uart@73fbc000 { + uart1: uart@73fbc000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; interrupts = <31>; status = "disabled"; }; - uart1: uart@73fc0000 { + uart2: uart@73fc0000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fc0000 0x4000>; interrupts = <32>; diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index 2ab7f80..2dccce4 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts @@ -29,8 +29,8 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ - cd-gpios = <&gpio0 1 0>; /* GPIO1_1 */ - wp-gpios = <&gpio0 9 0>; /* GPIO1_9 */ + cd-gpios = <&gpio1 1 0>; + wp-gpios = <&gpio1 9 0>; status = "okay"; }; }; @@ -44,7 +44,7 @@ reg = <0x53fa8000 0x4000>; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { status = "okay"; }; }; @@ -67,7 +67,7 @@ compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0xf4000000 0x2000000>; phy-mode = "mii"; - interrupt-parent = <&gpio1>; + interrupt-parent = <&gpio2>; interrupts = <31>; reg-io-width = <4>; smsc,irq-push-pull; @@ -79,34 +79,34 @@ home { label = "Home"; - gpios = <&gpio4 10 0>; /* GPIO5_10 */ + gpios = <&gpio5 10 0>; linux,code = <102>; /* KEY_HOME */ gpio-key,wakeup; }; back { label = "Back"; - gpios = <&gpio4 11 0>; /* GPIO5_11 */ + gpios = <&gpio5 11 0>; linux,code = <158>; /* KEY_BACK */ gpio-key,wakeup; }; program { label = "Program"; - gpios = <&gpio4 12 0>; /* GPIO5_12 */ + gpios = <&gpio5 12 0>; linux,code = <362>; /* KEY_PROGRAM */ gpio-key,wakeup; }; volume-up { label = "Volume Up"; - gpios = <&gpio4 13 0>; /* GPIO5_13 */ + gpios = <&gpio5 13 0>; linux,code = <115>; /* KEY_VOLUMEUP */ }; volume-down { label = "Volume Down"; - gpios = <&gpio3 0 0>; /* GPIO4_0 */ + gpios = <&gpio4 0 0>; linux,code = <114>; /* KEY_VOLUMEDOWN */ }; }; diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts index 3f3a881..5bac4aa 100644 --- a/arch/arm/boot/dts/imx53-evk.dts +++ b/arch/arm/boot/dts/imx53-evk.dts @@ -29,15 +29,14 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ - cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */ - wp-gpios = <&gpio2 14 0>; /* GPIO3_14 */ + cd-gpios = <&gpio3 13 0>; + wp-gpios = <&gpio3 14 0>; status = "okay"; }; ecspi@50010000 { /* ECSPI1 */ fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */ - <&gpio2 19 0>; /* GPIO3_19 */ + cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; status = "okay"; flash: at45db321d@1 { @@ -61,8 +60,8 @@ }; esdhc@50020000 { /* ESDHC3 */ - cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */ - wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */ + cd-gpios = <&gpio3 11 0>; + wp-gpios = <&gpio3 12 0>; status = "okay"; }; }; @@ -76,7 +75,7 @@ reg = <0x53fa8000 0x4000>; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { status = "okay"; }; }; @@ -102,7 +101,7 @@ fec@63fec000 { phy-mode = "rmii"; - phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */ + phy-reset-gpios = <&gpio7 6 0>; status = "okay"; }; }; @@ -113,7 +112,7 @@ green { label = "Heartbeat"; - gpios = <&gpio6 7 0>; /* GPIO7_7 */ + gpios = <&gpio7 7 0>; linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index ae6de6d..5c57c86 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -29,13 +29,13 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ - cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */ + cd-gpios = <&gpio3 13 0>; status = "okay"; }; esdhc@50020000 { /* ESDHC3 */ - cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */ - wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */ + cd-gpios = <&gpio3 11 0>; + wp-gpios = <&gpio3 12 0>; status = "okay"; }; }; @@ -49,7 +49,7 @@ reg = <0x53fa8000 0x4000>; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { status = "okay"; }; }; @@ -84,7 +84,7 @@ fec@63fec000 { phy-mode = "rmii"; - phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */ + phy-reset-gpios = <&gpio7 6 0>; status = "okay"; }; }; @@ -95,20 +95,20 @@ power { label = "Power Button"; - gpios = <&gpio0 8 0>; /* GPIO1_8 */ + gpios = <&gpio1 8 0>; linux,code = <116>; /* KEY_POWER */ gpio-key,wakeup; }; volume-up { label = "Volume Up"; - gpios = <&gpio1 14 0>; /* GPIO2_14 */ + gpios = <&gpio2 14 0>; linux,code = <115>; /* KEY_VOLUMEUP */ }; volume-down { label = "Volume Down"; - gpios = <&gpio1 15 0>; /* GPIO2_15 */ + gpios = <&gpio2 15 0>; linux,code = <114>; /* KEY_VOLUMEDOWN */ }; }; @@ -118,7 +118,7 @@ user { label = "Heartbeat"; - gpios = <&gpio6 7 0>; /* GPIO7_7 */ + gpios = <&gpio7 7 0>; linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index b1c062e..c7ee86c 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -29,8 +29,8 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ - cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */ - wp-gpios = <&gpio3 11 0>; /* GPIO4_11 */ + cd-gpios = <&gpio3 13 0>; + wp-gpios = <&gpio4 11 0>; status = "okay"; }; @@ -39,15 +39,14 @@ status = "okay"; }; - uart2: uart@5000c000 { /* UART3 */ + uart3: uart@5000c000 { fsl,uart-has-rtscts; status = "okay"; }; ecspi@50010000 { /* ECSPI1 */ fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */ - <&gpio2 19 0>; /* GPIO3_19 */ + cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; status = "okay"; zigbee: mc1323@0 { @@ -91,11 +90,11 @@ reg = <0x53fa8000 0x4000>; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { status = "okay"; }; - uart1: uart@53fc0000 { /* UART2 */ + uart2: uart@53fc0000 { status = "okay"; }; }; @@ -145,7 +144,7 @@ fec@63fec000 { phy-mode = "rmii"; - phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */ + phy-reset-gpios = <&gpio7 6 0>; status = "okay"; }; }; @@ -156,13 +155,13 @@ volume-up { label = "Volume Up"; - gpios = <&gpio1 14 0>; /* GPIO2_14 */ + gpios = <&gpio2 14 0>; linux,code = <115>; /* KEY_VOLUMEUP */ }; volume-down { label = "Volume Down"; - gpios = <&gpio1 15 0>; /* GPIO2_15 */ + gpios = <&gpio2 15 0>; linux,code = <114>; /* KEY_VOLUMEDOWN */ }; }; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 099cd84..5dd91b9 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -14,11 +14,11 @@ / { aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; }; tzic: tz-interrupt-controller@0fffc000 { @@ -88,7 +88,7 @@ status = "disabled"; }; - uart2: uart@5000c000 { /* UART3 */ + uart3: uart@5000c000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; interrupts = <33>; @@ -119,7 +119,7 @@ }; }; - gpio0: gpio@53f84000 { /* GPIO1 */ + gpio1: gpio@53f84000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53f84000 0x4000>; interrupts = <50 51>; @@ -129,7 +129,7 @@ #interrupt-cells = <1>; }; - gpio1: gpio@53f88000 { /* GPIO2 */ + gpio2: gpio@53f88000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53f88000 0x4000>; interrupts = <52 53>; @@ -139,7 +139,7 @@ #interrupt-cells = <1>; }; - gpio2: gpio@53f8c000 { /* GPIO3 */ + gpio3: gpio@53f8c000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53f8c000 0x4000>; interrupts = <54 55>; @@ -149,7 +149,7 @@ #interrupt-cells = <1>; }; - gpio3: gpio@53f90000 { /* GPIO4 */ + gpio4: gpio@53f90000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53f90000 0x4000>; interrupts = <56 57>; @@ -173,21 +173,21 @@ status = "disabled"; }; - uart0: uart@53fbc000 { /* UART1 */ + uart1: uart@53fbc000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fbc000 0x4000>; interrupts = <31>; status = "disabled"; }; - uart1: uart@53fc0000 { /* UART2 */ + uart2: uart@53fc0000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fc0000 0x4000>; interrupts = <32>; status = "disabled"; }; - gpio4: gpio@53fdc000 { /* GPIO5 */ + gpio5: gpio@53fdc000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53fdc000 0x4000>; interrupts = <103 104>; @@ -197,7 +197,7 @@ #interrupt-cells = <1>; }; - gpio5: gpio@53fe0000 { /* GPIO6 */ + gpio6: gpio@53fe0000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53fe0000 0x4000>; interrupts = <105 106>; @@ -207,7 +207,7 @@ #interrupt-cells = <1>; }; - gpio6: gpio@53fe4000 { /* GPIO7 */ + gpio7: gpio@53fe4000 { compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; reg = <0x53fe4000 0x4000>; interrupts = <107 108>; @@ -226,7 +226,7 @@ status = "disabled"; }; - uart3: uart@53ff0000 { /* UART4 */ + uart4: uart@53ff0000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53ff0000 0x4000>; interrupts = <13>; @@ -241,7 +241,7 @@ reg = <0x60000000 0x10000000>; ranges; - uart4: uart@63f90000 { /* UART5 */ + uart5: uart@63f90000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x63f90000 0x4000>; interrupts = <86>; diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-arm2.dts index 072974e..c3977e0 100644 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -14,8 +14,8 @@ /include/ "imx6q.dtsi" / { - model = "Freescale i.MX6 Quad SABRE Automotive Board"; - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; + model = "Freescale i.MX6 Quad Armadillo2 Board"; + compatible = "fsl,imx6q-arm2", "fsl,imx6q"; chosen { bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait"; @@ -34,8 +34,8 @@ }; usdhc@02198000 { /* uSDHC3 */ - cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */ - wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */ + cd-gpios = <&gpio6 11 0>; + wp-gpios = <&gpio6 14 0>; status = "okay"; }; @@ -44,7 +44,7 @@ status = "okay"; }; - uart3: uart@021f0000 { /* UART4 */ + uart4: uart@021f0000 { status = "okay"; }; }; @@ -55,7 +55,7 @@ debug-led { label = "Heartbeat"; - gpios = <&gpio2 25 0>; /* GPIO3_25 */ + gpios = <&gpio3 25 0>; linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts new file mode 100644 index 0000000..08d920d --- /dev/null +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx6q.dtsi" + +/ { + model = "Freescale i.MX6 Quad SABRE Lite Board"; + compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + soc { + aips-bus@02100000 { /* AIPS2 */ + enet@02188000 { + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 23 0>; + status = "okay"; + }; + + usdhc@02198000 { /* uSDHC3 */ + cd-gpios = <&gpio7 0 0>; + wp-gpios = <&gpio7 1 0>; + status = "okay"; + }; + + usdhc@0219c000 { /* uSDHC4 */ + cd-gpios = <&gpio2 6 0>; + wp-gpios = <&gpio2 7 0>; + status = "okay"; + }; + + uart2: uart@021e8000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 7dda599..263e8f3 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -14,11 +14,11 @@ / { aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; }; cpus { @@ -165,7 +165,7 @@ status = "disabled"; }; - uart0: uart@02020000 { /* UART1 */ + uart1: uart@02020000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = <0 26 0x04>; @@ -247,7 +247,7 @@ interrupts = <0 55 0x04>; }; - gpio0: gpio@0209c000 { /* GPIO1 */ + gpio1: gpio@0209c000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x0209c000 0x4000>; interrupts = <0 66 0x04 0 67 0x04>; @@ -257,7 +257,7 @@ #interrupt-cells = <1>; }; - gpio1: gpio@020a0000 { /* GPIO2 */ + gpio2: gpio@020a0000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x020a0000 0x4000>; interrupts = <0 68 0x04 0 69 0x04>; @@ -267,7 +267,7 @@ #interrupt-cells = <1>; }; - gpio2: gpio@020a4000 { /* GPIO3 */ + gpio3: gpio@020a4000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x020a4000 0x4000>; interrupts = <0 70 0x04 0 71 0x04>; @@ -277,7 +277,7 @@ #interrupt-cells = <1>; }; - gpio3: gpio@020a8000 { /* GPIO4 */ + gpio4: gpio@020a8000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x020a8000 0x4000>; interrupts = <0 72 0x04 0 73 0x04>; @@ -287,7 +287,7 @@ #interrupt-cells = <1>; }; - gpio4: gpio@020ac000 { /* GPIO5 */ + gpio5: gpio@020ac000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x020ac000 0x4000>; interrupts = <0 74 0x04 0 75 0x04>; @@ -297,7 +297,7 @@ #interrupt-cells = <1>; }; - gpio5: gpio@020b0000 { /* GPIO6 */ + gpio6: gpio@020b0000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x020b0000 0x4000>; interrupts = <0 76 0x04 0 77 0x04>; @@ -307,7 +307,7 @@ #interrupt-cells = <1>; }; - gpio6: gpio@020b4000 { /* GPIO7 */ + gpio7: gpio@020b4000 { compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio"; reg = <0x020b4000 0x4000>; interrupts = <0 78 0x04 0 79 0x04>; @@ -543,28 +543,28 @@ interrupts = <0 18 0x04>; }; - uart1: uart@021e8000 { /* UART2 */ + uart2: uart@021e8000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = <0 27 0x04>; status = "disabled"; }; - uart2: uart@021ec000 { /* UART3 */ + uart3: uart@021ec000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = <0 28 0x04>; status = "disabled"; }; - uart3: uart@021f0000 { /* UART4 */ + uart4: uart@021f0000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = <0 29 0x04>; status = "disabled"; }; - uart4: uart@021f4000 { /* UART5 */ + uart5: uart@021f4000 { compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = <0 30 0x04>; diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi new file mode 100644 index 0000000..f2ab4ea --- /dev/null +++ b/arch/arm/boot/dts/omap2.dtsi @@ -0,0 +1,67 @@ +/* + * Device Tree Source for OMAP2 SoC + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + cpus { + cpu@0 { + compatible = "arm,arm1136jf-s"; + }; + }; + + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap2-mpu"; + ti,hwmods = "mpu"; + }; + }; + + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + intc: interrupt-controller@1 { + compatible = "ti,omap2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart1: serial@4806a000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@4806c000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@4806e000 { + compatible = "ti,omap2-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index d202bb5..216c331 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -13,6 +13,13 @@ / { compatible = "ti,omap3430", "ti,omap3"; + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + }; + cpus { cpu@0 { compatible = "arm,cortex-a8"; @@ -59,5 +66,29 @@ interrupt-controller; #interrupt-cells = <1>; }; + + uart1: serial@0x4806a000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@0x4806c000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@0x49020000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + uart4: serial@0x49042000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; }; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 4c61c82..e8fe75f 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -21,6 +21,10 @@ interrupt-parent = <&gic>; aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; }; cpus { @@ -99,5 +103,29 @@ reg = <0x48241000 0x1000>, <0x48240100 0x0100>; }; + + uart1: serial@0x4806a000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@0x4806c000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@0x48020000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + uart4: serial@0x4806e000 { + compatible = "ti,omap4-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; }; }; diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts new file mode 100644 index 0000000..70c41fc --- /dev/null +++ b/arch/arm/boot/dts/tegra-cardhu.dts @@ -0,0 +1,36 @@ +/dts-v1/; + +/include/ "tegra30.dtsi" + +/ { + model = "NVIDIA Tegra30 Cardhu evaluation board"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; + + memory { + reg = < 0x80000000 0x40000000 >; + }; + + serial@70006000 { + clock-frequency = < 408000000 >; + }; + + i2c@7000c000 { + clock-frequency = <100000>; + }; + + i2c@7000c400 { + clock-frequency = <100000>; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + }; + + i2c@7000c700 { + clock-frequency = <100000>; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + }; +}; diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts index 0e225b8..80afa1b 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra-harmony.dts @@ -1,16 +1,11 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; /include/ "tegra20.dtsi" / { model = "NVIDIA Tegra2 Harmony evaluation board"; compatible = "nvidia,harmony", "nvidia,tegra20"; - chosen { - bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait"; - }; - memory@0 { reg = < 0x00000000 0x40000000 >; }; @@ -52,16 +47,40 @@ ext-mic-en-gpios = <&gpio 185 0>; }; + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + serial@70006300 { clock-frequency = < 216000000 >; }; + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + sdhci@c8000200 { cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 155 0>; /* gpio PT3 */ }; + sdhci@c8000400 { + status = "disable"; + }; + sdhci@c8000600 { cd-gpios = <&gpio 58 0>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts new file mode 100644 index 0000000..1a1d702 --- /dev/null +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -0,0 +1,77 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "Toshiba AC100 / Dynabook AZ"; + compatible = "compal,paz00", "nvidia,tegra20"; + + memory@0 { + reg = <0x00000000 0x20000000>; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + status = "disable"; + }; + + nvec@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,nvec"; + reg = <0x7000C500 0x100>; + interrupts = <0 92 0x04>; + clock-frequency = <80000>; + request-gpios = <&gpio 170 0>; + slave-addr = <138>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + }; + + serial@70006000 { + clock-frequency = <216000000>; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + clock-frequency = <216000000>; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + cd-gpios = <&gpio 173 0>; /* gpio PV5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + status = "disable"; + }; + + sdhci@c8000600 { + support-8bit; + }; +}; diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts index a72299b..b55a02e 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra-seaboard.dts @@ -1,25 +1,65 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; /include/ "tegra20.dtsi" / { model = "NVIDIA Seaboard"; compatible = "nvidia,seaboard", "nvidia,tegra20"; - chosen { - bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; - }; - memory { device_type = "memory"; reg = < 0x00000000 0x40000000 >; }; + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + + adt7461@4c { + compatible = "adt7461"; + reg = <0x4c>; + }; + }; + + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + serial@70006300 { clock-frequency = < 216000000 >; }; + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + sdhci@c8000400 { cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ @@ -29,4 +69,28 @@ sdhci@c8000600 { support-8bit; }; + + usb@c5000000 { + nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio 170 1>; /* gpio PV2, active low */ + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + + lid { + label = "Lid"; + gpios = <&gpio 23 0>; /* gpio PC7 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + gpio-key,wakeup; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts new file mode 100644 index 0000000..3b3ee7d --- /dev/null +++ b/arch/arm/boot/dts/tegra-trimslice.dts @@ -0,0 +1,65 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "Compulab TrimSlice board"; + compatible = "compulab,trimslice", "nvidia,tegra20"; + + memory@0 { + reg = < 0x00000000 0x40000000 >; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + status = "disable"; + }; + + serial@70006000 { + clock-frequency = < 216000000 >; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + + serial@70006300 { + status = "disable"; + }; + + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + + sdhci@c8000400 { + status = "disable"; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 121 0>; + wp-gpios = <&gpio 122 0>; + }; +}; diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts index 3f9abd6b..c7d3b87 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra-ventana.dts @@ -1,24 +1,59 @@ /dts-v1/; -/memreserve/ 0x1c000000 0x04000000; /include/ "tegra20.dtsi" / { model = "NVIDIA Tegra2 Ventana evaluation board"; compatible = "nvidia,ventana", "nvidia,tegra20"; - chosen { - bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init"; - }; - memory { reg = < 0x00000000 0x40000000 >; }; + i2c@7000c000 { + clock-frequency = <400000>; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + }; + + serial@70006000 { + status = "disable"; + }; + + serial@70006040 { + status = "disable"; + }; + + serial@70006200 { + status = "disable"; + }; + serial@70006300 { clock-frequency = < 216000000 >; }; + serial@70006400 { + status = "disable"; + }; + + sdhci@c8000000 { + status = "disable"; + }; + + sdhci@c8000200 { + status = "disable"; + }; + sdhci@c8000400 { cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 65d7e6a..3da7afd 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -5,9 +5,9 @@ interrupt-parent = <&intc>; intc: interrupt-controller@50041000 { - compatible = "nvidia,tegra20-gic"; + compatible = "arm,cortex-a9-gic"; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <3>; reg = < 0x50041000 0x1000 >, < 0x50040100 0x0100 >; }; @@ -17,7 +17,7 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000C000 0x100>; - interrupts = < 70 >; + interrupts = < 0 38 0x04 >; }; i2c@7000c400 { @@ -25,7 +25,7 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000C400 0x100>; - interrupts = < 116 >; + interrupts = < 0 84 0x04 >; }; i2c@7000c500 { @@ -33,38 +33,32 @@ #size-cells = <0>; compatible = "nvidia,tegra20-i2c"; reg = <0x7000C500 0x100>; - interrupts = < 124 >; + interrupts = < 0 92 0x04 >; }; i2c@7000d000 { #address-cells = <1>; #size-cells = <0>; - compatible = "nvidia,tegra20-i2c"; + compatible = "nvidia,tegra20-i2c-dvc"; reg = <0x7000D000 0x200>; - interrupts = < 85 >; + interrupts = < 0 53 0x04 >; }; i2s@70002800 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-i2s"; reg = <0x70002800 0x200>; - interrupts = < 45 >; + interrupts = < 0 13 0x04 >; dma-channel = < 2 >; }; i2s@70002a00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-i2s"; reg = <0x70002a00 0x200>; - interrupts = < 35 >; + interrupts = < 0 3 0x04 >; dma-channel = < 1 >; }; das@70000c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "nvidia,tegra20-das"; reg = <0x70000c00 0x80>; }; @@ -72,7 +66,13 @@ gpio: gpio@6000d000 { compatible = "nvidia,tegra20-gpio"; reg = < 0x6000d000 0x1000 >; - interrupts = < 64 65 66 67 87 119 121 >; + interrupts = < 0 32 0x04 + 0 33 0x04 + 0 34 0x04 + 0 35 0x04 + 0 55 0x04 + 0 87 0x04 + 0 89 0x04 >; #gpio-cells = <2>; gpio-controller; }; @@ -89,59 +89,80 @@ compatible = "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; reg-shift = <2>; - interrupts = < 68 >; + interrupts = < 0 36 0x04 >; }; serial@70006040 { compatible = "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; - interrupts = < 69 >; + interrupts = < 0 37 0x04 >; }; serial@70006200 { compatible = "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; - interrupts = < 78 >; + interrupts = < 0 46 0x04 >; }; serial@70006300 { compatible = "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; - interrupts = < 122 >; + interrupts = < 0 90 0x04 >; }; serial@70006400 { compatible = "nvidia,tegra20-uart"; reg = <0x70006400 0x100>; reg-shift = <2>; - interrupts = < 123 >; + interrupts = < 0 91 0x04 >; }; sdhci@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; - interrupts = < 46 >; + interrupts = < 0 14 0x04 >; }; sdhci@c8000200 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; - interrupts = < 47 >; + interrupts = < 0 15 0x04 >; }; sdhci@c8000400 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; - interrupts = < 51 >; + interrupts = < 0 19 0x04 >; }; sdhci@c8000600 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; - interrupts = < 63 >; + interrupts = < 0 31 0x04 >; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5000000 0x4000>; + interrupts = < 0 20 0x04 >; + phy_type = "utmi"; + }; + + usb@c5004000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5004000 0x4000>; + interrupts = < 0 21 0x04 >; + phy_type = "ulpi"; + }; + + usb@c5008000 { + compatible = "nvidia,tegra20-ehci", "usb-ehci"; + reg = <0xc5008000 0x4000>; + interrupts = < 0 97 0x04 >; + phy_type = "utmi"; }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi new file mode 100644 index 0000000..ee7db98 --- /dev/null +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -0,0 +1,127 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra30"; + interrupt-parent = <&intc>; + + intc: interrupt-controller@50041000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x50041000 0x1000 >, + < 0x50040100 0x0100 >; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + interrupts = < 0 38 0x04 >; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 0 84 0x04 >; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + interrupts = < 0 92 0x04 >; + }; + + i2c@7000c700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000c700 0x100>; + interrupts = < 0 120 0x04 >; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000D000 0x100>; + interrupts = < 0 53 0x04 >; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >; + #gpio-cells = <2>; + gpio-controller; + }; + + serial@70006000 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = < 0 36 0x04 >; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = < 0 37 0x04 >; + }; + + serial@70006200 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = < 0 46 0x04 >; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = < 0 90 0x04 >; + }; + + serial@70006400 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = < 0 91 0x04 >; + }; + + sdhci@78000000 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000000 0x200>; + interrupts = < 0 14 0x04 >; + }; + + sdhci@78000200 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000200 0x200>; + interrupts = < 0 15 0x04 >; + }; + + sdhci@78000400 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000400 0x200>; + interrupts = < 0 19 0x04 >; + }; + + sdhci@78000600 { + compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + reg = <0x78000600 0x200>; + interrupts = < 0 31 0x04 >; + }; + + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra30-pinmux"; + reg = < 0x70000868 0xd0 /* Pad control registers */ + 0x70003000 0x3e0 >; /* Mux registers */ + }; +}; diff --git a/arch/arm/boot/dts/testcases/tests-phandle.dtsi b/arch/arm/boot/dts/testcases/tests-phandle.dtsi new file mode 100644 index 0000000..ec0c4e6 --- /dev/null +++ b/arch/arm/boot/dts/testcases/tests-phandle.dtsi @@ -0,0 +1,37 @@ + +/ { + testcase-data { + phandle-tests { + provider0: provider0 { + #phandle-cells = <0>; + }; + + provider1: provider1 { + #phandle-cells = <1>; + }; + + provider2: provider2 { + #phandle-cells = <2>; + }; + + provider3: provider3 { + #phandle-cells = <3>; + }; + + consumer-a { + phandle-list = <&provider1 1>, + <&provider2 2 0>, + <0>, + <&provider3 4 4 3>, + <&provider2 5 100>, + <&provider0>, + <&provider1 7>; + phandle-list-names = "first", "second", "third"; + + phandle-list-bad-phandle = <12345678 0 0>; + phandle-list-bad-args = <&provider2 1 0>, + <&provider3 0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/testcases/tests.dtsi b/arch/arm/boot/dts/testcases/tests.dtsi new file mode 100644 index 0000000..a7c5067 --- /dev/null +++ b/arch/arm/boot/dts/testcases/tests.dtsi @@ -0,0 +1 @@ +/include/ "tests-phandle.dtsi" diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts index d66e2c0..f04b535 100644 --- a/arch/arm/boot/dts/usb_a9g20.dts +++ b/arch/arm/boot/dts/usb_a9g20.dts @@ -25,6 +25,11 @@ dbgu: serial@fffff200 { status = "okay"; }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; }; }; }; diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts index 8a614e3..1664610 100644 --- a/arch/arm/boot/dts/versatile-pb.dts +++ b/arch/arm/boot/dts/versatile-pb.dts @@ -46,3 +46,5 @@ }; }; }; + +/include/ "testcases/tests.dtsi" |
