diff options
Diffstat (limited to 'arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts')
-rw-r--r-- | arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 109 |
1 files changed, 109 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts new file mode 100644 index 0000000..52153ec --- /dev/null +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -0,0 +1,109 @@ +/* + * Device Tree Source for the iWave-RZG1E SODIMM carrier board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7745-iwg22m.dtsi" + +/ { + model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E"; + compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; + + aliases { + serial0 = &scif4; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&pfc { + scif4_pins: scif4 { + groups = "scif4_data_b"; + function = "scif4"; + }; + + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; +}; + +&scif4 { + pinctrl-0 = <&scif4_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + /* + * On some older versions of the platform (before R4.0) the phy address + * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. + */ + reg = <3>; + micrel,led-mode = <1>; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&usbphy { + status = "okay"; +}; |