diff options
| -rw-r--r-- | drivers/video/matrox/g450_pll.c | 23 | ||||
| -rw-r--r-- | drivers/video/matrox/matroxfb_DAC1064.h | 15 | ||||
| -rw-r--r-- | drivers/video/matrox/matroxfb_base.h | 1 | ||||
| -rw-r--r-- | drivers/video/matrox/matroxfb_misc.c | 1 |
4 files changed, 30 insertions, 10 deletions
diff --git a/drivers/video/matrox/g450_pll.c b/drivers/video/matrox/g450_pll.c index 7c76e07..d42346e 100644 --- a/drivers/video/matrox/g450_pll.c +++ b/drivers/video/matrox/g450_pll.c @@ -331,16 +331,19 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll, tmp |= M1064_XPIXCLKCTRL_PLL_UP; } matroxfb_DAC_out(PMINFO M1064_XPIXCLKCTRL, tmp); -#ifdef __powerpc__ - /* This is necessary to avoid jitter on PowerPC - * (OpenFirmware) systems, but apparently - * introduces jitter, at least on a x86-64 - * using DVI. - * A simple workaround is disable for non-PPC. - */ - matroxfb_DAC_out(PMINFO M1064_XDVICLKCTRL, 0); -#endif /* __powerpc__ */ - matroxfb_DAC_out(PMINFO M1064_XPWRCTRL, xpwrctrl); + /* DVI PLL preferred for frequencies up to + panel link max, standard PLL otherwise */ + if (fout >= MINFO->max_pixel_clock_panellink) + tmp = 0; + else tmp = + M1064_XDVICLKCTRL_DVIDATAPATHSEL | + M1064_XDVICLKCTRL_C1DVICLKSEL | + M1064_XDVICLKCTRL_C1DVICLKEN | + M1064_XDVICLKCTRL_DVILOOPCTL | + M1064_XDVICLKCTRL_P1LOOPBWDTCTL; + matroxfb_DAC_out(PMINFO M1064_XDVICLKCTRL,tmp); + matroxfb_DAC_out(PMINFO M1064_XPWRCTRL, + xpwrctrl); matroxfb_DAC_unlock_irqrestore(flags); } diff --git a/drivers/video/matrox/matroxfb_DAC1064.h b/drivers/video/matrox/matroxfb_DAC1064.h index df39c31..7a98ce8 100644 --- a/drivers/video/matrox/matroxfb_DAC1064.h +++ b/drivers/video/matrox/matroxfb_DAC1064.h @@ -33,6 +33,21 @@ void DAC1064_global_restore(WPMINFO2); #define M1064_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */ #define M1064_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */ #define M1064_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */ + /* drive DVI by standard(0)/DVI(1) PLL */ + /* if set(1), C?DVICLKEN and C?DVICLKSEL must be set(1) */ +#define M1064_XDVICLKCTRL_DVIDATAPATHSEL 0x01 + /* drive CRTC1 by standard(0)/DVI(1) PLL */ +#define M1064_XDVICLKCTRL_C1DVICLKSEL 0x02 + /* drive CRTC2 by standard(0)/DVI(1) PLL */ +#define M1064_XDVICLKCTRL_C2DVICLKSEL 0x04 + /* pixel clock allowed to(0)/blocked from(1) driving CRTC1 */ +#define M1064_XDVICLKCTRL_C1DVICLKEN 0x08 + /* DVI PLL loop filter bandwidth selection bits */ +#define M1064_XDVICLKCTRL_DVILOOPCTL 0x30 + /* CRTC2 pixel clock allowed to(0)/blocked from(1) driving CRTC2 */ +#define M1064_XDVICLKCTRL_C2DVICLKEN 0x40 + /* P1PLL loop filter bandwith selection */ +#define M1064_XDVICLKCTRL_P1LOOPBWDTCTL 0x80 #define M1064_XCURCOL0RED 0x08 #define M1064_XCURCOL0GREEN 0x09 #define M1064_XCURCOL0BLUE 0x0A diff --git a/drivers/video/matrox/matroxfb_base.h b/drivers/video/matrox/matroxfb_base.h index d59577c..f3107ad 100644 --- a/drivers/video/matrox/matroxfb_base.h +++ b/drivers/video/matrox/matroxfb_base.h @@ -424,6 +424,7 @@ struct matrox_fb_info { } mmio; unsigned int max_pixel_clock; + unsigned int max_pixel_clock_panellink; struct matrox_switch* hw_switch; diff --git a/drivers/video/matrox/matroxfb_misc.c b/drivers/video/matrox/matroxfb_misc.c index 5948e54..ab7fb50 100644 --- a/drivers/video/matrox/matroxfb_misc.c +++ b/drivers/video/matrox/matroxfb_misc.c @@ -658,6 +658,7 @@ static int parse_pins5(WPMINFO const struct matrox_bios* bd) { MINFO->values.reg.mctlwtst_core = (MINFO->values.reg.mctlwtst & ~7) | wtst_xlat[MINFO->values.reg.mctlwtst & 7]; } + MINFO->max_pixel_clock_panellink = bd->pins[47] * 4000; return 0; } |
