diff options
413 files changed, 23377 insertions, 6826 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 32cbf3e..a3fb23b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -364,6 +364,14 @@ config ARCH_MXC help Support for Freescale MXC/iMX-based family of processors +config ARCH_MXS + bool "Freescale MXS-based" + select GENERIC_CLOCKEVENTS + select ARCH_REQUIRE_GPIOLIB + select COMMON_CLKDEV + help + Support for Freescale MXS-based family of processors + config ARCH_STMP3XXX bool "Freescale STMP3xxx" select CPU_ARM926T @@ -817,6 +825,7 @@ config ARCH_U8500 select GENERIC_CLOCKEVENTS select CLKDEV_LOOKUP select ARCH_REQUIRE_GPIOLIB + select ARCH_HAS_CPUFREQ help Support for ST-Ericsson's Ux500 architecture @@ -923,6 +932,8 @@ source "arch/arm/mach-mv78xx0/Kconfig" source "arch/arm/plat-mxc/Kconfig" +source "arch/arm/mach-mxs/Kconfig" + source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-nomadik/Kconfig" @@ -1022,8 +1033,8 @@ source arch/arm/mm/Kconfig config IWMMXT bool "Enable iWMMXt support" - depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK - default y if PXA27x || PXA3xx || ARCH_MMP + depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 + default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP help Enable support for iWMMXt context switching at run time if running on a CPU that supports it. diff --git a/arch/arm/Makefile b/arch/arm/Makefile index b87aed0..c22c1ad 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -154,10 +154,11 @@ machine-$(CONFIG_ARCH_MSM) := msm machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 machine-$(CONFIG_ARCH_MX1) := imx machine-$(CONFIG_ARCH_MX2) := imx -machine-$(CONFIG_ARCH_MX25) := mx25 +machine-$(CONFIG_ARCH_MX25) := imx machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_MX5) := mx5 machine-$(CONFIG_ARCH_MXC91231) := mxc91231 +machine-$(CONFIG_ARCH_MXS) := mxs machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NOMADIK) := nomadik machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig index f0c339f..e648ea3 100644 --- a/arch/arm/configs/mx3_defconfig +++ b/arch/arm/configs/mx3_defconfig @@ -84,6 +84,7 @@ CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_IMX=y +CONFIG_SPI=y CONFIG_W1=y CONFIG_W1_MASTER_MXC=y CONFIG_W1_SLAVE_THERM=y diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h index 4d8ae9d..f389b27 100644 --- a/arch/arm/include/asm/hw_breakpoint.h +++ b/arch/arm/include/asm/hw_breakpoint.h @@ -20,8 +20,8 @@ struct arch_hw_breakpoint_ctrl { struct arch_hw_breakpoint { u32 address; u32 trigger; - struct perf_event *suspended_wp; - struct arch_hw_breakpoint_ctrl ctrl; + struct arch_hw_breakpoint_ctrl step_ctrl; + struct arch_hw_breakpoint_ctrl ctrl; }; static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 7c33e6f..185ee82 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -54,6 +54,7 @@ AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o +obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o obj-$(CONFIG_CPU_HAS_PMU) += pmu.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 27f6448..2b46fea 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -178,6 +178,7 @@ __dabt_svc: @ @ set desired IRQ state, then call main handler @ + debug_entry r1 msr cpsr_c, r9 mov r2, sp bl do_DataAbort @@ -304,6 +305,7 @@ __pabt_svc: #else bl CPU_PABORT_HANDLER #endif + debug_entry r1 msr cpsr_c, r9 @ Maybe enable interrupts mov r2, sp @ regs bl do_PrefetchAbort @ call abort handler @@ -419,6 +421,7 @@ __dabt_usr: @ @ IRQs on, then call the main handler @ + debug_entry r1 enable_irq mov r2, sp adr lr, BSYM(ret_from_exception) @@ -683,6 +686,7 @@ __pabt_usr: #else bl CPU_PABORT_HANDLER #endif + debug_entry r1 enable_irq @ Enable interrupts mov r2, sp @ regs bl do_PrefetchAbort @ call abort handler diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index d93f976..ae94649 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -165,6 +165,25 @@ .endm #endif /* !CONFIG_THUMB2_KERNEL */ + @ + @ Debug exceptions are taken as prefetch or data aborts. + @ We must disable preemption during the handler so that + @ we can access the debug registers safely. + @ + .macro debug_entry, fsr +#if defined(CONFIG_HAVE_HW_BREAKPOINT) && defined(CONFIG_PREEMPT) + ldr r4, =0x40f @ mask out fsr.fs + and r5, r4, \fsr + cmp r5, #2 @ debug exception + bne 1f + get_thread_info r10 + ldr r6, [r10, #TI_PREEMPT] @ get preempt count + add r11, r6, #1 @ increment it + str r11, [r10, #TI_PREEMPT] +1: +#endif + .endm + /* * These are the registers used in the syscall handler, and allow us to * have in theory up to 7 arguments to a function - r0 to r6. diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 21e3a4a..c9f3f04 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -24,6 +24,7 @@ #define pr_fmt(fmt) "hw-breakpoint: " fmt #include <linux/errno.h> +#include <linux/hardirq.h> #include <linux/perf_event.h> #include <linux/hw_breakpoint.h> #include <linux/smp.h> @@ -44,6 +45,7 @@ static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]); /* Number of BRP/WRP registers on this CPU. */ static int core_num_brps; +static int core_num_reserved_brps; static int core_num_wrps; /* Debug architecture version. */ @@ -52,87 +54,6 @@ static u8 debug_arch; /* Maximum supported watchpoint length. */ static u8 max_watchpoint_len; -/* Determine number of BRP registers available. */ -static int get_num_brps(void) -{ - u32 didr; - ARM_DBG_READ(c0, 0, didr); - return ((didr >> 24) & 0xf) + 1; -} - -/* Determine number of WRP registers available. */ -static int get_num_wrps(void) -{ - /* - * FIXME: When a watchpoint fires, the only way to work out which - * watchpoint it was is by disassembling the faulting instruction - * and working out the address of the memory access. - * - * Furthermore, we can only do this if the watchpoint was precise - * since imprecise watchpoints prevent us from calculating register - * based addresses. - * - * For the time being, we only report 1 watchpoint register so we - * always know which watchpoint fired. In the future we can either - * add a disassembler and address generation emulator, or we can - * insert a check to see if the DFAR is set on watchpoint exception - * entry [the ARM ARM states that the DFAR is UNKNOWN, but - * experience shows that it is set on some implementations]. - */ - -#if 0 - u32 didr, wrps; - ARM_DBG_READ(c0, 0, didr); - return ((didr >> 28) & 0xf) + 1; -#endif - - return 1; -} - -int hw_breakpoint_slots(int type) -{ - /* - * We can be called early, so don't rely on - * our static variables being initialised. - */ - switch (type) { - case TYPE_INST: - return get_num_brps(); - case TYPE_DATA: - return get_num_wrps(); - default: - pr_warning("unknown slot type: %d\n", type); - return 0; - } -} - -/* Determine debug architecture. */ -static u8 get_debug_arch(void) -{ - u32 didr; - - /* Do we implement the extended CPUID interface? */ - if (((read_cpuid_id() >> 16) & 0xf) != 0xf) { - pr_warning("CPUID feature registers not supported. " - "Assuming v6 debug is present.\n"); - return ARM_DEBUG_ARCH_V6; - } - - ARM_DBG_READ(c0, 0, didr); - return (didr >> 16) & 0xf; -} - -/* Does this core support mismatch breakpoints? */ -static int core_has_mismatch_bps(void) -{ - return debug_arch >= ARM_DEBUG_ARCH_V7_ECP14 && core_num_brps > 1; -} - -u8 arch_get_debug_arch(void) -{ - return debug_arch; -} - #define READ_WB_REG_CASE(OP2, M, VAL) \ case ((OP2 << 4) + M): \ ARM_DBG_READ(c ## M, OP2, VAL); \ @@ -210,6 +131,94 @@ static void write_wb_reg(int n, u32 val) isb(); } +/* Determine debug architecture. */ +static u8 get_debug_arch(void) +{ + u32 didr; + + /* Do we implement the extended CPUID interface? */ + if (((read_cpuid_id() >> 16) & 0xf) != 0xf) { + pr_warning("CPUID feature registers not supported. " + "Assuming v6 debug is present.\n"); + return ARM_DEBUG_ARCH_V6; + } + + ARM_DBG_READ(c0, 0, didr); + return (didr >> 16) & 0xf; +} + +u8 arch_get_debug_arch(void) +{ + return debug_arch; +} + +/* Determine number of BRP register available. */ +static int get_num_brp_resources(void) +{ + u32 didr; + ARM_DBG_READ(c0, 0, didr); + return ((didr >> 24) & 0xf) + 1; +} + +/* Does this core support mismatch breakpoints? */ +static int core_has_mismatch_brps(void) +{ + return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 && + get_num_brp_resources() > 1); +} + +/* Determine number of usable WRPs available. */ +static int get_num_wrps(void) +{ + /* + * FIXME: When a watchpoint fires, the only way to work out which + * watchpoint it was is by disassembling the faulting instruction + * and working out the address of the memory access. + * + * Furthermore, we can only do this if the watchpoint was precise + * since imprecise watchpoints prevent us from calculating register + * based addresses. + * + * Providing we have more than 1 breakpoint register, we only report + * a single watchpoint register for the time being. This way, we always + * know which watchpoint fired. In the future we can either add a + * disassembler and address generation emulator, or we can insert a + * check to see if the DFAR is set on watchpoint exception entry + * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows + * that it is set on some implementations]. + */ + +#if 0 + int wrps; + u32 didr; + ARM_DBG_READ(c0, 0, didr); + wrps = ((didr >> 28) & 0xf) + 1; +#endif + int wrps = 1; + + if (core_has_mismatch_brps() && wrps >= get_num_brp_resources()) + wrps = get_num_brp_resources() - 1; + + return wrps; +} + +/* We reserve one breakpoint for each watchpoint. */ +static int get_num_reserved_brps(void) +{ + if (core_has_mismatch_brps()) + return get_num_wrps(); + return 0; +} + +/* Determine number of usable BRPs available. */ +static int get_num_brps(void) +{ + int brps = get_num_brp_resources(); + if (core_has_mismatch_brps()) + brps -= get_num_reserved_brps(); + return brps; +} + /* * In order to access the breakpoint/watchpoint control registers, * we must be running in debug monitor mode. Unfortunately, we can @@ -230,8 +239,12 @@ static int enable_monitor_mode(void) goto out; } + /* If monitor mode is already enabled, just return. */ + if (dscr & ARM_DSCR_MDBGEN) + goto out; + /* Write to the corresponding DSCR. */ - switch (debug_arch) { + switch (get_debug_arch()) { case ARM_DEBUG_ARCH_V6: case ARM_DEBUG_ARCH_V6_1: ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN)); @@ -246,15 +259,30 @@ static int enable_monitor_mode(void) /* Check that the write made it through. */ ARM_DBG_READ(c1, 0, dscr); - if (WARN_ONCE(!(dscr & ARM_DSCR_MDBGEN), - "failed to enable monitor mode.")) { + if (!(dscr & ARM_DSCR_MDBGEN)) ret = -EPERM; - } out: return ret; } +int hw_breakpoint_slots(int type) +{ + /* + * We can be called early, so don't rely on + * our static variables being initialised. + */ + switch (type) { + case TYPE_INST: + return get_num_brps(); + case TYPE_DATA: + return get_num_wrps(); + default: + pr_warning("unknown slot type: %d\n", type); + return 0; + } +} + /* * Check if 8-bit byte-address select is available. * This clobbers WRP 0. @@ -268,9 +296,6 @@ static u8 get_max_wp_len(void) if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14) goto out; - if (enable_monitor_mode()) - goto out; - memset(&ctrl, 0, sizeof(ctrl)); ctrl.len = ARM_BREAKPOINT_LEN_8; ctrl_reg = encode_ctrl_reg(ctrl); @@ -290,23 +315,6 @@ u8 arch_get_max_wp_len(void) } /* - * Handler for reactivating a suspended watchpoint when the single - * step `mismatch' breakpoint is triggered. - */ -static void wp_single_step_handler(struct perf_event *bp, int unused, - struct perf_sample_data *data, - struct pt_regs *regs) -{ - perf_event_enable(counter_arch_bp(bp)->suspended_wp); - unregister_hw_breakpoint(bp); -} - -static int bp_is_single_step(struct perf_event *bp) -{ - return bp->overflow_handler == wp_single_step_handler; -} - -/* * Install a perf counter breakpoint. */ int arch_install_hw_breakpoint(struct perf_event *bp) @@ -314,30 +322,41 @@ int arch_install_hw_breakpoint(struct perf_event *bp) struct arch_hw_breakpoint *info = counter_arch_bp(bp); struct perf_event **slot, **slots; int i, max_slots, ctrl_base, val_base, ret = 0; + u32 addr, ctrl; /* Ensure that we are in monitor mode and halting mode is disabled. */ ret = enable_monitor_mode(); if (ret) goto out; + addr = info->address; + ctrl = encode_ctrl_reg(info->ctrl) | 0x1; + if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { /* Breakpoint */ ctrl_base = ARM_BASE_BCR; val_base = ARM_BASE_BVR; - slots = __get_cpu_var(bp_on_reg); - max_slots = core_num_brps - 1; - - if (bp_is_single_step(bp)) { - info->ctrl.mismatch = 1; - i = max_slots; - slots[i] = bp; - goto setup; + slots = (struct perf_event **)__get_cpu_var(bp_on_reg); + max_slots = core_num_brps; + if (info->step_ctrl.enabled) { + /* Override the breakpoint data with the step data. */ + addr = info->trigger & ~0x3; + ctrl = encode_ctrl_reg(info->step_ctrl); } } else { /* Watchpoint */ - ctrl_base = ARM_BASE_WCR; - val_base = ARM_BASE_WVR; - slots = __get_cpu_var(wp_on_reg); + if (info->step_ctrl.enabled) { + /* Install into the reserved breakpoint region. */ + ctrl_base = ARM_BASE_BCR + core_num_brps; + val_base = ARM_BASE_BVR + core_num_brps; + /* Override the watchpoint data with the step data. */ + addr = info->trigger & ~0x3; + ctrl = encode_ctrl_reg(info->step_ctrl); + } else { + ctrl_base = ARM_BASE_WCR; + val_base = ARM_BASE_WVR; + } + slots = (struct perf_event **)__get_cpu_var(wp_on_reg); max_slots = core_num_wrps; } @@ -355,12 +374,11 @@ int arch_install_hw_breakpoint(struct perf_event *bp) goto out; } -setup: /* Setup the address register. */ - write_wb_reg(val_base + i, info->address); + write_wb_reg(val_base + i, addr); /* Setup the control register. */ - write_wb_reg(ctrl_base + i, encode_ctrl_reg(info->ctrl) | 0x1); + write_wb_reg(ctrl_base + i, ctrl); out: return ret; @@ -375,18 +393,15 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp) if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { /* Breakpoint */ base = ARM_BASE_BCR; - slots = __get_cpu_var(bp_on_reg); - max_slots = core_num_brps - 1; - - if (bp_is_single_step(bp)) { - i = max_slots; - slots[i] = NULL; - goto reset; - } + slots = (struct perf_event **)__get_cpu_var(bp_on_reg); + max_slots = core_num_brps; } else { /* Watchpoint */ - base = ARM_BASE_WCR; - slots = __get_cpu_var(wp_on_reg); + if (info->step_ctrl.enabled) + base = ARM_BASE_BCR + core_num_brps; + else + base = ARM_BASE_WCR; + slots = (struct perf_event **)__get_cpu_var(wp_on_reg); max_slots = core_num_wrps; } @@ -403,7 +418,6 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp) if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) return; -reset: /* Reset the control register. */ write_wb_reg(base + i, 0); } @@ -537,12 +551,23 @@ static int arch_build_bp_info(struct perf_event *bp) return -EINVAL; } + /* + * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes. + * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported + * by the hardware and must be aligned to the appropriate number of + * bytes. + */ + if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE && + info->ctrl.len != ARM_BREAKPOINT_LEN_2 && + info->ctrl.len != ARM_BREAKPOINT_LEN_4) + return -EINVAL; + /* Address */ info->address = bp->attr.bp_addr; /* Privilege */ info->ctrl.privilege = ARM_BREAKPOINT_USER; - if (arch_check_bp_in_kernelspace(bp) && !bp_is_single_step(bp)) + if (arch_check_bp_in_kernelspace(bp)) info->ctrl.privilege |= ARM_BREAKPOINT_PRIV; /* Enabled? */ @@ -561,7 +586,7 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) { struct arch_hw_breakpoint *info = counter_arch_bp(bp); int ret = 0; - u32 bytelen, max_len, offset, alignment_mask = 0x3; + u32 offset, alignment_mask = 0x3; /* Build the arch_hw_breakpoint. */ ret = arch_build_bp_info(bp); @@ -571,84 +596,85 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) /* Check address alignment. */ if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) alignment_mask = 0x7; - if (info->address & alignment_mask) { - /* - * Try to fix the alignment. This may result in a length - * that is too large, so we must check for that. - */ - bytelen = get_hbp_len(info->ctrl.len); - max_len = info->ctrl.type == ARM_BREAKPOINT_EXECUTE ? 4 : - max_watchpoint_len; - - if (max_len >= 8) - offset = info->address & 0x7; - else - offset = info->address & 0x3; - - if (bytelen > (1 << ((max_len - (offset + 1)) >> 1))) { - ret = -EFBIG; - goto out; - } - - info->ctrl.len <<= offset; - info->address &= ~offset; - - pr_debug("breakpoint alignment fixup: length = 0x%x, " - "address = 0x%x\n", info->ctrl.len, info->address); + offset = info->address & alignment_mask; + switch (offset) { + case 0: + /* Aligned */ + break; + case 1: + /* Allow single byte watchpoint. */ + if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) + break; + case 2: + /* Allow halfword watchpoints and breakpoints. */ + if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) + break; + default: + ret = -EINVAL; + goto out; } + info->address &= ~alignment_mask; + info->ctrl.len <<= offset; + /* * Currently we rely on an overflow handler to take * care of single-stepping the breakpoint when it fires. * In the case of userspace breakpoints on a core with V7 debug, - * we can use the mismatch feature as a poor-man's hardware single-step. + * we can use the mismatch feature as a poor-man's hardware + * single-step, but this only works for per-task breakpoints. */ if (WARN_ONCE(!bp->overflow_handler && - (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_bps()), + (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_brps() + || !bp->hw.bp_target), "overflow handler required but none found")) { ret = -EINVAL; - goto out; } out: return ret; } -static void update_mismatch_flag(int idx, int flag) +/* + * Enable/disable single-stepping over the breakpoint bp at address addr. + */ +static void enable_single_step(struct perf_event *bp, u32 addr) { - struct perf_event *bp = __get_cpu_var(bp_on_reg[idx]); - struct arch_hw_breakpoint *info; - - if (bp == NULL) - return; + struct arch_hw_breakpoint *info = counter_arch_bp(bp); - info = counter_arch_bp(bp); + arch_uninstall_hw_breakpoint(bp); + info->step_ctrl.mismatch = 1; + info->step_ctrl.len = ARM_BREAKPOINT_LEN_4; + info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE; + info->step_ctrl.privilege = info->ctrl.privilege; + info->step_ctrl.enabled = 1; + info->trigger = addr; + arch_install_hw_breakpoint(bp); +} - /* Update the mismatch field to enter/exit `single-step' mode */ - if (!bp->overflow_handler && info->ctrl.mismatch != flag) { - info->ctrl.mismatch = flag; - write_wb_reg(ARM_BASE_BCR + idx, encode_ctrl_reg(info->ctrl) | 0x1); - } +static void disable_single_step(struct perf_event *bp) +{ + arch_uninstall_hw_breakpoint(bp); + counter_arch_bp(bp)->step_ctrl.enabled = 0; + arch_install_hw_breakpoint(bp); } static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs) { int i; - struct perf_event *bp, **slots = __get_cpu_var(wp_on_reg); + struct perf_event *wp, **slots; struct arch_hw_breakpoint *info; - struct perf_event_attr attr; + + slots = (struct perf_event **)__get_cpu_var(wp_on_reg); /* Without a disassembler, we can only handle 1 watchpoint. */ BUG_ON(core_num_wrps > 1); - hw_breakpoint_init(&attr); - attr.bp_addr = regs->ARM_pc & ~0x3; - attr.bp_len = HW_BREAKPOINT_LEN_4; - attr.bp_type = HW_BREAKPOINT_X; - for (i = 0; i < core_num_wrps; ++i) { rcu_read_lock(); - if (slots[i] == NULL) { + wp = slots[i]; + + if (wp == NULL) { rcu_read_unlock(); continue; } @@ -658,24 +684,51 @@ static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs) * single watchpoint, we can set the trigger to the lowest * possible faulting address. */ - info = counter_arch_bp(slots[i]); - info->trigger = slots[i]->attr.bp_addr; + info = counter_arch_bp(wp); + info->trigger = wp->attr.bp_addr; pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); - perf_bp_event(slots[i], regs); + perf_bp_event(wp, regs); /* * If no overflow handler is present, insert a temporary * mismatch breakpoint so we can single-step over the * watchpoint trigger. */ - if (!slots[i]->overflow_handler) { - bp = register_user_hw_breakpoint(&attr, - wp_single_step_handler, - current); - counter_arch_bp(bp)->suspended_wp = slots[i]; - perf_event_disable(slots[i]); - } + if (!wp->overflow_handler) + enable_single_step(wp, instruction_pointer(regs)); + + rcu_read_unlock(); + } +} +static void watchpoint_single_step_handler(unsigned long pc) +{ + int i; + struct perf_event *wp, **slots; + struct arch_hw_breakpoint *info; + + slots = (struct perf_event **)__get_cpu_var(wp_on_reg); + + for (i = 0; i < core_num_reserved_brps; ++i) { + rcu_read_lock(); + + wp = slots[i]; + + if (wp == NULL) + goto unlock; + + info = counter_arch_bp(wp); + if (!info->step_ctrl.enabled) + goto unlock; + + /* + * Restore the original watchpoint if we've completed the + * single-step. + */ + if (info->trigger != pc) + disable_single_step(wp); + +unlock: rcu_read_unlock(); } } @@ -683,62 +736,69 @@ static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs) static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) { int i; - int mismatch; u32 ctrl_reg, val, addr; - struct perf_event *bp, **slots = __get_cpu_var(bp_on_reg); + struct perf_event *bp, **slots; struct arch_hw_breakpoint *info; struct arch_hw_breakpoint_ctrl ctrl; + slots = (struct perf_event **)__get_cpu_var(bp_on_reg); + /* The exception entry code places the amended lr in the PC. */ addr = regs->ARM_pc; + /* Check the currently installed breakpoints first. */ for (i = 0; i < core_num_brps; ++i) { rcu_read_lock(); bp = slots[i]; - if (bp == NULL) { - rcu_read_unlock(); - continue; - } + if (bp == NULL) + goto unlock; - mismatch = 0; + info = counter_arch_bp(bp); /* Check if the breakpoint value matches. */ val = read_wb_reg(ARM_BASE_BVR + i); if (val != (addr & ~0x3)) - goto unlock; + goto mismatch; /* Possible match, check the byte address select to confirm. */ ctrl_reg = read_wb_reg(ARM_BASE_BCR + i); decode_ctrl_reg(ctrl_reg, &ctrl); if ((1 << (addr & 0x3)) & ctrl.len) { - mismatch = 1; - info = counter_arch_bp(bp); info->trigger = addr; - } - -unlock: - if ((mismatch && !info->ctrl.mismatch) || bp_is_single_step(bp)) { pr_debug("breakpoint fired: address = 0x%x\n", addr); perf_bp_event(bp, regs); + if (!bp->overflow_handler) + enable_single_step(bp, addr); + goto unlock; } - update_mismatch_flag(i, mismatch); +mismatch: + /* If we're stepping a breakpoint, it can now be restored. */ + if (info->step_ctrl.enabled) + disable_single_step(bp); +unlock: rcu_read_unlock(); } + + /* Handle any pending watchpoint single-step breakpoints. */ + watchpoint_single_step_handler(addr); } /* * Called from either the Data Abort Handler [watchpoint] or the - * Prefetch Abort Handler [breakpoint]. + * Prefetch Abort Handler [breakpoint] with preemption disabled. */ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { - int ret = 1; /* Unhandled fault. */ + int ret = 0; u32 dscr; + /* We must be called with preemption disabled. */ + WARN_ON(preemptible()); + /* We only handle watchpoints and hardware breakpoints. */ ARM_DBG_READ(c1, 0, dscr); @@ -753,25 +813,47 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, watchpoint_handler(addr, regs); break; default: - goto out; + ret = 1; /* Unhandled fault. */ } - ret = 0; -out: + /* + * Re-enable preemption after it was disabled in the + * low-level exception handling code. + */ + preempt_enable(); + return ret; } /* * One-time initialisation. */ -static void __init reset_ctrl_regs(void *unused) +static void reset_ctrl_regs(void *unused) { int i; + /* + * v7 debug contains save and restore registers so that debug state + * can be maintained across low-power modes without leaving + * the debug logic powered up. It is IMPLEMENTATION DEFINED whether + * we can write to the debug registers out of reset, so we must + * unlock the OS Lock Access Register to avoid taking undefined + * instruction exceptions later on. + */ + if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) { + /* + * Unconditionally clear the lock by writing a value + * other than 0xC5ACCE55 to the access register. + */ + asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0)); + isb(); + } + if (enable_monitor_mode()) return; - for (i = 0; i < core_num_brps; ++i) { + /* We must also reset any reserved registers. */ + for (i = 0; i < core_num_brps + core_num_reserved_brps; ++i) { write_wb_reg(ARM_BASE_BCR + i, 0UL); write_wb_reg(ARM_BASE_BVR + i, 0UL); } @@ -782,45 +864,57 @@ static void __init reset_ctrl_regs(void *unused) } } +static int __cpuinit dbg_reset_notify(struct notifier_block *self, + unsigned long action, void *cpu) +{ + if (action == CPU_ONLINE) + smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1); + return NOTIFY_OK; +} + +static struct notifier_block __cpuinitdata dbg_reset_nb = { + .notifier_call = dbg_reset_notify, +}; + static int __init arch_hw_breakpoint_init(void) { - int ret = 0; u32 dscr; debug_arch = get_debug_arch(); if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) { pr_info("debug architecture 0x%x unsupported.\n", debug_arch); - ret = -ENODEV; - goto out; + return 0; } /* Determine how many BRPs/WRPs are available. */ core_num_brps = get_num_brps(); + core_num_reserved_brps = get_num_reserved_brps(); core_num_wrps = get_num_wrps(); pr_info("found %d breakpoint and %d watchpoint registers.\n", - core_num_brps, core_num_wrps); + core_num_brps + core_num_reserved_brps, core_num_wrps); - if (core_has_mismatch_bps()) - pr_info("1 breakpoint reserved for watchpoint single-step.\n"); + if (core_num_reserved_brps) + pr_info("%d breakpoint(s) reserved for watchpoint " + "single-step.\n", core_num_reserved_brps); ARM_DBG_READ(c1, 0, dscr); if (dscr & ARM_DSCR_HDBGEN) { pr_warning("halting debug mode enabled. Assuming maximum " "watchpoint size of 4 bytes."); } else { - /* Work out the maximum supported watchpoint length. */ - max_watchpoint_len = get_max_wp_len(); - pr_info("maximum watchpoint size is %u bytes.\n", - max_watchpoint_len); - /* * Reset the breakpoint resources. We assume that a halting * debugger will leave the world in a nice state for us. */ smp_call_function(reset_ctrl_regs, NULL, 1); reset_ctrl_regs(NULL); + + /* Work out the maximum supported watchpoint length. */ + max_watchpoint_len = get_max_wp_len(); + pr_info("maximum watchpoint size is %u bytes.\n", + max_watchpoint_len); } /* Register debug fault handler. */ @@ -829,8 +923,9 @@ static int __init arch_hw_breakpoint_init(void) hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, "breakpoint debug exception"); -out: - return ret; + /* Register hotplug notifier. */ + register_cpu_notifier(&dbg_reset_nb); + return 0; } arch_initcall(arch_hw_breakpoint_init); diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S index b63b528..7fa3bb0 100644 --- a/arch/arm/kernel/iwmmxt.S +++ b/arch/arm/kernel/iwmmxt.S @@ -19,6 +19,14 @@ #include <asm/thread_info.h> #include <asm/asm-offsets.h> +#if defined(CONFIG_CPU_PJ4) +#define PJ4(code...) code +#define XSC(code...) +#else +#define PJ4(code...) +#define XSC(code...) code +#endif + #define MMX_WR0 (0x00) #define MMX_WR1 (0x08) #define MMX_WR2 (0x10) @@ -58,11 +66,17 @@ ENTRY(iwmmxt_task_enable) - mrc p15, 0, r2, c15, c1, 0 - tst r2, #0x3 @ CP0 and CP1 accessible? + XSC(mrc p15, 0, r2, c15, c1, 0) + PJ4(mrc p15, 0, r2, c1, c0, 2) + @ CP0 and CP1 accessible? + XSC(tst r2, #0x3) + PJ4(tst r2, #0xf) movne pc, lr @ if so no business here - orr r2, r2, #0x3 @ enable access to CP0 and CP1 - mcr p15, 0, r2, c15, c1, 0 + @ enable access to CP0 and CP1 + XSC(orr r2, r2, #0x3) + XSC(mcr p15, 0, r2, c15, c1, 0) + PJ4(orr r2, r2, #0xf) + PJ4(mcr p15, 0, r2, c1, c0, 2) ldr r3, =concan_owner add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area @@ -179,17 +193,26 @@ ENTRY(iwmmxt_task_disable) teqne r1, r2 @ or specified one? bne 1f @ no: quit - mrc p15, 0, r4, c15, c1, 0 - orr r4, r4, #0x3 @ enable access to CP0 and CP1 - mcr p15, 0, r4, c15, c1, 0 + @ enable access to CP0 and CP1 + XSC(mrc p15, 0, r4, c15, c1, 0) + XSC(orr r4, r4, #0xf) + XSC(mcr p15, 0, r4, c15, c1, 0) + PJ4(mrc p15, 0, r4, c1, c0, 2) + PJ4(orr r4, r4, #0x3) + PJ4(mcr p15, 0, r4, c1, c0, 2) + mov r0, #0 @ nothing to load str r0, [r3] @ no more current owner mrc p15, 0, r2, c2, c0, 0 mov r2, r2 @ cpwait bl concan_save - bic r4, r4, #0x3 @ disable access to CP0 and CP1 - mcr p15, 0, r4, c15, c1, 0 + @ disable access to CP0 and CP1 + XSC(bic r4, r4, #0x3) + XSC(mcr p15, 0, r4, c15, c1, 0) + PJ4(bic r4, r4, #0xf) + PJ4(mcr p15, 0, r4, c1, c0, 2) + mrc p15, 0, r2, c2, c0, 0 mov r2, r2 @ cpwait @@ -277,8 +300,11 @@ ENTRY(iwmmxt_task_restore) */ ENTRY(iwmmxt_task_switch) - mrc p15, 0, r1, c15, c1, 0 - tst r1, #0x3 @ CP0 and CP1 accessible? + XSC(mrc p15, 0, r1, c15, c1, 0) + PJ4(mrc p15, 0, r1, c1, c0, 2) + @ CP0 and CP1 accessible? + XSC(tst r1, #0x3) + PJ4(tst r1, #0xf) bne 1f @ yes: block them for next task ldr r2, =concan_owner @@ -287,8 +313,11 @@ ENTRY(iwmmxt_task_switch) teq r2, r3 @ next task owns it? movne pc, lr @ no: leave Concan disabled -1: eor r1, r1, #3 @ flip Concan access - mcr p15, 0, r1, c15, c1, 0 +1: @ flip Conan access + XSC(eor r1, r1, #0x3) + XSC(mcr p15, 0, r1, c15, c1, 0) + PJ4(eor r1, r1, #0xf) + PJ4(mcr p15, 0, r1, c1, c0, 2) mrc p15, 0, r1, c2, c0, 0 sub pc, lr, r1, lsr #32 @ cpwait and return diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 421a4bb..624e2a5 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -32,7 +32,7 @@ static struct platform_device *pmu_device; * Hardware lock to serialize accesses to PMU registers. Needed for the * read/modify/write sequences. */ -DEFINE_SPINLOCK(pmu_lock); +static DEFINE_RAW_SPINLOCK(pmu_lock); /* * ARMv6 supports a maximum of 3 events, starting from index 1. If we add @@ -65,7 +65,7 @@ struct cpu_hw_events { */ unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; }; -DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); +static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); struct arm_pmu { enum arm_perf_pmu_ids id; @@ -673,17 +673,17 @@ arch_initcall(init_hw_perf_events); * This code has been adapted from the ARM OProfile support. */ struct frame_tail { - struct frame_tail *fp; - unsigned long sp; - unsigned long lr; + struct frame_tail __user *fp; + unsigned long sp; + unsigned long lr; } __attribute__((packed)); /* * Get the return address for a single stackframe and return a pointer to the * next frame tail. */ -static struct frame_tail * -user_backtrace(struct frame_tail *tail, +static struct frame_tail __user * +user_backtrace(struct frame_tail __user *tail, struct perf_callchain_entry *entry) { struct frame_tail buftail; @@ -709,10 +709,10 @@ user_backtrace(struct frame_tail *tail, void perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) { - struct frame_tail *tail; + struct frame_tail __user *tail; - tail = (struct frame_tail *)regs->ARM_fp - 1; + tail = (struct frame_tail __user *)regs->ARM_fp - 1; while (tail && !((unsigned long)tail & 0x3)) tail = user_backtrace(tail, entry); diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c index 7aeb07d..c058bfc 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/arch/arm/kernel/perf_event_v6.c @@ -400,7 +400,7 @@ armv6pmu_write_counter(int counter, WARN_ONCE(1, "invalid counter number (%d)\n", counter); } -void +static void armv6pmu_enable_event(struct hw_perf_event *hwc, int idx) { @@ -426,12 +426,12 @@ armv6pmu_enable_event(struct hw_perf_event *hwc, * Mask out the current event and set the counter to count the event * that we're interested in. */ - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); val = armv6_pmcr_read(); val &= ~mask; val |= evt; armv6_pmcr_write(val); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static irqreturn_t @@ -500,11 +500,11 @@ armv6pmu_start(void) { unsigned long flags, val; - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); val = armv6_pmcr_read(); val |= ARMV6_PMCR_ENABLE; armv6_pmcr_write(val); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static void @@ -512,11 +512,11 @@ armv6pmu_stop(void) { unsigned long flags, val; - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); val = armv6_pmcr_read(); val &= ~ARMV6_PMCR_ENABLE; armv6_pmcr_write(val); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static int @@ -570,12 +570,12 @@ armv6pmu_disable_event(struct hw_perf_event *hwc, * of ETM bus signal assertion cycles. The external reporting should * be disabled and so this should never increment. */ - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); val = armv6_pmcr_read(); val &= ~mask; val |= evt; armv6_pmcr_write(val); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static void @@ -599,12 +599,12 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc, * Unlike UP ARMv6, we don't have a way of stopping the counters. We * simply disable the interrupt reporting. */ - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); val = armv6_pmcr_read(); val &= ~mask; val |= evt; armv6_pmcr_write(val); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static const struct arm_pmu armv6pmu = { @@ -625,7 +625,7 @@ static const struct arm_pmu armv6pmu = { .max_period = (1LLU << 32) - 1, }; -const struct arm_pmu *__init armv6pmu_init(void) +static const struct arm_pmu *__init armv6pmu_init(void) { return &armv6pmu; } @@ -655,17 +655,17 @@ static const struct arm_pmu armv6mpcore_pmu = { .max_period = (1LLU << 32) - 1, }; -const struct arm_pmu *__init armv6mpcore_pmu_init(void) +static const struct arm_pmu *__init armv6mpcore_pmu_init(void) { return &armv6mpcore_pmu; } #else -const struct arm_pmu *__init armv6pmu_init(void) +static const struct arm_pmu *__init armv6pmu_init(void) { return NULL; } -const struct arm_pmu *__init armv6mpcore_pmu_init(void) +static const struct arm_pmu *__init armv6mpcore_pmu_init(void) { return NULL; } diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 4d04239..2e14025 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -681,7 +681,7 @@ static void armv7_pmnc_dump_regs(void) } #endif -void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx) +static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx) { unsigned long flags; @@ -689,7 +689,7 @@ void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx) * Enable counter and interrupt, and set the counter to count * the event that we're interested in. */ - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); /* * Disable counter @@ -713,7 +713,7 @@ void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx) */ armv7_pmnc_enable_counter(idx); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx) @@ -723,7 +723,7 @@ static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx) /* * Disable counter and interrupt */ - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); /* * Disable counter @@ -735,7 +735,7 @@ static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx) */ armv7_pmnc_disable_intens(idx); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) @@ -805,20 +805,20 @@ static void armv7pmu_start(void) { unsigned long flags; - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); /* Enable all counters */ armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static void armv7pmu_stop(void) { unsigned long flags; - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); /* Disable all counters */ armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc, @@ -874,7 +874,7 @@ static u32 __init armv7_reset_read_pmnc(void) return nb_cnt + 1; } -const struct arm_pmu *__init armv7_a8_pmu_init(void) +static const struct arm_pmu *__init armv7_a8_pmu_init(void) { armv7pmu.id = ARM_PERF_PMU_ID_CA8; armv7pmu.name = "ARMv7 Cortex-A8"; @@ -884,7 +884,7 @@ const struct arm_pmu *__init armv7_a8_pmu_init(void) return &armv7pmu; } -const struct arm_pmu *__init armv7_a9_pmu_init(void) +static const struct arm_pmu *__init armv7_a9_pmu_init(void) { armv7pmu.id = ARM_PERF_PMU_ID_CA9; armv7pmu.name = "ARMv7 Cortex-A9"; @@ -894,12 +894,12 @@ const struct arm_pmu *__init armv7_a9_pmu_init(void) return &armv7pmu; } #else -const struct arm_pmu *__init armv7_a8_pmu_init(void) +static const struct arm_pmu *__init armv7_a8_pmu_init(void) { return NULL; } -const struct arm_pmu *__init armv7_a9_pmu_init(void) +static const struct arm_pmu *__init armv7_a9_pmu_init(void) { return NULL; } diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c index 4e95927..28cd3b0 100644 --- a/arch/arm/kernel/perf_event_xscale.c +++ b/arch/arm/kernel/perf_event_xscale.c @@ -291,12 +291,12 @@ xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx) return; } - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); val = xscale1pmu_read_pmnc(); val &= ~mask; val |= evt; xscale1pmu_write_pmnc(val); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static void @@ -322,12 +322,12 @@ xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx) return; } - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); val = xscale1pmu_read_pmnc(); val &= ~mask; val |= evt; xscale1pmu_write_pmnc(val); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static int @@ -355,11 +355,11 @@ xscale1pmu_start(void) { unsigned long flags, val; - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); val = xscale1pmu_read_pmnc(); val |= XSCALE_PMU_ENABLE; xscale1pmu_write_pmnc(val); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static void @@ -367,11 +367,11 @@ xscale1pmu_stop(void) { unsigned long flags, val; - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); val = xscale1pmu_read_pmnc(); val &= ~XSCALE_PMU_ENABLE; xscale1pmu_write_pmnc(val); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static inline u32 @@ -428,7 +428,7 @@ static const struct arm_pmu xscale1pmu = { .max_period = (1LLU << 32) - 1, }; -const struct arm_pmu *__init xscale1pmu_init(void) +static const struct arm_pmu *__init xscale1pmu_init(void) { return &xscale1pmu; } @@ -635,10 +635,10 @@ xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx) return; } - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); xscale2pmu_write_event_select(evtsel); xscale2pmu_write_int_enable(ien); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static void @@ -678,10 +678,10 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx) return; } - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); xscale2pmu_write_event_select(evtsel); xscale2pmu_write_int_enable(ien); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static int @@ -705,11 +705,11 @@ xscale2pmu_start(void) { unsigned long flags, val; - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64; val |= XSCALE_PMU_ENABLE; xscale2pmu_write_pmnc(val); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static void @@ -717,11 +717,11 @@ xscale2pmu_stop(void) { unsigned long flags, val; - spin_lock_irqsave(&pmu_lock, flags); + raw_spin_lock_irqsave(&pmu_lock, flags); val = xscale2pmu_read_pmnc(); val &= ~XSCALE_PMU_ENABLE; xscale2pmu_write_pmnc(val); - spin_unlock_irqrestore(&pmu_lock, flags); + raw_spin_unlock_irqrestore(&pmu_lock, flags); } static inline u32 @@ -790,17 +790,17 @@ static const struct arm_pmu xscale2pmu = { .max_period = (1LLU << 32) - 1, }; -const struct arm_pmu *__init xscale2pmu_init(void) +static const struct arm_pmu *__init xscale2pmu_init(void) { return &xscale2pmu; } #else -const struct arm_pmu *__init xscale1pmu_init(void) +static const struct arm_pmu *__init xscale1pmu_init(void) { return NULL; } -const struct arm_pmu *__init xscale2pmu_init(void) +static const struct arm_pmu *__init xscale2pmu_init(void) { return NULL; } diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c new file mode 100644 index 0000000..a4b1b07 --- /dev/null +++ b/arch/arm/kernel/pj4-cp0.c @@ -0,0 +1,94 @@ +/* + * linux/arch/arm/kernel/pj4-cp0.c + * + * PJ4 iWMMXt coprocessor context switching and handling + * + * Copyright (c) 2010 Marvell International Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/signal.h> +#include <linux/sched.h> +#include <linux/init.h> +#include <linux/io.h> +#include <asm/thread_notify.h> + +static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t) +{ + struct thread_info *thread = t; + + switch (cmd) { + case THREAD_NOTIFY_FLUSH: + /* + * flush_thread() zeroes thread->fpstate, so no need + * to do anything here. + * + * FALLTHROUGH: Ensure we don't try to overwrite our newly + * initialised state information on the first fault. + */ + + case THREAD_NOTIFY_EXIT: + iwmmxt_task_release(thread); + break; + + case THREAD_NOTIFY_SWITCH: + iwmmxt_task_switch(thread); + break; + } + + return NOTIFY_DONE; +} + +static struct notifier_block iwmmxt_notifier_block = { + .notifier_call = iwmmxt_do, +}; + + +static u32 __init pj4_cp_access_read(void) +{ + u32 value; + + __asm__ __volatile__ ( + "mrc p15, 0, %0, c1, c0, 2\n\t" + : "=r" (value)); + return value; +} + +static void __init pj4_cp_access_write(u32 value) +{ + u32 temp; + + __asm__ __volatile__ ( + "mcr p15, 0, %1, c1, c0, 2\n\t" + "mrc p15, 0, %0, c1, c0, 2\n\t" + "mov %0, %0\n\t" + "sub pc, pc, #4\n\t" + : "=r" (temp) : "r" (value)); +} + + +/* + * Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy + * switch code handle iWMMXt context switching. + */ +static int __init pj4_cp0_init(void) +{ + u32 cp_access; + + cp_access = pj4_cp_access_read() & ~0xf; + pj4_cp_access_write(cp_access); + + printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n"); + elf_hwcap |= HWCAP_IWMMXT; + thread_register_notifier(&iwmmxt_notifier_block); + + return 0; +} + +late_initcall(pj4_cp0_init); diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 3e97483..19c6816 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -1060,8 +1060,8 @@ static int ptrace_sethbpregs(struct task_struct *tsk, long num, goto out; if ((gen_type & implied_type) != gen_type) { - ret = -EINVAL; - goto out; + ret = -EINVAL; + goto out; } attr.bp_len = gen_len; diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index 90fe9ab..08e5c87 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -17,6 +17,7 @@ #include <linux/kernel.h> #include <linux/compiler.h> #include <linux/io.h> +#include <linux/dma-mapping.h> #include <linux/serial_core.h> #include <linux/serial_8250.h> #include <linux/platform_device.h> @@ -108,10 +109,63 @@ static void __init cns3420_early_serial_setup(void) } /* + * USB + */ +static struct resource cns3xxx_usb_ehci_resources[] = { + [0] = { + .start = CNS3XXX_USB_BASE, + .end = CNS3XXX_USB_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CNS3XXX_USB_EHCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device cns3xxx_usb_ehci_device = { + .name = "cns3xxx-ehci", + .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources), + .resource = cns3xxx_usb_ehci_resources, + .dev = { + .dma_mask = &cns3xxx_usb_ehci_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource cns3xxx_usb_ohci_resources[] = { + [0] = { + .start = CNS3XXX_USB_OHCI_BASE, + .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CNS3XXX_USB_OHCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device cns3xxx_usb_ohci_device = { + .name = "cns3xxx-ohci", + .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources), + .resource = cns3xxx_usb_ohci_resources, + .dev = { + .dma_mask = &cns3xxx_usb_ohci_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +/* * Initialization */ static struct platform_device *cns3420_pdevs[] __initdata = { &cns3420_nor_pdev, + &cns3xxx_usb_ehci_device, + &cns3xxx_usb_ohci_device, }; static void __init cns3420_init(void) diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h index ef9e511..ffeb3a8 100644 --- a/arch/arm/mach-cns3xxx/core.h +++ b/arch/arm/mach-cns3xxx/core.h @@ -16,7 +16,5 @@ extern struct sys_timer cns3xxx_timer; void __init cns3xxx_map_io(void); void __init cns3xxx_init_irq(void); void cns3xxx_power_off(void); -void cns3xxx_pwr_power_up(unsigned int block); -void cns3xxx_pwr_power_down(unsigned int block); #endif /* __CNS3XXX_CORE_H */ diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c index 50b4d31..79d1fb0 100644 --- a/arch/arm/mach-cns3xxx/devices.c +++ b/arch/arm/mach-cns3xxx/devices.c @@ -18,6 +18,7 @@ #include <linux/platform_device.h> #include <mach/cns3xxx.h> #include <mach/irqs.h> +#include <mach/pm.h> #include "core.h" #include "devices.h" diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h index 6dbce13..191c8e5 100644 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h @@ -165,7 +165,6 @@ #define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000 #define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ -#define CNS3XXX_USB_BASE_VIRT 0xFFF16000 #define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ #define CNS3XXX_SATA2_SIZE SZ_16M @@ -184,7 +183,6 @@ #define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000 #define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ -#define CNS3XXX_USB_OHCI_BASE_VIRT 0xFFF1C000 #define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ #define CNS3XXX_L2C_BASE_VIRT 0xFFF27000 diff --git a/arch/arm/mach-cns3xxx/include/mach/pm.h b/arch/arm/mach-cns3xxx/include/mach/pm.h new file mode 100644 index 0000000..6eae7f7 --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/pm.h @@ -0,0 +1,23 @@ +/* + * Copyright 2000 Deep Blue Solutions Ltd + * Copyright 2004 ARM Limited + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __CNS3XXX_PM_H +#define __CNS3XXX_PM_H + +#include <asm/atomic.h> + +void cns3xxx_pwr_clk_en(unsigned int block); +void cns3xxx_pwr_clk_dis(unsigned int block); +void cns3xxx_pwr_power_up(unsigned int block); +void cns3xxx_pwr_power_down(unsigned int block); + +extern atomic_t usb_pwr_ref; + +#endif /* __CNS3XXX_PM_H */ diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c index 38e4470..5e57955 100644 --- a/arch/arm/mach-cns3xxx/pm.c +++ b/arch/arm/mach-cns3xxx/pm.c @@ -6,10 +6,14 @@ * published by the Free Software Foundation. */ +#include <linux/init.h> +#include <linux/module.h> #include <linux/io.h> #include <linux/delay.h> +#include <asm/atomic.h> #include <mach/system.h> #include <mach/cns3xxx.h> +#include <mach/pm.h> void cns3xxx_pwr_clk_en(unsigned int block) { @@ -18,6 +22,16 @@ void cns3xxx_pwr_clk_en(unsigned int block) reg |= (block & PM_CLK_GATE_REG_MASK); __raw_writel(reg, PM_CLK_GATE_REG); } +EXPORT_SYMBOL(cns3xxx_pwr_clk_en); + +void cns3xxx_pwr_clk_dis(unsigned int block) +{ + u32 reg = __raw_readl(PM_CLK_GATE_REG); + + reg &= ~(block & PM_CLK_GATE_REG_MASK); + __raw_writel(reg, PM_CLK_GATE_REG); +} +EXPORT_SYMBOL(cns3xxx_pwr_clk_dis); void cns3xxx_pwr_power_up(unsigned int block) { @@ -29,6 +43,7 @@ void cns3xxx_pwr_power_up(unsigned int block) /* Wait for 300us for the PLL output clock locked. */ udelay(300); }; +EXPORT_SYMBOL(cns3xxx_pwr_power_up); void cns3xxx_pwr_power_down(unsigned int block) { @@ -38,6 +53,7 @@ void cns3xxx_pwr_power_down(unsigned int block) reg |= (block & CNS3XXX_PWR_PLL_ALL); __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); }; +EXPORT_SYMBOL(cns3xxx_pwr_power_down); static void cns3xxx_pwr_soft_rst_force(unsigned int block) { @@ -51,11 +67,13 @@ static void cns3xxx_pwr_soft_rst_force(unsigned int block) reg &= ~(block & PM_SOFT_RST_REG_MASK); } else { reg &= ~(block & PM_SOFT_RST_REG_MASK); + __raw_writel(reg, PM_SOFT_RST_REG); reg |= (block & PM_SOFT_RST_REG_MASK); } __raw_writel(reg, PM_SOFT_RST_REG); } +EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force); void cns3xxx_pwr_soft_rst(unsigned int block) { @@ -69,6 +87,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block) } cns3xxx_pwr_soft_rst_force(block); } +EXPORT_SYMBOL(cns3xxx_pwr_soft_rst); void arch_reset(char mode, const char *cmd) { @@ -99,3 +118,7 @@ int cns3xxx_cpu_clock(void) return cpu; } +EXPORT_SYMBOL(cns3xxx_cpu_clock); + +atomic_t usb_pwr_ref = ATOMIC_INIT(0); +EXPORT_SYMBOL(usb_pwr_ref); diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index b77b860..32f1479 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -61,6 +61,8 @@ config MACH_DAVINCI_EVM bool "TI DM644x EVM" default ARCH_DAVINCI_DM644x depends on ARCH_DAVINCI_DM644x + select MISC_DEVICES + select EEPROM_AT24 help Configure this option to specify the whether the board used for development is a DM644x EVM @@ -68,6 +70,8 @@ config MACH_DAVINCI_EVM config MACH_SFFSDR bool "Lyrtech SFFSDR" depends on ARCH_DAVINCI_DM644x + select MISC_DEVICES + select EEPROM_AT24 help Say Y here to select the Lyrtech Small Form Factor Software Defined Radio (SFFSDR) board. @@ -99,6 +103,8 @@ config MACH_DAVINCI_DM6467_EVM default ARCH_DAVINCI_DM646x depends on ARCH_DAVINCI_DM646x select MACH_DAVINCI_DM6467TEVM + select MISC_DEVICES + select EEPROM_AT24 help Configure this option to specify the whether the board used for development is a DM6467 EVM @@ -110,6 +116,8 @@ config MACH_DAVINCI_DM365_EVM bool "TI DM365 EVM" default ARCH_DAVINCI_DM365 depends on ARCH_DAVINCI_DM365 + select MISC_DEVICES + select EEPROM_AT24 help Configure this option to specify whether the board used for development is a DM365 EVM @@ -119,6 +127,8 @@ config MACH_DAVINCI_DA830_EVM default ARCH_DAVINCI_DA830 depends on ARCH_DAVINCI_DA830 select GPIO_PCF857X + select MISC_DEVICES + select EEPROM_AT24 help Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. @@ -148,7 +158,6 @@ config MACH_DAVINCI_DA850_EVM bool "TI DA850/OMAP-L138/AM18x Reference Platform" default ARCH_DAVINCI_DA850 depends on ARCH_DAVINCI_DA850 - select GPIO_PCA953X help Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module. @@ -178,6 +187,12 @@ config DA850_UI_RMII endchoice +config GPIO_PCA953X + default MACH_DAVINCI_DA850_EVM + +config KEYBOARD_GPIO_POLLED + default MACH_DAVINCI_DA850_EVM + config MACH_TNETV107X bool "TI TNETV107X Reference Platform" default ARCH_DAVINCI_TNETV107X @@ -188,6 +203,8 @@ config MACH_TNETV107X config MACH_MITYOMAPL138 bool "Critical Link MityDSP-L138/MityARM-1808 SoM" depends on ARCH_DAVINCI_DA850 + select MISC_DEVICES + select EEPROM_AT24 help Say Y here to select the Critical Link MityDSP-L138/MityARM-1808 System on Module. Information on this SoM may be found at diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c index 9c3f500..1ce70a9 100644 --- a/arch/arm/mach-davinci/aemif.c +++ b/arch/arm/mach-davinci/aemif.c @@ -90,7 +90,7 @@ int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, void __iomem *base, unsigned cs) { unsigned set, val; - unsigned ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; + int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; unsigned offset = A1CR_OFFSET + cs * 4; struct clk *aemif_clk; unsigned long clkrate; diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index c6e11c6..b01fb2a 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -17,8 +17,10 @@ #include <linux/i2c.h> #include <linux/i2c/at24.h> #include <linux/i2c/pca953x.h> +#include <linux/input.h> #include <linux/mfd/tps6507x.h> #include <linux/gpio.h> +#include <linux/gpio_keys.h> #include <linux/platform_device.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> @@ -266,34 +268,115 @@ static inline void da850_evm_setup_emac_rmii(int rmii_sel) struct davinci_soc_info *soc_info = &davinci_soc_info; soc_info->emac_pdata->rmii_en = 1; - gpio_set_value(rmii_sel, 0); + gpio_set_value_cansleep(rmii_sel, 0); } #else static inline void da850_evm_setup_emac_rmii(int rmii_sel) { } #endif + +#define DA850_KEYS_DEBOUNCE_MS 10 +/* + * At 200ms polling interval it is possible to miss an + * event by tapping very lightly on the push button but most + * pushes do result in an event; longer intervals require the + * user to hold the button whereas shorter intervals require + * more CPU time for polling. + */ +#define DA850_GPIO_KEYS_POLL_MS 200 + +enum da850_evm_ui_exp_pins { + DA850_EVM_UI_EXP_SEL_C = 5, + DA850_EVM_UI_EXP_SEL_B, + DA850_EVM_UI_EXP_SEL_A, + DA850_EVM_UI_EXP_PB8, + DA850_EVM_UI_EXP_PB7, + DA850_EVM_UI_EXP_PB6, + DA850_EVM_UI_EXP_PB5, + DA850_EVM_UI_EXP_PB4, + DA850_EVM_UI_EXP_PB3, + DA850_EVM_UI_EXP_PB2, + DA850_EVM_UI_EXP_PB1, +}; + +static const char const *da850_evm_ui_exp[] = { + [DA850_EVM_UI_EXP_SEL_C] = "sel_c", + [DA850_EVM_UI_EXP_SEL_B] = "sel_b", + [DA850_EVM_UI_EXP_SEL_A] = "sel_a", + [DA850_EVM_UI_EXP_PB8] = "pb8", + [DA850_EVM_UI_EXP_PB7] = "pb7", + [DA850_EVM_UI_EXP_PB6] = "pb6", + [DA850_EVM_UI_EXP_PB5] = "pb5", + [DA850_EVM_UI_EXP_PB4] = "pb4", + [DA850_EVM_UI_EXP_PB3] = "pb3", + [DA850_EVM_UI_EXP_PB2] = "pb2", + [DA850_EVM_UI_EXP_PB1] = "pb1", +}; + +#define DA850_N_UI_PB 8 + +static struct gpio_keys_button da850_evm_ui_keys[] = { + [0 ... DA850_N_UI_PB - 1] = { + .type = EV_KEY, + .active_low = 1, + .wakeup = 0, + .debounce_interval = DA850_KEYS_DEBOUNCE_MS, + .code = -1, /* assigned at runtime */ + .gpio = -1, /* assigned at runtime */ + .desc = NULL, /* assigned at runtime */ + }, +}; + +static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = { + .buttons = da850_evm_ui_keys, + .nbuttons = ARRAY_SIZE(da850_evm_ui_keys), + .poll_interval = DA850_GPIO_KEYS_POLL_MS, +}; + +static struct platform_device da850_evm_ui_keys_device = { + .name = "gpio-keys-polled", + .id = 0, + .dev = { + .platform_data = &da850_evm_ui_keys_pdata + }, +}; + +static void da850_evm_ui_keys_init(unsigned gpio) +{ + int i; + struct gpio_keys_button *button; + + for (i = 0; i < DA850_N_UI_PB; i++) { + button = &da850_evm_ui_keys[i]; + button->code = KEY_F8 - i; + button->desc = (char *) + da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i]; + button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i; + } +} + static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, unsigned ngpio, void *c) { int sel_a, sel_b, sel_c, ret; - sel_a = gpio + 7; - sel_b = gpio + 6; - sel_c = gpio + 5; + sel_a = gpio + DA850_EVM_UI_EXP_SEL_A; + sel_b = gpio + DA850_EVM_UI_EXP_SEL_B; + sel_c = gpio + DA850_EVM_UI_EXP_SEL_C; - ret = gpio_request(sel_a, "sel_a"); + ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]); if (ret) { pr_warning("Cannot open UI expander pin %d\n", sel_a); goto exp_setup_sela_fail; } - ret = gpio_request(sel_b, "sel_b"); + ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]); if (ret) { pr_warning("Cannot open UI expander pin %d\n", sel_b); goto exp_setup_selb_fail; } - ret = gpio_request(sel_c, "sel_c"); + ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]); if (ret) { pr_warning("Cannot open UI expander pin %d\n", sel_c); goto exp_setup_selc_fail; @@ -304,6 +387,13 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, gpio_direction_output(sel_b, 1); gpio_direction_output(sel_c, 1); + da850_evm_ui_keys_init(gpio); + ret = platform_device_register(&da850_evm_ui_keys_device); + if (ret) { + pr_warning("Could not register UI GPIO expander push-buttons"); + goto exp_setup_keys_fail; + } + ui_card_detected = 1; pr_info("DA850/OMAP-L138 EVM UI card detected\n"); @@ -313,6 +403,8 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, return 0; +exp_setup_keys_fail: + gpio_free(sel_c); exp_setup_selc_fail: gpio_free(sel_b); exp_setup_selb_fail: @@ -324,14 +416,192 @@ exp_setup_sela_fail: static int da850_evm_ui_expander_teardown(struct i2c_client *client, unsigned gpio, unsigned ngpio, void *c) { + platform_device_unregister(&da850_evm_ui_keys_device); + /* deselect all functionalities */ - gpio_set_value(gpio + 5, 1); - gpio_set_value(gpio + 6, 1); - gpio_set_value(gpio + 7, 1); + gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1); + gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1); + gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1); + + gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C); + gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B); + gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A); + + return 0; +} + +/* assign the baseboard expander's GPIOs after the UI board's */ +#define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp) +#define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS) + +enum da850_evm_bb_exp_pins { + DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0, + DA850_EVM_BB_EXP_SW_RST, + DA850_EVM_BB_EXP_TP_23, + DA850_EVM_BB_EXP_TP_22, + DA850_EVM_BB_EXP_TP_21, + DA850_EVM_BB_EXP_USER_PB1, + DA850_EVM_BB_EXP_USER_LED2, + DA850_EVM_BB_EXP_USER_LED1, + DA850_EVM_BB_EXP_USER_SW1, + DA850_EVM_BB_EXP_USER_SW2, + DA850_EVM_BB_EXP_USER_SW3, + DA850_EVM_BB_EXP_USER_SW4, + DA850_EVM_BB_EXP_USER_SW5, + DA850_EVM_BB_EXP_USER_SW6, + DA850_EVM_BB_EXP_USER_SW7, + DA850_EVM_BB_EXP_USER_SW8 +}; + +static const char const *da850_evm_bb_exp[] = { + [DA850_EVM_BB_EXP_DEEP_SLEEP_EN] = "deep_sleep_en", + [DA850_EVM_BB_EXP_SW_RST] = "sw_rst", + [DA850_EVM_BB_EXP_TP_23] = "tp_23", + [DA850_EVM_BB_EXP_TP_22] = "tp_22", + [DA850_EVM_BB_EXP_TP_21] = "tp_21", + [DA850_EVM_BB_EXP_USER_PB1] = "user_pb1", + [DA850_EVM_BB_EXP_USER_LED2] = "user_led2", + [DA850_EVM_BB_EXP_USER_LED1] = "user_led1", + [DA850_EVM_BB_EXP_USER_SW1] = "user_sw1", + [DA850_EVM_BB_EXP_USER_SW2] = "user_sw2", + [DA850_EVM_BB_EXP_USER_SW3] = "user_sw3", + [DA850_EVM_BB_EXP_USER_SW4] = "user_sw4", + [DA850_EVM_BB_EXP_USER_SW5] = "user_sw5", + [DA850_EVM_BB_EXP_USER_SW6] = "user_sw6", + [DA850_EVM_BB_EXP_USER_SW7] = "user_sw7", + [DA850_EVM_BB_EXP_USER_SW8] = "user_sw8", +}; + +#define DA850_N_BB_USER_SW 8 + +static struct gpio_keys_button da850_evm_bb_keys[] = { + [0] = { + .type = EV_KEY, + .active_low = 1, + .wakeup = 0, + .debounce_interval = DA850_KEYS_DEBOUNCE_MS, + .code = KEY_PROG1, + .desc = NULL, /* assigned at runtime */ + .gpio = -1, /* assigned at runtime */ + }, + [1 ... DA850_N_BB_USER_SW] = { + .type = EV_SW, + .active_low = 1, + .wakeup = 0, + .debounce_interval = DA850_KEYS_DEBOUNCE_MS, + .code = -1, /* assigned at runtime */ + .desc = NULL, /* assigned at runtime */ + .gpio = -1, /* assigned at runtime */ + }, +}; + +static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = { + .buttons = da850_evm_bb_keys, + .nbuttons = ARRAY_SIZE(da850_evm_bb_keys), + .poll_interval = DA850_GPIO_KEYS_POLL_MS, +}; + +static struct platform_device da850_evm_bb_keys_device = { + .name = "gpio-keys-polled", + .id = 1, + .dev = { + .platform_data = &da850_evm_bb_keys_pdata + }, +}; + +static void da850_evm_bb_keys_init(unsigned gpio) +{ + int i; + struct gpio_keys_button *button; + + button = &da850_evm_bb_keys[0]; + button->desc = (char *) + da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1]; + button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1; + + for (i = 0; i < DA850_N_BB_USER_SW; i++) { + button = &da850_evm_bb_keys[i + 1]; + button->code = SW_LID + i; + button->desc = (char *) + da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i]; + button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i; + } +} - gpio_free(gpio + 5); - gpio_free(gpio + 6); - gpio_free(gpio + 7); +#define DA850_N_BB_USER_LED 2 + +static struct gpio_led da850_evm_bb_leds[] = { + [0 ... DA850_N_BB_USER_LED - 1] = { + .active_low = 1, + .gpio = -1, /* assigned at runtime */ + .name = NULL, /* assigned at runtime */ + }, +}; + +static struct gpio_led_platform_data da850_evm_bb_leds_pdata = { + .leds = da850_evm_bb_leds, + .num_leds = ARRAY_SIZE(da850_evm_bb_leds), +}; + +static struct platform_device da850_evm_bb_leds_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &da850_evm_bb_leds_pdata + } +}; + +static void da850_evm_bb_leds_init(unsigned gpio) +{ + int i; + struct gpio_led *led; + + for (i = 0; i < DA850_N_BB_USER_LED; i++) { + led = &da850_evm_bb_leds[i]; + + led->gpio = gpio + DA850_EVM_BB_EXP_USER_LED2 + i; + led->name = + da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_LED2 + i]; + } +} + +static int da850_evm_bb_expander_setup(struct i2c_client *client, + unsigned gpio, unsigned ngpio, + void *c) +{ + int ret; + + /* + * Register the switches and pushbutton on the baseboard as a gpio-keys + * device. + */ + da850_evm_bb_keys_init(gpio); + ret = platform_device_register(&da850_evm_bb_keys_device); + if (ret) { + pr_warning("Could not register baseboard GPIO expander keys"); + goto io_exp_setup_sw_fail; + } + + da850_evm_bb_leds_init(gpio); + ret = platform_device_register(&da850_evm_bb_leds_device); + if (ret) { + pr_warning("Could not register baseboard GPIO expander LEDS"); + goto io_exp_setup_leds_fail; + } + + return 0; + +io_exp_setup_leds_fail: + platform_device_unregister(&da850_evm_bb_keys_device); +io_exp_setup_sw_fail: + return ret; +} + +static int da850_evm_bb_expander_teardown(struct i2c_client *client, + unsigned gpio, unsigned ngpio, void *c) +{ + platform_device_unregister(&da850_evm_bb_leds_device); + platform_device_unregister(&da850_evm_bb_keys_device); return 0; } @@ -340,6 +610,14 @@ static struct pca953x_platform_data da850_evm_ui_expander_info = { .gpio_base = DAVINCI_N_GPIO, .setup = da850_evm_ui_expander_setup, .teardown = da850_evm_ui_expander_teardown, + .names = da850_evm_ui_exp, +}; + +static struct pca953x_platform_data da850_evm_bb_expander_info = { + .gpio_base = DA850_BB_EXPANDER_GPIO_BASE, + .setup = da850_evm_bb_expander_setup, + .teardown = da850_evm_bb_expander_teardown, + .names = da850_evm_bb_exp, }; static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { @@ -350,6 +628,10 @@ static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { I2C_BOARD_INFO("tca6416", 0x20), .platform_data = &da850_evm_ui_expander_info, }, + { + I2C_BOARD_INFO("tca6416", 0x21), + .platform_data = &da850_evm_bb_expander_info, + }, }; static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = { @@ -540,7 +822,7 @@ static struct regulator_init_data tps65070_regulator_data[] = { { .constraints = { .min_uV = 950000, - .max_uV = 1320000, + .max_uV = 1350000, .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS), .boot_on = 1, @@ -591,7 +873,7 @@ static struct tps6507x_board tps_board = { .tps6507x_ts_init_data = &tps6507x_touchscreen_data, }; -static struct i2c_board_info __initdata da850evm_tps65070_info[] = { +static struct i2c_board_info __initdata da850_evm_tps65070_info[] = { { I2C_BOARD_INFO("tps6507x", 0x48), .platform_data = &tps_board, @@ -600,8 +882,8 @@ static struct i2c_board_info __initdata da850evm_tps65070_info[] = { static int __init pmic_tps65070_init(void) { - return i2c_register_board_info(1, da850evm_tps65070_info, - ARRAY_SIZE(da850evm_tps65070_info)); + return i2c_register_board_info(1, da850_evm_tps65070_info, + ARRAY_SIZE(da850_evm_tps65070_info)); } static const short da850_evm_lcdc_pins[] = { @@ -736,6 +1018,27 @@ static struct edma_rsv_info *da850_edma_rsv[2] = { &da850_edma_cc1_rsv, }; +#ifdef CONFIG_CPU_FREQ +static __init int da850_evm_init_cpufreq(void) +{ + switch (system_rev & 0xF) { + case 3: + da850_max_speed = 456000; + break; + case 2: + da850_max_speed = 408000; + break; + case 1: + da850_max_speed = 372000; + break; + } + + return da850_register_cpufreq("pll0_sysclk3"); +} +#else +static __init int da850_evm_init_cpufreq(void) { return 0; } +#endif + static __init void da850_evm_init(void) { int ret; @@ -836,7 +1139,7 @@ static __init void da850_evm_init(void) if (ret) pr_warning("da850_evm_init: rtc setup failed: %d\n", ret); - ret = da850_register_cpufreq("pll0_sysclk3"); + ret = da850_evm_init_cpufreq(); if (ret) pr_warning("da850_evm_init: cpufreq registration failed: %d\n", ret); diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 01ba080..e4e3af1 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -336,7 +336,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) ratio--; } - if (ratio > PLLDIV_RATIO_MASK) + if (ratio > pll->div_ratio_mask) return -EINVAL; do { @@ -344,7 +344,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) } while (v & PLLSTAT_GOSTAT); v = __raw_readl(pll->base + clk->div_reg); - v &= ~PLLDIV_RATIO_MASK; + v &= ~pll->div_ratio_mask; v |= ratio | PLLDIV_EN; __raw_writel(v, pll->base + clk->div_reg); diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 63916b9..78b5ae2 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -830,8 +830,7 @@ static void da850_set_async3_src(int pllnum) * According to the TRM, minimum PLLM results in maximum power savings. * The OPP definitions below should keep the PLLM as low as possible. * - * The output of the PLLM must be between 400 to 600 MHz. - * This rules out prediv of anything but divide-by-one for 24Mhz OSC input. + * The output of the PLLM must be between 300 to 600 MHz. */ struct da850_opp { unsigned int freq; /* in KHz */ @@ -842,6 +841,33 @@ struct da850_opp { unsigned int cvdd_max; /* in uV */ }; +static const struct da850_opp da850_opp_456 = { + .freq = 456000, + .prediv = 1, + .mult = 19, + .postdiv = 1, + .cvdd_min = 1300000, + .cvdd_max = 1350000, +}; + +static const struct da850_opp da850_opp_408 = { + .freq = 408000, + .prediv = 1, + .mult = 17, + .postdiv = 1, + .cvdd_min = 1300000, + .cvdd_max = 1350000, +}; + +static const struct da850_opp da850_opp_372 = { + .freq = 372000, + .prediv = 2, + .mult = 31, + .postdiv = 1, + .cvdd_min = 1200000, + .cvdd_max = 1320000, +}; + static const struct da850_opp da850_opp_300 = { .freq = 300000, .prediv = 1, @@ -876,6 +902,9 @@ static const struct da850_opp da850_opp_96 = { } static struct cpufreq_frequency_table da850_freq_table[] = { + OPP(456), + OPP(408), + OPP(372), OPP(300), OPP(200), OPP(96), @@ -886,6 +915,19 @@ static struct cpufreq_frequency_table da850_freq_table[] = { }; #ifdef CONFIG_REGULATOR +static int da850_set_voltage(unsigned int index); +static int da850_regulator_init(void); +#endif + +static struct davinci_cpufreq_config cpufreq_info = { + .freq_table = da850_freq_table, +#ifdef CONFIG_REGULATOR + .init = da850_regulator_init, + .set_voltage = da850_set_voltage, +#endif +}; + +#ifdef CONFIG_REGULATOR static struct regulator *cvdd; static int da850_set_voltage(unsigned int index) @@ -895,7 +937,7 @@ static int da850_set_voltage(unsigned int index) if (!cvdd) return -ENODEV; - opp = (struct da850_opp *) da850_freq_table[index].index; + opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); } @@ -912,14 +954,6 @@ static int da850_regulator_init(void) } #endif -static struct davinci_cpufreq_config cpufreq_info = { - .freq_table = &da850_freq_table[0], -#ifdef CONFIG_REGULATOR - .init = da850_regulator_init, - .set_voltage = da850_set_voltage, -#endif -}; - static struct platform_device da850_cpufreq_device = { .name = "cpufreq-davinci", .dev = { @@ -928,12 +962,22 @@ static struct platform_device da850_cpufreq_device = { .id = -1, }; +unsigned int da850_max_speed = 300000; + int __init da850_register_cpufreq(char *async_clk) { + int i; + /* cpufreq driver can help keep an "async" clock constant */ if (async_clk) clk_add_alias("async", da850_cpufreq_device.name, async_clk, NULL); + for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) { + if (da850_freq_table[i].frequency <= da850_max_speed) { + cpufreq_info.freq_table = &da850_freq_table[i]; + break; + } + } return platform_device_register(&da850_cpufreq_device); } @@ -942,17 +986,18 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate) { int i, ret = 0, diff; unsigned int best = (unsigned int) -1; + struct cpufreq_frequency_table *table = cpufreq_info.freq_table; rate /= 1000; /* convert to kHz */ - for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { - diff = da850_freq_table[i].frequency - rate; + for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) { + diff = table[i].frequency - rate; if (diff < 0) diff = -diff; if (diff < best) { best = diff; - ret = da850_freq_table[i].frequency; + ret = table[i].frequency; } } @@ -973,7 +1018,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index) struct pll_data *pll = clk->pll_data; int ret; - opp = (struct da850_opp *) da850_freq_table[index].index; + opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; prediv = opp->prediv; mult = opp->mult; postdiv = opp->postdiv; diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c index c9a86d8..85503deb 100644 --- a/arch/arm/mach-davinci/devices-tnetv107x.c +++ b/arch/arm/mach-davinci/devices-tnetv107x.c @@ -344,7 +344,20 @@ static struct platform_device tsc_device = { void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) { - int i; + int i, error; + struct clk *tsc_clk; + + /* + * The reset defaults for tnetv107x tsc clock divider is set too high. + * This forces the clock down to a range that allows the ADC to + * complete sample conversion in time. + */ + tsc_clk = clk_get(NULL, "sys_tsc_clk"); + if (tsc_clk) { + error = clk_set_rate(tsc_clk, 5000000); + WARN_ON(error < 0); + clk_put(tsc_clk); + } platform_device_register(&edma_device); platform_device_register(&tnetv107x_wdt_device); diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 4247b3f..e7f9520 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -28,6 +28,13 @@ extern void __iomem *da8xx_syscfg0_base; extern void __iomem *da8xx_syscfg1_base; /* + * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade + * (than the regular 300Mhz variant), the board code should set this up + * with the supported speed before calling da850_register_cpufreq(). + */ +extern unsigned int da850_max_speed; + +/* * The cp_intc interrupt controller for the da8xx isn't in the same * chunk of physical memory space as the other registers (like it is * on the davincis) so it needs to be mapped separately. It will be diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index 1b15dbd..a415804 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -83,21 +83,16 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr, pdctl1 = __raw_readl(psc_base + PDCTL1); pdctl1 |= 0x100; __raw_writel(pdctl1, psc_base + PDCTL1); - - do { - ptstat = __raw_readl(psc_base + - PTSTAT); - } while (!(((ptstat >> domain) & 1) == 0)); } else { ptcmd = 1 << domain; __raw_writel(ptcmd, psc_base + PTCMD); - - do { - ptstat = __raw_readl(psc_base + PTSTAT); - } while (!(((ptstat >> domain) & 1) == 0)); } do { + ptstat = __raw_readl(psc_base + PTSTAT); + } while (!(((ptstat >> domain) & 1) == 0)); + + do { mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); } while (!((mdstat & MDSTAT_STATE_MASK) == next_state)); diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index c148671..e1969ce 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -272,14 +272,35 @@ static cycle_t read_cycles(struct clocksource *cs) return (cycles_t)timer32_read(t); } +/* + * Kernel assumes that sched_clock can be called early but may not have + * things ready yet. + */ +static cycle_t read_dummy(struct clocksource *cs) +{ + return 0; +} + + static struct clocksource clocksource_davinci = { .rating = 300, - .read = read_cycles, + .read = read_dummy, .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; /* + * Overwrite weak default sched_clock with something more precise + */ +unsigned long long notrace sched_clock(void) +{ + const cycle_t cyc = clocksource_davinci.read(&clocksource_davinci); + + return clocksource_cyc2ns(cyc, clocksource_davinci.mult, + clocksource_davinci.shift); +} + +/* * clockevent */ static int davinci_set_next_event(unsigned long cycles, @@ -376,6 +397,7 @@ static void __init davinci_timer_init(void) davinci_clock_tick_rate = clk_get_rate(timer_clk); /* setup clocksource */ + clocksource_davinci.read = read_cycles; clocksource_davinci.name = id_to_name[clocksource_id]; if (clocksource_register_hz(&clocksource_davinci, davinci_clock_tick_rate)) diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c index daeae06..6fcdece 100644 --- a/arch/arm/mach-davinci/tnetv107x.c +++ b/arch/arm/mach-davinci/tnetv107x.c @@ -131,12 +131,13 @@ define_pll_clk(tdm, 1, 0x0ff, 0x200); define_pll_clk(eth, 2, 0x0ff, 0x400); /* Level 2 - divided outputs from the PLLs */ -#define define_pll_div_clk(pll, cname, div) \ - static struct clk pll##_##cname##_clk = { \ - .name = #pll "_" #cname "_clk",\ - .parent = &pll_##pll##_clk, \ - .flags = CLK_PLL, \ - .div_reg = PLLDIV##div, \ +#define define_pll_div_clk(pll, cname, div) \ + static struct clk pll##_##cname##_clk = { \ + .name = #pll "_" #cname "_clk", \ + .parent = &pll_##pll##_clk, \ + .flags = CLK_PLL, \ + .div_reg = PLLDIV##div, \ + .set_rate = davinci_set_sysclk_rate, \ } define_pll_div_clk(sys, arm1176, 1); @@ -192,6 +193,7 @@ lpsc_clk_enabled(system, sys_half_clk, SYSTEM); lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST); lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST); lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM); +lpsc_clk_enabled(timer1, sys_half_clk, TIMER1); lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE); lpsc_clk(ethss, eth_125mhz_clk, ETHSS); @@ -205,16 +207,15 @@ lpsc_clk(mdio, sys_half_clk, MDIO); lpsc_clk(sdio0, sys_half_clk, SDIO0); lpsc_clk(sdio1, sys_half_clk, SDIO1); lpsc_clk(timer0, sys_half_clk, TIMER0); -lpsc_clk(timer1, sys_half_clk, TIMER1); lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP); lpsc_clk(ssp, sys_half_clk, SSP); lpsc_clk(tdm0, tdm_0_clk, TDM0); lpsc_clk(tdm1, tdm_1_clk, TDM1); lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ); lpsc_clk(mcdma, sys_half_clk, MCDMA); -lpsc_clk(usb0, sys_half_clk, USB0); -lpsc_clk(usb1, sys_half_clk, USB1); lpsc_clk(usbss, sys_half_clk, USBSS); +lpsc_clk(usb0, clk_usbss, USB0); +lpsc_clk(usb1, clk_usbss, USB1); lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII); lpsc_clk(imcop, sys_dsp_clk, IMCOP); lpsc_clk(spare, sys_half_clk, SPARE); @@ -281,7 +282,9 @@ static struct clk_lookup clks[] = { CLK(NULL, "clk_tdm0", &clk_tdm0), CLK(NULL, "clk_vlynq", &clk_vlynq), CLK(NULL, "clk_mcdma", &clk_mcdma), + CLK(NULL, "clk_usbss", &clk_usbss), CLK(NULL, "clk_usb0", &clk_usb0), + CLK(NULL, "clk_usb1", &clk_usb1), CLK(NULL, "clk_tdm1", &clk_tdm1), CLK(NULL, "clk_debugss", &clk_debugss), CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii), @@ -289,8 +292,6 @@ static struct clk_lookup clks[] = { CLK(NULL, "clk_imcop", &clk_imcop), CLK(NULL, "clk_spare", &clk_spare), CLK("davinci_mmc.1", NULL, &clk_sdio1), - CLK(NULL, "clk_usb1", &clk_usb1), - CLK(NULL, "clk_usbss", &clk_usbss), CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst), CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst), CLK(NULL, NULL, NULL), diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index 3b9a32a..a4ed390 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig @@ -9,6 +9,12 @@ config MACH_DOVE_DB Say 'Y' here if you want your kernel to support the Marvell DB-MV88AP510 Development Board. + config MACH_CM_A510 + bool "CompuLab CM-A510 Board" + help + Say 'Y' here if you want your kernel to support the + CompuLab CM-A510 Board. + endmenu endif diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile index 7ab3be5..fa0f018 100644 --- a/arch/arm/mach-dove/Makefile +++ b/arch/arm/mach-dove/Makefile @@ -1,3 +1,4 @@ -obj-y += common.o addr-map.o irq.o pcie.o +obj-y += common.o addr-map.o irq.o pcie.o mpp.o obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o +obj-$(CONFIG_MACH_CM_A510) += cm-a510.o diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c new file mode 100644 index 0000000..96e0e94 --- /dev/null +++ b/arch/arm/mach-dove/cm-a510.c @@ -0,0 +1,95 @@ +/* + * arch/arm/mach-dove/cm-a510.c + * + * Copyright (C) 2010 CompuLab, Ltd. + * Konstantin Sinyuk <kostyas@compulab.co.il> + * + * Based on Marvell DB-MV88AP510-BP Development Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/dove.h> + +#include "common.h" + +static struct mv643xx_eth_platform_data cm_a510_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, +}; + +static struct mv_sata_platform_data cm_a510_sata_data = { + .n_ports = 1, +}; + +/* + * SPI Devices: + * SPI0: 1M Flash Winbond w25q32bv + */ +static const struct flash_platform_data cm_a510_spi_flash_data = { + .type = "w25q32bv", +}; + +static struct spi_board_info __initdata cm_a510_spi_flash_info[] = { + { + .modalias = "m25p80", + .platform_data = &cm_a510_spi_flash_data, + .irq = -1, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static int __init cm_a510_pci_init(void) +{ + if (machine_is_cm_a510()) + dove_pcie_init(1, 1); + + return 0; +} + +subsys_initcall(cm_a510_pci_init); + +/* Board Init */ +static void __init cm_a510_init(void) +{ + /* + * Basic Dove setup. Needs to be called early. + */ + dove_init(); + + dove_ge00_init(&cm_a510_ge00_data); + dove_ehci0_init(); + dove_ehci1_init(); + dove_sata_init(&cm_a510_sata_data); + dove_sdio0_init(); + dove_sdio1_init(); + dove_spi0_init(); + dove_spi1_init(); + dove_uart0_init(); + dove_uart1_init(); + dove_i2c_init(); + spi_register_board_info(cm_a510_spi_flash_info, + ARRAY_SIZE(cm_a510_spi_flash_info)); +} + +MACHINE_START(CM_A510, "Compulab CM-A510 Board") + .boot_params = 0x00000100, + .init_machine = cm_a510_init, + .map_io = dove_map_io, + .init_irq = dove_init_irq, + .timer = &dove_timer, +MACHINE_END diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index f6a0839..27b4145 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h @@ -131,14 +131,21 @@ #define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014) #define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018) #define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) +#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400) #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) #define DOVE_NAND_GPIO_EN (1 << 0) #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40) - +#define DOVE_SPI_GPIO_SEL (1 << 5) +#define DOVE_UART1_GPIO_SEL (1 << 4) +#define DOVE_AU1_GPIO_SEL (1 << 3) +#define DOVE_CAM_GPIO_SEL (1 << 2) +#define DOVE_SD1_GPIO_SEL (1 << 1) +#define DOVE_SD0_GPIO_SEL (1 << 0) /* Power Management */ #define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000) +#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c) /* Real Time Clock */ #define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500) diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h index 0ee70ff..340bb7a 100644 --- a/arch/arm/mach-dove/include/mach/gpio.h +++ b/arch/arm/mach-dove/include/mach/gpio.h @@ -14,12 +14,14 @@ #include <plat/gpio.h> #include <asm-generic/gpio.h> /* cansleep wrappers */ -#define GPIO_MAX 64 +#define GPIO_MAX 72 #define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00) #define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20) -#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI) +#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : \ + ((pin < 64) ? GPIO_BASE_HI : \ + DOVE_GPIO2_VIRT_BASE)) #define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00) #define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04) diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c new file mode 100644 index 0000000..71db2bd --- /dev/null +++ b/arch/arm/mach-dove/mpp.c @@ -0,0 +1,212 @@ +/* + * arch/arm/mach-dove/mpp.c + * + * MPP functions for Marvell Dove SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <linux/io.h> + +#include <mach/dove.h> + +#include "mpp.h" + +#define MPP_NR_REGS 4 +#define MPP_CTRL(i) ((i) == 3 ? \ + DOVE_MPP_CTRL4_VIRT_BASE : \ + DOVE_MPP_VIRT_BASE + (i) * 4) +#define PMU_SIG_REGS 2 +#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4) + +struct dove_mpp_grp { + int start; + int end; +}; + +static struct dove_mpp_grp dove_mpp_grp[] = { + [MPP_24_39] = { + .start = 24, + .end = 39, + }, + [MPP_40_45] = { + .start = 40, + .end = 45, + }, + [MPP_46_51] = { + .start = 40, + .end = 45, + }, + [MPP_58_61] = { + .start = 58, + .end = 61, + }, + [MPP_62_63] = { + .start = 62, + .end = 63, + }, +}; + +static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) +{ + int i; + + for (i = start; i <= end; i++) + orion_gpio_set_valid(i, gpio_mode); +} + +static void dove_mpp_dump_regs(void) +{ +#ifdef DEBUG + int i; + + pr_debug("MPP_CTRL regs:"); + for (i = 0; i < MPP_NR_REGS; i++) + printk(" %08x", readl(MPP_CTRL(i))); + printk("\n"); + + pr_debug("PMU_SIG_CTRL regs:"); + for (i = 0; i < PMU_SIG_REGS; i++) + printk(" %08x", readl(PMU_SIG_CTRL(i))); + printk("\n"); + + pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL)); + pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); +#endif +} + +static void dove_mpp_cfg_nfc(int sel) +{ + u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE); + + mpp_gen_cfg &= ~0x1; + mpp_gen_cfg |= sel; + writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE); + + dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK); +} + +static void dove_mpp_cfg_au1(int sel) +{ + u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); + u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); + u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); + u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); + + mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL); + ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1); + mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN); + global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO); + + if (!sel || sel == 0x2) + dove_mpp_gpio_mode(52, 57, 0); + else + dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK); + + if (sel & 0x1) { + global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO; + dove_mpp_gpio_mode(56, 57, 0); + } + if (sel & 0x2) { + mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN; + dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK); + } + if (sel & 0x4) { + ssp_ctrl1 |= DOVE_SSP_ON_AU1; + dove_mpp_gpio_mode(52, 55, 0); + } + if (sel & 0x8) + mpp_ctrl4 |= DOVE_AU1_GPIO_SEL; + + writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); + writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1); + writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE); + writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); +} + +static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl) +{ + int start = dove_mpp_grp[num].start; + int end = dove_mpp_grp[num].end; + int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0; + + *mpp_ctrl &= ~(0x1 << num); + *mpp_ctrl |= sel << num; + + dove_mpp_gpio_mode(start, end, gpio_mode); +} + +void __init dove_mpp_conf(unsigned int *mpp_list) +{ + u32 mpp_ctrl[MPP_NR_REGS]; + u32 pmu_mpp_ctrl = 0; + u32 pmu_sig_ctrl[PMU_SIG_REGS]; + int i; + + /* Initialize gpiolib. */ + orion_gpio_init(); + + for (i = 0; i < MPP_NR_REGS; i++) + mpp_ctrl[i] = readl(MPP_CTRL(i)); + + for (i = 0; i < PMU_SIG_REGS; i++) + pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i)); + + pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL); + + dove_mpp_dump_regs(); + + for ( ; *mpp_list != MPP_END; mpp_list++) { + unsigned int num = MPP_NUM(*mpp_list); + unsigned int sel = MPP_SEL(*mpp_list); + int shift, gpio_mode; + + if (num > MPP_MAX) { + pr_err("dove: invalid MPP number (%u)\n", num); + continue; + } + + if (*mpp_list & MPP_NFC_MASK) { + dove_mpp_cfg_nfc(sel); + continue; + } + + if (*mpp_list & MPP_AU1_MASK) { + dove_mpp_cfg_au1(sel); + continue; + } + + if (*mpp_list & MPP_GRP_MASK) { + dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]); + continue; + } + + shift = (num & 7) << 2; + if (*mpp_list & MPP_PMU_MASK) { + pmu_mpp_ctrl |= (0x1 << num); + pmu_sig_ctrl[num / 8] &= ~(0xf << shift); + pmu_sig_ctrl[num / 8] |= 0xf << shift; + gpio_mode = 0; + } else { + mpp_ctrl[num / 8] &= ~(0xf << shift); + mpp_ctrl[num / 8] |= sel << shift; + gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK; + } + + orion_gpio_set_valid(num, gpio_mode); + } + + for (i = 0; i < MPP_NR_REGS; i++) + writel(mpp_ctrl[i], MPP_CTRL(i)); + + for (i = 0; i < PMU_SIG_REGS; i++) + writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i)); + + writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL); + + dove_mpp_dump_regs(); +} diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h new file mode 100644 index 0000000..2a43ce4 --- /dev/null +++ b/arch/arm/mach-dove/mpp.h @@ -0,0 +1,220 @@ +#ifndef __ARCH_DOVE_MPP_CODED_H +#define __ARCH_DOVE_MPP_CODED_H + +#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \ +/* MPP/group number */ ((_num) & 0xff) | \ +/* MPP select value */ (((_mode) & 0xf) << 8) | \ +/* MPP PMU */ ((!!(_pmu)) << 12) | \ +/* group flag */ ((!!(_grp)) << 13) | \ +/* AU1 flag */ ((!!(_au1)) << 14) | \ +/* NFCE flag */ ((!!(_nfc)) << 15)) + +#define MPP_MAX 71 + +#define MPP_NUM(x) ((x) & 0xff) +#define MPP_SEL(x) (((x) >> 8) & 0xf) + +#define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0) +#define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0) +#define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0) +#define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1) + +#define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1) + +#define MPP_PMU_DRIVE_0 0x1 +#define MPP_PMU_DRIVE_1 0x2 +#define MPP_PMU_SDI 0x3 +#define MPP_PMU_CPU_PWRDWN 0x4 +#define MPP_PMU_STBY_PWRDWN 0x5 +#define MPP_PMU_CORE_PWR_GOOD 0x8 +#define MPP_PMU_BAT_FAULT 0xa +#define MPP_PMU_EXT0_WU 0xb +#define MPP_PMU_EXT1_WU 0xc +#define MPP_PMU_EXT2_WU 0xd +#define MPP_PMU_BLINK 0xe +#define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0) + +#define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0) +#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0) +#define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0) +#define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1) + +#define MPP0_GPIO0 MPP_PIN(0, 0x0) +#define MPP0_UA2_RTSn MPP_PIN(0, 0x2) +#define MPP0_SDIO0_CD MPP_PIN(0, 0x3) +#define MPP0_LCD0_PWM MPP_PIN(0, 0xf) + +#define MPP1_GPIO1 MPP_PIN(1, 0x0) +#define MPP1_UA2_CTSn MPP_PIN(1, 0x2) +#define MPP1_SDIO0_WP MPP_PIN(1, 0x3) +#define MPP1_LCD1_PWM MPP_PIN(1, 0xf) + +#define MPP2_GPIO2 MPP_PIN(2, 0x0) +#define MPP2_SATA_PRESENT MPP_PIN(2, 0x1) +#define MPP2_UA2_TXD MPP_PIN(2, 0x2) +#define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3) +#define MPP2_UA_RTSn1 MPP_PIN(2, 0x4) + +#define MPP3_GPIO3 MPP_PIN(3, 0x0) +#define MPP3_SATA_ACT MPP_PIN(3, 0x1) +#define MPP3_UA2_RXD MPP_PIN(3, 0x2) +#define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3) +#define MPP3_UA_CTSn1 MPP_PIN(3, 0x4) +#define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf) + +#define MPP4_GPIO4 MPP_PIN(4, 0x0) +#define MPP4_UA3_RTSn MPP_PIN(4, 0x2) +#define MPP4_SDIO1_CD MPP_PIN(4, 0x3) +#define MPP4_SPI_1_MISO MPP_PIN(4, 0x4) + +#define MPP5_GPIO5 MPP_PIN(5, 0x0) +#define MPP5_UA3_CTSn MPP_PIN(5, 0x2) +#define MPP5_SDIO1_WP MPP_PIN(5, 0x3) +#define MPP5_SPI_1_CS MPP_PIN(5, 0x4) + +#define MPP6_GPIO6 MPP_PIN(6, 0x0) +#define MPP6_UA3_TXD MPP_PIN(6, 0x2) +#define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3) +#define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4) + +#define MPP7_GPIO7 MPP_PIN(7, 0x0) +#define MPP7_UA3_RXD MPP_PIN(7, 0x2) +#define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3) +#define MPP7_SPI_1_SCK MPP_PIN(7, 0x4) + +#define MPP8_GPIO8 MPP_PIN(8, 0x0) +#define MPP8_WD_RST_OUT MPP_PIN(8, 0x1) + +#define MPP9_GPIO9 MPP_PIN(9, 0x0) +#define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5) + +#define MPP10_GPIO10 MPP_PIN(10, 0x0) +#define MPP10_SSP_SCLK MPP_PIN(10, 0x5) + +#define MPP11_GPIO11 MPP_PIN(11, 0x0) +#define MPP11_SATA_PRESENT MPP_PIN(11, 0x1) +#define MPP11_SATA_ACT MPP_PIN(11, 0x2) +#define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3) +#define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4) +#define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5) + +#define MPP12_GPIO12 MPP_PIN(12, 0x0) +#define MPP12_SATA_ACT MPP_PIN(12, 0x1) +#define MPP12_UA2_RTSn MPP_PIN(12, 0x2) +#define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3) +#define MPP12_SDIO1_CD MPP_PIN(12, 0x4) + +#define MPP13_GPIO13 MPP_PIN(13, 0x0) +#define MPP13_UA2_CTSn MPP_PIN(13, 0x2) +#define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3) +#define MPP13_SDIO1WP MPP_PIN(13, 0x4) +#define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5) + +#define MPP14_GPIO14 MPP_PIN(14, 0x0) +#define MPP14_UA2_TXD MPP_PIN(14, 0x2) +#define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4) +#define MPP14_SSP_RXD MPP_PIN(14, 0x5) + +#define MPP15_GPIO15 MPP_PIN(15, 0x0) +#define MPP15_UA2_RXD MPP_PIN(15, 0x2) +#define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4) +#define MPP15_SSP_SFRM MPP_PIN(15, 0x5) + +#define MPP16_GPIO16 MPP_PIN(16, 0x0) +#define MPP16_UA3_RTSn MPP_PIN(16, 0x2) +#define MPP16_SDIO0_CD MPP_PIN(16, 0x3) +#define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4) +#define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5) + +#define MPP17_GPIO17 MPP_PIN(17, 0x0) +#define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1) +#define MPP17_UA3_CTSn MPP_PIN(17, 0x2) +#define MPP17_SDIO0_WP MPP_PIN(17, 0x3) +#define MPP17_TW_SDA2 MPP_PIN(17, 0x4) +#define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5) + +#define MPP18_GPIO18 MPP_PIN(18, 0x0) +#define MPP18_UA3_TXD MPP_PIN(18, 0x2) +#define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3) +#define MPP18_LCD0_PWM MPP_PIN(18, 0x4) +#define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5) + +#define MPP19_GPIO19 MPP_PIN(19, 0x0) +#define MPP19_UA3_RXD MPP_PIN(19, 0x2) +#define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3) +#define MPP19_TW_SCK2 MPP_PIN(19, 0x4) + +#define MPP20_GPIO20 MPP_PIN(20, 0x0) +#define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1) +#define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2) +#define MPP20_SDIO1_CD MPP_PIN(20, 0x3) +#define MPP20_SDIO0_CD MPP_PIN(20, 0x5) +#define MPP20_SPI_1_MISO MPP_PIN(20, 0x6) + +#define MPP21_GPIO21 MPP_PIN(21, 0x0) +#define MPP21_UA1_RTSn MPP_PIN(21, 0x1) +#define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2) +#define MPP21_SDIO1_WP MPP_PIN(21, 0x3) +#define MPP21_SSP_SFRM MPP_PIN(21, 0x4) +#define MPP21_SDIO0_WP MPP_PIN(21, 0x5) +#define MPP21_SPI_1_CS MPP_PIN(21, 0x6) + +#define MPP22_GPIO22 MPP_PIN(22, 0x0) +#define MPP22_UA1_CTSn MPP_PIN(22, 0x1) +#define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2) +#define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3) +#define MPP22_SSP_TXD MPP_PIN(22, 0x4) +#define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5) +#define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6) + +#define MPP23_GPIO23 MPP_PIN(23, 0x0) +#define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2) +#define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3) +#define MPP23_SSP_SCLK MPP_PIN(23, 0x4) +#define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5) +#define MPP23_SPI_1_SCK MPP_PIN(23, 0x6) + +/* for MPP groups _num is a group index */ +enum dove_mpp_grp_idx { + MPP_24_39 = 2, + MPP_40_45 = 0, + MPP_46_51 = 1, + MPP_58_61 = 5, + MPP_62_63 = 4, +}; + +#define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1) +#define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0) + +#define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1) +#define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0) + +#define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1) +#define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0) + +#define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1) +#define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0) + +#define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1) +#define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0) + +/* The MPP[64:71] control differs from other groups */ +#define MPP64_71_GPO MPP_GRP_NFC(0x1) +#define MPP64_71_NFC MPP_GRP_NFC(0x0) + +/* + * The MPP[52:57] functionality is encoded by 4 bits in different + * registers. The _num field in this case encodes those bits in + * correspodence with Table 135 of 88AP510 Functional specification + */ +#define MPP52_57_AU1 MPP_GRP_AU1(0x0) +#define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2) +#define MPP52_57_GPIO MPP_GRP_AU1(0xa) +#define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb) +#define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc) +#define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe) +#define MPP52_57_SSP_TW MPP_GRP_AU1(0xf) + +void dove_mpp_conf(unsigned int *mpp_list); + +#endif /* __ARCH_DOVE_MPP_CODED_H */ diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 197f9e2..17d2e60 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -1,13 +1,37 @@ config IMX_HAVE_DMA_V1 bool -if ARCH_MX1 - config SOC_IMX1 + bool select CPU_ARM920T select IMX_HAVE_DMA_V1 select IMX_HAVE_IOMUX_V1 + select MXC_AVIC + +config SOC_IMX21 + bool + select CPU_ARM926T + select ARCH_MXC_AUDMUX_V1 + select IMX_HAVE_DMA_V1 + select IMX_HAVE_IOMUX_V1 + select MXC_AVIC + +config SOC_IMX25 bool + select CPU_ARM926T + select ARCH_MXC_AUDMUX_V2 + select ARCH_MXC_IOMUX_V3 + select MXC_AVIC + +config SOC_IMX27 + bool + select CPU_ARM926T + select ARCH_MXC_AUDMUX_V1 + select IMX_HAVE_DMA_V1 + select IMX_HAVE_IOMUX_V1 + select MXC_AVIC + +if ARCH_MX1 comment "MX1 platforms:" config MACH_MXLADS @@ -31,33 +55,17 @@ endif if ARCH_MX2 -config SOC_IMX21 - select CPU_ARM926T - select ARCH_MXC_AUDMUX_V1 - select IMX_HAVE_DMA_V1 - select IMX_HAVE_IOMUX_V1 - bool - -config SOC_IMX27 - select CPU_ARM926T - select ARCH_MXC_AUDMUX_V1 - select IMX_HAVE_DMA_V1 - select IMX_HAVE_IOMUX_V1 - bool - choice prompt "CPUs:" default MACH_MX21 config MACH_MX21 bool "i.MX21 support" - select SOC_IMX21 help This enables support for Freescale's MX2 based i.MX21 processor. config MACH_MX27 bool "i.MX27 support" - select SOC_IMX27 help This enables support for Freescale's MX2 based i.MX27 processor. @@ -71,7 +79,10 @@ comment "MX21 platforms:" config MACH_MX21ADS bool "MX21ADS platform" + select SOC_IMX21 + select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND help Include support for MX21ADS platform. This includes specific @@ -79,24 +90,79 @@ config MACH_MX21ADS endif +if ARCH_MX25 + +comment "MX25 platforms:" + +config MACH_MX25_3DS + bool "Support MX25PDK (3DS) Platform" + select SOC_IMX25 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMXDI_RTC + select IMX_HAVE_PLATFORM_IMX_FB + select IMX_HAVE_PLATFORM_IMX_KEYPAD + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + +config MACH_EUKREA_CPUIMX25 + bool "Support Eukrea CPUIMX25 Platform" + select SOC_IMX25 + select IMX_HAVE_PLATFORM_FLEXCAN + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMXDI_RTC + select IMX_HAVE_PLATFORM_IMX_FB + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select MXC_ULPI if USB_ULPI + +choice + prompt "Baseboard" + depends on MACH_EUKREA_CPUIMX25 + default MACH_EUKREA_MBIMXSD25_BASEBOARD + +config MACH_EUKREA_MBIMXSD25_BASEBOARD + bool "Eukrea MBIMXSD development board" + select IMX_HAVE_PLATFORM_IMX_SSI + help + This adds board specific devices that can be found on Eukrea's + MBIMXSD evaluation board. + +endchoice + +endif + if MACH_MX27 comment "MX27 platforms:" config MACH_MX27ADS bool "MX27ADS platform" + select SOC_IMX27 + select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_MXC_W1 help Include support for MX27ADS platform. This includes specific configurations for the board and its peripherals. config MACH_PCM038 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" + select SOC_IMX27 + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_MXC_W1 select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help @@ -109,8 +175,9 @@ choice default MACH_PCM970_BASEBOARD config MACH_PCM970_BASEBOARD - prompt "PHYTEC PCM970 development board" - bool + bool "PHYTEC PCM970 development board" + select IMX_HAVE_PLATFORM_IMX_FB + select IMX_HAVE_PLATFORM_MXC_MMC help This adds board specific devices that can be found on Phytec's PCM970 evaluation board. @@ -119,9 +186,14 @@ endchoice config MACH_CPUIMX27 bool "Eukrea CPUIMX27 module" + select SOC_IMX27 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_MXC_W1 select MXC_ULPI if USB_ULPI help Include support for Eukrea CPUIMX27 platform. This includes @@ -130,6 +202,7 @@ config MACH_CPUIMX27 config MACH_EUKREA_CPUIMX27_USESDHC2 bool "CPUIMX27 integrates SDHC2 module" depends on MACH_CPUIMX27 + select IMX_HAVE_PLATFORM_MXC_MMC help This adds support for the internal SDHC2 used on CPUIMX27 for wifi or eMMC. @@ -148,8 +221,11 @@ choice config MACH_EUKREA_MBIMX27_BASEBOARD bool "Eukrea MBIMX27 development board" + select IMX_HAVE_PLATFORM_IMX_FB + select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_SPI_IMX help This adds board specific devices that can be found on Eukrea's @@ -159,15 +235,26 @@ endchoice config MACH_MX27_3DS bool "MX27PDK platform" + select SOC_IMX27 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC + select IMX_HAVE_PLATFORM_SPI_IMX + select MXC_ULPI if USB_ULPI help Include support for MX27PDK platform. This includes specific configurations for the board and its peripherals. config MACH_IMX27_VISSTRIM_M10 bool "Vista Silicon i.MX27 Visstrim_m10" + select SOC_IMX27 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_MMC + select IMX_HAVE_PLATFORM_MXC_EHCI help Include support for Visstrim_m10 platform and its different variants. This includes specific configurations for the board and its @@ -175,6 +262,7 @@ config MACH_IMX27_VISSTRIM_M10 config MACH_IMX27LITE bool "LogicPD MX27 LITEKIT platform" + select SOC_IMX27 select IMX_HAVE_PLATFORM_IMX_UART help Include support for MX27 LITEKIT platform. This includes specific @@ -182,10 +270,17 @@ config MACH_IMX27LITE config MACH_PCA100 bool "Phytec phyCARD-s (pca100)" + select SOC_IMX27 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_MXC_W1 select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help @@ -194,8 +289,11 @@ config MACH_PCA100 config MACH_MXT_TD60 bool "Maxtrack i-MXT TD60" + select SOC_IMX27 + select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND help Include support for i-MXT (aka td60) platform. This diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 5582692..77100bf 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -4,13 +4,13 @@ # Object file lists. -obj-y := devices.o - obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o +obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o + obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o @@ -22,6 +22,10 @@ obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o +obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o +obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o +obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o + obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index 7988a85..3953d60 100644 --- a/arch/arm/mach-imx/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot @@ -6,6 +6,10 @@ zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000 params_phys-$(CONFIG_MACH_MX21) := 0xC0000100 initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000 +zreladdr-$(CONFIG_ARCH_MX25) := 0x80008000 +params_phys-$(CONFIG_ARCH_MX25) := 0x80000100 +initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000 + zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000 params_phys-$(CONFIG_MACH_MX27) := 0xA0000100 initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000 diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c index d705655..bf30a8c 100644 --- a/arch/arm/mach-imx/clock-imx21.c +++ b/arch/arm/mach-imx/clock-imx21.c @@ -1185,7 +1185,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "brom", brom_clk) _REGISTER_CLOCK(NULL, "emma", emma_clk[0]) _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0]) - _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) + _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) _REGISTER_CLOCK(NULL, "gpio", gpio_clk) _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-imx/clock-imx25.c index 00dcb08..daa0165 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-imx/clock-imx25.c @@ -295,7 +295,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) - _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) + _REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c index ca1017b..583f251 100644 --- a/arch/arm/mach-imx/clock-imx27.c +++ b/arch/arm/mach-imx/clock-imx27.c @@ -125,7 +125,7 @@ static int clk_cpu_set_parent(struct clk *clk, struct clk *parent) if (clk->parent == parent) return 0; - if (mx27_revision() >= CHIP_REV_2_0) { + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { if (parent == &mpll_main1_clk) { cscr |= CCM_CSCR_ARM_SRC; } else { @@ -174,7 +174,7 @@ static int set_rate_cpu(struct clk *clk, unsigned long rate) div--; reg = __raw_readl(CCM_CSCR); - if (mx27_revision() >= CHIP_REV_2_0) { + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { reg &= ~(3 << 12); reg |= div << 12; reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN); @@ -244,7 +244,7 @@ static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf) parent_rate = clk_get_rate(clk->parent); - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) pdf += 4; /* MX27 TO2+ */ else pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ @@ -269,7 +269,7 @@ static unsigned long get_rate_nfc(struct clk *clk) parent_rate = clk_get_rate(clk->parent); - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf; else nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf; @@ -284,7 +284,7 @@ static unsigned long get_rate_vpu(struct clk *clk) parent_rate = clk_get_rate(clk->parent); - if (mx27_revision() >= CHIP_REV_2_0) { + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f; vpu_pdf += 4; } else { @@ -347,7 +347,7 @@ static unsigned long get_rate_mpll_main(struct clk *clk) * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2 * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3 */ - if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1) return 2UL * parent_rate / 3UL; return parent_rate; @@ -365,7 +365,7 @@ static unsigned long get_rate_spll(struct clk *clk) /* On TO2 we have to write the value back. Otherwise we * read 0 from this register the next time. */ - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) __raw_writel(reg, CCM_SPCTL0); return mxc_decode_pll(reg, rate); @@ -376,7 +376,7 @@ static unsigned long get_rate_cpu(struct clk *clk) u32 div; unsigned long rate; - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) div = (__raw_readl(CCM_CSCR) >> 12) & 0x3; else div = (__raw_readl(CCM_CSCR) >> 13) & 0x7; @@ -389,7 +389,7 @@ static unsigned long get_rate_ahb(struct clk *clk) { unsigned long rate, bclk_pdf; - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3; else bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf; @@ -402,7 +402,7 @@ static unsigned long get_rate_ipg(struct clk *clk) { unsigned long rate, ipg_pdf; - if (mx27_revision() >= CHIP_REV_2_0) + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) return clk_get_rate(clk->parent); else ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1; @@ -667,7 +667,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk) _REGISTER_CLOCK(NULL, "ata", ata_clk) _REGISTER_CLOCK(NULL, "mstick", mstick_clk) - _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) + _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) _REGISTER_CLOCK(NULL, "gpio", gpio_clk) _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) @@ -683,7 +683,7 @@ static void __init to2_adjust_clocks(void) { unsigned long cscr = __raw_readl(CCM_CSCR); - if (mx27_revision() >= CHIP_REV_2_0) { + if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { if (cscr & CCM_CSCR_ARM_SRC) cpu_clk.parent = &mpll_main1_clk; diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c index d8d3b2d..3b117be 100644 --- a/arch/arm/mach-imx/cpu-imx27.c +++ b/arch/arm/mach-imx/cpu-imx27.c @@ -42,7 +42,19 @@ static void query_silicon_parameter(void) val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + SYS_CHIP_ID)); - cpu_silicon_rev = (int)(val >> 28); + switch (val >> 28) { + case 0: + cpu_silicon_rev = IMX_CHIP_REVISION_1_0; + break; + case 1: + cpu_silicon_rev = IMX_CHIP_REVISION_2_0; + break; + case 2: + cpu_silicon_rev = IMX_CHIP_REVISION_2_1; + break; + default: + cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN; + } cpu_partnumber = (int)((val >> 12) & 0xFFFF); } diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h index d189039..16744d2 100644 --- a/arch/arm/mach-imx/devices-imx21.h +++ b/arch/arm/mach-imx/devices-imx21.h @@ -9,10 +9,26 @@ #include <mach/mx21.h> #include <mach/devices-common.h> +extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst; +#define imx21_add_imx21_hcd(pdata) \ + imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata) + +extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst; +#define imx21_add_imx2_wdt(pdata) \ + imx_add_imx2_wdt(&imx21_imx2_wdt_data) + +extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst; +#define imx21_add_imx_fb(pdata) \ + imx_add_imx_fb(&imx21_imx_fb_data, pdata) + extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst; #define imx21_add_imx_i2c(pdata) \ imx_add_imx_i2c(&imx21_imx_i2c_data, pdata) +extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst; +#define imx21_add_imx_keypad(pdata) \ + imx_add_imx_keypad(&imx21_imx_keypad_data, pdata) + extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst; #define imx21_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata) @@ -25,10 +41,18 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst; #define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata) #define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata) +extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst; +#define imx21_add_mxc_mmc(id, pdata) \ + imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata) + extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst; #define imx21_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) +extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst; +#define imx21_add_mxc_w1(pdata) \ + imx_add_mxc_w1(&imx21_mxc_w1_data) + extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst; #define imx21_add_cspi(id, pdata) \ imx_add_spi_imx(&imx21_cspi_data[id], pdata) diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h index d94d282..bde33ca 100644 --- a/arch/arm/mach-mx25/devices-imx25.h +++ b/arch/arm/mach-imx/devices-imx25.h @@ -13,10 +13,27 @@ extern const struct imx_fec_data imx25_fec_data __initconst; #define imx25_add_fec(pdata) \ imx_add_fec(&imx25_fec_data, pdata) -#define imx25_add_flexcan0(pdata) \ - imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata) -#define imx25_add_flexcan1(pdata) \ - imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata) +extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst; +#define imx25_add_flexcan(id, pdata) \ + imx_add_flexcan(&imx25_flexcan_data[id], pdata) +#define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata) +#define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata) + +extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst; +#define imx25_add_fsl_usb2_udc(pdata) \ + imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata) + +extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst; +#define imx25_add_imxdi_rtc(pdata) \ + imx_add_imxdi_rtc(&imx25_imxdi_rtc_data) + +extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst; +#define imx25_add_imx2_wdt(pdata) \ + imx_add_imx2_wdt(&imx25_imx2_wdt_data) + +extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst; +#define imx25_add_imx_fb(pdata) \ + imx_add_imx_fb(&imx25_imx_fb_data, pdata) extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst; #define imx25_add_imx_i2c(id, pdata) \ @@ -25,6 +42,10 @@ extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst; #define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata) #define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata) +extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst; +#define imx25_add_imx_keypad(pdata) \ + imx_add_imx_keypad(&imx25_imx_keypad_data, pdata) + extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst; #define imx25_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata) @@ -38,17 +59,29 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst; #define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata) #define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata) +extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst; +#define imx25_add_mx2_camera(pdata) \ + imx_add_mx2_camera(&imx25_mx2_camera_data, pdata) + +extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst; +#define imx25_add_mxc_ehci_otg(pdata) \ + imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata) +extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst; +#define imx25_add_mxc_ehci_hs(pdata) \ + imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata) + extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst; #define imx25_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx25_mxc_nand_data, pdata) +extern const struct imx_sdhci_esdhc_imx_data +imx25_sdhci_esdhc_imx_data[] __initconst; +#define imx25_add_sdhci_esdhc_imx(id, pdata) \ + imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata) + extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst; #define imx25_add_spi_imx(id, pdata) \ - imx_add_spi_imx(&imx25_cspi_data[id], pdata) + imx_add_spi_imx(&imx25_spi_imx_data[id], pdata) #define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) #define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) #define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) - -extern const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst; -#define imx25_add_esdhc(id, pdata) \ - imx_add_esdhc(&imx25_esdhc_data[id], pdata) diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index 7011690..f1272d4 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h @@ -13,10 +13,26 @@ extern const struct imx_fec_data imx27_fec_data __initconst; #define imx27_add_fec(pdata) \ imx_add_fec(&imx27_fec_data, pdata) +extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst; +#define imx27_add_fsl_usb2_udc(pdata) \ + imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata) + +extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst; +#define imx27_add_imx2_wdt(pdata) \ + imx_add_imx2_wdt(&imx27_imx2_wdt_data) + +extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst; +#define imx27_add_imx_fb(pdata) \ + imx_add_imx_fb(&imx27_imx_fb_data, pdata) + extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst; #define imx27_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata) +extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst; +#define imx27_add_imx_keypad(pdata) \ + imx_add_imx_keypad(&imx27_imx_keypad_data, pdata) + extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst; #define imx27_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata) @@ -31,10 +47,29 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst; #define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata) #define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata) +extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst; +#define imx27_add_mx2_camera(pdata) \ + imx_add_mx2_camera(&imx27_mx2_camera_data, pdata) + +extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst; +#define imx27_add_mxc_ehci_otg(pdata) \ + imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata) +extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst; +#define imx27_add_mxc_ehci_hs(id, pdata) \ + imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata) + +extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst; +#define imx27_add_mxc_mmc(id, pdata) \ + imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata) + extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst; #define imx27_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) +extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst; +#define imx27_add_mxc_w1(pdata) \ + imx_add_mxc_w1(&imx27_mxc_w1_data) + extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst; #define imx27_add_cspi(id, pdata) \ imx_add_spi_imx(&imx27_cspi_data[id], pdata) diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c deleted file mode 100644 index fba5047..0000000 --- a/arch/arm/mach-imx/devices.c +++ /dev/null @@ -1,553 +0,0 @@ -/* - * Author: MontaVista Software, Inc. - * <source@mvista.com> - * - * Based on the OMAP devices.c - * - * 2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * Copyright 2008 Sascha Hauer, kernel@pengutronix.de - * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> - * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/dma-mapping.h> -#include <linux/serial.h> - -#include <mach/irqs.h> -#include <mach/hardware.h> -#include <mach/common.h> -#include <mach/mmc.h> - -#include "devices.h" - -#if defined(CONFIG_ARCH_MX1) -static struct resource imx1_camera_resources[] = { - { - .start = 0x00224000, - .end = 0x00224010, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_CSI_INT, - .end = MX1_CSI_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 imx1_camera_dmamask = DMA_BIT_MASK(32); - -struct platform_device imx1_camera_device = { - .name = "mx1-camera", - .id = 0, /* This is used to put cameras on this interface */ - .dev = { - .dma_mask = &imx1_camera_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = imx1_camera_resources, - .num_resources = ARRAY_SIZE(imx1_camera_resources), -}; - -static struct resource imx_rtc_resources[] = { - { - .start = 0x00204000, - .end = 0x00204024, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_RTC_INT, - .end = MX1_RTC_INT, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_RTC_SAMINT, - .end = MX1_RTC_SAMINT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_rtc_device = { - .name = "rtc-imx", - .id = 0, - .resource = imx_rtc_resources, - .num_resources = ARRAY_SIZE(imx_rtc_resources), -}; - -static struct resource imx_wdt_resources[] = { - { - .start = 0x00201000, - .end = 0x00201008, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_WDT_INT, - .end = MX1_WDT_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_wdt_device = { - .name = "imx-wdt", - .id = 0, - .resource = imx_wdt_resources, - .num_resources = ARRAY_SIZE(imx_wdt_resources), -}; - -static struct resource imx_usb_resources[] = { - { - .start = 0x00212000, - .end = 0x00212148, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_USBD_INT0, - .end = MX1_USBD_INT0, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT1, - .end = MX1_USBD_INT1, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT2, - .end = MX1_USBD_INT2, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT3, - .end = MX1_USBD_INT3, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT4, - .end = MX1_USBD_INT4, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT5, - .end = MX1_USBD_INT5, - .flags = IORESOURCE_IRQ, - }, { - .start = MX1_USBD_INT6, - .end = MX1_USBD_INT6, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_usb_device = { - .name = "imx_udc", - .id = 0, - .num_resources = ARRAY_SIZE(imx_usb_resources), - .resource = imx_usb_resources, -}; - -/* GPIO port description */ -static struct mxc_gpio_port imx_gpio_ports[] = { - { - .chip.label = "gpio-0", - .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), - .irq = MX1_GPIO_INT_PORTA, - .virtual_irq_start = MXC_GPIO_IRQ_START, - }, { - .chip.label = "gpio-1", - .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100), - .irq = MX1_GPIO_INT_PORTB, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, { - .chip.label = "gpio-2", - .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200), - .irq = MX1_GPIO_INT_PORTC, - .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - }, { - .chip.label = "gpio-3", - .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300), - .irq = MX1_GPIO_INT_PORTD, - .virtual_irq_start = MXC_GPIO_IRQ_START + 96, - } -}; - -int __init imx1_register_gpios(void) -{ - return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); -} -#endif - -#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) - -#ifdef CONFIG_MACH_MX27 -static struct resource mx27_camera_resources[] = { - { - .start = MX27_CSI_BASE_ADDR, - .end = MX27_CSI_BASE_ADDR + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_EMMA_PRP_BASE_ADDR, - .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_INT_CSI, - .end = MX27_INT_CSI, - .flags = IORESOURCE_IRQ, - },{ - .start = MX27_INT_EMMAPRP, - .end = MX27_INT_EMMAPRP, - .flags = IORESOURCE_IRQ, - }, -}; -struct platform_device mx27_camera_device = { - .name = "mx2-camera", - .id = 0, - .num_resources = ARRAY_SIZE(mx27_camera_resources), - .resource = mx27_camera_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; -#endif - -/* - * General Purpose Timer - * - i.MX21: 3 timers - * - i.MX27: 6 timers - */ -#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \ - static struct resource timer ## n ##_resources[] = { \ - { \ - .start = baseaddr, \ - .end = baseaddr + SZ_4K - 1, \ - .flags = IORESOURCE_MEM, \ - }, { \ - .start = irq, \ - .end = irq, \ - .flags = IORESOURCE_IRQ, \ - } \ - }; \ - \ - struct platform_device mxc_gpt ## n = { \ - .name = "imx_gpt", \ - .id = n, \ - .num_resources = ARRAY_SIZE(timer ## n ## _resources), \ - .resource = timer ## n ## _resources, \ - } - -/* We use gpt1 as system timer, so do not add a device for this one */ -DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2); -DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3); - -#ifdef CONFIG_MACH_MX27 -DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4); -DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5); -DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); -#endif - -/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */ -static struct resource mxc_wdt_resources[] = { - { - .start = MX2x_WDOG_BASE_ADDR, - .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_wdt = { - .name = "imx2-wdt", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_wdt_resources), - .resource = mxc_wdt_resources, -}; - -static struct resource mxc_w1_master_resources[] = { - { - .start = MX2x_OWIRE_BASE_ADDR, - .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_w1_master_device = { - .name = "mxc_w1", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_w1_master_resources), - .resource = mxc_w1_master_resources, -}; - -/* - * lcdc: - * - i.MX1: the basic controller - * - i.MX21: to be checked - * - i.MX27: like i.MX1, with slightly variations - */ -static struct resource mxc_fb[] = { - { - .start = MX2x_LCDC_BASE_ADDR, - .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX2x_INT_LCDC, - .end = MX2x_INT_LCDC, - .flags = IORESOURCE_IRQ, - } -}; - -/* mxc lcd driver */ -struct platform_device mxc_fb_device = { - .name = "imx-fb", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_fb), - .resource = mxc_fb, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource mxc_pwm_resources[] = { - { - .start = MX2x_PWM_BASE_ADDR, - .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX2x_INT_PWM, - .end = MX2x_INT_PWM, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_pwm_device = { - .name = "mxc_pwm", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_pwm_resources), - .resource = mxc_pwm_resources, -}; - -#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \ - static struct resource mxc_sdhc_resources ## n[] = { \ - { \ - .start = baseaddr, \ - .end = baseaddr + SZ_4K - 1, \ - .flags = IORESOURCE_MEM, \ - }, { \ - .start = irq, \ - .end = irq, \ - .flags = IORESOURCE_IRQ, \ - }, { \ - .start = dmareq, \ - .end = dmareq, \ - .flags = IORESOURCE_DMA, \ - }, \ - }; \ - \ - static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \ - \ - struct platform_device mxc_sdhc_device ## n = { \ - .name = "mxc-mmc", \ - .id = n, \ - .dev = { \ - .dma_mask = &mxc_sdhc ## n ## _dmamask, \ - .coherent_dma_mask = DMA_BIT_MASK(32), \ - }, \ - .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \ - .resource = mxc_sdhc_resources ## n, \ - } - -DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1); -DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2); - -#ifdef CONFIG_MACH_MX27 -static struct resource otg_resources[] = { - { - .start = MX27_USBOTG_BASE_ADDR, - .end = MX27_USBOTG_BASE_ADDR + 0x1ff, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_INT_USB3, - .end = MX27_INT_USB3, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 otg_dmamask = DMA_BIT_MASK(32); - -/* OTG gadget device */ -struct platform_device mxc_otg_udc_device = { - .name = "fsl-usb2-udc", - .id = -1, - .dev = { - .dma_mask = &otg_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), -}; - -/* OTG host */ -struct platform_device mxc_otg_host = { - .name = "mxc-ehci", - .id = 0, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - .dma_mask = &otg_dmamask, - }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), -}; - -/* USB host 1 */ - -static u64 usbh1_dmamask = DMA_BIT_MASK(32); - -static struct resource mxc_usbh1_resources[] = { - { - .start = MX27_USBOTG_BASE_ADDR + 0x200, - .end = MX27_USBOTG_BASE_ADDR + 0x3ff, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_INT_USB1, - .end = MX27_INT_USB1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_usbh1 = { - .name = "mxc-ehci", - .id = 1, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - .dma_mask = &usbh1_dmamask, - }, - .resource = mxc_usbh1_resources, - .num_resources = ARRAY_SIZE(mxc_usbh1_resources), -}; - -/* USB host 2 */ -static u64 usbh2_dmamask = DMA_BIT_MASK(32); - -static struct resource mxc_usbh2_resources[] = { - { - .start = MX27_USBOTG_BASE_ADDR + 0x400, - .end = MX27_USBOTG_BASE_ADDR + 0x5ff, - .flags = IORESOURCE_MEM, - }, { - .start = MX27_INT_USB2, - .end = MX27_INT_USB2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_usbh2 = { - .name = "mxc-ehci", - .id = 2, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - .dma_mask = &usbh2_dmamask, - }, - .resource = mxc_usbh2_resources, - .num_resources = ARRAY_SIZE(mxc_usbh2_resources), -}; -#endif - -/* GPIO port description */ -#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \ - { \ - .chip.label = "gpio-" #n, \ - .irq = _irq, \ - .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ - n * 0x100), \ - .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ - } - -#define DEFINE_MXC_GPIO_PORT(SOC, n) \ - { \ - .chip.label = "gpio-" #n, \ - .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ - n * 0x100), \ - .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ - } - -#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \ - static struct mxc_gpio_port pfx ## _gpio_ports[] = { \ - DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \ - DEFINE_MXC_GPIO_PORT(SOC, 1), \ - DEFINE_MXC_GPIO_PORT(SOC, 2), \ - DEFINE_MXC_GPIO_PORT(SOC, 3), \ - DEFINE_MXC_GPIO_PORT(SOC, 4), \ - DEFINE_MXC_GPIO_PORT(SOC, 5), \ - } - -#ifdef CONFIG_MACH_MX21 -DEFINE_MXC_GPIO_PORTS(MX21, imx21); - -int __init imx21_register_gpios(void) -{ - return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); -} -#endif - -#ifdef CONFIG_MACH_MX27 -DEFINE_MXC_GPIO_PORTS(MX27, imx27); - -int __init imx27_register_gpios(void) -{ - return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); -} -#endif - -#ifdef CONFIG_MACH_MX21 -static struct resource mx21_usbhc_resources[] = { - { - .start = MX21_USBOTG_BASE_ADDR, - .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MX21_INT_USBHOST, - .end = MX21_INT_USBHOST, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mx21_usbhc_device = { - .name = "imx21-hcd", - .id = 0, - .dev = { - .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(mx21_usbhc_resources), - .resource = mx21_usbhc_resources, -}; -#endif - -static struct resource imx_kpp_resources[] = { - { - .start = MX2x_KPP_BASE_ADDR, - .end = MX2x_KPP_BASE_ADDR + 0xf, - .flags = IORESOURCE_MEM - }, { - .start = MX2x_INT_KPP, - .end = MX2x_INT_KPP, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_kpp_device = { - .name = "imx-keypad", - .id = -1, - .num_resources = ARRAY_SIZE(imx_kpp_resources), - .resource = imx_kpp_resources, -}; - -#endif diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h deleted file mode 100644 index 807f02a..0000000 --- a/arch/arm/mach-imx/devices.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifdef CONFIG_ARCH_MX1 -extern struct platform_device imx1_camera_device; -extern struct platform_device imx_rtc_device; -extern struct platform_device imx_wdt_device; -extern struct platform_device imx_usb_device; -#endif - -#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) -extern struct platform_device mxc_gpt1; -extern struct platform_device mxc_gpt2; -#ifdef CONFIG_MACH_MX27 -extern struct platform_device mxc_gpt3; -extern struct platform_device mxc_gpt4; -extern struct platform_device mxc_gpt5; -#endif -extern struct platform_device mxc_wdt; -extern struct platform_device mxc_w1_master_device; -extern struct platform_device mxc_fb_device; -extern struct platform_device mxc_pwm_device; -extern struct platform_device mxc_sdhc_device0; -extern struct platform_device mxc_sdhc_device1; -extern struct platform_device mxc_otg_udc_device; -extern struct platform_device mx27_camera_device; -extern struct platform_device mxc_otg_host; -extern struct platform_device mxc_usbh1; -extern struct platform_device mxc_usbh2; -extern struct platform_device mx21_usbhc_device; -extern struct platform_device imx_kpp_device; -#endif diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c index 3e8c47c..e9f1769 100644 --- a/arch/arm/mach-imx/dma-v1.c +++ b/arch/arm/mach-imx/dma-v1.c @@ -818,9 +818,11 @@ static int __init imx_dma_init(void) imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); else #endif - BUG(); + return 0; dma_clk = clk_get(NULL, "dma"); + if (IS_ERR(dma_clk)) + return PTR_ERR(dma_clk); clk_enable(dma_clk); /* reset DMA module */ diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index 7e1e9dc..275c858 100644 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -26,20 +26,16 @@ #include <linux/spi/ads7846.h> #include <linux/backlight.h> #include <video/platform_lcd.h> -#include <linux/input/matrix_keypad.h> #include <asm/mach/arch.h> #include <mach/common.h> #include <mach/iomux-mx27.h> -#include <mach/imxfb.h> #include <mach/hardware.h> -#include <mach/mmc.h> #include <mach/spi.h> #include <mach/audmux.h> #include "devices-imx27.h" -#include "devices.h" static const int eukrea_mbimx27_pins[] __initconst = { /* UART2 */ @@ -111,7 +107,8 @@ static const uint32_t eukrea_mbimx27_keymap[] = { KEY(1, 1, KEY_LEFT), }; -static struct matrix_keymap_data eukrea_mbimx27_keymap_data = { +static const struct matrix_keymap_data +eukrea_mbimx27_keymap_data __initconst = { .keymap = eukrea_mbimx27_keymap, .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap), }; @@ -196,7 +193,7 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = { }, }; -static struct imx_fb_platform_data eukrea_mbimx27_fb_data = { +static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = { .mode = eukrea_mbimx27_modes, .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes), @@ -300,7 +297,7 @@ static struct platform_device *platform_devices[] __initdata = { &leds_gpio, }; -static struct imxmmc_platform_data sdhc_pdata = { +static const struct imxmmc_platform_data sdhc_pdata __initconst = { .dat3_card_detect = 1, }; @@ -345,8 +342,8 @@ void __init eukrea_mbimx27_baseboard_init(void) imx27_add_imx_uart3(&uart_pdata); #endif - mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data); - mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata); + imx27_add_imx_fb(&eukrea_mbimx27_fb_data); + imx27_add_mxc_mmc(0, &sdhc_pdata); i2c_register_board_info(0, eukrea_mbimx27_i2c_devices, ARRAY_SIZE(eukrea_mbimx27_i2c_devices)); @@ -380,7 +377,7 @@ void __init eukrea_mbimx27_baseboard_init(void) gpio_request(GPIO_PORTA | 25, "lcd_enable"); platform_device_register(&eukrea_mbimx27_lcd_powerdev); - mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data); + imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c index e765ac5..cb705c2 100644 --- a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c @@ -33,13 +33,11 @@ #include <asm/mach/arch.h> #include <mach/mx25.h> #include <mach/imx-uart.h> -#include <mach/imxfb.h> #include <mach/audmux.h> #include "devices-imx25.h" -#include "devices.h" -static struct pad_desc eukrea_mbimxsd_pads[] = { +static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { /* LCD */ MX25_PAD_LD0__LD0, MX25_PAD_LD1__LD1, @@ -151,7 +149,7 @@ static struct imx_fb_videomode eukrea_mximxsd_modes[] = { }, }; -static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = { +static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = { .mode = eukrea_mximxsd_modes, .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes), .pwmr = 0x00A903FF, @@ -273,11 +271,11 @@ void __init eukrea_mbimxsd25_baseboard_init(void) #endif imx25_add_imx_uart1(&uart_pdata); - mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata); + imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata); imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); imx25_add_flexcan1(NULL); - imx25_add_esdhc(0, NULL); + imx25_add_sdhci_esdhc_imx(0, NULL); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 745ee60..6cf04da 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -28,7 +28,6 @@ #include <linux/serial_8250.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> -#include <linux/fsl_devices.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -40,11 +39,9 @@ #include <mach/hardware.h> #include <mach/iomux-mx27.h> #include <mach/mxc_nand.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx27.h" -#include "devices.h" static const int eukrea_cpuimx27_pins[] __initconst = { /* UART1 */ @@ -157,8 +154,6 @@ cpuimx27_nand_board_info __initconst = { static struct platform_device *platform_devices[] __initdata = { &eukrea_cpuimx27_nor_mtd_device, - &mxc_wdt, - &mxc_w1_master_device, }; static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = { @@ -215,18 +210,18 @@ static struct platform_device serial_device = { #endif #if defined(CONFIG_USB_ULPI) -static struct mxc_usbh_platform_data otg_pdata = { +static struct mxc_usbh_platform_data otg_pdata __initdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; #endif -static struct fsl_usb2_platform_data otg_device_pdata = { +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; @@ -262,10 +257,12 @@ static void __init eukrea_cpuimx27_init(void) imx27_add_fec(NULL); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + imx27_add_imx2_wdt(NULL); + imx27_add_mxc_w1(NULL); #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) /* SDHC2 can be used for Wifi */ - mxc_register_device(&mxc_sdhc_device1, NULL); + imx27_add_mxc_mmc(1, NULL); #endif #if defined(MACH_EUKREA_CPUIMX27_USEUART4) /* in which case UART4 is also used for Bluetooth */ @@ -281,16 +278,16 @@ static void __init eukrea_cpuimx27_init(void) otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_otg_host, &otg_pdata); + imx27_add_mxc_ehci_otg(&otg_pdata); } usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx27_add_mxc_ehci_hs(2, &usbh2_pdata); #endif if (!otg_mode_host) - mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + imx27_add_fsl_usb2_udc(&otg_device_pdata); #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD eukrea_mbimx27_baseboard_init(); diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c index f6f9ad6..eb395ab 100644 --- a/arch/arm/mach-mx25/mach-cpuimx25.c +++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c @@ -26,7 +26,6 @@ #include <linux/platform_device.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> -#include <linux/fsl_devices.h> #include <mach/eukrea-baseboards.h> #include <mach/hardware.h> @@ -39,17 +38,15 @@ #include <mach/mx25.h> #include <mach/mxc_nand.h> #include <mach/imxfb.h> -#include <mach/mxc_ehci.h> #include <mach/iomux-mx25.h> #include "devices-imx25.h" -#include "devices.h" static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct pad_desc eukrea_cpuimx25_pads[] = { +static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = { /* FEC - RMII */ MX25_PAD_FEC_MDC__FEC_MDC, MX25_PAD_FEC_MDIO__FEC_MDIO, @@ -87,18 +84,18 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = { }, }; -static struct mxc_usbh_platform_data otg_pdata = { +static const struct mxc_usbh_platform_data otg_pdata __initconst = { .portsc = MXC_EHCI_MODE_UTMI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; -static struct mxc_usbh_platform_data usbh2_pdata = { +static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { .portsc = MXC_EHCI_MODE_SERIAL, .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN, }; -static struct fsl_usb2_platform_data otg_device_pdata = { +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI, }; @@ -126,7 +123,7 @@ static void __init eukrea_cpuimx25_init(void) imx25_add_imx_uart0(&uart_pdata); imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); - mxc_register_device(&mx25_rtc_device, NULL); + imx25_add_imxdi_rtc(NULL); imx25_add_fec(&mx25_fec_pdata); i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, @@ -134,11 +131,11 @@ static void __init eukrea_cpuimx25_init(void) imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data); if (otg_mode_host) - mxc_register_device(&mxc_otg, &otg_pdata); + imx25_add_mxc_ehci_otg(&otg_pdata); else - mxc_register_device(&otg_udc_device, &otg_device_pdata); + imx25_add_fsl_usb2_udc(&otg_device_pdata); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx25_add_mxc_ehci_hs(&usbh2_pdata); #ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD eukrea_mbimxsd25_baseboard_init(); diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index 59716fa..40a3666 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -34,12 +34,9 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <mach/common.h> -#include <mach/mmc.h> #include <mach/iomux.h> -#include <mach/mxc_ehci.h> #include "devices-imx27.h" -#include "devices.h" #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) #define SDHC1_IRQ IRQ_GPIOB(25) @@ -156,7 +153,7 @@ static void visstrim_m10_sdhc1_exit(struct device *dev, void *data) free_irq(SDHC1_IRQ, data); } -static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = { +static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = { .init = visstrim_m10_sdhc1_init, .exit = visstrim_m10_sdhc1_exit, }; @@ -216,7 +213,8 @@ static int otg_phy_init(struct platform_device *pdev) return 0; } -static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = { +static const struct mxc_usbh_platform_data +visstrim_m10_usbotg_pdata __initconst = { .init = otg_phy_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED, @@ -237,8 +235,8 @@ static void __init visstrim_m10_board_init(void) ARRAY_SIZE(visstrim_m10_i2c_devices)); imx27_add_imx_i2c(0, &visstrim_m10_i2c_data); imx27_add_imx_i2c(1, &visstrim_m10_i2c_data); - mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata); - mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata); + imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata); + imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata); imx27_add_fec(NULL); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c index bbdbc75..3a1202e 100644 --- a/arch/arm/mach-imx/mach-imx27lite.c +++ b/arch/arm/mach-imx/mach-imx27lite.c @@ -25,7 +25,6 @@ #include <mach/iomux-mx27.h> #include "devices-imx27.h" -#include "devices.h" static const int mx27lite_pins[] __initconst = { /* UART1 */ diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 6187ce9..1f446e5 100644 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c @@ -30,7 +30,6 @@ #include <mach/irqs.h> #include "devices-imx1.h" -#include "devices.h" static const int mx1ads_pins[] __initconst = { /* UART1 */ diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index e1282e9..0a37257 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -24,13 +24,10 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/mach/map.h> -#include <mach/imxfb.h> #include <mach/iomux-mx21.h> #include <mach/mxc_nand.h> -#include <mach/mmc.h> #include "devices-imx21.h" -#include "devices.h" /* * Memory-mapped I/O on MX21ADS base board @@ -213,7 +210,7 @@ static struct imx_fb_videomode mx21ads_modes[] = { }, }; -static struct imx_fb_platform_data mx21ads_fb_data = { +static const struct imx_fb_platform_data mx21ads_fb_data __initconst = { .mode = mx21ads_modes, .num_modes = ARRAY_SIZE(mx21ads_modes), @@ -233,15 +230,8 @@ static int mx21ads_sdhc_get_ro(struct device *dev) static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq, void *data) { - int ret; - - ret = request_irq(IRQ_GPIOD(25), detect_irq, + return request_irq(IRQ_GPIOD(25), detect_irq, IRQF_TRIGGER_FALLING, "mmc-detect", data); - if (ret) - goto out; - return 0; -out: - return ret; } static void mx21ads_sdhc_exit(struct device *dev, void *data) @@ -249,7 +239,7 @@ static void mx21ads_sdhc_exit(struct device *dev, void *data) free_irq(IRQ_GPIOD(25), data); } -static struct imxmmc_platform_data mx21ads_sdhc_pdata = { +static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = { .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */ .get_ro = mx21ads_sdhc_get_ro, .init = mx21ads_sdhc_init, @@ -296,8 +286,8 @@ static void __init mx21ads_board_init(void) imx21_add_imx_uart0(&uart_pdata_rts); imx21_add_imx_uart2(&uart_pdata_norts); imx21_add_imx_uart3(&uart_pdata_rts); - mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); - mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); + imx21_add_imx_fb(&mx21ads_fb_data); + imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata); imx21_add_mxc_nand(&mx21ads_nand_board_info); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); diff --git a/arch/arm/mach-mx25/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index f8be1eb..aa76cfd 100644 --- a/arch/arm/mach-mx25/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c @@ -30,6 +30,7 @@ #include <linux/gpio.h> #include <linux/platform_device.h> #include <linux/input/matrix_keypad.h> +#include <linux/usb/otg.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -39,17 +40,15 @@ #include <asm/mach/map.h> #include <mach/common.h> #include <mach/mx25.h> -#include <mach/imxfb.h> #include <mach/iomux-mx25.h> #include "devices-imx25.h" -#include "devices.h" static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct pad_desc mx25pdk_pads[] = { +static iomux_v3_cfg_t mx25pdk_pads[] = { MX25_PAD_FEC_MDC__FEC_MDC, MX25_PAD_FEC_MDIO__FEC_MDIO, MX25_PAD_FEC_TDATA0__FEC_TDATA0, @@ -107,7 +106,7 @@ static struct pad_desc mx25pdk_pads[] = { }; static const struct fec_platform_data mx25_fec_pdata __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, + .phy = PHY_INTERFACE_MODE_RMII, }; #define FEC_ENABLE_GPIO 35 @@ -154,7 +153,7 @@ static struct imx_fb_videomode mx25pdk_modes[] = { }, }; -static struct imx_fb_platform_data mx25pdk_fb_pdata = { +static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = { .mode = mx25pdk_modes, .num_modes = ARRAY_SIZE(mx25pdk_modes), .pwmr = 0x00A903FF, @@ -181,28 +180,39 @@ static const uint32_t mx25pdk_keymap[] = { KEY(3, 3, KEY_POWER), }; -static struct matrix_keymap_data mx25pdk_keymap_data = { +static const struct matrix_keymap_data mx25pdk_keymap_data __initdata = { .keymap = mx25pdk_keymap, .keymap_size = ARRAY_SIZE(mx25pdk_keymap), }; +static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { + .portsc = MXC_EHCI_MODE_SERIAL, + .flags = MXC_EHCI_INTERNAL_PHY, +}; + +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI, +}; + static void __init mx25pdk_init(void) { mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, ARRAY_SIZE(mx25pdk_pads)); imx25_add_imx_uart0(&uart_pdata); - mxc_register_device(&mxc_usbh2, NULL); + imx25_add_fsl_usb2_udc(&otg_device_pdata); + imx25_add_mxc_ehci_hs(&usbh2_pdata); imx25_add_mxc_nand(&mx25pdk_nand_board_info); - mxc_register_device(&mx25_rtc_device, NULL); - mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata); - mxc_register_device(&mxc_wdt, NULL); + imx25_add_imxdi_rtc(NULL); + imx25_add_imx_fb(&mx25pdk_fb_pdata); + imx25_add_imx2_wdt(NULL); mx25pdk_fec_reset(); imx25_add_fec(&mx25_fec_pdata); - mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data); + imx25_add_imx_keypad(&mx25pdk_keymap_data); - imx25_add_esdhc(0, NULL); + imx25_add_sdhci_esdhc_imx(0, NULL); } static void __init mx25pdk_timer_init(void) diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 84a5ba03..6fd0f8f 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -22,20 +22,27 @@ #include <linux/platform_device.h> #include <linux/gpio.h> -#include <linux/input/matrix_keypad.h> #include <linux/irq.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> +#include <linux/delay.h> +#include <linux/mfd/mc13783.h> +#include <linux/spi/spi.h> +#include <linux/regulator/machine.h> + #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <mach/hardware.h> #include <mach/common.h> #include <mach/iomux-mx27.h> -#include <mach/mmc.h> +#include <mach/ulpi.h> #include "devices-imx27.h" -#include "devices.h" #define SD1_EN_GPIO (GPIO_PORTB + 25) +#define OTG_PHY_RESET_GPIO (GPIO_PORTB + 23) +#define SPI2_SS0 (GPIO_PORTD + 21) static const int mx27pdk_pins[] __initconst = { /* UART1 */ @@ -70,6 +77,24 @@ static const int mx27pdk_pins[] __initconst = { PE22_PF_SD1_CMD, PE23_PF_SD1_CLK, SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT, + /* OTG */ + OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT, + PC7_PF_USBOTG_DATA5, + PC8_PF_USBOTG_DATA6, + PC9_PF_USBOTG_DATA0, + PC10_PF_USBOTG_DATA2, + PC11_PF_USBOTG_DATA1, + PC12_PF_USBOTG_DATA4, + PC13_PF_USBOTG_DATA3, + PE0_PF_USBOTG_NXT, + PE1_PF_USBOTG_STP, + PE2_PF_USBOTG_DIR, + PE24_PF_USBOTG_CLK, + PE25_PF_USBOTG_DATA7, + /* CSPI2 */ + PD22_PF_CSPI2_SCLK, + PD23_PF_CSPI2_MISO, + PD24_PF_CSPI2_MOSI, }; static const struct imxuart_platform_data uart_pdata __initconst = { @@ -92,7 +117,7 @@ static const uint32_t mx27_3ds_keymap[] = { KEY(2, 3, KEY_F10), }; -static struct matrix_keymap_data mx27_3ds_keymap_data = { +static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = { .keymap = mx27_3ds_keymap, .keymap_size = ARRAY_SIZE(mx27_3ds_keymap), }; @@ -109,7 +134,7 @@ static void mx27_3ds_sdhc1_exit(struct device *dev, void *data) free_irq(IRQ_GPIOB(26), data); } -static struct imxmmc_platform_data sdhc1_pdata = { +static const struct imxmmc_platform_data sdhc1_pdata __initconst = { .init = mx27_3ds_sdhc1_init, .exit = mx27_3ds_sdhc1_exit, }; @@ -121,6 +146,111 @@ static void mx27_3ds_sdhc1_enable_level_translator(void) gpio_direction_output(SD1_EN_GPIO, 1); } + +static int otg_phy_init(void) +{ + gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset"); + gpio_direction_output(OTG_PHY_RESET_GPIO, 0); + mdelay(1); + gpio_set_value(OTG_PHY_RESET_GPIO, 1); + return 0; +} + +#if defined(CONFIG_USB_ULPI) + +static struct mxc_usbh_platform_data otg_pdata __initdata = { + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; +#endif + +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, +}; + +static int otg_mode_host; + +static int __init mx27_3ds_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", mx27_3ds_otg_mode); + +/* Regulators */ +static struct regulator_consumer_supply vmmc1_consumers[] = { + REGULATOR_SUPPLY("lcd_2v8", NULL), +}; + +static struct regulator_init_data vmmc1_init = { + .constraints = { + .min_uV = 2800000, + .max_uV = 2800000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), + .consumer_supplies = vmmc1_consumers, +}; + +static struct regulator_consumer_supply vgen_consumers[] = { + REGULATOR_SUPPLY("vdd_lcdio", NULL), +}; + +static struct regulator_init_data vgen_init = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), + .consumer_supplies = vgen_consumers, +}; + +static struct mc13783_regulator_init_data mx27_3ds_regulators[] = { + { + .id = MC13783_REGU_VMMC1, + .init_data = &vmmc1_init, + }, { + .id = MC13783_REGU_VGEN, + .init_data = &vgen_init, + }, +}; + +/* MC13783 */ +static struct mc13783_platform_data mc13783_pdata __initdata = { + .regulators = mx27_3ds_regulators, + .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), + .flags = MC13783_USE_REGULATOR, +}; + +/* SPI */ +static int spi2_internal_chipselect[] = {SPI2_SS0}; + +static const struct spi_imx_master spi2_pdata __initconst = { + .chipselect = spi2_internal_chipselect, + .num_chipselect = ARRAY_SIZE(spi2_internal_chipselect), +}; + +static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { + { + .modalias = "mc13783", + .max_speed_hz = 1000000, + .bus_num = 1, + .chip_select = 0, /* SS0 */ + .platform_data = &mc13783_pdata, + .irq = IRQ_GPIOC(14), + .mode = SPI_CS_HIGH, + }, +}; + + static void __init mx27pdk_init(void) { mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), @@ -128,8 +258,24 @@ static void __init mx27pdk_init(void) mx27_3ds_sdhc1_enable_level_translator(); imx27_add_imx_uart0(&uart_pdata); imx27_add_fec(NULL); - mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data); - mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); + imx27_add_imx_keypad(&mx27_3ds_keymap_data); + imx27_add_mxc_mmc(0, &sdhc1_pdata); + imx27_add_imx2_wdt(NULL); + otg_phy_init(); +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + + imx27_add_mxc_ehci_otg(&otg_pdata); + } +#endif + if (!otg_mode_host) + imx27_add_fsl_usb2_udc(&otg_device_pdata); + + imx27_add_spi_imx1(&spi2_pdata); + spi_register_board_info(mx27_3ds_spi_devs, + ARRAY_SIZE(mx27_3ds_spi_devs)); } static void __init mx27pdk_timer_init(void) diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index a1e4bc5..b832f96 100644 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c @@ -30,11 +30,8 @@ #include <mach/gpio.h> #include <mach/iomux-mx27.h> #include <mach/mxc_nand.h> -#include <mach/imxfb.h> -#include <mach/mmc.h> #include "devices-imx27.h" -#include "devices.h" /* * Base address of PBC controller, CS4 @@ -228,7 +225,7 @@ static struct imx_fb_videomode mx27ads_modes[] = { }, }; -static struct imx_fb_platform_data mx27ads_fb_data = { +static const struct imx_fb_platform_data mx27ads_fb_data __initconst = { .mode = mx27ads_modes, .num_modes = ARRAY_SIZE(mx27ads_modes), @@ -272,19 +269,18 @@ static void mx27ads_sdhc2_exit(struct device *dev, void *data) free_irq(IRQ_GPIOB(7), data); } -static struct imxmmc_platform_data sdhc1_pdata = { +static const struct imxmmc_platform_data sdhc1_pdata __initconst = { .init = mx27ads_sdhc1_init, .exit = mx27ads_sdhc1_exit, }; -static struct imxmmc_platform_data sdhc2_pdata = { +static const struct imxmmc_platform_data sdhc2_pdata __initconst = { .init = mx27ads_sdhc2_init, .exit = mx27ads_sdhc2_exit, }; static struct platform_device *platform_devices[] __initdata = { &mx27ads_nor_mtd_device, - &mxc_w1_master_device, }; static const struct imxuart_platform_data uart_pdata __initconst = { @@ -308,12 +304,13 @@ static void __init mx27ads_board_init(void) i2c_register_board_info(1, mx27ads_i2c_devices, ARRAY_SIZE(mx27ads_i2c_devices)); imx27_add_imx_i2c(1, &mx27ads_i2c1_data); - mxc_register_device(&mxc_fb_device, &mx27ads_fb_data); - mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); - mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata); + imx27_add_imx_fb(&mx27ads_fb_data); + imx27_add_mxc_mmc(0, &sdhc1_pdata); + imx27_add_mxc_mmc(1, &sdhc2_pdata); imx27_add_fec(NULL); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + imx27_add_mxc_w1(NULL); } static void __init mx27ads_timer_init(void) diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c index 38d3a4a..4ce71b0 100644 --- a/arch/arm/mach-imx/mach-mxt_td60.c +++ b/arch/arm/mach-imx/mach-mxt_td60.c @@ -31,11 +31,8 @@ #include <mach/iomux-mx27.h> #include <mach/mxc_nand.h> #include <linux/i2c/pca953x.h> -#include <mach/imxfb.h> -#include <mach/mmc.h> #include "devices-imx27.h" -#include "devices.h" static const int mxt_td60_pins[] __initconst = { /* UART0 */ @@ -196,7 +193,7 @@ static struct imx_fb_videomode mxt_td60_modes[] = { }, }; -static struct imx_fb_platform_data mxt_td60_fb_data = { +static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = { .mode = mxt_td60_modes, .num_modes = ARRAY_SIZE(mxt_td60_modes), @@ -226,7 +223,7 @@ static void mxt_td60_sdhc1_exit(struct device *dev, void *data) free_irq(IRQ_GPIOF(8), data); } -static struct imxmmc_platform_data sdhc1_pdata = { +static const struct imxmmc_platform_data sdhc1_pdata __initconst = { .init = mxt_td60_sdhc1_init, .exit = mxt_td60_sdhc1_exit, }; @@ -253,8 +250,8 @@ static void __init mxt_td60_board_init(void) imx27_add_imx_i2c(0, &mxt_td60_i2c0_data); imx27_add_imx_i2c(1, &mxt_td60_i2c1_data); - mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data); - mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); + imx27_add_imx_fb(&mxt_td60_fb_data); + imx27_add_mxc_mmc(0, &sdhc1_pdata); imx27_add_fec(NULL); } diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 8c720d4..cccc0a0 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -29,7 +29,6 @@ #include <linux/gpio.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> -#include <linux/fsl_devices.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -40,13 +39,9 @@ #include <mach/audmux.h> #include <mach/mxc_nand.h> #include <mach/irqs.h> -#include <mach/mmc.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> -#include <mach/imxfb.h> #include "devices-imx27.h" -#include "devices.h" #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) @@ -171,11 +166,6 @@ pca100_nand_board_info __initconst = { .hw_ecc = 1, }; -static struct platform_device *platform_devices[] __initdata = { - &mxc_w1_master_device, - &mxc_wdt, -}; - static const struct imxi2c_platform_data pca100_i2c1_data __initconst = { .bitrate = 100000, }; @@ -274,7 +264,7 @@ static void pca100_sdhc2_exit(struct device *dev, void *data) free_irq(IRQ_GPIOC(29), data); } -static struct imxmmc_platform_data sdhc_pdata = { +static const struct imxmmc_platform_data sdhc_pdata __initconst = { .init = pca100_sdhc2_init, .exit = pca100_sdhc2_exit, }; @@ -286,7 +276,7 @@ static int otg_phy_init(struct platform_device *pdev) return 0; } -static struct mxc_usbh_platform_data otg_pdata = { +static struct mxc_usbh_platform_data otg_pdata __initdata = { .init = otg_phy_init, .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, @@ -298,14 +288,14 @@ static int usbh2_phy_init(struct platform_device *pdev) return 0; } -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_phy_init, .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; #endif -static struct fsl_usb2_platform_data otg_device_pdata = { +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; @@ -355,7 +345,7 @@ static struct imx_fb_videomode pca100_fb_modes[] = { }, }; -static struct imx_fb_platform_data pca100_fb_data = { +static const struct imx_fb_platform_data pca100_fb_data __initconst = { .mode = pca100_fb_modes, .num_modes = ARRAY_SIZE(pca100_fb_modes), @@ -389,7 +379,7 @@ static void __init pca100_init(void) imx27_add_imx_uart0(&uart_pdata); - mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); + imx27_add_mxc_mmc(1, &sdhc_pdata); imx27_add_mxc_nand(&pca100_nand_board_info); @@ -417,23 +407,24 @@ static void __init pca100_init(void) otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_otg_host, &otg_pdata); + imx27_add_mxc_ehci_otg(&otg_pdata); } usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx27_add_mxc_ehci_hs(2, &usbh2_pdata); #endif if (!otg_mode_host) { gpio_set_value(OTG_PHY_CS_GPIO, 0); - mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + imx27_add_fsl_usb2_udc(&otg_device_pdata); } - mxc_register_device(&mxc_fb_device, &pca100_fb_data); + imx27_add_imx_fb(&pca100_fb_data); imx27_add_fec(NULL); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + imx27_add_imx2_wdt(NULL); + imx27_add_mxc_w1(NULL); } static void __init pca100_timer_init(void) diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 49a97ce..f667a26 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -37,11 +37,9 @@ #include <mach/hardware.h> #include <mach/iomux-mx27.h> #include <mach/mxc_nand.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx27.h" -#include "devices.h" static const int pcm038_pins[] __initconst = { /* UART1 */ @@ -172,9 +170,7 @@ pcm038_nand_board_info __initconst = { static struct platform_device *platform_devices[] __initdata = { &pcm038_nor_mtd_device, - &mxc_w1_master_device, &pcm038_sram_mtd_device, - &mxc_wdt, }; /* On pcm038 there's a sram attached to CS1, we enable the chipselect here and @@ -214,7 +210,7 @@ static const struct spi_imx_master pcm038_spi0_data __initconst = { static struct regulator_consumer_supply sdhc1_consumers[] = { { - .dev = &mxc_sdhc_device1.dev, + .dev_name = "mxc-mmc.1", .supply = "sdhc_vcc", }, }; @@ -285,7 +281,7 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = { } }; -static struct mxc_usbh_platform_data usbh2_pdata = { +static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, }; @@ -322,10 +318,12 @@ static void __init pcm038_init(void) spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx27_add_mxc_ehci_hs(2, &usbh2_pdata); imx27_add_fec(NULL); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + imx27_add_imx2_wdt(NULL); + imx27_add_mxc_w1(NULL); #ifdef CONFIG_MACH_PCM970_BASEBOARD pcm970_baseboard_init(); diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c index 1fbdd3f..eae878f 100644 --- a/arch/arm/mach-imx/mach-scb9328.c +++ b/arch/arm/mach-imx/mach-scb9328.c @@ -25,7 +25,6 @@ #include <mach/iomux-mx1.h> #include "devices-imx1.h" -#include "devices.h" /* * This scb9328 has a 32MiB flash diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c index 9be92b9..729ae09 100644 --- a/arch/arm/mach-imx/mm-imx1.c +++ b/arch/arm/mach-imx/mm-imx1.c @@ -25,12 +25,7 @@ #include <mach/hardware.h> static struct map_desc imx_io_desc[] __initdata = { - { - .virtual = MX1_IO_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX1_IO_BASE_ADDR), - .length = MX1_IO_SIZE, - .type = MT_DEVICE - } + imx_map_entry(MX1, IO, MT_DEVICE), }; void __init mx1_map_io(void) diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index 12faeeaa..e728af8 100644 --- a/arch/arm/mach-imx/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c @@ -35,33 +35,18 @@ static struct map_desc imx21_io_desc[] __initdata = { * - ROM Patch * - and some reserved space */ - { - .virtual = MX21_AIPI_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR), - .length = MX21_AIPI_SIZE, - .type = MT_DEVICE - }, + imx_map_entry(MX21, AIPI, MT_DEVICE), /* * this fixed mapping covers: * - CSI * - ATA */ - { - .virtual = MX21_SAHB1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR), - .length = MX21_SAHB1_SIZE, - .type = MT_DEVICE - }, + imx_map_entry(MX21, SAHB1, MT_DEVICE), /* * this fixed mapping covers: * - EMI */ - { - .virtual = MX21_X_MEMC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR), - .length = MX21_X_MEMC_SIZE, - .type = MT_DEVICE - }, + imx_map_entry(MX21, X_MEMC, MT_DEVICE), }; /* diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-imx/mm-imx25.c index bb67711..2edec6c 100644 --- a/arch/arm/mach-mx25/mm.c +++ b/arch/arm/mach-imx/mm-imx25.c @@ -30,25 +30,12 @@ /* * This table defines static virtual address mappings for I/O regions. - * These are the mappings common across all MX3 boards. + * These are the mappings common across all MX25 boards. */ -static struct map_desc mxc_io_desc[] __initdata = { - { - .virtual = MX25_AVIC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX25_AVIC_BASE_ADDR), - .length = MX25_AVIC_SIZE, - .type = MT_DEVICE_NONSHARED - }, { - .virtual = MX25_AIPS1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX25_AIPS1_BASE_ADDR), - .length = MX25_AIPS1_SIZE, - .type = MT_DEVICE_NONSHARED - }, { - .virtual = MX25_AIPS2_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX25_AIPS2_BASE_ADDR), - .length = MX25_AIPS2_SIZE, - .type = MT_DEVICE_NONSHARED - }, +static struct map_desc mx25_io_desc[] __initdata = { + imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED), + imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED), + imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED), }; /* @@ -62,14 +49,14 @@ void __init mx25_map_io(void) mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); + iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc)); } int imx25_register_gpios(void); void __init mx25_init_irq(void) { - mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT); + mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR)); imx25_register_gpios(); } diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index a246229..374e48b 100644 --- a/arch/arm/mach-imx/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c @@ -35,33 +35,18 @@ static struct map_desc imx27_io_desc[] __initdata = { * - ROM Patch * - and some reserved space */ - { - .virtual = MX27_AIPI_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR), - .length = MX27_AIPI_SIZE, - .type = MT_DEVICE - }, + imx_map_entry(MX27, AIPI, MT_DEVICE), /* * this fixed mapping covers: * - CSI * - ATA */ - { - .virtual = MX27_SAHB1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR), - .length = MX27_SAHB1_SIZE, - .type = MT_DEVICE - }, + imx_map_entry(MX27, SAHB1, MT_DEVICE), /* * this fixed mapping covers: * - EMI */ - { - .virtual = MX27_X_MEMC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR), - .length = MX27_X_MEMC_SIZE, - .type = MT_DEVICE - }, + imx_map_entry(MX27, X_MEMC, MT_DEVICE), }; /* diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c index 9110d9c..99afbc3 100644 --- a/arch/arm/mach-imx/pcm970-baseboard.c +++ b/arch/arm/mach-imx/pcm970-baseboard.c @@ -25,11 +25,9 @@ #include <mach/common.h> #include <mach/iomux-mx27.h> -#include <mach/imxfb.h> #include <mach/hardware.h> -#include <mach/mmc.h> -#include "devices.h" +#include "devices-imx27.h" static const int pcm970_pins[] __initconst = { /* SDHC */ @@ -119,7 +117,7 @@ static void pcm970_sdhc2_exit(struct device *dev, void *data) gpio_free(GPIO_PORTC + 28); } -static struct imxmmc_platform_data sdhc_pdata = { +static const struct imxmmc_platform_data sdhc_pdata __initconst = { .get_ro = pcm970_sdhc2_get_ro, .init = pcm970_sdhc2_init, .exit = pcm970_sdhc2_exit, @@ -179,7 +177,7 @@ static struct imx_fb_videomode pcm970_modes[] = { }, }; -static struct imx_fb_platform_data pcm038_fb_data = { +static const struct imx_fb_platform_data pcm038_fb_data __initconst = { .mode = pcm970_modes, .num_modes = ARRAY_SIZE(pcm970_modes), @@ -226,8 +224,8 @@ void __init pcm970_baseboard_init(void) mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins), "PCM970"); - mxc_register_device(&mxc_fb_device, &pcm038_fb_data); + imx27_add_imx_fb(&pcm038_fb_data); mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN); - mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); + imx27_add_mxc_mmc(1, &sdhc_pdata); platform_device_register(&pcm970_sja1000); } diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c index afc17ce..6bf81ce 100644 --- a/arch/arm/mach-imx/pm-imx27.c +++ b/arch/arm/mach-imx/pm-imx27.c @@ -39,6 +39,9 @@ static struct platform_suspend_ops mx27_suspend_ops = { static int __init mx27_pm_init(void) { + if (!cpu_is_mx27()) + return 0; + suspend_set_ops(&mx27_suspend_ops); return 0; } diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 3410633..7fc603b 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -45,18 +45,18 @@ config MACH_GURUPLUG Marvell GuruPlug Reference Board. config MACH_TS219 - bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS" + bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS" help Say 'Y' here if you want your kernel to support the - QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS - devices. + QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and + TS-219P+ Turbo NAS devices. config MACH_TS41X - bool "QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS" + bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS" help Say 'Y' here if you want your kernel to support the - QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS - devices. + QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo + NAS devices. config MACH_DOCKSTAR bool "Seagate FreeAgent DockStar" diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c index 6710bd7..dc999c4 100644 --- a/arch/arm/mach-kirkwood/ts219-setup.c +++ b/arch/arm/mach-kirkwood/ts219-setup.c @@ -80,15 +80,19 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = { MPP11_UART0_RXD, MPP13_UART1_TXD, /* PIC controller */ MPP14_UART1_RXD, /* PIC controller */ - MPP15_GPIO, /* USB Copy button */ - MPP16_GPIO, /* Reset button */ + MPP15_GPIO, /* USB Copy button (on devices with 88F6281) */ + MPP16_GPIO, /* Reset button (on devices with 88F6281) */ MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ + MPP37_GPIO, /* Reset button (on devices with 88F6282) */ + MPP43_GPIO, /* USB Copy button (on devices with 88F6282) */ MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */ 0 }; static void __init qnap_ts219_init(void) { + u32 dev, rev; + /* * Basic setup. Needs to be called early. */ @@ -100,6 +104,14 @@ static void __init qnap_ts219_init(void) qnap_tsx1x_register_flash(); kirkwood_i2c_init(); i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1); + + kirkwood_pcie_id(&dev, &rev); + if (dev == MV88F6282_DEV_ID) { + qnap_ts219_buttons[0].gpio = 43; /* USB Copy button */ + qnap_ts219_buttons[1].gpio = 37; /* Reset button */ + qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); + } + kirkwood_ge00_init(&qnap_ts219_ge00_data); kirkwood_sata_init(&qnap_ts219_sata_data); kirkwood_ehci_init(); diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c index 3587a28..9a44029 100644 --- a/arch/arm/mach-kirkwood/ts41x-setup.c +++ b/arch/arm/mach-kirkwood/ts41x-setup.c @@ -119,6 +119,8 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = { static void __init qnap_ts41x_init(void) { + u32 dev, rev; + /* * Basic setup. Needs to be called early. */ @@ -130,8 +132,15 @@ static void __init qnap_ts41x_init(void) qnap_tsx1x_register_flash(); kirkwood_i2c_init(); i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1); + + kirkwood_pcie_id(&dev, &rev); + if (dev == MV88F6282_DEV_ID) { + qnap_ts41x_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); + qnap_ts41x_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1); + } kirkwood_ge00_init(&qnap_ts41x_ge00_data); kirkwood_ge01_init(&qnap_ts41x_ge01_data); + kirkwood_sata_init(&qnap_ts41x_sata_data); kirkwood_ehci_init(); platform_device_register(&qnap_ts41x_button_device); diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index 0711d3b..67793a6 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -37,25 +37,38 @@ config MACH_TTC_DKB Say 'Y' here if you want to support the Marvell PXA910-based TTC_DKB Development Board. +config MACH_BROWNSTONE + bool "Marvell's Brownstone Development Platform" + depends on !CPU_MOHAWK + select CPU_MMP2 + help + Say 'Y' here if you want to support the Marvell MMP2-based + Brown Development Platform. + MMP2-based board can't be co-existed with PXA168-based & + PXA910-based development board. Since MMP2 is compatible to + ARMv7 architecture. + config MACH_FLINT bool "Marvell's Flint Development Platform" + depends on !CPU_MOHAWK select CPU_MMP2 help Say 'Y' here if you want to support the Marvell MMP2-based Flint Development Platform. MMP2-based board can't be co-existed with PXA168-based & PXA910-based development board. Since MMP2 is compatible to - ARMv6 architecture. + ARMv7 architecture. config MACH_MARVELL_JASPER bool "Marvell's Jasper Development Platform" + depends on !CPU_MOHAWK select CPU_MMP2 help Say 'Y' here if you want to support the Marvell MMP2-base Jasper Development Platform. MMP2-based board can't be co-existed with PXA168-based & PXA910-based development board. Since MMP2 is compatible to - ARMv6 architecture. + ARMv7 architecture. config MACH_TETON_BGA bool "Marvell's PXA168 Teton BGA Development Board" @@ -80,8 +93,7 @@ config CPU_PXA910 config CPU_MMP2 bool - select CPU_V6 - select CPU_32v6K + select CPU_PJ4 help - Select code specific to MMP2. MMP2 is ARMv6 compatible. + Select code specific to MMP2. MMP2 is ARMv7 compatible. endif diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 751cdbf..5c68382 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o +obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o obj-$(CONFIG_MACH_FLINT) += flint.o obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c new file mode 100644 index 0000000..7bb78fd --- /dev/null +++ b/arch/arm/mach-mmp/brownstone.c @@ -0,0 +1,204 @@ +/* + * linux/arch/arm/mach-mmp/brownstone.c + * + * Support for the Marvell Brownstone Development Platform. + * + * Copyright (C) 2009-2010 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/max8649.h> +#include <linux/regulator/fixed.h> +#include <linux/mfd/max8925.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/addr-map.h> +#include <mach/mfp-mmp2.h> +#include <mach/mmp2.h> +#include <mach/irqs.h> + +#include "common.h" + +#define BROWNSTONE_NR_IRQS (IRQ_BOARD_START + 40) + +#define GPIO_5V_ENABLE (89) + +static unsigned long brownstone_pin_config[] __initdata = { + /* UART1 */ + GPIO29_UART1_RXD, + GPIO30_UART1_TXD, + + /* UART3 */ + GPIO51_UART3_RXD, + GPIO52_UART3_TXD, + + /* DFI */ + GPIO168_DFI_D0, + GPIO167_DFI_D1, + GPIO166_DFI_D2, + GPIO165_DFI_D3, + GPIO107_DFI_D4, + GPIO106_DFI_D5, + GPIO105_DFI_D6, + GPIO104_DFI_D7, + GPIO111_DFI_D8, + GPIO164_DFI_D9, + GPIO163_DFI_D10, + GPIO162_DFI_D11, + GPIO161_DFI_D12, + GPIO110_DFI_D13, + GPIO109_DFI_D14, + GPIO108_DFI_D15, + GPIO143_ND_nCS0, + GPIO144_ND_nCS1, + GPIO147_ND_nWE, + GPIO148_ND_nRE, + GPIO150_ND_ALE, + GPIO149_ND_CLE, + GPIO112_ND_RDY0, + GPIO160_ND_RDY1, + + /* PMIC */ + PMIC_PMIC_INT | MFP_LPM_EDGE_FALL, + + /* MMC0 */ + GPIO131_MMC1_DAT3 | MFP_PULL_HIGH, + GPIO132_MMC1_DAT2 | MFP_PULL_HIGH, + GPIO133_MMC1_DAT1 | MFP_PULL_HIGH, + GPIO134_MMC1_DAT0 | MFP_PULL_HIGH, + GPIO136_MMC1_CMD | MFP_PULL_HIGH, + GPIO139_MMC1_CLK, + GPIO140_MMC1_CD | MFP_PULL_LOW, + GPIO141_MMC1_WP | MFP_PULL_LOW, + + /* MMC1 */ + GPIO37_MMC2_DAT3 | MFP_PULL_HIGH, + GPIO38_MMC2_DAT2 | MFP_PULL_HIGH, + GPIO39_MMC2_DAT1 | MFP_PULL_HIGH, + GPIO40_MMC2_DAT0 | MFP_PULL_HIGH, + GPIO41_MMC2_CMD | MFP_PULL_HIGH, + GPIO42_MMC2_CLK, + + /* MMC2 */ + GPIO165_MMC3_DAT7 | MFP_PULL_HIGH, + GPIO162_MMC3_DAT6 | MFP_PULL_HIGH, + GPIO166_MMC3_DAT5 | MFP_PULL_HIGH, + GPIO163_MMC3_DAT4 | MFP_PULL_HIGH, + GPIO167_MMC3_DAT3 | MFP_PULL_HIGH, + GPIO164_MMC3_DAT2 | MFP_PULL_HIGH, + GPIO168_MMC3_DAT1 | MFP_PULL_HIGH, + GPIO111_MMC3_DAT0 | MFP_PULL_HIGH, + GPIO112_MMC3_CMD | MFP_PULL_HIGH, + GPIO151_MMC3_CLK, + + /* 5V regulator */ + GPIO89_GPIO, +}; + +static struct regulator_consumer_supply max8649_supply[] = { + REGULATOR_SUPPLY("vcc_core", NULL), +}; + +static struct regulator_init_data max8649_init_data = { + .constraints = { + .name = "vcc_core range", + .min_uV = 1150000, + .max_uV = 1280000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8649_supply[0], +}; + +static struct max8649_platform_data brownstone_max8649_info = { + .mode = 2, /* VID1 = 1, VID0 = 0 */ + .extclk = 0, + .ramp_timing = MAX8649_RAMP_32MV, + .regulator = &max8649_init_data, +}; + +static struct regulator_consumer_supply brownstone_v_5vp_supplies[] = { + REGULATOR_SUPPLY("v_5vp", NULL), +}; + +static struct regulator_init_data brownstone_v_5vp_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(brownstone_v_5vp_supplies), + .consumer_supplies = brownstone_v_5vp_supplies, +}; + +static struct fixed_voltage_config brownstone_v_5vp = { + .supply_name = "v_5vp", + .microvolts = 5000000, + .gpio = GPIO_5V_ENABLE, + .enable_high = 1, + .enabled_at_boot = 1, + .init_data = &brownstone_v_5vp_data, +}; + +static struct platform_device brownstone_v_5vp_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &brownstone_v_5vp, + }, +}; + +static struct max8925_platform_data brownstone_max8925_info = { + .irq_base = IRQ_BOARD_START, +}; + +static struct i2c_board_info brownstone_twsi1_info[] = { + [0] = { + .type = "max8649", + .addr = 0x60, + .platform_data = &brownstone_max8649_info, + }, + [1] = { + .type = "max8925", + .addr = 0x3c, + .irq = IRQ_MMP2_PMIC, + .platform_data = &brownstone_max8925_info, + }, +}; + +static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = { + .max_speed = 25000000, +}; + +static void __init brownstone_init(void) +{ + mfp_config(ARRAY_AND_SIZE(brownstone_pin_config)); + + /* on-chip devices */ + mmp2_add_uart(1); + mmp2_add_uart(3); + mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info)); + mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */ + + /* enable 5v regulator */ + platform_device_register(&brownstone_v_5vp_device); +} + +MACHINE_START(BROWNSTONE, "Brownstone Development Platform") + /* Maintainer: Haojian Zhuang <haojian.zhuang@marvell.com> */ + .map_io = mmp_map_io, + .nr_irqs = BROWNSTONE_NR_IRQS, + .init_irq = mmp2_init_irq, + .timer = &mmp2_timer, + .init_machine = brownstone_init, +MACHINE_END diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c index bdeb6db..c4fd806 100644 --- a/arch/arm/mach-mmp/flint.c +++ b/arch/arm/mach-mmp/flint.c @@ -47,7 +47,7 @@ static unsigned long flint_pin_config[] __initdata = { GPIO113_SMC_RDY, /*Ethernet*/ - GPIO155_GPIO155, + GPIO155_GPIO, /* DFI */ GPIO168_DFI_D0, diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h index 761c2da..117e303 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h +++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h @@ -9,175 +9,175 @@ #define MFP_DRIVE_FAST (0x8 << 13) /* GPIO */ -#define GPIO0_GPIO0 MFP_CFG(GPIO0, AF0) -#define GPIO1_GPIO1 MFP_CFG(GPIO1, AF0) -#define GPIO2_GPIO2 MFP_CFG(GPIO2, AF0) -#define GPIO3_GPIO3 MFP_CFG(GPIO3, AF0) -#define GPIO4_GPIO4 MFP_CFG(GPIO4, AF0) -#define GPIO5_GPIO5 MFP_CFG(GPIO5, AF0) -#define GPIO6_GPIO6 MFP_CFG(GPIO6, AF0) -#define GPIO7_GPIO7 MFP_CFG(GPIO7, AF0) -#define GPIO8_GPIO8 MFP_CFG(GPIO8, AF0) -#define GPIO9_GPIO9 MFP_CFG(GPIO9, AF0) -#define GPIO10_GPIO10 MFP_CFG(GPIO10, AF0) -#define GPIO11_GPIO11 MFP_CFG(GPIO11, AF0) -#define GPIO12_GPIO12 MFP_CFG(GPIO12, AF0) -#define GPIO13_GPIO13 MFP_CFG(GPIO13, AF0) -#define GPIO14_GPIO14 MFP_CFG(GPIO14, AF0) -#define GPIO15_GPIO15 MFP_CFG(GPIO15, AF0) -#define GPIO16_GPIO16 MFP_CFG(GPIO16, AF0) -#define GPIO17_GPIO17 MFP_CFG(GPIO17, AF0) -#define GPIO18_GPIO18 MFP_CFG(GPIO18, AF0) -#define GPIO19_GPIO19 MFP_CFG(GPIO19, AF0) -#define GPIO20_GPIO20 MFP_CFG(GPIO20, AF0) -#define GPIO21_GPIO21 MFP_CFG(GPIO21, AF0) -#define GPIO22_GPIO22 MFP_CFG(GPIO22, AF0) -#define GPIO23_GPIO23 MFP_CFG(GPIO23, AF0) -#define GPIO24_GPIO24 MFP_CFG(GPIO24, AF0) -#define GPIO25_GPIO25 MFP_CFG(GPIO25, AF0) -#define GPIO26_GPIO26 MFP_CFG(GPIO26, AF0) -#define GPIO27_GPIO27 MFP_CFG(GPIO27, AF0) -#define GPIO28_GPIO28 MFP_CFG(GPIO28, AF0) -#define GPIO29_GPIO29 MFP_CFG(GPIO29, AF0) -#define GPIO30_GPIO30 MFP_CFG(GPIO30, AF0) -#define GPIO31_GPIO31 MFP_CFG(GPIO31, AF0) -#define GPIO32_GPIO32 MFP_CFG(GPIO32, AF0) -#define GPIO33_GPIO33 MFP_CFG(GPIO33, AF0) -#define GPIO34_GPIO34 MFP_CFG(GPIO34, AF0) -#define GPIO35_GPIO35 MFP_CFG(GPIO35, AF0) -#define GPIO36_GPIO36 MFP_CFG(GPIO36, AF0) -#define GPIO37_GPIO37 MFP_CFG(GPIO37, AF0) -#define GPIO38_GPIO38 MFP_CFG(GPIO38, AF0) -#define GPIO39_GPIO39 MFP_CFG(GPIO39, AF0) -#define GPIO40_GPIO40 MFP_CFG(GPIO40, AF0) -#define GPIO41_GPIO41 MFP_CFG(GPIO41, AF0) -#define GPIO42_GPIO42 MFP_CFG(GPIO42, AF0) -#define GPIO43_GPIO43 MFP_CFG(GPIO43, AF0) -#define GPIO44_GPIO44 MFP_CFG(GPIO44, AF0) -#define GPIO45_GPIO45 MFP_CFG(GPIO45, AF0) -#define GPIO46_GPIO46 MFP_CFG(GPIO46, AF0) -#define GPIO47_GPIO47 MFP_CFG(GPIO47, AF0) -#define GPIO48_GPIO48 MFP_CFG(GPIO48, AF0) -#define GPIO49_GPIO49 MFP_CFG(GPIO49, AF0) -#define GPIO50_GPIO50 MFP_CFG(GPIO50, AF0) -#define GPIO51_GPIO51 MFP_CFG(GPIO51, AF0) -#define GPIO52_GPIO52 MFP_CFG(GPIO52, AF0) -#define GPIO53_GPIO53 MFP_CFG(GPIO53, AF0) -#define GPIO54_GPIO54 MFP_CFG(GPIO54, AF0) -#define GPIO55_GPIO55 MFP_CFG(GPIO55, AF0) -#define GPIO56_GPIO56 MFP_CFG(GPIO56, AF0) -#define GPIO57_GPIO57 MFP_CFG(GPIO57, AF0) -#define GPIO58_GPIO58 MFP_CFG(GPIO58, AF0) -#define GPIO59_GPIO59 MFP_CFG(GPIO59, AF0) -#define GPIO60_GPIO60 MFP_CFG(GPIO60, AF0) -#define GPIO61_GPIO61 MFP_CFG(GPIO61, AF0) -#define GPIO62_GPIO62 MFP_CFG(GPIO62, AF0) -#define GPIO63_GPIO63 MFP_CFG(GPIO63, AF0) -#define GPIO64_GPIO64 MFP_CFG(GPIO64, AF0) -#define GPIO65_GPIO65 MFP_CFG(GPIO65, AF0) -#define GPIO66_GPIO66 MFP_CFG(GPIO66, AF0) -#define GPIO67_GPIO67 MFP_CFG(GPIO67, AF0) -#define GPIO68_GPIO68 MFP_CFG(GPIO68, AF0) -#define GPIO69_GPIO69 MFP_CFG(GPIO69, AF0) -#define GPIO70_GPIO70 MFP_CFG(GPIO70, AF0) -#define GPIO71_GPIO71 MFP_CFG(GPIO71, AF0) -#define GPIO72_GPIO72 MFP_CFG(GPIO72, AF0) -#define GPIO73_GPIO73 MFP_CFG(GPIO73, AF0) -#define GPIO74_GPIO74 MFP_CFG(GPIO74, AF0) -#define GPIO75_GPIO75 MFP_CFG(GPIO75, AF0) -#define GPIO76_GPIO76 MFP_CFG(GPIO76, AF0) -#define GPIO77_GPIO77 MFP_CFG(GPIO77, AF0) -#define GPIO78_GPIO78 MFP_CFG(GPIO78, AF0) -#define GPIO79_GPIO79 MFP_CFG(GPIO79, AF0) -#define GPIO80_GPIO80 MFP_CFG(GPIO80, AF0) -#define GPIO81_GPIO81 MFP_CFG(GPIO81, AF0) -#define GPIO82_GPIO82 MFP_CFG(GPIO82, AF0) -#define GPIO83_GPIO83 MFP_CFG(GPIO83, AF0) -#define GPIO84_GPIO84 MFP_CFG(GPIO84, AF0) -#define GPIO85_GPIO85 MFP_CFG(GPIO85, AF0) -#define GPIO86_GPIO86 MFP_CFG(GPIO86, AF0) -#define GPIO87_GPIO87 MFP_CFG(GPIO87, AF0) -#define GPIO88_GPIO88 MFP_CFG(GPIO88, AF0) -#define GPIO89_GPIO89 MFP_CFG(GPIO89, AF0) -#define GPIO90_GPIO90 MFP_CFG(GPIO90, AF0) -#define GPIO91_GPIO91 MFP_CFG(GPIO91, AF0) -#define GPIO92_GPIO92 MFP_CFG(GPIO92, AF0) -#define GPIO93_GPIO93 MFP_CFG(GPIO93, AF0) -#define GPIO94_GPIO94 MFP_CFG(GPIO94, AF0) -#define GPIO95_GPIO95 MFP_CFG(GPIO95, AF0) -#define GPIO96_GPIO96 MFP_CFG(GPIO96, AF0) -#define GPIO97_GPIO97 MFP_CFG(GPIO97, AF0) -#define GPIO98_GPIO98 MFP_CFG(GPIO98, AF0) -#define GPIO99_GPIO99 MFP_CFG(GPIO99, AF0) -#define GPIO100_GPIO100 MFP_CFG(GPIO100, AF0) -#define GPIO101_GPIO101 MFP_CFG(GPIO101, AF0) -#define GPIO102_GPIO102 MFP_CFG(GPIO102, AF1) -#define GPIO103_GPIO103 MFP_CFG(GPIO103, AF1) -#define GPIO104_GPIO104 MFP_CFG(GPIO104, AF1) -#define GPIO105_GPIO105 MFP_CFG(GPIO105, AF1) -#define GPIO106_GPIO106 MFP_CFG(GPIO106, AF1) -#define GPIO107_GPIO107 MFP_CFG(GPIO107, AF1) -#define GPIO108_GPIO108 MFP_CFG(GPIO108, AF1) -#define GPIO109_GPIO109 MFP_CFG(GPIO109, AF1) -#define GPIO110_GPIO110 MFP_CFG(GPIO110, AF1) -#define GPIO111_GPIO111 MFP_CFG(GPIO111, AF1) -#define GPIO112_GPIO112 MFP_CFG(GPIO112, AF1) -#define GPIO113_GPIO113 MFP_CFG(GPIO113, AF1) -#define GPIO114_GPIO114 MFP_CFG(GPIO114, AF0) -#define GPIO115_GPIO115 MFP_CFG(GPIO115, AF0) -#define GPIO116_GPIO116 MFP_CFG(GPIO116, AF0) -#define GPIO117_GPIO117 MFP_CFG(GPIO117, AF0) -#define GPIO118_GPIO118 MFP_CFG(GPIO118, AF0) -#define GPIO119_GPIO119 MFP_CFG(GPIO119, AF0) -#define GPIO120_GPIO120 MFP_CFG(GPIO120, AF0) -#define GPIO121_GPIO121 MFP_CFG(GPIO121, AF0) -#define GPIO122_GPIO122 MFP_CFG(GPIO122, AF0) -#define GPIO123_GPIO123 MFP_CFG(GPIO123, AF0) -#define GPIO124_GPIO124 MFP_CFG(GPIO124, AF0) -#define GPIO125_GPIO125 MFP_CFG(GPIO125, AF0) -#define GPIO126_GPIO126 MFP_CFG(GPIO126, AF0) -#define GPIO127_GPIO127 MFP_CFG(GPIO127, AF0) -#define GPIO128_GPIO128 MFP_CFG(GPIO128, AF0) -#define GPIO129_GPIO129 MFP_CFG(GPIO129, AF0) -#define GPIO130_GPIO130 MFP_CFG(GPIO130, AF0) -#define GPIO131_GPIO131 MFP_CFG(GPIO131, AF0) -#define GPIO132_GPIO132 MFP_CFG(GPIO132, AF0) -#define GPIO133_GPIO133 MFP_CFG(GPIO133, AF0) -#define GPIO134_GPIO134 MFP_CFG(GPIO134, AF0) -#define GPIO135_GPIO135 MFP_CFG(GPIO135, AF0) -#define GPIO136_GPIO136 MFP_CFG(GPIO136, AF0) -#define GPIO137_GPIO137 MFP_CFG(GPIO137, AF0) -#define GPIO138_GPIO138 MFP_CFG(GPIO138, AF0) -#define GPIO139_GPIO139 MFP_CFG(GPIO139, AF0) -#define GPIO140_GPIO140 MFP_CFG(GPIO140, AF0) -#define GPIO141_GPIO141 MFP_CFG(GPIO141, AF0) -#define GPIO142_GPIO142 MFP_CFG(GPIO142, AF1) -#define GPIO143_GPIO143 MFP_CFG(GPIO143, AF1) -#define GPIO144_GPIO144 MFP_CFG(GPIO144, AF1) -#define GPIO145_GPIO145 MFP_CFG(GPIO145, AF1) -#define GPIO146_GPIO146 MFP_CFG(GPIO146, AF1) -#define GPIO147_GPIO147 MFP_CFG(GPIO147, AF1) -#define GPIO148_GPIO148 MFP_CFG(GPIO148, AF1) -#define GPIO149_GPIO149 MFP_CFG(GPIO149, AF1) -#define GPIO150_GPIO150 MFP_CFG(GPIO150, AF1) -#define GPIO151_GPIO151 MFP_CFG(GPIO151, AF1) -#define GPIO152_GPIO152 MFP_CFG(GPIO152, AF1) -#define GPIO153_GPIO153 MFP_CFG(GPIO153, AF1) -#define GPIO154_GPIO154 MFP_CFG(GPIO154, AF1) -#define GPIO155_GPIO155 MFP_CFG(GPIO155, AF1) -#define GPIO156_GPIO156 MFP_CFG(GPIO156, AF1) -#define GPIO157_GPIO157 MFP_CFG(GPIO157, AF1) -#define GPIO158_GPIO158 MFP_CFG(GPIO158, AF1) -#define GPIO159_GPIO159 MFP_CFG(GPIO159, AF1) -#define GPIO160_GPIO160 MFP_CFG(GPIO160, AF1) -#define GPIO161_GPIO161 MFP_CFG(GPIO161, AF1) -#define GPIO162_GPIO162 MFP_CFG(GPIO162, AF1) -#define GPIO163_GPIO163 MFP_CFG(GPIO163, AF1) -#define GPIO164_GPIO164 MFP_CFG(GPIO164, AF1) -#define GPIO165_GPIO165 MFP_CFG(GPIO165, AF1) -#define GPIO166_GPIO166 MFP_CFG(GPIO166, AF1) -#define GPIO167_GPIO167 MFP_CFG(GPIO167, AF1) -#define GPIO168_GPIO168 MFP_CFG(GPIO168, AF1) +#define GPIO0_GPIO MFP_CFG(GPIO0, AF0) +#define GPIO1_GPIO MFP_CFG(GPIO1, AF0) +#define GPIO2_GPIO MFP_CFG(GPIO2, AF0) +#define GPIO3_GPIO MFP_CFG(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG(GPIO4, AF0) +#define GPIO5_GPIO MFP_CFG(GPIO5, AF0) +#define GPIO6_GPIO MFP_CFG(GPIO6, AF0) +#define GPIO7_GPIO MFP_CFG(GPIO7, AF0) +#define GPIO8_GPIO MFP_CFG(GPIO8, AF0) +#define GPIO9_GPIO MFP_CFG(GPIO9, AF0) +#define GPIO10_GPIO MFP_CFG(GPIO10, AF0) +#define GPIO11_GPIO MFP_CFG(GPIO11, AF0) +#define GPIO12_GPIO MFP_CFG(GPIO12, AF0) +#define GPIO13_GPIO MFP_CFG(GPIO13, AF0) +#define GPIO14_GPIO MFP_CFG(GPIO14, AF0) +#define GPIO15_GPIO MFP_CFG(GPIO15, AF0) +#define GPIO16_GPIO MFP_CFG(GPIO16, AF0) +#define GPIO17_GPIO MFP_CFG(GPIO17, AF0) +#define GPIO18_GPIO MFP_CFG(GPIO18, AF0) +#define GPIO19_GPIO MFP_CFG(GPIO19, AF0) +#define GPIO20_GPIO MFP_CFG(GPIO20, AF0) +#define GPIO21_GPIO MFP_CFG(GPIO21, AF0) +#define GPIO22_GPIO MFP_CFG(GPIO22, AF0) +#define GPIO23_GPIO MFP_CFG(GPIO23, AF0) +#define GPIO24_GPIO MFP_CFG(GPIO24, AF0) +#define GPIO25_GPIO MFP_CFG(GPIO25, AF0) +#define GPIO26_GPIO MFP_CFG(GPIO26, AF0) +#define GPIO27_GPIO MFP_CFG(GPIO27, AF0) +#define GPIO28_GPIO MFP_CFG(GPIO28, AF0) +#define GPIO29_GPIO MFP_CFG(GPIO29, AF0) +#define GPIO30_GPIO MFP_CFG(GPIO30, AF0) +#define GPIO31_GPIO MFP_CFG(GPIO31, AF0) +#define GPIO32_GPIO MFP_CFG(GPIO32, AF0) +#define GPIO33_GPIO MFP_CFG(GPIO33, AF0) +#define GPIO34_GPIO MFP_CFG(GPIO34, AF0) +#define GPIO35_GPIO MFP_CFG(GPIO35, AF0) +#define GPIO36_GPIO MFP_CFG(GPIO36, AF0) +#define GPIO37_GPIO MFP_CFG(GPIO37, AF0) +#define GPIO38_GPIO MFP_CFG(GPIO38, AF0) +#define GPIO39_GPIO MFP_CFG(GPIO39, AF0) +#define GPIO40_GPIO MFP_CFG(GPIO40, AF0) +#define GPIO41_GPIO MFP_CFG(GPIO41, AF0) +#define GPIO42_GPIO MFP_CFG(GPIO42, AF0) +#define GPIO43_GPIO MFP_CFG(GPIO43, AF0) +#define GPIO44_GPIO MFP_CFG(GPIO44, AF0) +#define GPIO45_GPIO MFP_CFG(GPIO45, AF0) +#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) +#define GPIO47_GPIO MFP_CFG(GPIO47, AF0) +#define GPIO48_GPIO MFP_CFG(GPIO48, AF0) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) +#define GPIO53_GPIO MFP_CFG(GPIO53, AF0) +#define GPIO54_GPIO MFP_CFG(GPIO54, AF0) +#define GPIO55_GPIO MFP_CFG(GPIO55, AF0) +#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) +#define GPIO57_GPIO MFP_CFG(GPIO57, AF0) +#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) +#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) +#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) +#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) +#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) +#define GPIO63_GPIO MFP_CFG(GPIO63, AF0) +#define GPIO64_GPIO MFP_CFG(GPIO64, AF0) +#define GPIO65_GPIO MFP_CFG(GPIO65, AF0) +#define GPIO66_GPIO MFP_CFG(GPIO66, AF0) +#define GPIO67_GPIO MFP_CFG(GPIO67, AF0) +#define GPIO68_GPIO MFP_CFG(GPIO68, AF0) +#define GPIO69_GPIO MFP_CFG(GPIO69, AF0) +#define GPIO70_GPIO MFP_CFG(GPIO70, AF0) +#define GPIO71_GPIO MFP_CFG(GPIO71, AF0) +#define GPIO72_GPIO MFP_CFG(GPIO72, AF0) +#define GPIO73_GPIO MFP_CFG(GPIO73, AF0) +#define GPIO74_GPIO MFP_CFG(GPIO74, AF0) +#define GPIO75_GPIO MFP_CFG(GPIO75, AF0) +#define GPIO76_GPIO MFP_CFG(GPIO76, AF0) +#define GPIO77_GPIO MFP_CFG(GPIO77, AF0) +#define GPIO78_GPIO MFP_CFG(GPIO78, AF0) +#define GPIO79_GPIO MFP_CFG(GPIO79, AF0) +#define GPIO80_GPIO MFP_CFG(GPIO80, AF0) +#define GPIO81_GPIO MFP_CFG(GPIO81, AF0) +#define GPIO82_GPIO MFP_CFG(GPIO82, AF0) +#define GPIO83_GPIO MFP_CFG(GPIO83, AF0) +#define GPIO84_GPIO MFP_CFG(GPIO84, AF0) +#define GPIO85_GPIO MFP_CFG(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG(GPIO86, AF0) +#define GPIO87_GPIO MFP_CFG(GPIO87, AF0) +#define GPIO88_GPIO MFP_CFG(GPIO88, AF0) +#define GPIO89_GPIO MFP_CFG(GPIO89, AF0) +#define GPIO90_GPIO MFP_CFG(GPIO90, AF0) +#define GPIO91_GPIO MFP_CFG(GPIO91, AF0) +#define GPIO92_GPIO MFP_CFG(GPIO92, AF0) +#define GPIO93_GPIO MFP_CFG(GPIO93, AF0) +#define GPIO94_GPIO MFP_CFG(GPIO94, AF0) +#define GPIO95_GPIO MFP_CFG(GPIO95, AF0) +#define GPIO96_GPIO MFP_CFG(GPIO96, AF0) +#define GPIO97_GPIO MFP_CFG(GPIO97, AF0) +#define GPIO98_GPIO MFP_CFG(GPIO98, AF0) +#define GPIO99_GPIO MFP_CFG(GPIO99, AF0) +#define GPIO100_GPIO MFP_CFG(GPIO100, AF0) +#define GPIO101_GPIO MFP_CFG(GPIO101, AF0) +#define GPIO102_GPIO MFP_CFG(GPIO102, AF1) +#define GPIO103_GPIO MFP_CFG(GPIO103, AF1) +#define GPIO104_GPIO MFP_CFG(GPIO104, AF1) +#define GPIO105_GPIO MFP_CFG(GPIO105, AF1) +#define GPIO106_GPIO MFP_CFG(GPIO106, AF1) +#define GPIO107_GPIO MFP_CFG(GPIO107, AF1) +#define GPIO108_GPIO MFP_CFG(GPIO108, AF1) +#define GPIO109_GPIO MFP_CFG(GPIO109, AF1) +#define GPIO110_GPIO MFP_CFG(GPIO110, AF1) +#define GPIO111_GPIO MFP_CFG(GPIO111, AF1) +#define GPIO112_GPIO MFP_CFG(GPIO112, AF1) +#define GPIO113_GPIO MFP_CFG(GPIO113, AF1) +#define GPIO114_GPIO MFP_CFG(GPIO114, AF0) +#define GPIO115_GPIO MFP_CFG(GPIO115, AF0) +#define GPIO116_GPIO MFP_CFG(GPIO116, AF0) +#define GPIO117_GPIO MFP_CFG(GPIO117, AF0) +#define GPIO118_GPIO MFP_CFG(GPIO118, AF0) +#define GPIO119_GPIO MFP_CFG(GPIO119, AF0) +#define GPIO120_GPIO MFP_CFG(GPIO120, AF0) +#define GPIO121_GPIO MFP_CFG(GPIO121, AF0) +#define GPIO122_GPIO MFP_CFG(GPIO122, AF0) +#define GPIO123_GPIO MFP_CFG(GPIO123, AF0) +#define GPIO124_GPIO MFP_CFG(GPIO124, AF0) +#define GPIO125_GPIO MFP_CFG(GPIO125, AF0) +#define GPIO126_GPIO MFP_CFG(GPIO126, AF0) +#define GPIO127_GPIO MFP_CFG(GPIO127, AF0) +#define GPIO128_GPIO MFP_CFG(GPIO128, AF0) +#define GPIO129_GPIO MFP_CFG(GPIO129, AF0) +#define GPIO130_GPIO MFP_CFG(GPIO130, AF0) +#define GPIO131_GPIO MFP_CFG(GPIO131, AF0) +#define GPIO132_GPIO MFP_CFG(GPIO132, AF0) +#define GPIO133_GPIO MFP_CFG(GPIO133, AF0) +#define GPIO134_GPIO MFP_CFG(GPIO134, AF0) +#define GPIO135_GPIO MFP_CFG(GPIO135, AF0) +#define GPIO136_GPIO MFP_CFG(GPIO136, AF0) +#define GPIO137_GPIO MFP_CFG(GPIO137, AF0) +#define GPIO138_GPIO MFP_CFG(GPIO138, AF0) +#define GPIO139_GPIO MFP_CFG(GPIO139, AF0) +#define GPIO140_GPIO MFP_CFG(GPIO140, AF0) +#define GPIO141_GPIO MFP_CFG(GPIO141, AF0) +#define GPIO142_GPIO MFP_CFG(GPIO142, AF1) +#define GPIO143_GPIO MFP_CFG(GPIO143, AF1) +#define GPIO144_GPIO MFP_CFG(GPIO144, AF1) +#define GPIO145_GPIO MFP_CFG(GPIO145, AF1) +#define GPIO146_GPIO MFP_CFG(GPIO146, AF1) +#define GPIO147_GPIO MFP_CFG(GPIO147, AF1) +#define GPIO148_GPIO MFP_CFG(GPIO148, AF1) +#define GPIO149_GPIO MFP_CFG(GPIO149, AF1) +#define GPIO150_GPIO MFP_CFG(GPIO150, AF1) +#define GPIO151_GPIO MFP_CFG(GPIO151, AF1) +#define GPIO152_GPIO MFP_CFG(GPIO152, AF1) +#define GPIO153_GPIO MFP_CFG(GPIO153, AF1) +#define GPIO154_GPIO MFP_CFG(GPIO154, AF1) +#define GPIO155_GPIO MFP_CFG(GPIO155, AF1) +#define GPIO156_GPIO MFP_CFG(GPIO156, AF1) +#define GPIO157_GPIO MFP_CFG(GPIO157, AF1) +#define GPIO158_GPIO MFP_CFG(GPIO158, AF1) +#define GPIO159_GPIO MFP_CFG(GPIO159, AF1) +#define GPIO160_GPIO MFP_CFG(GPIO160, AF1) +#define GPIO161_GPIO MFP_CFG(GPIO161, AF1) +#define GPIO162_GPIO MFP_CFG(GPIO162, AF1) +#define GPIO163_GPIO MFP_CFG(GPIO163, AF1) +#define GPIO164_GPIO MFP_CFG(GPIO164, AF1) +#define GPIO165_GPIO MFP_CFG(GPIO165, AF1) +#define GPIO166_GPIO MFP_CFG(GPIO166, AF1) +#define GPIO167_GPIO MFP_CFG(GPIO167, AF1) +#define GPIO168_GPIO MFP_CFG(GPIO168, AF1) /* DFI */ #define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0) diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h index dbba6e8..4aec493 100644 --- a/arch/arm/mach-mmp/include/mach/mmp2.h +++ b/arch/arm/mach-mmp/include/mach/mmp2.h @@ -1,6 +1,8 @@ #ifndef __ASM_MACH_MMP2_H #define __ASM_MACH_MMP2_H +#include <plat/sdhci.h> + struct sys_timer; extern struct sys_timer mmp2_timer; @@ -22,6 +24,10 @@ extern struct pxa_device_desc mmp2_device_twsi3; extern struct pxa_device_desc mmp2_device_twsi4; extern struct pxa_device_desc mmp2_device_twsi5; extern struct pxa_device_desc mmp2_device_twsi6; +extern struct pxa_device_desc mmp2_device_sdh0; +extern struct pxa_device_desc mmp2_device_sdh1; +extern struct pxa_device_desc mmp2_device_sdh2; +extern struct pxa_device_desc mmp2_device_sdh3; static inline int mmp2_add_uart(int id) { @@ -63,5 +69,21 @@ static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data, return pxa_register_device(d, data, sizeof(*data)); } +static inline int mmp2_add_sdhost(int id, struct sdhci_pxa_platdata *data) +{ + struct pxa_device_desc *d = NULL; + + switch (id) { + case 0: d = &mmp2_device_sdh0; break; + case 1: d = &mmp2_device_sdh1; break; + case 2: d = &mmp2_device_sdh2; break; + case 3: d = &mmp2_device_sdh3; break; + default: + return -EINVAL; + } + + return pxa_register_device(d, data, sizeof(*data)); +} + #endif /* __ASM_MACH_MMP2_H */ diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h index ac47023..f7011ef 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apmu.h +++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h @@ -27,6 +27,8 @@ #define APMU_DMA APMU_REG(0x064) #define APMU_GEU APMU_REG(0x068) #define APMU_BUS APMU_REG(0x06c) +#define APMU_SDH2 APMU_REG(0x0e8) +#define APMU_SDH3 APMU_REG(0x0ec) #define APMU_FNCLK_EN (1 << 4) #define APMU_AXICLK_EN (1 << 3) diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c index 2a684fa..24172a0 100644 --- a/arch/arm/mach-mmp/jasper.c +++ b/arch/arm/mach-mmp/jasper.c @@ -67,6 +67,36 @@ static unsigned long jasper_pin_config[] __initdata = { /* PMIC */ PMIC_PMIC_INT | MFP_LPM_EDGE_FALL, + + /* MMC1 */ + GPIO131_MMC1_DAT3, + GPIO132_MMC1_DAT2, + GPIO133_MMC1_DAT1, + GPIO134_MMC1_DAT0, + GPIO136_MMC1_CMD, + GPIO139_MMC1_CLK, + GPIO140_MMC1_CD, + GPIO141_MMC1_WP, + + /* MMC2 */ + GPIO37_MMC2_DAT3, + GPIO38_MMC2_DAT2, + GPIO39_MMC2_DAT1, + GPIO40_MMC2_DAT0, + GPIO41_MMC2_CMD, + GPIO42_MMC2_CLK, + + /* MMC3 */ + GPIO165_MMC3_DAT7, + GPIO162_MMC3_DAT6, + GPIO166_MMC3_DAT5, + GPIO163_MMC3_DAT4, + GPIO167_MMC3_DAT3, + GPIO164_MMC3_DAT2, + GPIO168_MMC3_DAT1, + GPIO111_MMC3_DAT0, + GPIO112_MMC3_CMD, + GPIO151_MMC3_CLK, }; static struct regulator_consumer_supply max8649_supply[] = { @@ -123,6 +153,10 @@ static struct i2c_board_info jasper_twsi1_info[] = { }, }; +static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = { + .max_speed = 25000000, +}; + static void __init jasper_init(void) { mfp_config(ARRAY_AND_SIZE(jasper_pin_config)); @@ -131,6 +165,7 @@ static void __init jasper_init(void) mmp2_add_uart(1); mmp2_add_uart(3); mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info)); + mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */ regulator_has_full_constraints(); } diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index 2e3dd08..8e6c3ac 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c @@ -115,6 +115,29 @@ void __init mmp2_init_irq(void) mmp2_init_gpio(); } +static void sdhc_clk_enable(struct clk *clk) +{ + uint32_t clk_rst; + + clk_rst = __raw_readl(clk->clk_rst); + clk_rst |= clk->enable_val; + __raw_writel(clk_rst, clk->clk_rst); +} + +static void sdhc_clk_disable(struct clk *clk) +{ + uint32_t clk_rst; + + clk_rst = __raw_readl(clk->clk_rst); + clk_rst &= ~clk->enable_val; + __raw_writel(clk_rst, clk->clk_rst); +} + +struct clkops sdhc_clk_ops = { + .enable = sdhc_clk_enable, + .disable = sdhc_clk_disable, +}; + /* APB peripheral clocks */ static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); @@ -128,6 +151,10 @@ static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); static APMU_CLK(nand, NAND, 0xbf, 100000000); +static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); +static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops); +static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops); +static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops); static struct clk_lookup mmp2_clkregs[] = { INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), @@ -141,6 +168,10 @@ static struct clk_lookup mmp2_clkregs[] = { INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_sdh0, "sdhci-pxa.0", "PXA-SDHCLK"), + INIT_CLKREG(&clk_sdh1, "sdhci-pxa.1", "PXA-SDHCLK"), + INIT_CLKREG(&clk_sdh2, "sdhci-pxa.2", "PXA-SDHCLK"), + INIT_CLKREG(&clk_sdh3, "sdhci-pxa.3", "PXA-SDHCLK"), }; static int __init mmp2_init(void) @@ -191,4 +222,8 @@ MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70); MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); +MMP2_DEVICE(sdh0, "sdhci-pxa", 0, MMC, 0xd4280000, 0x120); +MMP2_DEVICE(sdh1, "sdhci-pxa", 1, MMC2, 0xd4280800, 0x120); +MMP2_DEVICE(sdh2, "sdhci-pxa", 2, MMC3, 0xd4281000, 0x120); +MMP2_DEVICE(sdh3, "sdhci-pxa", 3, MMC4, 0xd4281800, 0x120); diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index 46f2d69..8f92ccd 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c @@ -111,6 +111,7 @@ static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); static APMU_CLK(nand, NAND, 0x01db, 208000000); +static APMU_CLK(u2o, USB, 0x1b, 480000000); /* device and clock bindings */ static struct clk_lookup pxa910_clkregs[] = { @@ -123,6 +124,7 @@ static struct clk_lookup pxa910_clkregs[] = { INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"), }; static int __init pxa910_init(void) diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index 788bdac..3eff399 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -65,7 +65,7 @@ */ #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) #define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) -#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700) +#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570) #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig deleted file mode 100644 index 38ca09a..0000000 --- a/arch/arm/mach-mx25/Kconfig +++ /dev/null @@ -1,34 +0,0 @@ -if ARCH_MX25 - -comment "MX25 platforms:" - -config MACH_MX25_3DS - bool "Support MX25PDK (3DS) Platform" - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_ESDHC - -config MACH_EUKREA_CPUIMX25 - bool "Support Eukrea CPUIMX25 Platform" - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_ESDHC - select MXC_ULPI if USB_ULPI - -choice - prompt "Baseboard" - depends on MACH_EUKREA_CPUIMX25 - default MACH_EUKREA_MBIMXSD25_BASEBOARD - -config MACH_EUKREA_MBIMXSD25_BASEBOARD - bool "Eukrea MBIMXSD development board" - select IMX_HAVE_PLATFORM_IMX_SSI - help - This adds board specific devices that can be found on Eukrea's - MBIMXSD evaluation board. - -endchoice - -endif diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile deleted file mode 100644 index d9e46ce..0000000 --- a/arch/arm/mach-mx25/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -obj-y := mm.o devices.o -obj-$(CONFIG_ARCH_MX25) += clock.o -obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o -obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-cpuimx25.o -obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd-baseboard.o diff --git a/arch/arm/mach-mx25/Makefile.boot b/arch/arm/mach-mx25/Makefile.boot deleted file mode 100644 index e1dd366..0000000 --- a/arch/arm/mach-mx25/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x80008000 -params_phys-y := 0x80000100 -initrd_phys-y := 0x80800000 diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c deleted file mode 100644 index 1d0eb3e..0000000 --- a/arch/arm/mach-mx25/devices.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/gpio.h> -#include <mach/mx25.h> -#include <mach/irqs.h> - -static u64 otg_dmamask = DMA_BIT_MASK(32); - -static struct resource mxc_otg_resources[] = { - { - .start = MX25_OTG_BASE_ADDR, - .end = MX25_OTG_BASE_ADDR + 0x1ff, - .flags = IORESOURCE_MEM, - }, { - .start = 37, - .end = 37, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_otg = { - .name = "mxc-ehci", - .id = 0, - .dev = { - .coherent_dma_mask = 0xffffffff, - .dma_mask = &otg_dmamask, - }, - .resource = mxc_otg_resources, - .num_resources = ARRAY_SIZE(mxc_otg_resources), -}; - -/* OTG gadget device */ -struct platform_device otg_udc_device = { - .name = "fsl-usb2-udc", - .id = -1, - .dev = { - .dma_mask = &otg_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .resource = mxc_otg_resources, - .num_resources = ARRAY_SIZE(mxc_otg_resources), -}; - -static u64 usbh2_dmamask = DMA_BIT_MASK(32); - -static struct resource mxc_usbh2_resources[] = { - { - .start = MX25_OTG_BASE_ADDR + 0x400, - .end = MX25_OTG_BASE_ADDR + 0x5ff, - .flags = IORESOURCE_MEM, - }, { - .start = 35, - .end = 35, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_usbh2 = { - .name = "mxc-ehci", - .id = 1, - .dev = { - .coherent_dma_mask = 0xffffffff, - .dma_mask = &usbh2_dmamask, - }, - .resource = mxc_usbh2_resources, - .num_resources = ARRAY_SIZE(mxc_usbh2_resources), -}; - -static struct resource mxc_pwm_resources0[] = { - { - .start = 0x53fe0000, - .end = 0x53fe3fff, - .flags = IORESOURCE_MEM, - }, { - .start = 26, - .end = 26, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_pwm_device0 = { - .name = "mxc_pwm", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_pwm_resources0), - .resource = mxc_pwm_resources0, -}; - -static struct resource mxc_pwm_resources1[] = { - { - .start = 0x53fa0000, - .end = 0x53fa3fff, - .flags = IORESOURCE_MEM, - }, { - .start = 36, - .end = 36, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_pwm_device1 = { - .name = "mxc_pwm", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_pwm_resources1), - .resource = mxc_pwm_resources1, -}; - -static struct resource mxc_pwm_resources2[] = { - { - .start = 0x53fa8000, - .end = 0x53fabfff, - .flags = IORESOURCE_MEM, - }, { - .start = 41, - .end = 41, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_pwm_device2 = { - .name = "mxc_pwm", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_pwm_resources2), - .resource = mxc_pwm_resources2, -}; - -static struct resource mxc_keypad_resources[] = { - { - .start = 0x43fa8000, - .end = 0x43fabfff, - .flags = IORESOURCE_MEM, - }, { - .start = 24, - .end = 24, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_keypad_device = { - .name = "mxc-keypad", - .id = -1, - .num_resources = ARRAY_SIZE(mxc_keypad_resources), - .resource = mxc_keypad_resources, -}; - -static struct resource mxc_pwm_resources3[] = { - { - .start = 0x53fc8000, - .end = 0x53fcbfff, - .flags = IORESOURCE_MEM, - }, { - .start = 42, - .end = 42, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_pwm_device3 = { - .name = "mxc_pwm", - .id = 3, - .num_resources = ARRAY_SIZE(mxc_pwm_resources3), - .resource = mxc_pwm_resources3, -}; - -static struct mxc_gpio_port imx_gpio_ports[] = { - { - .chip.label = "gpio-0", - .base = (void __iomem *)MX25_GPIO1_BASE_ADDR_VIRT, - .irq = 52, - .virtual_irq_start = MXC_GPIO_IRQ_START, - }, { - .chip.label = "gpio-1", - .base = (void __iomem *)MX25_GPIO2_BASE_ADDR_VIRT, - .irq = 51, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, { - .chip.label = "gpio-2", - .base = (void __iomem *)MX25_GPIO3_BASE_ADDR_VIRT, - .irq = 16, - .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - }, { - .chip.label = "gpio-3", - .base = (void __iomem *)MX25_GPIO4_BASE_ADDR_VIRT, - .irq = 23, - .virtual_irq_start = MXC_GPIO_IRQ_START + 96, - } -}; - -int __init imx25_register_gpios(void) -{ - return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); -} - -static struct resource mx25_rtc_resources[] = { - { - .start = MX25_DRYICE_BASE_ADDR, - .end = MX25_DRYICE_BASE_ADDR + 0x40, - .flags = IORESOURCE_MEM, - }, - { - .start = MX25_INT_DRYICE, - .flags = IORESOURCE_IRQ - }, -}; - -struct platform_device mx25_rtc_device = { - .name = "imxdi_rtc", - .id = 0, - .num_resources = ARRAY_SIZE(mx25_rtc_resources), - .resource = mx25_rtc_resources, -}; - -static struct resource mx25_fb_resources[] = { - { - .start = MX25_LCDC_BASE_ADDR, - .end = MX25_LCDC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - { - .start = MX25_INT_LCDC, - .end = MX25_INT_LCDC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mx25_fb_device = { - .name = "imx-fb", - .id = 0, - .resource = mx25_fb_resources, - .num_resources = ARRAY_SIZE(mx25_fb_resources), - .dev = { - .coherent_dma_mask = 0xFFFFFFFF, - }, -}; - -static struct resource mxc_wdt_resources[] = { - { - .start = MX25_WDOG_BASE_ADDR, - .end = MX25_WDOG_BASE_ADDR + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_wdt = { - .name = "imx2-wdt", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_wdt_resources), - .resource = mxc_wdt_resources, -}; - -static struct resource mx25_kpp_resources[] = { - { - .start = MX25_KPP_BASE_ADDR, - .end = MX25_KPP_BASE_ADDR + 0xf, - .flags = IORESOURCE_MEM, - }, - { - .start = MX25_INT_KPP, - .end = MX25_INT_KPP, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mx25_kpp_device = { - .name = "imx-keypad", - .id = -1, - .num_resources = ARRAY_SIZE(mx25_kpp_resources), - .resource = mx25_kpp_resources, -}; - -static struct resource mx25_csi_resources[] = { - { - .start = MX25_CSI_BASE_ADDR, - .end = MX25_CSI_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - { - .start = MX25_INT_CSI, - .flags = IORESOURCE_IRQ - }, -}; - -struct platform_device mx25_csi_device = { - .name = "mx2-camera", - .id = 0, - .num_resources = ARRAY_SIZE(mx25_csi_resources), - .resource = mx25_csi_resources, - .dev = { - .coherent_dma_mask = 0xffffffff, - }, -}; diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h deleted file mode 100644 index 7b70a43..0000000 --- a/arch/arm/mach-mx25/devices.h +++ /dev/null @@ -1,13 +0,0 @@ -extern struct platform_device mxc_otg; -extern struct platform_device otg_udc_device; -extern struct platform_device mxc_usbh2; -extern struct platform_device mxc_pwm_device0; -extern struct platform_device mxc_pwm_device1; -extern struct platform_device mxc_pwm_device2; -extern struct platform_device mxc_pwm_device3; -extern struct platform_device mxc_keypad_device; -extern struct platform_device mx25_rtc_device; -extern struct platform_device mx25_fb_device; -extern struct platform_device mxc_wdt; -extern struct platform_device mx25_kpp_device; -extern struct platform_device mx25_csi_device; diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 5000ac1..0717f88 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -1,21 +1,35 @@ if ARCH_MX3 +# ARCH_MX31 and ARCH_MX35 are left for compatibility +# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2. +# To easily distinguish good and reviewed from unreviewed usages new (and IMHO +# more sensible) names are used: SOC_IMX31 and SOC_IMX35 config ARCH_MX31 - select ARCH_HAS_RNGA - select ARCH_MXC_AUDMUX_V2 bool config ARCH_MX35 bool + +config SOC_IMX31 + bool + select IMX_HAVE_PLATFORM_MXC_RNGA + select ARCH_MXC_AUDMUX_V2 + select ARCH_MX31 + select MXC_AVIC + +config SOC_IMX35 + bool select ARCH_MXC_IOMUX_V3 select ARCH_MXC_AUDMUX_V2 select HAVE_EPIT + select ARCH_MX35 + select MXC_AVIC comment "MX3 platforms:" config MACH_MX31ADS bool "Support MX31ADS platforms" - select ARCH_MX31 + select SOC_IMX31 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART @@ -37,10 +51,15 @@ config MACH_MX31ADS_WM1133_EV1 config MACH_PCM037 bool "Support Phytec pcm037 (i.MX31) platforms" - select ARCH_MX31 + select SOC_IMX31 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND + select IMX_HAVE_PLATFORM_MXC_W1 select MXC_ULPI if USB_ULPI help Include support for Phytec pcm037 platform. This includes @@ -57,9 +76,12 @@ config MACH_PCM037_EET config MACH_MX31LITE bool "Support MX31 LITEKIT (LogicPD)" - select ARCH_MX31 + select SOC_IMX31 select MXC_ULPI if USB_ULPI + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SPI_IMX help @@ -68,11 +90,16 @@ config MACH_MX31LITE config MACH_MX31_3DS bool "Support MX31PDK (3DS)" - select ARCH_MX31 + select SOC_IMX31 select MXC_DEBUG_BOARD + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_KEYPAD select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SPI_IMX + select MXC_ULPI if USB_ULPI help Include support for MX31PDK (3DS) platform. This includes specific configurations for the board and its peripherals. @@ -88,9 +115,12 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT config MACH_MX31MOBOARD bool "Support mx31moboard platforms (EPFL Mobots group)" - select ARCH_MX31 + select SOC_IMX31 + select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help @@ -99,8 +129,10 @@ config MACH_MX31MOBOARD config MACH_MX31LILLY bool "Support MX31 LILLY-1131 platforms (INCO startec)" - select ARCH_MX31 + select SOC_IMX31 select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_SPI_IMX select MXC_ULPI if USB_ULPI help @@ -109,7 +141,7 @@ config MACH_MX31LILLY config MACH_QONG bool "Support Dave/DENX QongEVB-LITE platform" - select ARCH_MX31 + select SOC_IMX31 select IMX_HAVE_PLATFORM_IMX_UART help Include support for Dave/DENX QongEVB-LITE platform. This includes @@ -117,13 +149,16 @@ config MACH_QONG config MACH_PCM043 bool "Support Phytec pcm043 (i.MX35) platforms" - select ARCH_MX35 + select SOC_IMX35 + select IMX_HAVE_PLATFORM_FLEXCAN + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_ESDHC + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select MXC_ULPI if USB_ULPI help Include support for Phytec pcm043 platform. This includes @@ -131,9 +166,11 @@ config MACH_PCM043 config MACH_ARMADILLO5X0 bool "Support Atmark Armadillo-500 Development Base Board" - select ARCH_MX31 + select SOC_IMX31 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_MXC_MMC select IMX_HAVE_PLATFORM_MXC_NAND select MXC_ULPI if USB_ULPI help @@ -142,19 +179,21 @@ config MACH_ARMADILLO5X0 config MACH_MX35_3DS bool "Support MX35PDK platform" - select ARCH_MX35 + select SOC_IMX35 select MXC_DEBUG_BOARD + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_ESDHC - default n + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX help Include support for MX35PDK platform. This includes specific configurations for the board and its peripherals. config MACH_KZM_ARM11_01 bool "Support KZM-ARM11-01(Kyoto Microcomputer)" - select ARCH_MX31 + select SOC_IMX31 select IMX_HAVE_PLATFORM_IMX_UART help Include support for KZM-ARM11-01. This includes specific @@ -162,12 +201,15 @@ config MACH_KZM_ARM11_01 config MACH_EUKREA_CPUIMX35 bool "Support Eukrea CPUIMX35 Platform" - select ARCH_MX35 - select IMX_HAVE_PLATFORM_IMX_UART + select SOC_IMX35 + select IMX_HAVE_PLATFORM_FLEXCAN + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_ESDHC + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select MXC_ULPI if USB_ULPI help Include support for Eukrea CPUIMX35 platform. This includes diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 8a182d0a..8db1329 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -5,17 +5,14 @@ # Object file lists. obj-y := mm.o devices.o cpu.o -CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS -CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS -obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o -obj-$(CONFIG_ARCH_MX35) += clock-imx35.o +obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o +obj-$(CONFIG_SOC_IMX35) += clock-imx35.o obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o -CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ mx31moboard-marxbot.o mx31moboard-smartbot.o obj-$(CONFIG_MACH_QONG) += mach-qong.o diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c index 1cd8b40..d423cac 100644 --- a/arch/arm/mach-mx3/clock-imx31.c +++ b/arch/arm/mach-mx3/clock-imx31.c @@ -530,7 +530,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk) _REGISTER_CLOCK(NULL, "gpt", gpt_clk) _REGISTER_CLOCK(NULL, "pwm", pwm_clk) - _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) + _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) _REGISTER_CLOCK(NULL, "rtc", rtc_clk) _REGISTER_CLOCK(NULL, "epit", epit1_clk) _REGISTER_CLOCK(NULL, "epit", epit2_clk) @@ -615,7 +615,7 @@ int __init mx31_clocks_init(unsigned long fref) mx31_read_cpu_rev(); - if (mx31_revision() >= MX31_CHIP_REV_2_0) { + if (mx31_revision() >= IMX_CHIP_REVISION_2_0) { reg = __raw_readl(MXC_CCM_PMCR1); /* No PLL restart on DVFS switch; enable auto EMI handshake */ reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 819dd80..448a038 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -494,7 +494,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk) - _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) + _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) _REGISTER_CLOCK(NULL, "max", max_clk) _REGISTER_CLOCK(NULL, "audmux", audmux_clk) _REGISTER_CLOCK(NULL, "csi", csi_clk) diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c index d00a754..d1d3395 100644 --- a/arch/arm/mach-mx3/cpu.c +++ b/arch/arm/mach-mx3/cpu.c @@ -25,15 +25,15 @@ struct mx3_cpu_type { }; static struct mx3_cpu_type mx31_cpu_type[] __initdata = { - { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = MX3x_CHIP_REV_1_0 }, - { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 }, - { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 }, - { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 }, - { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 }, - { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 }, - { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 }, - { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 }, - { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 }, + { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 }, + { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, + { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, + { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 }, + { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 }, + { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 }, + { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 }, + { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 }, + { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 }, }; void __init mx31_read_cpu_rev(void) @@ -53,6 +53,8 @@ void __init mx31_read_cpu_rev(void) return; } + mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN; + printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); } @@ -62,22 +64,25 @@ EXPORT_SYMBOL(mx35_cpu_rev); void __init mx35_read_cpu_rev(void) { u32 rev; - char *srev = "unknown"; + char *srev; rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); switch (rev) { case 0x00: - mx35_cpu_rev = MX3x_CHIP_REV_1_0; + mx35_cpu_rev = IMX_CHIP_REVISION_1_0; srev = "1.0"; break; case 0x10: - mx35_cpu_rev = MX3x_CHIP_REV_2_0; + mx35_cpu_rev = IMX_CHIP_REVISION_2_0; srev = "2.0"; break; case 0x11: - mx35_cpu_rev = MX3x_CHIP_REV_2_1; + mx35_cpu_rev = IMX_CHIP_REVISION_2_1; srev = "2.1"; break; + default: + mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN; + srev = "unknown"; } printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev); diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h index de95985..40f4e84 100644 --- a/arch/arm/mach-mx3/devices-imx31.h +++ b/arch/arm/mach-mx3/devices-imx31.h @@ -9,6 +9,14 @@ #include <mach/mx31.h> #include <mach/devices-common.h> +extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst; +#define imx31_add_fsl_usb2_udc(pdata) \ + imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata) + +extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst; +#define imx31_add_imx2_wdt(pdata) \ + imx_add_imx2_wdt(&imx31_imx2_wdt_data) + extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst; #define imx31_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata) @@ -16,6 +24,10 @@ extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst; #define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata) #define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata) +extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst; +#define imx31_add_imx_keypad(pdata) \ + imx_add_imx_keypad(&imx31_imx_keypad_data, pdata) + extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst; #define imx31_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata) @@ -29,10 +41,25 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst; #define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) #define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) +extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst; +#define imx31_add_mxc_ehci_otg(pdata) \ + imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata) +extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst; +#define imx31_add_mxc_ehci_hs(id, pdata) \ + imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata) + +extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst; +#define imx31_add_mxc_mmc(id, pdata) \ + imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata) + extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst; #define imx31_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) +extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst; +#define imx31_add_mxc_w1(pdata) \ + imx_add_mxc_w1(&imx31_mxc_w1_data) + extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst; #define imx31_add_cspi(id, pdata) \ imx_add_spi_imx(&imx31_cspi_data[id], pdata) diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h index 5eb917b..677b18a 100644 --- a/arch/arm/mach-mx3/devices-imx35.h +++ b/arch/arm/mach-mx3/devices-imx35.h @@ -13,10 +13,19 @@ extern const struct imx_fec_data imx35_fec_data __initconst; #define imx35_add_fec(pdata) \ imx_add_fec(&imx35_fec_data, pdata) -#define imx35_add_flexcan0(pdata) \ - imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata) -#define imx35_add_flexcan1(pdata) \ - imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata) +extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst; +#define imx35_add_fsl_usb2_udc(pdata) \ + imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata) + +extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst; +#define imx35_add_flexcan(id, pdata) \ + imx_add_flexcan(&imx35_flexcan_data[id], pdata) +#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata) +#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata) + +extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst; +#define imx35_add_imx2_wdt(pdata) \ + imx_add_imx2_wdt(&imx35_imx2_wdt_data) extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst; #define imx35_add_imx_i2c(id, pdata) \ @@ -25,6 +34,10 @@ extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst; #define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata) #define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) +extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst; +#define imx31_add_imx_keypad(pdata) \ + imx_add_imx_keypad(&imx35_imx_keypad_data, pdata) + extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst; #define imx35_add_imx_ssi(id, pdata) \ imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata) @@ -36,16 +49,28 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst; #define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) #define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) +extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst; +#define imx35_add_mxc_ehci_otg(pdata) \ + imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata) +extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst; +#define imx35_add_mxc_ehci_hs(pdata) \ + imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata) + extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst; #define imx35_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) +extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst; +#define imx35_add_mxc_w1(pdata) \ + imx_add_mxc_w1(&imx35_mxc_w1_data) + +extern const struct imx_sdhci_esdhc_imx_data +imx35_sdhci_esdhc_imx_data[] __initconst; +#define imx35_add_sdhci_esdhc_imx(id, pdata) \ + imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata) + extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst; #define imx35_add_cspi(id, pdata) \ imx_add_spi_imx(&imx35_cspi_data[id], pdata) #define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) #define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) - -extern const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst; -#define imx35_add_esdhc(id, pdata) \ - imx_add_esdhc(&imx35_esdhc_data[id], pdata) diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index d4da949..b6672db 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -29,120 +29,25 @@ #include "devices.h" -/* GPIO port description */ -static struct mxc_gpio_port imx_gpio_ports[] = { - { - .chip.label = "gpio-0", - .base = IO_ADDRESS(GPIO1_BASE_ADDR), - .irq = MXC_INT_GPIO1, - .virtual_irq_start = MXC_GPIO_IRQ_START, - }, { - .chip.label = "gpio-1", - .base = IO_ADDRESS(GPIO2_BASE_ADDR), - .irq = MXC_INT_GPIO2, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, { - .chip.label = "gpio-2", - .base = IO_ADDRESS(GPIO3_BASE_ADDR), - .irq = MXC_INT_GPIO3, - .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - } -}; - -int __init imx3x_register_gpios(void) -{ - return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); -} - -static struct resource mxc_w1_master_resources[] = { - { - .start = OWIRE_BASE_ADDR, - .end = OWIRE_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_w1_master_device = { - .name = "mxc_w1", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_w1_master_resources), - .resource = mxc_w1_master_resources, -}; - -#ifdef CONFIG_ARCH_MX31 -static struct resource mxcsdhc0_resources[] = { - { - .start = MX31_MMC_SDHC1_BASE_ADDR, - .end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX31_INT_MMC_SDHC1, - .end = MX31_INT_MMC_SDHC1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource mxcsdhc1_resources[] = { - { - .start = MX31_MMC_SDHC2_BASE_ADDR, - .end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX31_INT_MMC_SDHC2, - .end = MX31_INT_MMC_SDHC2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxcsdhc_device0 = { - .name = "mxc-mmc", - .id = 0, - .num_resources = ARRAY_SIZE(mxcsdhc0_resources), - .resource = mxcsdhc0_resources, -}; - -struct platform_device mxcsdhc_device1 = { - .name = "mxc-mmc", - .id = 1, - .num_resources = ARRAY_SIZE(mxcsdhc1_resources), - .resource = mxcsdhc1_resources, -}; - -static struct resource rnga_resources[] = { - { - .start = RNGA_BASE_ADDR, - .end = RNGA_BASE_ADDR + 0x28, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxc_rnga_device = { - .name = "mxc_rnga", - .id = -1, - .num_resources = 1, - .resource = rnga_resources, -}; -#endif /* CONFIG_ARCH_MX31 */ - /* i.MX31 Image Processing Unit */ /* The resource order is important! */ static struct resource mx3_ipu_rsrc[] = { { - .start = IPU_CTRL_BASE_ADDR, - .end = IPU_CTRL_BASE_ADDR + 0x5F, + .start = MX3x_IPU_CTRL_BASE_ADDR, + .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F, .flags = IORESOURCE_MEM, }, { - .start = IPU_CTRL_BASE_ADDR + 0x88, - .end = IPU_CTRL_BASE_ADDR + 0xB3, + .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88, + .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_IPU_SYN, - .end = MXC_INT_IPU_SYN, + .start = MX3x_INT_IPU_SYN, + .end = MX3x_INT_IPU_SYN, .flags = IORESOURCE_IRQ, }, { - .start = MXC_INT_IPU_ERR, - .end = MXC_INT_IPU_ERR, + .start = MX3x_INT_IPU_ERR, + .end = MX3x_INT_IPU_ERR, .flags = IORESOURCE_IRQ, }, }; @@ -156,8 +61,8 @@ struct platform_device mx3_ipu = { static struct resource fb_resources[] = { { - .start = IPU_CTRL_BASE_ADDR + 0xB4, - .end = IPU_CTRL_BASE_ADDR + 0x1BF, + .start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4, + .end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF, .flags = IORESOURCE_MEM, }, }; @@ -174,8 +79,8 @@ struct platform_device mx3_fb = { static struct resource camera_resources[] = { { - .start = IPU_CTRL_BASE_ADDR + 0x60, - .end = IPU_CTRL_BASE_ADDR + 0x87, + .start = MX3x_IPU_CTRL_BASE_ADDR + 0x60, + .end = MX3x_IPU_CTRL_BASE_ADDR + 0x87, .flags = IORESOURCE_MEM, }, }; @@ -190,110 +95,6 @@ struct platform_device mx3_camera = { }, }; -static struct resource otg_resources[] = { - { - .start = MX31_OTG_BASE_ADDR, - .end = MX31_OTG_BASE_ADDR + 0x1ff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_USB3, - .end = MXC_INT_USB3, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 otg_dmamask = DMA_BIT_MASK(32); - -/* OTG gadget device */ -struct platform_device mxc_otg_udc_device = { - .name = "fsl-usb2-udc", - .id = -1, - .dev = { - .dma_mask = &otg_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), -}; - -/* OTG host */ -struct platform_device mxc_otg_host = { - .name = "mxc-ehci", - .id = 0, - .dev = { - .coherent_dma_mask = 0xffffffff, - .dma_mask = &otg_dmamask, - }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), -}; - -/* USB host 1 */ - -static u64 usbh1_dmamask = ~(u32)0; - -static struct resource mxc_usbh1_resources[] = { - { - .start = MX31_OTG_BASE_ADDR + 0x200, - .end = MX31_OTG_BASE_ADDR + 0x3ff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_USB1, - .end = MXC_INT_USB1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_usbh1 = { - .name = "mxc-ehci", - .id = 1, - .dev = { - .coherent_dma_mask = 0xffffffff, - .dma_mask = &usbh1_dmamask, - }, - .resource = mxc_usbh1_resources, - .num_resources = ARRAY_SIZE(mxc_usbh1_resources), -}; - -/* USB host 2 */ -static u64 usbh2_dmamask = ~(u32)0; - -static struct resource mxc_usbh2_resources[] = { - { - .start = MX31_OTG_BASE_ADDR + 0x400, - .end = MX31_OTG_BASE_ADDR + 0x5ff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_USB2, - .end = MXC_INT_USB2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_usbh2 = { - .name = "mxc-ehci", - .id = 2, - .dev = { - .coherent_dma_mask = 0xffffffff, - .dma_mask = &usbh2_dmamask, - }, - .resource = mxc_usbh2_resources, - .num_resources = ARRAY_SIZE(mxc_usbh2_resources), -}; - -static struct resource imx_wdt_resources[] = { - { - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device imx_wdt_device0 = { - .name = "imx2-wdt", - .id = 0, - .num_resources = ARRAY_SIZE(imx_wdt_resources), - .resource = imx_wdt_resources, -}; - static struct resource imx_rtc_resources[] = { { .start = MX31_RTC_BASE_ADDR, @@ -312,51 +113,3 @@ struct platform_device imx_rtc_device0 = { .num_resources = ARRAY_SIZE(imx_rtc_resources), .resource = imx_rtc_resources, }; - -static struct resource imx_kpp_resources[] = { - { - .start = MX3x_KPP_BASE_ADDR, - .end = MX3x_KPP_BASE_ADDR + 0xf, - .flags = IORESOURCE_MEM - }, { - .start = MX3x_INT_KPP, - .end = MX3x_INT_KPP, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_kpp_device = { - .name = "imx-keypad", - .id = -1, - .num_resources = ARRAY_SIZE(imx_kpp_resources), - .resource = imx_kpp_resources, -}; - -static int __init mx3_devices_init(void) -{ -#if defined(CONFIG_ARCH_MX31) - if (cpu_is_mx31()) { - imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR; - imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff; - mxc_register_device(&mxc_rnga_device, NULL); - } -#endif -#if defined(CONFIG_ARCH_MX35) - if (cpu_is_mx35()) { - otg_resources[0].start = MX35_OTG_BASE_ADDR; - otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; - otg_resources[1].start = MXC_INT_USBOTG; - otg_resources[1].end = MXC_INT_USBOTG; - mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400; - mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; - mxc_usbh1_resources[1].start = MXC_INT_USBHS; - mxc_usbh1_resources[1].end = MXC_INT_USBHS; - imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; - imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; - } -#endif - - return 0; -} - -subsys_initcall(mx3_devices_init); diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index 585f814..121962c 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h @@ -1,14 +1,4 @@ -extern struct platform_device mxc_w1_master_device; extern struct platform_device mx3_ipu; extern struct platform_device mx3_fb; extern struct platform_device mx3_camera; -extern struct platform_device mxcsdhc_device0; -extern struct platform_device mxcsdhc_device1; -extern struct platform_device mxc_otg_udc_device; -extern struct platform_device mxc_otg_host; -extern struct platform_device mxc_usbh1; -extern struct platform_device mxc_usbh2; -extern struct platform_device mxc_rnga_device; -extern struct platform_device imx_wdt_device0; extern struct platform_device imx_rtc_device0; -extern struct platform_device imx_kpp_device; diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c index 1abc10d..14a5ffc 100644 --- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c @@ -111,7 +111,7 @@ static struct mx3fb_platform_data mx3fb_pdata = { .num_modes = ARRAY_SIZE(fb_modedb), }; -static struct pad_desc eukrea_mbimxsd_pads[] = { +static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { /* LCD */ MX35_PAD_LD0__IPU_DISPB_DAT_0, MX35_PAD_LD1__IPU_DISPB_DAT_1, @@ -289,7 +289,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void) imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); imx35_add_flexcan1(NULL); - imx35_add_esdhc(0, NULL); + imx35_add_sdhci_esdhc_imx(0, NULL); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c index aaa30fe..28b6f41 100644 --- a/arch/arm/mach-mx3/mach-armadillo5x0.c +++ b/arch/arm/mach-mx3/mach-armadillo5x0.c @@ -49,10 +49,8 @@ #include <mach/common.h> #include <mach/iomux-mx3.h> -#include <mach/mmc.h> #include <mach/ipu.h> #include <mach/mx3fb.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx31.h" @@ -245,13 +243,13 @@ h2_free_cs: return err; } -static struct mxc_usbh_platform_data usbotg_pdata = { +static struct mxc_usbh_platform_data usbotg_pdata __initdata = { .init = usbotg_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, }; -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, @@ -453,7 +451,7 @@ static void armadillo5x0_sdhc1_exit(struct device *dev, void *data) gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B)); } -static struct imxmmc_platform_data sdhc_pdata = { +static const struct imxmmc_platform_data sdhc_pdata __initconst = { .get_ro = armadillo5x0_sdhc1_get_ro, .init = armadillo5x0_sdhc1_init, .exit = armadillo5x0_sdhc1_exit, @@ -520,7 +518,7 @@ static void __init armadillo5x0_init(void) gpio_direction_input(MX31_PIN_GPIO1_0); /* Register SDHC */ - mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); + imx31_add_mxc_mmc(0, &sdhc_pdata); /* Register FB */ mxc_register_device(&mx3_ipu, &mx3_ipu_data); @@ -555,8 +553,8 @@ static void __init armadillo5x0_init(void) usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_otg_host, &usbotg_pdata); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx31_add_mxc_ehci_otg(&usbotg_pdata); + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); #endif } diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c index 9fde873..26ae90f 100644 --- a/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/arch/arm/mach-mx3/mach-cpuimx35.c @@ -30,7 +30,6 @@ #include <linux/i2c/tsc2007.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> -#include <linux/fsl_devices.h> #include <linux/i2c-gpio.h> #include <asm/mach-types.h> @@ -43,7 +42,6 @@ #include <mach/common.h> #include <mach/iomux-mx35.h> #include <mach/mxc_nand.h> -#include <mach/mxc_ehci.h> #include "devices-imx35.h" #include "devices.h" @@ -74,11 +72,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { }, }; -static struct platform_device *devices[] __initdata = { - &imx_wdt_device0, -}; - -static struct pad_desc eukrea_cpuimx35_pads[] = { +static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = { /* UART1 */ MX35_PAD_CTS1__UART1_CTS, MX35_PAD_RTS1__UART1_RTS, @@ -117,18 +111,18 @@ static const struct mxc_nand_platform_data .flash_bbt = 1, }; -static struct mxc_usbh_platform_data __maybe_unused otg_pdata = { +static const struct mxc_usbh_platform_data otg_pdata __initconst = { .portsc = MXC_EHCI_MODE_UTMI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; -static struct mxc_usbh_platform_data __maybe_unused usbh1_pdata = { +static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { .portsc = MXC_EHCI_MODE_SERIAL, .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN, }; -static struct fsl_usb2_platform_data otg_device_pdata = { +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI, .workaround = FLS_USB2_WORKAROUND_ENGCM09152, @@ -158,7 +152,7 @@ static void __init mxc_board_init(void) ARRAY_SIZE(eukrea_cpuimx35_pads)); imx35_add_fec(NULL); - platform_add_devices(devices, ARRAY_SIZE(devices)); + imx35_add_imx2_wdt(NULL); imx35_add_imx_uart0(&uart_pdata); imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info); @@ -168,11 +162,11 @@ static void __init mxc_board_init(void) imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data); if (otg_mode_host) - mxc_register_device(&mxc_otg_host, &otg_pdata); + imx35_add_mxc_ehci_otg(&otg_pdata); else - mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + imx35_add_fsl_usb2_udc(&otg_device_pdata); - mxc_register_device(&mxc_usbh1, &usbh1_pdata); + imx35_add_mxc_ehci_hs(&usbh1_pdata); #ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD eukrea_mbimxsd35_baseboard_init(); diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c index 042cd56..a5f3eb2 100644 --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c @@ -41,9 +41,9 @@ #include "devices-imx31.h" #include "devices.h" -#define KZM_ARM11_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX31_CS4) ?: \ - IMX_IO_ADDRESS(x, MX31_CS5) ?: \ +#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \ + IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \ + IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \ MX31_IO_ADDRESS(x)) /* diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 0ad9e78..4e516b4 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -22,8 +22,8 @@ #include <linux/mfd/mc13783.h> #include <linux/spi/spi.h> #include <linux/regulator/machine.h> -#include <linux/fsl_devices.h> -#include <linux/input/matrix_keypad.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -34,6 +34,7 @@ #include <mach/common.h> #include <mach/iomux-mx3.h> #include <mach/3ds_debugboard.h> +#include <mach/ulpi.h> #include "devices-imx31.h" #include "devices.h" @@ -84,6 +85,21 @@ static int mx31_3ds_pins[] = { MX31_PIN_KEY_COL1_KEY_COL1, MX31_PIN_KEY_COL2_KEY_COL2, MX31_PIN_KEY_COL3_KEY_COL3, + /* USB Host 2 */ + IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1), + IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1), + IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1), + IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1), + IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1), + IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1), + /* USB Host2 reset */ + IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO), }; /* @@ -102,7 +118,7 @@ static const uint32_t mx31_3ds_keymap[] = { KEY(2, 3, KEY_F10), }; -static struct matrix_keymap_data mx31_3ds_keymap_data = { +static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = { .keymap = mx31_3ds_keymap, .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), }; @@ -115,6 +131,13 @@ static struct regulator_init_data pwgtx_init = { }, }; +static struct regulator_init_data gpo_init = { + .constraints = { + .boot_on = 1, + .always_on = 1, + } +}; + static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { { .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */ @@ -122,6 +145,13 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { }, { .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */ .init_data = &pwgtx_init, + }, { + + .id = MC13783_REGU_GPO1, /* Turn on 1.8V */ + .init_data = &gpo_init, + }, { + .id = MC13783_REGU_GPO3, /* Turn on 3.3V */ + .init_data = &gpo_init, }, }; @@ -129,7 +159,7 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { static struct mc13783_platform_data mc13783_pdata __initdata = { .regulators = mx31_3ds_regulators, .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), - .flags = MC13783_USE_REGULATOR, + .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN, }; /* SPI */ @@ -175,6 +205,7 @@ mx31_3ds_nand_board_info __initconst = { PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) +#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP) static int mx31_3ds_usbotg_init(void) { @@ -214,11 +245,77 @@ usbotg_free_reset: return err; } -static struct fsl_usb2_platform_data usbotg_pdata = { +static int mx31_3ds_host2_init(struct platform_device *pdev) +{ + int err; + + mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG); + + err = gpio_request(USBH2_RST_B, "usbh2-reset"); + if (err) { + pr_err("Failed to request the USB Host 2 reset gpio\n"); + return err; + } + + err = gpio_direction_output(USBH2_RST_B, 0); + if (err) { + pr_err("Failed to drive the USB Host 2 reset gpio\n"); + goto usbotg_free_reset; + } + + mdelay(1); + gpio_set_value(USBH2_RST_B, 1); + return 0; + +usbotg_free_reset: + gpio_free(USBH2_RST_B); + return err; +} + +#if defined(CONFIG_USB_ULPI) +static struct mxc_usbh_platform_data otg_pdata __initdata = { + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_POWER_PINS_ENABLED, +}; + +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { + .init = mx31_3ds_host2_init, + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_POWER_PINS_ENABLED, +}; +#endif + +static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; +static int otg_mode_host; + +static int __init mx31_3ds_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", mx31_3ds_otg_mode); + static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -246,14 +343,27 @@ static void __init mxc_board_init(void) spi_register_board_info(mx31_3ds_spi_devs, ARRAY_SIZE(mx31_3ds_spi_devs)); - mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data); + imx31_add_imx_keypad(&mx31_3ds_keymap_data); mx31_3ds_usbotg_init(); - mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata); +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + + imx31_add_mxc_ehci_otg(&otg_pdata); + } + usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); +#endif + if (!otg_mode_host) + imx31_add_fsl_usb2_udc(&usbotg_pdata); if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) printk(KERN_WARNING "Init of the debug board failed, all " "devices on the debug board are unusable.\n"); + imx31_add_imx2_wdt(NULL); } static void __init mx31_3ds_timer_init(void) diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index 42f47fa..2c59548 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -42,7 +42,6 @@ #include <mach/common.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31lilly.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx31.h" @@ -230,13 +229,13 @@ static struct mxc_usbh_platform_data usbotg_pdata = { .flags = MXC_EHCI_POWER_PINS_ENABLED, }; -static struct mxc_usbh_platform_data usbh1_pdata = { +static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { .init = usbh1_init, .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, }; -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED, @@ -249,8 +248,8 @@ static void lilly1131_usb_init(void) usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_usbh1, &usbh1_pdata); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx31_add_mxc_ehci_hs(1, &usbh1_pdata); + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); } #else diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index b938958..9e64c66 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -40,7 +40,6 @@ #include <mach/board-mx31lite.h> #include <mach/iomux-mx3.h> #include <mach/irqs.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx31.h" @@ -171,7 +170,7 @@ static int usbh2_init(struct platform_device *pdev) return 0; } -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .init = usbh2_init, .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED, @@ -258,7 +257,7 @@ static void __init mxc_board_init(void) usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); #endif /* SMSC9117 IRQ pin */ diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index eb5f426..203d21a 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -40,8 +40,6 @@ #include <mach/hardware.h> #include <mach/iomux-mx3.h> #include <mach/ipu.h> -#include <mach/mmc.h> -#include <mach/mxc_ehci.h> #include <mach/mx3_camera.h> #include <mach/spi.h> #include <mach/ulpi.h> @@ -170,11 +168,11 @@ static const struct spi_imx_master moboard_spi1_pdata __initconst = { static struct regulator_consumer_supply sdhc_consumers[] = { { - .dev = &mxcsdhc_device0.dev, + .dev_name = "mxc-mmc.0", .supply = "sdhc0_vcc", }, { - .dev = &mxcsdhc_device1.dev, + .dev_name = "mxc-mmc.1", .supply = "sdhc1_vcc", }, }; @@ -345,7 +343,7 @@ static void moboard_sdhc1_exit(struct device *dev, void *data) gpio_free(SDHC1_CD); } -static struct imxmmc_platform_data sdhc1_pdata = { +static const struct imxmmc_platform_data sdhc1_pdata __initconst = { .get_ro = moboard_sdhc1_get_ro, .init = moboard_sdhc1_init, .exit = moboard_sdhc1_exit, @@ -404,17 +402,23 @@ static void usb_xcvr_reset(void) #if defined(CONFIG_USB_ULPI) -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED, }; static int __init moboard_usbh2_init(void) { + struct platform_device *pdev; + usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - return mxc_register_device(&mxc_usbh2, &usbh2_pdata); + pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + return 0; } #else static inline int moboard_usbh2_init(void) { return 0; } @@ -520,7 +524,7 @@ static void __init mxc_board_init(void) spi_register_board_info(moboard_spi_board_info, ARRAY_SIZE(moboard_spi_board_info)); - mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata); + imx31_add_mxc_mmc(0, &sdhc1_pdata); mxc_register_device(&mx3_ipu, &mx3_ipu_data); if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE)) diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index b66a75a..b1963f2 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -26,7 +26,7 @@ #include <linux/platform_device.h> #include <linux/memory.h> #include <linux/gpio.h> -#include <linux/fsl_devices.h> +#include <linux/usb/otg.h> #include <linux/mtd/physmap.h> @@ -40,7 +40,6 @@ #include <mach/iomux-mx35.h> #include <mach/irqs.h> #include <mach/3ds_debugboard.h> -#include <mach/mxc_ehci.h> #include "devices-imx35.h" #include "devices.h" @@ -81,7 +80,7 @@ static struct platform_device *devices[] __initdata = { &mx35pdk_flash, }; -static struct pad_desc mx35pdk_pads[] = { +static iomux_v3_cfg_t mx35pdk_pads[] = { /* UART1 */ MX35_PAD_CTS1__UART1_CTS, MX35_PAD_RTS1__UART1_RTS, @@ -122,18 +121,38 @@ static struct pad_desc mx35pdk_pads[] = { }; /* OTG config */ -static struct fsl_usb2_platform_data usb_otg_pdata = { +static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI_WIDE, }; +static struct mxc_usbh_platform_data otg_pdata __initdata = { + .portsc = MXC_EHCI_MODE_UTMI, + .flags = MXC_EHCI_INTERNAL_PHY, +}; + /* USB HOST config */ -static struct mxc_usbh_platform_data usb_host_pdata = { +static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { .portsc = MXC_EHCI_MODE_SERIAL, .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY, }; +static int otg_mode_host; + +static int __init mx35_3ds_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", mx35_3ds_otg_mode); + /* * Board specific initialization. */ @@ -142,16 +161,21 @@ static void __init mxc_board_init(void) mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); imx35_add_fec(NULL); + imx35_add_imx2_wdt(NULL); platform_add_devices(devices, ARRAY_SIZE(devices)); imx35_add_imx_uart0(&uart_pdata); - mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata); + if (otg_mode_host) + imx35_add_mxc_ehci_otg(&otg_pdata); + + imx35_add_mxc_ehci_hs(&usb_host_pdata); - mxc_register_device(&mxc_usbh1, &usb_host_pdata); + if (!otg_mode_host) + imx35_add_fsl_usb2_udc(&usb_otg_pdata); imx35_add_mxc_nand(&mx35pdk_nand_board_info); - imx35_add_esdhc(0, NULL); + imx35_add_sdhci_esdhc_imx(0, NULL); if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT)) pr_warn("Init of the debugboard failed, all " diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index 2ff3f66..b752f6b 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -27,7 +27,6 @@ #include <linux/delay.h> #include <linux/spi/spi.h> #include <linux/irq.h> -#include <linux/fsl_devices.h> #include <linux/can/platform/sja1000.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> @@ -43,10 +42,8 @@ #include <mach/hardware.h> #include <mach/iomux-mx3.h> #include <mach/ipu.h> -#include <mach/mmc.h> #include <mach/mx3_camera.h> #include <mach/mx3fb.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx31.h" @@ -399,7 +396,7 @@ static void pcm970_sdhc1_exit(struct device *dev, void *data) gpio_free(SDHC1_GPIO_WP); } -static struct imxmmc_platform_data sdhc_pdata = { +static const struct imxmmc_platform_data sdhc_pdata __initconst = { #ifdef PCM970_SDHC_RW_SWITCH .get_ro = pcm970_sdhc1_get_ro, #endif @@ -441,7 +438,6 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size) static struct platform_device *devices[] __initdata = { &pcm037_flash, &pcm037_sram_device, - &imx_wdt_device0, &pcm037_mt9t031, &pcm037_mt9v022, }; @@ -538,18 +534,18 @@ static struct platform_device pcm970_sja1000 = { }; #if defined(CONFIG_USB_ULPI) -static struct mxc_usbh_platform_data otg_pdata = { +static struct mxc_usbh_platform_data otg_pdata __initdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; -static struct mxc_usbh_platform_data usbh2_pdata = { +static struct mxc_usbh_platform_data usbh2_pdata __initdata = { .portsc = MXC_EHCI_MODE_ULPI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; #endif -static struct fsl_usb2_platform_data otg_device_pdata = { +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; @@ -607,12 +603,13 @@ static void __init mxc_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); + imx31_add_imx2_wdt(NULL); imx31_add_imx_uart0(&uart_pdata); /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ imx31_add_imx_uart1(&uart_pdata); imx31_add_imx_uart2(&uart_pdata); - mxc_register_device(&mxc_w1_master_device, NULL); + imx31_add_mxc_w1(NULL); /* LAN9217 IRQ pin */ ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); @@ -632,7 +629,7 @@ static void __init mxc_board_init(void) imx31_add_imx_i2c2(&pcm037_i2c2_data); imx31_add_mxc_nand(&pcm037_nand_board_info); - mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); + imx31_add_mxc_mmc(0, &sdhc_pdata); mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); @@ -654,16 +651,16 @@ static void __init mxc_board_init(void) otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_otg_host, &otg_pdata); + imx31_add_mxc_ehci_otg(&otg_pdata); } usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_usbh2, &usbh2_pdata); + imx31_add_mxc_ehci_hs(2, &usbh2_pdata); #endif if (!otg_mode_host) - mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + imx31_add_fsl_usb2_udc(&otg_device_pdata); } diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 4e1de87..bcf83fc 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -27,7 +27,6 @@ #include <linux/i2c/at24.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> -#include <linux/fsl_devices.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -39,7 +38,6 @@ #include <mach/iomux-mx35.h> #include <mach/ipu.h> #include <mach/mx3fb.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include <mach/audmux.h> @@ -140,10 +138,9 @@ static struct i2c_board_info pcm043_i2c_devices[] = { static struct platform_device *devices[] __initdata = { &pcm043_flash, - &imx_wdt_device0, }; -static struct pad_desc pcm043_pads[] = { +static iomux_v3_cfg_t pcm043_pads[] = { /* UART1 */ MX35_PAD_CTS1__UART1_CTS, MX35_PAD_RTS1__UART1_RTS, @@ -230,8 +227,8 @@ static struct pad_desc pcm043_pads[] = { static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) { - struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; - struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; + iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; + iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; int ret; ret = gpio_request(AC97_GPIO_TXFS, "SSI"); @@ -240,7 +237,7 @@ static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) return; } - mxc_iomux_v3_setup_pad(&txfs_gpio); + mxc_iomux_v3_setup_pad(txfs_gpio); /* warm reset */ gpio_direction_output(AC97_GPIO_TXFS, 1); @@ -248,16 +245,16 @@ static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) gpio_set_value(AC97_GPIO_TXFS, 0); gpio_free(AC97_GPIO_TXFS); - mxc_iomux_v3_setup_pad(&txfs); + mxc_iomux_v3_setup_pad(txfs); } static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) { - struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; - struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; - struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28; - struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; - struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; + iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; + iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; + iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28; + iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; + iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; int ret; ret = gpio_request(AC97_GPIO_TXFS, "SSI"); @@ -272,9 +269,9 @@ static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) if (ret) goto err3; - mxc_iomux_v3_setup_pad(&txfs_gpio); - mxc_iomux_v3_setup_pad(&txd_gpio); - mxc_iomux_v3_setup_pad(&reset_gpio); + mxc_iomux_v3_setup_pad(txfs_gpio); + mxc_iomux_v3_setup_pad(txd_gpio); + mxc_iomux_v3_setup_pad(reset_gpio); gpio_direction_output(AC97_GPIO_TXFS, 0); gpio_direction_output(AC97_GPIO_TXD, 0); @@ -284,8 +281,8 @@ static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) udelay(10); gpio_direction_output(AC97_GPIO_RESET, 1); - mxc_iomux_v3_setup_pad(&txd); - mxc_iomux_v3_setup_pad(&txfs); + mxc_iomux_v3_setup_pad(txd); + mxc_iomux_v3_setup_pad(txfs); gpio_free(AC97_GPIO_RESET); err3: @@ -311,19 +308,19 @@ pcm037_nand_board_info __initconst = { }; #if defined(CONFIG_USB_ULPI) -static struct mxc_usbh_platform_data otg_pdata = { +static struct mxc_usbh_platform_data otg_pdata __initdata = { .portsc = MXC_EHCI_MODE_UTMI, .flags = MXC_EHCI_INTERFACE_DIFF_UNI, }; -static struct mxc_usbh_platform_data usbh1_pdata = { +static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { .portsc = MXC_EHCI_MODE_SERIAL, .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN, }; #endif -static struct fsl_usb2_platform_data otg_device_pdata = { +static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI, }; @@ -364,6 +361,7 @@ static void __init mxc_board_init(void) imx35_add_fec(NULL); platform_add_devices(devices, ARRAY_SIZE(devices)); + imx35_add_imx2_wdt(NULL); imx35_add_imx_uart0(&uart_pdata); imx35_add_mxc_nand(&pcm037_nand_board_info); @@ -386,16 +384,16 @@ static void __init mxc_board_init(void) otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - mxc_register_device(&mxc_otg_host, &otg_pdata); + imx35_add_mxc_ehci_otg(&otg_pdata); } - mxc_register_device(&mxc_usbh1, &usbh1_pdata); + imx35_add_mxc_ehci_hs(&usbh1_pdata); #endif if (!otg_mode_host) - mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + imx35_add_fsl_usb2_udc(&otg_device_pdata); imx35_add_flexcan1(NULL); - imx35_add_esdhc(0, NULL); + imx35_add_sdhci_esdhc_imx(0, NULL); } static void __init pcm043_timer_init(void) diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c index b4ffc53..47118f7 100644 --- a/arch/arm/mach-mx3/mm.c +++ b/arch/arm/mach-mx3/mm.c @@ -36,40 +36,16 @@ * @ingroup Memory */ -/*! - * This table defines static virtual address mappings for I/O regions. - * These are the mappings common across all MX3 boards. - */ -static struct map_desc mxc_io_desc[] __initdata = { - { - .virtual = X_MEMC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), - .length = X_MEMC_SIZE, - .type = MT_DEVICE - }, { - .virtual = AVIC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(AVIC_BASE_ADDR), - .length = AVIC_SIZE, - .type = MT_DEVICE_NONSHARED - }, { - .virtual = AIPS1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), - .length = AIPS1_SIZE, - .type = MT_DEVICE_NONSHARED - }, { - .virtual = AIPS2_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), - .length = AIPS2_SIZE, - .type = MT_DEVICE_NONSHARED - }, { - .virtual = SPBA0_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), - .length = SPBA0_SIZE, - .type = MT_DEVICE_NONSHARED - }, +#ifdef CONFIG_SOC_IMX31 +static struct map_desc mx31_io_desc[] __initdata = { + imx_map_entry(MX31, X_MEMC, MT_DEVICE), + imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), + imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), + imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), + imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), }; -/*! +/* * This function initializes the memory map. It is called during the * system startup to create static physical to virtual memory mappings * for the IO modules. @@ -77,34 +53,44 @@ static struct map_desc mxc_io_desc[] __initdata = { void __init mx31_map_io(void) { mxc_set_cpu_type(MXC_CPU_MX31); - mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); + mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); + iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); } -#ifdef CONFIG_ARCH_MX35 -void __init mx35_map_io(void) +int imx31_register_gpios(void); +void __init mx31_init_irq(void) { - mxc_set_cpu_type(MXC_CPU_MX35); - mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); - - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); + mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); + imx31_register_gpios(); } -#endif - -int imx3x_register_gpios(void); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +static struct map_desc mx35_io_desc[] __initdata = { + imx_map_entry(MX35, X_MEMC, MT_DEVICE), + imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), + imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), + imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), + imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), +}; -void __init mx31_init_irq(void) +void __init mx35_map_io(void) { - mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); - imx3x_register_gpios(); + mxc_set_cpu_type(MXC_CPU_MX35); + mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); + mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); + + iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); } +int imx35_register_gpios(void); void __init mx35_init_irq(void) { - mx31_init_irq(); + mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); + imx35_register_gpios(); } +#endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_CACHE_L2X0 static int mxc_init_l2x0(void) @@ -129,7 +115,7 @@ static int mxc_init_l2x0(void) pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); } - l2x0_base = ioremap(L2CC_BASE_ADDR, 4096); + l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); if (IS_ERR(l2x0_base)) { printk(KERN_ERR "remapping L2 cache area failed with %ld\n", PTR_ERR(l2x0_base)); diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c index 827fd3c..8f1a38e 100644 --- a/arch/arm/mach-mx3/mx31lilly-db.c +++ b/arch/arm/mach-mx3/mx31lilly-db.c @@ -34,7 +34,6 @@ #include <mach/common.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31lilly.h> -#include <mach/mmc.h> #include <mach/mx3fb.h> #include <mach/ipu.h> @@ -158,7 +157,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data) free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); } -static struct imxmmc_platform_data mmc_pdata = { +static const struct imxmmc_platform_data mmc_pdata __initconst = { .get_ro = mxc_mmc1_get_ro, .init = mxc_mmc1_init, .exit = mxc_mmc1_exit, @@ -216,7 +215,7 @@ void __init mx31lilly_db_init(void) imx31_add_imx_uart0(&uart_pdata); imx31_add_imx_uart1(&uart_pdata); imx31_add_imx_uart2(&uart_pdata); - mxc_register_device(&mxcsdhc_device0, &mmc_pdata); + imx31_add_mxc_mmc(0, &mmc_pdata); mx31lilly_init_fb(); } diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c index 7b0e74e..3124ea8 100644 --- a/arch/arm/mach-mx3/mx31lite-db.c +++ b/arch/arm/mach-mx3/mx31lite-db.c @@ -35,7 +35,6 @@ #include <mach/common.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31lite.h> -#include <mach/mmc.h> #include "devices-imx31.h" #include "devices.h" @@ -142,7 +141,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data) free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data); } -static struct imxmmc_platform_data mmc_pdata = { +static const struct imxmmc_platform_data mmc_pdata __initconst = { .get_ro = mxc_mmc1_get_ro, .init = mxc_mmc1_init, .exit = mxc_mmc1_exit, @@ -197,10 +196,9 @@ void __init mx31lite_db_init(void) ARRAY_SIZE(litekit_db_board_pins), "development board pins"); imx31_add_imx_uart0(&uart_pdata); - mxc_register_device(&mxcsdhc_device0, &mmc_pdata); + imx31_add_mxc_mmc(0, &mmc_pdata); imx31_add_spi_imx0(&spi0_pdata); platform_device_register(&litekit_led_device); - mxc_register_device(&imx_wdt_device0, NULL); + imx31_add_imx2_wdt(NULL); mxc_register_device(&imx_rtc_device0, NULL); } - diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c index fc395a7..94a0b9e 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c @@ -18,15 +18,12 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/types.h> -#include <linux/fsl_devices.h> #include <linux/usb/otg.h> #include <mach/common.h> #include <mach/iomux-mx3.h> #include <mach/hardware.h> -#include <mach/mmc.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include "devices-imx31.h" @@ -103,7 +100,7 @@ static void devboard_sdhc2_exit(struct device *dev, void *data) gpio_free(SDHC2_CD); } -static struct imxmmc_platform_data sdhc2_pdata = { +static const struct imxmmc_platform_data sdhc2_pdata __initconst = { .get_ro = devboard_sdhc2_get_ro, .init = devboard_sdhc2_init, .exit = devboard_sdhc2_exit, @@ -187,7 +184,7 @@ static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on) return 0; } -static struct mxc_usbh_platform_data usbh1_pdata = { +static struct mxc_usbh_platform_data usbh1_pdata __initdata = { .init = devboard_usbh1_hw_init, .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, @@ -196,6 +193,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = { static int __init devboard_usbh1_init(void) { struct otg_transceiver *otg; + struct platform_device *pdev; otg = kzalloc(sizeof(*otg), GFP_KERNEL); if (!otg) @@ -207,11 +205,15 @@ static int __init devboard_usbh1_init(void) usbh1_pdata.otg = otg; - return mxc_register_device(&mxc_usbh1, &usbh1_pdata); + pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + return 0; } -static struct fsl_usb2_platform_data usb_pdata = { +static const struct fsl_usb2_platform_data usb_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; @@ -228,11 +230,11 @@ void __init mx31moboard_devboard_init(void) imx31_add_imx_uart1(&uart_pdata); - mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); + imx31_add_mxc_mmc(1, &sdhc2_pdata); devboard_init_sel_gpios(); - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + imx31_add_fsl_usb2_udc(&usb_pdata); devboard_usbh1_init(); } diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index 18069cb..f449a97 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -21,7 +21,6 @@ #include <linux/slab.h> #include <linux/platform_device.h> #include <linux/types.h> -#include <linux/fsl_devices.h> #include <linux/usb/otg.h> @@ -29,12 +28,11 @@ #include <mach/hardware.h> #include <mach/imx-uart.h> #include <mach/iomux-mx3.h> -#include <mach/mmc.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include <media/soc_camera.h> +#include "devices-imx31.h" #include "devices.h" static unsigned int marxbot_pins[] = { @@ -116,7 +114,7 @@ static void marxbot_sdhc2_exit(struct device *dev, void *data) gpio_free(SDHC2_CD); } -static struct imxmmc_platform_data sdhc2_pdata = { +static const struct imxmmc_platform_data sdhc2_pdata __initconst = { .get_ro = marxbot_sdhc2_get_ro, .init = marxbot_sdhc2_init, .exit = marxbot_sdhc2_exit, @@ -302,7 +300,7 @@ static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on) return 0; } -static struct mxc_usbh_platform_data usbh1_pdata = { +static struct mxc_usbh_platform_data usbh1_pdata __initdata = { .init = marxbot_usbh1_hw_init, .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, @@ -311,6 +309,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = { static int __init marxbot_usbh1_init(void) { struct otg_transceiver *otg; + struct platform_device *pdev; otg = kzalloc(sizeof(*otg), GFP_KERNEL); if (!otg) @@ -322,10 +321,14 @@ static int __init marxbot_usbh1_init(void) usbh1_pdata.otg = otg; - return mxc_register_device(&mxc_usbh1, &usbh1_pdata); + pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + return 0; } -static struct fsl_usb2_platform_data usb_pdata = { +static const struct fsl_usb2_platform_data usb_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; @@ -344,7 +347,7 @@ void __init mx31moboard_marxbot_init(void) dspics_resets_init(); - mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); + imx31_add_mxc_mmc(1, &sdhc2_pdata); spi_register_board_info(marxbot_spi_board_info, ARRAY_SIZE(marxbot_spi_board_info)); @@ -357,7 +360,7 @@ void __init mx31moboard_marxbot_init(void) gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + imx31_add_fsl_usb2_udc(&usb_pdata); marxbot_usbh1_init(); } diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c index 04760a5..bbec3c8 100644 --- a/arch/arm/mach-mx3/mx31moboard-smartbot.c +++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c @@ -19,7 +19,6 @@ #include <linux/i2c.h> #include <linux/platform_device.h> #include <linux/types.h> -#include <linux/fsl_devices.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> @@ -28,7 +27,6 @@ #include <mach/hardware.h> #include <mach/iomux-mx3.h> #include <mach/board-mx31moboard.h> -#include <mach/mxc_ehci.h> #include <mach/ulpi.h> #include <media/soc_camera.h> @@ -118,24 +116,30 @@ static int __init smartbot_cam_init(void) return 0; } -static struct fsl_usb2_platform_data usb_pdata = { +static const struct fsl_usb2_platform_data usb_pdata __initconst = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_ULPI, }; #if defined(CONFIG_USB_ULPI) -static struct mxc_usbh_platform_data otg_host_pdata = { +static struct mxc_usbh_platform_data otg_host_pdata __initdata = { .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, .flags = MXC_EHCI_POWER_PINS_ENABLED, }; static int __init smartbot_otg_host_init(void) { + struct platform_device *pdev; + otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - return mxc_register_device(&mxc_otg_host, &otg_host_pdata); + pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + return 0; } #else static inline int smartbot_otg_host_init(void) { return 0; } @@ -182,7 +186,7 @@ void __init mx31moboard_smartbot_init(int board) switch (board) { case MX31SMARTBOT: - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + imx31_add_fsl_usb2_udc(&usb_pdata); break; case MX31EYEBOT: smartbot_otg_host_init(); diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 3ec910a..55254b6 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -1,20 +1,47 @@ if ARCH_MX5 +# ARCH_MX51 and ARCH_MX50 are left for compatibility + +config ARCH_MX50 + bool config ARCH_MX51 bool - default y + +config ARCH_MX53 + bool + +config SOC_IMX50 + bool + select MXC_TZIC + select ARCH_MXC_IOMUX_V3 + select ARCH_MXC_AUDMUX_V2 + select ARCH_HAS_CPUFREQ + select ARCH_MX50 + +config SOC_IMX51 + bool select MXC_TZIC select ARCH_MXC_IOMUX_V3 select ARCH_MXC_AUDMUX_V2 select ARCH_HAS_CPUFREQ + select ARCH_MX51 + +config SOC_IMX53 + bool + select MXC_TZIC + select ARCH_MXC_IOMUX_V3 + select ARCH_MX53 comment "MX5 platforms:" config MACH_MX51_BABBAGE bool "Support MX51 BABBAGE platforms" + select SOC_IMX51 + select IMX_HAVE_PLATFORM_IMX2_WDT select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_ESDHC + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select IMX_HAVE_PLATFORM_SPI_IMX help Include support for MX51 Babbage platform, also known as MX51EVK in u-boot. This includes specific configurations for the board and its @@ -22,7 +49,9 @@ config MACH_MX51_BABBAGE config MACH_MX51_3DS bool "Support MX51PDK (3DS)" + select SOC_IMX51 select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_SPI_IMX select MXC_DEBUG_BOARD help @@ -31,6 +60,7 @@ config MACH_MX51_3DS config MACH_EUKREA_CPUIMX51 bool "Support Eukrea CPUIMX51 module" + select SOC_IMX51 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_NAND @@ -47,7 +77,7 @@ choice config MACH_EUKREA_MBIMX51_BASEBOARD prompt "Eukrea MBIMX51 development board" bool - select IMX_HAVE_PLATFORM_ESDHC + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX help This adds board specific devices that can be found on Eukrea's MBIMX51 evaluation board. @@ -56,6 +86,7 @@ endchoice config MACH_EUKREA_CPUIMX51SD bool "Support Eukrea CPUIMX51SD module" + select SOC_IMX51 select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_SPI_IMX select IMX_HAVE_PLATFORM_IMX_UART @@ -72,7 +103,7 @@ choice config MACH_EUKREA_MBIMXSD51_BASEBOARD prompt "Eukrea MBIMXSD development board" bool - select IMX_HAVE_PLATFORM_ESDHC + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX help This adds board specific devices that can be found on Eukrea's MBIMXSD evaluation board. @@ -81,9 +112,33 @@ endchoice config MACH_MX51_EFIKAMX bool "Support MX51 Genesi Efika MX nettop" + select SOC_IMX51 select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select IMX_HAVE_PLATFORM_SPI_IMX help Include support for Genesi Efika MX nettop. This includes specific configurations for the board and its peripherals. +config MACH_MX53_EVK + bool "Support MX53 EVK platforms" + select SOC_IMX53 + select IMX_HAVE_PLATFORM_IMX_UART + help + Include support for MX53 EVK platform. This includes specific + configurations for the board and its peripherals. + + +config MACH_MX50_RDP + bool "Support MX50 reference design platform" + depends on BROKEN + select SOC_IMX50 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select IMX_HAVE_PLATFORM_SPI_IMX + help + Include support for MX50 reference design platform (RDP) board. This + includes specific configurations for the board and its peripherals. + endif diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 462f177..0c398ba 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -3,13 +3,16 @@ # # Object file lists. -obj-y := cpu.o mm.o clock-mx51.o devices.o +obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o +obj-$(CONFIG_SOC_IMX50) += mm-mx50.o obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o +obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o +obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot index 9939a19..e928be1 100644 --- a/arch/arm/mach-mx5/Makefile.boot +++ b/arch/arm/mach-mx5/Makefile.boot @@ -1,3 +1,9 @@ - zreladdr-y := 0x90008000 -params_phys-y := 0x90000100 -initrd_phys-y := 0x90800000 + zreladdr-$(CONFIG_ARCH_MX50) := 0x70008000 +params_phys-$(CONFIG_ARCH_MX50) := 0x70000100 +initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000 + zreladdr-$(CONFIG_ARCH_MX51) := 0x90008000 +params_phys-$(CONFIG_ARCH_MX51) := 0x90000100 +initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000 + zreladdr-$(CONFIG_ARCH_MX53) := 0x70008000 +params_phys-$(CONFIG_ARCH_MX53) := 0x70000100 +initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000 diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c index 6a9792f..f8652ef 100644 --- a/arch/arm/mach-mx5/board-cpuimx51.c +++ b/arch/arm/mach-mx5/board-cpuimx51.c @@ -40,11 +40,11 @@ #include "devices-imx51.h" #include "devices.h" -#define CPUIMX51_USBH1_STP (0*32 + 27) -#define CPUIMX51_QUARTA_GPIO (2*32 + 28) -#define CPUIMX51_QUARTB_GPIO (2*32 + 25) -#define CPUIMX51_QUARTC_GPIO (2*32 + 26) -#define CPUIMX51_QUARTD_GPIO (2*32 + 27) +#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27) +#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28) +#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25) +#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26) +#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27) #define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO) #define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO) #define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO) @@ -113,7 +113,7 @@ static struct platform_device *devices[] __initdata = { #endif }; -static struct pad_desc eukrea_cpuimx51_pads[] = { +static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { /* UART1 */ MX51_PAD_UART1_RXD__UART1_RXD, MX51_PAD_UART1_TXD__UART1_TXD, @@ -121,15 +121,15 @@ static struct pad_desc eukrea_cpuimx51_pads[] = { MX51_PAD_UART1_CTS__UART1_CTS, /* I2C2 */ - MX51_PAD_GPIO_1_2__I2C2_SCL, - MX51_PAD_GPIO_1_3__I2C2_SDA, - MX51_PAD_NANDF_D10__GPIO_3_30, + MX51_PAD_GPIO1_2__I2C2_SCL, + MX51_PAD_GPIO1_3__I2C2_SDA, + MX51_PAD_NANDF_D10__GPIO3_30, /* QUART IRQ */ - MX51_PAD_NANDF_D15__GPIO_3_25, - MX51_PAD_NANDF_D14__GPIO_3_26, - MX51_PAD_NANDF_D13__GPIO_3_27, - MX51_PAD_NANDF_D12__GPIO_3_28, + MX51_PAD_NANDF_D15__GPIO3_25, + MX51_PAD_NANDF_D14__GPIO3_26, + MX51_PAD_NANDF_D13__GPIO3_27, + MX51_PAD_NANDF_D12__GPIO3_28, /* USB HOST1 */ MX51_PAD_USBH1_CLK__USBH1_CLK, @@ -178,6 +178,8 @@ static int initialize_otg_port(struct platform_device *pdev) void __iomem *usbother_base; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + if (!usb_base) + return -ENOMEM; usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; /* Set the PHY clock to 19.2MHz */ @@ -196,6 +198,8 @@ static int initialize_usbh1_port(struct platform_device *pdev) void __iomem *usbother_base; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + if (!usb_base) + return -ENOMEM; usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; /* The clock for the USBH1 ULPI port will come externally from the PHY. */ @@ -292,7 +296,7 @@ static struct sys_timer mxc_timer = { MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") /* Maintainer: Eric Bénard <eric@eukrea.com> */ - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX51_PHYS_OFFSET + 0x100, .map_io = mx51_map_io, .init_irq = mx51_init_irq, .init_machine = eukrea_cpuimx51_init, diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c index 4b3a611..ad93189 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c @@ -43,19 +43,19 @@ #include "devices-imx51.h" #include "devices.h" -#define USBH1_RST (1*32 + 28) -#define ETH_RST (1*32 + 31) -#define TSC2007_IRQGPIO (2*32 + 12) -#define CAN_IRQGPIO (0*32 + 1) -#define CAN_RST (3*32 + 15) -#define CAN_NCS (3*32 + 24) -#define CAN_RXOBF (0*32 + 4) -#define CAN_RX1BF (0*32 + 6) -#define CAN_TXORTS (0*32 + 7) -#define CAN_TX1RTS (0*32 + 8) -#define CAN_TX2RTS (0*32 + 9) -#define I2C_SCL (3*32 + 16) -#define I2C_SDA (3*32 + 17) +#define USBH1_RST IMX_GPIO_NR(2, 28) +#define ETH_RST IMX_GPIO_NR(2, 31) +#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12) +#define CAN_IRQGPIO IMX_GPIO_NR(1, 1) +#define CAN_RST IMX_GPIO_NR(4, 15) +#define CAN_NCS IMX_GPIO_NR(4, 24) +#define CAN_RXOBF IMX_GPIO_NR(1, 4) +#define CAN_RX1BF IMX_GPIO_NR(1, 6) +#define CAN_TXORTS IMX_GPIO_NR(1, 7) +#define CAN_TX1RTS IMX_GPIO_NR(1, 8) +#define CAN_TX2RTS IMX_GPIO_NR(1, 9) +#define I2C_SCL IMX_GPIO_NR(4, 16) +#define I2C_SDA IMX_GPIO_NR(4, 17) /* USB_CTRL_1 */ #define MX51_USB_CTRL_1_OFFSET 0x10 @@ -65,10 +65,7 @@ #define MX51_USB_PLL_DIV_19_2_MHZ 0x01 #define MX51_USB_PLL_DIV_24_MHZ 0x02 -#define CPUIMX51SD_GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, \ - MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) - -static struct pad_desc eukrea_cpuimx51sd_pads[] = { +static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = { /* UART1 */ MX51_PAD_UART1_RXD__UART1_RXD, MX51_PAD_UART1_TXD__UART1_TXD, @@ -88,30 +85,33 @@ static struct pad_desc eukrea_cpuimx51sd_pads[] = { MX51_PAD_USBH1_DATA6__USBH1_DATA6, MX51_PAD_USBH1_DATA7__USBH1_DATA7, MX51_PAD_USBH1_STP__USBH1_STP, - MX51_PAD_EIM_CS3__GPIO_2_28, /* PHY nRESET */ + MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */ /* FEC */ - MX51_PAD_EIM_DTACK__GPIO_2_31, /* PHY nRESET */ + MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */ /* HSI2C */ - MX51_PAD_I2C1_CLK__GPIO_4_16, - MX51_PAD_I2C1_DAT__GPIO_4_17, + MX51_PAD_I2C1_CLK__GPIO4_16, + MX51_PAD_I2C1_DAT__GPIO4_17, /* CAN */ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, MX51_PAD_CSPI1_MISO__ECSPI1_MISO, MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, - MX51_PAD_CSPI1_SS0__GPIO_4_24, /* nCS */ - MX51_PAD_CSI2_PIXCLK__GPIO_4_15, /* nReset */ - MX51_PAD_GPIO_1_1__GPIO_1_1, /* IRQ */ - MX51_PAD_GPIO_1_4__GPIO_1_4, /* Control signals */ - MX51_PAD_GPIO_1_6__GPIO_1_6, - MX51_PAD_GPIO_1_7__GPIO_1_7, - MX51_PAD_GPIO_1_8__GPIO_1_8, - MX51_PAD_GPIO_1_9__GPIO_1_9, + MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */ + MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */ + MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */ + MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */ + MX51_PAD_GPIO1_6__GPIO1_6, + MX51_PAD_GPIO1_7__GPIO1_7, + MX51_PAD_GPIO1_8__GPIO1_8, + MX51_PAD_GPIO1_9__GPIO1_9, /* Touchscreen */ - CPUIMX51SD_GPIO_3_12, /* IRQ */ + /* IRQ */ + _MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | + PAD_CTL_PKE | PAD_CTL_SRE_FAST | + PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), }; static const struct imxuart_platform_data uart_pdata __initconst = { @@ -157,6 +157,8 @@ static int initialize_otg_port(struct platform_device *pdev) void __iomem *usbother_base; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + if (!usb_base) + return -ENOMEM; usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; /* Set the PHY clock to 19.2MHz */ @@ -175,6 +177,8 @@ static int initialize_usbh1_port(struct platform_device *pdev) void __iomem *usbother_base; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + if (!usb_base) + return -ENOMEM; usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; /* The clock for the USBH1 ULPI port will come from the PHY. */ @@ -243,7 +247,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = { .mode = SPI_MODE_0, .chip_select = 0, .platform_data = &mcp251x_info, - .irq = gpio_to_irq(0 * 32 + 1) + .irq = gpio_to_irq(CAN_IRQGPIO) }, }; @@ -323,7 +327,7 @@ static struct sys_timer mxc_timer = { MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD") /* Maintainer: Eric Bénard <eric@eukrea.com> */ - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX51_PHYS_OFFSET + 0x100, .map_io = mx51_map_io, .init_irq = mx51_init_irq, .init_machine = eukrea_cpuimx51sd_init, diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c new file mode 100644 index 0000000..fd32e4c --- /dev/null +++ b/arch/arm/mach-mx5/board-mx50_rdp.c @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/fsl_devices.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/iomux-mx50.h> + +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include "devices-mx50.h" + +static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = { + /* SD1 */ + MX50_PAD_ECSPI2_SS0__GPIO_4_19, + MX50_PAD_EIM_CRE__GPIO_1_27, + MX50_PAD_SD1_CMD__SD1_CMD, + + MX50_PAD_SD1_CLK__SD1_CLK, + MX50_PAD_SD1_D0__SD1_D0, + MX50_PAD_SD1_D1__SD1_D1, + MX50_PAD_SD1_D2__SD1_D2, + MX50_PAD_SD1_D3__SD1_D3, + + /* SD2 */ + MX50_PAD_SD2_CD__GPIO_5_17, + MX50_PAD_SD2_WP__GPIO_5_16, + MX50_PAD_SD2_CMD__SD2_CMD, + MX50_PAD_SD2_CLK__SD2_CLK, + MX50_PAD_SD2_D0__SD2_D0, + MX50_PAD_SD2_D1__SD2_D1, + MX50_PAD_SD2_D2__SD2_D2, + MX50_PAD_SD2_D3__SD2_D3, + MX50_PAD_SD2_D4__SD2_D4, + MX50_PAD_SD2_D5__SD2_D5, + MX50_PAD_SD2_D6__SD2_D6, + MX50_PAD_SD2_D7__SD2_D7, + + /* SD3 */ + MX50_PAD_SD3_CMD__SD3_CMD, + MX50_PAD_SD3_CLK__SD3_CLK, + MX50_PAD_SD3_D0__SD3_D0, + MX50_PAD_SD3_D1__SD3_D1, + MX50_PAD_SD3_D2__SD3_D2, + MX50_PAD_SD3_D3__SD3_D3, + MX50_PAD_SD3_D4__SD3_D4, + MX50_PAD_SD3_D5__SD3_D5, + MX50_PAD_SD3_D6__SD3_D6, + MX50_PAD_SD3_D7__SD3_D7, + + /* PWR_INT */ + MX50_PAD_ECSPI2_MISO__GPIO_4_18, + + /* UART pad setting */ + MX50_PAD_UART1_TXD__UART1_TXD, + MX50_PAD_UART1_RXD__UART1_RXD, + MX50_PAD_UART1_RTS__UART1_RTS, + MX50_PAD_UART2_TXD__UART2_TXD, + MX50_PAD_UART2_RXD__UART2_RXD, + MX50_PAD_UART2_CTS__UART2_CTS, + MX50_PAD_UART2_RTS__UART2_RTS, + + MX50_PAD_I2C1_SCL__I2C1_SCL, + MX50_PAD_I2C1_SDA__I2C1_SDA, + MX50_PAD_I2C2_SCL__I2C2_SCL, + MX50_PAD_I2C2_SDA__I2C2_SDA, + + MX50_PAD_EPITO__USBH1_PWR, + /* Need to comment below line if + * one needs to debug owire. + */ + MX50_PAD_OWIRE__USBH1_OC, + /* using gpio to control otg pwr */ + MX50_PAD_PWM2__GPIO_6_25, + MX50_PAD_I2C3_SCL__USBOTG_OC, + + MX50_PAD_SSI_RXC__FEC_MDIO, + MX50_PAD_SSI_RXC__FEC_MDIO, + MX50_PAD_DISP_D0__FEC_TXCLK, + MX50_PAD_DISP_D1__FEC_RX_ER, + MX50_PAD_DISP_D2__FEC_RX_DV, + MX50_PAD_DISP_D3__FEC_RXD1, + MX50_PAD_DISP_D4__FEC_RXD0, + MX50_PAD_DISP_D5__FEC_TX_EN, + MX50_PAD_DISP_D6__FEC_TXD1, + MX50_PAD_DISP_D7__FEC_TXD0, + MX50_PAD_SSI_RXFS__FEC_MDC, + MX50_PAD_I2C3_SDA__GPIO_6_23, + MX50_PAD_ECSPI1_SCLK__GPIO_4_12, + + MX50_PAD_CSPI_SS0__CSPI_SS0, + MX50_PAD_ECSPI1_MOSI__CSPI_SS1, + MX50_PAD_CSPI_MOSI__CSPI_MOSI, + MX50_PAD_CSPI_MISO__CSPI_MISO, + + /* SGTL500_OSC_EN */ + MX50_PAD_UART1_CTS__GPIO_6_8, + + /* SGTL_AMP_SHDN */ + MX50_PAD_UART3_RXD__GPIO_6_15, + + /* Keypad */ + MX50_PAD_KEY_COL0__KEY_COL0, + MX50_PAD_KEY_ROW0__KEY_ROW0, + MX50_PAD_KEY_COL1__KEY_COL1, + MX50_PAD_KEY_ROW1__KEY_ROW1, + MX50_PAD_KEY_COL2__KEY_COL2, + MX50_PAD_KEY_ROW2__KEY_ROW2, + MX50_PAD_KEY_COL3__KEY_COL3, + MX50_PAD_KEY_ROW3__KEY_ROW3, + MX50_PAD_EIM_DA0__KEY_COL4, + MX50_PAD_EIM_DA1__KEY_ROW4, + MX50_PAD_EIM_DA2__KEY_COL5, + MX50_PAD_EIM_DA3__KEY_ROW5, + MX50_PAD_EIM_DA4__KEY_COL6, + MX50_PAD_EIM_DA5__KEY_ROW6, + MX50_PAD_EIM_DA6__KEY_COL7, + MX50_PAD_EIM_DA7__KEY_ROW7, + /*EIM pads */ + MX50_PAD_EIM_DA8__GPIO_1_8, + MX50_PAD_EIM_DA9__GPIO_1_9, + MX50_PAD_EIM_DA10__GPIO_1_10, + MX50_PAD_EIM_DA11__GPIO_1_11, + MX50_PAD_EIM_DA12__GPIO_1_12, + MX50_PAD_EIM_DA13__GPIO_1_13, + MX50_PAD_EIM_DA14__GPIO_1_14, + MX50_PAD_EIM_DA15__GPIO_1_15, + MX50_PAD_EIM_CS2__GPIO_1_16, + MX50_PAD_EIM_CS1__GPIO_1_17, + MX50_PAD_EIM_CS0__GPIO_1_18, + MX50_PAD_EIM_EB0__GPIO_1_19, + MX50_PAD_EIM_EB1__GPIO_1_20, + MX50_PAD_EIM_WAIT__GPIO_1_21, + MX50_PAD_EIM_BCLK__GPIO_1_22, + MX50_PAD_EIM_RDY__GPIO_1_23, + MX50_PAD_EIM_OE__GPIO_1_24, +}; + +/* Serial ports */ +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +/* + * Board specific initialization. + */ +static void __init mx50_rdp_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads, + ARRAY_SIZE(mx50_rdp_pads)); + + imx50_add_imx_uart(0, &uart_pdata); + imx50_add_imx_uart(1, &uart_pdata); +} + +static void __init mx50_rdp_timer_init(void) +{ + mx50_clocks_init(32768, 24000000, 22579200); +} + +static struct sys_timer mx50_rdp_timer = { + .init = mx50_rdp_timer_init, +}; + +MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform") + .map_io = mx50_map_io, + .init_irq = mx50_init_irq, + .init_machine = mx50_rdp_board_init, + .timer = &mx50_rdp_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index 79ce8dc..e42bd2e 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -30,7 +30,7 @@ #define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6) #define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) -static struct pad_desc mx51_3ds_pads[] = { +static iomux_v3_cfg_t mx51_3ds_pads[] = { /* UART1 */ MX51_PAD_UART1_RXD__UART1_RXD, MX51_PAD_UART1_TXD__UART1_TXD, @@ -50,7 +50,7 @@ static struct pad_desc mx51_3ds_pads[] = { MX51_PAD_EIM_D27__UART3_RTS, /* CPLD PARENT IRQ PIN */ - MX51_PAD_GPIO_1_6__GPIO_1_6, + MX51_PAD_GPIO1_6__GPIO1_6, /* KPP */ MX51_PAD_KEY_ROW0__KEY_ROW0, @@ -68,7 +68,7 @@ static struct pad_desc mx51_3ds_pads[] = { MX51_PAD_NANDF_RB2__ECSPI2_SCLK, MX51_PAD_NANDF_RB3__ECSPI2_MISO, MX51_PAD_NANDF_D15__ECSPI2_MOSI, - MX51_PAD_NANDF_D12__GPIO_3_28, + MX51_PAD_NANDF_D12__GPIO3_28, }; /* Serial ports */ @@ -172,6 +172,7 @@ static void __init mxc_board_init(void) printk(KERN_WARNING "Init of the debugboard failed, all " "devices on the board are unusable.\n"); + imx51_add_sdhci_esdhc_imx(0, NULL); mxc_init_keypad(); } @@ -186,7 +187,7 @@ static struct sys_timer mxc_timer = { MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") /* Maintainer: Freescale Semiconductor, Inc. */ - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX51_PHYS_OFFSET + 0x100, .map_io = mx51_map_io, .init_irq = mx51_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index acbe30d..1d231e8 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -20,6 +20,8 @@ #include <linux/fec.h> #include <linux/gpio_keys.h> #include <linux/input.h> +#include <linux/spi/flash.h> +#include <linux/spi/spi.h> #include <mach/common.h> #include <mach/hardware.h> @@ -36,11 +38,13 @@ #include "devices.h" #include "cpu_op-mx51.h" -#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ -#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ -#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */ -#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */ -#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */ +#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7) +#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27) +#define BABBAGE_PHY_RESET IMX_GPIO_NR(2, 5) +#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14) +#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21) +#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24) +#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25) /* USB_CTRL_1 */ #define MX51_USB_CTRL_1_OFFSET 0x10 @@ -65,7 +69,7 @@ static const struct gpio_keys_platform_data imx_button_data __initconst = { .nbuttons = ARRAY_SIZE(babbage_buttons), }; -static struct pad_desc mx51babbage_pads[] = { +static iomux_v3_cfg_t mx51babbage_pads[] = { /* UART1 */ MX51_PAD_UART1_RXD__UART1_RXD, MX51_PAD_UART1_TXD__UART1_TXD, @@ -91,8 +95,8 @@ static struct pad_desc mx51babbage_pads[] = { MX51_PAD_KEY_COL5__I2C2_SDA, /* HSI2C */ - MX51_PAD_I2C1_CLK__HSI2C_CLK, - MX51_PAD_I2C1_DAT__HSI2C_DAT, + MX51_PAD_I2C1_CLK__I2C1_CLK, + MX51_PAD_I2C1_DAT__I2C1_DAT, /* USB HOST1 */ MX51_PAD_USBH1_CLK__USBH1_CLK, @@ -108,29 +112,29 @@ static struct pad_desc mx51babbage_pads[] = { MX51_PAD_USBH1_DATA7__USBH1_DATA7, /* USB HUB reset line*/ - MX51_PAD_GPIO_1_7__GPIO_1_7, + MX51_PAD_GPIO1_7__GPIO1_7, /* FEC */ MX51_PAD_EIM_EB2__FEC_MDIO, - MX51_PAD_EIM_EB3__FEC_RDAT1, - MX51_PAD_EIM_CS2__FEC_RDAT2, - MX51_PAD_EIM_CS3__FEC_RDAT3, + MX51_PAD_EIM_EB3__FEC_RDATA1, + MX51_PAD_EIM_CS2__FEC_RDATA2, + MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_EIM_CS4__FEC_RX_ER, MX51_PAD_EIM_CS5__FEC_CRS, MX51_PAD_NANDF_RB2__FEC_COL, - MX51_PAD_NANDF_RB3__FEC_RXCLK, - MX51_PAD_NANDF_RB6__FEC_RDAT0, - MX51_PAD_NANDF_RB7__FEC_TDAT0, + MX51_PAD_NANDF_RB3__FEC_RX_CLK, + MX51_PAD_NANDF_D9__FEC_RDATA0, + MX51_PAD_NANDF_D8__FEC_TDATA0, MX51_PAD_NANDF_CS2__FEC_TX_ER, MX51_PAD_NANDF_CS3__FEC_MDC, - MX51_PAD_NANDF_CS4__FEC_TDAT1, - MX51_PAD_NANDF_CS5__FEC_TDAT2, - MX51_PAD_NANDF_CS6__FEC_TDAT3, + MX51_PAD_NANDF_CS4__FEC_TDATA1, + MX51_PAD_NANDF_CS5__FEC_TDATA2, + MX51_PAD_NANDF_CS6__FEC_TDATA3, MX51_PAD_NANDF_CS7__FEC_TX_EN, MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, /* FEC PHY reset line */ - MX51_PAD_EIM_A20__GPIO_2_14, + MX51_PAD_EIM_A20__GPIO2_14, /* SD 1 */ MX51_PAD_SD1_CMD__SD1_CMD, @@ -147,6 +151,13 @@ static struct pad_desc mx51babbage_pads[] = { MX51_PAD_SD2_DATA1__SD2_DATA1, MX51_PAD_SD2_DATA2__SD2_DATA2, MX51_PAD_SD2_DATA3__SD2_DATA3, + + /* eCSPI1 */ + MX51_PAD_CSPI1_MISO__ECSPI1_MISO, + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + MX51_PAD_CSPI1_SS0__GPIO4_24, + MX51_PAD_CSPI1_SS1__GPIO4_25, }; /* Serial ports */ @@ -177,12 +188,12 @@ static struct imxi2c_platform_data babbage_hsi2c_data = { static int gpio_usbh1_active(void) { - struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27; - struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5; + iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27; + iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO2_5; int ret; /* Set USBH1_STP to GPIO and toggle it */ - mxc_iomux_v3_setup_pad(&usbh1stp_gpio); + mxc_iomux_v3_setup_pad(usbh1stp_gpio); ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp"); if (ret) { @@ -195,7 +206,7 @@ static int gpio_usbh1_active(void) gpio_free(BABBAGE_USBH1_STP); /* De-assert USB PHY RESETB */ - mxc_iomux_v3_setup_pad(&phyreset_gpio); + mxc_iomux_v3_setup_pad(phyreset_gpio); ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset"); if (ret) { @@ -251,6 +262,8 @@ static int initialize_otg_port(struct platform_device *pdev) void __iomem *usbother_base; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + if (!usb_base) + return -ENOMEM; usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; /* Set the PHY clock to 19.2MHz */ @@ -269,6 +282,8 @@ static int initialize_usbh1_port(struct platform_device *pdev) void __iomem *usbother_base; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + if (!usb_base) + return -ENOMEM; usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; /* The clock for the USBH1 ULPI port will come externally from the PHY. */ @@ -310,13 +325,35 @@ static int __init babbage_otg_mode(char *options) } __setup("otg_mode=", babbage_otg_mode); +static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = { + { + .modalias = "mtd_dataflash", + .max_speed_hz = 25000000, + .bus_num = 0, + .chip_select = 1, + .mode = SPI_MODE_0, + .platform_data = NULL, + }, +}; + +static int mx51_babbage_spi_cs[] = { + BABBAGE_ECSPI1_CS0, + BABBAGE_ECSPI1_CS1, +}; + +static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = { + .chipselect = mx51_babbage_spi_cs, + .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs), +}; + /* * Board specific initialization. */ static void __init mxc_board_init(void) { - struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; - struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21; + iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; + iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 | + MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP); #if defined(CONFIG_CPU_FREQ_IMX) get_cpu_op = mx51_get_cpu_op; @@ -328,8 +365,7 @@ static void __init mxc_board_init(void) imx51_add_fec(NULL); /* Set the PAD settings for the pwr key. */ - power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2; - mxc_iomux_v3_setup_pad(&power_key); + mxc_iomux_v3_setup_pad(power_key); imx51_add_gpio_keys(&imx_button_data); imx51_add_imx_i2c(0, &babbage_i2c_data); @@ -346,11 +382,16 @@ static void __init mxc_board_init(void) gpio_usbh1_active(); mxc_register_device(&mxc_usbh1_device, &usbh1_config); /* setback USBH1_STP to be function */ - mxc_iomux_v3_setup_pad(&usbh1stp); + mxc_iomux_v3_setup_pad(usbh1stp); babbage_usbhub_reset(); - imx51_add_esdhc(0, NULL); - imx51_add_esdhc(1, NULL); + imx51_add_sdhci_esdhc_imx(0, NULL); + imx51_add_sdhci_esdhc_imx(1, NULL); + + spi_register_board_info(mx51_babbage_spi_board_info, + ARRAY_SIZE(mx51_babbage_spi_board_info)); + imx51_add_ecspi(0, &mx51_babbage_spi_pdata); + imx51_add_imx2_wdt(0, NULL); } static void __init mx51_babbage_timer_init(void) diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index 6e623bd..b7946f8 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c @@ -18,9 +18,13 @@ #include <linux/platform_device.h> #include <linux/i2c.h> #include <linux/gpio.h> +#include <linux/leds.h> +#include <linux/input.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/fsl_devices.h> +#include <linux/spi/flash.h> +#include <linux/spi/spi.h> #include <mach/common.h> #include <mach/hardware.h> @@ -39,12 +43,81 @@ #define MX51_USB_PLL_DIV_24_MHZ 0x01 -static struct pad_desc mx51efikamx_pads[] = { +#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) +#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17) +#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11) + +#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13) +#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14) +#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15) + +#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31) + +#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24) +#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25) + +/* board 1.1 doesn't have same reset gpio */ +#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2) +#define EFIKAMX_RESET IMX_GPIO_NR(1, 4) + +/* the pci ids pin have pull up. they're driven low according to board id */ +#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) + +static iomux_v3_cfg_t mx51efikamx_pads[] = { /* UART1 */ MX51_PAD_UART1_RXD__UART1_RXD, MX51_PAD_UART1_TXD__UART1_TXD, MX51_PAD_UART1_RTS__UART1_RTS, MX51_PAD_UART1_CTS__UART1_CTS, + /* board id */ + MX51_PAD_PCBID0, + MX51_PAD_PCBID1, + MX51_PAD_PCBID2, + + /* SD 1 */ + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + + /* SD 2 */ + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + + /* SD/MMC WP/CD */ + MX51_PAD_GPIO1_0__SD1_CD, + MX51_PAD_GPIO1_1__SD1_WP, + MX51_PAD_GPIO1_7__SD2_WP, + MX51_PAD_GPIO1_8__SD2_CD, + + /* leds */ + MX51_PAD_CSI1_D9__GPIO3_13, + MX51_PAD_CSI1_VSYNC__GPIO3_14, + MX51_PAD_CSI1_HSYNC__GPIO3_15, + + /* power key */ + MX51_PAD_PWRKEY, + + /* spi */ + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, + MX51_PAD_CSPI1_MISO__ECSPI1_MISO, + MX51_PAD_CSPI1_SS0__GPIO4_24, + MX51_PAD_CSPI1_SS1__GPIO4_25, + MX51_PAD_CSPI1_RDY__ECSPI1_RDY, + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + + /* reset */ + MX51_PAD_DI1_PIN13__GPIO3_2, + MX51_PAD_GPIO1_4__GPIO1_4, }; /* Serial ports */ @@ -75,6 +148,8 @@ static int initialize_otg_port(struct platform_device *pdev) void __iomem *usb_base; void __iomem *usbother_base; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + if (!usb_base) + return -ENOMEM; usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); /* Set the PHY clock to 19.2MHz */ @@ -92,12 +167,182 @@ static struct mxc_usbh_platform_data dr_utmi_config = { .flags = MXC_EHCI_INTERNAL_PHY, }; +/* PCBID2 PCBID1 PCBID0 STATE + 1 1 1 ER1:rev1.1 + 1 1 0 ER2:rev1.2 + 1 0 1 ER3:rev1.3 + 1 0 0 ER4:rev1.4 +*/ +static void __init mx51_efikamx_board_id(void) +{ + int id; + + /* things are taking time to settle */ + msleep(150); + + gpio_request(EFIKAMX_PCBID0, "pcbid0"); + gpio_direction_input(EFIKAMX_PCBID0); + gpio_request(EFIKAMX_PCBID1, "pcbid1"); + gpio_direction_input(EFIKAMX_PCBID1); + gpio_request(EFIKAMX_PCBID2, "pcbid2"); + gpio_direction_input(EFIKAMX_PCBID2); + + id = gpio_get_value(EFIKAMX_PCBID0); + id |= gpio_get_value(EFIKAMX_PCBID1) << 1; + id |= gpio_get_value(EFIKAMX_PCBID2) << 2; + + switch (id) { + case 7: + system_rev = 0x11; + break; + case 6: + system_rev = 0x12; + break; + case 5: + system_rev = 0x13; + break; + case 4: + system_rev = 0x14; + break; + default: + system_rev = 0x10; + break; + } + + if ((system_rev == 0x10) + || (system_rev == 0x12) + || (system_rev == 0x14)) { + printk(KERN_WARNING + "EfikaMX: Unsupported board revision 1.%u!\n", + system_rev & 0xf); + } +} + +static struct gpio_led mx51_efikamx_leds[] = { + { + .name = "efikamx:green", + .default_trigger = "default-on", + .gpio = EFIKAMX_GREEN_LED, + }, + { + .name = "efikamx:red", + .default_trigger = "ide-disk", + .gpio = EFIKAMX_RED_LED, + }, + { + .name = "efikamx:blue", + .default_trigger = "mmc0", + .gpio = EFIKAMX_BLUE_LED, + }, +}; + +static struct gpio_led_platform_data mx51_efikamx_leds_data = { + .leds = mx51_efikamx_leds, + .num_leds = ARRAY_SIZE(mx51_efikamx_leds), +}; + +static struct platform_device mx51_efikamx_leds_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &mx51_efikamx_leds_data, + }, +}; + +static struct gpio_keys_button mx51_efikamx_powerkey[] = { + { + .code = KEY_POWER, + .gpio = EFIKAMX_POWER_KEY, + .type = EV_PWR, + .desc = "Power Button (CM)", + .wakeup = 1, + .debounce_interval = 10, /* ms */ + }, +}; + +static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = { + .buttons = mx51_efikamx_powerkey, + .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey), +}; + +static struct mtd_partition mx51_efikamx_spi_nor_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = SZ_256K, + }, + { + .name = "config", + .offset = MTDPART_OFS_APPEND, + .size = SZ_64K, + }, +}; + +static struct flash_platform_data mx51_efikamx_spi_flash_data = { + .name = "spi_flash", + .parts = mx51_efikamx_spi_nor_partitions, + .nr_parts = ARRAY_SIZE(mx51_efikamx_spi_nor_partitions), + .type = "sst25vf032b", +}; + +static struct spi_board_info mx51_efikamx_spi_board_info[] __initdata = { + { + .modalias = "m25p80", + .max_speed_hz = 25000000, + .bus_num = 0, + .chip_select = 1, + .platform_data = &mx51_efikamx_spi_flash_data, + .irq = -1, + }, +}; + +static int mx51_efikamx_spi_cs[] = { + EFIKAMX_SPI_CS0, + EFIKAMX_SPI_CS1, +}; + +static const struct spi_imx_master mx51_efikamx_spi_pdata __initconst = { + .chipselect = mx51_efikamx_spi_cs, + .num_chipselect = ARRAY_SIZE(mx51_efikamx_spi_cs), +}; + +void mx51_efikamx_reset(void) +{ + if (system_rev == 0x11) + gpio_direction_output(EFIKAMX_RESET1_1, 0); + else + gpio_direction_output(EFIKAMX_RESET, 0); +} + static void __init mxc_board_init(void) { mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, ARRAY_SIZE(mx51efikamx_pads)); + mx51_efikamx_board_id(); mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); mxc_init_imx_uart(); + imx51_add_sdhci_esdhc_imx(0, NULL); + + /* on < 1.2 boards both SD controllers are used */ + if (system_rev < 0x12) { + imx51_add_sdhci_esdhc_imx(1, NULL); + mx51_efikamx_leds[2].default_trigger = "mmc1"; + } + + platform_device_register(&mx51_efikamx_leds_device); + imx51_add_gpio_keys(&mx51_efikamx_powerkey_data); + + spi_register_board_info(mx51_efikamx_spi_board_info, + ARRAY_SIZE(mx51_efikamx_spi_board_info)); + imx51_add_ecspi(0, &mx51_efikamx_spi_pdata); + + if (system_rev == 0x11) { + gpio_request(EFIKAMX_RESET1_1, "reset"); + gpio_direction_output(EFIKAMX_RESET1_1, 1); + } else { + gpio_request(EFIKAMX_RESET, "reset"); + gpio_direction_output(EFIKAMX_RESET, 1); + } } static void __init mx51_efikamx_timer_init(void) diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c new file mode 100644 index 0000000..fa97d0d --- /dev/null +++ b/arch/arm/mach-mx5/board-mx53_evk.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/init.h> +#include <linux/clk.h> +#include <mach/common.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx53.h> + +#include "crm_regs.h" +#include "devices-imx53.h" + +static iomux_v3_cfg_t mx53_evk_pads[] = { + MX53_PAD_CSI0_D10__UART1_TXD, + MX53_PAD_CSI0_D11__UART1_RXD, + MX53_PAD_ATA_DIOW__UART1_TXD, + MX53_PAD_ATA_DMACK__UART1_RXD, + + MX53_PAD_ATA_BUFFER_EN__UART2_RXD, + MX53_PAD_ATA_DMARQ__UART2_TXD, + MX53_PAD_ATA_DIOR__UART2_RTS, + MX53_PAD_ATA_INTRQ__UART2_CTS, + + MX53_PAD_ATA_CS_0__UART3_TXD, + MX53_PAD_ATA_CS_1__UART3_RXD, + MX53_PAD_ATA_DA_1__UART3_CTS, + MX53_PAD_ATA_DA_2__UART3_RTS, +}; + +static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static inline void mx53_evk_init_uart(void) +{ + imx53_add_imx_uart(0, &mx53_evk_uart_pdata); + imx53_add_imx_uart(1, &mx53_evk_uart_pdata); + imx53_add_imx_uart(2, &mx53_evk_uart_pdata); +} + +static void __init mx53_evk_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads, + ARRAY_SIZE(mx53_evk_pads)); + mx53_evk_init_uart(); +} + +static void __init mx53_evk_timer_init(void) +{ + mx53_clocks_init(32768, 24000000, 22579200, 0); +} + +static struct sys_timer mx53_evk_timer = { + .init = mx53_evk_timer_init, +}; + +MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") + .map_io = mx53_map_io, + .init_irq = mx53_init_irq, + .init_machine = mx53_evk_board_init, + .timer = &mx53_evk_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 5975edb..785e1a3 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -33,11 +33,15 @@ static struct clk pll1_main_clk; static struct clk pll1_sw_clk; static struct clk pll2_sw_clk; static struct clk pll3_sw_clk; +static struct clk mx53_pll4_sw_clk; static struct clk lp_apm_clk; static struct clk periph_apm_clk; static struct clk ahb_clk; static struct clk ipg_clk; static struct clk usboh3_clk; +static struct clk emi_fast_clk; +static struct clk ipu_clk; +static struct clk mipi_hsc1_clk; #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ @@ -123,7 +127,7 @@ static inline u32 _get_mux(struct clk *parent, struct clk *m0, return -EINVAL; } -static inline void __iomem *_get_pll_base(struct clk *pll) +static inline void __iomem *_mx51_get_pll_base(struct clk *pll) { if (pll == &pll1_main_clk) return MX51_DPLL1_BASE; @@ -137,6 +141,30 @@ static inline void __iomem *_get_pll_base(struct clk *pll) return NULL; } +static inline void __iomem *_mx53_get_pll_base(struct clk *pll) +{ + if (pll == &pll1_main_clk) + return MX53_DPLL1_BASE; + else if (pll == &pll2_sw_clk) + return MX53_DPLL2_BASE; + else if (pll == &pll3_sw_clk) + return MX53_DPLL3_BASE; + else if (pll == &mx53_pll4_sw_clk) + return MX53_DPLL4_BASE; + else + BUG(); + + return NULL; +} + +static inline void __iomem *_get_pll_base(struct clk *pll) +{ + if (cpu_is_mx51()) + return _mx51_get_pll_base(pll); + else + return _mx53_get_pll_base(pll); +} + static unsigned long clk_pll_get_rate(struct clk *clk) { long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; @@ -514,7 +542,10 @@ static int _clk_max_enable(struct clk *clk) /* Handshake with MAX when LPM is entered. */ reg = __raw_readl(MXC_CCM_CLPCR); - reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + if (cpu_is_mx51()) + reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; + else if (cpu_is_mx53()) + reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; __raw_writel(reg, MXC_CCM_CLPCR); return 0; @@ -528,7 +559,10 @@ static void _clk_max_disable(struct clk *clk) /* No Handshake with MAX when LPM is entered as its disabled. */ reg = __raw_readl(MXC_CCM_CLPCR); - reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + if (cpu_is_mx51()) + reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; + else if (cpu_is_mx53()) + reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; __raw_writel(reg, MXC_CCM_CLPCR); } @@ -679,6 +713,19 @@ static unsigned long clk_emi_slow_get_rate(struct clk *clk) return clk_get_rate(clk->parent) / div; } +static unsigned long _clk_ddr_hf_get_rate(struct clk *clk) +{ + unsigned long rate; + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >> + MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1; + rate = clk_get_rate(clk->parent) / div; + + return rate; +} + /* External high frequency clock */ static struct clk ckih_clk = { .get_rate = get_high_reference_clock_rate, @@ -739,6 +786,14 @@ static struct clk pll3_sw_clk = { .disable = _clk_pll_disable, }; +/* PLL4 SW supplies to LVDS Display Bridge(LDB) */ +static struct clk mx53_pll4_sw_clk = { + .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + /* Low-power Audio Playback Mode clock */ static struct clk lp_apm_clk = { .parent = &osc_clk, @@ -763,6 +818,12 @@ static struct clk ahb_clk = { .round_rate = _clk_ahb_round_rate, }; +static struct clk iim_clk = { + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, +}; + /* Main IP interface clock for access to registers */ static struct clk ipg_clk = { .parent = &ahb_clk, @@ -810,6 +871,10 @@ static struct clk kpp_clk = { .id = 0, }; +static struct clk dummy_clk = { + .id = 0, +}; + static struct clk emi_slow_clk = { .parent = &pll2_sw_clk, .enable_reg = MXC_CCM_CCGR5, @@ -819,6 +884,109 @@ static struct clk emi_slow_clk = { .get_rate = clk_emi_slow_get_rate, }; +static int clk_ipu_enable(struct clk *clk) +{ + u32 reg; + + _clk_ccgr_enable(clk); + + /* Enable handshake with IPU when certain clock rates are changed */ + reg = __raw_readl(MXC_CCM_CCDR); + reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + /* Enable handshake with IPU when LPM is entered */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + +static void clk_ipu_disable(struct clk *clk) +{ + u32 reg; + + _clk_ccgr_disable(clk); + + /* Disable handshake with IPU whe dividers are changed */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + /* Disable handshake with IPU when LPM is entered */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + +static struct clk ahbmux1_clk = { + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable_inwait, +}; + +static struct clk ipu_sec_clk = { + .parent = &emi_fast_clk, + .secondary = &ahbmux1_clk, +}; + +static struct clk ddr_hf_clk = { + .parent = &pll1_sw_clk, + .get_rate = _clk_ddr_hf_get_rate, +}; + +static struct clk ddr_clk = { + .parent = &ddr_hf_clk, +}; + +/* clock definitions for MIPI HSC unit which has been removed + * from documentation, but not from hardware + */ +static int _clk_hsc_enable(struct clk *clk) +{ + u32 reg; + + _clk_ccgr_enable(clk); + /* Handshake with IPU when certain clock rates are changed. */ + reg = __raw_readl(MXC_CCM_CCDR); + reg &= ~MXC_CCM_CCDR_HSC_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + +static void _clk_hsc_disable(struct clk *clk) +{ + u32 reg; + + _clk_ccgr_disable(clk); + /* No handshake with HSC as its not enabled. */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_HSC_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + +static struct clk mipi_hsp_clk = { + .parent = &ipu_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_hsc_enable, + .disable = _clk_hsc_disable, + .secondary = &mipi_hsc1_clk, +}; + #define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \ static struct clk name = { \ .id = i, \ @@ -927,6 +1095,41 @@ static struct clk usboh3_clk = { .parent = &pll2_sw_clk, .get_rate = clk_usboh3_get_rate, .set_parent = clk_usboh3_set_parent, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, +}; + +static struct clk usb_ahb_clk = { + .parent = &ipg_clk, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, +}; + +static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + + if (parent == &pll3_sw_clk) + reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET; + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk usb_phy1_clk = { + .parent = &pll3_sw_clk, + .set_parent = clk_usb_phy1_set_parent, + .enable = _clk_ccgr_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .disable = _clk_ccgr_disable, }; /* eCSPI */ @@ -1013,6 +1216,10 @@ DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET, NULL, NULL, &ipg_clk, NULL); DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET, NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk); +DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET, + NULL, NULL, &ipg_clk, NULL); +DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET, + NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk); /* eCSPI */ DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, @@ -1046,6 +1253,23 @@ DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET, DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk); +DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk); +DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk); +DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk); + +/* IPU */ +DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET, + NULL, NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk); + +DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET, + NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait, + &ddr_clk, NULL); + +DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET, + NULL, NULL, &pll3_sw_clk, NULL); +DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET, + NULL, NULL, &pll3_sw_clk, NULL); + #define _REGISTER_CLOCK(d, n, c) \ { \ .dev_id = d, \ @@ -1053,7 +1277,7 @@ DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, .clk = &c, \ }, -static struct clk_lookup lookups[] = { +static struct clk_lookup mx51_lookups[] = { _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) @@ -1063,15 +1287,19 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk) _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) - _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) + _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk) + _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk) _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) - _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) + _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk) + _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk) + _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) + _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) _REGISTER_CLOCK(NULL, "ckih", ckih_clk) _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk) @@ -1082,6 +1310,22 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) + _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) + _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk) + _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk) + _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk) + _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk) + _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) + _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) +}; + +static struct clk_lookup mx53_lookups[] = { + _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) + _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) + _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) + _REGISTER_CLOCK(NULL, "gpt", gpt_clk) + _REGISTER_CLOCK("fec.0", NULL, fec_clk) + _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) }; static void clk_tree_init(void) @@ -1114,14 +1358,22 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, ckih2_reference = ckih2; oscillator_reference = osc; - for (i = 0; i < ARRAY_SIZE(lookups); i++) - clkdev_add(&lookups[i]); + for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++) + clkdev_add(&mx51_lookups[i]); clk_tree_init(); + clk_set_parent(&uart_root_clk, &pll3_sw_clk); clk_enable(&cpu_clk); clk_enable(&main_bus_clk); + clk_enable(&iim_clk); + mx51_revision(); + clk_disable(&iim_clk); + + /* move usb_phy_clk to 24MHz */ + clk_set_parent(&usb_phy1_clk, &osc_clk); + /* set the usboh3_clk parent to pll2_sw_clk */ clk_set_parent(&usboh3_clk, &pll2_sw_clk); @@ -1138,3 +1390,31 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, MX51_MXC_INT_GPT); return 0; } + +int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2) +{ + int i; + + external_low_reference = ckil; + external_high_reference = ckih1; + ckih2_reference = ckih2; + oscillator_reference = osc; + + for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++) + clkdev_add(&mx53_lookups[i]); + + clk_tree_init(); + + clk_enable(&cpu_clk); + clk_enable(&main_bus_clk); + + clk_enable(&iim_clk); + mx53_revision(); + clk_disable(&iim_clk); + + /* System timer */ + mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), + MX53_INT_GPT); + return 0; +} diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index eaacb6e..d40671d 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -20,37 +20,18 @@ static int cpu_silicon_rev = -1; -#define SI_REV 0x48 +#define IIM_SREV 0x24 -static void query_silicon_parameter(void) +static int get_mx51_srev(void) { - void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE); - u32 rev; + void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); + u32 rev = readl(iim_base + IIM_SREV) & 0xff; - if (!rom) { - cpu_silicon_rev = -EINVAL; - return; - } - - rev = readl(rom + SI_REV); - switch (rev) { - case 0x1: - cpu_silicon_rev = MX51_CHIP_REV_1_0; - break; - case 0x2: - cpu_silicon_rev = MX51_CHIP_REV_1_1; - break; - case 0x10: - cpu_silicon_rev = MX51_CHIP_REV_2_0; - break; - case 0x20: - cpu_silicon_rev = MX51_CHIP_REV_3_0; - break; - default: - cpu_silicon_rev = 0; - } - - iounmap(rom); + if (rev == 0x0) + return IMX_CHIP_REVISION_2_0; + else if (rev == 0x10) + return IMX_CHIP_REVISION_3_0; + return 0; } /* @@ -64,7 +45,7 @@ int mx51_revision(void) return -EINVAL; if (cpu_silicon_rev == -1) - query_silicon_parameter(); + cpu_silicon_rev = get_mx51_srev(); return cpu_silicon_rev; } @@ -79,7 +60,10 @@ EXPORT_SYMBOL(mx51_revision); */ static int __init mx51_neon_fixup(void) { - if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) { + if (!cpu_is_mx51()) + return 0; + + if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) { elf_hwcap &= ~HWCAP_NEON; pr_info("Turning off NEON support, detected broken NEON implementation\n"); } @@ -89,29 +73,65 @@ static int __init mx51_neon_fixup(void) late_initcall(mx51_neon_fixup); #endif +static int get_mx53_srev(void) +{ + void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); + u32 rev = readl(iim_base + IIM_SREV) & 0xff; + + if (rev == 0x0) + return IMX_CHIP_REVISION_1_0; + else if (rev == 0x10) + return IMX_CHIP_REVISION_2_0; + return 0; +} + +/* + * Returns: + * the silicon revision of the cpu + * -EINVAL - not a mx53 + */ +int mx53_revision(void) +{ + if (!cpu_is_mx53()) + return -EINVAL; + + if (cpu_silicon_rev == -1) + cpu_silicon_rev = get_mx53_srev(); + + return cpu_silicon_rev; +} +EXPORT_SYMBOL(mx53_revision); + static int __init post_cpu_init(void) { unsigned int reg; void __iomem *base; - if (!cpu_is_mx51()) - return 0; - - base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); - __raw_writel(0x0, base + 0x40); - __raw_writel(0x0, base + 0x44); - __raw_writel(0x0, base + 0x48); - __raw_writel(0x0, base + 0x4C); - reg = __raw_readl(base + 0x50) & 0x00FFFFFF; - __raw_writel(reg, base + 0x50); - - base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); - __raw_writel(0x0, base + 0x40); - __raw_writel(0x0, base + 0x44); - __raw_writel(0x0, base + 0x48); - __raw_writel(0x0, base + 0x4C); - reg = __raw_readl(base + 0x50) & 0x00FFFFFF; - __raw_writel(reg, base + 0x50); + if (cpu_is_mx51() || cpu_is_mx53()) { + if (cpu_is_mx51()) + base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); + else + base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR); + + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + + if (cpu_is_mx51()) + base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); + else + base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR); + + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + } return 0; } diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index c776b9a..b462c22 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -18,6 +18,13 @@ #define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) #define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) +/*MX53*/ +#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR) +#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR) +#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR) +#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) +#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) + /* PLL Register Offsets */ #define MXC_PLL_DP_CTL 0x00 #define MXC_PLL_DP_CONFIG 0x04 @@ -380,7 +387,8 @@ /* Define the bits in register CLPCR */ #define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) #define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) -#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) +#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) +#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) #define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h index 8c50cb5..6302e46 100644 --- a/arch/arm/mach-mx5/devices-imx51.h +++ b/arch/arm/mach-mx5/devices-imx51.h @@ -31,6 +31,11 @@ extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst; #define imx51_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) +extern const struct imx_sdhci_esdhc_imx_data +imx51_sdhci_esdhc_imx_data[] __initconst; +#define imx51_add_sdhci_esdhc_imx(id, pdata) \ + imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata) + extern const struct imx_spi_imx_data imx51_cspi_data __initconst; #define imx51_add_cspi(pdata) \ imx_add_spi_imx(&imx51_cspi_data, pdata) @@ -39,6 +44,6 @@ extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst; #define imx51_add_ecspi(id, pdata) \ imx_add_spi_imx(&imx51_ecspi_data[id], pdata) -extern const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst; -#define imx51_add_esdhc(id, pdata) \ - imx_add_esdhc(&imx51_esdhc_data[id], pdata) +extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst; +#define imx51_add_imx2_wdt(id, pdata) \ + imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h new file mode 100644 index 0000000..9d0ec25 --- /dev/null +++ b/arch/arm/mach-mx5/devices-imx53.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx53.h> +#include <mach/devices-common.h> + +extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst; +#define imx53_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata) diff --git a/arch/arm/mach-mx5/devices-mx50.h b/arch/arm/mach-mx5/devices-mx50.h new file mode 100644 index 0000000..98ab074 --- /dev/null +++ b/arch/arm/mach-mx5/devices-mx50.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/mx50.h> +#include <mach/devices-common.h> + +extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst; +#define imx50_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata) diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 4c7be87..1bda5cb 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -97,19 +97,27 @@ struct platform_device mxc_usbh1_device = { }, }; -static struct resource mxc_wdt_resources[] = { +static struct resource usbh2_resources[] = { { - .start = MX51_WDOG_BASE_ADDR, - .end = MX51_WDOG_BASE_ADDR + SZ_16K - 1, + .start = MX51_OTG_BASE_ADDR + 0x400, + .end = MX51_OTG_BASE_ADDR + 0x400 + 0x1ff, .flags = IORESOURCE_MEM, }, + { + .start = MX51_MXC_INT_USB_H2, + .flags = IORESOURCE_IRQ, + }, }; -struct platform_device mxc_wdt = { - .name = "imx2-wdt", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_wdt_resources), - .resource = mxc_wdt_resources, +struct platform_device mxc_usbh2_device = { + .name = "mxc-ehci", + .id = 2, + .num_resources = ARRAY_SIZE(usbh2_resources), + .resource = usbh2_resources, + .dev = { + .dma_mask = &usb_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, }; static struct resource mxc_kpp_resources[] = { @@ -160,9 +168,36 @@ static struct mxc_gpio_port mxc_gpio_ports[] = { .irq_high = MX51_MXC_INT_GPIO4_HIGH, .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 }, + { + .chip.label = "gpio-4", + .base = MX53_IO_ADDRESS(MX53_GPIO5_BASE_ADDR), + .irq = MX53_INT_GPIO5_LOW, + .irq_high = MX53_INT_GPIO5_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4 + }, + { + .chip.label = "gpio-5", + .base = MX53_IO_ADDRESS(MX53_GPIO6_BASE_ADDR), + .irq = MX53_INT_GPIO6_LOW, + .irq_high = MX53_INT_GPIO6_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 5 + }, + { + .chip.label = "gpio-6", + .base = MX53_IO_ADDRESS(MX53_GPIO7_BASE_ADDR), + .irq = MX53_INT_GPIO7_LOW, + .irq_high = MX53_INT_GPIO7_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 6 + }, }; int __init imx51_register_gpios(void) { + return mxc_gpio_init(mxc_gpio_ports, 4); +} + +int __init imx53_register_gpios(void) +{ return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); } + diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index af1d07c..16891aa 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h @@ -1,6 +1,6 @@ extern struct platform_device mxc_usbdr_host_device; extern struct platform_device mxc_usbh1_device; +extern struct platform_device mxc_usbh2_device; extern struct platform_device mxc_usbdr_udc_device; -extern struct platform_device mxc_wdt; extern struct platform_device mxc_hsi2c_device; extern struct platform_device mxc_keypad_device; diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index a2e6e8c..c96d018 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c @@ -33,12 +33,12 @@ #include "devices-imx51.h" #include "devices.h" -#define MBIMX51_TSC2007_GPIO (2*32 + 30) +#define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30) #define MBIMX51_TSC2007_IRQ (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO) -#define MBIMX51_LED0 (2*32 + 5) -#define MBIMX51_LED1 (2*32 + 6) -#define MBIMX51_LED2 (2*32 + 7) -#define MBIMX51_LED3 (2*32 + 8) +#define MBIMX51_LED0 IMX_GPIO_NR(3, 5) +#define MBIMX51_LED1 IMX_GPIO_NR(3, 6) +#define MBIMX51_LED2 IMX_GPIO_NR(3, 7) +#define MBIMX51_LED3 IMX_GPIO_NR(3, 8) static struct gpio_led mbimx51_leds[] = { { @@ -84,7 +84,7 @@ static struct platform_device *devices[] __initdata = { &mbimx51_leds_gpio, }; -static struct pad_desc mbimx51_pads[] = { +static iomux_v3_cfg_t mbimx51_pads[] = { /* UART2 */ MX51_PAD_UART2_RXD__UART2_RXD, MX51_PAD_UART2_TXD__UART2_TXD, @@ -96,13 +96,13 @@ static struct pad_desc mbimx51_pads[] = { MX51_PAD_KEY_COL5__UART3_CTS, /* TSC2007 IRQ */ - MX51_PAD_NANDF_D10__GPIO_3_30, + MX51_PAD_NANDF_D10__GPIO3_30, /* LEDS */ - MX51_PAD_DISPB2_SER_DIN__GPIO_3_5, - MX51_PAD_DISPB2_SER_DIO__GPIO_3_6, - MX51_PAD_DISPB2_SER_CLK__GPIO_3_7, - MX51_PAD_DISPB2_SER_RS__GPIO_3_8, + MX51_PAD_DISPB2_SER_DIN__GPIO3_5, + MX51_PAD_DISPB2_SER_DIO__GPIO3_6, + MX51_PAD_DISPB2_SER_CLK__GPIO3_7, + MX51_PAD_DISPB2_SER_RS__GPIO3_8, /* KPP */ MX51_PAD_KEY_ROW0__KEY_ROW0, @@ -217,6 +217,6 @@ void __init eukrea_mbimx51_baseboard_init(void) i2c_register_board_info(1, mbimx51_i2c_devices, ARRAY_SIZE(mbimx51_i2c_devices)); - imx51_add_esdhc(0, NULL); - imx51_add_esdhc(1, NULL); + imx51_add_sdhci_esdhc_imx(0, NULL); + imx51_add_sdhci_esdhc_imx(1, NULL); } diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c index 2b48f51..c372a43 100644 --- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c @@ -45,14 +45,13 @@ #include "devices-imx51.h" #include "devices.h" -#define MBIMXSD_GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, \ - MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) - -static struct pad_desc eukrea_mbimxsd_pads[] = { +static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { /* LED */ - MX51_PAD_NANDF_D10__GPIO_3_30, + MX51_PAD_NANDF_D10__GPIO3_30, /* SWITCH */ - MBIMXSD_GPIO_3_31, + _MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | + PAD_CTL_PKE | PAD_CTL_SRE_FAST | + PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), /* UART2 */ MX51_PAD_UART2_RXD__UART2_RXD, MX51_PAD_UART2_TXD__UART2_TXD, @@ -70,8 +69,8 @@ static struct pad_desc eukrea_mbimxsd_pads[] = { MX51_PAD_SD1_DATA3__SD1_DATA3, }; -#define GPIO_LED1 (2 * 32 + 30) -#define GPIO_SWITCH1 (2 * 32 + 31) +#define GPIO_LED1 IMX_GPIO_NR(3, 30) +#define GPIO_SWITCH1 IMX_GPIO_NR(3, 31) static struct gpio_led eukrea_mbimxsd_leds[] = { { @@ -149,7 +148,7 @@ void __init eukrea_mbimxsd51_baseboard_init(void) imx51_add_imx_uart(1, NULL); imx51_add_imx_uart(2, &uart_pdata); - imx51_add_esdhc(0, NULL); + imx51_add_sdhci_esdhc_imx(0, NULL); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c new file mode 100644 index 0000000..8c6540e --- /dev/null +++ b/arch/arm/mach-mx5/mm-mx50.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Create static mapping between physical to virtual memory. + */ + +#include <linux/mm.h> +#include <linux/init.h> + +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/iomux-v3.h> + +/* + * Define the MX50 memory map. + */ +static struct map_desc mx50_io_desc[] __initdata = { + imx_map_entry(MX50, TZIC, MT_DEVICE), + imx_map_entry(MX50, SPBA0, MT_DEVICE), + imx_map_entry(MX50, AIPS1, MT_DEVICE), + imx_map_entry(MX50, AIPS2, MT_DEVICE), +}; + +/* + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory mappings + * for the IO modules. + */ +void __init mx50_map_io(void) +{ + mxc_set_cpu_type(MXC_CPU_MX50); + mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); + mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); + iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc)); +} + +int imx50_register_gpios(void); + +void __init mx50_init_irq(void) +{ + tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); + imx50_register_gpios(); +} diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index bc3f30d..457f9f9 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -23,33 +23,21 @@ /* * Define the MX51 memory map. */ -static struct map_desc mxc_io_desc[] __initdata = { - { - .virtual = MX51_IRAM_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR), - .length = MX51_IRAM_SIZE, - .type = MT_DEVICE - }, { - .virtual = MX51_DEBUG_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR), - .length = MX51_DEBUG_SIZE, - .type = MT_DEVICE - }, { - .virtual = MX51_AIPS1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR), - .length = MX51_AIPS1_SIZE, - .type = MT_DEVICE - }, { - .virtual = MX51_SPBA0_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR), - .length = MX51_SPBA0_SIZE, - .type = MT_DEVICE - }, { - .virtual = MX51_AIPS2_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR), - .length = MX51_AIPS2_SIZE, - .type = MT_DEVICE - }, +static struct map_desc mx51_io_desc[] __initdata = { + imx_map_entry(MX51, IRAM, MT_DEVICE), + imx_map_entry(MX51, DEBUG, MT_DEVICE), + imx_map_entry(MX51, AIPS1, MT_DEVICE), + imx_map_entry(MX51, SPBA0, MT_DEVICE), + imx_map_entry(MX51, AIPS2, MT_DEVICE), +}; + +/* + * Define the MX53 memory map. + */ +static struct map_desc mx53_io_desc[] __initdata = { + imx_map_entry(MX53, AIPS1, MT_DEVICE), + imx_map_entry(MX53, SPBA0, MT_DEVICE), + imx_map_entry(MX53, AIPS2, MT_DEVICE), }; /* @@ -61,8 +49,16 @@ void __init mx51_map_io(void) { mxc_set_cpu_type(MXC_CPU_MX51); mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR)); - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); + mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); + iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); +} + +void __init mx53_map_io(void) +{ + mxc_set_cpu_type(MXC_CPU_MX53); + mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); + mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR)); + iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); } int imx51_register_gpios(void); @@ -72,7 +68,7 @@ void __init mx51_init_irq(void) unsigned long tzic_addr; void __iomem *tzic_virt; - if (mx51_revision() < MX51_CHIP_REV_2_0) + if (mx51_revision() < IMX_CHIP_REVISION_2_0) tzic_addr = MX51_TZIC_BASE_ADDR_TO1; else tzic_addr = MX51_TZIC_BASE_ADDR; @@ -84,3 +80,20 @@ void __init mx51_init_irq(void) tzic_init_irq(tzic_virt); imx51_register_gpios(); } + +int imx53_register_gpios(void); + +void __init mx53_init_irq(void) +{ + unsigned long tzic_addr; + void __iomem *tzic_virt; + + tzic_addr = MX53_TZIC_BASE_ADDR; + + tzic_virt = ioremap(tzic_addr, SZ_16K); + if (!tzic_virt) + panic("unable to map TZIC interrupt controller\n"); + + tzic_init_irq(tzic_virt); + imx53_register_gpios(); +} diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c index aeccfd75..7652c30 100644 --- a/arch/arm/mach-mxc91231/mm.c +++ b/arch/arm/mach-mxc91231/mm.c @@ -27,48 +27,15 @@ /* * This structure defines the MXC memory map. */ -static struct map_desc mxc_io_desc[] __initdata = { - { - .virtual = MXC91231_L2CC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_L2CC_BASE_ADDR), - .length = MXC91231_L2CC_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_X_MEMC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_X_MEMC_BASE_ADDR), - .length = MXC91231_X_MEMC_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_ROMP_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_ROMP_BASE_ADDR), - .length = MXC91231_ROMP_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_AVIC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_AVIC_BASE_ADDR), - .length = MXC91231_AVIC_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_AIPS1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_AIPS1_BASE_ADDR), - .length = MXC91231_AIPS1_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_SPBA0_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_SPBA0_BASE_ADDR), - .length = MXC91231_SPBA0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_SPBA1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_SPBA1_BASE_ADDR), - .length = MXC91231_SPBA1_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MXC91231_AIPS2_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MXC91231_AIPS2_BASE_ADDR), - .length = MXC91231_AIPS2_SIZE, - .type = MT_DEVICE, - }, +static struct map_desc mxc91231_io_desc[] __initdata = { + imx_map_entry(MXC91231, L2CC, MT_DEVICE), + imx_map_entry(MXC91231, X_MEMC, MT_DEVICE), + imx_map_entry(MXC91231, ROMP, MT_DEVICE), + imx_map_entry(MXC91231, AVIC, MT_DEVICE), + imx_map_entry(MXC91231, AIPS1, MT_DEVICE), + imx_map_entry(MXC91231, SPBA0, MT_DEVICE), + imx_map_entry(MXC91231, SPBA1, MT_DEVICE), + imx_map_entry(MXC91231, AIPS2, MT_DEVICE), }; /* @@ -80,7 +47,7 @@ void __init mxc91231_map_io(void) { mxc_set_cpu_type(MXC_CPU_MXC91231); - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); + iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc)); } int mxc91231_register_gpios(void); diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig new file mode 100644 index 0000000..c4ac7b4 --- /dev/null +++ b/arch/arm/mach-mxs/Kconfig @@ -0,0 +1,34 @@ +if ARCH_MXS + +source "arch/arm/mach-mxs/devices/Kconfig" + +config SOC_IMX23 + bool + select CPU_ARM926T + +config SOC_IMX28 + bool + select CPU_ARM926T + +comment "MXS platforms:" + +config MACH_MX23EVK + bool "Support MX23EVK Platform" + select SOC_IMX23 + select MXS_HAVE_PLATFORM_DUART + default y + help + Include support for MX23EVK platform. This includes specific + configurations for the board and its peripherals. + +config MACH_MX28EVK + bool "Support MX28EVK Platform" + select SOC_IMX28 + select MXS_HAVE_PLATFORM_DUART + select MXS_HAVE_PLATFORM_FEC + default y + help + Include support for MX28EVK platform. This includes specific + configurations for the board and its peripherals. + +endif diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile new file mode 100644 index 0000000..39d3f9c --- /dev/null +++ b/arch/arm/mach-mxs/Makefile @@ -0,0 +1,10 @@ +# Common support +obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o + +obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o +obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o + +obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o +obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o + +obj-y += devices/ diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot new file mode 100644 index 0000000..eb541e0 --- /dev/null +++ b/arch/arm/mach-mxs/Makefile.boot @@ -0,0 +1 @@ +zreladdr-y := 0x40008000 diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c new file mode 100644 index 0000000..8f5a19a --- /dev/null +++ b/arch/arm/mach-mxs/clock-mx23.c @@ -0,0 +1,526 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/mm.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/jiffies.h> + +#include <asm/clkdev.h> +#include <asm/div64.h> + +#include <mach/mx23.h> +#include <mach/common.h> +#include <mach/clock.h> + +#include "regs-clkctrl-mx23.h" + +#define CLKCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR) +#define DIGCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR) + +#define PARENT_RATE_SHIFT 8 + +static int _raw_clk_enable(struct clk *clk) +{ + u32 reg; + + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg &= ~(1 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + } + + return 0; +} + +static void _raw_clk_disable(struct clk *clk) +{ + u32 reg; + + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + } +} + +/* + * ref_xtal_clk + */ +static unsigned long ref_xtal_clk_get_rate(struct clk *clk) +{ + return 24000000; +} + +static struct clk ref_xtal_clk = { + .get_rate = ref_xtal_clk_get_rate, +}; + +/* + * pll_clk + */ +static unsigned long pll_clk_get_rate(struct clk *clk) +{ + return 480000000; +} + +static int pll_clk_enable(struct clk *clk) +{ + __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER | + BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET); + + /* Only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer + * and is incorrect (excessive). Per definition of the PLLCTRL0 + * POWER field, waiting at least 10us. + */ + udelay(10); + + return 0; +} + +static void pll_clk_disable(struct clk *clk) +{ + __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER | + BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR); +} + +static struct clk pll_clk = { + .get_rate = pll_clk_get_rate, + .enable = pll_clk_enable, + .disable = pll_clk_disable, + .parent = &ref_xtal_clk, +}; + +/* + * ref_clk + */ +#define _CLK_GET_RATE_REF(name, sr, ss) \ +static unsigned long name##_get_rate(struct clk *clk) \ +{ \ + unsigned long parent_rate; \ + u32 reg, div; \ + \ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \ + div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \ + parent_rate = clk_get_rate(clk->parent); \ + \ + return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \ + div, PARENT_RATE_SHIFT); \ +} + +_CLK_GET_RATE_REF(ref_cpu_clk, FRAC, CPU) +_CLK_GET_RATE_REF(ref_emi_clk, FRAC, EMI) +_CLK_GET_RATE_REF(ref_pix_clk, FRAC, PIX) +_CLK_GET_RATE_REF(ref_io_clk, FRAC, IO) + +#define _DEFINE_CLOCK_REF(name, er, es) \ + static struct clk name = { \ + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \ + .enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \ + .get_rate = name##_get_rate, \ + .enable = _raw_clk_enable, \ + .disable = _raw_clk_disable, \ + .parent = &pll_clk, \ + } + +_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC, CPU); +_DEFINE_CLOCK_REF(ref_emi_clk, FRAC, EMI); +_DEFINE_CLOCK_REF(ref_pix_clk, FRAC, PIX); +_DEFINE_CLOCK_REF(ref_io_clk, FRAC, IO); + +/* + * General clocks + * + * clk_get_rate + */ +static unsigned long rtc_clk_get_rate(struct clk *clk) +{ + /* ref_xtal_clk is implemented as the only parent */ + return clk_get_rate(clk->parent) / 768; +} + +static unsigned long clk32k_clk_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 750; +} + +#define _CLK_GET_RATE(name, rs) \ +static unsigned long name##_get_rate(struct clk *clk) \ +{ \ + u32 reg, div; \ + \ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ + \ + if (clk->parent == &ref_xtal_clk) \ + div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \ + BP_CLKCTRL_##rs##_DIV_XTAL; \ + else \ + div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \ + BP_CLKCTRL_##rs##_DIV_##rs; \ + \ + if (!div) \ + return -EINVAL; \ + \ + return clk_get_rate(clk->parent) / div; \ +} + +_CLK_GET_RATE(cpu_clk, CPU) +_CLK_GET_RATE(emi_clk, EMI) + +#define _CLK_GET_RATE1(name, rs) \ +static unsigned long name##_get_rate(struct clk *clk) \ +{ \ + u32 reg, div; \ + \ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ + div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \ + \ + if (!div) \ + return -EINVAL; \ + \ + return clk_get_rate(clk->parent) / div; \ +} + +_CLK_GET_RATE1(hbus_clk, HBUS) +_CLK_GET_RATE1(xbus_clk, XBUS) +_CLK_GET_RATE1(ssp_clk, SSP) +_CLK_GET_RATE1(gpmi_clk, GPMI) +_CLK_GET_RATE1(lcdif_clk, PIX) + +#define _CLK_GET_RATE_STUB(name) \ +static unsigned long name##_get_rate(struct clk *clk) \ +{ \ + return clk_get_rate(clk->parent); \ +} + +_CLK_GET_RATE_STUB(uart_clk) +_CLK_GET_RATE_STUB(audio_clk) +_CLK_GET_RATE_STUB(pwm_clk) + +/* + * clk_set_rate + */ +static int cpu_clk_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, bm_busy, div_max, d, f, div, frac; + unsigned long diff, parent_rate, calc_rate; + int i; + + parent_rate = clk_get_rate(clk->parent); + + if (clk->parent == &ref_xtal_clk) { + div_max = BM_CLKCTRL_CPU_DIV_XTAL >> BP_CLKCTRL_CPU_DIV_XTAL; + bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL; + div = DIV_ROUND_UP(parent_rate, rate); + if (div == 0 || div > div_max) + return -EINVAL; + } else { + div_max = BM_CLKCTRL_CPU_DIV_CPU >> BP_CLKCTRL_CPU_DIV_CPU; + bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU; + rate >>= PARENT_RATE_SHIFT; + parent_rate >>= PARENT_RATE_SHIFT; + diff = parent_rate; + div = frac = 1; + for (d = 1; d <= div_max; d++) { + f = parent_rate * 18 / d / rate; + if ((parent_rate * 18 / d) % rate) + f++; + if (f < 18 || f > 35) + continue; + + calc_rate = parent_rate * 18 / f / d; + if (calc_rate > rate) + continue; + + if (rate - calc_rate < diff) { + frac = f; + div = d; + diff = rate - calc_rate; + } + + if (diff == 0) + break; + } + + if (diff == parent_rate) + return -EINVAL; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); + reg &= ~BM_CLKCTRL_FRAC_CPUFRAC; + reg |= frac; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); + } + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); + reg &= ~BM_CLKCTRL_CPU_DIV_CPU; + reg |= div << BP_CLKCTRL_CPU_DIV_CPU; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); + + for (i = 10000; i; i--) + if (!(__raw_readl(CLKCTRL_BASE_ADDR + + HW_CLKCTRL_CPU) & bm_busy)) + break; + if (!i) { + pr_err("%s: divider writing timeout\n", __func__); + return -ETIMEDOUT; + } + + return 0; +} + +#define _CLK_SET_RATE(name, dr) \ +static int name##_set_rate(struct clk *clk, unsigned long rate) \ +{ \ + u32 reg, div_max, div; \ + unsigned long parent_rate; \ + int i; \ + \ + parent_rate = clk_get_rate(clk->parent); \ + div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \ + \ + div = DIV_ROUND_UP(parent_rate, rate); \ + if (div == 0 || div > div_max) \ + return -EINVAL; \ + \ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \ + reg &= ~BM_CLKCTRL_##dr##_DIV; \ + reg |= div << BP_CLKCTRL_##dr##_DIV; \ + if (reg | (1 << clk->enable_shift)) { \ + pr_err("%s: clock is gated\n", __func__); \ + return -EINVAL; \ + } \ + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \ + \ + for (i = 10000; i; i--) \ + if (!(__raw_readl(CLKCTRL_BASE_ADDR + \ + HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \ + break; \ + if (!i) { \ + pr_err("%s: divider writing timeout\n", __func__); \ + return -ETIMEDOUT; \ + } \ + \ + return 0; \ +} + +_CLK_SET_RATE(xbus_clk, XBUS) +_CLK_SET_RATE(ssp_clk, SSP) +_CLK_SET_RATE(gpmi_clk, GPMI) +_CLK_SET_RATE(lcdif_clk, PIX) + +#define _CLK_SET_RATE_STUB(name) \ +static int name##_set_rate(struct clk *clk, unsigned long rate) \ +{ \ + return -EINVAL; \ +} + +_CLK_SET_RATE_STUB(emi_clk) +_CLK_SET_RATE_STUB(uart_clk) +_CLK_SET_RATE_STUB(audio_clk) +_CLK_SET_RATE_STUB(pwm_clk) +_CLK_SET_RATE_STUB(clk32k_clk) + +/* + * clk_set_parent + */ +#define _CLK_SET_PARENT(name, bit) \ +static int name##_set_parent(struct clk *clk, struct clk *parent) \ +{ \ + if (parent != clk->parent) { \ + __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \ + HW_CLKCTRL_CLKSEQ_TOG); \ + clk->parent = parent; \ + } \ + \ + return 0; \ +} + +_CLK_SET_PARENT(cpu_clk, CPU) +_CLK_SET_PARENT(emi_clk, EMI) +_CLK_SET_PARENT(ssp_clk, SSP) +_CLK_SET_PARENT(gpmi_clk, GPMI) +_CLK_SET_PARENT(lcdif_clk, PIX) + +#define _CLK_SET_PARENT_STUB(name) \ +static int name##_set_parent(struct clk *clk, struct clk *parent) \ +{ \ + if (parent != clk->parent) \ + return -EINVAL; \ + else \ + return 0; \ +} + +_CLK_SET_PARENT_STUB(uart_clk) +_CLK_SET_PARENT_STUB(audio_clk) +_CLK_SET_PARENT_STUB(pwm_clk) +_CLK_SET_PARENT_STUB(clk32k_clk) + +/* + * clk definition + */ +static struct clk cpu_clk = { + .get_rate = cpu_clk_get_rate, + .set_rate = cpu_clk_set_rate, + .set_parent = cpu_clk_set_parent, + .parent = &ref_cpu_clk, +}; + +static struct clk hbus_clk = { + .get_rate = hbus_clk_get_rate, + .parent = &cpu_clk, +}; + +static struct clk xbus_clk = { + .get_rate = xbus_clk_get_rate, + .set_rate = xbus_clk_set_rate, + .parent = &ref_xtal_clk, +}; + +static struct clk rtc_clk = { + .get_rate = rtc_clk_get_rate, + .parent = &ref_xtal_clk, +}; + +/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */ +static struct clk usb_clk = { + .enable_reg = DIGCTRL_BASE_ADDR, + .enable_shift = 2, + .enable = _raw_clk_enable, + .disable = _raw_clk_disable, + .parent = &pll_clk, +}; + +#define _DEFINE_CLOCK(name, er, es, p) \ + static struct clk name = { \ + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \ + .enable_shift = BP_CLKCTRL_##er##_##es, \ + .get_rate = name##_get_rate, \ + .set_rate = name##_set_rate, \ + .set_parent = name##_set_parent, \ + .enable = _raw_clk_enable, \ + .disable = _raw_clk_disable, \ + .parent = p, \ + } + +_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk); +_DEFINE_CLOCK(ssp_clk, SSP, CLKGATE, &ref_xtal_clk); +_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk); +_DEFINE_CLOCK(lcdif_clk, PIX, CLKGATE, &ref_xtal_clk); +_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk); +_DEFINE_CLOCK(audio_clk, XTAL, FILT_CLK24M_GATE, &ref_xtal_clk); +_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk); +_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk); + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = d, \ + .con_id = n, \ + .clk = &c, \ + }, + +static struct clk_lookup lookups[] = { + _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk) + _REGISTER_CLOCK("rtc", NULL, rtc_clk) + _REGISTER_CLOCK(NULL, "hclk", hbus_clk) + _REGISTER_CLOCK(NULL, "xclk", xbus_clk) + _REGISTER_CLOCK(NULL, "usb", usb_clk) + _REGISTER_CLOCK(NULL, "audio", audio_clk) + _REGISTER_CLOCK(NULL, "pwm", pwm_clk) +}; + +static int clk_misc_init(void) +{ + u32 reg; + int i; + + /* Fix up parent per register setting */ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ? + &ref_xtal_clk : &ref_cpu_clk; + emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ? + &ref_xtal_clk : &ref_emi_clk; + ssp_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ? + &ref_xtal_clk : &ref_io_clk; + gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ? + &ref_xtal_clk : &ref_io_clk; + lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) ? + &ref_xtal_clk : &ref_pix_clk; + + /* Use int div over frac when both are available */ + __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR); + __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR); + __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR); + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP); + reg &= ~BM_CLKCTRL_SSP_DIV_FRAC_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP); + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); + reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX); + reg &= ~BM_CLKCTRL_PIX_DIV_FRAC_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX); + + /* + * Set safe hbus clock divider. A divider of 3 ensure that + * the Vddd voltage required for the cpu clock is sufficiently + * high for the hbus clock. + */ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + reg &= BM_CLKCTRL_HBUS_DIV; + reg |= 3 << BP_CLKCTRL_HBUS_DIV; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + + for (i = 10000; i; i--) + if (!(__raw_readl(CLKCTRL_BASE_ADDR + + HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_BUSY)) + break; + if (!i) { + pr_err("%s: divider writing timeout\n", __func__); + return -ETIMEDOUT; + } + + /* Gate off cpu clock in WFI for power saving */ + __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); + + return 0; +} + +int __init mx23_clocks_init(void) +{ + clk_misc_init(); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0); + + return 0; +} diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c new file mode 100644 index 0000000..74e2103 --- /dev/null +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -0,0 +1,734 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/mm.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/jiffies.h> + +#include <asm/clkdev.h> +#include <asm/div64.h> + +#include <mach/mx28.h> +#include <mach/common.h> +#include <mach/clock.h> + +#include "regs-clkctrl-mx28.h" + +#define CLKCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR) +#define DIGCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR) + +#define PARENT_RATE_SHIFT 8 + +static struct clk pll2_clk; +static struct clk cpu_clk; +static struct clk emi_clk; +static struct clk saif0_clk; +static struct clk saif1_clk; +static struct clk clk32k_clk; + +static int _raw_clk_enable(struct clk *clk) +{ + u32 reg; + + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg &= ~(1 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + } + + return 0; +} + +static void _raw_clk_disable(struct clk *clk) +{ + u32 reg; + + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + } +} + +/* + * ref_xtal_clk + */ +static unsigned long ref_xtal_clk_get_rate(struct clk *clk) +{ + return 24000000; +} + +static struct clk ref_xtal_clk = { + .get_rate = ref_xtal_clk_get_rate, +}; + +/* + * pll_clk + */ +static unsigned long pll0_clk_get_rate(struct clk *clk) +{ + return 480000000; +} + +static unsigned long pll1_clk_get_rate(struct clk *clk) +{ + return 480000000; +} + +static unsigned long pll2_clk_get_rate(struct clk *clk) +{ + return 50000000; +} + +#define _CLK_ENABLE_PLL(name, r, g) \ +static int name##_enable(struct clk *clk) \ +{ \ + __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \ + CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \ + udelay(10); \ + \ + if (clk == &pll2_clk) \ + __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \ + CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \ + else \ + __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \ + CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \ + \ + return 0; \ +} + +_CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS) +_CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS) +_CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE) + +#define _CLK_DISABLE_PLL(name, r, g) \ +static void name##_disable(struct clk *clk) \ +{ \ + __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \ + CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \ + \ + if (clk == &pll2_clk) \ + __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \ + CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \ + else \ + __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \ + CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \ + \ +} + +_CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS) +_CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS) +_CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE) + +#define _DEFINE_CLOCK_PLL(name) \ + static struct clk name = { \ + .get_rate = name##_get_rate, \ + .enable = name##_enable, \ + .disable = name##_disable, \ + .parent = &ref_xtal_clk, \ + } + +_DEFINE_CLOCK_PLL(pll0_clk); +_DEFINE_CLOCK_PLL(pll1_clk); +_DEFINE_CLOCK_PLL(pll2_clk); + +/* + * ref_clk + */ +#define _CLK_GET_RATE_REF(name, sr, ss) \ +static unsigned long name##_get_rate(struct clk *clk) \ +{ \ + unsigned long parent_rate; \ + u32 reg, div; \ + \ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \ + div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \ + parent_rate = clk_get_rate(clk->parent); \ + \ + return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \ + div, PARENT_RATE_SHIFT); \ +} + +_CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU) +_CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI) +_CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0) +_CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1) +_CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX) +_CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI) + +#define _DEFINE_CLOCK_REF(name, er, es) \ + static struct clk name = { \ + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \ + .enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \ + .get_rate = name##_get_rate, \ + .enable = _raw_clk_enable, \ + .disable = _raw_clk_disable, \ + .parent = &pll0_clk, \ + } + +_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU); +_DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI); +_DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0); +_DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1); +_DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX); +_DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI); + +/* + * General clocks + * + * clk_get_rate + */ +static unsigned long lradc_clk_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 16; +} + +static unsigned long rtc_clk_get_rate(struct clk *clk) +{ + /* ref_xtal_clk is implemented as the only parent */ + return clk_get_rate(clk->parent) / 768; +} + +static unsigned long clk32k_clk_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 750; +} + +static unsigned long spdif_clk_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 4; +} + +#define _CLK_GET_RATE(name, rs) \ +static unsigned long name##_get_rate(struct clk *clk) \ +{ \ + u32 reg, div; \ + \ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ + \ + if (clk->parent == &ref_xtal_clk) \ + div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \ + BP_CLKCTRL_##rs##_DIV_XTAL; \ + else \ + div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \ + BP_CLKCTRL_##rs##_DIV_##rs; \ + \ + if (!div) \ + return -EINVAL; \ + \ + return clk_get_rate(clk->parent) / div; \ +} + +_CLK_GET_RATE(cpu_clk, CPU) +_CLK_GET_RATE(emi_clk, EMI) + +#define _CLK_GET_RATE1(name, rs) \ +static unsigned long name##_get_rate(struct clk *clk) \ +{ \ + u32 reg, div; \ + \ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ + div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \ + \ + if (!div) \ + return -EINVAL; \ + \ + if (clk == &saif0_clk || clk == &saif1_clk) \ + return clk_get_rate(clk->parent) >> 16 * div; \ + else \ + return clk_get_rate(clk->parent) / div; \ +} + +_CLK_GET_RATE1(hbus_clk, HBUS) +_CLK_GET_RATE1(xbus_clk, XBUS) +_CLK_GET_RATE1(ssp0_clk, SSP0) +_CLK_GET_RATE1(ssp1_clk, SSP1) +_CLK_GET_RATE1(ssp2_clk, SSP2) +_CLK_GET_RATE1(ssp3_clk, SSP3) +_CLK_GET_RATE1(gpmi_clk, GPMI) +_CLK_GET_RATE1(lcdif_clk, DIS_LCDIF) +_CLK_GET_RATE1(saif0_clk, SAIF0) +_CLK_GET_RATE1(saif1_clk, SAIF1) + +#define _CLK_GET_RATE_STUB(name) \ +static unsigned long name##_get_rate(struct clk *clk) \ +{ \ + return clk_get_rate(clk->parent); \ +} + +_CLK_GET_RATE_STUB(uart_clk) +_CLK_GET_RATE_STUB(pwm_clk) +_CLK_GET_RATE_STUB(can0_clk) +_CLK_GET_RATE_STUB(can1_clk) +_CLK_GET_RATE_STUB(fec_clk) + +/* + * clk_set_rate + */ +/* fool compiler */ +#define BM_CLKCTRL_CPU_DIV 0 +#define BP_CLKCTRL_CPU_DIV 0 +#define BM_CLKCTRL_CPU_BUSY 0 + +#define _CLK_SET_RATE(name, dr, fr, fs) \ +static int name##_set_rate(struct clk *clk, unsigned long rate) \ +{ \ + u32 reg, bm_busy, div_max, d, f, div, frac; \ + unsigned long diff, parent_rate, calc_rate; \ + int i; \ + \ + parent_rate = clk_get_rate(clk->parent); \ + div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \ + bm_busy = BM_CLKCTRL_##dr##_BUSY; \ + \ + if (clk->parent == &ref_xtal_clk) { \ + div = DIV_ROUND_UP(parent_rate, rate); \ + if (clk == &cpu_clk) { \ + div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \ + BP_CLKCTRL_CPU_DIV_XTAL; \ + bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL; \ + } \ + if (div == 0 || div > div_max) \ + return -EINVAL; \ + } else { \ + rate >>= PARENT_RATE_SHIFT; \ + parent_rate >>= PARENT_RATE_SHIFT; \ + diff = parent_rate; \ + div = frac = 1; \ + if (clk == &cpu_clk) { \ + div_max = BM_CLKCTRL_CPU_DIV_CPU >> \ + BP_CLKCTRL_CPU_DIV_CPU; \ + bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU; \ + } \ + for (d = 1; d <= div_max; d++) { \ + f = parent_rate * 18 / d / rate; \ + if ((parent_rate * 18 / d) % rate) \ + f++; \ + if (f < 18 || f > 35) \ + continue; \ + \ + calc_rate = parent_rate * 18 / f / d; \ + if (calc_rate > rate) \ + continue; \ + \ + if (rate - calc_rate < diff) { \ + frac = f; \ + div = d; \ + diff = rate - calc_rate; \ + } \ + \ + if (diff == 0) \ + break; \ + } \ + \ + if (diff == parent_rate) \ + return -EINVAL; \ + \ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \ + reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \ + reg |= frac; \ + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \ + } \ + \ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \ + if (clk == &cpu_clk) { \ + reg &= ~BM_CLKCTRL_CPU_DIV_CPU; \ + reg |= div << BP_CLKCTRL_CPU_DIV_CPU; \ + } else { \ + reg &= ~BM_CLKCTRL_##dr##_DIV; \ + reg |= div << BP_CLKCTRL_##dr##_DIV; \ + if (reg | (1 << clk->enable_shift)) { \ + pr_err("%s: clock is gated\n", __func__); \ + return -EINVAL; \ + } \ + } \ + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); \ + \ + for (i = 10000; i; i--) \ + if (!(__raw_readl(CLKCTRL_BASE_ADDR + \ + HW_CLKCTRL_##dr) & bm_busy)) \ + break; \ + if (!i) { \ + pr_err("%s: divider writing timeout\n", __func__); \ + return -ETIMEDOUT; \ + } \ + \ + return 0; \ +} + +_CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU) +_CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0) +_CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0) +_CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1) +_CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1) +_CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX) +_CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI) + +#define _CLK_SET_RATE1(name, dr) \ +static int name##_set_rate(struct clk *clk, unsigned long rate) \ +{ \ + u32 reg, div_max, div; \ + unsigned long parent_rate; \ + int i; \ + \ + parent_rate = clk_get_rate(clk->parent); \ + div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \ + \ + div = DIV_ROUND_UP(parent_rate, rate); \ + if (div == 0 || div > div_max) \ + return -EINVAL; \ + \ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \ + reg &= ~BM_CLKCTRL_##dr##_DIV; \ + reg |= div << BP_CLKCTRL_##dr##_DIV; \ + if (reg | (1 << clk->enable_shift)) { \ + pr_err("%s: clock is gated\n", __func__); \ + return -EINVAL; \ + } \ + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \ + \ + for (i = 10000; i; i--) \ + if (!(__raw_readl(CLKCTRL_BASE_ADDR + \ + HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \ + break; \ + if (!i) { \ + pr_err("%s: divider writing timeout\n", __func__); \ + return -ETIMEDOUT; \ + } \ + \ + return 0; \ +} + +_CLK_SET_RATE1(xbus_clk, XBUS) + +/* saif clock uses 16 bits frac div */ +#define _CLK_SET_RATE_SAIF(name, rs) \ +static int name##_set_rate(struct clk *clk, unsigned long rate) \ +{ \ + u16 div; \ + u32 reg; \ + u64 lrate; \ + unsigned long parent_rate; \ + int i; \ + \ + parent_rate = clk_get_rate(clk->parent); \ + if (rate > parent_rate) \ + return -EINVAL; \ + \ + lrate = (u64)rate << 16; \ + do_div(lrate, parent_rate); \ + div = (u16)lrate; \ + \ + if (!div) \ + return -EINVAL; \ + \ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ + reg &= ~BM_CLKCTRL_##rs##_DIV; \ + reg |= div << BP_CLKCTRL_##rs##_DIV; \ + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ + \ + for (i = 10000; i; i--) \ + if (!(__raw_readl(CLKCTRL_BASE_ADDR + \ + HW_CLKCTRL_##rs) & BM_CLKCTRL_##rs##_BUSY)) \ + break; \ + if (!i) { \ + pr_err("%s: divider writing timeout\n", __func__); \ + return -ETIMEDOUT; \ + } \ + \ + return 0; \ +} + +_CLK_SET_RATE_SAIF(saif0_clk, SAIF0) +_CLK_SET_RATE_SAIF(saif1_clk, SAIF1) + +#define _CLK_SET_RATE_STUB(name) \ +static int name##_set_rate(struct clk *clk, unsigned long rate) \ +{ \ + return -EINVAL; \ +} + +_CLK_SET_RATE_STUB(emi_clk) +_CLK_SET_RATE_STUB(uart_clk) +_CLK_SET_RATE_STUB(pwm_clk) +_CLK_SET_RATE_STUB(spdif_clk) +_CLK_SET_RATE_STUB(clk32k_clk) +_CLK_SET_RATE_STUB(can0_clk) +_CLK_SET_RATE_STUB(can1_clk) +_CLK_SET_RATE_STUB(fec_clk) + +/* + * clk_set_parent + */ +#define _CLK_SET_PARENT(name, bit) \ +static int name##_set_parent(struct clk *clk, struct clk *parent) \ +{ \ + if (parent != clk->parent) { \ + __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \ + HW_CLKCTRL_CLKSEQ_TOG); \ + clk->parent = parent; \ + } \ + \ + return 0; \ +} + +_CLK_SET_PARENT(cpu_clk, CPU) +_CLK_SET_PARENT(emi_clk, EMI) +_CLK_SET_PARENT(ssp0_clk, SSP0) +_CLK_SET_PARENT(ssp1_clk, SSP1) +_CLK_SET_PARENT(ssp2_clk, SSP2) +_CLK_SET_PARENT(ssp3_clk, SSP3) +_CLK_SET_PARENT(lcdif_clk, DIS_LCDIF) +_CLK_SET_PARENT(gpmi_clk, GPMI) +_CLK_SET_PARENT(saif0_clk, SAIF0) +_CLK_SET_PARENT(saif1_clk, SAIF1) + +#define _CLK_SET_PARENT_STUB(name) \ +static int name##_set_parent(struct clk *clk, struct clk *parent) \ +{ \ + if (parent != clk->parent) \ + return -EINVAL; \ + else \ + return 0; \ +} + +_CLK_SET_PARENT_STUB(pwm_clk) +_CLK_SET_PARENT_STUB(uart_clk) +_CLK_SET_PARENT_STUB(clk32k_clk) +_CLK_SET_PARENT_STUB(spdif_clk) +_CLK_SET_PARENT_STUB(fec_clk) +_CLK_SET_PARENT_STUB(can0_clk) +_CLK_SET_PARENT_STUB(can1_clk) + +/* + * clk definition + */ +static struct clk cpu_clk = { + .get_rate = cpu_clk_get_rate, + .set_rate = cpu_clk_set_rate, + .set_parent = cpu_clk_set_parent, + .parent = &ref_cpu_clk, +}; + +static struct clk hbus_clk = { + .get_rate = hbus_clk_get_rate, + .parent = &cpu_clk, +}; + +static struct clk xbus_clk = { + .get_rate = xbus_clk_get_rate, + .set_rate = xbus_clk_set_rate, + .parent = &ref_xtal_clk, +}; + +static struct clk lradc_clk = { + .get_rate = lradc_clk_get_rate, + .parent = &clk32k_clk, +}; + +static struct clk rtc_clk = { + .get_rate = rtc_clk_get_rate, + .parent = &ref_xtal_clk, +}; + +/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */ +static struct clk usb0_clk = { + .enable_reg = DIGCTRL_BASE_ADDR, + .enable_shift = 2, + .enable = _raw_clk_enable, + .disable = _raw_clk_disable, + .parent = &pll0_clk, +}; + +static struct clk usb1_clk = { + .enable_reg = DIGCTRL_BASE_ADDR, + .enable_shift = 16, + .enable = _raw_clk_enable, + .disable = _raw_clk_disable, + .parent = &pll1_clk, +}; + +#define _DEFINE_CLOCK(name, er, es, p) \ + static struct clk name = { \ + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \ + .enable_shift = BP_CLKCTRL_##er##_##es, \ + .get_rate = name##_get_rate, \ + .set_rate = name##_set_rate, \ + .set_parent = name##_set_parent, \ + .enable = _raw_clk_enable, \ + .disable = _raw_clk_disable, \ + .parent = p, \ + } + +_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk); +_DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk); +_DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk); +_DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk); +_DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk); +_DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk); +_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk); +_DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk); +_DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk); +_DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk); +_DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk); +_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk); +_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk); +_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk); +_DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk); +_DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk); + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = d, \ + .con_id = n, \ + .clk = &c, \ + }, + +static struct clk_lookup lookups[] = { + _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk) + _REGISTER_CLOCK("fec.0", NULL, fec_clk) + _REGISTER_CLOCK("rtc", NULL, rtc_clk) + _REGISTER_CLOCK("pll2", NULL, pll2_clk) + _REGISTER_CLOCK(NULL, "hclk", hbus_clk) + _REGISTER_CLOCK(NULL, "xclk", xbus_clk) + _REGISTER_CLOCK(NULL, "can0", can0_clk) + _REGISTER_CLOCK(NULL, "can1", can1_clk) + _REGISTER_CLOCK(NULL, "usb0", usb0_clk) + _REGISTER_CLOCK(NULL, "usb1", usb1_clk) + _REGISTER_CLOCK(NULL, "pwm", pwm_clk) + _REGISTER_CLOCK(NULL, "lradc", lradc_clk) + _REGISTER_CLOCK(NULL, "spdif", spdif_clk) +}; + +static int clk_misc_init(void) +{ + u32 reg; + int i; + + /* Fix up parent per register setting */ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ? + &ref_xtal_clk : &ref_cpu_clk; + emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ? + &ref_xtal_clk : &ref_emi_clk; + ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ? + &ref_xtal_clk : &ref_io0_clk; + ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ? + &ref_xtal_clk : &ref_io0_clk; + ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ? + &ref_xtal_clk : &ref_io1_clk; + ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ? + &ref_xtal_clk : &ref_io1_clk; + lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ? + &ref_xtal_clk : &ref_pix_clk; + gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ? + &ref_xtal_clk : &ref_gpmi_clk; + saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ? + &ref_xtal_clk : &pll0_clk; + saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ? + &ref_xtal_clk : &pll0_clk; + + /* Use int div over frac when both are available */ + __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR); + __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR); + __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR); + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0); + reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0); + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1); + reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1); + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2); + reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2); + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3); + reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3); + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); + reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF); + reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF); + + /* SAIF has to use frac div for functional operation */ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0); + reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0); + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1); + reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1); + + /* + * Set safe hbus clock divider. A divider of 3 ensure that + * the Vddd voltage required for the cpu clock is sufficiently + * high for the hbus clock. + */ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + reg &= BM_CLKCTRL_HBUS_DIV; + reg |= 3 << BP_CLKCTRL_HBUS_DIV; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + + for (i = 10000; i; i--) + if (!(__raw_readl(CLKCTRL_BASE_ADDR + + HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_ASM_BUSY)) + break; + if (!i) { + pr_err("%s: divider writing timeout\n", __func__); + return -ETIMEDOUT; + } + + /* Gate off cpu clock in WFI for power saving */ + __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); + + /* Extra fec clock setting */ + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); + reg &= ~BM_CLKCTRL_ENET_SLEEP; + reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); + + return 0; +} + +int __init mx28_clocks_init(void) +{ + clk_misc_init(); + + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + + mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0); + + return 0; +} diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c new file mode 100644 index 0000000..e7d2269 --- /dev/null +++ b/arch/arm/mach-mxs/clock.c @@ -0,0 +1,200 @@ +/* + * Based on arch/arm/plat-omap/clock.c + * + * Copyright (C) 2004 - 2005 Nokia corporation + * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> + * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +/* #define DEBUG */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/platform_device.h> +#include <linux/proc_fs.h> +#include <linux/semaphore.h> +#include <linux/string.h> + +#include <mach/clock.h> + +static LIST_HEAD(clocks); +static DEFINE_MUTEX(clocks_mutex); + +/*------------------------------------------------------------------------- + * Standard clock functions defined in include/linux/clk.h + *-------------------------------------------------------------------------*/ + +static void __clk_disable(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return; + WARN_ON(!clk->usecount); + + if (!(--clk->usecount)) { + if (clk->disable) + clk->disable(clk); + __clk_disable(clk->parent); + __clk_disable(clk->secondary); + } +} + +static int __clk_enable(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + if (clk->usecount++ == 0) { + __clk_enable(clk->parent); + __clk_enable(clk->secondary); + + if (clk->enable) + clk->enable(clk); + } + return 0; +} + +/* This function increments the reference count on the clock and enables the + * clock if not already enabled. The parent clock tree is recursively enabled + */ +int clk_enable(struct clk *clk) +{ + int ret = 0; + + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + mutex_lock(&clocks_mutex); + ret = __clk_enable(clk); + mutex_unlock(&clocks_mutex); + + return ret; +} +EXPORT_SYMBOL(clk_enable); + +/* This function decrements the reference count on the clock and disables + * the clock when reference count is 0. The parent clock tree is + * recursively disabled + */ +void clk_disable(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return; + + mutex_lock(&clocks_mutex); + __clk_disable(clk); + mutex_unlock(&clocks_mutex); +} +EXPORT_SYMBOL(clk_disable); + +/* Retrieve the *current* clock rate. If the clock itself + * does not provide a special calculation routine, ask + * its parent and so on, until one is able to return + * a valid clock rate + */ +unsigned long clk_get_rate(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return 0UL; + + if (clk->get_rate) + return clk->get_rate(clk); + + return clk_get_rate(clk->parent); +} +EXPORT_SYMBOL(clk_get_rate); + +/* Round the requested clock rate to the nearest supported + * rate that is less than or equal to the requested rate. + * This is dependent on the clock's current parent. + */ +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk == NULL || IS_ERR(clk) || !clk->round_rate) + return 0; + + return clk->round_rate(clk, rate); +} +EXPORT_SYMBOL(clk_round_rate); + +/* Set the clock to the requested clock rate. The rate must + * match a supported rate exactly based on what clk_round_rate returns + */ +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EINVAL; + + if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0) + return ret; + + mutex_lock(&clocks_mutex); + ret = clk->set_rate(clk, rate); + mutex_unlock(&clocks_mutex); + + return ret; +} +EXPORT_SYMBOL(clk_set_rate); + +/* Set the clock's parent to another clock source */ +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + struct clk *old; + + if (clk == NULL || IS_ERR(clk) || parent == NULL || + IS_ERR(parent) || clk->set_parent == NULL) + return ret; + + if (clk->usecount) + clk_enable(parent); + + mutex_lock(&clocks_mutex); + ret = clk->set_parent(clk, parent); + if (ret == 0) { + old = clk->parent; + clk->parent = parent; + } else { + old = parent; + } + mutex_unlock(&clocks_mutex); + + if (clk->usecount) + clk_disable(old); + + return ret; +} +EXPORT_SYMBOL(clk_set_parent); + +/* Retrieve the clock's parent clock source */ +struct clk *clk_get_parent(struct clk *clk) +{ + struct clk *ret = NULL; + + if (clk == NULL || IS_ERR(clk)) + return ret; + + return clk->parent; +} +EXPORT_SYMBOL(clk_get_parent); diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h new file mode 100644 index 0000000..d0f49fc --- /dev/null +++ b/arch/arm/mach-mxs/devices-mx23.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx23.h> +#include <mach/devices-common.h> + +extern const struct mxs_duart_data mx23_duart_data __initconst; +#define mx23_add_duart() \ + mxs_add_duart(&mx23_duart_data) diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h new file mode 100644 index 0000000..00b736c --- /dev/null +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx28.h> +#include <mach/devices-common.h> + +extern const struct mxs_duart_data mx28_duart_data __initconst; +#define mx28_add_duart() \ + mxs_add_duart(&mx28_duart_data) + +extern const struct mxs_fec_data mx28_fec_data[] __initconst; +#define mx28_add_fec(id, pdata) \ + mxs_add_fec(&mx28_fec_data[id], pdata) diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c new file mode 100644 index 0000000..6b60f02 --- /dev/null +++ b/arch/arm/mach-mxs/devices.c @@ -0,0 +1,75 @@ +/* + * Copyright 2008 Sascha Hauer, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + */ + +#include <linux/kernel.h> +#include <linux/slab.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <mach/common.h> + +struct platform_device *__init mxs_add_platform_device_dmamask( + const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data, u64 dmamask) +{ + int ret = -ENOMEM; + struct platform_device *pdev; + + pdev = platform_device_alloc(name, id); + if (!pdev) + goto err; + + if (dmamask) { + /* + * This memory isn't freed when the device is put, + * I don't have a nice idea for that though. Conceptually + * dma_mask in struct device should not be a pointer. + * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 + */ + pdev->dev.dma_mask = + kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); + if (!pdev->dev.dma_mask) + /* ret is still -ENOMEM; */ + goto err; + + *pdev->dev.dma_mask = dmamask; + pdev->dev.coherent_dma_mask = dmamask; + } + + if (res) { + ret = platform_device_add_resources(pdev, res, num_resources); + if (ret) + goto err; + } + + if (data) { + ret = platform_device_add_data(pdev, data, size_data); + if (ret) + goto err; + } + + ret = platform_device_add(pdev); + if (ret) { +err: + platform_device_put(pdev); + return ERR_PTR(ret); + } + + return pdev; +} diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig new file mode 100644 index 0000000..a35a2dc --- /dev/null +++ b/arch/arm/mach-mxs/devices/Kconfig @@ -0,0 +1,5 @@ +config MXS_HAVE_PLATFORM_DUART + bool + +config MXS_HAVE_PLATFORM_FEC + bool diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile new file mode 100644 index 0000000..4b5266a --- /dev/null +++ b/arch/arm/mach-mxs/devices/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_MXS_HAVE_PLATFORM_DUART) += platform-duart.o +obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o diff --git a/arch/arm/mach-mxs/devices/platform-duart.c b/arch/arm/mach-mxs/devices/platform-duart.c new file mode 100644 index 0000000..2fe0df5 --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-duart.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/mx23.h> +#include <mach/mx28.h> +#include <mach/devices-common.h> + +#define mxs_duart_data_entry(soc) \ + { \ + .iobase = soc ## _DUART_BASE_ADDR, \ + .irq = soc ## _INT_DUART, \ + } + +#ifdef CONFIG_SOC_IMX23 +const struct mxs_duart_data mx23_duart_data __initconst = + mxs_duart_data_entry(MX23); +#endif + +#ifdef CONFIG_SOC_IMX28 +const struct mxs_duart_data mx28_duart_data __initconst = + mxs_duart_data_entry(MX28); +#endif + +struct platform_device *__init mxs_add_duart( + const struct mxs_duart_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return mxs_add_platform_device("mxs-duart", 0, res, ARRAY_SIZE(res), + NULL, 0); +} diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c new file mode 100644 index 0000000..c08168c --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-fec.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/mx28.h> +#include <mach/devices-common.h> + +#define mxs_fec_data_entry_single(soc, _id) \ + { \ + .id = _id, \ + .iobase = soc ## _ENET_MAC ## _id ## _BASE_ADDR, \ + .irq = soc ## _INT_ENET_MAC ## _id, \ + } + +#define mxs_fec_data_entry(soc, _id) \ + [_id] = mxs_fec_data_entry_single(soc, _id) + +#ifdef CONFIG_SOC_IMX28 +const struct mxs_fec_data mx28_fec_data[] __initconst = { +#define mx28_fec_data_entry(_id) \ + mxs_fec_data_entry(MX28, _id) + mx28_fec_data_entry(0), + mx28_fec_data_entry(1), +}; +#endif + +struct platform_device *__init mxs_add_fec( + const struct mxs_fec_data *data, + const struct fec_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return mxs_add_platform_device("fec", data->id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c new file mode 100644 index 0000000..d7ad7a6 --- /dev/null +++ b/arch/arm/mach-mxs/gpio.c @@ -0,0 +1,325 @@ +/* + * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * Based on code from Freescale, + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <mach/mx23.h> +#include <mach/mx28.h> +#include <asm-generic/bug.h> + +#include "gpio.h" + +static struct mxs_gpio_port *mxs_gpio_ports; +static int gpio_table_size; + +#define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10) +#define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10) +#define PINCTRL_DOE(n) ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10) +#define PINCTRL_PIN2IRQ(n) ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10) +#define PINCTRL_IRQEN(n) ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10) +#define PINCTRL_IRQLEV(n) ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10) +#define PINCTRL_IRQPOL(n) ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10) +#define PINCTRL_IRQSTAT(n) ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10) + +#define GPIO_INT_FALL_EDGE 0x0 +#define GPIO_INT_LOW_LEV 0x1 +#define GPIO_INT_RISE_EDGE 0x2 +#define GPIO_INT_HIGH_LEV 0x3 +#define GPIO_INT_LEV_MASK (1 << 0) +#define GPIO_INT_POL_MASK (1 << 1) + +/* Note: This driver assumes 32 GPIOs are handled in one register */ + +static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index) +{ + __mxs_clrl(1 << index, port->base + PINCTRL_IRQSTAT(port->id)); +} + +static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index, + int enable) +{ + if (enable) { + __mxs_setl(1 << index, port->base + PINCTRL_IRQEN(port->id)); + __mxs_setl(1 << index, port->base + PINCTRL_PIN2IRQ(port->id)); + } else { + __mxs_clrl(1 << index, port->base + PINCTRL_IRQEN(port->id)); + } +} + +static void mxs_gpio_ack_irq(u32 irq) +{ + u32 gpio = irq_to_gpio(irq); + clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f); +} + +static void mxs_gpio_mask_irq(u32 irq) +{ + u32 gpio = irq_to_gpio(irq); + set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0); +} + +static void mxs_gpio_unmask_irq(u32 irq) +{ + u32 gpio = irq_to_gpio(irq); + set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1); +} + +static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset); + +static int mxs_gpio_set_irq_type(u32 irq, u32 type) +{ + u32 gpio = irq_to_gpio(irq); + u32 pin_mask = 1 << (gpio & 31); + struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32]; + void __iomem *pin_addr; + int edge; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + edge = GPIO_INT_RISE_EDGE; + break; + case IRQ_TYPE_EDGE_FALLING: + edge = GPIO_INT_FALL_EDGE; + break; + case IRQ_TYPE_LEVEL_LOW: + edge = GPIO_INT_LOW_LEV; + break; + case IRQ_TYPE_LEVEL_HIGH: + edge = GPIO_INT_HIGH_LEV; + break; + default: + return -EINVAL; + } + + /* set level or edge */ + pin_addr = port->base + PINCTRL_IRQLEV(port->id); + if (edge & GPIO_INT_LEV_MASK) + __mxs_setl(pin_mask, pin_addr); + else + __mxs_clrl(pin_mask, pin_addr); + + /* set polarity */ + pin_addr = port->base + PINCTRL_IRQPOL(port->id); + if (edge & GPIO_INT_POL_MASK) + __mxs_setl(pin_mask, pin_addr); + else + __mxs_clrl(pin_mask, pin_addr); + + clear_gpio_irqstatus(port, gpio & 0x1f); + + return 0; +} + +/* MXS has one interrupt *per* gpio port */ +static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 irq_stat; + struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq); + u32 gpio_irq_no_base = port->virtual_irq_start; + + irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) & + __raw_readl(port->base + PINCTRL_IRQEN(port->id)); + + while (irq_stat != 0) { + int irqoffset = fls(irq_stat) - 1; + generic_handle_irq(gpio_irq_no_base + irqoffset); + irq_stat &= ~(1 << irqoffset); + } +} + +/* + * Set interrupt number "irq" in the GPIO as a wake-up source. + * While system is running, all registered GPIO interrupts need to have + * wake-up enabled. When system is suspended, only selected GPIO interrupts + * need to have wake-up enabled. + * @param irq interrupt source number + * @param enable enable as wake-up if equal to non-zero + * @return This function returns 0 on success. + */ +static int mxs_gpio_set_wake_irq(u32 irq, u32 enable) +{ + u32 gpio = irq_to_gpio(irq); + u32 gpio_idx = gpio & 0x1f; + struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32]; + + if (enable) { + if (port->irq_high && (gpio_idx >= 16)) + enable_irq_wake(port->irq_high); + else + enable_irq_wake(port->irq); + } else { + if (port->irq_high && (gpio_idx >= 16)) + disable_irq_wake(port->irq_high); + else + disable_irq_wake(port->irq); + } + + return 0; +} + +static struct irq_chip gpio_irq_chip = { + .ack = mxs_gpio_ack_irq, + .mask = mxs_gpio_mask_irq, + .unmask = mxs_gpio_unmask_irq, + .set_type = mxs_gpio_set_irq_type, + .set_wake = mxs_gpio_set_wake_irq, +}; + +static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset, + int dir) +{ + struct mxs_gpio_port *port = + container_of(chip, struct mxs_gpio_port, chip); + void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id); + + if (dir) + __mxs_setl(1 << offset, pin_addr); + else + __mxs_clrl(1 << offset, pin_addr); +} + +static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct mxs_gpio_port *port = + container_of(chip, struct mxs_gpio_port, chip); + + return (__raw_readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1; +} + +static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct mxs_gpio_port *port = + container_of(chip, struct mxs_gpio_port, chip); + void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id); + + if (value) + __mxs_setl(1 << offset, pin_addr); + else + __mxs_clrl(1 << offset, pin_addr); +} + +static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct mxs_gpio_port *port = + container_of(chip, struct mxs_gpio_port, chip); + + return port->virtual_irq_start + offset; +} + +static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + mxs_set_gpio_direction(chip, offset, 0); + return 0; +} + +static int mxs_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + mxs_gpio_set(chip, offset, value); + mxs_set_gpio_direction(chip, offset, 1); + return 0; +} + +int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt) +{ + int i, j; + + /* save for local usage */ + mxs_gpio_ports = port; + gpio_table_size = cnt; + + pr_info("MXS GPIO hardware\n"); + + for (i = 0; i < cnt; i++) { + /* disable the interrupt and clear the status */ + __raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i)); + __raw_writel(0, port[i].base + PINCTRL_IRQEN(i)); + + /* clear address has to be used to clear IRQSTAT bits */ + __mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i)); + + for (j = port[i].virtual_irq_start; + j < port[i].virtual_irq_start + 32; j++) { + set_irq_chip(j, &gpio_irq_chip); + set_irq_handler(j, handle_level_irq); + set_irq_flags(j, IRQF_VALID); + } + + /* setup one handler for each entry */ + set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler); + set_irq_data(port[i].irq, &port[i]); + + /* register gpio chip */ + port[i].chip.direction_input = mxs_gpio_direction_input; + port[i].chip.direction_output = mxs_gpio_direction_output; + port[i].chip.get = mxs_gpio_get; + port[i].chip.set = mxs_gpio_set; + port[i].chip.to_irq = mxs_gpio_to_irq; + port[i].chip.base = i * 32; + port[i].chip.ngpio = 32; + + /* its a serious configuration bug when it fails */ + BUG_ON(gpiochip_add(&port[i].chip) < 0); + } + + return 0; +} + +#define DEFINE_MXS_GPIO_PORT(soc, _id) \ + { \ + .chip.label = "gpio-" #_id, \ + .id = _id, \ + .irq = soc ## _INT_GPIO ## _id, \ + .base = soc ## _IO_ADDRESS( \ + soc ## _PINCTRL ## _BASE_ADDR), \ + .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \ + } + +#define DEFINE_REGISTER_FUNCTION(prefix) \ +int __init prefix ## _register_gpios(void) \ +{ \ + return mxs_gpio_init(prefix ## _gpio_ports, \ + ARRAY_SIZE(prefix ## _gpio_ports)); \ +} + +#ifdef CONFIG_SOC_IMX23 +static struct mxs_gpio_port mx23_gpio_ports[] = { + DEFINE_MXS_GPIO_PORT(MX23, 0), + DEFINE_MXS_GPIO_PORT(MX23, 1), + DEFINE_MXS_GPIO_PORT(MX23, 2), +}; +DEFINE_REGISTER_FUNCTION(mx23) +#endif + +#ifdef CONFIG_SOC_IMX28 +static struct mxs_gpio_port mx28_gpio_ports[] = { + DEFINE_MXS_GPIO_PORT(MX28, 0), + DEFINE_MXS_GPIO_PORT(MX28, 1), + DEFINE_MXS_GPIO_PORT(MX28, 2), + DEFINE_MXS_GPIO_PORT(MX28, 3), + DEFINE_MXS_GPIO_PORT(MX28, 4), +}; +DEFINE_REGISTER_FUNCTION(mx28) +#endif diff --git a/arch/arm/mach-mxs/gpio.h b/arch/arm/mach-mxs/gpio.h new file mode 100644 index 0000000..005bb06 --- /dev/null +++ b/arch/arm/mach-mxs/gpio.h @@ -0,0 +1,34 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MXS_GPIO_H__ +#define __MXS_GPIO_H__ + +struct mxs_gpio_port { + void __iomem *base; + int id; + int irq; + int irq_high; + int virtual_irq_start; + struct gpio_chip chip; +}; + +int mxs_gpio_init(struct mxs_gpio_port*, int); + +#endif /* __MXS_GPIO_H__ */ diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c new file mode 100644 index 0000000..5dd43ba --- /dev/null +++ b/arch/arm/mach-mxs/icoll.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <mach/mxs.h> +#include <mach/common.h> + +#define HW_ICOLL_VECTOR 0x0000 +#define HW_ICOLL_LEVELACK 0x0010 +#define HW_ICOLL_CTRL 0x0020 +#define HW_ICOLL_INTERRUPTn_SET(n) (0x0124 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_CLR(n) (0x0128 + (n) * 0x10) +#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 + +static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR); + +static void icoll_ack_irq(unsigned int irq) +{ + /* + * The Interrupt Collector is able to prioritize irqs. + * Currently only level 0 is used. So acking can use + * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally. + */ + __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0, + icoll_base + HW_ICOLL_LEVELACK); +} + +static void icoll_mask_irq(unsigned int irq) +{ + __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, + icoll_base + HW_ICOLL_INTERRUPTn_CLR(irq)); +} + +static void icoll_unmask_irq(unsigned int irq) +{ + __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, + icoll_base + HW_ICOLL_INTERRUPTn_SET(irq)); +} + +static struct irq_chip mxs_icoll_chip = { + .ack = icoll_ack_irq, + .mask = icoll_mask_irq, + .unmask = icoll_unmask_irq, +}; + +void __init icoll_init_irq(void) +{ + int i; + + /* + * Interrupt Collector reset, which initializes the priority + * for each irq to level 0. + */ + mxs_reset_block(icoll_base + HW_ICOLL_CTRL); + + for (i = 0; i < MXS_INTERNAL_IRQS; i++) { + set_irq_chip(i, &mxs_icoll_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } +} diff --git a/arch/arm/mach-mxs/include/mach/clkdev.h b/arch/arm/mach-mxs/include/mach/clkdev.h new file mode 100644 index 0000000..3a8f2e3 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __MACH_MXS_CLKDEV_H__ +#define __MACH_MXS_CLKDEV_H__ + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/mach-mxs/include/mach/clock.h b/arch/arm/mach-mxs/include/mach/clock.h new file mode 100644 index 0000000..041e276 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/clock.h @@ -0,0 +1,64 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_MXS_CLOCK_H__ +#define __MACH_MXS_CLOCK_H__ + +#ifndef __ASSEMBLY__ +#include <linux/list.h> + +struct module; + +struct clk { + int id; + /* Source clock this clk depends on */ + struct clk *parent; + /* Secondary clock to enable/disable with this clock */ + struct clk *secondary; + /* Reference count of clock enable/disable */ + __s8 usecount; + /* Register bit position for clock's enable/disable control. */ + u8 enable_shift; + /* Register address for clock's enable/disable control. */ + void __iomem *enable_reg; + u32 flags; + /* get the current clock rate (always a fresh value) */ + unsigned long (*get_rate) (struct clk *); + /* Function ptr to set the clock to a new rate. The rate must match a + supported rate returned from round_rate. Leave blank if clock is not + programmable */ + int (*set_rate) (struct clk *, unsigned long); + /* Function ptr to round the requested clock rate to the nearest + supported rate that is less than or equal to the requested rate. */ + unsigned long (*round_rate) (struct clk *, unsigned long); + /* Function ptr to enable the clock. Leave blank if clock can not + be gated. */ + int (*enable) (struct clk *); + /* Function ptr to disable the clock. Leave blank if clock can not + be gated. */ + void (*disable) (struct clk *); + /* Function ptr to set the parent clock of the clock. */ + int (*set_parent) (struct clk *, struct clk *); +}; + +int clk_register(struct clk *clk); +void clk_unregister(struct clk *clk); + +#endif /* __ASSEMBLY__ */ +#endif /* __MACH_MXS_CLOCK_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h new file mode 100644 index 0000000..59133eb --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/common.h @@ -0,0 +1,31 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_MXS_COMMON_H__ +#define __MACH_MXS_COMMON_H__ + +struct clk; + +extern int mxs_reset_block(void __iomem *); +extern void mxs_timer_init(struct clk *, int); + +extern int mx23_register_gpios(void); +extern int mx23_clocks_init(void); +extern void mx23_map_io(void); +extern void mx23_init_irq(void); + +extern int mx28_register_gpios(void); +extern int mx28_clocks_init(void); +extern void mx28_map_io(void); +extern void mx28_init_irq(void); + +extern void icoll_init_irq(void); + +#endif /* __MACH_MXS_COMMON_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/debug-macro.S b/arch/arm/mach-mxs/include/mach/debug-macro.S new file mode 100644 index 0000000..79650a1 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/debug-macro.S @@ -0,0 +1,38 @@ +/* arch/arm/mach-mxs/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <mach/mx23.h> +#include <mach/mx28.h> + +#ifdef CONFIG_SOC_IMX23 +#ifdef UART_PADDR +#error "CONFIG_DEBUG_LL is incompatible with multiple archs" +#endif +#define UART_PADDR MX23_DUART_BASE_ADDR +#endif + +#ifdef CONFIG_SOC_IMX28 +#ifdef UART_PADDR +#error "CONFIG_DEBUG_LL is incompatible with multiple archs" +#endif +#define UART_PADDR MX28_DUART_BASE_ADDR +#endif + +#define UART_VADDR MXS_IO_ADDRESS(UART_PADDR) + + .macro addruart, rp, rv + ldr \rp, =UART_PADDR @ physical + ldr \rv, =UART_VADDR @ virtual + .endm + +#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h new file mode 100644 index 0000000..3da48d4 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/devices-common.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/init.h> + +struct platform_device *mxs_add_platform_device_dmamask( + const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data, u64 dmamask); + +static inline struct platform_device *mxs_add_platform_device( + const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data) +{ + return mxs_add_platform_device_dmamask( + name, id, res, num_resources, data, size_data, 0); +} + +/* duart */ +struct mxs_duart_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init mxs_add_duart( + const struct mxs_duart_data *data); + +/* fec */ +#include <linux/fec.h> +struct mxs_fec_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init mxs_add_fec( + const struct mxs_fec_data *data, + const struct fec_platform_data *pdata); diff --git a/arch/arm/mach-mxs/include/mach/entry-macro.S b/arch/arm/mach-mxs/include/mach/entry-macro.S new file mode 100644 index 0000000..9f0da12 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/entry-macro.S @@ -0,0 +1,41 @@ +/* + * Low-level IRQ helper macros for Freescale MXS-based + * + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <mach/mxs.h> + +#define MXS_ICOLL_VBASE MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR) +#define HW_ICOLL_STAT_OFFSET 0x70 + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqnr, [\base, #HW_ICOLL_STAT_OFFSET] + cmp \irqnr, #0x7F + strne \irqnr, [\base] + moveqs \irqnr, #0 + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =MXS_ICOLL_VBASE + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h new file mode 100644 index 0000000..828cccc --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/gpio.h @@ -0,0 +1,35 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_MXS_GPIO_H__ +#define __MACH_MXS_GPIO_H__ + +#include <asm-generic/gpio.h> + +#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) + +/* use gpiolib dispatchers */ +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + +#define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START) + +#endif /* __MACH_MXS_GPIO_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/hardware.h b/arch/arm/mach-mxs/include/mach/hardware.h new file mode 100644 index 0000000..53e89a0 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/hardware.h @@ -0,0 +1,29 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_MXS_HARDWARE_H__ +#define __MACH_MXS_HARDWARE_H__ + +#ifdef __ASSEMBLER__ +#define IOMEM(addr) (addr) +#else +#define IOMEM(addr) ((void __force __iomem *)(addr)) +#endif + +#endif /* __MACH_MXS_HARDWARE_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/io.h b/arch/arm/mach-mxs/include/mach/io.h new file mode 100644 index 0000000..289b722 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/io.h @@ -0,0 +1,22 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_MXS_IO_H__ +#define __MACH_MXS_IO_H__ + +/* Allow IO space to be anywhere in the memory */ +#define IO_SPACE_LIMIT 0xffffffff + +/* io address mapping macro */ +#define __io(a) __typesafe_io(a) + +#define __mem_pci(a) (a) + +#endif /* __MACH_MXS_IO_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h new file mode 100644 index 0000000..94e5dd8 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/iomux-mx23.h @@ -0,0 +1,355 @@ +/* + * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MACH_IOMUX_MX23_H__ +#define __MACH_IOMUX_MX23_H__ + +#include <mach/iomux.h> + +/* + * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> + * See also iomux.h + * + * BANK PIN MUX + */ +/* MUXSEL_0 */ +#define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) +#define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) +#define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) +#define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) +#define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0) +#define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0) +#define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0) + +#define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) +#define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) +#define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) +#define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) +#define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) +#define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) +#define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) +#define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) +#define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) +#define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) +#define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) +#define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) +#define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) +#define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) +#define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) + +#define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) +#define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) +#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) +#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) +#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) +#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) +#define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) +#define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) +#define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) +#define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) +#define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0) +#define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0) +#define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) +#define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) +#define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) +#define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0) +#define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0) +#define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0) +#define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0) + +#define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) +#define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) +#define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) +#define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) +#define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) +#define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0) +#define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) +#define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) + +/* MUXSEL_1 */ +#define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) +#define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) +#define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) +#define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) +#define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1) +#define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1) +#define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1) + +#define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1) +#define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1) +#define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1) +#define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1) +#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) +#define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) +#define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) +#define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) +#define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) +#define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) +#define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) +#define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) +#define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) + +#define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1) +#define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1) +#define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) +#define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) +#define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1) + +/* MUXSEL_2 */ +#define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) +#define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2) +#define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) +#define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) +#define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2) +#define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2) +#define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2) +#define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2) + +#define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) +#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) +#define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) +#define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2) +#define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2) +#define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) +#define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) + +#define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2) +#define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2) +#define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2) +#define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2) +#define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2) +#define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2) +#define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2) +#define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2) +#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) + +/* MUXSEL_GPIO */ +#define MX23_PAD_GPMI_D00__GPO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D01__GPO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D02__GPO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D03__GPO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D04__GPO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D05__GPO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D06__GPO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D07__GPO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D08__GPO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D09__GPO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D10__GPO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D11__GPO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D12__GPO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D13__GPO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D14__GPO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_D15__GPO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_CLE__GPO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_ALE__GPO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_CE2N__GPO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDY0__GPO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDY1__GPO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDY2__GPO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDY3__GPO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_WPN__GPO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_WRN__GPO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_RDN__GPO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) +#define MX23_PAD_AUART1_CTS__GPO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) +#define MX23_PAD_AUART1_RTS__GPO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) +#define MX23_PAD_AUART1_RX__GPO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) +#define MX23_PAD_AUART1_TX__GPO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) +#define MX23_PAD_I2C_SCL__GPO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) +#define MX23_PAD_I2C_SDA__GPO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) + +#define MX23_PAD_LCD_D00__GPO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D01__GPO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D02__GPO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D03__GPO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D04__GPO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D05__GPO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D06__GPO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D07__GPO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D08__GPO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D09__GPO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D10__GPO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D11__GPO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D12__GPO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D13__GPO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D14__GPO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D15__GPO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D16__GPO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_D17__GPO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_RESET__GPO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_RS__GPO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_WR__GPO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_CS__GPO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_DOTCK__GPO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_ENABLE__GPO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_HSYNC__GPO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) +#define MX23_PAD_LCD_VSYNC__GPO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM0__GPO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM1__GPO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM2__GPO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM3__GPO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) +#define MX23_PAD_PWM4__GPO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) + +#define MX23_PAD_SSP1_CMD__GPO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DETECT__GPO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DATA0__GPO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DATA1__GPO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DATA2__GPO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_DATA3__GPO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) +#define MX23_PAD_SSP1_SCK__GPO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) +#define MX23_PAD_ROTARYA__GPO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) +#define MX23_PAD_ROTARYB__GPO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A00__GPO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A01__GPO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A02__GPO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A03__GPO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A04__GPO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A05__GPO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A06__GPO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A07__GPO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A08__GPO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A09__GPO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A10__GPO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A11__GPO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_A12__GPO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_BA0__GPO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_BA1__GPO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_CASN__GPO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_CE0N__GPO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_CE1N__GPO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_CE1N__GPO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) +#define MX23_PAD_GPMI_CE0N__GPO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_CKE__GPO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_RASN__GPO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) +#define MX23_PAD_EMI_WEN__GPO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) + +#endif /* __MACH_IOMUX_MX23_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx28.h b/arch/arm/mach-mxs/include/mach/iomux-mx28.h new file mode 100644 index 0000000..f50fefd --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/iomux-mx28.h @@ -0,0 +1,537 @@ +/* + * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MACH_IOMUX_MX28_H__ +#define __MACH_IOMUX_MX28_H__ + +#include <mach/iomux.h> + +/* + * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> + * See also iomux.h + * + * BANK PIN MUX + */ +/* MUXSEL_0 */ +#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) + +#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) +#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) +#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) +#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) +#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) +#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) +#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) + +#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) + +#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) +#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) +#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) +#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) +#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) +#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) +#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) +#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) +#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) +#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) + +#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) +#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) +#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) + +#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) +#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) +#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) + +#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) +#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) +#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) + +/* MUXSEL_1 */ +#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) + +#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) +#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) +#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) +#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) +#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) +#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) + +#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) + +#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) +#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) +#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) +#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) +#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) +#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) +#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) + +#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) + +/* MUXSEL_2 */ +#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) + +#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) +#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) +#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) +#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) +#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) + +#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) + +#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) +#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) +#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) +#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) +#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) +#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) +#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) +#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) + +#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) + +/* MUXSEL_GPIO */ +#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) + +#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) + +#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) + +#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) + +#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) + +#endif /* __MACH_IOMUX_MX28_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h new file mode 100644 index 0000000..fe558e3 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/iomux.h @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * <armlinux@phytec.de> + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_MXS_IOMUX_H__ +#define __MACH_MXS_IOMUX_H__ + +/* + * IOMUX/PAD Bit field definitions + * + * PAD_BANK: 0..2 (3) + * PAD_PIN: 3..7 (5) + * PAD_MUXSEL: 8..9 (2) + * PAD_MA: 10..11 (2) + * PAD_MA_VALID: 12 (1) + * PAD_VOL: 13 (1) + * PAD_VOL_VALID: 14 (1) + * PAD_PULL: 15 (1) + * PAD_PULL_VALID: 16 (1) + * RESERVED: 17..31 (15) + */ +typedef u32 iomux_cfg_t; + +#define MXS_PAD_BANK_SHIFT 0 +#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) +#define MXS_PAD_PIN_SHIFT 3 +#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) +#define MXS_PAD_MUXSEL_SHIFT 8 +#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) +#define MXS_PAD_MA_SHIFT 10 +#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) +#define MXS_PAD_MA_VALID_SHIFT 12 +#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) +#define MXS_PAD_VOL_SHIFT 13 +#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) +#define MXS_PAD_VOL_VALID_SHIFT 14 +#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) +#define MXS_PAD_PULL_SHIFT 15 +#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) +#define MXS_PAD_PULL_VALID_SHIFT 16 +#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) + +#define PAD_MUXSEL_0 0 +#define PAD_MUXSEL_1 1 +#define PAD_MUXSEL_2 2 +#define PAD_MUXSEL_GPIO 3 + +#define PAD_4MA 0 +#define PAD_8MA 1 +#define PAD_12MA 2 +#define PAD_16MA 3 + +#define PAD_1V8 0 +#define PAD_3V3 1 + +#define PAD_NOPULL 0 +#define PAD_PULLUP 1 + +#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) + +#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ + MXS_PAD_VOL_VALID_MASK) +#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ + MXS_PAD_VOL_VALID_MASK) + +#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ + MXS_PAD_PULL_VALID_MASK) +#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ + MXS_PAD_PULL_VALID_MASK) + +#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ + (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ + ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ + ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ + ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ + ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ + ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) + +/* + * A pad becomes naked, when none of mA, vol or pull + * validity bits is set. + */ +#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ + MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) + +static inline unsigned int PAD_BANK(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; +} + +static inline unsigned int PAD_PIN(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; +} + +static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; +} + +static inline unsigned int PAD_MA(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; +} + +static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; +} + +static inline unsigned int PAD_VOL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; +} + +static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; +} + +static inline unsigned int PAD_PULL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; +} + +static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; +} + +/* + * configures a single pad in the iomuxer + */ +int mxs_iomux_setup_pad(iomux_cfg_t pad); + +/* + * configures multiple pads + * convenient way to call the above function with tables + */ +int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); + +#endif /* __MACH_MXS_IOMUX_H__*/ diff --git a/arch/arm/mach-mxs/include/mach/irqs.h b/arch/arm/mach-mxs/include/mach/irqs.h new file mode 100644 index 0000000..f771039 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/irqs.h @@ -0,0 +1,32 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_MXS_IRQS_H__ +#define __MACH_MXS_IRQS_H__ + +#define MXS_INTERNAL_IRQS 128 + +#define MXS_GPIO_IRQ_START MXS_INTERNAL_IRQS + +/* the maximum for MXS-based */ +#define MXS_GPIO_IRQS (32 * 5) + +/* + * The next 16 interrupts are for board specific purposes. Since + * the kernel can only run on one machine at a time, we can re-use + * these. If you need more, increase MXS_BOARD_IRQS, but keep it + * within sensible limits. + */ +#define MXS_BOARD_IRQ_START (MXS_GPIO_IRQ_START + MXS_GPIO_IRQS) +#define MXS_BOARD_IRQS 16 + +#define NR_IRQS (MXS_BOARD_IRQ_START + MXS_BOARD_IRQS) + +#endif /* __MACH_MXS_IRQS_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/memory.h b/arch/arm/mach-mxs/include/mach/memory.h new file mode 100644 index 0000000..b5420a5 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/memory.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MXS_MEMORY_H__ +#define __MACH_MXS_MEMORY_H__ + +#define PHYS_OFFSET UL(0x40000000) + +#endif /* __MACH_MXS_MEMORY_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h new file mode 100644 index 0000000..9edd02e --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/mx23.h @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MX23_H__ +#define __MACH_MX23_H__ + +#include <mach/mxs.h> + +/* + * OCRAM + */ +#define MX23_OCRAM_BASE_ADDR 0x00000000 +#define MX23_OCRAM_SIZE SZ_32K + +/* + * IO + */ +#define MX23_IO_BASE_ADDR 0x80000000 +#define MX23_IO_SIZE SZ_1M + +#define MX23_ICOLL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x000000) +#define MX23_APBH_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x004000) +#define MX23_BCH_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00a000) +#define MX23_GPMI_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00c000) +#define MX23_SSP1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x010000) +#define MX23_PINCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x018000) +#define MX23_DIGCTL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x01c000) +#define MX23_ETM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x020000) +#define MX23_APBX_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x024000) +#define MX23_DCP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x028000) +#define MX23_PXP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02a000) +#define MX23_OCOTP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02c000) +#define MX23_AXI_AHB0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02e000) +#define MX23_LCDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x030000) +#define MX23_SSP2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x034000) +#define MX23_TVENC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x038000) +#define MX23_CLKCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x040000) +#define MX23_SAIF0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x042000) +#define MX23_POWER_BASE_ADDR (MX23_IO_BASE_ADDR + 0x044000) +#define MX23_SAIF1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x046000) +#define MX23_AUDIOOUT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x048000) +#define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000) +#define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000) +#define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000) +#define MX23_I2C0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000) +#define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000) +#define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000) +#define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000) +#define MX23_AUART1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06c000) +#define MX23_AUART2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06e000) +#define MX23_DUART_BASE_ADDR (MX23_IO_BASE_ADDR + 0x070000) +#define MX23_USBPHY_BASE_ADDR (MX23_IO_BASE_ADDR + 0x07c000) +#define MX23_USBCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x080000) +#define MX23_DRAM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x0e0000) + +#define MX23_IO_P2V(x) MXS_IO_P2V(x) +#define MX23_IO_ADDRESS(x) IOMEM(MX23_IO_P2V(x)) + +/* + * IRQ + */ +#define MX23_INT_DUART 0 +#define MX23_INT_COMMS_RX 1 +#define MX23_INT_COMMS_TX 1 +#define MX23_INT_SSP2_ERROR 2 +#define MX23_INT_VDD5V 3 +#define MX23_INT_HEADPHONE_SHORT 4 +#define MX23_INT_DAC_DMA 5 +#define MX23_INT_DAC_ERROR 6 +#define MX23_INT_ADC_DMA 7 +#define MX23_INT_ADC_ERROR 8 +#define MX23_INT_SPDIF_DMA 9 +#define MX23_INT_SAIF2_DMA 9 +#define MX23_INT_SPDIF_ERROR 10 +#define MX23_INT_SAIF1_IRQ 10 +#define MX23_INT_SAIF2_IRQ 10 +#define MX23_INT_USB_CTRL 11 +#define MX23_INT_USB_WAKEUP 12 +#define MX23_INT_GPMI_DMA 13 +#define MX23_INT_SSP1_DMA 14 +#define MX23_INT_SSP_ERROR 15 +#define MX23_INT_GPIO0 16 +#define MX23_INT_GPIO1 17 +#define MX23_INT_GPIO2 18 +#define MX23_INT_SAIF1_DMA 19 +#define MX23_INT_SSP2_DMA 20 +#define MX23_INT_ECC8_IRQ 21 +#define MX23_INT_RTC_ALARM 22 +#define MX23_INT_UARTAPP_TX_DMA 23 +#define MX23_INT_UARTAPP_INTERNAL 24 +#define MX23_INT_UARTAPP_RX_DMA 25 +#define MX23_INT_I2C_DMA 26 +#define MX23_INT_I2C_ERROR 27 +#define MX23_INT_TIMER0 28 +#define MX23_INT_TIMER1 29 +#define MX23_INT_TIMER2 30 +#define MX23_INT_TIMER3 31 +#define MX23_INT_BATT_BRNOUT 32 +#define MX23_INT_VDDD_BRNOUT 33 +#define MX23_INT_VDDIO_BRNOUT 34 +#define MX23_INT_VDD18_BRNOUT 35 +#define MX23_INT_TOUCH_DETECT 36 +#define MX23_INT_LRADC_CH0 37 +#define MX23_INT_LRADC_CH1 38 +#define MX23_INT_LRADC_CH2 39 +#define MX23_INT_LRADC_CH3 40 +#define MX23_INT_LRADC_CH4 41 +#define MX23_INT_LRADC_CH5 42 +#define MX23_INT_LRADC_CH6 43 +#define MX23_INT_LRADC_CH7 44 +#define MX23_INT_LCDIF_DMA 45 +#define MX23_INT_LCDIF_ERROR 46 +#define MX23_INT_DIGCTL_DEBUG_TRAP 47 +#define MX23_INT_RTC_1MSEC 48 +#define MX23_INT_DRI_DMA 49 +#define MX23_INT_DRI_ATTENTION 50 +#define MX23_INT_GPMI_ATTENTION 51 +#define MX23_INT_IR 52 +#define MX23_INT_DCP_VMI 53 +#define MX23_INT_DCP 54 +#define MX23_INT_BCH 56 +#define MX23_INT_PXP 57 +#define MX23_INT_UARTAPP2_TX_DMA 58 +#define MX23_INT_UARTAPP2_INTERNAL 59 +#define MX23_INT_UARTAPP2_RX_DMA 60 +#define MX23_INT_VDAC_DETECT 61 +#define MX23_INT_VDD5V_DROOP 64 +#define MX23_INT_DCDC4P2_BO 65 + +#endif /* __MACH_MX23_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h new file mode 100644 index 0000000..0716745 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/mx28.h @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MX28_H__ +#define __MACH_MX28_H__ + +#include <mach/mxs.h> + +/* + * OCRAM + */ +#define MX28_OCRAM_BASE_ADDR 0x00000000 +#define MX28_OCRAM_SIZE SZ_128K + +/* + * IO + */ +#define MX28_IO_BASE_ADDR 0x80000000 +#define MX28_IO_SIZE SZ_1M + +#define MX28_ICOLL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x000000) +#define MX28_HSADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x002000) +#define MX28_APBH_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x004000) +#define MX28_PERFMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x006000) +#define MX28_BCH_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00a000) +#define MX28_GPMI_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00c000) +#define MX28_SSP0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x010000) +#define MX28_SSP1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x012000) +#define MX28_SSP2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x014000) +#define MX28_SSP3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x016000) +#define MX28_PINCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x018000) +#define MX28_DIGCTL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x01c000) +#define MX28_ETM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x022000) +#define MX28_APBX_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x024000) +#define MX28_DCP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x028000) +#define MX28_PXP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02a000) +#define MX28_OCOTP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02c000) +#define MX28_AXI_AHB0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02e000) +#define MX28_LCDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x030000) +#define MX28_CAN0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x032000) +#define MX28_CAN1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x034000) +#define MX28_SIMDBG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c000) +#define MX28_SIMGPMISEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c200) +#define MX28_SIMSSPSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c300) +#define MX28_SIMMEMSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c400) +#define MX28_GPIOMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c500) +#define MX28_SIMENET_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c700) +#define MX28_ARMJTAG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c800) +#define MX28_CLKCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x040000) +#define MX28_SAIF0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x042000) +#define MX28_POWER_BASE_ADDR (MX28_IO_BASE_ADDR + 0x044000) +#define MX28_SAIF1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x046000) +#define MX28_LRADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x050000) +#define MX28_SPDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x054000) +#define MX28_RTC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x056000) +#define MX28_I2C0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x058000) +#define MX28_I2C1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x05a000) +#define MX28_PWM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x064000) +#define MX28_TIMROT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x068000) +#define MX28_AUART0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06a000) +#define MX28_AUART1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06c000) +#define MX28_AUART2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06e000) +#define MX28_AUART3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x070000) +#define MX28_AUART4_BASE_ADDR (MX28_IO_BASE_ADDR + 0x072000) +#define MX28_DUART_BASE_ADDR (MX28_IO_BASE_ADDR + 0x074000) +#define MX28_USBPHY0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07C000) +#define MX28_USBPHY1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07e000) +#define MX28_USBCTRL0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x080000) +#define MX28_USBCTRL1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x090000) +#define MX28_DFLPT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0c0000) +#define MX28_DRAM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0e0000) +#define MX28_ENET_MAC0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f0000) +#define MX28_ENET_MAC1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f4000) + +#define MX28_IO_P2V(x) MXS_IO_P2V(x) +#define MX28_IO_ADDRESS(x) IOMEM(MX28_IO_P2V(x)) + +/* + * IRQ + */ +#define MX28_INT_BATT_BRNOUT 0 +#define MX28_INT_VDDD_BRNOUT 1 +#define MX28_INT_VDDIO_BRNOUT 2 +#define MX28_INT_VDDA_BRNOUT 3 +#define MX28_INT_VDD5V_DROOP 4 +#define MX28_INT_DCDC4P2_BRNOUT 5 +#define MX28_INT_VDD5V 6 +#define MX28_INT_CAN0 8 +#define MX28_INT_CAN1 9 +#define MX28_INT_LRADC_TOUCH 10 +#define MX28_INT_HSADC 13 +#define MX28_INT_IRADC_THRESH0 14 +#define MX28_INT_IRADC_THRESH1 15 +#define MX28_INT_LRADC_CH0 16 +#define MX28_INT_LRADC_CH1 17 +#define MX28_INT_LRADC_CH2 18 +#define MX28_INT_LRADC_CH3 19 +#define MX28_INT_LRADC_CH4 20 +#define MX28_INT_LRADC_CH5 21 +#define MX28_INT_LRADC_CH6 22 +#define MX28_INT_LRADC_CH7 23 +#define MX28_INT_LRADC_BUTTON0 24 +#define MX28_INT_LRADC_BUTTON1 25 +#define MX28_INT_PERFMON 27 +#define MX28_INT_RTC_1MSEC 28 +#define MX28_INT_RTC_ALARM 29 +#define MX28_INT_COMMS 31 +#define MX28_INT_EMI_ERR 32 +#define MX28_INT_LCDIF 38 +#define MX28_INT_PXP 39 +#define MX28_INT_BCH 41 +#define MX28_INT_GPMI 42 +#define MX28_INT_SPDIF_ERROR 45 +#define MX28_INT_DUART 47 +#define MX28_INT_TIMER0 48 +#define MX28_INT_TIMER1 49 +#define MX28_INT_TIMER2 50 +#define MX28_INT_TIMER3 51 +#define MX28_INT_DCP_VMI 52 +#define MX28_INT_DCP 53 +#define MX28_INT_DCP_SECURE 54 +#define MX28_INT_SAIF1 58 +#define MX28_INT_SAIF0 59 +#define MX28_INT_SPDIF_DMA 66 +#define MX28_INT_I2C0_DMA 68 +#define MX28_INT_I2C1_DMA 69 +#define MX28_INT_AUART0_RX_DMA 70 +#define MX28_INT_AUART0_TX_DMA 71 +#define MX28_INT_AUART1_RX_DMA 72 +#define MX28_INT_AUART1_TX_DMA 73 +#define MX28_INT_AUART2_RX_DMA 74 +#define MX28_INT_AUART2_TX_DMA 75 +#define MX28_INT_AUART3_RX_DMA 76 +#define MX28_INT_AUART3_TX_DMA 77 +#define MX28_INT_AUART4_RX_DMA 78 +#define MX28_INT_AUART4_TX_DMA 79 +#define MX28_INT_SAIF0_DMA 80 +#define MX28_INT_SAIF1_DMA 81 +#define MX28_INT_SSP0_DMA 82 +#define MX28_INT_SSP1_DMA 83 +#define MX28_INT_SSP2_DMA 84 +#define MX28_INT_SSP3_DMA 85 +#define MX28_INT_LCDIF_DMA 86 +#define MX28_INT_HSADC_DMA 87 +#define MX28_INT_GPMI_DMA 88 +#define MX28_INT_DIGCTL_DEBUG_TRAP 89 +#define MX28_INT_USB1 92 +#define MX28_INT_USB0 93 +#define MX28_INT_USB1_WAKEUP 94 +#define MX28_INT_USB0_WAKEUP 95 +#define MX28_INT_SSP0 96 +#define MX28_INT_SSP1 97 +#define MX28_INT_SSP2 98 +#define MX28_INT_SSP3 99 +#define MX28_INT_ENET_SWI 100 +#define MX28_INT_ENET_MAC0 101 +#define MX28_INT_ENET_MAC1 102 +#define MX28_INT_ENET_MAC0_1588 103 +#define MX28_INT_ENET_MAC1_1588 104 +#define MX28_INT_I2C1_ERROR 110 +#define MX28_INT_I2C0_ERROR 111 +#define MX28_INT_AUART0 112 +#define MX28_INT_AUART1 113 +#define MX28_INT_AUART2 114 +#define MX28_INT_AUART3 115 +#define MX28_INT_AUART4 116 +#define MX28_INT_GPIO4 123 +#define MX28_INT_GPIO3 124 +#define MX28_INT_GPIO2 125 +#define MX28_INT_GPIO1 126 +#define MX28_INT_GPIO0 127 + +#endif /* __MACH_MX28_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h new file mode 100644 index 0000000..f186c08 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/mxs.h @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MXS_H__ +#define __MACH_MXS_H__ + +#ifndef __ASSEMBLER__ +#include <linux/io.h> +#endif +#include <asm/mach-types.h> +#include <mach/hardware.h> + +/* + * MXS CPU types + */ +#define cpu_is_mx23() (machine_is_mx23evk()) +#define cpu_is_mx28() (machine_is_mx28evk()) + +/* + * IO addresses common to MXS-based + */ +#define MXS_IO_BASE_ADDR 0x80000000 +#define MXS_IO_SIZE SZ_1M + +#define MXS_ICOLL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x000000) +#define MXS_APBH_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x004000) +#define MXS_BCH_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00a000) +#define MXS_GPMI_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00c000) +#define MXS_PINCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x018000) +#define MXS_DIGCTL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x01c000) +#define MXS_APBX_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x024000) +#define MXS_DCP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x028000) +#define MXS_PXP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02a000) +#define MXS_OCOTP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02c000) +#define MXS_AXI_AHB0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02e000) +#define MXS_LCDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x030000) +#define MXS_CLKCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x040000) +#define MXS_SAIF0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x042000) +#define MXS_POWER_BASE_ADDR (MXS_IO_BASE_ADDR + 0x044000) +#define MXS_SAIF1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x046000) +#define MXS_LRADC_BASE_ADDR (MXS_IO_BASE_ADDR + 0x050000) +#define MXS_SPDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x054000) +#define MXS_I2C0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x058000) +#define MXS_PWM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x064000) +#define MXS_TIMROT_BASE_ADDR (MXS_IO_BASE_ADDR + 0x068000) +#define MXS_AUART1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06c000) +#define MXS_AUART2_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06e000) +#define MXS_DRAM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x0e0000) + +/* + * It maps the whole address space to [0xf4000000, 0xf50fffff]. + * + * OCRAM 0x00000000+0x020000 -> 0xf4000000+0x020000 + * IO 0x80000000+0x100000 -> 0xf5000000+0x100000 + */ +#define MXS_IO_P2V(x) (0xf4000000 + \ + (((x) & 0x80000000) >> 7) + \ + (((x) & 0x000fffff))) + +#define MXS_IO_ADDRESS(x) IOMEM(MXS_IO_P2V(x)) + +#define mxs_map_entry(soc, name, _type) { \ + .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ + .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ + .length = soc ## _ ## name ## _SIZE, \ + .type = _type, \ +} + +#define MXS_SET_ADDR 0x4 +#define MXS_CLR_ADDR 0x8 +#define MXS_TOG_ADDR 0xc + +#ifndef __ASSEMBLER__ +static inline void __mxs_setl(u32 mask, void __iomem *reg) +{ + __raw_writel(mask, reg + MXS_SET_ADDR); +} + +static inline void __mxs_clrl(u32 mask, void __iomem *reg) +{ + __raw_writel(mask, reg + MXS_CLR_ADDR); +} + +static inline void __mxs_togl(u32 mask, void __iomem *reg) +{ + __raw_writel(mask, reg + MXS_TOG_ADDR); +} +#endif + +#endif /* __MACH_MXS_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/system.h b/arch/arm/mach-mxs/include/mach/system.h new file mode 100644 index 0000000..0e42823 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/system.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_MXS_SYSTEM_H__ +#define __MACH_MXS_SYSTEM_H__ + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +void arch_reset(char mode, const char *cmd); + +#endif /* __MACH_MXS_SYSTEM_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/timex.h b/arch/arm/mach-mxs/include/mach/timex.h new file mode 100644 index 0000000..734ce89 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/timex.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_MXS_TIMEX_H__ +#define __MACH_MXS_TIMEX_H__ + +#define CLOCK_TICK_RATE 32000 /* 32K */ + +#endif /* __MACH_MXS_TIMEX_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h new file mode 100644 index 0000000..a005e76f --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/uncompress.h @@ -0,0 +1,76 @@ +/* + * arch/arm/mach-mxs/include/mach/uncompress.h + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) Shane Nay (shane@minirl.com) + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __MACH_MXS_UNCOMPRESS_H__ +#define __MACH_MXS_UNCOMPRESS_H__ + +#include <asm/mach-types.h> + +static unsigned long mxs_duart_base; + +#define MXS_DUART(x) (*(volatile unsigned long *)(mxs_duart_base + (x))) + +#define MXS_DUART_DR 0x00 +#define MXS_DUART_FR 0x18 +#define MXS_DUART_FR_TXFE (1 << 7) +#define MXS_DUART_CR 0x30 +#define MXS_DUART_CR_UARTEN (1 << 0) + +/* + * The following code assumes the serial port has already been + * initialized by the bootloader. If it's not, the output is + * simply discarded. + */ + +static void putc(int ch) +{ + if (!mxs_duart_base) + return; + if (!(MXS_DUART(MXS_DUART_CR) & MXS_DUART_CR_UARTEN)) + return; + + while (!(MXS_DUART(MXS_DUART_FR) & MXS_DUART_FR_TXFE)) + barrier(); + + MXS_DUART(MXS_DUART_DR) = ch; +} + +static inline void flush(void) +{ +} + +#define MX23_DUART_BASE_ADDR 0x80070000 +#define MX28_DUART_BASE_ADDR 0x80074000 + +static inline void __arch_decomp_setup(unsigned long arch_id) +{ + switch (arch_id) { + case MACH_TYPE_MX23EVK: + mxs_duart_base = MX23_DUART_BASE_ADDR; + break; + case MACH_TYPE_MX28EVK: + mxs_duart_base = MX28_DUART_BASE_ADDR; + break; + default: + break; + } +} + +#define arch_decomp_setup() __arch_decomp_setup(arch_id) +#define arch_decomp_wdog() + +#endif /* __MACH_MXS_UNCOMPRESS_H__ */ diff --git a/arch/arm/mach-mxs/include/mach/vmalloc.h b/arch/arm/mach-mxs/include/mach/vmalloc.h new file mode 100644 index 0000000..103b016 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/vmalloc.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2000 Russell King. + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_MXS_VMALLOC_H__ +#define __MACH_MXS_VMALLOC_H__ + +/* vmalloc ending address */ +#define VMALLOC_END 0xf4000000UL + +#endif /* __MACH_MXS_VMALLOC_H__ */ diff --git a/arch/arm/mach-mxs/iomux.c b/arch/arm/mach-mxs/iomux.c new file mode 100644 index 0000000..0e804e2 --- /dev/null +++ b/arch/arm/mach-mxs/iomux.c @@ -0,0 +1,101 @@ +/* + * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * <armlinux@phytec.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/string.h> +#include <linux/gpio.h> + +#include <asm/mach/map.h> + +#include <mach/mxs.h> +#include <mach/iomux.h> + +/* + * configures a single pad in the iomuxer + */ +int mxs_iomux_setup_pad(iomux_cfg_t pad) +{ + u32 reg, ofs, bp, bm; + void __iomem *iomux_base = MXS_IO_ADDRESS(MXS_PINCTRL_BASE_ADDR); + + /* muxsel */ + ofs = 0x100; + ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10; + bp = PAD_PIN(pad) % 16 * 2; + bm = 0x3 << bp; + reg = __raw_readl(iomux_base + ofs); + reg &= ~bm; + reg |= PAD_MUXSEL(pad) << bp; + __raw_writel(reg, iomux_base + ofs); + + /* drive */ + ofs = cpu_is_mx23() ? 0x200 : 0x300; + ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10; + /* mA */ + if (PAD_MA_VALID(pad)) { + bp = PAD_PIN(pad) % 8 * 4; + bm = 0x3 << bp; + reg = __raw_readl(iomux_base + ofs); + reg &= ~bm; + reg |= PAD_MA(pad) << bp; + __raw_writel(reg, iomux_base + ofs); + } + /* vol */ + if (PAD_VOL_VALID(pad)) { + bp = PAD_PIN(pad) % 8 * 4 + 2; + if (PAD_VOL(pad)) + __mxs_setl(1 << bp, iomux_base + ofs); + else + __mxs_clrl(1 << bp, iomux_base + ofs); + } + + /* pull */ + if (PAD_PULL_VALID(pad)) { + ofs = cpu_is_mx23() ? 0x400 : 0x600; + ofs += PAD_BANK(pad) * 0x10; + bp = PAD_PIN(pad); + if (PAD_PULL(pad)) + __mxs_setl(1 << bp, iomux_base + ofs); + else + __mxs_clrl(1 << bp, iomux_base + ofs); + } + + return 0; +} + +int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count) +{ + const iomux_cfg_t *p = pad_list; + int i; + int ret; + + for (i = 0; i < count; i++) { + ret = mxs_iomux_setup_pad(*p); + if (ret) + return ret; + p++; + } + + return 0; +} diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c new file mode 100644 index 0000000..aa06400 --- /dev/null +++ b/arch/arm/mach-mxs/mach-mx23evk.c @@ -0,0 +1,57 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/irq.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include <mach/common.h> +#include <mach/iomux-mx23.h> + +#include "devices-mx23.h" + +static const iomux_cfg_t mx23evk_pads[] __initconst = { + /* duart */ + MX23_PAD_PWM0__DUART_RX | MXS_PAD_4MA, + MX23_PAD_PWM1__DUART_TX | MXS_PAD_4MA, +}; + +static void __init mx23evk_init(void) +{ + mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads)); + + mx23_add_duart(); +} + +static void __init mx23evk_timer_init(void) +{ + mx23_clocks_init(); +} + +static struct sys_timer mx23evk_timer = { + .init = mx23evk_timer_init, +}; + +MACHINE_START(MX23EVK, "Freescale MX23 EVK") + /* Maintainer: Freescale Semiconductor, Inc. */ + .map_io = mx23_map_io, + .init_irq = mx23_init_irq, + .init_machine = mx23evk_init, + .timer = &mx23evk_timer, +MACHINE_END diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c new file mode 100644 index 0000000..d162e95 --- /dev/null +++ b/arch/arm/mach-mxs/mach-mx28evk.c @@ -0,0 +1,138 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/irq.h> +#include <linux/clk.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include <mach/common.h> +#include <mach/iomux-mx28.h> + +#include "devices-mx28.h" +#include "gpio.h" + +#define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) +#define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) + +static const iomux_cfg_t mx28evk_pads[] __initconst = { + /* duart */ + MX28_PAD_PWM0__DUART_RX | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_PWM1__DUART_TX | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + + /* fec0 */ + MX28_PAD_ENET0_MDC__ENET0_MDC | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_MDIO__ENET0_MDIO | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX28_PAD_ENET_CLK__CLKCTRL_ENET | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + /* phy power line */ + MX28_PAD_SSP1_DATA3__GPIO_2_15 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* phy reset line */ + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), +}; + +/* fec */ +static void __init mx28evk_fec_reset(void) +{ + int ret; + struct clk *clk; + + /* Enable fec phy clock */ + clk = clk_get_sys("pll2", NULL); + if (!IS_ERR(clk)) + clk_enable(clk); + + /* Power up fec phy */ + ret = gpio_request(MX28EVK_FEC_PHY_POWER, "fec-phy-power"); + if (ret) { + pr_err("Failed to request gpio fec-phy-%s: %d\n", "power", ret); + return; + } + + ret = gpio_direction_output(MX28EVK_FEC_PHY_POWER, 0); + if (ret) { + pr_err("Failed to drive gpio fec-phy-%s: %d\n", "power", ret); + return; + } + + /* Reset fec phy */ + ret = gpio_request(MX28EVK_FEC_PHY_RESET, "fec-phy-reset"); + if (ret) { + pr_err("Failed to request gpio fec-phy-%s: %d\n", "reset", ret); + return; + } + + gpio_direction_output(MX28EVK_FEC_PHY_RESET, 0); + if (ret) { + pr_err("Failed to drive gpio fec-phy-%s: %d\n", "reset", ret); + return; + } + + mdelay(1); + gpio_set_value(MX28EVK_FEC_PHY_RESET, 1); +} + +static const struct fec_platform_data mx28_fec_pdata __initconst = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +static void __init mx28evk_init(void) +{ + mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); + + mx28_add_duart(); + + mx28evk_fec_reset(); + mx28_add_fec(0, &mx28_fec_pdata); +} + +static void __init mx28evk_timer_init(void) +{ + mx28_clocks_init(); +} + +static struct sys_timer mx28evk_timer = { + .init = mx28evk_timer_init, +}; + +MACHINE_START(MX28EVK, "Freescale MX28 EVK") + /* Maintainer: Freescale Semiconductor, Inc. */ + .map_io = mx28_map_io, + .init_irq = mx28_init_irq, + .init_machine = mx28evk_init, + .timer = &mx28evk_timer, +MACHINE_END diff --git a/arch/arm/mach-mxs/mm-mx23.c b/arch/arm/mach-mxs/mm-mx23.c new file mode 100644 index 0000000..5148cd6 --- /dev/null +++ b/arch/arm/mach-mxs/mm-mx23.c @@ -0,0 +1,45 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * Create static mapping between physical to virtual memory. + */ + +#include <linux/mm.h> +#include <linux/init.h> + +#include <asm/mach/map.h> + +#include <mach/mx23.h> +#include <mach/common.h> +#include <mach/iomux.h> + +/* + * Define the MX23 memory map. + */ +static struct map_desc mx23_io_desc[] __initdata = { + mxs_map_entry(MX23, OCRAM, MT_DEVICE), + mxs_map_entry(MX23, IO, MT_DEVICE), +}; + +/* + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory mappings + * for the IO modules. + */ +void __init mx23_map_io(void) +{ + iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc)); +} + +void __init mx23_init_irq(void) +{ + icoll_init_irq(); + mx23_register_gpios(); +} diff --git a/arch/arm/mach-mxs/mm-mx28.c b/arch/arm/mach-mxs/mm-mx28.c new file mode 100644 index 0000000..7e4cea3 --- /dev/null +++ b/arch/arm/mach-mxs/mm-mx28.c @@ -0,0 +1,45 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * Create static mapping between physical to virtual memory. + */ + +#include <linux/mm.h> +#include <linux/init.h> + +#include <asm/mach/map.h> + +#include <mach/mx28.h> +#include <mach/common.h> +#include <mach/iomux.h> + +/* + * Define the MX28 memory map. + */ +static struct map_desc mx28_io_desc[] __initdata = { + mxs_map_entry(MX28, OCRAM, MT_DEVICE), + mxs_map_entry(MX28, IO, MT_DEVICE), +}; + +/* + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory mappings + * for the IO modules. + */ +void __init mx28_map_io(void) +{ + iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); +} + +void __init mx28_init_irq(void) +{ + icoll_init_irq(); + mx28_register_gpios(); +} diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h new file mode 100644 index 0000000..dbc0474 --- /dev/null +++ b/arch/arm/mach-mxs/regs-clkctrl-mx23.h @@ -0,0 +1,455 @@ +/* + * Freescale CLKCTRL Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.48 + * Template revision: 26195 + */ + +#ifndef __REGS_CLKCTRL_MX23_H__ +#define __REGS_CLKCTRL_MX23_H__ + + +#define HW_CLKCTRL_PLLCTRL0 (0x00000000) +#define HW_CLKCTRL_PLLCTRL0_SET (0x00000004) +#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008) +#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c) + +#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30 +#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \ + (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6) +#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL) +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5) +#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL) +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4) +#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL) +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000 +#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000 +#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000 +#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF +#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1) + +#define HW_CLKCTRL_PLLCTRL1 (0x00000010) + +#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1) +#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_CPU (0x00000020) +#define HW_CLKCTRL_CPU_SET (0x00000024) +#define HW_CLKCTRL_CPU_CLR (0x00000028) +#define HW_CLKCTRL_CPU_TOG (0x0000002c) + +#define BP_CLKCTRL_CPU_RSRVD5 30 +#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 +#define BF_CLKCTRL_CPU_RSRVD5(v) \ + (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) +#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 +#define BM_CLKCTRL_CPU_RSRVD4 0x08000000 +#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 +#define BP_CLKCTRL_CPU_DIV_XTAL 16 +#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 +#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ + (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) +#define BP_CLKCTRL_CPU_RSRVD3 13 +#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 +#define BF_CLKCTRL_CPU_RSRVD3(v) \ + (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) +#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 +#define BM_CLKCTRL_CPU_RSRVD2 0x00000800 +#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 +#define BP_CLKCTRL_CPU_RSRVD1 6 +#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 +#define BF_CLKCTRL_CPU_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) +#define BP_CLKCTRL_CPU_DIV_CPU 0 +#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F +#define BF_CLKCTRL_CPU_DIV_CPU(v) \ + (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) + +#define HW_CLKCTRL_HBUS (0x00000030) +#define HW_CLKCTRL_HBUS_SET (0x00000034) +#define HW_CLKCTRL_HBUS_CLR (0x00000038) +#define HW_CLKCTRL_HBUS_TOG (0x0000003c) + +#define BP_CLKCTRL_HBUS_RSRVD4 30 +#define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000 +#define BF_CLKCTRL_HBUS_RSRVD4(v) \ + (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4) +#define BM_CLKCTRL_HBUS_BUSY 0x20000000 +#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 +#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000 +#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 +#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 +#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 +#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 +#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000 +#define BM_CLKCTRL_HBUS_RSRVD2 0x00080000 +#define BP_CLKCTRL_HBUS_SLOW_DIV 16 +#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 +#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 +#define BP_CLKCTRL_HBUS_RSRVD1 6 +#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 +#define BF_CLKCTRL_HBUS_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) +#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 +#define BP_CLKCTRL_HBUS_DIV 0 +#define BM_CLKCTRL_HBUS_DIV 0x0000001F +#define BF_CLKCTRL_HBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_HBUS_DIV) + +#define HW_CLKCTRL_XBUS (0x00000040) + +#define BM_CLKCTRL_XBUS_BUSY 0x80000000 +#define BP_CLKCTRL_XBUS_RSRVD1 11 +#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800 +#define BF_CLKCTRL_XBUS_RSRVD1(v) \ + (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1) +#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_XBUS_DIV 0 +#define BM_CLKCTRL_XBUS_DIV 0x000003FF +#define BF_CLKCTRL_XBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_XBUS_DIV) + +#define HW_CLKCTRL_XTAL (0x00000050) +#define HW_CLKCTRL_XTAL_SET (0x00000054) +#define HW_CLKCTRL_XTAL_CLR (0x00000058) +#define HW_CLKCTRL_XTAL_TOG (0x0000005c) + +#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 +#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 +#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30 +#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 +#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 +#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 +#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 +#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000 +#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 +#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 +#define BP_CLKCTRL_XTAL_RSRVD1 2 +#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC +#define BF_CLKCTRL_XTAL_RSRVD1(v) \ + (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) +#define BP_CLKCTRL_XTAL_DIV_UART 0 +#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 +#define BF_CLKCTRL_XTAL_DIV_UART(v) \ + (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) + +#define HW_CLKCTRL_PIX (0x00000060) + +#define BP_CLKCTRL_PIX_CLKGATE 31 +#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 +#define BM_CLKCTRL_PIX_RSRVD2 0x40000000 +#define BM_CLKCTRL_PIX_BUSY 0x20000000 +#define BP_CLKCTRL_PIX_RSRVD1 13 +#define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000 +#define BF_CLKCTRL_PIX_RSRVD1(v) \ + (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1) +#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000 +#define BP_CLKCTRL_PIX_DIV 0 +#define BM_CLKCTRL_PIX_DIV 0x00000FFF +#define BF_CLKCTRL_PIX_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_PIX_DIV) + +#define HW_CLKCTRL_SSP (0x00000070) + +#define BP_CLKCTRL_SSP_CLKGATE 31 +#define BM_CLKCTRL_SSP_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP_BUSY 0x20000000 +#define BP_CLKCTRL_SSP_RSRVD1 10 +#define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1) +#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP_DIV 0 +#define BM_CLKCTRL_SSP_DIV 0x000001FF +#define BF_CLKCTRL_SSP_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP_DIV) + +#define HW_CLKCTRL_GPMI (0x00000080) + +#define BP_CLKCTRL_GPMI_CLKGATE 31 +#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 +#define BM_CLKCTRL_GPMI_BUSY 0x20000000 +#define BP_CLKCTRL_GPMI_RSRVD1 11 +#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 +#define BF_CLKCTRL_GPMI_RSRVD1(v) \ + (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) +#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_GPMI_DIV 0 +#define BM_CLKCTRL_GPMI_DIV 0x000003FF +#define BF_CLKCTRL_GPMI_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_GPMI_DIV) + +#define HW_CLKCTRL_SPDIF (0x00000090) + +#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 +#define BP_CLKCTRL_SPDIF_RSRVD 0 +#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF +#define BF_CLKCTRL_SPDIF_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) + +#define HW_CLKCTRL_EMI (0x000000a0) + +#define BP_CLKCTRL_EMI_CLKGATE 31 +#define BM_CLKCTRL_EMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 +#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 +#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 +#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 +#define BP_CLKCTRL_EMI_RSRVD3 18 +#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 +#define BF_CLKCTRL_EMI_RSRVD3(v) \ + (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) +#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 +#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 +#define BP_CLKCTRL_EMI_RSRVD2 12 +#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 +#define BF_CLKCTRL_EMI_RSRVD2(v) \ + (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) +#define BP_CLKCTRL_EMI_DIV_XTAL 8 +#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 +#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ + (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) +#define BP_CLKCTRL_EMI_RSRVD1 6 +#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 +#define BF_CLKCTRL_EMI_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) +#define BP_CLKCTRL_EMI_DIV_EMI 0 +#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F +#define BF_CLKCTRL_EMI_DIV_EMI(v) \ + (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) + +#define HW_CLKCTRL_IR (0x000000b0) + +#define BM_CLKCTRL_IR_CLKGATE 0x80000000 +#define BM_CLKCTRL_IR_RSRVD3 0x40000000 +#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 +#define BM_CLKCTRL_IR_IR_BUSY 0x10000000 +#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000 +#define BP_CLKCTRL_IR_RSRVD2 25 +#define BM_CLKCTRL_IR_RSRVD2 0x06000000 +#define BF_CLKCTRL_IR_RSRVD2(v) \ + (((v) << 25) & BM_CLKCTRL_IR_RSRVD2) +#define BP_CLKCTRL_IR_IROV_DIV 16 +#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000 +#define BF_CLKCTRL_IR_IROV_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV) +#define BP_CLKCTRL_IR_RSRVD1 10 +#define BM_CLKCTRL_IR_RSRVD1 0x0000FC00 +#define BF_CLKCTRL_IR_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_IR_RSRVD1) +#define BP_CLKCTRL_IR_IR_DIV 0 +#define BM_CLKCTRL_IR_IR_DIV 0x000003FF +#define BF_CLKCTRL_IR_IR_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_IR_IR_DIV) + +#define HW_CLKCTRL_SAIF (0x000000c0) + +#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF_RSRVD1 17 +#define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1) +#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF_DIV 0 +#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF_DIV) + +#define HW_CLKCTRL_TV (0x000000d0) + +#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 +#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 +#define BP_CLKCTRL_TV_RSRVD 0 +#define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF +#define BF_CLKCTRL_TV_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_TV_RSRVD) + +#define HW_CLKCTRL_ETM (0x000000e0) + +#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 +#define BM_CLKCTRL_ETM_RSRVD2 0x40000000 +#define BM_CLKCTRL_ETM_BUSY 0x20000000 +#define BP_CLKCTRL_ETM_RSRVD1 7 +#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80 +#define BF_CLKCTRL_ETM_RSRVD1(v) \ + (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1) +#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040 +#define BP_CLKCTRL_ETM_DIV 0 +#define BM_CLKCTRL_ETM_DIV 0x0000003F +#define BF_CLKCTRL_ETM_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_ETM_DIV) + +#define HW_CLKCTRL_FRAC (0x000000f0) +#define HW_CLKCTRL_FRAC_SET (0x000000f4) +#define HW_CLKCTRL_FRAC_CLR (0x000000f8) +#define HW_CLKCTRL_FRAC_TOG (0x000000fc) + +#define BP_CLKCTRL_FRAC_CLKGATEIO 31 +#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 +#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC_IOFRAC 24 +#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000 +#define BF_CLKCTRL_FRAC_IOFRAC(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC) +#define BP_CLKCTRL_FRAC_CLKGATEPIX 23 +#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 +#define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC_PIXFRAC 16 +#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 +#define BF_CLKCTRL_FRAC_PIXFRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC) +#define BP_CLKCTRL_FRAC_CLKGATEEMI 15 +#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000 +#define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC_EMIFRAC 8 +#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC_EMIFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC) +#define BP_CLKCTRL_FRAC_CLKGATECPU 7 +#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080 +#define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC_CPUFRAC 0 +#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F +#define BF_CLKCTRL_FRAC_CPUFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC) + +#define HW_CLKCTRL_FRAC1 (0x00000100) +#define HW_CLKCTRL_FRAC1_SET (0x00000104) +#define HW_CLKCTRL_FRAC1_CLR (0x00000108) +#define HW_CLKCTRL_FRAC1_TOG (0x0000010c) + +#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 +#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC1_RSRVD1 0 +#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF +#define BF_CLKCTRL_FRAC1_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1) + +#define HW_CLKCTRL_CLKSEQ (0x00000110) +#define HW_CLKCTRL_CLKSEQ_SET (0x00000114) +#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118) +#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c) + +#define BP_CLKCTRL_CLKSEQ_RSRVD1 9 +#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00 +#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ + (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1) +#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 +#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 +#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 +#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 +#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 +#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004 +#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 + +#define HW_CLKCTRL_RESET (0x00000120) + +#define BP_CLKCTRL_RESET_RSRVD 2 +#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC +#define BF_CLKCTRL_RESET_RSRVD(v) \ + (((v) << 2) & BM_CLKCTRL_RESET_RSRVD) +#define BM_CLKCTRL_RESET_CHIP 0x00000002 +#define BM_CLKCTRL_RESET_DIG 0x00000001 + +#define HW_CLKCTRL_STATUS (0x00000130) + +#define BP_CLKCTRL_STATUS_CPU_LIMIT 30 +#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 +#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ + (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) +#define BP_CLKCTRL_STATUS_RSRVD 0 +#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF +#define BF_CLKCTRL_STATUS_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) + +#define HW_CLKCTRL_VERSION (0x00000140) + +#define BP_CLKCTRL_VERSION_MAJOR 24 +#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 +#define BF_CLKCTRL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) +#define BP_CLKCTRL_VERSION_MINOR 16 +#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 +#define BF_CLKCTRL_VERSION_MINOR(v) \ + (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) +#define BP_CLKCTRL_VERSION_STEP 0 +#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF +#define BF_CLKCTRL_VERSION_STEP(v) \ + (((v) << 0) & BM_CLKCTRL_VERSION_STEP) + +#endif /* __REGS_CLKCTRL_MX23_H__ */ diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h new file mode 100644 index 0000000..661df187 --- /dev/null +++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h @@ -0,0 +1,663 @@ +/* + * Freescale CLKCTRL Register Definitions + * + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.48 + * Template revision: 26195 + */ + +#ifndef __REGS_CLKCTRL_MX28_H__ +#define __REGS_CLKCTRL_MX28_H__ + +#define HW_CLKCTRL_PLL0CTRL0 (0x00000000) +#define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004) +#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008) +#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c) + +#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \ + (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6) +#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL) +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5) +#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL) +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4) +#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL) +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000 +#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF +#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1) + +#define HW_CLKCTRL_PLL0CTRL1 (0x00000010) + +#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1) +#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_PLL1CTRL0 (0x00000020) +#define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024) +#define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028) +#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c) + +#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000 +#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL) +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5) +#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL) +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4) +#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL) +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000 +#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF +#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1) + +#define HW_CLKCTRL_PLL1CTRL1 (0x00000030) + +#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1) +#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_PLL2CTRL0 (0x00000040) +#define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044) +#define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048) +#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c) + +#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000 +#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000 +#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL) +#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000 +#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000 +#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL) +#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000 +#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF +#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1) + +#define HW_CLKCTRL_CPU (0x00000050) +#define HW_CLKCTRL_CPU_SET (0x00000054) +#define HW_CLKCTRL_CPU_CLR (0x00000058) +#define HW_CLKCTRL_CPU_TOG (0x0000005c) + +#define BP_CLKCTRL_CPU_RSRVD5 30 +#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 +#define BF_CLKCTRL_CPU_RSRVD5(v) \ + (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) +#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 +#define BM_CLKCTRL_CPU_RSRVD4 0x08000000 +#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 +#define BP_CLKCTRL_CPU_DIV_XTAL 16 +#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 +#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ + (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) +#define BP_CLKCTRL_CPU_RSRVD3 13 +#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 +#define BF_CLKCTRL_CPU_RSRVD3(v) \ + (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) +#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 +#define BM_CLKCTRL_CPU_RSRVD2 0x00000800 +#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 +#define BP_CLKCTRL_CPU_RSRVD1 6 +#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 +#define BF_CLKCTRL_CPU_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) +#define BP_CLKCTRL_CPU_DIV_CPU 0 +#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F +#define BF_CLKCTRL_CPU_DIV_CPU(v) \ + (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) + +#define HW_CLKCTRL_HBUS (0x00000060) +#define HW_CLKCTRL_HBUS_SET (0x00000064) +#define HW_CLKCTRL_HBUS_CLR (0x00000068) +#define HW_CLKCTRL_HBUS_TOG (0x0000006c) + +#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000 +#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000 +#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000 +#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000 +#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000 +#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 +#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 +#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 +#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 +#define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000 +#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000 +#define BP_CLKCTRL_HBUS_SLOW_DIV 16 +#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 +#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 +#define BP_CLKCTRL_HBUS_RSRVD1 6 +#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 +#define BF_CLKCTRL_HBUS_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) +#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 +#define BP_CLKCTRL_HBUS_DIV 0 +#define BM_CLKCTRL_HBUS_DIV 0x0000001F +#define BF_CLKCTRL_HBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_HBUS_DIV) + +#define HW_CLKCTRL_XBUS (0x00000070) + +#define BM_CLKCTRL_XBUS_BUSY 0x80000000 +#define BP_CLKCTRL_XBUS_RSRVD1 12 +#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000 +#define BF_CLKCTRL_XBUS_RSRVD1(v) \ + (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1) +#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800 +#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_XBUS_DIV 0 +#define BM_CLKCTRL_XBUS_DIV 0x000003FF +#define BF_CLKCTRL_XBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_XBUS_DIV) + +#define HW_CLKCTRL_XTAL (0x00000080) +#define HW_CLKCTRL_XTAL_SET (0x00000084) +#define HW_CLKCTRL_XTAL_CLR (0x00000088) +#define HW_CLKCTRL_XTAL_TOG (0x0000008c) + +#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 +#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 +#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000 +#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 +#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 +#define BP_CLKCTRL_XTAL_RSRVD2 27 +#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000 +#define BF_CLKCTRL_XTAL_RSRVD2(v) \ + (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2) +#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 +#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 +#define BP_CLKCTRL_XTAL_RSRVD1 2 +#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC +#define BF_CLKCTRL_XTAL_RSRVD1(v) \ + (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) +#define BP_CLKCTRL_XTAL_DIV_UART 0 +#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 +#define BF_CLKCTRL_XTAL_DIV_UART(v) \ + (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) + +#define HW_CLKCTRL_SSP0 (0x00000090) + +#define BP_CLKCTRL_SSP0_CLKGATE 31 +#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP0_BUSY 0x20000000 +#define BP_CLKCTRL_SSP0_RSRVD1 10 +#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP0_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1) +#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP0_DIV 0 +#define BM_CLKCTRL_SSP0_DIV 0x000001FF +#define BF_CLKCTRL_SSP0_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP0_DIV) + +#define HW_CLKCTRL_SSP1 (0x000000a0) + +#define BP_CLKCTRL_SSP1_CLKGATE 31 +#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP1_BUSY 0x20000000 +#define BP_CLKCTRL_SSP1_RSRVD1 10 +#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP1_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1) +#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP1_DIV 0 +#define BM_CLKCTRL_SSP1_DIV 0x000001FF +#define BF_CLKCTRL_SSP1_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP1_DIV) + +#define HW_CLKCTRL_SSP2 (0x000000b0) + +#define BP_CLKCTRL_SSP2_CLKGATE 31 +#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP2_BUSY 0x20000000 +#define BP_CLKCTRL_SSP2_RSRVD1 10 +#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP2_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1) +#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP2_DIV 0 +#define BM_CLKCTRL_SSP2_DIV 0x000001FF +#define BF_CLKCTRL_SSP2_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP2_DIV) + +#define HW_CLKCTRL_SSP3 (0x000000c0) + +#define BP_CLKCTRL_SSP3_CLKGATE 31 +#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP3_BUSY 0x20000000 +#define BP_CLKCTRL_SSP3_RSRVD1 10 +#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP3_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1) +#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP3_DIV 0 +#define BM_CLKCTRL_SSP3_DIV 0x000001FF +#define BF_CLKCTRL_SSP3_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP3_DIV) + +#define HW_CLKCTRL_GPMI (0x000000d0) + +#define BP_CLKCTRL_GPMI_CLKGATE 31 +#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 +#define BM_CLKCTRL_GPMI_BUSY 0x20000000 +#define BP_CLKCTRL_GPMI_RSRVD1 11 +#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 +#define BF_CLKCTRL_GPMI_RSRVD1(v) \ + (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) +#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_GPMI_DIV 0 +#define BM_CLKCTRL_GPMI_DIV 0x000003FF +#define BF_CLKCTRL_GPMI_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_GPMI_DIV) + +#define HW_CLKCTRL_SPDIF (0x000000e0) + +#define BP_CLKCTRL_SPDIF_CLKGATE 31 +#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 +#define BP_CLKCTRL_SPDIF_RSRVD 0 +#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF +#define BF_CLKCTRL_SPDIF_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) + +#define HW_CLKCTRL_EMI (0x000000f0) + +#define BP_CLKCTRL_EMI_CLKGATE 31 +#define BM_CLKCTRL_EMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 +#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 +#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 +#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 +#define BP_CLKCTRL_EMI_RSRVD3 18 +#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 +#define BF_CLKCTRL_EMI_RSRVD3(v) \ + (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) +#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 +#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 +#define BP_CLKCTRL_EMI_RSRVD2 12 +#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 +#define BF_CLKCTRL_EMI_RSRVD2(v) \ + (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) +#define BP_CLKCTRL_EMI_DIV_XTAL 8 +#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 +#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ + (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) +#define BP_CLKCTRL_EMI_RSRVD1 6 +#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 +#define BF_CLKCTRL_EMI_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) +#define BP_CLKCTRL_EMI_DIV_EMI 0 +#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F +#define BF_CLKCTRL_EMI_DIV_EMI(v) \ + (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) + +#define HW_CLKCTRL_SAIF0 (0x00000100) + +#define BP_CLKCTRL_SAIF0_CLKGATE 31 +#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF0_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF0_RSRVD1 17 +#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF0_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1) +#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF0_DIV 0 +#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF0_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF0_DIV) + +#define HW_CLKCTRL_SAIF1 (0x00000110) + +#define BP_CLKCTRL_SAIF1_CLKGATE 31 +#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF1_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF1_RSRVD1 17 +#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF1_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1) +#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF1_DIV 0 +#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF1_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF1_DIV) + +#define HW_CLKCTRL_DIS_LCDIF (0x00000120) + +#define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31 +#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000 +#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000 +#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000 +#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14 +#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000 +#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \ + (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1) +#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000 +#define BP_CLKCTRL_DIS_LCDIF_DIV 0 +#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF +#define BF_CLKCTRL_DIS_LCDIF_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV) + +#define HW_CLKCTRL_ETM (0x00000130) + +#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 +#define BM_CLKCTRL_ETM_RSRVD2 0x40000000 +#define BM_CLKCTRL_ETM_BUSY 0x20000000 +#define BP_CLKCTRL_ETM_RSRVD1 8 +#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00 +#define BF_CLKCTRL_ETM_RSRVD1(v) \ + (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1) +#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080 +#define BP_CLKCTRL_ETM_DIV 0 +#define BM_CLKCTRL_ETM_DIV 0x0000007F +#define BF_CLKCTRL_ETM_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_ETM_DIV) + +#define HW_CLKCTRL_ENET (0x00000140) + +#define BM_CLKCTRL_ENET_SLEEP 0x80000000 +#define BP_CLKCTRL_ENET_DISABLE 30 +#define BM_CLKCTRL_ENET_DISABLE 0x40000000 +#define BM_CLKCTRL_ENET_STATUS 0x20000000 +#define BM_CLKCTRL_ENET_RSRVD1 0x10000000 +#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000 +#define BP_CLKCTRL_ENET_DIV_TIME 21 +#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000 +#define BF_CLKCTRL_ENET_DIV_TIME(v) \ + (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME) +#define BM_CLKCTRL_ENET_BUSY 0x08000000 +#define BP_CLKCTRL_ENET_DIV 21 +#define BM_CLKCTRL_ENET_DIV 0x07E00000 +#define BF_CLKCTRL_ENET_DIV(v) \ + (((v) << 21) & BM_CLKCTRL_ENET_DIV) +#define BP_CLKCTRL_ENET_TIME_SEL 19 +#define BM_CLKCTRL_ENET_TIME_SEL 0x00180000 +#define BF_CLKCTRL_ENET_TIME_SEL(v) \ + (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL) +#define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0 +#define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1 +#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2 +#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000 +#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000 +#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000 +#define BP_CLKCTRL_ENET_RSRVD0 0 +#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF +#define BF_CLKCTRL_ENET_RSRVD0(v) \ + (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0) + +#define HW_CLKCTRL_HSADC (0x00000150) + +#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000 +#define BM_CLKCTRL_HSADC_RESETB 0x40000000 +#define BP_CLKCTRL_HSADC_FREQDIV 28 +#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000 +#define BF_CLKCTRL_HSADC_FREQDIV(v) \ + (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV) +#define BP_CLKCTRL_HSADC_RSRVD1 0 +#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF +#define BF_CLKCTRL_HSADC_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1) + +#define HW_CLKCTRL_FLEXCAN (0x00000160) + +#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000 +#define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30 +#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000 +#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000 +#define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28 +#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000 +#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000 +#define BP_CLKCTRL_FLEXCAN_RSRVD1 0 +#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF +#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1) + +#define HW_CLKCTRL_FRAC0 (0x000001b0) +#define HW_CLKCTRL_FRAC0_SET (0x000001b4) +#define HW_CLKCTRL_FRAC0_CLR (0x000001b8) +#define HW_CLKCTRL_FRAC0_TOG (0x000001bc) + +#define BP_CLKCTRL_FRAC0_CLKGATEIO0 31 +#define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000 +#define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC0_IO0FRAC 24 +#define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000 +#define BF_CLKCTRL_FRAC0_IO0FRAC(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC) +#define BP_CLKCTRL_FRAC0_CLKGATEIO1 23 +#define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000 +#define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC0_IO1FRAC 16 +#define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000 +#define BF_CLKCTRL_FRAC0_IO1FRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC) +#define BP_CLKCTRL_FRAC0_CLKGATEEMI 15 +#define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000 +#define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC0_EMIFRAC 8 +#define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC0_EMIFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC) +#define BP_CLKCTRL_FRAC0_CLKGATECPU 7 +#define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080 +#define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC0_CPUFRAC 0 +#define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F +#define BF_CLKCTRL_FRAC0_CPUFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC) + +#define HW_CLKCTRL_FRAC1 (0x000001c0) +#define HW_CLKCTRL_FRAC1_SET (0x000001c4) +#define HW_CLKCTRL_FRAC1_CLR (0x000001c8) +#define HW_CLKCTRL_FRAC1_TOG (0x000001cc) + +#define BP_CLKCTRL_FRAC1_RSRVD2 24 +#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000 +#define BF_CLKCTRL_FRAC1_RSRVD2(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2) +#define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23 +#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000 +#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC1_GPMIFRAC 16 +#define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000 +#define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC) +#define BP_CLKCTRL_FRAC1_CLKGATEHSADC 15 +#define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000 +#define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC1_HSADCFRAC 8 +#define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC) +#define BP_CLKCTRL_FRAC1_CLKGATEPIX 7 +#define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080 +#define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC1_PIXFRAC 0 +#define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F +#define BF_CLKCTRL_FRAC1_PIXFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC) + +#define HW_CLKCTRL_CLKSEQ (0x000001d0) +#define HW_CLKCTRL_CLKSEQ_SET (0x000001d4) +#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8) +#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc) + +#define BP_CLKCTRL_CLKSEQ_RSRVD0 19 +#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000 +#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \ + (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0) +#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000 +#define BP_CLKCTRL_CLKSEQ_RSRVD1 15 +#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000 +#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ + (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1) +#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000 +#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1 +#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0 +#define BP_CLKCTRL_CLKSEQ_RSRVD2 9 +#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00 +#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \ + (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2) +#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 +#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008 +#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001 + +#define HW_CLKCTRL_RESET (0x000001e0) + +#define BP_CLKCTRL_RESET_RSRVD 6 +#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0 +#define BF_CLKCTRL_RESET_RSRVD(v) \ + (((v) << 6) & BM_CLKCTRL_RESET_RSRVD) +#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020 +#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010 +#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008 +#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004 +#define BM_CLKCTRL_RESET_CHIP 0x00000002 +#define BM_CLKCTRL_RESET_DIG 0x00000001 + +#define HW_CLKCTRL_STATUS (0x000001f0) + +#define BP_CLKCTRL_STATUS_CPU_LIMIT 30 +#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 +#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ + (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) +#define BP_CLKCTRL_STATUS_RSRVD 0 +#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF +#define BF_CLKCTRL_STATUS_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) + +#define HW_CLKCTRL_VERSION (0x00000200) + +#define BP_CLKCTRL_VERSION_MAJOR 24 +#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 +#define BF_CLKCTRL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) +#define BP_CLKCTRL_VERSION_MINOR 16 +#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 +#define BF_CLKCTRL_VERSION_MINOR(v) \ + (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) +#define BP_CLKCTRL_VERSION_STEP 0 +#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF +#define BF_CLKCTRL_VERSION_STEP(v) \ + (((v) << 0) & BM_CLKCTRL_VERSION_STEP) + +#endif /* __REGS_CLKCTRL_MX28_H__ */ diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c new file mode 100644 index 0000000..9343d7e --- /dev/null +++ b/arch/arm/mach-mxs/system.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/delay.h> +#include <linux/init.h> + +#include <asm/proc-fns.h> +#include <asm/system.h> + +#include <mach/mxs.h> +#include <mach/common.h> + +#define MX23_CLKCTRL_RESET_OFFSET 0x120 +#define MX28_CLKCTRL_RESET_OFFSET 0x1e0 +#define MXS_CLKCTRL_RESET_CHIP (1 << 1) + +#define MXS_MODULE_CLKGATE (1 << 30) +#define MXS_MODULE_SFTRST (1 << 31) + +static void __iomem *mxs_clkctrl_reset_addr; + +/* + * Reset the system. It is called by machine_restart(). + */ +void arch_reset(char mode, const char *cmd) +{ + /* reset the chip */ + __mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr); + + pr_err("Failed to assert the chip reset\n"); + + /* Delay to allow the serial port to show the message */ + mdelay(50); + + /* We'll take a jump through zero as a poor second */ + cpu_reset(0); +} + +static int __init mxs_arch_reset_init(void) +{ + struct clk *clk; + + mxs_clkctrl_reset_addr = MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR) + + (cpu_is_mx23() ? MX23_CLKCTRL_RESET_OFFSET : + MX28_CLKCTRL_RESET_OFFSET); + + clk = clk_get_sys("rtc", NULL); + if (!IS_ERR(clk)) + clk_enable(clk); + + return 0; +} +core_initcall(mxs_arch_reset_init); + +/* + * Clear the bit and poll it cleared. This is usually called with + * a reset address and mask being either SFTRST(bit 31) or CLKGATE + * (bit 30). + */ +static int clear_poll_bit(void __iomem *addr, u32 mask) +{ + int timeout = 0x400; + + /* clear the bit */ + __mxs_clrl(mask, addr); + + /* + * SFTRST needs 3 GPMI clocks to settle, the reference manual + * recommends to wait 1us. + */ + udelay(1); + + /* poll the bit becoming clear */ + while ((__raw_readl(addr) & mask) && --timeout) + /* nothing */; + + return !timeout; +} + +int mxs_reset_block(void __iomem *reset_addr) +{ + int ret; + int timeout = 0x400; + + /* clear and poll SFTRST */ + ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST); + if (unlikely(ret)) + goto error; + + /* clear CLKGATE */ + __mxs_clrl(MXS_MODULE_CLKGATE, reset_addr); + + /* set SFTRST to reset the block */ + __mxs_setl(MXS_MODULE_SFTRST, reset_addr); + udelay(1); + + /* poll CLKGATE becoming set */ + while ((!(__raw_readl(reset_addr) & MXS_MODULE_CLKGATE)) && --timeout) + /* nothing */; + if (unlikely(!timeout)) + goto error; + + /* clear and poll SFTRST */ + ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST); + if (unlikely(ret)) + goto error; + + /* clear and poll CLKGATE */ + ret = clear_poll_bit(reset_addr, MXS_MODULE_CLKGATE); + if (unlikely(ret)) + goto error; + + return 0; + +error: + pr_err("%s(%p): module reset timeout\n", __func__, reset_addr); + return -ETIMEDOUT; +} diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c new file mode 100644 index 0000000..13647f3 --- /dev/null +++ b/arch/arm/mach-mxs/timer.c @@ -0,0 +1,296 @@ +/* + * Copyright (C) 2000-2001 Deep Blue Solutions + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/clockchips.h> +#include <linux/clk.h> + +#include <asm/mach/time.h> +#include <mach/mxs.h> +#include <mach/common.h> + +/* + * There are 2 versions of the timrot on Freescale MXS-based SoCs. + * The v1 on MX23 only gets 16 bits counter, while v2 on MX28 + * extends the counter to 32 bits. + * + * The implementation uses two timers, one for clock_event and + * another for clocksource. MX28 uses timrot 0 and 1, while MX23 + * uses 0 and 2. + */ + +#define MX23_TIMROT_VERSION_OFFSET 0x0a0 +#define MX28_TIMROT_VERSION_OFFSET 0x120 +#define BP_TIMROT_MAJOR_VERSION 24 +#define BV_TIMROT_VERSION_1 0x01 +#define BV_TIMROT_VERSION_2 0x02 +#define timrot_is_v1() (timrot_major_version == BV_TIMROT_VERSION_1) + +/* + * There are 4 registers for each timrotv2 instance, and 2 registers + * for each timrotv1. So address step 0x40 in macros below strides + * one instance of timrotv2 while two instances of timrotv1. + * + * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1 + * on MX28 while timrot2 on MX23. + */ +/* common between v1 and v2 */ +#define HW_TIMROT_ROTCTRL 0x00 +#define HW_TIMROT_TIMCTRLn(n) (0x20 + (n) * 0x40) +/* v1 only */ +#define HW_TIMROT_TIMCOUNTn(n) (0x30 + (n) * 0x40) +/* v2 only */ +#define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40) +#define HW_TIMROT_FIXED_COUNTn(n) (0x40 + (n) * 0x40) + +#define BM_TIMROT_TIMCTRLn_RELOAD (1 << 6) +#define BM_TIMROT_TIMCTRLn_UPDATE (1 << 7) +#define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14) +#define BM_TIMROT_TIMCTRLn_IRQ (1 << 15) +#define BP_TIMROT_TIMCTRLn_SELECT 0 +#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 +#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb + +static struct clock_event_device mxs_clockevent_device; +static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED; + +static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR); +static u32 timrot_major_version; + +static inline void timrot_irq_disable(void) +{ + __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN, + mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); +} + +static inline void timrot_irq_enable(void) +{ + __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN, + mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); +} + +static void timrot_irq_acknowledge(void) +{ + __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ, + mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); +} + +static cycle_t timrotv1_get_cycles(struct clocksource *cs) +{ + return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1)) + & 0xffff0000) >> 16); +} + +static cycle_t timrotv2_get_cycles(struct clocksource *cs) +{ + return ~__raw_readl(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1)); +} + +static int timrotv1_set_next_event(unsigned long evt, + struct clock_event_device *dev) +{ + /* timrot decrements the count */ + __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0)); + + return 0; +} + +static int timrotv2_set_next_event(unsigned long evt, + struct clock_event_device *dev) +{ + /* timrot decrements the count */ + __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0)); + + return 0; +} + +static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + + timrot_irq_acknowledge(); + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction mxs_timer_irq = { + .name = "MXS Timer Tick", + .dev_id = &mxs_clockevent_device, + .flags = IRQF_TIMER | IRQF_IRQPOLL, + .handler = mxs_timer_interrupt, +}; + +#ifdef DEBUG +static const char *clock_event_mode_label[] const = { + [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", + [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", + [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", + [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED" +}; +#endif /* DEBUG */ + +static void mxs_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + /* Disable interrupt in timer module */ + timrot_irq_disable(); + + if (mode != mxs_clockevent_mode) { + /* Set event time into the furthest future */ + if (timrot_is_v1()) + __raw_writel(0xffff, + mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1)); + else + __raw_writel(0xffffffff, + mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1)); + + /* Clear pending interrupt */ + timrot_irq_acknowledge(); + } + +#ifdef DEBUG + pr_info("%s: changing mode from %s to %s\n", __func__, + clock_event_mode_label[mxs_clockevent_mode], + clock_event_mode_label[mode]); +#endif /* DEBUG */ + + /* Remember timer mode */ + mxs_clockevent_mode = mode; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + pr_err("%s: Periodic mode is not implemented\n", __func__); + break; + case CLOCK_EVT_MODE_ONESHOT: + timrot_irq_enable(); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + /* Left event sources disabled, no more interrupts appear */ + break; + } +} + +static struct clock_event_device mxs_clockevent_device = { + .name = "mxs_timrot", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_mode = mxs_set_mode, + .set_next_event = timrotv2_set_next_event, + .rating = 200, +}; + +static int __init mxs_clockevent_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + mxs_clockevent_device.mult = + div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift); + mxs_clockevent_device.cpumask = cpumask_of(0); + if (timrot_is_v1()) { + mxs_clockevent_device.set_next_event = timrotv1_set_next_event; + mxs_clockevent_device.max_delta_ns = + clockevent_delta2ns(0xfffe, &mxs_clockevent_device); + mxs_clockevent_device.min_delta_ns = + clockevent_delta2ns(0xf, &mxs_clockevent_device); + } else { + mxs_clockevent_device.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device); + mxs_clockevent_device.min_delta_ns = + clockevent_delta2ns(0xf, &mxs_clockevent_device); + } + + clockevents_register_device(&mxs_clockevent_device); + + return 0; +} + +static struct clocksource clocksource_mxs = { + .name = "mxs_timer", + .rating = 200, + .read = timrotv2_get_cycles, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int __init mxs_clocksource_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + if (timrot_is_v1()) { + clocksource_mxs.read = timrotv1_get_cycles; + clocksource_mxs.mask = CLOCKSOURCE_MASK(16); + } + + clocksource_register_hz(&clocksource_mxs, c); + + return 0; +} + +void __init mxs_timer_init(struct clk *timer_clk, int irq) +{ + clk_enable(timer_clk); + + /* + * Initialize timers to a known state + */ + mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL); + + /* get timrot version */ + timrot_major_version = __raw_readl(mxs_timrot_base + + (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET : + MX28_TIMROT_VERSION_OFFSET)); + timrot_major_version >>= BP_TIMROT_MAJOR_VERSION; + + /* one for clock_event */ + __raw_writel((timrot_is_v1() ? + BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL : + BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN, + mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); + + /* another for clocksource */ + __raw_writel((timrot_is_v1() ? + BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL : + BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) | + BM_TIMROT_TIMCTRLn_RELOAD, + mxs_timrot_base + HW_TIMROT_TIMCTRLn(1)); + + /* set clocksource timer fixed count to the maximum */ + if (timrot_is_v1()) + __raw_writel(0xffff, + mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1)); + else + __raw_writel(0xffffffff, + mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1)); + + /* init and register the timer to the framework */ + mxs_clocksource_init(timer_clk); + mxs_clockevent_init(timer_clk); + + /* Make irqs happen */ + setup_irq(irq, &mxs_timer_irq); +} diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index c897e03..6604fc6 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -51,6 +51,13 @@ config MACH_LINKSTATION_PRO Buffalo Linkstation Pro/Live platform. Both v1 and v2 devices are supported. +config MACH_LINKSTATION_LSCHL + bool "Buffalo Linkstation Live v3 (LS-CHL)" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + Buffalo Linkstation Live v3 (LS-CHL) platform. + config MACH_LINKSTATION_MINI bool "Buffalo Linkstation Mini" select I2C_BOARDINFO diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index eb6eabc..7f18cda 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o +obj-$(CONFIG_MACH_LINKSTATION_LSCHL) += ls-chl-setup.o diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c new file mode 100644 index 0000000..20a9b66 --- /dev/null +++ b/arch/arm/mach-orion5x/ls-chl-setup.c @@ -0,0 +1,327 @@ +/* + * arch/arm/mach-orion5x/ls-chl-setup.c + * + * Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/mv643xx_eth.h> +#include <linux/leds.h> +#include <linux/gpio_keys.h> +#include <linux/gpio-fan.h> +#include <linux/input.h> +#include <linux/i2c.h> +#include <linux/ata_platform.h> +#include <linux/gpio.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/system.h> +#include <mach/orion5x.h> +#include "common.h" +#include "mpp.h" + +/***************************************************************************** + * Linkstation LS-CHL Info + ****************************************************************************/ + +/* + * 256K NOR flash Device bus boot chip select + */ + +#define LSCHL_NOR_BOOT_BASE 0xf4000000 +#define LSCHL_NOR_BOOT_SIZE SZ_256K + +/***************************************************************************** + * 256KB NOR Flash on BOOT Device + ****************************************************************************/ + +static struct physmap_flash_data lschl_nor_flash_data = { + .width = 1, +}; + +static struct resource lschl_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = LSCHL_NOR_BOOT_BASE, + .end = LSCHL_NOR_BOOT_BASE + LSCHL_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device lschl_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &lschl_nor_flash_data, + }, + .num_resources = 1, + .resource = &lschl_nor_flash_resource, +}; + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data lschl_eth_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + +/***************************************************************************** + * RTC 5C372a on I2C bus + ****************************************************************************/ + +static struct i2c_board_info __initdata lschl_i2c_rtc = { + I2C_BOARD_INFO("rs5c372a", 0x32), +}; + +/***************************************************************************** + * LEDs attached to GPIO + ****************************************************************************/ + +#define LSCHL_GPIO_LED_ALARM 2 +#define LSCHL_GPIO_LED_INFO 3 +#define LSCHL_GPIO_LED_FUNC 17 +#define LSCHL_GPIO_LED_PWR 0 + +static struct gpio_led lschl_led_pins[] = { + { + .name = "alarm:red", + .gpio = LSCHL_GPIO_LED_ALARM, + .active_low = 1, + }, { + .name = "info:amber", + .gpio = LSCHL_GPIO_LED_INFO, + .active_low = 1, + }, { + .name = "func:blue:top", + .gpio = LSCHL_GPIO_LED_FUNC, + .active_low = 1, + }, { + .name = "power:blue:bottom", + .gpio = LSCHL_GPIO_LED_PWR, + }, +}; + +static struct gpio_led_platform_data lschl_led_data = { + .leds = lschl_led_pins, + .num_leds = ARRAY_SIZE(lschl_led_pins), +}; + +static struct platform_device lschl_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &lschl_led_data, + }, +}; + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct mv_sata_platform_data lschl_sata_data = { + .n_ports = 2, +}; + +/***************************************************************************** + * LS-CHL specific power off method: reboot + ****************************************************************************/ +/* + * On the LS-CHL, the shutdown process is following: + * - Userland monitors key events until the power switch goes to off position + * - The board reboots + * - U-boot starts and goes into an idle mode waiting for the user + * to move the switch to ON position + * + */ + +static void lschl_power_off(void) +{ + arm_machine_restart('h', NULL); +} + +/***************************************************************************** + * General Setup + ****************************************************************************/ +#define LSCHL_GPIO_USB_POWER 9 +#define LSCHL_GPIO_AUTO_POWER 17 +#define LSCHL_GPIO_POWER 18 + +/**************************************************************************** + * GPIO Attached Keys + ****************************************************************************/ +#define LSCHL_GPIO_KEY_FUNC 15 +#define LSCHL_GPIO_KEY_POWER 8 +#define LSCHL_GPIO_KEY_AUTOPOWER 10 +#define LSCHL_SW_POWER 0x00 +#define LSCHL_SW_AUTOPOWER 0x01 +#define LSCHL_SW_FUNC 0x02 + +static struct gpio_keys_button lschl_buttons[] = { + { + .type = EV_SW, + .code = LSCHL_SW_POWER, + .gpio = LSCHL_GPIO_KEY_POWER, + .desc = "Power-on Switch", + .active_low = 1, + }, { + .type = EV_SW, + .code = LSCHL_SW_AUTOPOWER, + .gpio = LSCHL_GPIO_KEY_AUTOPOWER, + .desc = "Power-auto Switch", + .active_low = 1, + }, { + .type = EV_SW, + .code = LSCHL_SW_FUNC, + .gpio = LSCHL_GPIO_KEY_FUNC, + .desc = "Function Switch", + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data lschl_button_data = { + .buttons = lschl_buttons, + .nbuttons = ARRAY_SIZE(lschl_buttons), +}; + +static struct platform_device lschl_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &lschl_button_data, + }, +}; + +#define LSCHL_GPIO_HDD_POWER 1 + +/**************************************************************************** + * GPIO Fan + ****************************************************************************/ + +#define LSCHL_GPIO_FAN_LOW 16 +#define LSCHL_GPIO_FAN_HIGH 14 +#define LSCHL_GPIO_FAN_LOCK 6 + +static struct gpio_fan_alarm lschl_alarm = { + .gpio = LSCHL_GPIO_FAN_LOCK, +}; + +static struct gpio_fan_speed lschl_speeds[] = { + { + .rpm = 0, + .ctrl_val = 3, + }, { + .rpm = 1500, + .ctrl_val = 2, + }, { + .rpm = 3250, + .ctrl_val = 1, + }, { + .rpm = 5000, + .ctrl_val = 0, + }, +}; + +static int lschl_gpio_list[] = { + LSCHL_GPIO_FAN_HIGH, LSCHL_GPIO_FAN_LOW, +}; + +static struct gpio_fan_platform_data lschl_fan_data = { + .num_ctrl = ARRAY_SIZE(lschl_gpio_list), + .ctrl = lschl_gpio_list, + .alarm = &lschl_alarm, + .num_speed = ARRAY_SIZE(lschl_speeds), + .speed = lschl_speeds, +}; + +static struct platform_device lschl_fan_device = { + .name = "gpio-fan", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &lschl_fan_data, + }, +}; + +/**************************************************************************** + * GPIO Data + ****************************************************************************/ + +static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = { + { 0, MPP_GPIO }, /* LED POWER */ + { 1, MPP_GPIO }, /* HDD POWER */ + { 2, MPP_GPIO }, /* LED ALARM */ + { 3, MPP_GPIO }, /* LED INFO */ + { 4, MPP_UNUSED }, + { 5, MPP_UNUSED }, + { 6, MPP_GPIO }, /* FAN LOCK */ + { 7, MPP_GPIO }, /* SW INIT */ + { 8, MPP_GPIO }, /* SW POWER */ + { 9, MPP_GPIO }, /* USB POWER */ + { 10, MPP_GPIO }, /* SW AUTO POWER */ + { 11, MPP_UNUSED }, + { 12, MPP_UNUSED }, + { 13, MPP_UNUSED }, + { 14, MPP_GPIO }, /* FAN HIGH */ + { 15, MPP_GPIO }, /* SW FUNC */ + { 16, MPP_GPIO }, /* FAN LOW */ + { 17, MPP_GPIO }, /* LED FUNC */ + { 18, MPP_UNUSED }, + { 19, MPP_UNUSED }, + { -1 }, +}; + +static void __init lschl_init(void) +{ + /* + * Setup basic Orion functions. Needs to be called early. + */ + orion5x_init(); + + orion5x_mpp_conf(lschl_mpp_modes); + + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + orion5x_ehci1_init(); + orion5x_eth_init(&lschl_eth_data); + orion5x_i2c_init(); + orion5x_sata_init(&lschl_sata_data); + orion5x_uart0_init(); + orion5x_xor_init(); + + orion5x_setup_dev_boot_win(LSCHL_NOR_BOOT_BASE, + LSCHL_NOR_BOOT_SIZE); + platform_device_register(&lschl_nor_flash); + + platform_device_register(&lschl_leds); + + platform_device_register(&lschl_button_device); + + platform_device_register(&lschl_fan_device); + + i2c_register_board_info(0, &lschl_i2c_rtc, 1); + + /* usb power on */ + gpio_set_value(LSCHL_GPIO_USB_POWER, 1); + + /* register power-off method */ + pm_power_off = lschl_power_off; + + pr_info("%s: finished\n", __func__); +} + +MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)") + /* Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk> */ + .boot_params = 0x00000100, + .init_machine = lschl_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32, +MACHINE_END diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index c98d81f..2fc9f94 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -50,6 +50,10 @@ config MACH_SAAR select PXA3xx select CPU_PXA930 +config MACH_SAARB + bool "PXA955 Handheld Platform (aka SAARB)" + select CPU_PXA955 + comment "Third Party Dev Platforms (sorted by vendor name)" config ARCH_PXA_IDP @@ -233,10 +237,6 @@ config MACH_COLIBRI bool "Toradex Colibri PXA270" select PXA27x -config MACH_COLIBRI_PXA270_EVALBOARD - bool "Toradex Colibri Evaluation Carrier Board support (PXA270)" - depends on MACH_COLIBRI - config MACH_COLIBRI_PXA270_INCOME bool "Income s.r.o. PXA270 SBC" depends on MACH_COLIBRI @@ -254,6 +254,10 @@ config MACH_COLIBRI320 select PXA3xx select CPU_PXA320 +config MACH_COLIBRI_EVALBOARD + bool "Toradex Colibri Evaluation Carrier Board support" + depends on MACH_COLIBRI || MACH_COLIBRI300 || MACH_COLIBRI320 + config MACH_VPAC270 bool "Voipac PXA270" select PXA27x @@ -653,11 +657,17 @@ config CPU_PXA935 help PXA935 (codename Tavor-P65) -config CPU_PXA950 +config PXA95x bool - select CPU_PXA930 + select CPU_PJ4 + help + Select code specific to PXA95x variants + +config CPU_PXA955 + bool + select PXA95x help - PXA950 (codename Tavor-PV2) + PXA950 (codename MG1) config PXA_SHARP_C7xx bool diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index e2f89c2..cc39d17 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -16,9 +16,10 @@ endif # Generic drivers that other drivers may depend upon # SoC-specific code -obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o -obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o -obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o +obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o +obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o +obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o +obj-$(CONFIG_PXA95x) += mfp-pxa3xx.o clock-pxa3xx.o pxa95x.o smemc.o obj-$(CONFIG_CPU_PXA300) += pxa300.o obj-$(CONFIG_CPU_PXA320) += pxa320.o obj-$(CONFIG_CPU_PXA930) += pxa930.o @@ -34,6 +35,7 @@ obj-$(CONFIG_MACH_LITTLETON) += littleton.o obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o obj-$(CONFIG_MACH_TAVOREVB3) += tavorevb3.o obj-$(CONFIG_MACH_SAAR) += saar.o +obj-$(CONFIG_MACH_SAARB) += saarb.o # 3rd Party Dev Platforms obj-$(CONFIG_ARCH_PXA_IDP) += idp.o @@ -60,7 +62,7 @@ obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o obj-$(CONFIG_MACH_PCM027) += pcm027.o obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o -obj-$(CONFIG_MACH_COLIBRI_PXA270_EVALBOARD) += colibri-pxa270-evalboard.o +obj-$(CONFIG_MACH_COLIBRI_EVALBOARD) += colibri-evalboard.o obj-$(CONFIG_MACH_COLIBRI_PXA270_INCOME) += colibri-pxa270-income.o obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index 21e1889..ccb2d0c 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -567,27 +567,29 @@ static inline void balloon3_i2c_init(void) {} * NAND ******************************************************************************/ #if defined(CONFIG_MTD_NAND_PLATFORM)||defined(CONFIG_MTD_NAND_PLATFORM_MODULE) -static uint16_t balloon3_ctl = - BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | - BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 | - BALLOON3_NAND_CONTROL_FLWP; - static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd->priv; + uint8_t balloon3_ctl_set = 0, balloon3_ctl_clr = 0; if (ctrl & NAND_CTRL_CHANGE) { if (ctrl & NAND_CLE) - balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCLE; + balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLCLE; else - balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLCLE; + balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLCLE; if (ctrl & NAND_ALE) - balloon3_ctl |= BALLOON3_NAND_CONTROL_FLALE; + balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLALE; else - balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLALE; - - __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG); + balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLALE; + + if (balloon3_ctl_clr) + __raw_writel(balloon3_ctl_clr, + BALLOON3_NAND_CONTROL_REG); + if (balloon3_ctl_set) + __raw_writel(balloon3_ctl_set, + BALLOON3_NAND_CONTROL_REG | + BALLOON3_FPGA_SETnCLR); } if (cmd != NAND_CMD_NONE) @@ -599,28 +601,33 @@ static void balloon3_nand_select_chip(struct mtd_info *mtd, int chip) if (chip < 0 || chip > 3) return; - balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCE0 | - BALLOON3_NAND_CONTROL_FLCE1 | - BALLOON3_NAND_CONTROL_FLCE2 | - BALLOON3_NAND_CONTROL_FLCE3; + /* Assert all nCE lines */ + __raw_writew( + BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | + BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3, + BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR); /* Deassert correct nCE line */ - balloon3_ctl &= ~(BALLOON3_NAND_CONTROL_FLCE0 << chip); + __raw_writew(BALLOON3_NAND_CONTROL_FLCE0 << chip, + BALLOON3_NAND_CONTROL_REG); +} - __raw_writew(balloon3_ctl, BALLOON3_NAND_CONTROL_REG); +static int balloon3_nand_dev_ready(struct mtd_info *mtd) +{ + return __raw_readl(BALLOON3_NAND_STAT_REG) & BALLOON3_NAND_STAT_RNB; } static int balloon3_nand_probe(struct platform_device *pdev) { - void __iomem *temp_map; uint16_t ver; int ret; - __raw_writew(BALLOON3_NAND_CONTROL2_16BIT, BALLOON3_NAND_CONTROL2_REG); + __raw_writew(BALLOON3_NAND_CONTROL2_16BIT, + BALLOON3_NAND_CONTROL2_REG | BALLOON3_FPGA_SETnCLR); ver = __raw_readw(BALLOON3_FPGA_VER); - if (ver > 0x0201) - pr_warn("The FPGA code, version 0x%04x, is newer than rel-0.3. " + if (ver < 0x4f08) + pr_warn("The FPGA code, version 0x%04x, is too old. " "NAND support might be broken in this version!", ver); /* Power up the NAND chips */ @@ -635,7 +642,11 @@ static int balloon3_nand_probe(struct platform_device *pdev) gpio_set_value(BALLOON3_GPIO_RUN_NAND, 1); /* Deassert all nCE lines and write protect line */ - __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG); + __raw_writel( + BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | + BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 | + BALLOON3_NAND_CONTROL_FLWP, + BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR); return 0; err2: @@ -677,7 +688,7 @@ struct platform_nand_data balloon3_nand_pdata = { }, .ctrl = { .hwcontrol = 0, - .dev_ready = 0, + .dev_ready = balloon3_nand_dev_ready, .select_chip = balloon3_nand_select_chip, .cmd_ctrl = balloon3_nand_cmd_ctl, .probe = balloon3_nand_probe, @@ -802,7 +813,7 @@ static struct map_desc balloon3_io_desc[] __initdata = { static void __init balloon3_map_io(void) { - pxa_map_io(); + pxa27x_map_io(); iotable_init(balloon3_io_desc, ARRAY_SIZE(balloon3_io_desc)); } diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c index 4bd7a3c..4284513 100644 --- a/arch/arm/mach-pxa/capc7117.c +++ b/arch/arm/mach-pxa/capc7117.c @@ -149,7 +149,7 @@ static void __init capc7117_init(void) MACHINE_START(CAPC7117, "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa3xx_map_io, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, .init_machine = capc7117_init diff --git a/arch/arm/mach-pxa/clock-pxa2xx.c b/arch/arm/mach-pxa/clock-pxa2xx.c new file mode 100644 index 0000000..1ce0904 --- /dev/null +++ b/arch/arm/mach-pxa/clock-pxa2xx.c @@ -0,0 +1,64 @@ +/* + * linux/arch/arm/mach-pxa/clock-pxa2xx.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/sysdev.h> + +#include <mach/pxa2xx-regs.h> + +#include "clock.h" + +void clk_pxa2xx_cken_enable(struct clk *clk) +{ + CKEN |= 1 << clk->cken; +} + +void clk_pxa2xx_cken_disable(struct clk *clk) +{ + CKEN &= ~(1 << clk->cken); +} + +const struct clkops clk_pxa2xx_cken_ops = { + .enable = clk_pxa2xx_cken_enable, + .disable = clk_pxa2xx_cken_disable, +}; + +#ifdef CONFIG_PM +static uint32_t saved_cken; + +static int pxa2xx_clock_suspend(struct sys_device *d, pm_message_t state) +{ + saved_cken = CKEN; + return 0; +} + +static int pxa2xx_clock_resume(struct sys_device *d) +{ + CKEN = saved_cken; + return 0; +} +#else +#define pxa2xx_clock_suspend NULL +#define pxa2xx_clock_resume NULL +#endif + +struct sysdev_class pxa2xx_clock_sysclass = { + .name = "pxa2xx-clock", + .suspend = pxa2xx_clock_suspend, + .resume = pxa2xx_clock_resume, +}; + +static int __init pxa2xx_clock_init(void) +{ + if (cpu_is_pxa2xx()) + return sysdev_class_register(&pxa2xx_clock_sysclass); + return 0; +} +postcore_initcall(pxa2xx_clock_init); diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c new file mode 100644 index 0000000..1b08a34 --- /dev/null +++ b/arch/arm/mach-pxa/clock-pxa3xx.c @@ -0,0 +1,218 @@ +/* + * linux/arch/arm/mach-pxa/clock-pxa3xx.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> + +#include <mach/smemc.h> +#include <mach/pxa3xx-regs.h> + +#include "clock.h" + +/* Crystal clock: 13MHz */ +#define BASE_CLK 13000000 + +/* Ring Oscillator Clock: 60MHz */ +#define RO_CLK 60000000 + +#define ACCR_D0CS (1 << 26) +#define ACCR_PCCE (1 << 11) + +/* crystal frequency to HSIO bus frequency multiplier (HSS) */ +static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; + +/* + * Get the clock frequency as reflected by CCSR and the turbo flag. + * We assume these values have been applied via a fcs. + * If info is not 0 we also display the current settings. + */ +unsigned int pxa3xx_get_clk_frequency_khz(int info) +{ + unsigned long acsr, xclkcfg; + unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; + + /* Read XCLKCFG register turbo bit */ + __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); + t = xclkcfg & 0x1; + + acsr = ACSR; + + xl = acsr & 0x1f; + xn = (acsr >> 8) & 0x7; + hss = (acsr >> 14) & 0x3; + + XL = xl * BASE_CLK; + XN = xn * XL; + + ro = acsr & ACCR_D0CS; + + CLK = (ro) ? RO_CLK : ((t) ? XN : XL); + HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; + + if (info) { + pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", + RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, + (ro) ? "" : "in"); + pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", + XL / 1000000, (XL % 1000000) / 10000, xl); + pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", + XN / 1000000, (XN % 1000000) / 10000, xn, + (t) ? "" : "in"); + pr_info("HSIO bus clock: %d.%02dMHz\n", + HSS / 1000000, (HSS % 1000000) / 10000); + } + + return CLK / 1000; +} + +/* + * Return the current AC97 clock frequency. + */ +static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) +{ + unsigned long rate = 312000000; + unsigned long ac97_div; + + ac97_div = AC97_DIV; + + /* This may loose precision for some rates but won't for the + * standard 24.576MHz. + */ + rate /= (ac97_div >> 12) & 0x7fff; + rate *= (ac97_div & 0xfff); + + return rate; +} + +/* + * Return the current HSIO bus clock frequency + */ +static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) +{ + unsigned long acsr; + unsigned int hss, hsio_clk; + + acsr = ACSR; + + hss = (acsr >> 14) & 0x3; + hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; + + return hsio_clk; +} + +/* crystal frequency to static memory controller multiplier (SMCFS) */ +static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; +static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 }; + +static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk) +{ + unsigned long acsr = ACSR; + unsigned long memclkcfg = __raw_readl(MEMCLKCFG); + unsigned int smcfs = (acsr >> 23) & 0x7; + + return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] / + df_clkdiv[(memclkcfg >> 16) & 0x3]; +} + +void clk_pxa3xx_cken_enable(struct clk *clk) +{ + unsigned long mask = 1ul << (clk->cken & 0x1f); + + if (clk->cken < 32) + CKENA |= mask; + else + CKENB |= mask; +} + +void clk_pxa3xx_cken_disable(struct clk *clk) +{ + unsigned long mask = 1ul << (clk->cken & 0x1f); + + if (clk->cken < 32) + CKENA &= ~mask; + else + CKENB &= ~mask; +} + +const struct clkops clk_pxa3xx_cken_ops = { + .enable = clk_pxa3xx_cken_enable, + .disable = clk_pxa3xx_cken_disable, +}; + +const struct clkops clk_pxa3xx_hsio_ops = { + .enable = clk_pxa3xx_cken_enable, + .disable = clk_pxa3xx_cken_disable, + .getrate = clk_pxa3xx_hsio_getrate, +}; + +const struct clkops clk_pxa3xx_ac97_ops = { + .enable = clk_pxa3xx_cken_enable, + .disable = clk_pxa3xx_cken_disable, + .getrate = clk_pxa3xx_ac97_getrate, +}; + +const struct clkops clk_pxa3xx_smemc_ops = { + .enable = clk_pxa3xx_cken_enable, + .disable = clk_pxa3xx_cken_disable, + .getrate = clk_pxa3xx_smemc_getrate, +}; + +static void clk_pout_enable(struct clk *clk) +{ + OSCC |= OSCC_PEN; +} + +static void clk_pout_disable(struct clk *clk) +{ + OSCC &= ~OSCC_PEN; +} + +const struct clkops clk_pxa3xx_pout_ops = { + .enable = clk_pout_enable, + .disable = clk_pout_disable, +}; + +#ifdef CONFIG_PM +static uint32_t cken[2]; +static uint32_t accr; + +static int pxa3xx_clock_suspend(struct sys_device *d, pm_message_t state) +{ + cken[0] = CKENA; + cken[1] = CKENB; + accr = ACCR; + return 0; +} + +static int pxa3xx_clock_resume(struct sys_device *d) +{ + ACCR = accr; + CKENA = cken[0]; + CKENB = cken[1]; + return 0; +} +#else +#define pxa3xx_clock_suspend NULL +#define pxa3xx_clock_resume NULL +#endif + +struct sysdev_class pxa3xx_clock_sysclass = { + .name = "pxa3xx-clock", + .suspend = pxa3xx_clock_suspend, + .resume = pxa3xx_clock_resume, +}; + +static int __init pxa3xx_clock_init(void) +{ + if (cpu_is_pxa3xx() || cpu_is_pxa95x()) + return sysdev_class_register(&pxa3xx_clock_sysclass); + return 0; +} +postcore_initcall(pxa3xx_clock_init); diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index 4e4a84b..d515222 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c @@ -3,21 +3,11 @@ */ #include <linux/module.h> #include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/string.h> #include <linux/clk.h> #include <linux/spinlock.h> -#include <linux/platform_device.h> #include <linux/delay.h> #include <linux/clkdev.h> -#include <mach/pxa2xx-regs.h> -#include <mach/hardware.h> - -#include "devices.h" -#include "generic.h" #include "clock.h" static DEFINE_SPINLOCK(clocks_lock); @@ -63,18 +53,19 @@ unsigned long clk_get_rate(struct clk *clk) } EXPORT_SYMBOL(clk_get_rate); - -void clk_cken_enable(struct clk *clk) +void clk_dummy_enable(struct clk *clk) { - CKEN |= 1 << clk->cken; } -void clk_cken_disable(struct clk *clk) +void clk_dummy_disable(struct clk *clk) { - CKEN &= ~(1 << clk->cken); } -const struct clkops clk_cken_ops = { - .enable = clk_cken_enable, - .disable = clk_cken_disable, +const struct clkops clk_dummy_ops = { + .enable = clk_dummy_enable, + .disable = clk_dummy_disable, +}; + +struct clk clk_dummy = { + .ops = &clk_dummy_ops, }; diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h index 12cc0e8..f9f349a 100644 --- a/arch/arm/mach-pxa/clock.h +++ b/arch/arm/mach-pxa/clock.h @@ -1,4 +1,5 @@ #include <linux/clkdev.h> +#include <linux/sysdev.h> struct clkops { void (*enable)(struct clk *); @@ -14,6 +15,12 @@ struct clk { unsigned int enabled; }; +void clk_dummy_enable(struct clk *); +void clk_dummy_disable(struct clk *); + +extern const struct clkops clk_dummy_ops; +extern struct clk clk_dummy; + #define INIT_CLKREG(_clk,_devname,_conname) \ { \ .clk = _clk, \ @@ -21,14 +28,6 @@ struct clk { .con_id = _conname, \ } -#define DEFINE_CKEN(_name, _cken, _rate, _delay) \ -struct clk clk_##_name = { \ - .ops = &clk_cken_ops, \ - .rate = _rate, \ - .cken = CKEN_##_cken, \ - .delay = _delay, \ - } - #define DEFINE_CK(_name, _cken, _ops) \ struct clk clk_##_name = { \ .ops = _ops, \ @@ -42,28 +41,38 @@ struct clk clk_##_name = { \ .delay = _delay, \ } -extern const struct clkops clk_cken_ops; - -void clk_cken_enable(struct clk *clk); -void clk_cken_disable(struct clk *clk); - -#ifdef CONFIG_PXA3xx -#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \ +#define DEFINE_PXA2_CKEN(_name, _cken, _rate, _delay) \ struct clk clk_##_name = { \ - .ops = &clk_pxa3xx_cken_ops, \ + .ops = &clk_pxa2xx_cken_ops, \ .rate = _rate, \ .cken = CKEN_##_cken, \ .delay = _delay, \ } -#define DEFINE_PXA3_CK(_name, _cken, _ops) \ +extern const struct clkops clk_pxa2xx_cken_ops; + +void clk_pxa2xx_cken_enable(struct clk *clk); +void clk_pxa2xx_cken_disable(struct clk *clk); + +extern struct sysdev_class pxa2xx_clock_sysclass; + +#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) +#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \ struct clk clk_##_name = { \ - .ops = _ops, \ + .ops = &clk_pxa3xx_cken_ops, \ + .rate = _rate, \ .cken = CKEN_##_cken, \ + .delay = _delay, \ } extern const struct clkops clk_pxa3xx_cken_ops; +extern const struct clkops clk_pxa3xx_hsio_ops; +extern const struct clkops clk_pxa3xx_ac97_ops; +extern const struct clkops clk_pxa3xx_pout_ops; +extern const struct clkops clk_pxa3xx_smemc_ops; + extern void clk_pxa3xx_cken_enable(struct clk *); extern void clk_pxa3xx_cken_disable(struct clk *); -#endif +extern struct sysdev_class pxa3xx_clock_sysclass; +#endif diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index d34b99f..b734d84 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c @@ -24,6 +24,7 @@ #include <mach/pxa2xx-regs.h> #include <mach/audio.h> #include <mach/pxafb.h> +#include <mach/smemc.h> #include <asm/hardware/it8152.h> @@ -392,9 +393,9 @@ static int cmx2xx_suspend(struct sys_device *dev, pm_message_t state) cmx2xx_pci_suspend(); /* save MSC registers */ - sleep_save_msc[0] = MSC0; - sleep_save_msc[1] = MSC1; - sleep_save_msc[2] = MSC2; + sleep_save_msc[0] = __raw_readl(MSC0); + sleep_save_msc[1] = __raw_readl(MSC1); + sleep_save_msc[2] = __raw_readl(MSC2); /* setup power saving mode registers */ PCFR = 0x0; @@ -416,9 +417,9 @@ static int cmx2xx_resume(struct sys_device *dev) cmx2xx_pci_resume(); /* restore MSC registers */ - MSC0 = sleep_save_msc[0]; - MSC1 = sleep_save_msc[1]; - MSC2 = sleep_save_msc[2]; + __raw_writel(sleep_save_msc[0], MSC0); + __raw_writel(sleep_save_msc[1], MSC1); + __raw_writel(sleep_save_msc[2], MSC2); return 0; } @@ -498,7 +499,12 @@ static struct map_desc cmx2xx_io_desc[] __initdata = { static void __init cmx2xx_map_io(void) { - pxa_map_io(); + if (cpu_is_pxa25x()) + pxa25x_map_io(); + + if (cpu_is_pxa27x()) + pxa27x_map_io(); + iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc)); it8152_base_address = CMX2XX_IT8152_VIRT; @@ -506,7 +512,11 @@ static void __init cmx2xx_map_io(void) #else static void __init cmx2xx_map_io(void) { - pxa_map_io(); + if (cpu_is_pxa25x()) + pxa25x_map_io(); + + if (cpu_is_pxa27x()) + pxa27x_map_io(); } #endif diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 922b107..7984268 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -857,7 +857,7 @@ static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags, MACHINE_START(CM_X300, "CM-X300 module") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa3xx_map_io, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, .init_machine = cm_x300_init, diff --git a/arch/arm/mach-pxa/colibri-pxa270-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c index 0f3b632..6b2c800 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-evalboard.c +++ b/arch/arm/mach-pxa/colibri-evalboard.c @@ -1,7 +1,7 @@ /* - * linux/arch/arm/mach-pxa/colibri-pxa270-evalboard.c + * linux/arch/arm/mach-pxa/colibri-evalboard.c * - * Support for Toradex PXA270 based Colibri Evaluation Carrier Board + * Support for Toradex Colibri Evaluation Carrier Board * Daniel Mack <daniel@caiaq.de> * Marek Vasut <marek.vasut@gmail.com> * @@ -19,6 +19,7 @@ #include <asm/mach-types.h> #include <mach/hardware.h> #include <asm/mach/arch.h> +#include <linux/i2c.h> #include <mach/pxa27x.h> #include <mach/colibri.h> @@ -26,86 +27,95 @@ #include <mach/ohci.h> #include <mach/pxa27x-udc.h> +#include <plat/i2c.h> + #include "generic.h" #include "devices.h" /****************************************************************************** - * Pin configuration - ******************************************************************************/ -static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = { - /* MMC */ - GPIO32_MMC_CLK, - GPIO92_MMC_DAT_0, - GPIO109_MMC_DAT_1, - GPIO110_MMC_DAT_2, - GPIO111_MMC_DAT_3, - GPIO112_MMC_CMD, - GPIO0_GPIO, /* SD detect */ - - /* FFUART */ - GPIO39_FFUART_TXD, - GPIO34_FFUART_RXD, - - /* UHC */ - GPIO88_USBH1_PWR, - GPIO89_USBH1_PEN, - GPIO119_USBH2_PWR, - GPIO120_USBH2_PEN, -}; - -/****************************************************************************** * SD/MMC card controller ******************************************************************************/ #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) -static struct pxamci_platform_data colibri_pxa270_mci_platform_data = { +static struct pxamci_platform_data colibri_mci_platform_data = { .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .gpio_power = -1, - .gpio_card_detect = GPIO0_COLIBRI_PXA270_SD_DETECT, .gpio_card_ro = -1, .detect_delay_ms = 200, }; -static void __init colibri_pxa270_mmc_init(void) +static void __init colibri_mmc_init(void) { - pxa_set_mci_info(&colibri_pxa270_mci_platform_data); + if (machine_is_colibri()) /* PXA270 Colibri */ + colibri_mci_platform_data.gpio_card_detect = + GPIO0_COLIBRI_PXA270_SD_DETECT; + if (machine_is_colibri300()) /* PXA300 Colibri */ + colibri_mci_platform_data.gpio_card_detect = + GPIO39_COLIBRI_PXA300_SD_DETECT; + else /* PXA320 Colibri */ + colibri_mci_platform_data.gpio_card_detect = + GPIO28_COLIBRI_PXA320_SD_DETECT; + + pxa_set_mci_info(&colibri_mci_platform_data); } #else -static inline void colibri_pxa270_mmc_init(void) {} +static inline void colibri_mmc_init(void) {} #endif /****************************************************************************** * USB Host ******************************************************************************/ #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) -static int colibri_pxa270_ohci_init(struct device *dev) +static int colibri_ohci_init(struct device *dev) { UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE; return 0; } -static struct pxaohci_platform_data colibri_pxa270_ohci_info = { +static struct pxaohci_platform_data colibri_ohci_info = { .port_mode = PMM_PERPORT_MODE, - .flags = ENABLE_PORT1 | ENABLE_PORT2 | + .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW, - .init = colibri_pxa270_ohci_init, + .init = colibri_ohci_init, }; -static void __init colibri_pxa270_uhc_init(void) +static void __init colibri_uhc_init(void) { - pxa_set_ohci_info(&colibri_pxa270_ohci_info); + /* Colibri PXA270 has two usb ports, TBA for 320 */ + if (machine_is_colibri()) + colibri_ohci_info.flags |= ENABLE_PORT2; + + pxa_set_ohci_info(&colibri_ohci_info); } #else -static inline void colibri_pxa270_uhc_init(void) {} +static inline void colibri_uhc_init(void) {} #endif -void __init colibri_pxa270_evalboard_init(void) +/****************************************************************************** + * I2C RTC + ******************************************************************************/ +#if defined(CONFIG_RTC_DRV_DS1307) || defined(CONFIG_RTC_DRV_DS1307_MODULE) +static struct i2c_board_info __initdata colibri_i2c_devs[] = { + { + I2C_BOARD_INFO("m41t00", 0x68), + }, +}; + +static void __init colibri_rtc_init(void) +{ + pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(colibri_i2c_devs)); +} +#else +static inline void colibri_rtc_init(void) {} +#endif + +void __init colibri_evalboard_init(void) { - pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_evalboard_pin_config)); pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); - colibri_pxa270_mmc_init(); - colibri_pxa270_uhc_init(); + colibri_mmc_init(); + colibri_uhc_init(); + colibri_rtc_init(); } - diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c index 37f0f3e..07b62a0 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-income.c +++ b/arch/arm/mach-pxa/colibri-pxa270-income.c @@ -46,52 +46,6 @@ #define GPIO113_INCOME_TS_IRQ (113) /****************************************************************************** - * Pin configuration - ******************************************************************************/ -static mfp_cfg_t income_pin_config[] __initdata = { - /* MMC */ - GPIO32_MMC_CLK, - GPIO92_MMC_DAT_0, - GPIO109_MMC_DAT_1, - GPIO110_MMC_DAT_2, - GPIO111_MMC_DAT_3, - GPIO112_MMC_CMD, - GPIO0_GPIO, /* SD detect */ - GPIO1_GPIO, /* SD read-only */ - - /* FFUART */ - GPIO39_FFUART_TXD, - GPIO34_FFUART_RXD, - - /* BFUART */ - GPIO42_BTUART_RXD, - GPIO43_BTUART_TXD, - GPIO45_BTUART_RTS, - - /* STUART */ - GPIO46_STUART_RXD, - GPIO47_STUART_TXD, - - /* UHC */ - GPIO88_USBH1_PWR, - GPIO89_USBH1_PEN, - - /* LCD */ - GPIOxx_LCD_TFT_16BPP, - - /* PWM */ - GPIO16_PWM0_OUT, - - /* I2C */ - GPIO117_I2C_SCL, - GPIO118_I2C_SDA, - - /* LED */ - GPIO54_GPIO, /* LED A */ - GPIO55_GPIO, /* LED B */ -}; - -/****************************************************************************** * SD/MMC card controller ******************************************************************************/ #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) @@ -257,7 +211,6 @@ static inline void income_pwm_init(void) {} void __init colibri_pxa270_income_boardinit(void) { - pxa2xx_mfp_config(ARRAY_AND_SIZE(income_pin_config)); pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c index bc04510..6fc5d32 100644 --- a/arch/arm/mach-pxa/colibri-pxa270.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c @@ -33,6 +33,103 @@ #include "generic.h" /****************************************************************************** + * Evaluation board MFP + ******************************************************************************/ +#ifdef CONFIG_MACH_COLIBRI_EVALBOARD +static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = { + /* MMC */ + GPIO32_MMC_CLK, + GPIO92_MMC_DAT_0, + GPIO109_MMC_DAT_1, + GPIO110_MMC_DAT_2, + GPIO111_MMC_DAT_3, + GPIO112_MMC_CMD, + GPIO0_GPIO, /* SD detect */ + + /* FFUART */ + GPIO39_FFUART_TXD, + GPIO34_FFUART_RXD, + + /* UHC */ + GPIO88_USBH1_PWR, + GPIO89_USBH1_PEN, + GPIO119_USBH2_PWR, + GPIO120_USBH2_PEN, + + /* PCMCIA */ + GPIO85_nPCE_1, + GPIO54_nPCE_2, + GPIO55_nPREG, + GPIO50_nPIOR, + GPIO51_nPIOW, + GPIO49_nPWE, + GPIO48_nPOE, + GPIO57_nIOIS16, + GPIO56_nPWAIT, + GPIO104_PSKTSEL, + GPIO53_GPIO, /* RESET */ + GPIO83_GPIO, /* BVD1 */ + GPIO82_GPIO, /* BVD2 */ + GPIO1_GPIO, /* READY */ + GPIO84_GPIO, /* DETECT */ + GPIO107_GPIO, /* PPEN */ + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, +}; +#else +static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = {}; +#endif + +#ifdef CONFIG_MACH_COLIBRI_PXA270_INCOME +static mfp_cfg_t income_pin_config[] __initdata = { + /* MMC */ + GPIO32_MMC_CLK, + GPIO92_MMC_DAT_0, + GPIO109_MMC_DAT_1, + GPIO110_MMC_DAT_2, + GPIO111_MMC_DAT_3, + GPIO112_MMC_CMD, + GPIO0_GPIO, /* SD detect */ + GPIO1_GPIO, /* SD read-only */ + + /* FFUART */ + GPIO39_FFUART_TXD, + GPIO34_FFUART_RXD, + + /* BFUART */ + GPIO42_BTUART_RXD, + GPIO43_BTUART_TXD, + GPIO45_BTUART_RTS, + + /* STUART */ + GPIO46_STUART_RXD, + GPIO47_STUART_TXD, + + /* UHC */ + GPIO88_USBH1_PWR, + GPIO89_USBH1_PEN, + + /* LCD */ + GPIOxx_LCD_TFT_16BPP, + + /* PWM */ + GPIO16_PWM0_OUT, + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + + /* LED */ + GPIO54_GPIO, /* LED A */ + GPIO55_GPIO, /* LED B */ +}; +#else +static mfp_cfg_t income_pin_config[] __initdata = {}; +#endif + +/****************************************************************************** * Pin configuration ******************************************************************************/ static mfp_cfg_t colibri_pxa270_pin_config[] __initdata = { @@ -184,10 +281,13 @@ static void __init colibri_pxa270_init(void) colibri_pxa270_tsc_init(); switch (colibri_pxa270_baseboard) { - case COLIBRI_PXA270_EVALBOARD: - colibri_pxa270_evalboard_init(); + case COLIBRI_EVALBOARD: + pxa2xx_mfp_config(ARRAY_AND_SIZE( + colibri_pxa270_evalboard_pin_config)); + colibri_evalboard_init(); break; case COLIBRI_PXA270_INCOME: + pxa2xx_mfp_config(ARRAY_AND_SIZE(income_pin_config)); colibri_pxa270_income_boardinit(); break; default: @@ -209,7 +309,7 @@ static void __init colibri_pxa270_income_init(void) MACHINE_START(COLIBRI, "Toradex Colibri PXA270") .boot_params = COLIBRI_SDRAM_BASE + 0x100, .init_machine = colibri_pxa270_init, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, MACHINE_END @@ -217,7 +317,7 @@ MACHINE_END MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC") .boot_params = 0xa0000100, .init_machine = colibri_pxa270_income_init, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, MACHINE_END diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c index a70b256..fddb16d 100644 --- a/arch/arm/mach-pxa/colibri-pxa300.c +++ b/arch/arm/mach-pxa/colibri-pxa300.c @@ -31,9 +31,38 @@ #include "generic.h" #include "devices.h" + +#ifdef CONFIG_MACH_COLIBRI_EVALBOARD +static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = { + /* MMC */ + GPIO7_MMC1_CLK, + GPIO14_MMC1_CMD, + GPIO3_MMC1_DAT0, + GPIO4_MMC1_DAT1, + GPIO5_MMC1_DAT2, + GPIO6_MMC1_DAT3, + GPIO39_GPIO, /* SD detect */ + + /* UHC */ + GPIO0_2_USBH_PEN, + GPIO1_2_USBH_PWR, + GPIO77_USB_P3_1, + GPIO78_USB_P3_2, + GPIO79_USB_P3_3, + GPIO80_USB_P3_4, + GPIO81_USB_P3_5, + GPIO82_USB_P3_6, + + /* I2C */ + GPIO21_I2C_SCL, + GPIO22_I2C_SDA, +}; +#else +static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = {}; +#endif + #if defined(CONFIG_AX88796) #define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO26_GPIO) - /* * Asix AX88796 Ethernet */ @@ -80,35 +109,6 @@ static void __init colibri_pxa300_init_eth(void) static inline void __init colibri_pxa300_init_eth(void) {} #endif /* CONFIG_AX88796 */ -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) -static mfp_cfg_t colibri_pxa300_usb_pin_config[] __initdata = { - GPIO0_2_USBH_PEN, - GPIO1_2_USBH_PWR, -}; - -static struct pxaohci_platform_data colibri_pxa300_ohci_info = { - .port_mode = PMM_GLOBAL_MODE, - .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW, -}; - -void __init colibri_pxa300_init_ohci(void) -{ - pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_usb_pin_config)); - pxa_set_ohci_info(&colibri_pxa300_ohci_info); -} -#else -static inline void colibri_pxa300_init_ohci(void) {} -#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */ - -static mfp_cfg_t colibri_pxa300_mmc_pin_config[] __initdata = { - GPIO7_MMC1_CLK, - GPIO14_MMC1_CMD, - GPIO3_MMC1_DAT0, - GPIO4_MMC1_DAT1, - GPIO5_MMC1_DAT2, - GPIO6_MMC1_DAT3, -}; - #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) static mfp_cfg_t colibri_pxa300_lcd_pin_config[] __initdata = { GPIO54_LCD_LDD_0, @@ -171,24 +171,21 @@ static inline void colibri_pxa310_init_ac97(void) {} void __init colibri_pxa300_init(void) { - pxa_set_ffuart_info(NULL); - pxa_set_btuart_info(NULL); - pxa_set_stuart_info(NULL); - colibri_pxa300_init_eth(); - colibri_pxa300_init_ohci(); colibri_pxa3xx_init_nand(); colibri_pxa300_init_lcd(); colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO39_GPIO)); colibri_pxa310_init_ac97(); - colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa300_mmc_pin_config), - mfp_to_gpio(MFP_PIN_GPIO13)); + + /* Evalboard init */ + pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_evalboard_pin_config)); + colibri_evalboard_init(); } MACHINE_START(COLIBRI300, "Toradex Colibri PXA300") .boot_params = COLIBRI_SDRAM_BASE + 0x100, .init_machine = colibri_pxa300_init, - .map_io = pxa_map_io, + .map_io = pxa3xx_map_io, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, MACHINE_END diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c index ca5f29e..ff9ff5f 100644 --- a/arch/arm/mach-pxa/colibri-pxa320.c +++ b/arch/arm/mach-pxa/colibri-pxa320.c @@ -35,9 +35,72 @@ #include "generic.h" #include "devices.h" +#ifdef CONFIG_MACH_COLIBRI_EVALBOARD +static mfp_cfg_t colibri_pxa320_evalboard_pin_config[] __initdata = { + /* MMC */ + GPIO22_MMC1_CLK, + GPIO23_MMC1_CMD, + GPIO18_MMC1_DAT0, + GPIO19_MMC1_DAT1, + GPIO20_MMC1_DAT2, + GPIO21_MMC1_DAT3, + GPIO28_GPIO, /* SD detect */ + + /* UART 1 configuration (may be set by bootloader) */ + GPIO99_UART1_CTS, + GPIO104_UART1_RTS, + GPIO97_UART1_RXD, + GPIO98_UART1_TXD, + GPIO101_UART1_DTR, + GPIO103_UART1_DSR, + GPIO100_UART1_DCD, + GPIO102_UART1_RI, + + /* UART 2 configuration */ + GPIO109_UART2_CTS, + GPIO112_UART2_RTS, + GPIO110_UART2_RXD, + GPIO111_UART2_TXD, + + /* UART 3 configuration */ + GPIO30_UART3_RXD, + GPIO31_UART3_TXD, + + /* UHC */ + GPIO2_2_USBH_PEN, + GPIO3_2_USBH_PWR, + + /* I2C */ + GPIO32_I2C_SCL, + GPIO33_I2C_SDA, + + /* PCMCIA */ + MFP_CFG(GPIO59, AF7), /* PRST ; AF7 to tristate */ + MFP_CFG(GPIO61, AF7), /* PCE1 ; AF7 to tristate */ + MFP_CFG(GPIO60, AF7), /* PCE2 ; AF7 to tristate */ + MFP_CFG(GPIO62, AF7), /* PCD ; AF7 to tristate */ + MFP_CFG(GPIO56, AF7), /* PSKTSEL ; AF7 to tristate */ + GPIO27_GPIO, /* RDnWR ; input/tristate */ + GPIO50_GPIO, /* PREG ; input/tristate */ + GPIO2_RDY, + GPIO5_NPIOR, + GPIO6_NPIOW, + GPIO7_NPIOS16, + GPIO8_NPWAIT, + GPIO29_GPIO, /* PRDY (READY GPIO) */ + GPIO57_GPIO, /* PPEN (POWER GPIO) */ + GPIO81_GPIO, /* PCD (DETECT GPIO) */ + GPIO77_GPIO, /* PRST (RESET GPIO) */ + GPIO53_GPIO, /* PBVD1 */ + GPIO79_GPIO, /* PBVD2 */ + GPIO54_GPIO, /* POE */ +}; +#else +static mfp_cfg_t colibri_pxa320_evalboard_pin_config[] __initdata = {}; +#endif + #if defined(CONFIG_AX88796) #define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO36_GPIO) - /* * Asix AX88796 Ethernet */ @@ -84,26 +147,6 @@ static void __init colibri_pxa320_init_eth(void) static inline void __init colibri_pxa320_init_eth(void) {} #endif /* CONFIG_AX88796 */ -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) -static mfp_cfg_t colibri_pxa320_usb_pin_config[] __initdata = { - GPIO2_2_USBH_PEN, - GPIO3_2_USBH_PWR, -}; - -static struct pxaohci_platform_data colibri_pxa320_ohci_info = { - .port_mode = PMM_GLOBAL_MODE, - .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW, -}; - -void __init colibri_pxa320_init_ohci(void) -{ - pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_usb_pin_config)); - pxa_set_ohci_info(&colibri_pxa320_ohci_info); -} -#else -static inline void colibri_pxa320_init_ohci(void) {} -#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */ - #if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE) static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = { .gpio_vbus = mfp_to_gpio(MFP_PIN_GPIO96), @@ -140,15 +183,6 @@ static void __init colibri_pxa320_init_udc(void) static inline void colibri_pxa320_init_udc(void) {} #endif -static mfp_cfg_t colibri_pxa320_mmc_pin_config[] __initdata = { - GPIO22_MMC1_CLK, - GPIO23_MMC1_CMD, - GPIO18_MMC1_DAT0, - GPIO19_MMC1_DAT1, - GPIO20_MMC1_DAT2, - GPIO21_MMC1_DAT3 -}; - #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) static mfp_cfg_t colibri_pxa320_lcd_pin_config[] __initdata = { GPIO6_2_LCD_LDD_0, @@ -205,59 +239,24 @@ static inline void __init colibri_pxa320_init_ac97(void) static inline void colibri_pxa320_init_ac97(void) {} #endif -/* - * The following configuration is verified to work with the Toradex Orchid - * carrier board - */ -static mfp_cfg_t colibri_pxa320_uart_pin_config[] __initdata = { - /* UART 1 configuration (may be set by bootloader) */ - GPIO99_UART1_CTS, - GPIO104_UART1_RTS, - GPIO97_UART1_RXD, - GPIO98_UART1_TXD, - GPIO101_UART1_DTR, - GPIO103_UART1_DSR, - GPIO100_UART1_DCD, - GPIO102_UART1_RI, - - /* UART 2 configuration */ - GPIO109_UART2_CTS, - GPIO112_UART2_RTS, - GPIO110_UART2_RXD, - GPIO111_UART2_TXD, - - /* UART 3 configuration */ - GPIO30_UART3_RXD, - GPIO31_UART3_TXD, -}; - -static void __init colibri_pxa320_init_uart(void) -{ - pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_uart_pin_config)); -} - void __init colibri_pxa320_init(void) { - pxa_set_ffuart_info(NULL); - pxa_set_btuart_info(NULL); - pxa_set_stuart_info(NULL); - colibri_pxa320_init_eth(); - colibri_pxa320_init_ohci(); colibri_pxa3xx_init_nand(); colibri_pxa320_init_lcd(); colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO49_GPIO)); colibri_pxa320_init_ac97(); - colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config), - mfp_to_gpio(MFP_PIN_GPIO28)); - colibri_pxa320_init_uart(); colibri_pxa320_init_udc(); + + /* Evalboard init */ + pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_evalboard_pin_config)); + colibri_evalboard_init(); } MACHINE_START(COLIBRI320, "Toradex Colibri PXA320") .boot_params = COLIBRI_SDRAM_BASE + 0x100, .init_machine = colibri_pxa320_init, - .map_io = pxa_map_io, + .map_io = pxa3xx_map_io, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, MACHINE_END diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index 199afa2..96b2d9f 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c @@ -64,55 +64,6 @@ void __init colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data) } #endif -#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) -static int mmc_detect_pin; - -static int colibri_pxa3xx_mci_init(struct device *dev, - irq_handler_t colibri_mmc_detect_int, - void *data) -{ - int ret; - - ret = gpio_request(mmc_detect_pin, "mmc card detect"); - if (ret) - return ret; - - gpio_direction_input(mmc_detect_pin); - ret = request_irq(gpio_to_irq(mmc_detect_pin), colibri_mmc_detect_int, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "MMC card detect", data); - if (ret) { - gpio_free(mmc_detect_pin); - return ret; - } - - return 0; -} - -static void colibri_pxa3xx_mci_exit(struct device *dev, void *data) -{ - free_irq(mmc_detect_pin, data); - gpio_free(gpio_to_irq(mmc_detect_pin)); -} - -static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = { - .detect_delay_ms = 200, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .init = colibri_pxa3xx_mci_init, - .exit = colibri_pxa3xx_mci_exit, - .gpio_card_detect = -1, - .gpio_card_ro = -1, - .gpio_power = -1, -}; - -void __init colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin) -{ - pxa3xx_mfp_config(pins, len); - mmc_detect_pin = detect_pin; - pxa_set_mci_info(&colibri_pxa3xx_mci_platform_data); -} -#endif /* CONFIG_MMC_PXA || CONFIG_MMC_PXA_MODULE */ - #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) static int lcd_bl_pin; diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 821229ac..9f3e5af 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -721,7 +721,7 @@ static void __init fixup_corgi(struct machine_desc *desc, #ifdef CONFIG_MACH_CORGI MACHINE_START(CORGI, "SHARP Corgi") .fixup = fixup_corgi, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .init_irq = pxa25x_init_irq, .init_machine = corgi_init, .timer = &pxa_timer, @@ -731,7 +731,7 @@ MACHINE_END #ifdef CONFIG_MACH_SHEPHERD MACHINE_START(SHEPHERD, "SHARP Shepherd") .fixup = fixup_corgi, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .init_irq = pxa25x_init_irq, .init_machine = corgi_init, .timer = &pxa_timer, @@ -741,7 +741,7 @@ MACHINE_END #ifdef CONFIG_MACH_HUSKY MACHINE_START(HUSKY, "SHARP Husky") .fixup = fixup_corgi, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .init_irq = pxa25x_init_irq, .init_machine = corgi_init, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c index 58093d9..6a7aeab 100644 --- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c +++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c @@ -38,8 +38,10 @@ #include <linux/cpufreq.h> #include <linux/err.h> #include <linux/regulator/consumer.h> +#include <linux/io.h> #include <mach/pxa2xx-regs.h> +#include <mach/smemc.h> #ifdef DEBUG static unsigned int freq_debug; @@ -242,7 +244,7 @@ static void pxa27x_guess_max_freq(void) static void init_sdram_rows(void) { - uint32_t mdcnfg = MDCNFG; + uint32_t mdcnfg = __raw_readl(MDCNFG); unsigned int drac2 = 0, drac0 = 0; if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3)) @@ -331,8 +333,8 @@ static int pxa_set_target(struct cpufreq_policy *policy, * we need to preset the smaller DRI before the change. If we're * speeding up we need to set the larger DRI value after the change. */ - preset_mdrefr = postset_mdrefr = MDREFR; - if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) { + preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR); + if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) { preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK); preset_mdrefr |= mdrefr_dri(new_freq_mem); } @@ -370,7 +372,7 @@ static int pxa_set_target(struct cpufreq_policy *policy, 3: nop \n\ " : "=&r" (unused) - : "r" (&MDREFR), "r" (cclkcfg), + : "r" (MDREFR), "r" (cclkcfg), "r" (preset_mdrefr), "r" (postset_mdrefr) : "r4", "r5"); local_irq_restore(flags); diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c index 57cacaf..a305424 100644 --- a/arch/arm/mach-pxa/csb726.c +++ b/arch/arm/mach-pxa/csb726.c @@ -27,6 +27,7 @@ #include <mach/ohci.h> #include <mach/pxa2xx-regs.h> #include <mach/audio.h> +#include <mach/smemc.h> #include "generic.h" #include "devices.h" @@ -255,9 +256,9 @@ static struct platform_device *devices[] __initdata = { static void __init csb726_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(csb726_pin_config)); -/* MSC1 = 0x7ffc3ffc; *//* LAN9215/EXP_CS */ -/* MSC2 = 0x06697ff4; *//* none/SM501 */ - MSC2 = (MSC2 & ~0xffff) | 0x7ff4; /* SM501 */ +/* __raw_writel(0x7ffc3ffc, MSC1); *//* LAN9215/EXP_CS */ +/* __raw_writel(0x06697ff4, MSC2); *//* none/SM501 */ + __raw_writel((__raw_readl(MSC2) & ~0xffff) | 0x7ff4, MSC2); /* SM501 */ pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); @@ -273,7 +274,7 @@ static void __init csb726_init(void) MACHINE_START(CSB726, "Cogent CSB726") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .init_irq = pxa27x_init_irq, .init_machine = csb726_init, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index aaa1166..022c2fa 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -342,27 +342,6 @@ struct platform_device pxa27x_device_i2c_power = { }; #endif -#ifdef CONFIG_PXA3xx -static struct resource pxa3xx_resources_i2c_power[] = { - { - .start = 0x40f500c0, - .end = 0x40f500d3, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PWRI2C, - .end = IRQ_PWRI2C, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa3xx_device_i2c_power = { - .name = "pxa3xx-pwri2c", - .id = 1, - .resource = pxa3xx_resources_i2c_power, - .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power), -}; -#endif - static struct resource pxai2s_resources[] = { { .start = 0x40400000, @@ -633,30 +612,35 @@ struct platform_device pxa25x_device_assp = { #endif /* CONFIG_PXA25x */ #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) - -static struct resource pxa27x_resource_keypad[] = { +static struct resource pxa27x_resource_camera[] = { [0] = { - .start = 0x41500000, - .end = 0x4150004c, + .start = 0x50000000, + .end = 0x50000fff, .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_KEYPAD, - .end = IRQ_KEYPAD, + .start = IRQ_CAMERA, + .end = IRQ_CAMERA, .flags = IORESOURCE_IRQ, }, }; -struct platform_device pxa27x_device_keypad = { - .name = "pxa27x-keypad", - .id = -1, - .resource = pxa27x_resource_keypad, - .num_resources = ARRAY_SIZE(pxa27x_resource_keypad), +static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32); + +static struct platform_device pxa27x_device_camera = { + .name = "pxa27x-camera", + .id = 0, /* This is used to put cameras on this interface */ + .dev = { + .dma_mask = &pxa27x_dma_mask_camera, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(pxa27x_resource_camera), + .resource = pxa27x_resource_camera, }; -void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info) +void __init pxa_set_camera_info(struct pxacamera_platform_data *info) { - pxa_register_device(&pxa27x_device_keypad, info); + pxa_register_device(&pxa27x_device_camera, info); } static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32); @@ -689,6 +673,33 @@ void __init pxa_set_ohci_info(struct pxaohci_platform_data *info) { pxa_register_device(&pxa27x_device_ohci, info); } +#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ + +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) +static struct resource pxa27x_resource_keypad[] = { + [0] = { + .start = 0x41500000, + .end = 0x4150004c, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_KEYPAD, + .end = IRQ_KEYPAD, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa27x_device_keypad = { + .name = "pxa27x-keypad", + .id = -1, + .resource = pxa27x_resource_keypad, + .num_resources = ARRAY_SIZE(pxa27x_resource_keypad), +}; + +void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info) +{ + pxa_register_device(&pxa27x_device_keypad, info); +} static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32); @@ -833,79 +844,9 @@ struct platform_device pxa27x_device_pwm1 = { .resource = pxa27x_resource_pwm1, .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1), }; - -static struct resource pxa27x_resource_camera[] = { - [0] = { - .start = 0x50000000, - .end = 0x50000fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CAMERA, - .end = IRQ_CAMERA, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32); - -static struct platform_device pxa27x_device_camera = { - .name = "pxa27x-camera", - .id = 0, /* This is used to put cameras on this interface */ - .dev = { - .dma_mask = &pxa27x_dma_mask_camera, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(pxa27x_resource_camera), - .resource = pxa27x_resource_camera, -}; - -void __init pxa_set_camera_info(struct pxacamera_platform_data *info) -{ - pxa_register_device(&pxa27x_device_camera, info); -} -#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ +#endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/ #ifdef CONFIG_PXA3xx -static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32); - -static struct resource pxa3xx_resource_ssp4[] = { - [0] = { - .start = 0x41a00000, - .end = 0x41a0003f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SSP4, - .end = IRQ_SSP4, - .flags = IORESOURCE_IRQ, - }, - [2] = { - /* DRCMR for RX */ - .start = 2, - .end = 2, - .flags = IORESOURCE_DMA, - }, - [3] = { - /* DRCMR for TX */ - .start = 3, - .end = 3, - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device pxa3xx_device_ssp4 = { - /* PXA3xx SSP is basically equivalent to PXA27x */ - .name = "pxa27x-ssp", - .id = 3, - .dev = { - .dma_mask = &pxa3xx_ssp4_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = pxa3xx_resource_ssp4, - .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4), -}; - static struct resource pxa3xx_resources_mci2[] = { [0] = { .start = 0x42000000, @@ -984,6 +925,54 @@ void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info) pxa_register_device(&pxa3xx_device_mci3, info); } +static struct resource pxa3xx_resources_gcu[] = { + { + .start = 0x54000000, + .end = 0x54000fff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_GCU, + .end = IRQ_GCU, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32); + +struct platform_device pxa3xx_device_gcu = { + .name = "pxa3xx-gcu", + .id = -1, + .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu), + .resource = pxa3xx_resources_gcu, + .dev = { + .dma_mask = &pxa3xx_gcu_dmamask, + .coherent_dma_mask = 0xffffffff, + }, +}; + +#endif /* CONFIG_PXA3xx */ + +#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) +static struct resource pxa3xx_resources_i2c_power[] = { + { + .start = 0x40f500c0, + .end = 0x40f500d3, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_PWRI2C, + .end = IRQ_PWRI2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa3xx_device_i2c_power = { + .name = "pxa3xx-pwri2c", + .id = 1, + .resource = pxa3xx_resources_i2c_power, + .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power), +}; + static struct resource pxa3xx_resources_nand[] = { [0] = { .start = 0x43100000, @@ -1027,33 +1016,45 @@ void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info) pxa_register_device(&pxa3xx_device_nand, info); } -static struct resource pxa3xx_resources_gcu[] = { - { - .start = 0x54000000, - .end = 0x54000fff, +static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32); + +static struct resource pxa3xx_resource_ssp4[] = { + [0] = { + .start = 0x41a00000, + .end = 0x41a0003f, .flags = IORESOURCE_MEM, }, - { - .start = IRQ_GCU, - .end = IRQ_GCU, + [1] = { + .start = IRQ_SSP4, + .end = IRQ_SSP4, .flags = IORESOURCE_IRQ, }, + [2] = { + /* DRCMR for RX */ + .start = 2, + .end = 2, + .flags = IORESOURCE_DMA, + }, + [3] = { + /* DRCMR for TX */ + .start = 3, + .end = 3, + .flags = IORESOURCE_DMA, + }, }; -static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32); - -struct platform_device pxa3xx_device_gcu = { - .name = "pxa3xx-gcu", - .id = -1, - .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu), - .resource = pxa3xx_resources_gcu, +struct platform_device pxa3xx_device_ssp4 = { + /* PXA3xx SSP is basically equivalent to PXA27x */ + .name = "pxa27x-ssp", + .id = 3, .dev = { - .dma_mask = &pxa3xx_gcu_dmamask, - .coherent_dma_mask = 0xffffffff, + .dma_mask = &pxa3xx_ssp4_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), }, + .resource = pxa3xx_resource_ssp4, + .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4), }; - -#endif /* CONFIG_PXA3xx */ +#endif /* CONFIG_PXA3xx || CONFIG_PXA95x */ /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */ diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index ed0dbfdb..4cefd1d 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -1300,7 +1300,7 @@ static void __init em_x270_init(void) MACHINE_START(EM_X270, "Compulab EM-X270") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = em_x270_init, @@ -1308,7 +1308,7 @@ MACHINE_END MACHINE_START(EXEDA, "Compulab eXeda") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = em_x270_init, diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index b25690c..edca0a0 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -181,7 +181,7 @@ static void __init e330_init(void) MACHINE_START(E330, "Toshiba e330") /* Maintainer: Ian Molton (spyro@f2s.com) */ .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .nr_irqs = ESERIES_NR_IRQS, .init_irq = pxa25x_init_irq, .fixup = eseries_fixup, @@ -230,7 +230,7 @@ static void __init e350_init(void) MACHINE_START(E350, "Toshiba e350") /* Maintainer: Ian Molton (spyro@f2s.com) */ .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .nr_irqs = ESERIES_NR_IRQS, .init_irq = pxa25x_init_irq, .fixup = eseries_fixup, @@ -352,7 +352,7 @@ static void __init e400_init(void) MACHINE_START(E400, "Toshiba e400") /* Maintainer: Ian Molton (spyro@f2s.com) */ .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .nr_irqs = ESERIES_NR_IRQS, .init_irq = pxa25x_init_irq, .fixup = eseries_fixup, @@ -540,7 +540,7 @@ static void __init e740_init(void) MACHINE_START(E740, "Toshiba e740") /* Maintainer: Ian Molton (spyro@f2s.com) */ .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .nr_irqs = ESERIES_NR_IRQS, .init_irq = pxa25x_init_irq, .fixup = eseries_fixup, @@ -731,7 +731,7 @@ static void __init e750_init(void) MACHINE_START(E750, "Toshiba e750") /* Maintainer: Ian Molton (spyro@f2s.com) */ .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .nr_irqs = ESERIES_NR_IRQS, .init_irq = pxa25x_init_irq, .fixup = eseries_fixup, @@ -926,7 +926,7 @@ static void __init e800_init(void) MACHINE_START(E800, "Toshiba e800") /* Maintainer: Ian Molton (spyro@f2s.com) */ .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .nr_irqs = ESERIES_NR_IRQS, .init_irq = pxa25x_init_irq, .fixup = eseries_fixup, diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 142c711..87cec0a 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -798,7 +798,7 @@ static void __init a780_init(void) MACHINE_START(EZX_A780, "Motorola EZX A780") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, @@ -863,7 +863,7 @@ static void __init e680_init(void) MACHINE_START(EZX_E680, "Motorola EZX E680") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, @@ -928,7 +928,7 @@ static void __init a1200_init(void) MACHINE_START(EZX_A1200, "Motorola EZX A1200") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, @@ -1118,7 +1118,7 @@ static void __init a910_init(void) MACHINE_START(EZX_A910, "Motorola EZX A910") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, @@ -1183,7 +1183,7 @@ static void __init e6_init(void) MACHINE_START(EZX_E6, "Motorola EZX E6") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, @@ -1222,7 +1222,7 @@ static void __init e2_init(void) MACHINE_START(EZX_E2, "Motorola EZX E2") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 6451e9c..d6e15f7 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -28,6 +28,8 @@ #include <mach/reset.h> #include <mach/gpio.h> +#include <mach/smemc.h> +#include <mach/pxa3xx-regs.h> #include "generic.h" @@ -35,9 +37,10 @@ void clear_reset_status(unsigned int mask) { if (cpu_is_pxa2xx()) pxa2xx_clear_reset_status(mask); - - if (cpu_is_pxa3xx()) - pxa3xx_clear_reset_status(mask); + else { + /* RESET_STATUS_* has a 1:1 mapping with ARSR */ + ARSR = mask; + } } unsigned long get_clock_tick_rate(void) @@ -71,47 +74,17 @@ unsigned int get_clk_frequency_khz(int info) EXPORT_SYMBOL(get_clk_frequency_khz); /* - * Return the current memory clock frequency in units of 10kHz - */ -unsigned int get_memclk_frequency_10khz(void) -{ - if (cpu_is_pxa25x()) - return pxa25x_get_memclk_frequency_10khz(); - else if (cpu_is_pxa27x()) - return pxa27x_get_memclk_frequency_10khz(); - return 0; -} -EXPORT_SYMBOL(get_memclk_frequency_10khz); - -/* * Intel PXA2xx internal register mapping. * - * Note 1: not all PXA2xx variants implement all those addresses. - * - * Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table - * and cache flush area. + * Note: virtual 0xfffe0000-0xffffffff is reserved for the vector table + * and cache flush area. */ -static struct map_desc standard_io_desc[] __initdata = { +static struct map_desc common_io_desc[] __initdata = { { /* Devs */ .virtual = 0xf2000000, .pfn = __phys_to_pfn(0x40000000), .length = 0x02000000, .type = MT_DEVICE - }, { /* Mem Ctl */ - .virtual = 0xf6000000, - .pfn = __phys_to_pfn(0x48000000), - .length = 0x00200000, - .type = MT_DEVICE - }, { /* Camera */ - .virtual = 0xfa000000, - .pfn = __phys_to_pfn(0x50000000), - .length = 0x00100000, - .type = MT_DEVICE - }, { /* IMem ctl */ - .virtual = 0xfe000000, - .pfn = __phys_to_pfn(0x58000000), - .length = 0x00100000, - .type = MT_DEVICE }, { /* UNCACHED_PHYS_0 */ .virtual = 0xff000000, .pfn = __phys_to_pfn(0x00000000), @@ -122,6 +95,5 @@ static struct map_desc standard_io_desc[] __initdata = { void __init pxa_map_io(void) { - iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); - get_clk_frequency_khz(1); + iotable_init(ARRAY_AND_SIZE(common_io_desc)); } diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 4b1ad27..6205dc9 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -20,7 +20,12 @@ extern void __init pxa26x_init_irq(void); #endif extern void __init pxa27x_init_irq(void); extern void __init pxa3xx_init_irq(void); +extern void __init pxa95x_init_irq(void); + extern void __init pxa_map_io(void); +extern void __init pxa25x_map_io(void); +extern void __init pxa27x_map_io(void); +extern void __init pxa3xx_map_io(void); extern unsigned int get_clk_frequency_khz(int info); @@ -32,18 +37,14 @@ extern unsigned int get_clk_frequency_khz(int info); #ifdef CONFIG_PXA25x extern unsigned pxa25x_get_clk_frequency_khz(int); -extern unsigned pxa25x_get_memclk_frequency_10khz(void); #else #define pxa25x_get_clk_frequency_khz(x) (0) -#define pxa25x_get_memclk_frequency_10khz() (0) #endif #ifdef CONFIG_PXA27x extern unsigned pxa27x_get_clk_frequency_khz(int); -extern unsigned pxa27x_get_memclk_frequency_10khz(void); #else #define pxa27x_get_clk_frequency_khz(x) (0) -#define pxa27x_get_memclk_frequency_10khz() (0) #endif #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) @@ -54,10 +55,8 @@ static inline void pxa2xx_clear_reset_status(unsigned int mask) {} #ifdef CONFIG_PXA3xx extern unsigned pxa3xx_get_clk_frequency_khz(int); -extern void pxa3xx_clear_reset_status(unsigned int); #else #define pxa3xx_get_clk_frequency_khz(x) (0) -static inline void pxa3xx_clear_reset_status(unsigned int mask) {} #endif extern struct sysdev_class pxa_irq_sysclass; diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index 1e2a9a1..6fd319e 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c @@ -225,7 +225,7 @@ static void __init gumstix_init(void) MACHINE_START(GUMSTIX, "Gumstix") .boot_params = 0xa0000100, /* match u-boot bi_boot_params */ - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .init_irq = pxa25x_init_irq, .timer = &pxa_timer, .init_machine = gumstix_init, diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c index 7057a1f..657db46 100644 --- a/arch/arm/mach-pxa/h5000.c +++ b/arch/arm/mach-pxa/h5000.c @@ -32,6 +32,7 @@ #include <mach/pxa25x.h> #include <mach/h5000.h> #include <mach/udc.h> +#include <mach/smemc.h> #include "generic.h" @@ -172,11 +173,11 @@ static unsigned long h5000_pin_config[] __initdata = { static void fix_msc(void) { - MSC0 = 0x129c24f2; - MSC1 = 0x7ff424fa; - MSC2 = 0x7ff47ff4; + __raw_writel(0x129c24f2, MSC0); + __raw_writel(0x7ff424fa, MSC1); + __raw_writel(0x7ff47ff4, MSC2); - MDREFR |= 0x02080000; + __raw_writel(__raw_readl(MDREFR) | 0x02080000, MDREFR); } /* @@ -202,7 +203,7 @@ static void __init h5000_init(void) MACHINE_START(H5400, "HP iPAQ H5000") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .init_irq = pxa25x_init_irq, .timer = &pxa_timer, .init_machine = h5000_init, diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c index 01b7f07..e8603eb 100644 --- a/arch/arm/mach-pxa/himalaya.c +++ b/arch/arm/mach-pxa/himalaya.c @@ -160,7 +160,7 @@ static void __init himalaya_init(void) MACHINE_START(HIMALAYA, "HTC Himalaya") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .init_irq = pxa25x_init_irq, .init_machine = himalaya_init, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 76d93a2..cacb21b 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -871,7 +871,7 @@ static void __init hx4700_init(void) MACHINE_START(H4700, "HP iPAQ HX4700") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .nr_irqs = HX4700_NR_IRQS, .init_irq = pxa27x_init_irq, .init_machine = hx4700_init, diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c index d51ee3d..ac6ee12 100644 --- a/arch/arm/mach-pxa/icontrol.c +++ b/arch/arm/mach-pxa/icontrol.c @@ -192,7 +192,7 @@ static void __init icontrol_init(void) MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa3xx_map_io, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, .init_machine = icontrol_init diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index e773dce..dd40e4a 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -187,7 +187,7 @@ static struct map_desc idp_io_desc[] __initdata = { static void __init idp_map_io(void) { - pxa_map_io(); + pxa25x_map_io(); iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc)); } diff --git a/arch/arm/mach-pxa/include/mach/addr-map.h b/arch/arm/mach-pxa/include/mach/addr-map.h new file mode 100644 index 0000000..f4c0365 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/addr-map.h @@ -0,0 +1,48 @@ +#ifndef __ASM_MACH_ADDR_MAP_H +#define __ASM_MACH_ADDR_MAP_H + +/* + * Chip Selects + */ +#define PXA_CS0_PHYS 0x00000000 +#define PXA_CS1_PHYS 0x04000000 +#define PXA_CS2_PHYS 0x08000000 +#define PXA_CS3_PHYS 0x0C000000 +#define PXA_CS4_PHYS 0x10000000 +#define PXA_CS5_PHYS 0x14000000 + +#define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */ +#define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */ +#define PXA3xx_CS2_PHYS 0x10000000 +#define PXA3xx_CS3_PHYS 0x14000000 + +/* + * Peripheral Bus + */ +#define PERIPH_PHYS 0x40000000 +#define PERIPH_VIRT 0xf2000000 +#define PERIPH_SIZE 0x02000000 + +/* + * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x) + */ +#define PXA2XX_SMEMC_PHYS 0x48000000 +#define PXA3XX_SMEMC_PHYS 0x4a000000 +#define SMEMC_VIRT 0xf6000000 +#define SMEMC_SIZE 0x00100000 + +/* + * Dynamic Memory Controller (only on PXA3xx) + */ +#define DMEMC_PHYS 0x48100000 +#define DMEMC_VIRT 0xf6100000 +#define DMEMC_SIZE 0x00100000 + +/* + * Internal Memory Controller (PXA27x and later) + */ +#define IMEMC_PHYS 0x58000000 +#define IMEMC_VIRT 0xfe000000 +#define IMEMC_SIZE 0x00100000 + +#endif /* __ASM_MACH_ADDR_MAP_H */ diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h index 561562b..7074e76 100644 --- a/arch/arm/mach-pxa/include/mach/balloon3.h +++ b/arch/arm/mach-pxa/include/mach/balloon3.h @@ -26,6 +26,8 @@ enum balloon3_features { #define BALLOON3_FPGA_VIRT (0xf1000000) /* as per balloon2 */ #define BALLOON3_FPGA_LENGTH 0x01000000 +#define BALLOON3_FPGA_SETnCLR (0x1000) + /* FPGA / CPLD registers for CF socket */ #define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008) #define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008) @@ -35,7 +37,7 @@ enum balloon3_features { #define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000) #define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000) #define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010) -#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00010) +#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00014) #define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014) /* fpga/cpld interrupt control register */ @@ -174,7 +176,7 @@ enum balloon3_features { #define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) #define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) -#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 4) +#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16) extern int balloon3_has(enum balloon3_features feature); diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h index 58dada1..388a96f 100644 --- a/arch/arm/mach-pxa/include/mach/colibri.h +++ b/arch/arm/mach-pxa/include/mach/colibri.h @@ -9,14 +9,14 @@ */ enum { - COLIBRI_PXA270_EVALBOARD = 0, + COLIBRI_EVALBOARD = 0, COLIBRI_PXA270_INCOME, }; -#if defined(CONFIG_MACH_COLIBRI_PXA270_EVALBOARD) -extern void colibri_pxa270_evalboard_init(void); +#if defined(CONFIG_MACH_COLIBRI_EVALBOARD) +extern void colibri_evalboard_init(void); #else -static inline void colibri_pxa270_evalboard_init(void) {} +static inline void colibri_evalboard_init(void) {} #endif #if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME) @@ -59,5 +59,11 @@ static inline void colibri_pxa3xx_init_nand(void) {} #define GPIO0_COLIBRI_PXA270_SD_DETECT 0 #define GPIO113_COLIBRI_PXA270_TS_IRQ 113 +/* GPIO definitions for Colibri PXA300/310 */ +#define GPIO39_COLIBRI_PXA300_SD_DETECT 39 + +/* GPIO definitions for Colibri PXA320 */ +#define GPIO28_COLIBRI_PXA320_SD_DETECT 28 + #endif /* _COLIBRI_H_ */ diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index 814f145..6957ba5 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -13,6 +13,8 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H +#include <mach/addr-map.h> + /* * Workarounds for at least 2 errata so far require this. * The mapping is set in mach-pxa/generic.c. @@ -193,14 +195,15 @@ #define __cpu_is_pxa935(id) (0) #endif -#ifdef CONFIG_CPU_PXA950 -#define __cpu_is_pxa950(id) \ - ({ \ +#ifdef CONFIG_CPU_PXA955 +#define __cpu_is_pxa955(id) \ + ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ - _id == 0x697; \ - }) + _id == 0x581 || _id == 0xc08 \ + || _id == 0xb76; \ + }) #else -#define __cpu_is_pxa950(id) (0) +#define __cpu_is_pxa955(id) (0) #endif #define cpu_is_pxa210() \ @@ -253,16 +256,15 @@ __cpu_is_pxa935(read_cpuid_id()); \ }) -#define cpu_is_pxa950() \ +#define cpu_is_pxa955() \ ({ \ - __cpu_is_pxa950(read_cpuid_id()); \ - }) + __cpu_is_pxa955(read_cpuid_id()); \ + }) /* * CPUID Core Generation Bit * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x - * == 0x3 for pxa300/pxa310/pxa320 */ #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) #define __cpu_is_pxa2xx(id) \ @@ -277,8 +279,10 @@ #ifdef CONFIG_PXA3xx #define __cpu_is_pxa3xx(id) \ ({ \ - unsigned int _id = (id) >> 13 & 0x7; \ - _id == 0x3; \ + __cpu_is_pxa300(id) \ + || __cpu_is_pxa310(id) \ + || __cpu_is_pxa320(id) \ + || __cpu_is_pxa93x(id); \ }) #else #define __cpu_is_pxa3xx(id) (0) @@ -287,13 +291,22 @@ #if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935) #define __cpu_is_pxa93x(id) \ ({ \ - unsigned int _id = (id) >> 4 & 0xfff; \ - _id == 0x683 || _id == 0x693; \ + __cpu_is_pxa930(id) \ + || __cpu_is_pxa935(id); \ }) #else #define __cpu_is_pxa93x(id) (0) #endif +#ifdef CONFIG_PXA95x +#define __cpu_is_pxa95x(id) \ + ({ \ + __cpu_is_pxa955(id); \ + }) +#else +#define __cpu_is_pxa95x(id) (0) +#endif + #define cpu_is_pxa2xx() \ ({ \ __cpu_is_pxa2xx(read_cpuid_id()); \ @@ -308,6 +321,12 @@ ({ \ __cpu_is_pxa93x(read_cpuid_id()); \ }) + +#define cpu_is_pxa95x() \ + ({ \ + __cpu_is_pxa95x(read_cpuid_id()); \ + }) + /* * return current memory and LCD clock frequency in units of 10kHz */ diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index d372caa..a4285fc 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -21,16 +21,14 @@ #define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x)) -#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ -#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */ -#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI) */ +#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */ +#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */ #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ -#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */ +#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */ +#define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */ #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ -#endif - #define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ #define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ @@ -38,7 +36,8 @@ #define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */ #define IRQ_USB PXA_IRQ(11) /* USB Service */ #define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ -#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */ +#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt (PXA27x) */ +#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */ #define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ #define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */ #define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */ @@ -47,6 +46,7 @@ #define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ #define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ #define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ +#define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */ #define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */ #define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */ #define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/ @@ -60,19 +60,17 @@ #define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ #define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ -#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) #define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ #define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ -#endif - -#ifdef CONFIG_PXA3xx -#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request */ #define IRQ_CIR PXA_IRQ(34) /* Consumer IR */ #define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */ #define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ +#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */ #define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ -#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller */ +#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller (PXA3xx) */ +#define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */ #define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */ +#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball (PXA930) */ #define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */ #define IRQ_NAND PXA_IRQ(45) /* NAND Controller */ #define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */ @@ -80,30 +78,14 @@ #define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */ #define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */ #define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ -#endif -#ifdef CONFIG_CPU_PXA935 #define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */ #define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */ - -#define IRQ_MMC3_PXA935 PXA_IRQ(72) /* MMC3 Controller (PXA935) */ -#define IRQ_MMC4_PXA935 PXA_IRQ(73) /* MMC4 Controller (PXA935) */ -#define IRQ_MMC5_PXA935 PXA_IRQ(74) /* MMC5 Controller (PXA935) */ - +#define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */ +#define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */ +#define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */ +#define IRQ_PXA955_MMC3 PXA_IRQ(75) /* MMC3 Controller (PXA955) */ #define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */ -#endif - -#ifdef CONFIG_CPU_PXA930 -#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */ -#define IRQ_ACIPC0 PXA_IRQ(5) -#define IRQ_ACIPC1 PXA_IRQ(40) -#define IRQ_ACIPC2 PXA_IRQ(19) -#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball */ -#endif - -#ifdef CONFIG_CPU_PXA950 -#define IRQ_GC500 PXA_IRQ(70) /* Graphics Controller (PXA950) */ -#endif #define PXA_GPIO_IRQ_BASE PXA_IRQ(96) #define PXA_GPIO_IRQ_NUM (192) diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index 4fcddd9..ee6ced1 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h @@ -17,72 +17,6 @@ #include <mach/hardware.h> /* - * PXA Chip selects - */ - -#define PXA_CS0_PHYS 0x00000000 -#define PXA_CS1_PHYS 0x04000000 -#define PXA_CS2_PHYS 0x08000000 -#define PXA_CS3_PHYS 0x0C000000 -#define PXA_CS4_PHYS 0x10000000 -#define PXA_CS5_PHYS 0x14000000 - -/* - * Memory controller - */ - -#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ -#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ -#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ -#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ -#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ -#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ -#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ -#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ -#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ -#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ -#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ -#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ -#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ -#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ - -/* - * More handy macros for PCMCIA - * - * Arg is socket number - */ -#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */ -#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */ -#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */ - -/* MECR register defines */ -#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ -#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ - -#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ -#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ -#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ -#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ - -#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ -#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ -#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ -#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ -#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ -#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ -#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ -#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ -#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ -#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ -#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ -#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ -#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ -#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ - -/* * Power Manager */ diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index e91d63c..e4fb4668 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h @@ -16,15 +16,6 @@ #include <mach/hardware.h> /* - * Static Chip Selects - */ - -#define PXA300_CS0_PHYS (0x00000000) /* PXA300/PXA310 _only_ */ -#define PXA300_CS1_PHYS (0x30000000) /* PXA300/PXA310 _only_ */ -#define PXA3xx_CS2_PHYS (0x10000000) -#define PXA3xx_CS3_PHYS (0x14000000) - -/* * Oscillator Configuration Register (OSCC) */ #define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h index 68464ce..662288e 100644 --- a/arch/arm/mach-pxa/include/mach/regs-intc.h +++ b/arch/arm/mach-pxa/include/mach/regs-intc.h @@ -27,8 +27,4 @@ #define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */ #define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */ -#define IPR(x) __REG(0x40D0001C + (x < 32 ? (x << 2) \ - : (x < 64 ? (0x94 + ((x - 32) << 2)) \ - : (0x128 + ((x - 64) << 2))))) - #endif /* __ASM_MACH_REGS_INTC_H */ diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/include/mach/smemc.h new file mode 100644 index 0000000..654adc9 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/smemc.h @@ -0,0 +1,74 @@ +/* + * Static memory controller register definitions for PXA CPUs + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SMEMC_REGS_H +#define __SMEMC_REGS_H + +#define PXA2XX_SMEMC_BASE 0x48000000 +#define PXA3XX_SMEMC_BASE 0x4a000000 +#define SMEMC_VIRT 0xf6000000 + +#define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */ +#define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */ +#define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */ +#define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */ +#define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */ +#define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ +#define SXCNFG (SMEMC_VIRT + 0x1C) /* Synchronous Static Memory Control Register */ +#define SXMRS (SMEMC_VIRT + 0x24) /* MRS value to be written to Synchronous Flash or SMROM */ +#define MCMEM0 (SMEMC_VIRT + 0x28) /* Card interface Common Memory Space Socket 0 Timing */ +#define MCMEM1 (SMEMC_VIRT + 0x2C) /* Card interface Common Memory Space Socket 1 Timing */ +#define MCATT0 (SMEMC_VIRT + 0x30) /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCATT1 (SMEMC_VIRT + 0x34) /* Card interface Attribute Space Socket 1 Timing Configuration */ +#define MCIO0 (SMEMC_VIRT + 0x38) /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MCIO1 (SMEMC_VIRT + 0x3C) /* Card interface I/O Space Socket 1 Timing Configuration */ +#define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */ +#define BOOT_DEF (SMEMC_VIRT + 0x44) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ +#define MEMCLKCFG (SMEMC_VIRT + 0x68) /* Clock Configuration */ +#define CSADRCFG0 (SMEMC_VIRT + 0x80) /* Address Configuration Register for CS0 */ +#define CSADRCFG1 (SMEMC_VIRT + 0x84) /* Address Configuration Register for CS1 */ +#define CSADRCFG2 (SMEMC_VIRT + 0x88) /* Address Configuration Register for CS2 */ +#define CSADRCFG3 (SMEMC_VIRT + 0x8C) /* Address Configuration Register for CS3 */ + +/* + * More handy macros for PCMCIA + * + * Arg is socket number + */ +#define MCMEM(s) (SMEMC_VIRT + 0x28 + ((s)<<2)) /* Card interface Common Memory Space Socket s Timing */ +#define MCATT(s) (SMEMC_VIRT + 0x30 + ((s)<<2)) /* Card interface Attribute Space Socket s Timing Configuration */ +#define MCIO(s) (SMEMC_VIRT + 0x38 + ((s)<<2)) /* Card interface I/O Space Socket s Timing Configuration */ + +/* MECR register defines */ +#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ +#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ + +#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ +#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ +#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ +#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ + +#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ +#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ +#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ +#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ +#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ +#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ +#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ +#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ +#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ +#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ +#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ +#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ +#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ +#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ + +#endif diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 1beb40f..54e91c9 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -16,20 +16,31 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/sysdev.h> +#include <linux/io.h> +#include <linux/irq.h> #include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/mach/irq.h> +#include <mach/irqs.h> #include <mach/gpio.h> -#include <mach/regs-intc.h> #include "generic.h" -#define MAX_INTERNAL_IRQS 128 +#define IRQ_BASE (void __iomem *)io_p2v(0x40d00000) + +#define ICIP (0x000) +#define ICMR (0x004) +#define ICLR (0x008) +#define ICFR (0x00c) +#define ICPR (0x010) +#define ICCR (0x014) +#define ICHP (0x018) +#define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ + ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ + (0x144 + (((i) - 64) << 2))) +#define IPR_VALID (1 << 31) +#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) -#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) -#define _ICMR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR)) -#define _ICLR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR)) +#define MAX_INTERNAL_IRQS 128 /* * This is for peripheral IRQs internal to the PXA chip. @@ -37,14 +48,27 @@ static int pxa_internal_irq_nr; +static inline int cpu_has_ipr(void) +{ + return !cpu_is_pxa25x(); +} + static void pxa_mask_irq(unsigned int irq) { - _ICMR(irq) &= ~(1 << IRQ_BIT(irq)); + void __iomem *base = get_irq_chip_data(irq); + uint32_t icmr = __raw_readl(base + ICMR); + + icmr &= ~(1 << IRQ_BIT(irq)); + __raw_writel(icmr, base + ICMR); } static void pxa_unmask_irq(unsigned int irq) { - _ICMR(irq) |= 1 << IRQ_BIT(irq); + void __iomem *base = get_irq_chip_data(irq); + uint32_t icmr = __raw_readl(base + ICMR); + + icmr |= 1 << IRQ_BIT(irq); + __raw_writel(icmr, base + ICMR); } static struct irq_chip pxa_internal_irq_chip = { @@ -86,12 +110,16 @@ static void pxa_ack_low_gpio(unsigned int irq) static void pxa_mask_low_gpio(unsigned int irq) { - ICMR &= ~(1 << (irq - PXA_IRQ(0))); + struct irq_desc *desc = irq_to_desc(irq); + + desc->chip->mask(irq); } static void pxa_unmask_low_gpio(unsigned int irq) { - ICMR |= 1 << (irq - PXA_IRQ(0)); + struct irq_desc *desc = irq_to_desc(irq); + + desc->chip->unmask(irq); } static struct irq_chip pxa_low_gpio_chip = { @@ -120,33 +148,45 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn) pxa_low_gpio_chip.set_wake = fn; } +static inline void __iomem *irq_base(int i) +{ + static unsigned long phys_base[] = { + 0x40d00000, + 0x40d0009c, + 0x40d00130, + }; + + return (void __iomem *)io_p2v(phys_base[i >> 5]); +} + void __init pxa_init_irq(int irq_nr, set_wake_t fn) { - int irq, i; + int irq, i, n; BUG_ON(irq_nr > MAX_INTERNAL_IRQS); pxa_internal_irq_nr = irq_nr; - for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) { - _ICMR(irq) = 0; /* disable all IRQs */ - _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */ - } - - /* initialize interrupt priority */ - if (cpu_is_pxa27x() || cpu_is_pxa3xx()) { - for (i = 0; i < irq_nr; i++) - IPR(i) = i | (1 << 31); + for (n = 0; n < irq_nr; n += 32) { + void __iomem *base = irq_base(n); + + __raw_writel(0, base + ICMR); /* disable all IRQs */ + __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ + for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { + /* initialize interrupt priority */ + if (cpu_has_ipr()) + __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); + + irq = PXA_IRQ(i); + set_irq_chip(irq, &pxa_internal_irq_chip); + set_irq_chip_data(irq, base); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } } /* only unmasked interrupts kick us out of idle */ - ICCR = 1; - - for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) { - set_irq_chip(irq, &pxa_internal_irq_chip); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } + __raw_writel(1, irq_base(0) + ICCR); pxa_internal_irq_chip.set_wake = fn; pxa_init_low_gpio_irq(fn); @@ -158,16 +198,18 @@ static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) { - int i, irq = PXA_IRQ(0); + int i; - for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) { - saved_icmr[i] = _ICMR(irq); - _ICMR(irq) = 0; + for (i = 0; i < pxa_internal_irq_nr; i += 32) { + void __iomem *base = irq_base(i); + + saved_icmr[i] = __raw_readl(base + ICMR); + __raw_writel(0, base + ICMR); } - if (cpu_is_pxa27x() || cpu_is_pxa3xx()) { + if (cpu_has_ipr()) { for (i = 0; i < pxa_internal_irq_nr; i++) - saved_ipr[i] = IPR(i); + saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); } return 0; @@ -175,19 +217,20 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) static int pxa_irq_resume(struct sys_device *dev) { - int i, irq = PXA_IRQ(0); + int i; - if (cpu_is_pxa27x() || cpu_is_pxa3xx()) { - for (i = 0; i < pxa_internal_irq_nr; i++) - IPR(i) = saved_ipr[i]; - } + for (i = 0; i < pxa_internal_irq_nr; i += 32) { + void __iomem *base = irq_base(i); - for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) { - _ICMR(irq) = saved_icmr[i]; - _ICLR(irq) = 0; + __raw_writel(saved_icmr[i], base + ICMR); + __raw_writel(0, base + ICLR); } - ICCR = 1; + if (!cpu_is_pxa25x()) + for (i = 0; i < pxa_internal_irq_nr; i++) + __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); + + __raw_writel(1, IRQ_BASE + ICCR); return 0; } #else diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 41aa89e..719c260 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -438,7 +438,7 @@ static void __init littleton_init(void) MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa3xx_map_io, .nr_irqs = LITTLETON_NR_IRQS, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index 623af02..8ab62a6 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -46,6 +46,7 @@ #include <mach/mmc.h> #include <mach/irda.h> #include <mach/ohci.h> +#include <mach/smemc.h> #include "generic.h" #include "devices.h" @@ -463,7 +464,7 @@ static void __init lpd270_init(void) pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); - lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; + lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4; lpd270_flash_data[1].width = 4; /* @@ -495,7 +496,7 @@ static struct map_desc lpd270_io_desc[] __initdata = { static void __init lpd270_map_io(void) { - pxa_map_io(); + pxa27x_map_io(); iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc)); /* for use I SRAM as framebuffer. */ diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 1499493..d337548 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -50,6 +50,7 @@ #include <mach/pxafb.h> #include <mach/mmc.h> #include <mach/pm.h> +#include <mach/smemc.h> #include "generic.h" #include "clock.h" @@ -525,7 +526,7 @@ static void __init lubbock_init(void) pxa_set_ac97_info(NULL); lubbock_flash_data[0].width = lubbock_flash_data[1].width = - (BOOT_DEF & 1) ? 2 : 4; + (__raw_readl(BOOT_DEF) & 1) ? 2 : 4; /* Compensate for the nROMBT switch which swaps the flash banks */ printk(KERN_NOTICE "Lubbock configured to boot from %s (bank %d)\n", flashboot?"Flash":"ROM", flashboot); @@ -549,7 +550,7 @@ static struct map_desc lubbock_io_desc[] __initdata = { static void __init lubbock_map_io(void) { - pxa_map_io(); + pxa25x_map_io(); iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc)); PCFR |= PCFR_OPDE; diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 9066376..41198f0 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -765,7 +765,7 @@ static void __init magician_init(void) MACHINE_START(MAGICIAN, "HTC Magician") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .nr_irqs = MAGICIAN_NR_IRQS, .init_irq = pxa27x_init_irq, .init_machine = magician_init, diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index a980a5c..740c035 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -51,6 +51,7 @@ #include <mach/irda.h> #include <mach/ohci.h> #include <plat/pxa27x_keypad.h> +#include <mach/smemc.h> #include "generic.h" #include "devices.h" @@ -565,7 +566,7 @@ static void __init mainstone_init(void) pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); - mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; + mst_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4; mst_flash_data[1].width = 4; /* Compensate for SW7 which swaps the flash banks */ @@ -614,7 +615,7 @@ static struct map_desc mainstone_io_desc[] __initdata = { static void __init mainstone_map_io(void) { - pxa_map_io(); + pxa27x_map_io(); iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc)); /* for use I SRAM as framebuffer. */ diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index f5fb915..faafea3 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -819,7 +819,7 @@ static void mioa701_machine_exit(void) MACHINE_START(MIOA701, "MIO A701") .boot_params = 0xa0000100, - .map_io = &pxa_map_io, + .map_io = &pxa27x_map_io, .init_irq = &pxa27x_init_irq, .init_machine = mioa701_machine_init, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c index 116167aa..59cce78 100644 --- a/arch/arm/mach-pxa/mp900.c +++ b/arch/arm/mach-pxa/mp900.c @@ -94,7 +94,7 @@ static void __init mp900c_init(void) MACHINE_START(NEC_MP900, "MobilePro900/C") .boot_params = 0xa0220100, .timer = &pxa_timer, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .init_irq = pxa25x_init_irq, .init_machine = mp900c_init, MACHINE_END diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index ce092c5..a6f898c 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c @@ -313,7 +313,7 @@ static struct map_desc palmld_io_desc[] __initdata = { static void __init palmld_map_io(void) { - pxa_map_io(); + pxa27x_map_io(); iotable_init(palmld_io_desc, ARRAY_SIZE(palmld_io_desc)); } diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index 862da81..df4d7d0 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c @@ -203,7 +203,7 @@ static void __init palmt5_init(void) MACHINE_START(PALMT5, "Palm Tungsten|T5") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .reserve = palmt5_reserve, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index 2131d58..a09a237 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -25,6 +25,7 @@ #include <linux/power_supply.h> #include <linux/gpio_keys.h> #include <linux/mtd/physmap.h> +#include <linux/usb/gpio_vbus.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -116,6 +117,7 @@ static unsigned long palmtc_pin_config[] __initdata = { /****************************************************************************** * SD/MMC card controller ******************************************************************************/ +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) static struct pxamci_platform_data palmtc_mci_platform_data = { .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .gpio_power = GPIO_NR_PALMTC_SD_POWER, @@ -124,9 +126,18 @@ static struct pxamci_platform_data palmtc_mci_platform_data = { .detect_delay_ms = 200, }; +static void __init palmtc_mmc_init(void) +{ + pxa_set_mci_info(&palmtc_mci_platform_data); +} +#else +static inline void palmtc_mmc_init(void) {} +#endif + /****************************************************************************** * GPIO keys ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) static struct gpio_keys_button palmtc_pxa_buttons[] = { {KEY_F8, GPIO_NR_PALMTC_HOTSYNC_BUTTON, 1, "HotSync Button", EV_KEY, 1}, }; @@ -144,9 +155,18 @@ static struct platform_device palmtc_pxa_keys = { }, }; +static void __init palmtc_keys_init(void) +{ + platform_device_register(&palmtc_pxa_keys); +} +#else +static inline void palmtc_keys_init(void) {} +#endif + /****************************************************************************** * Backlight ******************************************************************************/ +#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) static int palmtc_backlight_init(struct device *dev) { int ret; @@ -196,17 +216,35 @@ static struct platform_device palmtc_backlight = { }, }; +static void __init palmtc_pwm_init(void) +{ + platform_device_register(&palmtc_backlight); +} +#else +static inline void palmtc_pwm_init(void) {} +#endif + /****************************************************************************** * IrDA ******************************************************************************/ +#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE) static struct pxaficp_platform_data palmtc_ficp_platform_data = { .gpio_pwdown = GPIO_NR_PALMTC_IR_DISABLE, .transceiver_cap = IR_SIRMODE | IR_OFF, }; +static void __init palmtc_irda_init(void) +{ + pxa_set_ficp_info(&palmtc_ficp_platform_data); +} +#else +static inline void palmtc_irda_init(void) {} +#endif + /****************************************************************************** * Keyboard ******************************************************************************/ +#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE) static const uint32_t palmtc_matrix_keys[] = { KEY(0, 0, KEY_F1), KEY(0, 1, KEY_X), @@ -290,27 +328,103 @@ static struct platform_device palmtc_keyboard = { .platform_data = &palmtc_keypad_platform_data, }, }; +static void __init palmtc_mkp_init(void) +{ + platform_device_register(&palmtc_keyboard); +} +#else +static inline void palmtc_mkp_init(void) {} +#endif /****************************************************************************** * UDC ******************************************************************************/ -static struct pxa2xx_udc_mach_info palmtc_udc_info __initdata = { +#if defined(CONFIG_USB_GADGET_PXA25X)||defined(CONFIG_USB_GADGET_PXA25X_MODULE) +static struct gpio_vbus_mach_info palmtc_udc_info = { .gpio_vbus = GPIO_NR_PALMTC_USB_DETECT_N, .gpio_vbus_inverted = 1, .gpio_pullup = GPIO_NR_PALMTC_USB_POWER, }; +static struct platform_device palmtc_gpio_vbus = { + .name = "gpio-vbus", + .id = -1, + .dev = { + .platform_data = &palmtc_udc_info, + }, +}; + +static void __init palmtc_udc_init(void) +{ + platform_device_register(&palmtc_gpio_vbus); +}; +#else +static inline void palmtc_udc_init(void) {} +#endif + /****************************************************************************** * Touchscreen / Battery / GPIO-extender ******************************************************************************/ -static struct platform_device palmtc_ucb1400_core = { +#if defined(CONFIG_TOUCHSCREEN_UCB1400) || \ + defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE) +static struct platform_device palmtc_ucb1400_device = { .name = "ucb1400_core", .id = -1, }; +static void __init palmtc_ts_init(void) +{ + pxa_set_ac97_info(NULL); + platform_device_register(&palmtc_ucb1400_device); +} +#else +static inline void palmtc_ts_init(void) {} +#endif + +/****************************************************************************** + * LEDs + ******************************************************************************/ +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +struct gpio_led palmtc_gpio_leds[] = { +{ + .name = "palmtc:green:user", + .default_trigger = "none", + .gpio = GPIO_NR_PALMTC_LED_POWER, + .active_low = 1, +}, { + .name = "palmtc:vibra:vibra", + .default_trigger = "none", + .gpio = GPIO_NR_PALMTC_VIBRA_POWER, + .active_low = 1, +} + +}; + +static struct gpio_led_platform_data palmtc_gpio_led_info = { + .leds = palmtc_gpio_leds, + .num_leds = ARRAY_SIZE(palmtc_gpio_leds), +}; + +static struct platform_device palmtc_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &palmtc_gpio_led_info, + } +}; + +static void __init palmtc_leds_init(void) +{ + platform_device_register(&palmtc_leds); +} +#else +static inline void palmtc_leds_init(void) {} +#endif + /****************************************************************************** * NOR Flash ******************************************************************************/ +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) static struct resource palmtc_flash_resource = { .start = PXA_CS0_PHYS, .end = PXA_CS0_PHYS + SZ_16M - 1, @@ -356,24 +470,33 @@ static struct platform_device palmtc_flash = { }, }; +static void __init palmtc_nor_init(void) +{ + platform_device_register(&palmtc_flash); +} +#else +static inline void palmtc_nor_init(void) {} +#endif + /****************************************************************************** * Framebuffer ******************************************************************************/ +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) static struct pxafb_mode_info palmtc_lcd_modes[] = { -{ - .pixclock = 115384, - .xres = 320, - .yres = 320, - .bpp = 16, - - .left_margin = 27, - .right_margin = 7, - .upper_margin = 7, - .lower_margin = 8, - - .hsync_len = 6, - .vsync_len = 1, -}, + { + .pixclock = 115384, + .xres = 320, + .yres = 320, + .bpp = 16, + + .left_margin = 27, + .right_margin = 7, + .upper_margin = 7, + .lower_margin = 8, + + .hsync_len = 6, + .vsync_len = 1, + }, }; static struct pxafb_mach_info palmtc_lcd_screen = { @@ -382,17 +505,17 @@ static struct pxafb_mach_info palmtc_lcd_screen = { .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, }; +static void __init palmtc_lcd_init(void) +{ + set_pxa_fb_info(&palmtc_lcd_screen); +} +#else +static inline void palmtc_lcd_init(void) {} +#endif + /****************************************************************************** * Machine init ******************************************************************************/ -static struct platform_device *devices[] __initdata = { - &palmtc_backlight, - &palmtc_ucb1400_core, - &palmtc_keyboard, - &palmtc_pxa_keys, - &palmtc_flash, -}; - static void __init palmtc_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtc_pin_config)); @@ -402,18 +525,21 @@ static void __init palmtc_init(void) pxa_set_stuart_info(NULL); pxa_set_hwuart_info(NULL); - set_pxa_fb_info(&palmtc_lcd_screen); - pxa_set_mci_info(&palmtc_mci_platform_data); - pxa_set_udc_info(&palmtc_udc_info); - pxa_set_ac97_info(NULL); - pxa_set_ficp_info(&palmtc_ficp_platform_data); - - platform_add_devices(devices, ARRAY_SIZE(devices)); + palmtc_mmc_init(); + palmtc_keys_init(); + palmtc_pwm_init(); + palmtc_irda_init(); + palmtc_mkp_init(); + palmtc_udc_init(); + palmtc_ts_init(); + palmtc_nor_init(); + palmtc_lcd_init(); + palmtc_leds_init(); }; MACHINE_START(PALMTC, "Palm Tungsten|C") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .init_irq = pxa25x_init_irq, .timer = &pxa_timer, .init_machine = palmtc_init diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index a9dae7b..3f25014 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -374,7 +374,7 @@ static void __init palmte2_init(void) MACHINE_START(PALMTE2, "Palm Tungsten|E2") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .init_irq = pxa25x_init_irq, .timer = &pxa_timer, .init_machine = palmte2_init diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index 00e2d7b..8aadad5 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c @@ -442,7 +442,7 @@ static void __init centro_init(void) MACHINE_START(TREO680, "Palm Treo 680") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .reserve = treo_reserve, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, @@ -451,7 +451,7 @@ MACHINE_END MACHINE_START(CENTRO, "Palm Centro 685") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .reserve = treo_reserve, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index e5c9932..595f002 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -334,7 +334,7 @@ static struct map_desc palmtx_io_desc[] __initdata = { static void __init palmtx_map_io(void) { - pxa_map_io(); + pxa27x_map_io(); iotable_init(palmtx_io_desc, ARRAY_SIZE(palmtx_io_desc)); } diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index af6203f..7bf4017 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -280,7 +280,7 @@ static void __init palmz72_init(void) MACHINE_START(PALMZ72, "Palm Zire72") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = palmz72_init diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c index c77e8f3..8547c9a 100644 --- a/arch/arm/mach-pxa/pcm027.c +++ b/arch/arm/mach-pxa/pcm027.c @@ -244,7 +244,7 @@ static void __init pcm027_init(void) static void __init pcm027_map_io(void) { - pxa_map_io(); + pxa27x_map_io(); /* initialize sleep mode regs (wake-up sources, etc) */ PGSR0 = 0x01308000; diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 93a191c..8451790 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -466,7 +466,7 @@ static void __init fixup_poodle(struct machine_desc *desc, MACHINE_START(POODLE, "SHARP Poodle") .fixup = fixup_poodle, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .nr_irqs = POODLE_NR_IRQS, /* 4 for LoCoMo */ .init_irq = pxa25x_init_irq, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index de53f2e..3f5241c 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -23,6 +23,7 @@ #include <linux/suspend.h> #include <linux/sysdev.h> +#include <asm/mach/map.h> #include <mach/hardware.h> #include <mach/irqs.h> #include <mach/gpio.h> @@ -30,6 +31,7 @@ #include <mach/reset.h> #include <mach/pm.h> #include <mach/dma.h> +#include <mach/smemc.h> #include "generic.h" #include "devices.h" @@ -90,23 +92,21 @@ unsigned int pxa25x_get_clk_frequency_khz(int info) return (turbo & 1) ? (N/1000) : (M/1000); } -/* - * Return the current memory clock frequency in units of 10kHz - */ -unsigned int pxa25x_get_memclk_frequency_10khz(void) +static unsigned long clk_pxa25x_mem_getrate(struct clk *clk) { - return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; + return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK; } -static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) -{ - return pxa25x_get_memclk_frequency_10khz() * 10000; -} +static const struct clkops clk_pxa25x_mem_ops = { + .enable = clk_dummy_enable, + .disable = clk_dummy_disable, + .getrate = clk_pxa25x_mem_getrate, +}; static const struct clkops clk_pxa25x_lcd_ops = { - .enable = clk_cken_enable, - .disable = clk_cken_disable, - .getrate = clk_pxa25x_lcd_getrate, + .enable = clk_pxa2xx_cken_enable, + .disable = clk_pxa2xx_cken_disable, + .getrate = clk_pxa25x_mem_getrate, }; static unsigned long gpio12_config_32k[] = { @@ -160,31 +160,30 @@ static const struct clkops clk_pxa25x_gpio11_ops = { * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) */ -static DEFINE_CKEN(pxa25x_hwuart, HWUART, 14745600, 1); - -static struct clk_lookup pxa25x_hwuart_clkreg = - INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL); /* * PXA 2xx clock declarations. */ +static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1); +static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1); +static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1); +static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1); +static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5); +static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0); +static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0); +static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0); +static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0); +static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0); +static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0); +static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0); +static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0); +static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0); +static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0); + static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops); -static DEFINE_CKEN(pxa25x_ffuart, FFUART, 14745600, 1); -static DEFINE_CKEN(pxa25x_btuart, BTUART, 14745600, 1); -static DEFINE_CKEN(pxa25x_stuart, STUART, 14745600, 1); -static DEFINE_CKEN(pxa25x_usb, USB, 47923000, 5); static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0); static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0); -static DEFINE_CKEN(pxa25x_mmc, MMC, 19169000, 0); -static DEFINE_CKEN(pxa25x_i2c, I2C, 31949000, 0); -static DEFINE_CKEN(pxa25x_ssp, SSP, 3686400, 0); -static DEFINE_CKEN(pxa25x_nssp, NSSP, 3686400, 0); -static DEFINE_CKEN(pxa25x_assp, ASSP, 3686400, 0); -static DEFINE_CKEN(pxa25x_pwm0, PWM0, 3686400, 0); -static DEFINE_CKEN(pxa25x_pwm1, PWM1, 3686400, 0); -static DEFINE_CKEN(pxa25x_ac97, AC97, 24576000, 0); -static DEFINE_CKEN(pxa25x_i2s, I2S, 14745600, 0); -static DEFINE_CKEN(pxa25x_ficp, FICP, 47923000, 0); +static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0); static struct clk_lookup pxa25x_clkregs[] = { INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL), @@ -205,8 +204,12 @@ static struct clk_lookup pxa25x_clkregs[] = { INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"), INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), + INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL), }; +static struct clk_lookup pxa25x_hwuart_clkreg = + INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL); + #ifdef CONFIG_PM #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x @@ -219,20 +222,17 @@ static struct clk_lookup pxa25x_clkregs[] = { */ enum { SLEEP_SAVE_PSTR, - SLEEP_SAVE_CKEN, SLEEP_SAVE_COUNT }; static void pxa25x_cpu_pm_save(unsigned long *sleep_save) { - SAVE(CKEN); SAVE(PSTR); } static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) { - RESTORE(CKEN); RESTORE(PSTR); } @@ -320,6 +320,22 @@ void __init pxa26x_init_irq(void) } #endif +static struct map_desc pxa25x_io_desc[] __initdata = { + { /* Mem Ctl */ + .virtual = SMEMC_VIRT, + .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), + .length = 0x00200000, + .type = MT_DEVICE + }, +}; + +void __init pxa25x_map_io(void) +{ + pxa_map_io(); + iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc)); + pxa25x_get_clk_frequency_khz(1); +} + static struct platform_device *pxa25x_devices[] __initdata = { &pxa25x_device_udc, &pxa_device_pmu, @@ -339,7 +355,9 @@ static struct sys_device pxa25x_sysdev[] = { .cls = &pxa2xx_mfp_sysclass, }, { .cls = &pxa_gpio_sysclass, - }, + }, { + .cls = &pxa2xx_clock_sysclass, + } }; static int __init pxa25x_init(void) diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index d1fbf29..b2130b7 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -17,7 +17,9 @@ #include <linux/suspend.h> #include <linux/platform_device.h> #include <linux/sysdev.h> +#include <linux/io.h> +#include <asm/mach/map.h> #include <mach/hardware.h> #include <asm/irq.h> #include <mach/irqs.h> @@ -27,6 +29,8 @@ #include <mach/ohci.h> #include <mach/pm.h> #include <mach/dma.h> +#include <mach/smemc.h> + #include <plat/i2c.h> #include "generic.h" @@ -107,10 +111,9 @@ unsigned int pxa27x_get_clk_frequency_khz(int info) } /* - * Return the current mem clock frequency in units of 10kHz as - * reflected by CCCR[A], B, and L + * Return the current mem clock frequency as reflected by CCCR[A], B, and L */ -unsigned int pxa27x_get_memclk_frequency_10khz(void) +static unsigned long clk_pxa27x_mem_getrate(struct clk *clk) { unsigned long ccsr, clkcfg; unsigned int l, L, m, M; @@ -129,9 +132,15 @@ unsigned int pxa27x_get_memclk_frequency_10khz(void) L = l * BASE_CLK; M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); - return (M / 10000); + return M; } +static const struct clkops clk_pxa27x_mem_ops = { + .enable = clk_dummy_enable, + .disable = clk_dummy_disable, + .getrate = clk_pxa27x_mem_getrate, +}; + /* * Return the current LCD clock frequency in units of 10kHz as */ @@ -157,36 +166,38 @@ static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk) } static const struct clkops clk_pxa27x_lcd_ops = { - .enable = clk_cken_enable, - .disable = clk_cken_disable, + .enable = clk_pxa2xx_cken_enable, + .disable = clk_pxa2xx_cken_disable, .getrate = clk_pxa27x_lcd_getrate, }; +static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1); +static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1); +static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1); +static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0); +static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0); +static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5); +static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0); +static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0); +static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0); +static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0); +static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0); +static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0); +static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0); +static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0); +static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0); +static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0); +static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0); +static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0); +static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0); +static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0); +static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0); +static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0); +static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0); + static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops); static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops); -static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1); -static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1); -static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1); -static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0); -static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0); -static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5); -static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0); -static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0); -static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0); -static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0); -static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0); -static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0); -static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0); -static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0); -static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0); -static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0); -static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0); -static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0); -static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0); -static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0); -static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0); -static DEFINE_CKEN(pxa27x_im, IM, 0, 0); -static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0); +static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0); static struct clk_lookup pxa27x_clkregs[] = { INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL), @@ -215,6 +226,7 @@ static struct clk_lookup pxa27x_clkregs[] = { INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"), INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), + INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL), }; #ifdef CONFIG_PM @@ -246,7 +258,6 @@ int __init pxa27x_set_pwrmode(unsigned int mode) */ enum { SLEEP_SAVE_PSTR, - SLEEP_SAVE_CKEN, SLEEP_SAVE_MDREFR, SLEEP_SAVE_PCFR, SLEEP_SAVE_COUNT @@ -254,21 +265,19 @@ enum { void pxa27x_cpu_pm_save(unsigned long *sleep_save) { - SAVE(MDREFR); + sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR); SAVE(PCFR); - SAVE(CKEN); SAVE(PSTR); } void pxa27x_cpu_pm_restore(unsigned long *sleep_save) { - RESTORE(MDREFR); + __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR); RESTORE(PCFR); PSSR = PSSR_RDH | PSSR_PH; - RESTORE(CKEN); RESTORE(PSTR); } @@ -370,6 +379,27 @@ void __init pxa27x_init_irq(void) pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake); } +static struct map_desc pxa27x_io_desc[] __initdata = { + { /* Mem Ctl */ + .virtual = SMEMC_VIRT, + .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), + .length = 0x00200000, + .type = MT_DEVICE + }, { /* IMem ctl */ + .virtual = 0xfe000000, + .pfn = __phys_to_pfn(0x58000000), + .length = 0x00100000, + .type = MT_DEVICE + }, +}; + +void __init pxa27x_map_io(void) +{ + pxa_map_io(); + iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc)); + pxa27x_get_clk_frequency_khz(1); +} + /* * device registration specific to PXA27x. */ @@ -405,7 +435,9 @@ static struct sys_device pxa27x_sysdev[] = { .cls = &pxa2xx_mfp_sysclass, }, { .cls = &pxa_gpio_sysclass, - }, + }, { + .cls = &pxa2xx_clock_sysclass, + } }; static int __init pxa27x_init(void) diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index d1c747c..e14818f 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <linux/sysdev.h> +#include <asm/mach/map.h> #include <mach/hardware.h> #include <mach/gpio.h> #include <mach/pxa3xx-regs.h> @@ -30,193 +31,16 @@ #include <mach/pm.h> #include <mach/dma.h> #include <mach/regs-intc.h> +#include <mach/smemc.h> #include <plat/i2c.h> #include "generic.h" #include "devices.h" #include "clock.h" -/* Crystal clock: 13MHz */ -#define BASE_CLK 13000000 - -/* Ring Oscillator Clock: 60MHz */ -#define RO_CLK 60000000 - -#define ACCR_D0CS (1 << 26) -#define ACCR_PCCE (1 << 11) - #define PECR_IE(n) ((1 << ((n) * 2)) << 28) #define PECR_IS(n) ((1 << ((n) * 2)) << 29) -/* crystal frequency to static memory controller multiplier (SMCFS) */ -static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; - -/* crystal frequency to HSIO bus frequency multiplier (HSS) */ -static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; - -/* - * Get the clock frequency as reflected by CCSR and the turbo flag. - * We assume these values have been applied via a fcs. - * If info is not 0 we also display the current settings. - */ -unsigned int pxa3xx_get_clk_frequency_khz(int info) -{ - unsigned long acsr, xclkcfg; - unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; - - /* Read XCLKCFG register turbo bit */ - __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); - t = xclkcfg & 0x1; - - acsr = ACSR; - - xl = acsr & 0x1f; - xn = (acsr >> 8) & 0x7; - hss = (acsr >> 14) & 0x3; - - XL = xl * BASE_CLK; - XN = xn * XL; - - ro = acsr & ACCR_D0CS; - - CLK = (ro) ? RO_CLK : ((t) ? XN : XL); - HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; - - if (info) { - pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", - RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, - (ro) ? "" : "in"); - pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", - XL / 1000000, (XL % 1000000) / 10000, xl); - pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", - XN / 1000000, (XN % 1000000) / 10000, xn, - (t) ? "" : "in"); - pr_info("HSIO bus clock: %d.%02dMHz\n", - HSS / 1000000, (HSS % 1000000) / 10000); - } - - return CLK / 1000; -} - -void pxa3xx_clear_reset_status(unsigned int mask) -{ - /* RESET_STATUS_* has a 1:1 mapping with ARSR */ - ARSR = mask; -} - -/* - * Return the current AC97 clock frequency. - */ -static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) -{ - unsigned long rate = 312000000; - unsigned long ac97_div; - - ac97_div = AC97_DIV; - - /* This may loose precision for some rates but won't for the - * standard 24.576MHz. - */ - rate /= (ac97_div >> 12) & 0x7fff; - rate *= (ac97_div & 0xfff); - - return rate; -} - -/* - * Return the current HSIO bus clock frequency - */ -static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) -{ - unsigned long acsr; - unsigned int hss, hsio_clk; - - acsr = ACSR; - - hss = (acsr >> 14) & 0x3; - hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; - - return hsio_clk; -} - -void clk_pxa3xx_cken_enable(struct clk *clk) -{ - unsigned long mask = 1ul << (clk->cken & 0x1f); - - if (clk->cken < 32) - CKENA |= mask; - else - CKENB |= mask; -} - -void clk_pxa3xx_cken_disable(struct clk *clk) -{ - unsigned long mask = 1ul << (clk->cken & 0x1f); - - if (clk->cken < 32) - CKENA &= ~mask; - else - CKENB &= ~mask; -} - -const struct clkops clk_pxa3xx_cken_ops = { - .enable = clk_pxa3xx_cken_enable, - .disable = clk_pxa3xx_cken_disable, -}; - -static const struct clkops clk_pxa3xx_hsio_ops = { - .enable = clk_pxa3xx_cken_enable, - .disable = clk_pxa3xx_cken_disable, - .getrate = clk_pxa3xx_hsio_getrate, -}; - -static const struct clkops clk_pxa3xx_ac97_ops = { - .enable = clk_pxa3xx_cken_enable, - .disable = clk_pxa3xx_cken_disable, - .getrate = clk_pxa3xx_ac97_getrate, -}; - -static void clk_pout_enable(struct clk *clk) -{ - OSCC |= OSCC_PEN; -} - -static void clk_pout_disable(struct clk *clk) -{ - OSCC &= ~OSCC_PEN; -} - -static const struct clkops clk_pout_ops = { - .enable = clk_pout_enable, - .disable = clk_pout_disable, -}; - -static void clk_dummy_enable(struct clk *clk) -{ -} - -static void clk_dummy_disable(struct clk *clk) -{ -} - -static const struct clkops clk_dummy_ops = { - .enable = clk_dummy_enable, - .disable = clk_dummy_disable, -}; - -static struct clk clk_pxa3xx_pout = { - .ops = &clk_pout_ops, - .rate = 13000000, - .delay = 70, -}; - -static struct clk clk_dummy = { - .ops = &clk_dummy_ops, -}; - -static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); -static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); -static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); @@ -234,6 +58,12 @@ static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); +static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); +static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops); +static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); +static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); +static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70); + static struct clk_lookup pxa3xx_clkregs[] = { INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), /* Power I2C clock is always on */ @@ -258,6 +88,7 @@ static struct clk_lookup pxa3xx_clkregs[] = { INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), + INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL), }; #ifdef CONFIG_PM @@ -268,30 +99,6 @@ static struct clk_lookup pxa3xx_clkregs[] = { static void __iomem *sram; static unsigned long wakeup_src; -#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x -#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] - -enum { SLEEP_SAVE_CKENA, - SLEEP_SAVE_CKENB, - SLEEP_SAVE_ACCR, - - SLEEP_SAVE_COUNT, -}; - -static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) -{ - SAVE(CKENA); - SAVE(CKENB); - SAVE(ACCR); -} - -static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) -{ - RESTORE(ACCR); - RESTORE(CKENA); - RESTORE(CKENB); -} - /* * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic * memory controller has to be reinitialised, so we place some code @@ -390,9 +197,6 @@ static int pxa3xx_cpu_pm_valid(suspend_state_t state) } static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { - .save_count = SLEEP_SAVE_COUNT, - .save = pxa3xx_cpu_pm_save, - .restore = pxa3xx_cpu_pm_restore, .valid = pxa3xx_cpu_pm_valid, .enter = pxa3xx_cpu_pm_enter, }; @@ -580,6 +384,22 @@ void __init pxa3xx_init_irq(void) pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); } +static struct map_desc pxa3xx_io_desc[] __initdata = { + { /* Mem Ctl */ + .virtual = SMEMC_VIRT, + .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), + .length = 0x00200000, + .type = MT_DEVICE + } +}; + +void __init pxa3xx_map_io(void) +{ + pxa_map_io(); + iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); + pxa3xx_get_clk_frequency_khz(1); +} + /* * device registration specific to PXA3xx. */ @@ -615,7 +435,9 @@ static struct sys_device pxa3xx_sysdev[] = { .cls = &pxa3xx_mfp_sysclass, }, { .cls = &pxa_gpio_sysclass, - }, + }, { + .cls = &pxa3xx_clock_sysclass, + } }; static int __init pxa3xx_init(void) diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c index 7d29dd3..8aeacf9 100644 --- a/arch/arm/mach-pxa/pxa930.c +++ b/arch/arm/mach-pxa/pxa930.c @@ -192,7 +192,7 @@ static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = { static int __init pxa930_init(void) { - if (cpu_is_pxa930() || cpu_is_pxa935() || cpu_is_pxa950()) { + if (cpu_is_pxa93x()) { mfp_init_base(io_p2v(MFPR_BASE)); mfp_init_addr(pxa930_mfp_addr_map); } diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c new file mode 100644 index 0000000..437980f --- /dev/null +++ b/arch/arm/mach-pxa/pxa95x.c @@ -0,0 +1,308 @@ +/* + * linux/arch/arm/mach-pxa/pxa95x.c + * + * code specific to PXA95x aka MGx + * + * Copyright (C) 2009-2010 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/pm.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/sysdev.h> + +#include <mach/hardware.h> +#include <mach/gpio.h> +#include <mach/pxa3xx-regs.h> +#include <mach/pxa930.h> +#include <mach/reset.h> +#include <mach/pm.h> +#include <mach/dma.h> +#include <mach/regs-intc.h> +#include <plat/i2c.h> + +#include "generic.h" +#include "devices.h" +#include "clock.h" + +static struct mfp_addr_map pxa95x_mfp_addr_map[] __initdata = { + + MFP_ADDR(GPIO0, 0x02e0), + MFP_ADDR(GPIO1, 0x02dc), + MFP_ADDR(GPIO2, 0x02e8), + MFP_ADDR(GPIO3, 0x02d8), + MFP_ADDR(GPIO4, 0x02e4), + MFP_ADDR(GPIO5, 0x02ec), + MFP_ADDR(GPIO6, 0x02f8), + MFP_ADDR(GPIO7, 0x02fc), + MFP_ADDR(GPIO8, 0x0300), + MFP_ADDR(GPIO9, 0x02d4), + MFP_ADDR(GPIO10, 0x02f4), + MFP_ADDR(GPIO11, 0x02f0), + MFP_ADDR(GPIO12, 0x0304), + MFP_ADDR(GPIO13, 0x0310), + MFP_ADDR(GPIO14, 0x0308), + MFP_ADDR(GPIO15, 0x030c), + MFP_ADDR(GPIO16, 0x04e8), + MFP_ADDR(GPIO17, 0x04f4), + MFP_ADDR(GPIO18, 0x04f8), + MFP_ADDR(GPIO19, 0x04fc), + MFP_ADDR(GPIO20, 0x0518), + MFP_ADDR(GPIO21, 0x051c), + MFP_ADDR(GPIO22, 0x04ec), + MFP_ADDR(GPIO23, 0x0500), + MFP_ADDR(GPIO24, 0x04f0), + MFP_ADDR(GPIO25, 0x0504), + MFP_ADDR(GPIO26, 0x0510), + MFP_ADDR(GPIO27, 0x0514), + MFP_ADDR(GPIO28, 0x0520), + MFP_ADDR(GPIO29, 0x0600), + MFP_ADDR(GPIO30, 0x0618), + MFP_ADDR(GPIO31, 0x0610), + MFP_ADDR(GPIO32, 0x060c), + MFP_ADDR(GPIO33, 0x061c), + MFP_ADDR(GPIO34, 0x0620), + MFP_ADDR(GPIO35, 0x0628), + MFP_ADDR(GPIO36, 0x062c), + MFP_ADDR(GPIO37, 0x0630), + MFP_ADDR(GPIO38, 0x0634), + MFP_ADDR(GPIO39, 0x0638), + MFP_ADDR(GPIO40, 0x063c), + MFP_ADDR(GPIO41, 0x0614), + MFP_ADDR(GPIO42, 0x0624), + MFP_ADDR(GPIO43, 0x0608), + MFP_ADDR(GPIO44, 0x0604), + MFP_ADDR(GPIO45, 0x050c), + MFP_ADDR(GPIO46, 0x0508), + MFP_ADDR(GPIO47, 0x02bc), + MFP_ADDR(GPIO48, 0x02b4), + MFP_ADDR(GPIO49, 0x02b8), + MFP_ADDR(GPIO50, 0x02c8), + MFP_ADDR(GPIO51, 0x02c0), + MFP_ADDR(GPIO52, 0x02c4), + MFP_ADDR(GPIO53, 0x02d0), + MFP_ADDR(GPIO54, 0x02cc), + MFP_ADDR(GPIO55, 0x029c), + MFP_ADDR(GPIO56, 0x02a0), + MFP_ADDR(GPIO57, 0x0294), + MFP_ADDR(GPIO58, 0x0298), + MFP_ADDR(GPIO59, 0x02a4), + MFP_ADDR(GPIO60, 0x02a8), + MFP_ADDR(GPIO61, 0x02b0), + MFP_ADDR(GPIO62, 0x02ac), + MFP_ADDR(GPIO63, 0x0640), + MFP_ADDR(GPIO64, 0x065c), + MFP_ADDR(GPIO65, 0x0648), + MFP_ADDR(GPIO66, 0x0644), + MFP_ADDR(GPIO67, 0x0674), + MFP_ADDR(GPIO68, 0x0658), + MFP_ADDR(GPIO69, 0x0654), + MFP_ADDR(GPIO70, 0x0660), + MFP_ADDR(GPIO71, 0x0668), + MFP_ADDR(GPIO72, 0x0664), + MFP_ADDR(GPIO73, 0x0650), + MFP_ADDR(GPIO74, 0x066c), + MFP_ADDR(GPIO75, 0x064c), + MFP_ADDR(GPIO76, 0x0670), + MFP_ADDR(GPIO77, 0x0678), + MFP_ADDR(GPIO78, 0x067c), + MFP_ADDR(GPIO79, 0x0694), + MFP_ADDR(GPIO80, 0x069c), + MFP_ADDR(GPIO81, 0x06a0), + MFP_ADDR(GPIO82, 0x06a4), + MFP_ADDR(GPIO83, 0x0698), + MFP_ADDR(GPIO84, 0x06bc), + MFP_ADDR(GPIO85, 0x06b4), + MFP_ADDR(GPIO86, 0x06b0), + MFP_ADDR(GPIO87, 0x06c0), + MFP_ADDR(GPIO88, 0x06c4), + MFP_ADDR(GPIO89, 0x06ac), + MFP_ADDR(GPIO90, 0x0680), + MFP_ADDR(GPIO91, 0x0684), + MFP_ADDR(GPIO92, 0x0688), + MFP_ADDR(GPIO93, 0x0690), + MFP_ADDR(GPIO94, 0x068c), + MFP_ADDR(GPIO95, 0x06a8), + MFP_ADDR(GPIO96, 0x06b8), + MFP_ADDR(GPIO97, 0x0410), + MFP_ADDR(GPIO98, 0x0418), + MFP_ADDR(GPIO99, 0x041c), + MFP_ADDR(GPIO100, 0x0414), + MFP_ADDR(GPIO101, 0x0408), + MFP_ADDR(GPIO102, 0x0324), + MFP_ADDR(GPIO103, 0x040c), + MFP_ADDR(GPIO104, 0x0400), + MFP_ADDR(GPIO105, 0x0328), + MFP_ADDR(GPIO106, 0x0404), + + MFP_ADDR(GPIO159, 0x0524), + MFP_ADDR(GPIO163, 0x0534), + MFP_ADDR(GPIO167, 0x0544), + MFP_ADDR(GPIO168, 0x0548), + MFP_ADDR(GPIO169, 0x054c), + MFP_ADDR(GPIO170, 0x0550), + MFP_ADDR(GPIO171, 0x0554), + MFP_ADDR(GPIO172, 0x0558), + MFP_ADDR(GPIO173, 0x055c), + + MFP_ADDR(nXCVREN, 0x0204), + MFP_ADDR(DF_CLE_nOE, 0x020c), + MFP_ADDR(DF_nADV1_ALE, 0x0218), + MFP_ADDR(DF_SCLK_E, 0x0214), + MFP_ADDR(DF_SCLK_S, 0x0210), + MFP_ADDR(nBE0, 0x021c), + MFP_ADDR(nBE1, 0x0220), + MFP_ADDR(DF_nADV2_ALE, 0x0224), + MFP_ADDR(DF_INT_RnB, 0x0228), + MFP_ADDR(DF_nCS0, 0x022c), + MFP_ADDR(DF_nCS1, 0x0230), + MFP_ADDR(nLUA, 0x0254), + MFP_ADDR(nLLA, 0x0258), + MFP_ADDR(DF_nWE, 0x0234), + MFP_ADDR(DF_nRE_nOE, 0x0238), + MFP_ADDR(DF_ADDR0, 0x024c), + MFP_ADDR(DF_ADDR1, 0x0250), + MFP_ADDR(DF_ADDR2, 0x025c), + MFP_ADDR(DF_ADDR3, 0x0260), + MFP_ADDR(DF_IO0, 0x023c), + MFP_ADDR(DF_IO1, 0x0240), + MFP_ADDR(DF_IO2, 0x0244), + MFP_ADDR(DF_IO3, 0x0248), + MFP_ADDR(DF_IO4, 0x0264), + MFP_ADDR(DF_IO5, 0x0268), + MFP_ADDR(DF_IO6, 0x026c), + MFP_ADDR(DF_IO7, 0x0270), + MFP_ADDR(DF_IO8, 0x0274), + MFP_ADDR(DF_IO9, 0x0278), + MFP_ADDR(DF_IO10, 0x027c), + MFP_ADDR(DF_IO11, 0x0280), + MFP_ADDR(DF_IO12, 0x0284), + MFP_ADDR(DF_IO13, 0x0288), + MFP_ADDR(DF_IO14, 0x028c), + MFP_ADDR(DF_IO15, 0x0290), + + MFP_ADDR(GSIM_UIO, 0x0314), + MFP_ADDR(GSIM_UCLK, 0x0318), + MFP_ADDR(GSIM_UDET, 0x031c), + MFP_ADDR(GSIM_nURST, 0x0320), + + MFP_ADDR(PMIC_INT, 0x06c8), + + MFP_ADDR(RDY, 0x0200), + + MFP_ADDR_END, +}; + +static DEFINE_CK(pxa95x_lcd, LCD, &clk_pxa3xx_hsio_ops); +static DEFINE_CLK(pxa95x_pout, &clk_pxa3xx_pout_ops, 13000000, 70); +static DEFINE_PXA3_CKEN(pxa95x_ffuart, FFUART, 14857000, 1); +static DEFINE_PXA3_CKEN(pxa95x_btuart, BTUART, 14857000, 1); +static DEFINE_PXA3_CKEN(pxa95x_stuart, STUART, 14857000, 1); +static DEFINE_PXA3_CKEN(pxa95x_i2c, I2C, 32842000, 0); +static DEFINE_PXA3_CKEN(pxa95x_keypad, KEYPAD, 32768, 0); +static DEFINE_PXA3_CKEN(pxa95x_ssp1, SSP1, 13000000, 0); +static DEFINE_PXA3_CKEN(pxa95x_ssp2, SSP2, 13000000, 0); +static DEFINE_PXA3_CKEN(pxa95x_ssp3, SSP3, 13000000, 0); +static DEFINE_PXA3_CKEN(pxa95x_ssp4, SSP4, 13000000, 0); +static DEFINE_PXA3_CKEN(pxa95x_pwm0, PWM0, 13000000, 0); +static DEFINE_PXA3_CKEN(pxa95x_pwm1, PWM1, 13000000, 0); + +static struct clk_lookup pxa95x_clkregs[] = { + INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"), + /* Power I2C clock is always on */ + INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), + INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL), + INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-ir", "UARTCLK"), + INIT_CLKREG(&clk_pxa95x_i2c, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_pxa95x_keypad, "pxa27x-keypad", NULL), + INIT_CLKREG(&clk_pxa95x_ssp1, "pxa27x-ssp.0", NULL), + INIT_CLKREG(&clk_pxa95x_ssp2, "pxa27x-ssp.1", NULL), + INIT_CLKREG(&clk_pxa95x_ssp3, "pxa27x-ssp.2", NULL), + INIT_CLKREG(&clk_pxa95x_ssp4, "pxa27x-ssp.3", NULL), + INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL), + INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL), +}; + +void __init pxa95x_init_irq(void) +{ + pxa_init_irq(96, NULL); + pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); +} + +/* + * device registration specific to PXA93x. + */ + +void __init pxa95x_set_i2c_power_info(struct i2c_pxa_platform_data *info) +{ + pxa_register_device(&pxa3xx_device_i2c_power, info); +} + +static struct platform_device *devices[] __initdata = { + &sa1100_device_rtc, + &pxa_device_rtc, + &pxa27x_device_ssp1, + &pxa27x_device_ssp2, + &pxa27x_device_ssp3, + &pxa3xx_device_ssp4, + &pxa27x_device_pwm0, + &pxa27x_device_pwm1, +}; + +static struct sys_device pxa95x_sysdev[] = { + { + .cls = &pxa_irq_sysclass, + }, { + .cls = &pxa_gpio_sysclass, + }, { + .cls = &pxa3xx_clock_sysclass, + } +}; + +static int __init pxa95x_init(void) +{ + int ret = 0, i; + + if (cpu_is_pxa95x()) { + mfp_init_base(io_p2v(MFPR_BASE)); + mfp_init_addr(pxa95x_mfp_addr_map); + + reset_status = ARSR; + + /* + * clear RDH bit every time after reset + * + * Note: the last 3 bits DxS are write-1-to-clear so carefully + * preserve them here in case they will be referenced later + */ + ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); + + clkdev_add_table(pxa95x_clkregs, ARRAY_SIZE(pxa95x_clkregs)); + + if ((ret = pxa_init_dma(IRQ_DMA, 32))) + return ret; + + for (i = 0; i < ARRAY_SIZE(pxa95x_sysdev); i++) { + ret = sysdev_register(&pxa95x_sysdev[i]); + if (ret) + pr_err("failed to register sysdev[%d]\n", i); + } + + ret = platform_add_devices(devices, ARRAY_SIZE(devices)); + } + + return ret; +} + +postcore_initcall(pxa95x_init); diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 4121d03..8361151 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -588,6 +588,9 @@ static struct pxafb_mach_info raumfeld_sharp_lcd_info = { .num_modes = 1, .video_mem_size = 0x400000, .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, +#ifdef CONFIG_PXA3XX_GCU + .acceleration_enabled = 1, +#endif }; static void __init raumfeld_lcd_init(void) @@ -616,6 +619,8 @@ static void __init raumfeld_lcd_init(void) pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n"); else gpio_direction_output(GPIO_DISPLAY_ENABLE, 1); + + platform_device_register(&pxa3xx_device_gcu); } /** @@ -1085,7 +1090,7 @@ static void __init raumfeld_speaker_init(void) MACHINE_START(RAUMFELD_RC, "Raumfeld Controller") .boot_params = RAUMFELD_SDRAM_BASE + 0x100, .init_machine = raumfeld_controller_init, - .map_io = pxa_map_io, + .map_io = pxa3xx_map_io, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, MACHINE_END @@ -1095,7 +1100,7 @@ MACHINE_END MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector") .boot_params = RAUMFELD_SDRAM_BASE + 0x100, .init_machine = raumfeld_connector_init, - .map_io = pxa_map_io, + .map_io = pxa3xx_map_io, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, MACHINE_END @@ -1105,7 +1110,7 @@ MACHINE_END MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker") .boot_params = RAUMFELD_SDRAM_BASE + 0x100, .init_machine = raumfeld_speaker_init, - .map_io = pxa_map_io, + .map_io = pxa3xx_map_io, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, MACHINE_END diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index ffa50e6..c1ca8cb 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c @@ -597,7 +597,7 @@ static void __init saar_init(void) MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)") /* Maintainer: Eric Miao <eric.miao@marvell.com> */ .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa3xx_map_io, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, .init_machine = saar_init, diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c new file mode 100644 index 0000000..e497922 --- /dev/null +++ b/arch/arm/mach-pxa/saarb.c @@ -0,0 +1,114 @@ +/* + * linux/arch/arm/mach-pxa/saarb.c + * + * Support for the Marvell Handheld Platform (aka SAARB) + * + * Copyright (C) 2007-2010 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/i2c.h> +#include <linux/mfd/88pm860x.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/irqs.h> +#include <mach/hardware.h> +#include <mach/mfp.h> +#include <mach/mfp-pxa930.h> +#include <mach/gpio.h> + +#include <plat/i2c.h> + +#include "generic.h" + +#define SAARB_NR_IRQS (IRQ_BOARD_START + 40) + +static struct pm860x_touch_pdata saarb_touch = { + .gpadc_prebias = 1, + .slot_cycle = 1, + .tsi_prebias = 6, + .pen_prebias = 16, + .pen_prechg = 2, + .res_x = 300, +}; + +static struct pm860x_backlight_pdata saarb_backlight[] = { + { + .id = PM8606_ID_BACKLIGHT, + .iset = PM8606_WLED_CURRENT(24), + .flags = PM8606_BACKLIGHT1, + }, + {}, +}; + +static struct pm860x_led_pdata saarb_led[] = { + { + .id = PM8606_ID_LED, + .iset = PM8606_LED_CURRENT(12), + .flags = PM8606_LED1_RED, + }, { + .id = PM8606_ID_LED, + .iset = PM8606_LED_CURRENT(12), + .flags = PM8606_LED1_GREEN, + }, { + .id = PM8606_ID_LED, + .iset = PM8606_LED_CURRENT(12), + .flags = PM8606_LED1_BLUE, + }, { + .id = PM8606_ID_LED, + .iset = PM8606_LED_CURRENT(12), + .flags = PM8606_LED2_RED, + }, { + .id = PM8606_ID_LED, + .iset = PM8606_LED_CURRENT(12), + .flags = PM8606_LED2_GREEN, + }, { + .id = PM8606_ID_LED, + .iset = PM8606_LED_CURRENT(12), + .flags = PM8606_LED2_BLUE, + }, +}; + +static struct pm860x_platform_data saarb_pm8607_info = { + .touch = &saarb_touch, + .backlight = &saarb_backlight[0], + .led = &saarb_led[0], + .companion_addr = 0x10, + .irq_mode = 0, + .irq_base = IRQ_BOARD_START, + + .i2c_port = GI2C_PORT, +}; + +static struct i2c_board_info saarb_i2c_info[] = { + { + .type = "88PM860x", + .addr = 0x34, + .platform_data = &saarb_pm8607_info, + .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), + }, +}; + +static void __init saarb_init(void) +{ + pxa_set_ffuart_info(NULL); + pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(saarb_i2c_info)); +} + +MACHINE_START(SAARB, "PXA955 Handheld Platform (aka SAARB)") + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .nr_irqs = SAARB_NR_IRQS, + .init_irq = pxa95x_init_irq, + .timer = &pxa_timer, + .init_machine = saarb_init, +MACHINE_END + diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index ae00811..c551da8 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@ -14,7 +14,7 @@ #include <linux/linkage.h> #include <asm/assembler.h> #include <mach/hardware.h> - +#include <mach/smemc.h> #include <mach/pxa2xx-regs.h> #define MDREFR_KDIV 0x200a4000 // all banks diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c index d6f6904..232b731 100644 --- a/arch/arm/mach-pxa/smemc.c +++ b/arch/arm/mach-pxa/smemc.c @@ -9,50 +9,37 @@ #include <linux/sysdev.h> #include <mach/hardware.h> - -#define SMEMC_PHYS_BASE (0x4A000000) -#define SMEMC_PHYS_SIZE (0x90) - -#define MSC0 (0x08) /* Static Memory Controller Register 0 */ -#define MSC1 (0x0C) /* Static Memory Controller Register 1 */ -#define SXCNFG (0x1C) /* Synchronous Static Memory Control Register */ -#define MEMCLKCFG (0x68) /* Clock Configuration */ -#define CSADRCFG0 (0x80) /* Address Configuration Register for CS0 */ -#define CSADRCFG1 (0x84) /* Address Configuration Register for CS1 */ -#define CSADRCFG2 (0x88) /* Address Configuration Register for CS2 */ -#define CSADRCFG3 (0x8C) /* Address Configuration Register for CS3 */ +#include <mach/smemc.h> #ifdef CONFIG_PM -static void __iomem *smemc_mmio_base; - static unsigned long msc[2]; static unsigned long sxcnfg, memclkcfg; static unsigned long csadrcfg[4]; static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state) { - msc[0] = __raw_readl(smemc_mmio_base + MSC0); - msc[1] = __raw_readl(smemc_mmio_base + MSC1); - sxcnfg = __raw_readl(smemc_mmio_base + SXCNFG); - memclkcfg = __raw_readl(smemc_mmio_base + MEMCLKCFG); - csadrcfg[0] = __raw_readl(smemc_mmio_base + CSADRCFG0); - csadrcfg[1] = __raw_readl(smemc_mmio_base + CSADRCFG1); - csadrcfg[2] = __raw_readl(smemc_mmio_base + CSADRCFG2); - csadrcfg[3] = __raw_readl(smemc_mmio_base + CSADRCFG3); + msc[0] = __raw_readl(MSC0); + msc[1] = __raw_readl(MSC1); + sxcnfg = __raw_readl(SXCNFG); + memclkcfg = __raw_readl(MEMCLKCFG); + csadrcfg[0] = __raw_readl(CSADRCFG0); + csadrcfg[1] = __raw_readl(CSADRCFG1); + csadrcfg[2] = __raw_readl(CSADRCFG2); + csadrcfg[3] = __raw_readl(CSADRCFG3); return 0; } static int pxa3xx_smemc_resume(struct sys_device *dev) { - __raw_writel(msc[0], smemc_mmio_base + MSC0); - __raw_writel(msc[1], smemc_mmio_base + MSC1); - __raw_writel(sxcnfg, smemc_mmio_base + SXCNFG); - __raw_writel(memclkcfg, smemc_mmio_base + MEMCLKCFG); - __raw_writel(csadrcfg[0], smemc_mmio_base + CSADRCFG0); - __raw_writel(csadrcfg[1], smemc_mmio_base + CSADRCFG1); - __raw_writel(csadrcfg[2], smemc_mmio_base + CSADRCFG2); - __raw_writel(csadrcfg[3], smemc_mmio_base + CSADRCFG3); + __raw_writel(msc[0], MSC0); + __raw_writel(msc[1], MSC1); + __raw_writel(sxcnfg, SXCNFG); + __raw_writel(memclkcfg, MEMCLKCFG); + __raw_writel(csadrcfg[0], CSADRCFG0); + __raw_writel(csadrcfg[1], CSADRCFG1); + __raw_writel(csadrcfg[2], CSADRCFG2); + __raw_writel(csadrcfg[3], CSADRCFG3); return 0; } @@ -73,10 +60,6 @@ static int __init smemc_init(void) int ret = 0; if (cpu_is_pxa3xx()) { - smemc_mmio_base = ioremap(SMEMC_PHYS_BASE, SMEMC_PHYS_SIZE); - if (smemc_mmio_base == NULL) - return -ENODEV; - ret = sysdev_class_register(&smemc_sysclass); if (ret) return ret; diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index f736119..0499a69 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -27,6 +27,7 @@ #include <linux/mtd/sharpsl.h> #include <linux/input/matrix_keypad.h> #include <linux/regulator/machine.h> +#include <linux/io.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -44,6 +45,7 @@ #include <mach/pxa2xx_spi.h> #include <mach/spitz.h> #include <mach/sharpsl_pm.h> +#include <mach/smemc.h> #include <plat/i2c.h> @@ -929,9 +931,10 @@ static void spitz_poweroff(void) static void spitz_restart(char mode, const char *cmd) { + uint32_t msc0 = __raw_readl(MSC0); /* Bootloader magic for a reboot */ - if ((MSC0 & 0xffff0000) == 0x7ff00000) - MSC0 = (MSC0 & 0xffff) | 0x7ee00000; + if ((msc0 & 0xffff0000) == 0x7ff00000) + __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0); spitz_poweroff(); } @@ -980,7 +983,7 @@ static void __init spitz_fixup(struct machine_desc *desc, #ifdef CONFIG_MACH_SPITZ MACHINE_START(SPITZ, "SHARP Spitz") .fixup = spitz_fixup, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .init_irq = pxa27x_init_irq, .init_machine = spitz_init, .timer = &pxa_timer, @@ -990,7 +993,7 @@ MACHINE_END #ifdef CONFIG_MACH_BORZOI MACHINE_START(BORZOI, "SHARP Borzoi") .fixup = spitz_fixup, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .init_irq = pxa27x_init_irq, .init_machine = spitz_init, .timer = &pxa_timer, @@ -1000,7 +1003,7 @@ MACHINE_END #ifdef CONFIG_MACH_AKITA MACHINE_START(AKITA, "SHARP Akita") .fixup = spitz_fixup, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .init_irq = pxa27x_init_irq, .init_machine = spitz_init, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 738adc1..3498a14 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -48,6 +48,7 @@ #include <mach/udc.h> #include <mach/pxa2xx_spi.h> #include <mach/pxa27x-udc.h> +#include <mach/smemc.h> #include <linux/spi/spi.h> #include <linux/mfd/da903x.h> @@ -976,7 +977,7 @@ static void __init stargate2_init(void) { /* This is probably a board specific hack as this must be set prior to connecting the MFP stuff up. */ - MECR &= ~MECR_NOS; + __raw_writel(__raw_readl(MECR) & ~MECR_NOS, MECR); pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config)); @@ -998,7 +999,7 @@ static void __init stargate2_init(void) #ifdef CONFIG_MACH_INTELMOTE2 MACHINE_START(INTELMOTE2, "IMOTE 2") - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = imote2_init, @@ -1008,7 +1009,7 @@ MACHINE_END #ifdef CONFIG_MACH_STARGATE2 MACHINE_START(STARGATE2, "Stargate 2") - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .nr_irqs = STARGATE_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index 2ea7545..9cecf83 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c @@ -490,7 +490,7 @@ static void __init tavorevb_init(void) MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)") /* Maintainer: Eric Miao <eric.miao@marvell.com> */ .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa3xx_map_io, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, .init_machine = tavorevb_init, diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c index dc30116..70191a9 100644 --- a/arch/arm/mach-pxa/tavorevb3.c +++ b/arch/arm/mach-pxa/tavorevb3.c @@ -127,7 +127,7 @@ static void __init evb3_init(void) MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa3xx_map_io, .nr_irqs = TAVOREVB3_NR_IRQS, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 0ee1df4..57d61ee 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -46,6 +46,7 @@ #include <mach/tosa_bt.h> #include <mach/pxa2xx_spi.h> #include <mach/audio.h> +#include <mach/smemc.h> #include <asm/mach/arch.h> #include <mach/tosa.h> @@ -893,9 +894,11 @@ static void tosa_poweroff(void) static void tosa_restart(char mode, const char *cmd) { + uint32_t msc0 = __raw_readl(MSC0); + /* Bootloader magic for a reboot */ - if((MSC0 & 0xffff0000) == 0x7ff00000) - MSC0 = (MSC0 & 0xffff) | 0x7ee00000; + if((msc0 & 0xffff0000) == 0x7ff00000) + __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0); tosa_poweroff(); } @@ -953,7 +956,7 @@ static void __init fixup_tosa(struct machine_desc *desc, MACHINE_START(TOSA, "SHARP Tosa") .fixup = fixup_tosa, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .nr_irqs = TOSA_NR_IRQS, .init_irq = pxa25x_init_irq, .init_machine = tosa_init, diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 565d062..43fc9ca 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -47,6 +47,7 @@ #include <mach/mmc.h> #include <mach/irda.h> #include <mach/ohci.h> +#include <mach/smemc.h> #include <plat/i2c.h> #include "generic.h" @@ -539,10 +540,10 @@ static void __init trizeps4_init(void) static void __init trizeps4_map_io(void) { - pxa_map_io(); + pxa27x_map_io(); iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc)); - if ((MSC0 & 0x8) && (BOOT_DEF & 0x1)) { + if ((__raw_readl(MSC0) & 0x8) && (__raw_readl(BOOT_DEF) & 0x1)) { /* if flash is 16 bit wide its a Trizeps4 WL */ __machine_arch_type = MACH_TYPE_TRIZEPS4WL; trizeps4_flash_data[0].width = 2; diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 438fc9a..de69b20 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -983,7 +983,7 @@ static struct map_desc viper_io_desc[] __initdata = { static void __init viper_map_io(void) { - pxa_map_io(); + pxa25x_map_io(); iotable_init(viper_io_desc, ARRAY_SIZE(viper_io_desc)); diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c index f45ac09..b9b5797 100644 --- a/arch/arm/mach-pxa/vpac270.c +++ b/arch/arm/mach-pxa/vpac270.c @@ -719,7 +719,7 @@ static void __init vpac270_init(void) MACHINE_START(VPAC270, "Voipac PXA270") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = vpac270_init diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c index 3260ce7..51c0281 100644 --- a/arch/arm/mach-pxa/xcep.c +++ b/arch/arm/mach-pxa/xcep.c @@ -31,6 +31,7 @@ #include <mach/hardware.h> #include <mach/pxa2xx-regs.h> #include <mach/mfp-pxa25x.h> +#include <mach/smemc.h> #include "generic.h" @@ -172,9 +173,9 @@ static void __init xcep_init(void) /* See Intel XScale Developer's Guide for details */ /* Set RDF and RDN to appropriate values (chip select 3 (smc91x)) */ - MSC1 = (MSC1 & 0xffff) | 0xD5540000; + __raw_writel((__raw_readl(MSC1) & 0xffff) | 0xD5540000, MSC1); /* Set RDF and RDN to appropriate values (chip select 5 (fpga)) */ - MSC2 = (MSC2 & 0xffff) | 0x72A00000; + __raw_writel((__raw_readl(MSC2) & 0xffff) | 0x72A00000, MSC2); platform_add_devices(ARRAY_AND_SIZE(devices)); pxa_set_i2c_info(&xcep_i2c_platform_data); @@ -183,7 +184,7 @@ static void __init xcep_init(void) MACHINE_START(XCEP, "Iskratel XCEP") .boot_params = 0xa0000100, .init_machine = xcep_init, - .map_io = pxa_map_io, + .map_io = pxa25x_map_io, .init_irq = pxa25x_init_irq, .timer = &pxa_timer, MACHINE_END diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index fefde98..527c2a1 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -704,7 +704,7 @@ static void __init z2_init(void) MACHINE_START(ZIPIT2, "Zipit Z2") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa27x_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = z2_init, diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index dea46a2..c87f2b3 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -47,6 +47,7 @@ #include <mach/audio.h> #include <mach/arcom-pcmcia.h> #include <mach/zeus.h> +#include <mach/smemc.h> #include "generic.h" @@ -823,13 +824,16 @@ static mfp_cfg_t zeus_pin_config[] __initdata = { static void __init zeus_init(void) { u16 dm9000_msc = DM9K_MSC_VALUE; + u32 msc0, msc1; system_rev = __raw_readw(ZEUS_CPLD_VERSION); pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f)); /* Fix timings for dm9000s (CS1/CS2)*/ - MSC0 = (MSC0 & 0xffff) | (dm9000_msc << 16); - MSC1 = (MSC1 & 0xffff0000) | dm9000_msc; + msc0 = __raw_readl(MSC0) & 0x0000ffff | (dm9000_msc << 16); + msc1 = __raw_readl(MSC1) & 0xffff0000 | dm9000_msc; + __raw_writel(msc0, MSC0); + __raw_writel(msc1, MSC1); pm_power_off = zeus_power_off; zeus_setup_apm(); @@ -883,7 +887,7 @@ static struct map_desc zeus_io_desc[] __initdata = { static void __init zeus_map_io(void) { - pxa_map_io(); + pxa27x_map_io(); iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc)); diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 702f7a6..a4c784a 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -423,7 +423,7 @@ static void __init zylonite_init(void) MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") .boot_params = 0xa0000100, - .map_io = pxa_map_io, + .map_io = pxa3xx_map_io, .nr_irqs = ZYLONITE_NR_IRQS, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 9e27a84..12052e8 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -2,14 +2,16 @@ # Makefile for the linux kernel, U8500 machine. # -obj-y := clock.o cpu.o devices.o -obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o +obj-y := clock.o cpu.o devices.o devices-common.o +obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o -obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o board-mop500-sdi.o -obj-$(CONFIG_MACH_U5500) += board-u5500.o +obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o board-mop500-sdi.o \ + board-mop500-keypads.o +obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o obj-$(CONFIG_REGULATOR_AB8500) += board-mop500-regulators.o -obj-$(CONFIG_U5500_MODEM_IRQ) += modem_irq.o -obj-$(CONFIG_U5500_MBOX) += mbox.o +obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o +obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o +obj-$(CONFIG_CPU_FREQ) += cpufreq.o diff --git a/arch/arm/mach-ux500/board-mop500-keypads.c b/arch/arm/mach-ux500/board-mop500-keypads.c new file mode 100644 index 0000000..70318c3 --- /dev/null +++ b/arch/arm/mach-ux500/board-mop500-keypads.c @@ -0,0 +1,229 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + * + * Keypad layouts for various boards + */ + +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/mfd/stmpe.h> +#include <linux/mfd/tc3589x.h> +#include <linux/input/matrix_keypad.h> + +#include <plat/pincfg.h> +#include <plat/ske.h> + +#include <mach/devices.h> +#include <mach/hardware.h> + +#include "devices-db8500.h" +#include "board-mop500.h" + +/* STMPE/SKE keypad use this key layout */ +static const unsigned int mop500_keymap[] = { + KEY(2, 5, KEY_END), + KEY(4, 1, KEY_POWER), + KEY(3, 5, KEY_VOLUMEDOWN), + KEY(1, 3, KEY_3), + KEY(5, 2, KEY_RIGHT), + KEY(5, 0, KEY_9), + + KEY(0, 5, KEY_MENU), + KEY(7, 6, KEY_ENTER), + KEY(4, 5, KEY_0), + KEY(6, 7, KEY_2), + KEY(3, 4, KEY_UP), + KEY(3, 3, KEY_DOWN), + + KEY(6, 4, KEY_SEND), + KEY(6, 2, KEY_BACK), + KEY(4, 2, KEY_VOLUMEUP), + KEY(5, 5, KEY_1), + KEY(4, 3, KEY_LEFT), + KEY(3, 2, KEY_7), +}; + +static const struct matrix_keymap_data mop500_keymap_data = { + .keymap = mop500_keymap, + .keymap_size = ARRAY_SIZE(mop500_keymap), +}; + +/* + * Nomadik SKE keypad + */ +#define ROW_PIN_I0 164 +#define ROW_PIN_I1 163 +#define ROW_PIN_I2 162 +#define ROW_PIN_I3 161 +#define ROW_PIN_I4 156 +#define ROW_PIN_I5 155 +#define ROW_PIN_I6 154 +#define ROW_PIN_I7 153 +#define COL_PIN_O0 168 +#define COL_PIN_O1 167 +#define COL_PIN_O2 166 +#define COL_PIN_O3 165 +#define COL_PIN_O4 160 +#define COL_PIN_O5 159 +#define COL_PIN_O6 158 +#define COL_PIN_O7 157 + +#define SKE_KPD_MAX_ROWS 8 +#define SKE_KPD_MAX_COLS 8 + +static int ske_kp_rows[] = { + ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3, + ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7, +}; + +/* + * ske_set_gpio_row: request and set gpio rows + */ +static int ske_set_gpio_row(int gpio) +{ + int ret; + + ret = gpio_request(gpio, "ske-kp"); + if (ret < 0) { + pr_err("ske_set_gpio_row: gpio request failed\n"); + return ret; + } + + ret = gpio_direction_output(gpio, 1); + if (ret < 0) { + pr_err("ske_set_gpio_row: gpio direction failed\n"); + gpio_free(gpio); + } + + return ret; +} + +/* + * ske_kp_init - enable the gpio configuration + */ +static int ske_kp_init(void) +{ + int ret, i; + + for (i = 0; i < SKE_KPD_MAX_ROWS; i++) { + ret = ske_set_gpio_row(ske_kp_rows[i]); + if (ret < 0) { + pr_err("ske_kp_init: failed init\n"); + return ret; + } + } + + return 0; +} + +static struct ske_keypad_platform_data ske_keypad_board = { + .init = ske_kp_init, + .keymap_data = &mop500_keymap_data, + .no_autorepeat = true, + .krow = SKE_KPD_MAX_ROWS, /* 8x8 matrix */ + .kcol = SKE_KPD_MAX_COLS, + .debounce_ms = 40, /* in millisecs */ +}; + +/* + * STMPE1601 + */ +static struct stmpe_keypad_platform_data stmpe1601_keypad_data = { + .debounce_ms = 64, + .scan_count = 8, + .no_autorepeat = true, + .keymap_data = &mop500_keymap_data, +}; + +static struct stmpe_platform_data stmpe1601_data = { + .id = 1, + .blocks = STMPE_BLOCK_KEYPAD, + .irq_trigger = IRQF_TRIGGER_FALLING, + .irq_base = MOP500_STMPE1601_IRQ(0), + .keypad = &stmpe1601_keypad_data, + .autosleep = true, + .autosleep_timeout = 1024, +}; + +static struct i2c_board_info mop500_i2c0_devices_stuib[] = { + { + I2C_BOARD_INFO("stmpe1601", 0x40), + .irq = NOMADIK_GPIO_TO_IRQ(218), + .platform_data = &stmpe1601_data, + .flags = I2C_CLIENT_WAKE, + }, +}; + +/* + * TC35893 + */ + +static const unsigned int uib_keymap[] = { + KEY(3, 1, KEY_END), + KEY(4, 1, KEY_POWER), + KEY(6, 4, KEY_VOLUMEDOWN), + KEY(4, 2, KEY_EMAIL), + KEY(3, 3, KEY_RIGHT), + KEY(2, 5, KEY_BACKSPACE), + + KEY(6, 7, KEY_MENU), + KEY(5, 0, KEY_ENTER), + KEY(4, 3, KEY_0), + KEY(3, 4, KEY_DOT), + KEY(5, 2, KEY_UP), + KEY(3, 5, KEY_DOWN), + + KEY(4, 5, KEY_SEND), + KEY(0, 5, KEY_BACK), + KEY(6, 2, KEY_VOLUMEUP), + KEY(1, 3, KEY_SPACE), + KEY(7, 6, KEY_LEFT), + KEY(5, 5, KEY_SEARCH), +}; + +static struct matrix_keymap_data uib_keymap_data = { + .keymap = uib_keymap, + .keymap_size = ARRAY_SIZE(uib_keymap), +}; + +static struct tc3589x_keypad_platform_data tc35893_data = { + .krow = TC_KPD_ROWS, + .kcol = TC_KPD_COLUMNS, + .debounce_period = TC_KPD_DEBOUNCE_PERIOD, + .settle_time = TC_KPD_SETTLE_TIME, + .irqtype = IRQF_TRIGGER_FALLING, + .enable_wakeup = true, + .keymap_data = &uib_keymap_data, + .no_autorepeat = true, +}; + +static struct tc3589x_platform_data tc3589x_keypad_data = { + .block = TC3589x_BLOCK_KEYPAD, + .keypad = &tc35893_data, + .irq_base = MOP500_EGPIO_IRQ_BASE, +}; + +static struct i2c_board_info mop500_i2c0_devices_uib[] = { + { + I2C_BOARD_INFO("tc3589x", 0x44), + .platform_data = &tc3589x_keypad_data, + .irq = NOMADIK_GPIO_TO_IRQ(218), + .flags = I2C_CLIENT_WAKE, + }, +}; + +void mop500_keypad_init(void) +{ + db8500_add_ske_keypad(&ske_keypad_board); + + i2c_register_board_info(0, mop500_i2c0_devices_stuib, + ARRAY_SIZE(mop500_i2c0_devices_stuib)); + + i2c_register_board_info(0, mop500_i2c0_devices_uib, + ARRAY_SIZE(mop500_i2c0_devices_uib)); + +} diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index bac9956..4b99667 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -16,10 +16,24 @@ #include <mach/devices.h> #include <mach/hardware.h> +#include "devices-db8500.h" #include "pins-db8500.h" #include "board-mop500.h" static pin_cfg_t mop500_sdi_pins[] = { + /* SDI0 (MicroSD slot) */ + GPIO18_MC0_CMDDIR, + GPIO19_MC0_DAT0DIR, + GPIO20_MC0_DAT2DIR, + GPIO21_MC0_DAT31DIR, + GPIO22_MC0_FBCLK, + GPIO23_MC0_CLK, + GPIO24_MC0_CMD, + GPIO25_MC0_DAT0, + GPIO26_MC0_DAT1, + GPIO27_MC0_DAT2, + GPIO28_MC0_DAT3, + /* SDI4 (on-board eMMC) */ GPIO197_MC4_DAT3, GPIO198_MC4_DAT2, @@ -50,6 +64,55 @@ static pin_cfg_t mop500_sdi2_pins[] = { }; /* + * SDI 0 (MicroSD slot) + */ + +/* MMCIPOWER bits */ +#define MCI_DATA2DIREN (1 << 2) +#define MCI_CMDDIREN (1 << 3) +#define MCI_DATA0DIREN (1 << 4) +#define MCI_DATA31DIREN (1 << 5) +#define MCI_FBCLKEN (1 << 7) + +static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd, + unsigned char power_mode) +{ + if (power_mode == MMC_POWER_UP) + gpio_set_value_cansleep(GPIO_SDMMC_EN, 1); + else if (power_mode == MMC_POWER_OFF) + gpio_set_value_cansleep(GPIO_SDMMC_EN, 0); + + return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN | + MCI_DATA2DIREN | MCI_DATA31DIREN; +} + +static struct mmci_platform_data mop500_sdi0_data = { + .vdd_handler = mop500_sdi0_vdd_handler, + .ocr_mask = MMC_VDD_29_30, + .f_max = 100000000, + .capabilities = MMC_CAP_4_BIT_DATA, + .gpio_cd = GPIO_SDMMC_CD, + .gpio_wp = -1, +}; + +void mop500_sdi_tc35892_init(void) +{ + int ret; + + ret = gpio_request(GPIO_SDMMC_EN, "SDMMC_EN"); + if (!ret) + ret = gpio_request(GPIO_SDMMC_1V8_3V_SEL, + "GPIO_SDMMC_1V8_3V_SEL"); + if (ret) + return; + + gpio_direction_output(GPIO_SDMMC_1V8_3V_SEL, 1); + gpio_direction_output(GPIO_SDMMC_EN, 0); + + db8500_add_sdi0(&mop500_sdi0_data); +} + +/* * SDI 2 (POP eMMC, not on DB8500ed) */ @@ -74,18 +137,24 @@ static struct mmci_platform_data mop500_sdi4_data = { .gpio_wp = -1, }; -void mop500_sdi_init(void) +void __init mop500_sdi_init(void) { nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins)); - u8500_sdi2_device.dev.platform_data = &mop500_sdi2_data; - u8500_sdi4_device.dev.platform_data = &mop500_sdi4_data; + /* + * sdi0 will finally be added when the TC35892 initializes and calls + * mop500_sdi_tc35892_init() above. + */ + /* PoP:ed eMMC */ if (!cpu_is_u8500ed()) { nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins)); - amba_device_register(&u8500_sdi2_device, &iomem_resource); + /* POP eMMC on v1.0 has problems with high speed */ + if (!cpu_is_u8500v10()) + mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; + db8500_add_sdi2(&mop500_sdi2_data); } /* On-board eMMC */ - amba_device_register(&u8500_sdi4_device, &iomem_resource); + db8500_add_sdi4(&mop500_sdi4_data); } diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index cac83a6..a1c9ea1 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -13,25 +13,26 @@ #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/i2c.h> #include <linux/gpio.h> #include <linux/amba/bus.h> #include <linux/amba/pl022.h> #include <linux/spi/spi.h> #include <linux/mfd/ab8500.h> -#include <linux/input/matrix_keypad.h> +#include <linux/mfd/tc3589x.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <plat/pincfg.h> #include <plat/i2c.h> -#include <plat/ske.h> #include <mach/hardware.h> #include <mach/setup.h> #include <mach/devices.h> #include <mach/irqs.h> +#include "devices-db8500.h" #include "pins-db8500.h" #include "board-mop500.h" @@ -69,22 +70,12 @@ static pin_cfg_t mop500_pins[] = { GPIO166_KP_O2, GPIO167_KP_O1, GPIO168_KP_O0, -}; -static void ab4500_spi_cs_control(u32 command) -{ - /* set the FRM signal, which is CS - TODO */ -} + /* GPIO_EXP_INT */ + GPIO217_GPIO, -struct pl022_config_chip ab4500_chip_info = { - .com_mode = INTERRUPT_TRANSFER, - .iface = SSP_INTERFACE_MOTOROLA_SPI, - /* we can act as master only */ - .hierarchy = SSP_MASTER, - .slave_tx_disable = 0, - .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, - .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, - .cs_control = ab4500_spi_cs_control, + /* STMPE1601 IRQ */ + GPIO218_GPIO | PIN_INPUT_PULLUP, }; static struct ab8500_platform_data ab8500_platdata = { @@ -93,9 +84,9 @@ static struct ab8500_platform_data ab8500_platdata = { static struct resource ab8500_resources[] = { [0] = { - .start = IRQ_AB8500, - .end = IRQ_AB8500, - .flags = IORESOURCE_IRQ + .start = IRQ_DB8500_AB8500, + .end = IRQ_DB8500_AB8500, + .flags = IORESOURCE_IRQ } }; @@ -109,19 +100,6 @@ struct platform_device ab8500_device = { .resource = ab8500_resources, }; -static struct spi_board_info ab8500_spi_devices[] = { - { - .modalias = "ab8500-spi", - .controller_data = &ab4500_chip_info, - .platform_data = &ab8500_platdata, - .max_speed_hz = 12000000, - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_3, - .irq = IRQ_DB8500_AB8500, - }, -}; - static struct pl022_ssp_controller ssp0_platform_data = { .bus_id = 0, /* pl022 not yet supports dma */ @@ -132,6 +110,34 @@ static struct pl022_ssp_controller ssp0_platform_data = { .num_chipselect = 5, }; +/* + * TC35892 + */ + +static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base) +{ + mop500_sdi_tc35892_init(); +} + +static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = { + .gpio_base = MOP500_EGPIO(0), + .setup = mop500_tc35892_init, +}; + +static struct tc3589x_platform_data mop500_tc35892_data = { + .block = TC3589x_BLOCK_GPIO, + .gpio = &mop500_tc35892_gpio_data, + .irq_base = MOP500_EGPIO_IRQ_BASE, +}; + +static struct i2c_board_info mop500_i2c0_devices[] = { + { + I2C_BOARD_INFO("tc3589x", 0x42), + .irq = NOMADIK_GPIO_TO_IRQ(217), + .platform_data = &mop500_tc35892_data, + }, +}; + #define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \ static struct nmk_i2c_controller u8500_i2c##id##_data = { \ /* \ @@ -161,159 +167,49 @@ U8500_I2C_CONTROLLER(1, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); -static struct amba_device *amba_devs[] __initdata = { - &ux500_uart0_device, - &ux500_uart1_device, - &ux500_uart2_device, - &u8500_ssp0_device, -}; - -static const unsigned int ux500_keymap[] = { - KEY(2, 5, KEY_END), - KEY(4, 1, KEY_POWER), - KEY(3, 5, KEY_VOLUMEDOWN), - KEY(1, 3, KEY_3), - KEY(5, 2, KEY_RIGHT), - KEY(5, 0, KEY_9), - - KEY(0, 5, KEY_MENU), - KEY(7, 6, KEY_ENTER), - KEY(4, 5, KEY_0), - KEY(6, 7, KEY_2), - KEY(3, 4, KEY_UP), - KEY(3, 3, KEY_DOWN), - - KEY(6, 4, KEY_SEND), - KEY(6, 2, KEY_BACK), - KEY(4, 2, KEY_VOLUMEUP), - KEY(5, 5, KEY_1), - KEY(4, 3, KEY_LEFT), - KEY(3, 2, KEY_7), -}; - -static const struct matrix_keymap_data ux500_keymap_data = { - .keymap = ux500_keymap, - .keymap_size = ARRAY_SIZE(ux500_keymap), -}; +static void __init mop500_i2c_init(void) +{ + db8500_add_i2c0(&u8500_i2c0_data); + db8500_add_i2c1(&u8500_i2c1_data); + db8500_add_i2c2(&u8500_i2c2_data); + db8500_add_i2c3(&u8500_i2c3_data); +} -/* - * Nomadik SKE keypad - */ -#define ROW_PIN_I0 164 -#define ROW_PIN_I1 163 -#define ROW_PIN_I2 162 -#define ROW_PIN_I3 161 -#define ROW_PIN_I4 156 -#define ROW_PIN_I5 155 -#define ROW_PIN_I6 154 -#define ROW_PIN_I7 153 -#define COL_PIN_O0 168 -#define COL_PIN_O1 167 -#define COL_PIN_O2 166 -#define COL_PIN_O3 165 -#define COL_PIN_O4 160 -#define COL_PIN_O5 159 -#define COL_PIN_O6 158 -#define COL_PIN_O7 157 - -#define SKE_KPD_MAX_ROWS 8 -#define SKE_KPD_MAX_COLS 8 - -static int ske_kp_rows[] = { - ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3, - ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7, +/* add any platform devices here - TODO */ +static struct platform_device *platform_devs[] __initdata = { }; -/* - * ske_set_gpio_row: request and set gpio rows - */ -static int ske_set_gpio_row(int gpio) +static void __init mop500_spi_init(void) { - int ret; - - ret = gpio_request(gpio, "ske-kp"); - if (ret < 0) { - pr_err("ske_set_gpio_row: gpio request failed\n"); - return ret; - } - - ret = gpio_direction_output(gpio, 1); - if (ret < 0) { - pr_err("ske_set_gpio_row: gpio direction failed\n"); - gpio_free(gpio); - } - - return ret; + db8500_add_ssp0(&ssp0_platform_data); } -/* - * ske_kp_init - enable the gpio configuration - */ -static int ske_kp_init(void) +static void __init mop500_uart_init(void) { - int ret, i; - - for (i = 0; i < SKE_KPD_MAX_ROWS; i++) { - ret = ske_set_gpio_row(ske_kp_rows[i]); - if (ret < 0) { - pr_err("ske_kp_init: failed init\n"); - return ret; - } - } - - return 0; + db8500_add_uart0(); + db8500_add_uart1(); + db8500_add_uart2(); } -static struct ske_keypad_platform_data ske_keypad_board = { - .init = ske_kp_init, - .keymap_data = &ux500_keymap_data, - .no_autorepeat = true, - .krow = SKE_KPD_MAX_ROWS, /* 8x8 matrix */ - .kcol = SKE_KPD_MAX_COLS, - .debounce_ms = 40, /* in millsecs */ -}; - - - -/* add any platform devices here - TODO */ -static struct platform_device *platform_devs[] __initdata = { - &u8500_i2c0_device, - &ux500_i2c1_device, - &ux500_i2c2_device, - &ux500_i2c3_device, - &ux500_ske_keypad_device, -}; - static void __init u8500_init_machine(void) { - int i; - u8500_init_devices(); nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins)); - u8500_i2c0_device.dev.platform_data = &u8500_i2c0_data; - ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data; - ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data; - ux500_i2c3_device.dev.platform_data = &u8500_i2c3_data; - ux500_ske_keypad_device.dev.platform_data = &ske_keypad_board; - - u8500_ssp0_device.dev.platform_data = &ssp0_platform_data; - - /* Register the active AMBA devices on this board */ - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) - amba_device_register(amba_devs[i], &iomem_resource); - platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); + mop500_i2c_init(); mop500_sdi_init(); + mop500_spi_init(); + mop500_uart_init(); + + mop500_keypad_init(); + + platform_device_register(&ab8500_device); - /* If HW is early drop (ED) or V1.0 then use SPI to access AB8500 */ - if (cpu_is_u8500ed() || cpu_is_u8500v10()) - spi_register_board_info(ab8500_spi_devices, - ARRAY_SIZE(ab8500_spi_devices)); - else /* If HW is v.1.1 or later use I2C to access AB8500 */ - platform_device_register(&ab8500_device); + i2c_register_board_info(0, mop500_i2c0_devices, + ARRAY_SIZE(mop500_i2c0_devices)); } MACHINE_START(U8500, "ST-Ericsson MOP500 platform") diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index 2d24032..3104ae2 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -7,6 +7,15 @@ #ifndef __BOARD_MOP500_H #define __BOARD_MOP500_H +#define MOP500_EGPIO(x) (NOMADIK_NR_GPIO + (x)) + +/* GPIOs on the TC35892 expander */ +#define GPIO_SDMMC_CD MOP500_EGPIO(3) +#define GPIO_SDMMC_EN MOP500_EGPIO(17) +#define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18) + extern void mop500_sdi_init(void); +extern void mop500_sdi_tc35892_init(void); +extern void mop500_keypad_init(void); #endif diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c new file mode 100644 index 0000000..54712ac --- /dev/null +++ b/arch/arm/mach-ux500/board-u5500-sdi.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Hanumath Prasad <ulf.hansson@stericsson.com> + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/amba/mmci.h> +#include <linux/mmc/host.h> +#include <linux/gpio.h> + +#include <plat/pincfg.h> +#include <mach/db5500-regs.h> +#include <plat/ste_dma40.h> + +#include "pins-db5500.h" +#include "devices-db5500.h" +#include "ste-dma40-db5500.h" + +static pin_cfg_t u5500_sdi_pins[] = { + /* SDI0 (POP eMMC) */ + GPIO5_MC0_DAT0 | PIN_DIR_INPUT | PIN_PULL_UP, + GPIO6_MC0_DAT1 | PIN_DIR_INPUT | PIN_PULL_UP, + GPIO7_MC0_DAT2 | PIN_DIR_INPUT | PIN_PULL_UP, + GPIO8_MC0_DAT3 | PIN_DIR_INPUT | PIN_PULL_UP, + GPIO9_MC0_DAT4 | PIN_DIR_INPUT | PIN_PULL_UP, + GPIO10_MC0_DAT5 | PIN_DIR_INPUT | PIN_PULL_UP, + GPIO11_MC0_DAT6 | PIN_DIR_INPUT | PIN_PULL_UP, + GPIO12_MC0_DAT7 | PIN_DIR_INPUT | PIN_PULL_UP, + GPIO13_MC0_CMD | PIN_DIR_INPUT | PIN_PULL_UP, + GPIO14_MC0_CLK | PIN_DIR_OUTPUT | PIN_VAL_LOW, +}; + +static struct mmci_platform_data u5500_sdi0_data = { + .ocr_mask = MMC_VDD_165_195, + .f_max = 50000000, + .capabilities = MMC_CAP_4_BIT_DATA | + MMC_CAP_8_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED, + .gpio_cd = -1, + .gpio_wp = -1, +}; + +void __init u5500_sdi_init(void) +{ + nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins)); + + db5500_add_sdi0(&u5500_sdi0_data); +} diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c index 1ca094a..39d370c 100644 --- a/arch/arm/mach-ux500/board-u5500.c +++ b/arch/arm/mach-ux500/board-u5500.c @@ -9,6 +9,7 @@ #include <linux/platform_device.h> #include <linux/amba/bus.h> #include <linux/gpio.h> +#include <linux/irq.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -17,20 +18,24 @@ #include <mach/devices.h> #include <mach/setup.h> -static struct amba_device *amba_board_devs[] __initdata = { - &ux500_uart0_device, - &ux500_uart1_device, - &ux500_uart2_device, -}; +#include "devices-db5500.h" + +static void __init u5500_uart_init(void) +{ + db5500_add_uart0(); + db5500_add_uart1(); + db5500_add_uart2(); +} static void __init u5500_init_machine(void) { u5500_init_devices(); - amba_add_devices(amba_board_devs, ARRAY_SIZE(amba_board_devs)); + u5500_sdi_init(); + u5500_uart_init(); } -MACHINE_START(U8500, "ST-Ericsson U5500 Platform") +MACHINE_START(U5500, "ST-Ericsson U5500 Platform") .boot_params = 0x00000100, .map_io = u5500_map_io, .init_irq = ux500_init_irq, diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index 531de5c..ccff2dae1 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -19,6 +19,12 @@ #include <mach/hardware.h> #include "clock.h" +#ifdef CONFIG_DEBUG_FS +#include <linux/debugfs.h> +#include <linux/uaccess.h> /* for copy_from_user */ +static LIST_HEAD(clk_list); +#endif + #define PRCC_PCKEN 0x00 #define PRCC_PCKDIS 0x04 #define PRCC_KCKEN 0x08 @@ -132,7 +138,7 @@ static unsigned long clk_mtu_get_rate(struct clk *clk) { void __iomem *addr = __io_address(UX500_PRCMU_BASE) + PRCM_TCR; - u32 tcr = readl(addr); + u32 tcr; int mtu = (int) clk->data; /* * One of these is selected eventually @@ -143,6 +149,14 @@ static unsigned long clk_mtu_get_rate(struct clk *clk) unsigned long mturate; unsigned long retclk; + /* + * On a startup, always conifgure the TCR to the doze mode; + * bootloaders do it for us. Do this in the kernel too. + */ + writel(PRCM_TCR_DOZE_MODE, addr); + + tcr = readl(addr); + /* Get the rate from the parent as a default */ if (clk->parent_periph) mturate = clk_get_rate(clk->parent_periph); @@ -152,45 +166,6 @@ static unsigned long clk_mtu_get_rate(struct clk *clk) /* We need to be connected SOMEWHERE */ BUG(); - /* - * Are we in doze mode? - * In this mode the parent peripheral or the fixed 32768 Hz - * clock is fed into the block. - */ - if (!(tcr & PRCM_TCR_DOZE_MODE)) { - /* - * Here we're using the clock input from the APE ULP - * clock domain. But first: are the timers stopped? - */ - if (tcr & PRCM_TCR_STOPPED) { - clk32k = 0; - mturate = 0; - } else { - /* Else default mode: 0 and 2.4 MHz */ - clk32k = 0; - if (cpu_is_u5500()) - /* DB5500 divides by 8 */ - mturate /= 8; - else if (cpu_is_u8500ed()) { - /* - * This clocking setting must not be used - * in the ED chip, it is simply not - * connected anywhere! - */ - mturate = 0; - BUG(); - } else - /* - * In this mode the ulp38m4 clock is divided - * by a factor 16, on the DB8500 typically - * 38400000 / 16 ~ 2.4 MHz. - * TODO: Replace the constant with a reference - * to the ULP source once this is modeled. - */ - mturate = 38400000 / 16; - } - } - /* Return the clock selected for this MTU */ if (tcr & (1 << mtu)) retclk = clk32k; @@ -316,6 +291,7 @@ static struct clkops clk_prcc_ops = { }; static struct clk clk_32khz = { + .name = "clk_32khz", .rate = 32000, }; @@ -365,94 +341,96 @@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ */ /* Peripheral Cluster #1 */ -static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); +static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); -static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); -static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); -static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL); -static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); +static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); +static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); +static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL); +static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); -static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk); -static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); -static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); -static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); -static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); +static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); +static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk); +static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); +static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); +static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); +static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); /* Peripheral Cluster #2 */ static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL); -static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); -static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); -static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); -static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); -static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); +static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); +static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); +static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); +static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL); -static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); -static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); -static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk); +static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); +static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); +static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk); static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL); -static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL); -static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL); -static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL); -static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk); -static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL); +static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL); +static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL); +static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk); +static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk); static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL); -static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL); -static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL); -static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk); +static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL); +static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL); +static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk); /* Peripheral Cluster #3 */ -static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); -static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); -static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); -static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); -static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); -static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk); -static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk); -static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); +static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); +static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); +static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); +static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); +static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); +static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); +static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk); +static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk); +static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); /* Peripheral Cluster #4 is in the always on domain */ /* Peripheral Cluster #5 */ -static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); -static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); -static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL); +static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); +static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); +static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL); /* Peripheral Cluster #6 */ /* MTU ID in data */ static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1); static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0); -static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); -static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); -static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); -static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); -static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL); -static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); -static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); -static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); -static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); -static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk); +static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); +static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); +static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); +static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); +static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL); +static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); +static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); +static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); +static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); +static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk); /* Peripheral Cluster #7 */ -static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); +static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); /* MTU ID in data */ static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1); static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0); -static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); -static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); +static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); +static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); -static struct clk clk_dummy_apb_pclk; +static struct clk clk_dummy_apb_pclk = { + .name = "apb_pclk", +}; static struct clk_lookup u8500_common_clks[] = { CLK(dummy_apb_pclk, NULL, "apb_pclk"), @@ -553,7 +531,7 @@ static struct clk_lookup u8500_ed_clks[] = { static struct clk_lookup u8500_v1_clks[] = { /* Peripheral Cluster #1 */ - CLK(i2c4, "nmk-i2c.4", NULL), + CLK(i2c4, "nmk-i2c.4", NULL), CLK(spi3_v1, "spi3", NULL), CLK(msp1_v1, "msp1", NULL), @@ -598,6 +576,183 @@ static struct clk_lookup u8500_v1_clks[] = { CLK(uiccclk, "uicc", NULL), }; +#ifdef CONFIG_DEBUG_FS +/* + * debugfs support to trace clock tree hierarchy and attributes with + * powerdebug + */ +static struct dentry *clk_debugfs_root; + +void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num) +{ + while (num--) { + /* Check that the clock has not been already registered */ + if (!(cl->clk->list.prev != cl->clk->list.next)) + list_add_tail(&cl->clk->list, &clk_list); + + cl++; + } +} + +static ssize_t usecount_dbg_read(struct file *file, char __user *buf, + size_t size, loff_t *off) +{ + struct clk *clk = file->f_dentry->d_inode->i_private; + char cusecount[128]; + unsigned int len; + + len = sprintf(cusecount, "%u\n", clk->enabled); + return simple_read_from_buffer(buf, size, off, cusecount, len); +} + +static ssize_t rate_dbg_read(struct file *file, char __user *buf, + size_t size, loff_t *off) +{ + struct clk *clk = file->f_dentry->d_inode->i_private; + char crate[128]; + unsigned int rate; + unsigned int len; + + rate = clk_get_rate(clk); + len = sprintf(crate, "%u\n", rate); + return simple_read_from_buffer(buf, size, off, crate, len); +} + +static const struct file_operations usecount_fops = { + .read = usecount_dbg_read, +}; + +static const struct file_operations set_rate_fops = { + .read = rate_dbg_read, +}; + +static struct dentry *clk_debugfs_register_dir(struct clk *c, + struct dentry *p_dentry) +{ + struct dentry *d, *clk_d, *child, *child_tmp; + char s[255]; + char *p = s; + + if (c->name == NULL) + p += sprintf(p, "BUG"); + else + p += sprintf(p, "%s", c->name); + + clk_d = debugfs_create_dir(s, p_dentry); + if (!clk_d) + return NULL; + + d = debugfs_create_file("usecount", S_IRUGO, + clk_d, c, &usecount_fops); + if (!d) + goto err_out; + d = debugfs_create_file("rate", S_IRUGO, + clk_d, c, &set_rate_fops); + if (!d) + goto err_out; + /* + * TODO : not currently available in ux500 + * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags); + * if (!d) + * goto err_out; + */ + + return clk_d; + +err_out: + d = clk_d; + list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child) + debugfs_remove(child); + debugfs_remove(clk_d); + return NULL; +} + +static void clk_debugfs_remove_dir(struct dentry *cdentry) +{ + struct dentry *d, *child, *child_tmp; + + d = cdentry; + list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child) + debugfs_remove(child); + debugfs_remove(cdentry); + return ; +} + +static int clk_debugfs_register_one(struct clk *c) +{ + struct clk *pa = c->parent_periph; + struct clk *bpa = c->parent_cluster; + + if (!(bpa && !pa)) { + c->dent = clk_debugfs_register_dir(c, + pa ? pa->dent : clk_debugfs_root); + if (!c->dent) + return -ENOMEM; + } + + if (bpa) { + c->dent_bus = clk_debugfs_register_dir(c, + bpa->dent_bus ? bpa->dent_bus : bpa->dent); + if ((!c->dent_bus) && (c->dent)) { + clk_debugfs_remove_dir(c->dent); + c->dent = NULL; + return -ENOMEM; + } + } + return 0; +} + +static int clk_debugfs_register(struct clk *c) +{ + int err; + struct clk *pa = c->parent_periph; + struct clk *bpa = c->parent_cluster; + + if (pa && (!pa->dent && !pa->dent_bus)) { + err = clk_debugfs_register(pa); + if (err) + return err; + } + + if (bpa && (!bpa->dent && !bpa->dent_bus)) { + err = clk_debugfs_register(bpa); + if (err) + return err; + } + + if ((!c->dent) && (!c->dent_bus)) { + err = clk_debugfs_register_one(c); + if (err) + return err; + } + return 0; +} + +static int __init clk_debugfs_init(void) +{ + struct clk *c; + struct dentry *d; + int err; + + d = debugfs_create_dir("clock", NULL); + if (!d) + return -ENOMEM; + clk_debugfs_root = d; + + list_for_each_entry(c, &clk_list, list) { + err = clk_debugfs_register(c); + if (err) + goto err_out; + } + return 0; +err_out: + debugfs_remove_recursive(clk_debugfs_root); + return err; +} + +late_initcall(clk_debugfs_init); +#endif /* defined(CONFIG_DEBUG_FS) */ + int __init clk_init(void) { if (cpu_is_u8500ed()) { @@ -608,7 +763,8 @@ int __init clk_init(void) /* Clock tree for U5500 not implemented yet */ clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; - clk_per6clk.rate = 26000000; + clk_uartclk.rate = 36360000; + clk_sdmmcclk.rate = 99900000; } clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); @@ -617,5 +773,12 @@ int __init clk_init(void) else clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); +#ifdef CONFIG_DEBUG_FS + clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); + if (cpu_is_u8500ed()) + clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks)); + else + clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); +#endif return 0; } diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h index a058025..0744907 100644 --- a/arch/arm/mach-ux500/clock.h +++ b/arch/arm/mach-ux500/clock.h @@ -90,6 +90,10 @@ struct clk { struct clk *parent_cluster; struct clk *parent_periph; +#if defined(CONFIG_DEBUG_FS) + struct dentry *dent; /* For visible tree hierarchy */ + struct dentry *dent_bus; /* For visible tree hierarchy */ +#endif }; #define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \ diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c index 2f87075..acc841e 100644 --- a/arch/arm/mach-ux500/cpu-db5500.c +++ b/arch/arm/mach-ux500/cpu-db5500.c @@ -8,14 +8,19 @@ #include <linux/platform_device.h> #include <linux/amba/bus.h> #include <linux/io.h> +#include <linux/irq.h> #include <asm/mach/map.h> +#include <plat/gpio.h> + #include <mach/hardware.h> #include <mach/devices.h> #include <mach/setup.h> #include <mach/irqs.h> +#include "devices-db5500.h" + static struct map_desc u5500_io_desc[] __initdata = { __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K), __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K), @@ -110,19 +115,32 @@ static struct platform_device mbox2_device = { }; static struct platform_device *u5500_platform_devs[] __initdata = { - &u5500_gpio_devs[0], - &u5500_gpio_devs[1], - &u5500_gpio_devs[2], - &u5500_gpio_devs[3], - &u5500_gpio_devs[4], - &u5500_gpio_devs[5], - &u5500_gpio_devs[6], - &u5500_gpio_devs[7], &mbox0_device, &mbox1_device, &mbox2_device, }; +static resource_size_t __initdata db5500_gpio_base[] = { + U5500_GPIOBANK0_BASE, + U5500_GPIOBANK1_BASE, + U5500_GPIOBANK2_BASE, + U5500_GPIOBANK3_BASE, + U5500_GPIOBANK4_BASE, + U5500_GPIOBANK5_BASE, + U5500_GPIOBANK6_BASE, + U5500_GPIOBANK7_BASE, +}; + +static void __init db5500_add_gpios(void) +{ + struct nmk_gpio_platform_data pdata = { + /* No custom data yet */ + }; + + dbx500_add_gpios(ARRAY_AND_SIZE(db5500_gpio_base), + IRQ_DB5500_GPIO0, &pdata); +} + void __init u5500_map_io(void) { ux500_map_io(); @@ -132,7 +150,9 @@ void __init u5500_map_io(void) void __init u5500_init_devices(void) { - ux500_init_devices(); + db5500_add_gpios(); + db5500_dma_init(); + db5500_add_rtc(); platform_add_devices(u5500_platform_devs, ARRAY_SIZE(u5500_platform_devs)); diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 4acab75..c0f34a4 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -22,23 +22,15 @@ #include <mach/setup.h> #include <mach/devices.h> +#include "devices-db8500.h" + static struct platform_device *platform_devs[] __initdata = { - &u8500_gpio_devs[0], - &u8500_gpio_devs[1], - &u8500_gpio_devs[2], - &u8500_gpio_devs[3], - &u8500_gpio_devs[4], - &u8500_gpio_devs[5], - &u8500_gpio_devs[6], - &u8500_gpio_devs[7], - &u8500_gpio_devs[8], &u8500_dma40_device, }; /* minimum static i/o mapping required to boot U8500 platforms */ static struct map_desc u8500_io_desc[] __initdata = { __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), - __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), @@ -46,13 +38,18 @@ static struct map_desc u8500_io_desc[] __initdata = { __MEM_DEV_DESC(U8500_BOOT_ROM_BASE, SZ_1M), }; -static struct map_desc u8500ed_io_desc[] __initdata = { +static struct map_desc u8500_ed_io_desc[] __initdata = { __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K), __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K), }; -static struct map_desc u8500v1_io_desc[] __initdata = { +static struct map_desc u8500_v1_io_desc[] __initdata = { __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), + __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K), +}; + +static struct map_desc u8500_v2_io_desc[] __initdata = { + __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), }; /* @@ -125,14 +122,38 @@ void __init u8500_map_io(void) iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); if (cpu_is_u8500ed()) - iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc)); - else - iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc)); + iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc)); + else if (cpu_is_u8500v1()) + iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc)); + else if (cpu_is_u8500v2()) + iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc)); /* Read out the ASIC ID as early as we can */ get_db8500_asic_id(); } +static resource_size_t __initdata db8500_gpio_base[] = { + U8500_GPIOBANK0_BASE, + U8500_GPIOBANK1_BASE, + U8500_GPIOBANK2_BASE, + U8500_GPIOBANK3_BASE, + U8500_GPIOBANK4_BASE, + U8500_GPIOBANK5_BASE, + U8500_GPIOBANK6_BASE, + U8500_GPIOBANK7_BASE, + U8500_GPIOBANK8_BASE, +}; + +static void __init db8500_add_gpios(void) +{ + struct nmk_gpio_platform_data pdata = { + /* No custom data yet */ + }; + + dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base), + IRQ_DB8500_GPIO0, &pdata); +} + /* * This function is called from the board init */ @@ -152,12 +173,13 @@ void __init u8500_init_devices(void) else pr_warning("ASIC: UNKNOWN SILICON VERSION!\n"); - ux500_init_devices(); - if (cpu_is_u8500ed()) dma40_u8500ed_fixup(); - /* Register the platform devices */ + db8500_add_rtc(); + db8500_add_gpios(); + + platform_device_register_simple("cpufreq-u8500", -1, NULL, 0); platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); return ; diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 7328c01..5730409 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -6,7 +6,6 @@ */ #include <linux/platform_device.h> -#include <linux/amba/bus.h> #include <linux/io.h> #include <linux/clk.h> @@ -20,6 +19,7 @@ #include <mach/hardware.h> #include <mach/setup.h> #include <mach/devices.h> +#include <mach/prcmu.h> #include "clock.h" @@ -45,20 +45,11 @@ static struct map_desc ux500_io_desc[] __initdata = { __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K), }; -static struct amba_device *ux500_amba_devs[] __initdata = { - &ux500_pl031_device, -}; - void __init ux500_map_io(void) { iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc)); } -void __init ux500_init_devices(void) -{ - amba_add_devices(ux500_amba_devs, ARRAY_SIZE(ux500_amba_devs)); -} - void __init ux500_init_irq(void) { gic_init(0, 29, __io_address(UX500_GIC_DIST_BASE), @@ -68,6 +59,8 @@ void __init ux500_init_irq(void) * Init clocks here so that they are available for system timer * initialization. */ + if (cpu_is_u8500()) + prcmu_early_init(); clk_init(); } diff --git a/arch/arm/mach-ux500/cpufreq.c b/arch/arm/mach-ux500/cpufreq.c new file mode 100644 index 0000000..5c5b747 --- /dev/null +++ b/arch/arm/mach-ux500/cpufreq.c @@ -0,0 +1,211 @@ +/* + * CPU frequency scaling for u8500 + * Inspired by linux/arch/arm/mach-davinci/cpufreq.c + * + * Copyright (C) STMicroelectronics 2009 + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + * + * Author: Sundar Iyer <sundar.iyer@stericsson.com> + * Author: Martin Persson <martin.persson@stericsson.com> + * Author: Jonas Aaberg <jonas.aberg@stericsson.com> + * + */ + +#include <linux/platform_device.h> +#include <linux/kernel.h> +#include <linux/cpufreq.h> +#include <linux/delay.h> + +#include <mach/hardware.h> +#include <mach/prcmu.h> +#include <mach/prcmu-defs.h> + +#define DRIVER_NAME "cpufreq-u8500" +#define CPUFREQ_NAME "u8500" + +static struct device *dev; + +static struct cpufreq_frequency_table freq_table[] = { + [0] = { + .index = 0, + .frequency = 200000, + }, + [1] = { + .index = 1, + .frequency = 300000, + }, + [2] = { + .index = 2, + .frequency = 600000, + }, + [3] = { + /* Used for CPU_OPP_MAX, if available */ + .index = 3, + .frequency = CPUFREQ_TABLE_END, + }, + [4] = { + .index = 4, + .frequency = CPUFREQ_TABLE_END, + }, +}; + +static enum prcmu_cpu_opp index2opp[] = { + CPU_OPP_EXT_CLK, + CPU_OPP_50, + CPU_OPP_100, + CPU_OPP_MAX +}; + +static int u8500_cpufreq_verify_speed(struct cpufreq_policy *policy) +{ + return cpufreq_frequency_table_verify(policy, freq_table); +} + +static int u8500_cpufreq_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + struct cpufreq_freqs freqs; + unsigned int index; + int ret = 0; + + /* + * Ensure desired rate is within allowed range. Some govenors + * (ondemand) will just pass target_freq=0 to get the minimum. + */ + if (target_freq < policy->cpuinfo.min_freq) + target_freq = policy->cpuinfo.min_freq; + if (target_freq > policy->cpuinfo.max_freq) + target_freq = policy->cpuinfo.max_freq; + + ret = cpufreq_frequency_table_target(policy, freq_table, + target_freq, relation, &index); + if (ret < 0) { + dev_err(dev, "Could not look up next frequency\n"); + return ret; + } + + freqs.old = policy->cur; + freqs.new = freq_table[index].frequency; + freqs.cpu = policy->cpu; + + if (freqs.old == freqs.new) { + dev_dbg(dev, "Current and target frequencies are equal\n"); + return 0; + } + + dev_dbg(dev, "transition: %u --> %u\n", freqs.old, freqs.new); + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + ret = prcmu_set_cpu_opp(index2opp[index]); + if (ret < 0) { + dev_err(dev, "Failed to set OPP level\n"); + return ret; + } + + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return ret; +} + +static unsigned int u8500_cpufreq_getspeed(unsigned int cpu) +{ + int i; + + for (i = 0; prcmu_get_cpu_opp() != index2opp[i]; i++) + ; + return freq_table[i].frequency; +} + +static int __cpuinit u8500_cpu_init(struct cpufreq_policy *policy) +{ + int res; + + BUILD_BUG_ON(ARRAY_SIZE(index2opp) + 1 != ARRAY_SIZE(freq_table)); + + if (cpu_is_u8500v2()) { + freq_table[1].frequency = 400000; + freq_table[2].frequency = 800000; + if (prcmu_has_arm_maxopp()) + freq_table[3].frequency = 1000000; + } + + /* get policy fields based on the table */ + res = cpufreq_frequency_table_cpuinfo(policy, freq_table); + if (!res) + cpufreq_frequency_table_get_attr(freq_table, policy->cpu); + else { + dev_err(dev, "u8500-cpufreq : Failed to read policy table\n"); + return res; + } + + policy->min = policy->cpuinfo.min_freq; + policy->max = policy->cpuinfo.max_freq; + policy->cur = u8500_cpufreq_getspeed(policy->cpu); + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + + /* + * FIXME : Need to take time measurement across the target() + * function with no/some/all drivers in the notification + * list. + */ + policy->cpuinfo.transition_latency = 200 * 1000; /* in ns */ + + /* policy sharing between dual CPUs */ + cpumask_copy(policy->cpus, &cpu_present_map); + + policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; + + return res; +} + +static struct freq_attr *u8500_cpufreq_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL, +}; +static int u8500_cpu_exit(struct cpufreq_policy *policy) +{ + cpufreq_frequency_table_put_attr(policy->cpu); + return 0; +} + +static struct cpufreq_driver u8500_driver = { + .owner = THIS_MODULE, + .flags = CPUFREQ_STICKY, + .verify = u8500_cpufreq_verify_speed, + .target = u8500_cpufreq_target, + .get = u8500_cpufreq_getspeed, + .init = u8500_cpu_init, + .exit = u8500_cpu_exit, + .name = CPUFREQ_NAME, + .attr = u8500_cpufreq_attr, +}; + +static int __init u8500_cpufreq_probe(struct platform_device *pdev) +{ + dev = &pdev->dev; + return cpufreq_register_driver(&u8500_driver); +} + +static int __exit u8500_cpufreq_remove(struct platform_device *pdev) +{ + return cpufreq_unregister_driver(&u8500_driver); +} + +static struct platform_driver u8500_cpufreq_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, + .remove = __exit_p(u8500_cpufreq_remove), +}; + +static int __init u8500_cpufreq_init(void) +{ + return platform_driver_probe(&u8500_cpufreq_driver, + &u8500_cpufreq_probe); +} + +device_initcall(u8500_cpufreq_init); diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c new file mode 100644 index 0000000..fe69f5f --- /dev/null +++ b/arch/arm/mach-ux500/devices-common.c @@ -0,0 +1,145 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL), version 2. + */ + +#include <linux/kernel.h> +#include <linux/dma-mapping.h> +#include <linux/err.h> +#include <linux/irq.h> +#include <linux/slab.h> +#include <linux/platform_device.h> +#include <linux/amba/bus.h> + +#include <plat/gpio.h> + +#include <mach/hardware.h> + +#include "devices-common.h" + +struct amba_device * +dbx500_add_amba_device(const char *name, resource_size_t base, + int irq, void *pdata, unsigned int periphid) +{ + struct amba_device *dev; + int ret; + + dev = kzalloc(sizeof *dev, GFP_KERNEL); + if (!dev) + return ERR_PTR(-ENOMEM); + + dev->dev.init_name = name; + + dev->res.start = base; + dev->res.end = base + SZ_4K - 1; + dev->res.flags = IORESOURCE_MEM; + + dev->dma_mask = DMA_BIT_MASK(32); + dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + + dev->irq[0] = irq; + dev->irq[1] = NO_IRQ; + + dev->periphid = periphid; + + dev->dev.platform_data = pdata; + + ret = amba_device_register(dev, &iomem_resource); + if (ret) { + kfree(dev); + return ERR_PTR(ret); + } + + return dev; +} + +static struct platform_device * +dbx500_add_platform_device(const char *name, int id, void *pdata, + struct resource *res, int resnum) +{ + struct platform_device *dev; + int ret; + + dev = platform_device_alloc(name, id); + if (!dev) + return ERR_PTR(-ENOMEM); + + dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + dev->dev.dma_mask = &dev->dev.coherent_dma_mask; + + ret = platform_device_add_resources(dev, res, resnum); + if (ret) + goto out_free; + + dev->dev.platform_data = pdata; + + ret = platform_device_add(dev); + if (ret) + goto out_free; + + return dev; + +out_free: + platform_device_put(dev); + return ERR_PTR(ret); +} + +struct platform_device * +dbx500_add_platform_device_4k1irq(const char *name, int id, + resource_size_t base, + int irq, void *pdata) +{ + struct resource resources[] = { + [0] = { + .start = base, + .end = base + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + } + }; + + return dbx500_add_platform_device(name, id, pdata, resources, + ARRAY_SIZE(resources)); +} + +static struct platform_device * +dbx500_add_gpio(int id, resource_size_t addr, int irq, + struct nmk_gpio_platform_data *pdata) +{ + struct resource resources[] = { + { + .start = addr, + .end = addr + 127, + .flags = IORESOURCE_MEM, + }, + { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + } + }; + + return platform_device_register_resndata(NULL, "gpio", id, + resources, ARRAY_SIZE(resources), + pdata, sizeof(*pdata)); +} + +void dbx500_add_gpios(resource_size_t *base, int num, int irq, + struct nmk_gpio_platform_data *pdata) +{ + int first = 0; + int i; + + for (i = 0; i < num; i++, first += 32, irq++) { + pdata->first_gpio = first; + pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first); + + dbx500_add_gpio(i, base[i], irq, pdata); + } +} diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h new file mode 100644 index 0000000..cbadc11 --- /dev/null +++ b/arch/arm/mach-ux500/devices-common.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL), version 2. + */ + +#ifndef __DEVICES_COMMON_H +#define __DEVICES_COMMON_H + +extern struct amba_device * +dbx500_add_amba_device(const char *name, resource_size_t base, + int irq, void *pdata, unsigned int periphid); + +extern struct platform_device * +dbx500_add_platform_device_4k1irq(const char *name, int id, + resource_size_t base, + int irq, void *pdata); + +struct spi_master_cntlr; + +static inline struct amba_device * +dbx500_add_msp_spi(const char *name, resource_size_t base, int irq, + struct spi_master_cntlr *pdata) +{ + return dbx500_add_amba_device(name, base, irq, pdata, 0); +} + +static inline struct amba_device * +dbx500_add_spi(const char *name, resource_size_t base, int irq, + struct spi_master_cntlr *pdata) +{ + return dbx500_add_amba_device(name, base, irq, pdata, 0); +} + +struct mmci_platform_data; + +static inline struct amba_device * +dbx500_add_sdi(const char *name, resource_size_t base, int irq, + struct mmci_platform_data *pdata) +{ + return dbx500_add_amba_device(name, base, irq, pdata, 0); +} + +static inline struct amba_device * +dbx500_add_uart(const char *name, resource_size_t base, int irq) +{ + return dbx500_add_amba_device(name, base, irq, NULL, 0); +} + +struct nmk_i2c_controller; + +static inline struct platform_device * +dbx500_add_i2c(int id, resource_size_t base, int irq, + struct nmk_i2c_controller *pdata) +{ + return dbx500_add_platform_device_4k1irq("nmk-i2c", id, base, irq, + pdata); +} + +struct msp_i2s_platform_data; + +static inline struct platform_device * +dbx500_add_msp_i2s(int id, resource_size_t base, int irq, + struct msp_i2s_platform_data *pdata) +{ + return dbx500_add_platform_device_4k1irq("MSP_I2S", id, base, irq, + pdata); +} + +static inline struct amba_device * +dbx500_add_rtc(resource_size_t base, int irq) +{ + return dbx500_add_amba_device("rtc-pl031", base, irq, NULL, 0); +} + +struct nmk_gpio_platform_data; + +void dbx500_add_gpios(resource_size_t *base, int num, int irq, + struct nmk_gpio_platform_data *pdata); + +#endif diff --git a/arch/arm/mach-ux500/devices-db5500.c b/arch/arm/mach-ux500/devices-db5500.c deleted file mode 100644 index 33e5b56..0000000 --- a/arch/arm/mach-ux500/devices-db5500.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/gpio.h> - -#include <mach/hardware.h> -#include <mach/devices.h> - -static struct nmk_gpio_platform_data u5500_gpio_data[] = { - GPIO_DATA("GPIO-0-31", 0), - GPIO_DATA("GPIO-32-63", 32), /* 36..63 not routed to pin */ - GPIO_DATA("GPIO-64-95", 64), /* 83..95 not routed to pin */ - GPIO_DATA("GPIO-96-127", 96), /* 102..127 not routed to pin */ - GPIO_DATA("GPIO-128-159", 128), /* 149..159 not routed to pin */ - GPIO_DATA("GPIO-160-191", 160), - GPIO_DATA("GPIO-192-223", 192), - GPIO_DATA("GPIO-224-255", 224), /* 228..255 not routed to pin */ -}; - -static struct resource u5500_gpio_resources[] = { - GPIO_RESOURCE(0), - GPIO_RESOURCE(1), - GPIO_RESOURCE(2), - GPIO_RESOURCE(3), - GPIO_RESOURCE(4), - GPIO_RESOURCE(5), - GPIO_RESOURCE(6), - GPIO_RESOURCE(7), -}; - -struct platform_device u5500_gpio_devs[] = { - GPIO_DEVICE(0), - GPIO_DEVICE(1), - GPIO_DEVICE(2), - GPIO_DEVICE(3), - GPIO_DEVICE(4), - GPIO_DEVICE(5), - GPIO_DEVICE(6), - GPIO_DEVICE(7), -}; diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h new file mode 100644 index 0000000..c8d7901 --- /dev/null +++ b/arch/arm/mach-ux500/devices-db5500.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL), version 2. + */ + +#ifndef __DEVICES_DB5500_H +#define __DEVICES_DB5500_H + +#include "devices-common.h" + +#define db5500_add_i2c1(pdata) \ + dbx500_add_i2c(1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata) +#define db5500_add_i2c2(pdata) \ + dbx500_add_i2c(2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata) +#define db5500_add_i2c3(pdata) \ + dbx500_add_i2c(3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata) + +#define db5500_add_msp0_i2s(pdata) \ + dbx500_add_msp_i2s(0, U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata) +#define db5500_add_msp1_i2s(pdata) \ + dbx500_add_msp_i2s(1, U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata) +#define db5500_add_msp2_i2s(pdata) \ + dbx500_add_msp_i2s(2, U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata) + +#define db5500_add_msp0_spi(pdata) \ + dbx500_add_msp_spi("msp0", U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata) +#define db5500_add_msp1_spi(pdata) \ + dbx500_add_msp_spi("msp1", U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata) +#define db5500_add_msp2_spi(pdata) \ + dbx500_add_msp_spi("msp2", U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata) + +#define db5500_add_rtc() \ + dbx500_add_rtc(U5500_RTC_BASE, IRQ_DB5500_RTC); + +#define db5500_add_sdi0(pdata) \ + dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata) +#define db5500_add_sdi1(pdata) \ + dbx500_add_sdi("sdi1", U5500_SDI1_BASE, IRQ_DB5500_SDMMC1, pdata) +#define db5500_add_sdi2(pdata) \ + dbx500_add_sdi("sdi2", U5500_SDI2_BASE, IRQ_DB5500_SDMMC2, pdata) +#define db5500_add_sdi3(pdata) \ + dbx500_add_sdi("sdi3", U5500_SDI3_BASE, IRQ_DB5500_SDMMC3, pdata) +#define db5500_add_sdi4(pdata) \ + dbx500_add_sdi("sdi4", U5500_SDI4_BASE, IRQ_DB5500_SDMMC4, pdata) + +#define db5500_add_spi0(pdata) \ + dbx500_add_spi("spi0", U5500_SPI0_BASE, IRQ_DB5500_SPI0, pdata) +#define db5500_add_spi1(pdata) \ + dbx500_add_spi("spi1", U5500_SPI1_BASE, IRQ_DB5500_SPI1, pdata) +#define db5500_add_spi2(pdata) \ + dbx500_add_spi("spi2", U5500_SPI2_BASE, IRQ_DB5500_SPI2, pdata) +#define db5500_add_spi3(pdata) \ + dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata) + +#define db5500_add_uart0() \ + dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0) +#define db5500_add_uart1() \ + dbx500_add_uart("uart1", U5500_UART1_BASE, IRQ_DB5500_UART1) +#define db5500_add_uart2() \ + dbx500_add_uart("uart2", U5500_UART2_BASE, IRQ_DB5500_UART2) +#define db5500_add_uart3() \ + dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3) + +#endif diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 4a94be3..23c695d5 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -19,173 +19,6 @@ #include "ste-dma40-db8500.h" -static struct nmk_gpio_platform_data u8500_gpio_data[] = { - GPIO_DATA("GPIO-0-31", 0), - GPIO_DATA("GPIO-32-63", 32), /* 37..63 not routed to pin */ - GPIO_DATA("GPIO-64-95", 64), - GPIO_DATA("GPIO-96-127", 96), /* 98..127 not routed to pin */ - GPIO_DATA("GPIO-128-159", 128), - GPIO_DATA("GPIO-160-191", 160), /* 172..191 not routed to pin */ - GPIO_DATA("GPIO-192-223", 192), - GPIO_DATA("GPIO-224-255", 224), /* 231..255 not routed to pin */ - GPIO_DATA("GPIO-256-288", 256), /* 268..288 not routed to pin */ -}; - -static struct resource u8500_gpio_resources[] = { - GPIO_RESOURCE(0), - GPIO_RESOURCE(1), - GPIO_RESOURCE(2), - GPIO_RESOURCE(3), - GPIO_RESOURCE(4), - GPIO_RESOURCE(5), - GPIO_RESOURCE(6), - GPIO_RESOURCE(7), - GPIO_RESOURCE(8), -}; - -struct platform_device u8500_gpio_devs[] = { - GPIO_DEVICE(0), - GPIO_DEVICE(1), - GPIO_DEVICE(2), - GPIO_DEVICE(3), - GPIO_DEVICE(4), - GPIO_DEVICE(5), - GPIO_DEVICE(6), - GPIO_DEVICE(7), - GPIO_DEVICE(8), -}; - -struct amba_device u8500_ssp0_device = { - .dev = { - .coherent_dma_mask = ~0, - .init_name = "ssp0", - }, - .res = { - .start = U8500_SSP0_BASE, - .end = U8500_SSP0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .irq = {IRQ_DB8500_SSP0, NO_IRQ }, - /* ST-Ericsson modified id */ - .periphid = SSP_PER_ID, -}; - -static struct resource u8500_i2c0_resources[] = { - [0] = { - .start = U8500_I2C0_BASE, - .end = U8500_I2C0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_DB8500_I2C0, - .end = IRQ_DB8500_I2C0, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device u8500_i2c0_device = { - .name = "nmk-i2c", - .id = 0, - .resource = u8500_i2c0_resources, - .num_resources = ARRAY_SIZE(u8500_i2c0_resources), -}; - -static struct resource u8500_i2c4_resources[] = { - [0] = { - .start = U8500_I2C4_BASE, - .end = U8500_I2C4_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_DB8500_I2C4, - .end = IRQ_DB8500_I2C4, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device u8500_i2c4_device = { - .name = "nmk-i2c", - .id = 4, - .resource = u8500_i2c4_resources, - .num_resources = ARRAY_SIZE(u8500_i2c4_resources), -}; - -/* - * SD/MMC - */ - -struct amba_device u8500_sdi0_device = { - .dev = { - .init_name = "sdi0", - }, - .res = { - .start = U8500_SDI0_BASE, - .end = U8500_SDI0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .irq = {IRQ_DB8500_SDMMC0, NO_IRQ}, -}; - -struct amba_device u8500_sdi1_device = { - .dev = { - .init_name = "sdi1", - }, - .res = { - .start = U8500_SDI1_BASE, - .end = U8500_SDI1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .irq = {IRQ_DB8500_SDMMC1, NO_IRQ}, -}; - -struct amba_device u8500_sdi2_device = { - .dev = { - .init_name = "sdi2", - }, - .res = { - .start = U8500_SDI2_BASE, - .end = U8500_SDI2_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .irq = {IRQ_DB8500_SDMMC2, NO_IRQ}, -}; - -struct amba_device u8500_sdi3_device = { - .dev = { - .init_name = "sdi3", - }, - .res = { - .start = U8500_SDI3_BASE, - .end = U8500_SDI3_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .irq = {IRQ_DB8500_SDMMC3, NO_IRQ}, -}; - -struct amba_device u8500_sdi4_device = { - .dev = { - .init_name = "sdi4", - }, - .res = { - .start = U8500_SDI4_BASE, - .end = U8500_SDI4_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .irq = {IRQ_DB8500_SDMMC4, NO_IRQ}, -}; - -struct amba_device u8500_sdi5_device = { - .dev = { - .init_name = "sdi5", - }, - .res = { - .start = U8500_SDI5_BASE, - .end = U8500_SDI5_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .irq = {IRQ_DB8500_SDMMC5, NO_IRQ}, -}; - static struct resource dma40_resources[] = { [0] = { .start = U8500_DMA_BASE, @@ -295,7 +128,7 @@ struct resource keypad_resources[] = { }, }; -struct platform_device ux500_ske_keypad_device = { +struct platform_device u8500_ske_keypad_device = { .name = "nmk-ske-keypad", .id = -1, .num_resources = ARRAY_SIZE(keypad_resources), diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h new file mode 100644 index 0000000..3a770c7 --- /dev/null +++ b/arch/arm/mach-ux500/devices-db8500.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * License terms: GNU General Public License (GPL), version 2. + */ + +#ifndef __DEVICES_DB8500_H +#define __DEVICES_DB8500_H + +#include "devices-common.h" + +struct ske_keypad_platform_data; +struct pl022_ssp_controller; + +static inline struct platform_device * +db8500_add_ske_keypad(struct ske_keypad_platform_data *pdata) +{ + return dbx500_add_platform_device_4k1irq("nmk-ske-keypad", -1, + U8500_SKE_BASE, + IRQ_DB8500_KB, pdata); +} + +static inline struct amba_device * +db8500_add_ssp(const char *name, resource_size_t base, int irq, + struct pl022_ssp_controller *pdata) +{ + return dbx500_add_amba_device(name, base, irq, pdata, SSP_PER_ID); +} + + +#define db8500_add_i2c0(pdata) \ + dbx500_add_i2c(0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata) +#define db8500_add_i2c1(pdata) \ + dbx500_add_i2c(1, U8500_I2C1_BASE, IRQ_DB8500_I2C1, pdata) +#define db8500_add_i2c2(pdata) \ + dbx500_add_i2c(2, U8500_I2C2_BASE, IRQ_DB8500_I2C2, pdata) +#define db8500_add_i2c3(pdata) \ + dbx500_add_i2c(3, U8500_I2C3_BASE, IRQ_DB8500_I2C3, pdata) +#define db8500_add_i2c4(pdata) \ + dbx500_add_i2c(4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata) + +#define db8500_add_msp0_i2s(pdata) \ + dbx500_add_msp_i2s(0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata) +#define db8500_add_msp1_i2s(pdata) \ + dbx500_add_msp_i2s(1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata) +#define db8500_add_msp2_i2s(pdata) \ + dbx500_add_msp_i2s(2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata) +#define db8500_add_msp3_i2s(pdata) \ + dbx500_add_msp_i2s(3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata) + +#define db8500_add_msp0_spi(pdata) \ + dbx500_add_msp_spi("msp0", U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata) +#define db8500_add_msp1_spi(pdata) \ + dbx500_add_msp_spi("msp1", U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata) +#define db8500_add_msp2_spi(pdata) \ + dbx500_add_msp_spi("msp2", U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata) +#define db8500_add_msp3_spi(pdata) \ + dbx500_add_msp_spi("msp3", U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata) + +#define db8500_add_rtc() \ + dbx500_add_rtc(U8500_RTC_BASE, IRQ_DB8500_RTC); + +#define db8500_add_sdi0(pdata) \ + dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata) +#define db8500_add_sdi1(pdata) \ + dbx500_add_sdi("sdi1", U8500_SDI1_BASE, IRQ_DB8500_SDMMC1, pdata) +#define db8500_add_sdi2(pdata) \ + dbx500_add_sdi("sdi2", U8500_SDI2_BASE, IRQ_DB8500_SDMMC2, pdata) +#define db8500_add_sdi3(pdata) \ + dbx500_add_sdi("sdi3", U8500_SDI3_BASE, IRQ_DB8500_SDMMC3, pdata) +#define db8500_add_sdi4(pdata) \ + dbx500_add_sdi("sdi4", U8500_SDI4_BASE, IRQ_DB8500_SDMMC4, pdata) +#define db8500_add_sdi5(pdata) \ + dbx500_add_sdi("sdi5", U8500_SDI5_BASE, IRQ_DB8500_SDMMC5, pdata) + +#define db8500_add_ssp0(pdata) \ + db8500_add_ssp("ssp0", U8500_SSP0_BASE, IRQ_DB8500_SSP0, pdata) +#define db8500_add_ssp1(pdata) \ + db8500_add_ssp("ssp1", U8500_SSP1_BASE, IRQ_DB8500_SSP1, pdata) + +#define db8500_add_spi0(pdata) \ + dbx500_add_spi("spi0", U8500_SPI0_BASE, IRQ_DB8500_SPI0, pdata) +#define db8500_add_spi1(pdata) \ + dbx500_add_spi("spi1", U8500_SPI1_BASE, IRQ_DB8500_SPI1, pdata) +#define db8500_add_spi2(pdata) \ + dbx500_add_spi("spi2", U8500_SPI2_BASE, IRQ_DB8500_SPI2, pdata) +#define db8500_add_spi3(pdata) \ + dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata) + +#define db8500_add_uart0() \ + dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0) +#define db8500_add_uart1() \ + dbx500_add_uart("uart1", U8500_UART1_BASE, IRQ_DB8500_UART1) +#define db8500_add_uart2() \ + dbx500_add_uart("uart2", U8500_UART2_BASE, IRQ_DB8500_UART2) + +#endif diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c index 8a26889..ea0a2f9 100644 --- a/arch/arm/mach-ux500/devices.c +++ b/arch/arm/mach-ux500/devices.c @@ -14,69 +14,6 @@ #include <mach/hardware.h> #include <mach/setup.h> -#define __MEM_4K_RESOURCE(x) \ - .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM} - -struct amba_device ux500_pl031_device = { - .dev = { - .init_name = "pl031", - }, - .res = { - .start = UX500_RTC_BASE, - .end = UX500_RTC_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - .irq = {IRQ_RTC_RTT, NO_IRQ}, -}; - -struct amba_device ux500_uart0_device = { - .dev = { .init_name = "uart0" }, - __MEM_4K_RESOURCE(UX500_UART0_BASE), - .irq = {IRQ_UART0, NO_IRQ}, -}; - -struct amba_device ux500_uart1_device = { - .dev = { .init_name = "uart1" }, - __MEM_4K_RESOURCE(UX500_UART1_BASE), - .irq = {IRQ_UART1, NO_IRQ}, -}; - -struct amba_device ux500_uart2_device = { - .dev = { .init_name = "uart2" }, - __MEM_4K_RESOURCE(UX500_UART2_BASE), - .irq = {IRQ_UART2, NO_IRQ}, -}; - -#define UX500_I2C_RESOURCES(id, size) \ -static struct resource ux500_i2c##id##_resources[] = { \ - [0] = { \ - .start = UX500_I2C##id##_BASE, \ - .end = UX500_I2C##id##_BASE + size - 1, \ - .flags = IORESOURCE_MEM, \ - }, \ - [1] = { \ - .start = IRQ_I2C##id, \ - .end = IRQ_I2C##id, \ - .flags = IORESOURCE_IRQ \ - } \ -} - -UX500_I2C_RESOURCES(1, SZ_4K); -UX500_I2C_RESOURCES(2, SZ_4K); -UX500_I2C_RESOURCES(3, SZ_4K); - -#define UX500_I2C_PDEVICE(cid) \ -struct platform_device ux500_i2c##cid##_device = { \ - .name = "nmk-i2c", \ - .id = cid, \ - .num_resources = 2, \ - .resource = ux500_i2c##cid##_resources, \ -} - -UX500_I2C_PDEVICE(1); -UX500_I2C_PDEVICE(2); -UX500_I2C_PDEVICE(3); - void __init amba_add_devices(struct amba_device *devs[], int num) { int i; diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c new file mode 100644 index 0000000..32a061f --- /dev/null +++ b/arch/arm/mach-ux500/dma-db5500.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson + * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson + * Author: Rabin Vincent <rabinv.vincent@stericsson.com> for ST-Ericsson + * + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <plat/ste_dma40.h> +#include <mach/setup.h> +#include <mach/hardware.h> + +#include "ste-dma40-db5500.h" + +static struct resource dma40_resources[] = { + [0] = { + .start = U5500_DMA_BASE, + .end = U5500_DMA_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + .name = "base", + }, + [1] = { + .start = U5500_DMA_LCPA_BASE, + .end = U5500_DMA_LCPA_BASE + 2 * SZ_1K - 1, + .flags = IORESOURCE_MEM, + .name = "lcpa", + }, + [2] = { + .start = IRQ_DB5500_DMA, + .end = IRQ_DB5500_DMA, + .flags = IORESOURCE_IRQ + } +}; + +/* Default configuration for physical memcpy */ +static struct stedma40_chan_cfg dma40_memcpy_conf_phy = { + .mode = STEDMA40_MODE_PHYSICAL, + .dir = STEDMA40_MEM_TO_MEM, + + .src_info.data_width = STEDMA40_BYTE_WIDTH, + .src_info.psize = STEDMA40_PSIZE_PHY_1, + .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, + + .dst_info.data_width = STEDMA40_BYTE_WIDTH, + .dst_info.psize = STEDMA40_PSIZE_PHY_1, + .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, +}; + +/* Default configuration for logical memcpy */ +static struct stedma40_chan_cfg dma40_memcpy_conf_log = { + .dir = STEDMA40_MEM_TO_MEM, + + .src_info.data_width = STEDMA40_BYTE_WIDTH, + .src_info.psize = STEDMA40_PSIZE_LOG_1, + .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, + + .dst_info.data_width = STEDMA40_BYTE_WIDTH, + .dst_info.psize = STEDMA40_PSIZE_LOG_1, + .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, +}; + +/* + * Mapping between soruce event lines and physical device address This was + * created assuming that the event line is tied to a device and therefore the + * address is constant, however this is not true for at least USB, and the + * values are just placeholders for USB. This table is preserved and used for + * now. + */ +static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = { + [DB5500_DMA_DEV24_SDMMC0_RX] = -1, +}; + +/* Mapping between destination event lines and physical device address */ +static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = { + [DB5500_DMA_DEV24_SDMMC0_TX] = -1, +}; + +static int dma40_memcpy_event[] = { + DB5500_DMA_MEMCPY_TX_1, + DB5500_DMA_MEMCPY_TX_2, + DB5500_DMA_MEMCPY_TX_3, + DB5500_DMA_MEMCPY_TX_4, + DB5500_DMA_MEMCPY_TX_5, +}; + +static struct stedma40_platform_data dma40_plat_data = { + .dev_len = ARRAY_SIZE(dma40_rx_map), + .dev_rx = dma40_rx_map, + .dev_tx = dma40_tx_map, + .memcpy = dma40_memcpy_event, + .memcpy_len = ARRAY_SIZE(dma40_memcpy_event), + .memcpy_conf_phy = &dma40_memcpy_conf_phy, + .memcpy_conf_log = &dma40_memcpy_conf_log, + .disabled_channels = {-1}, +}; + +static struct platform_device dma40_device = { + .dev = { + .platform_data = &dma40_plat_data, + }, + .name = "dma40", + .id = 0, + .num_resources = ARRAY_SIZE(dma40_resources), + .resource = dma40_resources +}; + +void __init db5500_dma_init(void) +{ + int ret; + + ret = platform_device_register(&dma40_device); + if (ret) + dev_err(&dma40_device.dev, "unable to register device: %d\n", ret); + +} diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h index 3eafc0e..bd88c1e 100644 --- a/arch/arm/mach-ux500/include/mach/db5500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h @@ -114,4 +114,8 @@ #define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20) #define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F) +#define U5500_ESRAM_BASE 0x40000000 +#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000 +#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET) + #endif diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index f07d098..0fefb34 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -92,7 +92,8 @@ #define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) #define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) -#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000) +#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) +#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) /* per3 base addresses */ #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h index b91a4d1..020b636 100644 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -14,27 +14,10 @@ extern struct platform_device u5500_gpio_devs[]; extern struct platform_device u8500_gpio_devs[]; extern struct amba_device ux500_pl031_device; -extern struct amba_device u8500_ssp0_device; -extern struct amba_device ux500_uart0_device; -extern struct amba_device ux500_uart1_device; -extern struct amba_device ux500_uart2_device; -extern struct platform_device ux500_i2c1_device; -extern struct platform_device ux500_i2c2_device; -extern struct platform_device ux500_i2c3_device; - -extern struct platform_device u8500_i2c0_device; -extern struct platform_device u8500_i2c4_device; extern struct platform_device u8500_dma40_device; extern struct platform_device ux500_ske_keypad_device; -extern struct amba_device u8500_sdi0_device; -extern struct amba_device u8500_sdi1_device; -extern struct amba_device u8500_sdi2_device; -extern struct amba_device u8500_sdi3_device; -extern struct amba_device u8500_sdi4_device; -extern struct amba_device u8500_sdi5_device; - void dma40_u8500ed_fixup(void); #endif diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h index d548a62..3c4cd31 100644 --- a/arch/arm/mach-ux500/include/mach/gpio.h +++ b/arch/arm/mach-ux500/include/mach/gpio.h @@ -9,42 +9,4 @@ #include <plat/gpio.h> -#define __GPIO_RESOURCE(soc, block) \ - { \ - .start = soc##_GPIOBANK##block##_BASE, \ - .end = soc##_GPIOBANK##block##_BASE + 127, \ - .flags = IORESOURCE_MEM, \ - }, \ - { \ - .start = IRQ_GPIO##block, \ - .end = IRQ_GPIO##block, \ - .flags = IORESOURCE_IRQ, \ - } - -#define __GPIO_DEVICE(soc, block) \ - { \ - .name = "gpio", \ - .id = block, \ - .num_resources = 2, \ - .resource = &soc##_gpio_resources[block * 2], \ - .dev = { \ - .platform_data = &soc##_gpio_data[block], \ - }, \ - } - -#define GPIO_DATA(_name, first) \ - { \ - .name = _name, \ - .first_gpio = first, \ - .first_irq = NOMADIK_GPIO_TO_IRQ(first), \ - } - -#ifdef CONFIG_UX500_SOC_DB8500 -#define GPIO_RESOURCE(block) __GPIO_RESOURCE(U8500, block) -#define GPIO_DEVICE(block) __GPIO_DEVICE(u8500, block) -#elif defined(CONFIG_UX500_SOC_DB5500) -#define GPIO_RESOURCE(block) __GPIO_RESOURCE(U5500, block) -#define GPIO_DEVICE(block) __GPIO_DEVICE(u5500, block) -#endif - #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index 32e883a..6295cc5 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -142,6 +142,8 @@ static inline bool cpu_is_u5500(void) #endif } +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) + #endif #endif /* __MACH_HARDWARE_H */ diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h index cca4f70..7cdeb2a 100644 --- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h +++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h @@ -8,12 +8,36 @@ #ifndef __MACH_IRQS_BOARD_MOP500_H #define __MACH_IRQS_BOARD_MOP500_H -#define AB8500_NR_IRQS 104 +/* Number of AB8500 irqs is taken from header file */ +#include <linux/mfd/ab8500.h> #define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START #define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \ + AB8500_NR_IRQS) -#define MOP500_IRQ_END MOP500_AB8500_IRQ_END + +/* TC35892 */ +#define TC35892_NR_INTERNAL_IRQS 8 +#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x)) +#define TC35892_NR_GPIOS 24 +#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS) + +#define MOP500_EGPIO_NR_IRQS TC35892_NR_IRQS + +#define MOP500_EGPIO_IRQ_BASE MOP500_AB8500_IRQ_END +#define MOP500_EGPIO_IRQ_END (MOP500_EGPIO_IRQ_BASE \ + + MOP500_EGPIO_NR_IRQS) +/* STMPE1601 irqs */ +#define STMPE_NR_INTERNAL_IRQS 9 +#define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x)) +#define STMPE_NR_GPIOS 24 +#define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS) + +#define MOP500_STMPE1601_IRQBASE MOP500_EGPIO_IRQ_END +#define MOP500_STMPE1601_IRQ(x) (MOP500_STMPE1601_IRQBASE + (x)) + +#define MOP500_NR_IRQS MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) + +#define MOP500_IRQ_END MOP500_NR_IRQS #if MOP500_IRQ_END > IRQ_BOARD_END #undef IRQ_BOARD_END diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h index 693aa57..880ae45 100644 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ b/arch/arm/mach-ux500/include/mach/irqs.h @@ -21,50 +21,6 @@ /* Interrupt numbers generic for shared peripheral */ #define IRQ_MTU0 (IRQ_SHPI_START + 4) -#define IRQ_SPI2 (IRQ_SHPI_START + 6) -#define IRQ_SPI0 (IRQ_SHPI_START + 8) -#define IRQ_UART0 (IRQ_SHPI_START + 11) -#define IRQ_I2C3 (IRQ_SHPI_START + 12) -#define IRQ_SSP0 (IRQ_SHPI_START + 14) -#define IRQ_MTU1 (IRQ_SHPI_START + 17) -#define IRQ_RTC_RTT (IRQ_SHPI_START + 18) -#define IRQ_UART1 (IRQ_SHPI_START + 19) -#define IRQ_I2C0 (IRQ_SHPI_START + 21) -#define IRQ_I2C1 (IRQ_SHPI_START + 22) -#define IRQ_USBOTG (IRQ_SHPI_START + 23) -#define IRQ_DMA (IRQ_SHPI_START + 25) -#define IRQ_UART2 (IRQ_SHPI_START + 26) -#define IRQ_HSIR_EXCEP (IRQ_SHPI_START + 29) -#define IRQ_MSP0 (IRQ_SHPI_START + 31) -#define IRQ_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32) -#define IRQ_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33) -#define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) -#define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) -#define IRQ_AB8500 (IRQ_SHPI_START + 40) -#define IRQ_PRCMU (IRQ_SHPI_START + 47) -#define IRQ_DISP (IRQ_SHPI_START + 48) -#define IRQ_SiPI3 (IRQ_SHPI_START + 49) -#define IRQ_I2C4 (IRQ_SHPI_START + 51) -#define IRQ_SSP1 (IRQ_SHPI_START + 52) -#define IRQ_I2C2 (IRQ_SHPI_START + 55) -#define IRQ_SDMMC0 (IRQ_SHPI_START + 60) -#define IRQ_MSP1 (IRQ_SHPI_START + 62) -#define IRQ_SPI1 (IRQ_SHPI_START + 96) -#define IRQ_MSP2 (IRQ_SHPI_START + 98) -#define IRQ_SDMMC4 (IRQ_SHPI_START + 99) -#define IRQ_HSIRD0 (IRQ_SHPI_START + 104) -#define IRQ_HSIRD1 (IRQ_SHPI_START + 105) -#define IRQ_HSITD0 (IRQ_SHPI_START + 106) -#define IRQ_HSITD1 (IRQ_SHPI_START + 107) -#define IRQ_GPIO0 (IRQ_SHPI_START + 119) -#define IRQ_GPIO1 (IRQ_SHPI_START + 120) -#define IRQ_GPIO2 (IRQ_SHPI_START + 121) -#define IRQ_GPIO3 (IRQ_SHPI_START + 122) -#define IRQ_GPIO4 (IRQ_SHPI_START + 123) -#define IRQ_GPIO5 (IRQ_SHPI_START + 124) -#define IRQ_GPIO6 (IRQ_SHPI_START + 125) -#define IRQ_GPIO7 (IRQ_SHPI_START + 126) -#define IRQ_GPIO8 (IRQ_SHPI_START + 127) /* There are 128 shared peripheral interrupts assigned to * INTID[160:32]. The first 32 interrupts are reserved. diff --git a/arch/arm/mach-ux500/include/mach/mbox.h b/arch/arm/mach-ux500/include/mach/mbox-db5500.h index 7f9da4d..7f9da4d 100644 --- a/arch/arm/mach-ux500/include/mach/mbox.h +++ b/arch/arm/mach-ux500/include/mach/mbox-db5500.h diff --git a/arch/arm/mach-ux500/include/mach/prcmu-defs.h b/arch/arm/mach-ux500/include/mach/prcmu-defs.h new file mode 100644 index 0000000..848ba64 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/prcmu-defs.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) STMicroelectronics 2009 + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Sundar Iyer <sundar.iyer@stericsson.com> + * Author: Martin Persson <martin.persson@stericsson.com> + * + * License Terms: GNU General Public License v2 + * + * PRCM Unit definitions + */ + +#ifndef __MACH_PRCMU_DEFS_H +#define __MACH_PRCMU_DEFS_H + +enum prcmu_cpu_opp { + CPU_OPP_INIT = 0x00, + CPU_OPP_NO_CHANGE = 0x01, + CPU_OPP_100 = 0x02, + CPU_OPP_50 = 0x03, + CPU_OPP_MAX = 0x04, + CPU_OPP_EXT_CLK = 0x07 +}; +enum prcmu_ape_opp { + APE_OPP_NO_CHANGE = 0x00, + APE_OPP_100 = 0x02, + APE_OPP_50 = 0x03, +}; + +#endif /* __MACH_PRCMU_DEFS_H */ diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h index 8885f39..455467e 100644 --- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h +++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h @@ -1,10 +1,15 @@ /* - * Copyright (c) 2009 ST-Ericsson SA + * Copyright (C) STMicroelectronics 2009 + * Copyright (C) ST-Ericsson SA 2010 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. + * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> + * Author: Sundar Iyer <sundar.iyer@stericsson.com> + * + * License Terms: GNU General Public License v2 + * + * PRCM Unit registers */ + #ifndef __MACH_PRCMU_REGS_H #define __MACH_PRCMU_REGS_H @@ -88,4 +93,4 @@ /* Miscellaneous unit registers */ #define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324) -#endif /* __MACH_PRCMU__REGS_H */ +#endif /* __MACH_PRCMU_REGS_H */ diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h index 549843f..c49e456 100644 --- a/arch/arm/mach-ux500/include/mach/prcmu.h +++ b/arch/arm/mach-ux500/include/mach/prcmu.h @@ -2,14 +2,27 @@ * Copyright (C) STMicroelectronics 2009 * Copyright (C) ST-Ericsson SA 2010 * + * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> + * Author: Sundar Iyer <sundar.iyer@stericsson.com> + * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> + * * License Terms: GNU General Public License v2 * - * PRCMU f/w APIs + * PRCM Unit f/w API */ #ifndef __MACH_PRCMU_H #define __MACH_PRCMU_H +#include <mach/prcmu-defs.h> +void __init prcmu_early_init(void); int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); +int prcmu_set_ape_opp(enum prcmu_ape_opp opp); +int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp); +int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp, + enum prcmu_cpu_opp cpu_opp); +int prcmu_get_ape_opp(void); +int prcmu_get_cpu_opp(void); +bool prcmu_has_arm_maxopp(void); #endif /* __MACH_PRCMU_H */ diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h index 54bbe64..469877e 100644 --- a/arch/arm/mach-ux500/include/mach/setup.h +++ b/arch/arm/mach-ux500/include/mach/setup.h @@ -18,14 +18,19 @@ extern void __init ux500_map_io(void); extern void __init u5500_map_io(void); extern void __init u8500_map_io(void); -extern void __init ux500_init_devices(void); extern void __init u5500_init_devices(void); extern void __init u8500_init_devices(void); extern void __init ux500_init_irq(void); + +extern void __init u5500_sdi_init(void); + +extern void __init db5500_dma_init(void); + /* We re-use nomadik_timer for this platform */ extern void nmdk_timer_init(void); +struct amba_device; extern void __init amba_add_devices(struct amba_device *devs[], int num); struct sys_timer; diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h index 0271ca0..9a6614c 100644 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ b/arch/arm/mach-ux500/include/mach/uncompress.h @@ -19,38 +19,43 @@ #define __ASM_ARCH_UNCOMPRESS_H #include <asm/setup.h> +#include <asm/mach-types.h> #include <linux/io.h> +#include <linux/amba/serial.h> #include <mach/hardware.h> -#define U8500_UART_DR 0x80007000 -#define U8500_UART_LCRH 0x8000702c -#define U8500_UART_CR 0x80007030 -#define U8500_UART_FR 0x80007018 +static u32 ux500_uart_base; static void putc(const char c) { /* Do nothing if the UART is not enabled. */ - if (!(__raw_readb(U8500_UART_CR) & 0x1)) + if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1)) return; if (c == '\n') putc('\r'); - while (__raw_readb(U8500_UART_FR) & (1 << 5)) + while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 5)) barrier(); - __raw_writeb(c, U8500_UART_DR); + __raw_writeb(c, ux500_uart_base + UART01x_DR); } static void flush(void) { - if (!(__raw_readb(U8500_UART_CR) & 0x1)) + if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1)) return; - while (__raw_readb(U8500_UART_FR) & (1 << 3)) + while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 3)) barrier(); } static inline void arch_decomp_setup(void) { + if (machine_is_u8500()) + ux500_uart_base = U8500_UART2_BASE; + else if (machine_is_u5500()) + ux500_uart_base = U5500_UART0_BASE; + else /* not much can be done to help here */ + ux500_uart_base = U8500_UART2_BASE; } #define arch_decomp_wdog() /* nothing to do here */ diff --git a/arch/arm/mach-ux500/mbox.c b/arch/arm/mach-ux500/mbox-db5500.c index 6343538..cbf1571 100644 --- a/arch/arm/mach-ux500/mbox.c +++ b/arch/arm/mach-ux500/mbox-db5500.c @@ -38,7 +38,7 @@ #include <linux/debugfs.h> #include <linux/seq_file.h> #include <linux/completion.h> -#include <mach/mbox.h> +#include <mach/mbox-db5500.h> #define MBOX_NAME "mbox" diff --git a/arch/arm/mach-ux500/modem_irq.c b/arch/arm/mach-ux500/modem-irq-db5500.c index 3187f88..3187f88 100644 --- a/arch/arm/mach-ux500/modem_irq.c +++ b/arch/arm/mach-ux500/modem-irq-db5500.c diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 2115a0c..d77e76c 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -25,7 +25,7 @@ * control for which core is the next to come out of the secondary * boot "holding pen" */ -volatile int __cpuinitdata pen_release = -1; +volatile int pen_release = -1; /* * Write pen_release in a way that is guaranteed to be visible to all diff --git a/arch/arm/mach-ux500/prcmu.c b/arch/arm/mach-ux500/prcmu.c index 293274d..c522d26 100644 --- a/arch/arm/mach-ux500/prcmu.c +++ b/arch/arm/mach-ux500/prcmu.c @@ -1,10 +1,14 @@ /* - * Copyright (C) ST Ericsson SA 2010 + * Copyright (C) STMicroelectronics 2009 + * Copyright (C) ST-Ericsson SA 2010 * * License Terms: GNU General Public License v2 + * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> + * Author: Sundar Iyer <sundar.iyer@stericsson.com> * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> * - * U8500 PRCMU driver. + * U8500 PRCM Unit interface driver + * */ #include <linux/kernel.h> #include <linux/module.h> @@ -19,11 +23,26 @@ #include <mach/hardware.h> #include <mach/prcmu-regs.h> +#include <mach/prcmu-defs.h> + +/* Global var to runtime determine TCDM base for v2 or v1 */ +static __iomem void *tcdm_base; + +#define _MBOX_HEADER (tcdm_base + 0xFE8) +#define MBOX_HEADER_REQ_MB0 (_MBOX_HEADER + 0x0) + +#define REQ_MB1 (tcdm_base + 0xFD0) +#define REQ_MB5 (tcdm_base + 0xE44) -#define PRCMU_TCDM_BASE __io_address(U8500_PRCMU_TCDM_BASE) +#define REQ_MB1_ARMOPP (REQ_MB1 + 0x0) +#define REQ_MB1_APEOPP (REQ_MB1 + 0x1) +#define REQ_MB1_BOOSTOPP (REQ_MB1 + 0x2) -#define REQ_MB5 (PRCMU_TCDM_BASE + 0xE44) -#define ACK_MB5 (PRCMU_TCDM_BASE + 0xDF4) +#define ACK_MB1 (tcdm_base + 0xE04) +#define ACK_MB5 (tcdm_base + 0xDF4) + +#define ACK_MB1_CURR_ARMOPP (ACK_MB1 + 0x0) +#define ACK_MB1_CURR_APEOPP (ACK_MB1 + 0x1) #define REQ_MB5_I2C_SLAVE_OP (REQ_MB5) #define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1) @@ -33,10 +52,33 @@ #define ACK_MB5_I2C_STATUS (ACK_MB5 + 1) #define ACK_MB5_I2C_VAL (ACK_MB5 + 3) -#define I2C_WRITE(slave) ((slave) << 1) -#define I2C_READ(slave) (((slave) << 1) | BIT(0)) +#define PRCM_AVS_VARM_MAX_OPP (tcdm_base + 0x2E4) +#define PRCM_AVS_ISMODEENABLE 7 +#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) + +#define I2C_WRITE(slave) \ + (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) +#define I2C_READ(slave) \ + (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0) | BIT(0)) #define I2C_STOP_EN BIT(3) +enum mb1_h { + MB1H_ARM_OPP = 1, + MB1H_APE_OPP, + MB1H_ARM_APE_OPP, +}; + +static struct { + struct mutex lock; + struct completion work; + struct { + u8 arm_opp; + u8 ape_opp; + u8 arm_status; + u8 ape_status; + } ack; +} mb1_transfer; + enum ack_mb5_status { I2C_WR_OK = 0x01, I2C_RD_OK = 0x02, @@ -145,6 +187,104 @@ unlock_and_return: } EXPORT_SYMBOL(prcmu_abb_write); +static int set_ape_cpu_opps(u8 header, enum prcmu_ape_opp ape_opp, + enum prcmu_cpu_opp cpu_opp) +{ + bool do_ape; + bool do_arm; + int err = 0; + + do_ape = ((header == MB1H_APE_OPP) || (header == MB1H_ARM_APE_OPP)); + do_arm = ((header == MB1H_ARM_OPP) || (header == MB1H_ARM_APE_OPP)); + + mutex_lock(&mb1_transfer.lock); + + while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) + cpu_relax(); + + writeb(0, MBOX_HEADER_REQ_MB0); + writeb(cpu_opp, REQ_MB1_ARMOPP); + writeb(ape_opp, REQ_MB1_APEOPP); + writeb(0, REQ_MB1_BOOSTOPP); + writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); + wait_for_completion(&mb1_transfer.work); + if ((do_ape) && (mb1_transfer.ack.ape_status != 0)) + err = -EIO; + if ((do_arm) && (mb1_transfer.ack.arm_status != 0)) + err = -EIO; + + mutex_unlock(&mb1_transfer.lock); + + return err; +} + +/** + * prcmu_set_ape_opp() - Set the OPP of the APE. + * @opp: The OPP to set. + * + * This function sets the OPP of the APE. + */ +int prcmu_set_ape_opp(enum prcmu_ape_opp opp) +{ + return set_ape_cpu_opps(MB1H_APE_OPP, opp, APE_OPP_NO_CHANGE); +} +EXPORT_SYMBOL(prcmu_set_ape_opp); + +/** + * prcmu_set_cpu_opp() - Set the OPP of the CPU. + * @opp: The OPP to set. + * + * This function sets the OPP of the CPU. + */ +int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp) +{ + return set_ape_cpu_opps(MB1H_ARM_OPP, CPU_OPP_NO_CHANGE, opp); +} +EXPORT_SYMBOL(prcmu_set_cpu_opp); + +/** + * prcmu_set_ape_cpu_opps() - Set the OPPs of the APE and the CPU. + * @ape_opp: The APE OPP to set. + * @cpu_opp: The CPU OPP to set. + * + * This function sets the OPPs of the APE and the CPU. + */ +int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp, + enum prcmu_cpu_opp cpu_opp) +{ + return set_ape_cpu_opps(MB1H_ARM_APE_OPP, ape_opp, cpu_opp); +} +EXPORT_SYMBOL(prcmu_set_ape_cpu_opps); + +/** + * prcmu_get_ape_opp() - Get the OPP of the APE. + * + * This function gets the OPP of the APE. + */ +enum prcmu_ape_opp prcmu_get_ape_opp(void) +{ + return readb(ACK_MB1_CURR_APEOPP); +} +EXPORT_SYMBOL(prcmu_get_ape_opp); + +/** + * prcmu_get_cpu_opp() - Get the OPP of the CPU. + * + * This function gets the OPP of the CPU. The OPP is specified in %%. + * PRCMU_OPP_EXT is a special OPP value, not specified in %%. + */ +int prcmu_get_cpu_opp(void) +{ + return readb(ACK_MB1_CURR_ARMOPP); +} +EXPORT_SYMBOL(prcmu_get_cpu_opp); + +bool prcmu_has_arm_maxopp(void) +{ + return (readb(PRCM_AVS_VARM_MAX_OPP) & PRCM_AVS_ISMODEENABLE_MASK) + == PRCM_AVS_ISMODEENABLE_MASK; +} + static void read_mailbox_0(void) { writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR); @@ -152,6 +292,9 @@ static void read_mailbox_0(void) static void read_mailbox_1(void) { + mb1_transfer.ack.arm_opp = readb(ACK_MB1_CURR_ARMOPP); + mb1_transfer.ack.ape_opp = readb(ACK_MB1_CURR_APEOPP); + complete(&mb1_transfer.work); writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR); } @@ -217,15 +360,35 @@ static irqreturn_t prcmu_irq_handler(int irq, void *data) return IRQ_HANDLED; } +void __init prcmu_early_init(void) +{ + if (cpu_is_u8500v11() || cpu_is_u8500ed()) { + tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE_V1); + } else if (cpu_is_u8500v2()) { + tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE); + } else { + pr_err("prcmu: Unsupported chip version\n"); + BUG(); + } +} + static int __init prcmu_init(void) { + if (cpu_is_u8500ed()) { + pr_err("prcmu: Unsupported chip version\n"); + return 0; + } + + mutex_init(&mb1_transfer.lock); + init_completion(&mb1_transfer.work); mutex_init(&mb5_transfer.lock); init_completion(&mb5_transfer.work); /* Clean up the mailbox interrupts after pre-kernel code. */ writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR); - return request_irq(IRQ_PRCMU, prcmu_irq_handler, 0, "prcmu", NULL); + return request_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, 0, + "prcmu", NULL); } arch_initcall(prcmu_init); diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 8493ed0..49db8b3 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -382,6 +382,12 @@ config CPU_FEROCEON_OLD_ID for which the CPU ID is equal to the ARM926 ID. Relevant for Feroceon-1850 and early Feroceon-2850. +# Marvell PJ4 +config CPU_PJ4 + bool + select CPU_V7 + select ARM_THUMBEE + # ARMv6 config CPU_V6 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE @@ -824,7 +830,7 @@ config CACHE_PL310 config CACHE_TAUROS2 bool "Enable the Tauros2 L2 cache controller" - depends on (ARCH_DOVE || ARCH_MMP) + depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) default y select OUTER_CACHE help diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 64e3a64..389f217 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -21,10 +21,6 @@ config ARCH_MX2 config ARCH_MX25 bool "MX25-based" - select CPU_ARM926T - select ARCH_MXC_IOMUX_V3 - select HAVE_FB_IMX - select ARCH_MXC_AUDMUX_V2 help This enables support for systems based on the Freescale i.MX25 family @@ -51,7 +47,6 @@ endchoice source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-mx3/Kconfig" -source "arch/arm/mach-mx25/Kconfig" source "arch/arm/mach-mxc91231/Kconfig" source "arch/arm/mach-mx5/Kconfig" @@ -68,12 +63,10 @@ config MXC_IRQ_PRIOR Say N here, unless you have a specialized requirement. config MXC_TZIC - bool "Enable TrustZone Interrupt Controller" - depends on ARCH_MX51 - help - This will be automatically selected for all processors - containing this interrupt controller. - Say N here only if you are really sure. + bool + +config MXC_AVIC + bool config MXC_PWM tristate "Enable PWM driver" diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 3726709..5fd20e9 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -3,10 +3,11 @@ # # Common support -obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o +obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o -# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) +# MX51 uses the TZIC interrupt controller, older platforms use AVIC obj-$(CONFIG_MXC_TZIC) += tzic.o +obj-$(CONFIG_MXC_AVIC) += avic.o obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 0be1ac7..175e364 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -209,7 +209,7 @@ static int mxc_audmux_v2_init(void) audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); } #endif -#if defined(CONFIG_ARCH_MX25) +#if defined(CONFIG_SOC_IMX25) if (cpu_is_mx25()) { audmux_clk = clk_get(NULL, "audmux"); if (IS_ERR(audmux_clk)) { @@ -220,7 +220,7 @@ static int mxc_audmux_v2_init(void) } audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); } -#endif +#endif /* if defined(CONFIG_SOC_IMX25) */ audmux_debugfs_init(); return 0; diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/avic.c index 7331f2a..9a4e8a2 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/avic.c @@ -24,6 +24,8 @@ #include <asm/mach/irq.h> #include <mach/hardware.h> +#include "irq-common.h" + #define AVIC_INTCNTL 0x00 /* int control reg */ #define AVIC_NIMASK 0x04 /* int mask reg */ #define AVIC_INTENNUM 0x08 /* int enable number reg */ @@ -46,9 +48,9 @@ void __iomem *avic_base; -int imx_irq_set_priority(unsigned char irq, unsigned char prio) -{ #ifdef CONFIG_MXC_IRQ_PRIOR +static int avic_irq_set_priority(unsigned char irq, unsigned char prio) +{ unsigned int temp; unsigned int mask = 0x0F << irq % 8 * 4; @@ -62,14 +64,11 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio) __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); return 0; -#else - return -ENOSYS; -#endif } -EXPORT_SYMBOL(imx_irq_set_priority); +#endif #ifdef CONFIG_FIQ -int mxc_set_irq_fiq(unsigned int irq, unsigned int type) +static int avic_set_irq_fiq(unsigned int irq, unsigned int type) { unsigned int irqt; @@ -87,7 +86,6 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type) return 0; } -EXPORT_SYMBOL(mxc_set_irq_fiq); #endif /* CONFIG_FIQ */ /* Disable interrupt number "irq" in the AVIC */ @@ -102,10 +100,18 @@ static void mxc_unmask_irq(unsigned int irq) __raw_writel(irq, avic_base + AVIC_INTENNUM); } -static struct irq_chip mxc_avic_chip = { - .ack = mxc_mask_irq, - .mask = mxc_mask_irq, - .unmask = mxc_unmask_irq, +static struct mxc_irq_chip mxc_avic_chip = { + .base = { + .ack = mxc_mask_irq, + .mask = mxc_mask_irq, + .unmask = mxc_unmask_irq, + }, +#ifdef CONFIG_MXC_IRQ_PRIOR + .set_priority = avic_irq_set_priority, +#endif +#ifdef CONFIG_FIQ + .set_irq_fiq = avic_set_irq_fiq, +#endif }; /* @@ -133,7 +139,7 @@ void __init mxc_init_irq(void __iomem *irqbase) __raw_writel(0, avic_base + AVIC_INTTYPEH); __raw_writel(0, avic_base + AVIC_INTTYPEL); for (i = 0; i < MXC_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxc_avic_chip); + set_irq_chip(i, &mxc_avic_chip.base); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c index 039538e..ce81481 100644 --- a/arch/arm/plat-mxc/cpufreq.c +++ b/arch/arm/plat-mxc/cpufreq.c @@ -144,7 +144,6 @@ static int __init mxc_cpufreq_init(struct cpufreq_policy *policy) imx_freq_table[i].frequency = CPUFREQ_TABLE_END; policy->cur = clk_get_rate(cpu_clk) / 1000; - policy->governor = CPUFREQ_DEFAULT_GOVERNOR; policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min; policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max; diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index 735776d..e9bcefe 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c @@ -17,6 +17,7 @@ */ #include <linux/kernel.h> +#include <linux/slab.h> #include <linux/init.h> #include <linux/err.h> #include <linux/platform_device.h> @@ -36,9 +37,10 @@ int __init mxc_register_device(struct platform_device *pdev, void *data) return ret; } -struct platform_device *__init imx_add_platform_device(const char *name, int id, +struct platform_device *__init imx_add_platform_device_dmamask( + const char *name, int id, const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data) + const void *data, size_t size_data, u64 dmamask) { int ret = -ENOMEM; struct platform_device *pdev; @@ -47,6 +49,23 @@ struct platform_device *__init imx_add_platform_device(const char *name, int id, if (!pdev) goto err; + if (dmamask) { + /* + * This memory isn't freed when the device is put, + * I don't have a nice idea for that though. Conceptually + * dma_mask in struct device should not be a pointer. + * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 + */ + pdev->dev.dma_mask = + kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); + if (!pdev->dev.dma_mask) + /* ret is still -ENOMEM; */ + goto err; + + *pdev->dev.dma_mask = dmamask; + pdev->dev.coherent_dma_mask = dmamask; + } + if (res) { ret = platform_device_add_resources(pdev, res, num_resources); if (ret) diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 9aa6f3e..2537166 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -1,29 +1,73 @@ -config IMX_HAVE_PLATFORM_ESDHC - bool - config IMX_HAVE_PLATFORM_FEC bool - default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51 + default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 config IMX_HAVE_PLATFORM_FLEXCAN select HAVE_CAN_FLEXCAN if CAN bool +config IMX_HAVE_PLATFORM_FSL_USB2_UDC + bool + config IMX_HAVE_PLATFORM_GPIO_KEYS bool - default y if ARCH_MX51 + default y if SOC_IMX51 + +config IMX_HAVE_PLATFORM_IMX21_HCD + bool +config IMX_HAVE_PLATFORM_IMX2_WDT + bool + +config IMX_HAVE_PLATFORM_IMXDI_RTC + bool + +config IMX_HAVE_PLATFORM_IMX_FB + bool + select HAVE_FB_IMX + config IMX_HAVE_PLATFORM_IMX_I2C bool +config IMX_HAVE_PLATFORM_IMX_KEYPAD + bool + config IMX_HAVE_PLATFORM_IMX_SSI bool config IMX_HAVE_PLATFORM_IMX_UART bool +config IMX_HAVE_PLATFORM_IMX_UDC + bool + +config IMX_HAVE_PLATFORM_MX1_CAMERA + bool + +config IMX_HAVE_PLATFORM_MX2_CAMERA + bool + +config IMX_HAVE_PLATFORM_MXC_EHCI + bool + +config IMX_HAVE_PLATFORM_MXC_MMC + bool + config IMX_HAVE_PLATFORM_MXC_NAND bool +config IMX_HAVE_PLATFORM_MXC_PWM + bool + +config IMX_HAVE_PLATFORM_MXC_RNGA + bool + select ARCH_HAS_RNGA + +config IMX_HAVE_PLATFORM_MXC_W1 + bool + +config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + bool + config IMX_HAVE_PLATFORM_SPI_IMX bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 45aefeb..75cd2ec 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -1,10 +1,24 @@ -obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o obj-y += platform-imx-dma.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c deleted file mode 100644 index 2605bfa..0000000 --- a/arch/arm/plat-mxc/devices/platform-esdhc.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include <mach/hardware.h> -#include <mach/devices-common.h> -#include <mach/esdhc.h> - -#define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \ - { \ - .id = _id, \ - .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ - .irq = soc ## _INT_ESDHC ## hwid, \ - } - -#define imx_esdhc_imx_data_entry(soc, id, hwid) \ - [id] = imx_esdhc_imx_data_entry_single(soc, id, hwid) - -#ifdef CONFIG_ARCH_MX25 -const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = { -#define imx25_esdhc_data_entry(_id, _hwid) \ - imx_esdhc_imx_data_entry(MX25, _id, _hwid) - imx25_esdhc_data_entry(0, 1), - imx25_esdhc_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_ARCH_MX25 */ - -#ifdef CONFIG_ARCH_MX35 -const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = { -#define imx35_esdhc_data_entry(_id, _hwid) \ - imx_esdhc_imx_data_entry(MX35, _id, _hwid) - imx35_esdhc_data_entry(0, 1), - imx35_esdhc_data_entry(1, 2), - imx35_esdhc_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_ARCH_MX35 */ - -#ifdef CONFIG_ARCH_MX51 -const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = { -#define imx51_esdhc_data_entry(_id, _hwid) \ - imx_esdhc_imx_data_entry(MX51, _id, _hwid) - imx51_esdhc_data_entry(0, 1), - imx51_esdhc_data_entry(1, 2), - imx51_esdhc_data_entry(2, 3), - imx51_esdhc_data_entry(3, 4), -}; -#endif /* ifdef CONFIG_ARCH_MX51 */ - -struct platform_device *__init imx_add_esdhc( - const struct imx_esdhc_imx_data *data, - const struct esdhc_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("sdhci-esdhc-imx", data->id, res, - ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index 11d087f..269ec78 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c @@ -16,22 +16,22 @@ .irq = soc ## _INT_FEC, \ } -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_fec_data imx25_fec_data __initconst = imx_fec_data_entry_single(MX25); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_fec_data imx27_fec_data __initconst = imx_fec_data_entry_single(MX27); #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_fec_data imx35_fec_data __initconst = imx_fec_data_entry_single(MX35); #endif -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_fec_data imx51_fec_data __initconst = imx_fec_data_entry_single(MX51); #endif diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c index 5e97a01..4e8497a 100644 --- a/arch/arm/plat-mxc/devices/platform-flexcan.c +++ b/arch/arm/plat-mxc/devices/platform-flexcan.c @@ -5,26 +5,54 @@ * the terms of the GNU General Public License version 2 as published by the * Free Software Foundation. */ - +#include <mach/hardware.h> #include <mach/devices-common.h> -struct platform_device *__init imx_add_flexcan(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, +#define imx_flexcan_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_CAN ## _hwid, \ + } + +#define imx_flexcan_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX25 +const struct imx_flexcan_data imx25_flexcan_data[] __initconst = { +#define imx25_flexcan_data_entry(_id, _hwid) \ + imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_flexcan_data_entry(0, 1), + imx25_flexcan_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_flexcan_data imx35_flexcan_data[] __initconst = { +#define imx35_flexcan_data_entry(_id, _hwid) \ + imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K) + imx35_flexcan_data_entry(0, 1), + imx35_flexcan_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_flexcan( + const struct imx_flexcan_data *data, const struct flexcan_platform_data *pdata) { struct resource res[] = { { - .start = iobase, - .end = iobase + iosize - 1, + .start = data->iobase, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = irq, - .end = irq, + .start = data->irq, + .end = data->irq, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); + return imx_add_platform_device("flexcan", data->id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); } diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c new file mode 100644 index 0000000..59c33f6 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_fsl_usb2_udc_data_entry_single(soc) \ + { \ + .iobase = soc ## _USB_OTG_BASE_ADDR, \ + .irq = soc ## _INT_USB_OTG, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX25); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX35); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_fsl_usb2_udc( + const struct imx_fsl_usb2_udc_data *data, + const struct fsl_usb2_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("fsl-usb2-udc", -1, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index 3a705c7..33530d2 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c @@ -31,25 +31,25 @@ struct imx_imx_sdma_data { }, \ } -#ifdef CONFIG_ARCH_MX25 -const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = +#ifdef CONFIG_SOC_IMX25 +struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0); -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0); -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 -const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = +#ifdef CONFIG_SOC_IMX51 +struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0); -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ static struct platform_device __init __maybe_unused *imx_add_imx_sdma( const struct imx_imx_sdma_data *data) @@ -76,6 +76,83 @@ static struct platform_device __init __maybe_unused *imx_add_imx_dma(void) return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0); } +#ifdef CONFIG_ARCH_MX25 +static struct sdma_script_start_addrs addr_imx25_to1 = { + .ap_2_ap_addr = 729, + .uart_2_mcu_addr = 904, + .per_2_app_addr = 1255, + .mcu_2_app_addr = 834, + .uartsh_2_mcu_addr = 1120, + .per_2_shp_addr = 1329, + .mcu_2_shp_addr = 1048, + .ata_2_mcu_addr = 1560, + .mcu_2_ata_addr = 1479, + .app_2_per_addr = 1189, + .app_2_mcu_addr = 770, + .shp_2_per_addr = 1407, + .shp_2_mcu_addr = 979, +}; +#endif + +#ifdef CONFIG_ARCH_MX31 +static struct sdma_script_start_addrs addr_imx31_to1 = { + .per_2_per_addr = 1677, +}; + +static struct sdma_script_start_addrs addr_imx31_to2 = { + .ap_2_ap_addr = 423, + .ap_2_bp_addr = 829, + .bp_2_ap_addr = 1029, +}; +#endif + +#ifdef CONFIG_ARCH_MX35 +static struct sdma_script_start_addrs addr_imx35_to1 = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .uartsh_2_mcu_addr = 1183, + .per_2_shp_addr = 1033, + .mcu_2_shp_addr = 961, + .ata_2_mcu_addr = 1333, + .mcu_2_ata_addr = 1252, + .app_2_mcu_addr = 683, + .shp_2_per_addr = 1111, + .shp_2_mcu_addr = 892, +}; + +static struct sdma_script_start_addrs addr_imx35_to2 = { + .ap_2_ap_addr = 729, + .uart_2_mcu_addr = 904, + .per_2_app_addr = 1597, + .mcu_2_app_addr = 834, + .uartsh_2_mcu_addr = 1270, + .per_2_shp_addr = 1120, + .mcu_2_shp_addr = 1048, + .ata_2_mcu_addr = 1429, + .mcu_2_ata_addr = 1339, + .app_2_per_addr = 1531, + .app_2_mcu_addr = 770, + .shp_2_per_addr = 1198, + .shp_2_mcu_addr = 979, +}; +#endif + +#ifdef CONFIG_SOC_IMX51 +static struct sdma_script_start_addrs addr_imx51_to1 = { + .ap_2_ap_addr = 642, + .uart_2_mcu_addr = 817, + .mcu_2_app_addr = 747, + .mcu_2_shp_addr = 961, + .ata_2_mcu_addr = 1473, + .mcu_2_ata_addr = 1392, + .app_2_per_addr = 1033, + .app_2_mcu_addr = 683, + .shp_2_per_addr = 1251, + .shp_2_mcu_addr = 892, +}; +#endif + static int __init imxXX_add_imx_dma(void) { struct platform_device *ret; @@ -86,30 +163,42 @@ static int __init imxXX_add_imx_dma(void) else #endif -#if defined(CONFIG_ARCH_MX25) - if (cpu_is_mx25()) +#if defined(CONFIG_SOC_IMX25) + if (cpu_is_mx25()) { + imx25_imx_sdma_data.pdata.script_addrs = &addr_imx25_to1; ret = imx_add_imx_sdma(&imx25_imx_sdma_data); - else + } else #endif -#if defined(CONFIG_ARCH_MX31) +#if defined(CONFIG_SOC_IMX31) if (cpu_is_mx31()) { - imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4; + int to_version = mx31_revision() >> 4; + imx31_imx_sdma_data.pdata.to_version = to_version; + if (to_version == 1) + imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to1; + else + imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to2; ret = imx_add_imx_sdma(&imx31_imx_sdma_data); } else #endif -#if defined(CONFIG_ARCH_MX35) +#if defined(CONFIG_SOC_IMX35) if (cpu_is_mx35()) { - imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4; + int to_version = mx35_revision() >> 4; + imx35_imx_sdma_data.pdata.to_version = to_version; + if (to_version == 1) + imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to1; + else + imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to2; ret = imx_add_imx_sdma(&imx35_imx_sdma_data); } else #endif #if defined(CONFIG_ARCH_MX51) - if (cpu_is_mx51()) + if (cpu_is_mx51()) { + imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1; ret = imx_add_imx_sdma(&imx51_imx_sdma_data); - else + } else #endif ret = ERR_PTR(-ENODEV); diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c new file mode 100644 index 0000000..6100a7d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_fb_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _LCDC_BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_LCDC, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_fb_data imx21_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX21, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx_fb_data imx25_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX25, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_fb_data imx27_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX27, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_imx_fb( + const struct imx_imx_fb_data *data, + const struct imx_fb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("imx-fb", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index 6795884..72ba880 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -30,7 +30,7 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { #define imx25_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K) @@ -38,7 +38,7 @@ const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { imx25_imx_i2c_data_entry(1, 2), imx25_imx_i2c_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { @@ -49,7 +49,7 @@ const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { #define imx31_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K) @@ -57,9 +57,9 @@ const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { imx31_imx_i2c_data_entry(1, 2), imx31_imx_i2c_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { #define imx35_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) @@ -67,16 +67,16 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { imx35_imx_i2c_data_entry(1, 2), imx35_imx_i2c_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { #define imx51_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K) imx51_imx_i2c_data_entry(0, 1), imx51_imx_i2c_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ struct platform_device *__init imx_add_imx_i2c( const struct imx_imx_i2c_data *data, diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c new file mode 100644 index 0000000..40238f0 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_keypad_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _KPP_BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_KPP, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX21, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX25, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX27, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX31, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX35, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_imx_keypad( + const struct imx_imx_keypad_data *data, + const struct matrix_keymap_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-keypad", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c index 38a7a0b..2569c8d 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c @@ -30,14 +30,14 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { #define imx25_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) imx25_imx_ssi_data_entry(0, 1), imx25_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { @@ -48,32 +48,33 @@ const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { #define imx31_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) imx31_imx_ssi_data_entry(0, 1), imx31_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { #define imx35_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) imx35_imx_ssi_data_entry(0, 1), imx35_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { #define imx51_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) imx51_imx_ssi_data_entry(0, 1), imx51_imx_ssi_data_entry(1, 2), + imx51_imx_ssi_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ struct platform_device *__init imx_add_imx_ssi( const struct imx_imx_ssi_data *data, diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index 2039640..3c854c2 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -47,7 +47,7 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { }; #endif -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { #define imx25_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) @@ -57,7 +57,7 @@ const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { imx25_imx_uart_data_entry(3, 4), imx25_imx_uart_data_entry(4, 5), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { @@ -72,7 +72,7 @@ const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { #define imx31_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) @@ -82,9 +82,9 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { imx31_imx_uart_data_entry(3, 4), imx31_imx_uart_data_entry(4, 5), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { #define imx35_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) @@ -92,9 +92,21 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { imx35_imx_uart_data_entry(1, 2), imx35_imx_uart_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX50 +const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = { +#define imx50_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K) + imx50_imx_uart_data_entry(0, 1), + imx50_imx_uart_data_entry(1, 2), + imx50_imx_uart_data_entry(2, 3), + imx50_imx_uart_data_entry(3, 4), + imx50_imx_uart_data_entry(4, 5), +}; +#endif /* ifdef CONFIG_SOC_IMX50 */ + +#ifdef CONFIG_SOC_IMX51 const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { #define imx51_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K) @@ -102,7 +114,17 @@ const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { imx51_imx_uart_data_entry(1, 2), imx51_imx_uart_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ + +#ifdef CONFIG_SOC_IMX53 +const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = { +#define imx53_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX53, _id, _hwid, SZ_4K) + imx53_imx_uart_data_entry(0, 1), + imx53_imx_uart_data_entry(1, 2), + imx53_imx_uart_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX53 */ struct platform_device *__init imx_add_imx_uart_3irq( const struct imx_imx_uart_3irq_data *data, diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c new file mode 100644 index 0000000..e0aec61 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _WDOG ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + } +#define imx_imx2_wdt_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX31, 0, , SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = { +#define imx51_imx2_wdt_data_entry(_id, _hwid) \ + imx_imx2_wdt_data_entry(MX51, _id, _hwid, SZ_16K) + imx51_imx2_wdt_data_entry(0, 1), + imx51_imx2_wdt_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + +struct platform_device *__init imx_add_imx2_wdt( + const struct imx_imx2_wdt_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, + }; + return imx_add_platform_device("imx2-wdt", data->id, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx21-hcd.c b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c new file mode 100644 index 0000000..5770a42 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx21_hcd_data_entry_single(soc) \ + { \ + .iobase = soc ## _USBOTG_BASE_ADDR, \ + .irq = soc ## _INT_USBHOST, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst = + imx_imx21_hcd_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +struct platform_device *__init imx_add_imx21_hcd( + const struct imx_imx21_hcd_data *data, + const struct mx21_usbh_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("imx21-hcd", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx_udc.c b/arch/arm/plat-mxc/devices/platform-imx_udc.c new file mode 100644 index 0000000..6fd675d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_udc.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_udc_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _USBD_BASE_ADDR, \ + .iosize = _size, \ + .irq0 = soc ## _INT_USBD0, \ + .irq1 = soc ## _INT_USBD1, \ + .irq2 = soc ## _INT_USBD2, \ + .irq3 = soc ## _INT_USBD3, \ + .irq4 = soc ## _INT_USBD4, \ + .irq5 = soc ## _INT_USBD5, \ + .irq6 = soc ## _INT_USBD6, \ + } + +#define imx_imx_udc_data_entry(soc, _size) \ + [_id] = imx_imx_udc_data_entry_single(soc, _size) + +#ifdef CONFIG_SOC_IMX1 +const struct imx_imx_udc_data imx1_imx_udc_data __initconst = + imx_imx_udc_data_entry_single(MX1, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX1 */ + +struct platform_device *__init imx_add_imx_udc( + const struct imx_imx_udc_data *data, + const struct imxusb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq0, + .end = data->irq0, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq1, + .end = data->irq1, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq2, + .end = data->irq2, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq3, + .end = data->irq3, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq4, + .end = data->irq4, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq5, + .end = data->irq5, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq6, + .end = data->irq6, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx_udc", 0, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c new file mode 100644 index 0000000..10653cc --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imxdi_rtc_data_entry_single(soc) \ + { \ + .iobase = soc ## _DRYICE_BASE_ADDR, \ + .irq = soc ## _INT_DRYICE, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst = + imx_imxdi_rtc_data_entry_single(MX25); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +struct platform_device *__init imx_add_imxdi_rtc( + const struct imx_imxdi_rtc_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imxdi_rtc", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-mx1-camera.c b/arch/arm/plat-mxc/devices/platform-mx1-camera.c new file mode 100644 index 0000000..edcc581 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx1-camera.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mx1_camera_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _CSI ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_CSI, \ + } + +#ifdef CONFIG_SOC_IMX1 +const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst = + imx_mx1_camera_data_entry_single(MX1, 10); +#endif /* ifdef CONFIG_SOC_IMX1 */ + +struct platform_device *__init imx_add_mx1_camera( + const struct imx_mx1_camera_data *data, + const struct mx1_camera_pdata *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mx1-camera", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/plat-mxc/devices/platform-mx2-camera.c new file mode 100644 index 0000000..b3f4828 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx2-camera.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mx2_camera_data_entry_single(soc) \ + { \ + .iobasecsi = soc ## _CSI_BASE_ADDR, \ + .iosizecsi = SZ_4K, \ + .irqcsi = soc ## _INT_CSI, \ + } +#define imx_mx2_camera_data_entry_single_emma(soc) \ + { \ + .iobasecsi = soc ## _CSI_BASE_ADDR, \ + .iosizecsi = SZ_32, \ + .irqcsi = soc ## _INT_CSI, \ + .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \ + .iosizeemmaprp = SZ_32, \ + .irqemmaprp = soc ## _INT_EMMAPRP, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst = + imx_mx2_camera_data_entry_single(MX25); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst = + imx_mx2_camera_data_entry_single_emma(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_mx2_camera( + const struct imx_mx2_camera_data *data, + const struct mx2_camera_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobasecsi, + .end = data->iobasecsi + data->iosizecsi - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irqcsi, + .end = data->irqcsi, + .flags = IORESOURCE_IRQ, + }, { + .start = data->iobaseemmaprp, + .end = data->iobaseemmaprp + data->iosizeemmaprp - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irqemmaprp, + .end = data->irqemmaprp, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mx2-camera", 0, + res, data->iobaseemmaprp ? 4 : 2, + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c new file mode 100644 index 0000000..cc488f4 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_ehci_data_entry_single(soc, _id, hs) \ + { \ + .id = _id, \ + .iobase = soc ## _USB_ ## hs ## _BASE_ADDR, \ + .irq = soc ## _INT_USB_ ## hs, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX25, 0, OTG); +const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst = + imx_mxc_ehci_data_entry_single(MX25, 1, HS); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX27, 0, OTG); +const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX27, 1, HS1), + imx_mxc_ehci_data_entry_single(MX27, 2, HS2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX31, 0, OTG); +const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX31, 1, HS1), + imx_mxc_ehci_data_entry_single(MX31, 2, HS2), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX35, 0, OTG); +const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst = + imx_mxc_ehci_data_entry_single(MX35, 1, HS); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_mxc_ehci( + const struct imx_mxc_ehci_data *data, + const struct mxc_usbh_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mxc-ehci", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c new file mode 100644 index 0000000..90d762f --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_SDHC ## _hwid, \ + .dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \ + } +#define imx_mxc_mmc_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = { +#define imx21_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX21, _id, _hwid, SZ_4K) + imx21_mxc_mmc_data_entry(0, 1), + imx21_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = { +#define imx27_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX27, _id, _hwid, SZ_4K) + imx27_mxc_mmc_data_entry(0, 1), + imx27_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = { +#define imx31_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX31, _id, _hwid, SZ_16K) + imx31_mxc_mmc_data_entry(0, 1), + imx31_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + +struct platform_device *__init imx_add_mxc_mmc( + const struct imx_mxc_mmc_data *data, + const struct imxmmc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, { + .start = data->dmareq, + .end = data->dmareq, + .flags = IORESOURCE_DMA, + }, + }; + return imx_add_platform_device_dmamask("mxc-mmc", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c index 3fdcc32..1568f39 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -31,27 +31,27 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX21, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX25, SZ_8K); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX27, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX31, SZ_4K); #endif -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX35, SZ_8K); #endif -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst = imx_mxc_nandv3_data_entry_single(MX51, SZ_16K); #endif diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c new file mode 100644 index 0000000..3d8ebdb --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_PWM ## _hwid, \ + } +#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst = + imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = { +#define imx25_mxc_pwm_data_entry(_id, _hwid) \ + imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_mxc_pwm_data_entry(0, 1), + imx25_mxc_pwm_data_entry(1, 2), + imx25_mxc_pwm_data_entry(2, 3), + imx25_mxc_pwm_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst = + imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_mxc_pwm( + const struct imx_mxc_pwm_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_pwm", data->id, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rnga.c b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c new file mode 100644 index 0000000..b4b7612 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +struct imx_mxc_rnga_data { + resource_size_t iobase; +}; + +#define imx_mxc_rnga_data_entry_single(soc) \ + { \ + .iobase = soc ## _RNGA_BASE_ADDR, \ + } + +#ifdef CONFIG_SOC_IMX31 +static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst = + imx_mxc_rnga_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +static struct platform_device *__init imx_add_mxc_rnga( + const struct imx_mxc_rnga_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + }; + return imx_add_platform_device("mxc_rnga", -1, + res, ARRAY_SIZE(res), NULL, 0); +} + +static int __init imxXX_add_mxc_rnga(void) +{ + struct platform_device *ret; + +#if defined(CONFIG_SOC_IMX31) + if (cpu_is_mx31()) + ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data); + else +#endif /* if defined(CONFIG_SOC_IMX31) */ + ret = ERR_PTR(-ENODEV); + + if (IS_ERR(ret)) + return PTR_ERR(ret); + + return 0; +} +arch_initcall(imxXX_add_mxc_rnga); diff --git a/arch/arm/plat-mxc/devices/platform-mxc_w1.c b/arch/arm/plat-mxc/devices/platform-mxc_w1.c new file mode 100644 index 0000000..96fa5ea --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_w1.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_w1_data_entry_single(soc) \ + { \ + .iobase = soc ## _OWIRE_BASE_ADDR, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX35); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_mxc_w1( + const struct imx_mxc_w1_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return imx_add_platform_device("mxc_w1", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c new file mode 100644 index 0000000..b352564 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> +#include <mach/esdhc.h> + +#define imx_sdhci_esdhc_imx_data_entry_single(soc, _id, hwid) \ + { \ + .id = _id, \ + .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ + .irq = soc ## _INT_ESDHC ## hwid, \ + } + +#define imx_sdhci_esdhc_imx_data_entry(soc, id, hwid) \ + [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, id, hwid) + +#ifdef CONFIG_SOC_IMX25 +const struct imx_sdhci_esdhc_imx_data +imx25_sdhci_esdhc_imx_data[] __initconst = { +#define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX25, _id, _hwid) + imx25_sdhci_esdhc_imx_data_entry(0, 1), + imx25_sdhci_esdhc_imx_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_sdhci_esdhc_imx_data +imx35_sdhci_esdhc_imx_data[] __initconst = { +#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX35, _id, _hwid) + imx35_sdhci_esdhc_imx_data_entry(0, 1), + imx35_sdhci_esdhc_imx_data_entry(1, 2), + imx35_sdhci_esdhc_imx_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_SOC_IMX51 +const struct imx_sdhci_esdhc_imx_data +imx51_sdhci_esdhc_imx_data[] __initconst = { +#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX51, _id, _hwid) + imx51_sdhci_esdhc_imx_data_entry(0, 1), + imx51_sdhci_esdhc_imx_data_entry(1, 2), + imx51_sdhci_esdhc_imx_data_entry(2, 3), + imx51_sdhci_esdhc_imx_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_SOC_IMX51 */ + +struct platform_device *__init imx_add_sdhci_esdhc_imx( + const struct imx_sdhci_esdhc_imx_data *data, + const struct esdhc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("sdhci-esdhc-imx", data->id, res, + ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index 17f724c..8ea49ad 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -30,7 +30,7 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { }; #endif -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { #define imx25_cspi_data_entry(_id, _hwid) \ imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K) @@ -38,7 +38,7 @@ const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { imx25_cspi_data_entry(1, 2), imx25_cspi_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { @@ -50,7 +50,7 @@ const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { #define imx31_cspi_data_entry(_id, _hwid) \ imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) @@ -58,18 +58,18 @@ const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { imx31_cspi_data_entry(1, 2), imx31_cspi_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { #define imx35_cspi_data_entry(_id, _hwid) \ imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) imx35_cspi_data_entry(0, 1), imx35_cspi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 const struct imx_spi_imx_data imx51_cspi_data __initconst = imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K); @@ -79,7 +79,7 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = { imx51_ecspi_data_entry(0, 1), imx51_ecspi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX51 */ +#endif /* ifdef CONFIG_SOC_IMX51 */ struct platform_device *__init imx_add_spi_imx( const struct imx_spi_imx_data *data, diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 9915607..8772ce3 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -49,6 +49,7 @@ #define MXC_OTG_OFFSET 0 #define MXC_H1_OFFSET 0x200 +#define MXC_H2_OFFSET 0x400 /* USB_CTRL */ #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ @@ -61,6 +62,11 @@ #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ +/* USBH2CTRL */ +#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) +#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) +#define MXC_H2_UCTRL_H2PM_BIT (1 << 4) + #define MXC_USBCMD_OFFSET 0x140 /* USBCMD */ @@ -69,9 +75,9 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) { unsigned int v; -#if defined(CONFIG_ARCH_MX25) +#if defined(CONFIG_SOC_IMX25) if (cpu_is_mx25()) { - v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -108,14 +114,14 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return -EINVAL; } - writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } -#endif /* CONFIG_ARCH_MX25 */ +#endif /* if defined(CONFIG_SOC_IMX25) */ #if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) { - v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + + v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -153,13 +159,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return -EINVAL; } - writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + + writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } if (cpu_is_mx35()) { - v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -196,7 +202,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return -EINVAL; } - writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } @@ -206,7 +212,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) /* On i.MX27 we can use the i.MX31 USBCTRL bits, they * are identical */ - v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { case 0: /* OTG port */ @@ -241,12 +247,12 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) default: return -EINVAL; } - writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } #endif /* CONFIG_MACH_MX27 */ -#ifdef CONFIG_ARCH_MX51 +#ifdef CONFIG_SOC_IMX51 if (cpu_is_mx51()) { void __iomem *usb_base; void __iomem *usbotg_base; @@ -254,6 +260,10 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) int ret = 0; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); + if (!usb_base) { + printk(KERN_ERR "%s(): ioremap failed\n", __func__); + return -ENOMEM; + } switch (port) { case 0: /* OTG port */ @@ -262,6 +272,9 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) case 1: /* Host 1 port */ usbotg_base = usb_base + MXC_H1_OFFSET; break; + case 2: /* Host 2 port */ + usbotg_base = usb_base + MXC_H2_OFFSET; + break; default: printk(KERN_ERR"%s no such port %d\n", __func__, port); ret = -ENOENT; @@ -274,10 +287,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) if (flags & MXC_EHCI_INTERNAL_PHY) { v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */ - else - v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */ + if (flags & MXC_EHCI_POWER_PINS_ENABLED) { + /* OC/USBPWR is not used */ + v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; + } else { + /* OC/USBPWR is used */ + v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; + } __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); @@ -285,16 +301,23 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ else v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v |= MXC_OTG_UCTRL_OPM_BIT; + else + v &= ~MXC_OTG_UCTRL_OPM_BIT; __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); } break; case 1: /* Host 1 */ /*Host ULPI */ v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); - if (flags & MXC_EHCI_WAKEUP_ENABLED) - v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ - else - v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ + if (flags & MXC_EHCI_WAKEUP_ENABLED) { + /* HOST1 wakeup/ULPI intr enable */ + v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); + } else { + /* HOST1 wakeup/ULPI intr disable */ + v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); + } if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ @@ -315,6 +338,22 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); break; + case 2: /* Host 2 ULPI */ + v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); + if (flags & MXC_EHCI_WAKEUP_ENABLED) { + /* HOST1 wakeup/ULPI intr enable */ + v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); + } else { + /* HOST1 wakeup/ULPI intr disable */ + v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); + } + + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ + else + v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ + __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); + break; } error: diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 9c3e362..bc2c7bc 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) { u32 irq_stat; - struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); + struct mxc_gpio_port *port = get_irq_data(irq); irq_stat = __raw_readl(port->base + GPIO_ISR) & __raw_readl(port->base + GPIO_IMR); @@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) { int i; u32 irq_msk, irq_stat; - struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); + struct mxc_gpio_port *port = get_irq_data(irq); /* walk through all interrupt status registers */ for (i = 0; i < gpio_table_size; i++) { @@ -349,3 +349,113 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) return 0; } + +#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \ + { \ + .chip.label = "gpio-" #_id, \ + .irq = _irq, \ + .irq_high = _irq_high, \ + .base = soc ## _IO_ADDRESS( \ + soc ## _GPIO ## _hwid ## _BASE_ADDR), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \ + } + +#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \ + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0) +#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \ + DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0) + +#define DEFINE_REGISTER_FUNCTION(prefix) \ +int __init prefix ## _register_gpios(void) \ +{ \ + return mxc_gpio_init(prefix ## _gpio_ports, \ + ARRAY_SIZE(prefix ## _gpio_ports)); \ +} + +#if defined(CONFIG_SOC_IMX1) +static struct mxc_gpio_port imx1_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD), +}; + +DEFINE_REGISTER_FUNCTION(imx1) + +#endif /* if defined(CONFIG_SOC_IMX1) */ + +#if defined(CONFIG_SOC_IMX21) +static struct mxc_gpio_port imx21_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO), + DEFINE_IMX_GPIO_PORT(MX21, 1, 2), + DEFINE_IMX_GPIO_PORT(MX21, 2, 3), + DEFINE_IMX_GPIO_PORT(MX21, 3, 4), + DEFINE_IMX_GPIO_PORT(MX21, 4, 5), + DEFINE_IMX_GPIO_PORT(MX21, 5, 6), +}; + +DEFINE_REGISTER_FUNCTION(imx21) + +#endif /* if defined(CONFIG_SOC_IMX21) */ + +#if defined(CONFIG_SOC_IMX25) +static struct mxc_gpio_port imx25_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4), +}; + +DEFINE_REGISTER_FUNCTION(imx25) + +#endif /* if defined(CONFIG_SOC_IMX25) */ + +#if defined(CONFIG_SOC_IMX27) +static struct mxc_gpio_port imx27_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO), + DEFINE_IMX_GPIO_PORT(MX27, 1, 2), + DEFINE_IMX_GPIO_PORT(MX27, 2, 3), + DEFINE_IMX_GPIO_PORT(MX27, 3, 4), + DEFINE_IMX_GPIO_PORT(MX27, 4, 5), + DEFINE_IMX_GPIO_PORT(MX27, 5, 6), +}; + +DEFINE_REGISTER_FUNCTION(imx27) + +#endif /* if defined(CONFIG_SOC_IMX27) */ + +#if defined(CONFIG_SOC_IMX31) +static struct mxc_gpio_port imx31_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3), +}; + +DEFINE_REGISTER_FUNCTION(imx31) + +#endif /* if defined(CONFIG_SOC_IMX31) */ + +#if defined(CONFIG_SOC_IMX35) +static struct mxc_gpio_port imx35_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3), +}; + +DEFINE_REGISTER_FUNCTION(imx35) + +#endif /* if defined(CONFIG_SOC_IMX35) */ + +#if defined(CONFIG_SOC_IMX50) +static struct mxc_gpio_port imx50_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), + DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), +}; + +DEFINE_REGISTER_FUNCTION(imx50) + +#endif /* if defined(CONFIG_SOC_IMX50) */ diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 7a1e1f8..aea2cd3 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -20,7 +20,9 @@ extern void mx25_map_io(void); extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); +extern void mx50_map_io(void); extern void mx51_map_io(void); +extern void mx53_map_io(void); extern void mxc91231_map_io(void); extern void mxc_init_irq(void __iomem *); extern void tzic_init_irq(void __iomem *); @@ -30,7 +32,9 @@ extern void mx25_init_irq(void); extern void mx27_init_irq(void); extern void mx31_init_irq(void); extern void mx35_init_irq(void); +extern void mx50_init_irq(void); extern void mx51_init_irq(void); +extern void mx53_init_irq(void); extern void mxc91231_init_irq(void); extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); @@ -42,6 +46,8 @@ extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); +extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2); extern int mxc91231_clocks_init(unsigned long fref); extern int mxc_register_gpios(void); extern int mxc_register_device(struct platform_device *pdev, void *data); @@ -50,5 +56,6 @@ extern void mxc_arch_reset_init(void __iomem *); extern void mxc91231_power_off(void); extern void mxc91231_arch_reset(int, const char *); extern void mxc91231_prepare_idle(void); - +extern void mx51_efikamx_reset(void); +extern int mx53_revision(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index d56213f..3b3a37c 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -10,58 +10,49 @@ * published by the Free Software Foundation. * */ -#define IMX_NEEDS_DEPRECATED_SYMBOLS +#include <mach/hardware.h> #ifdef CONFIG_ARCH_MX1 -#include <mach/mx1.h> -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX1_UART1_BASE_ADDR #endif #ifdef CONFIG_ARCH_MX25 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mx25.h> #define UART_PADDR MX25_UART1_BASE_ADDR -#define UART_VADDR MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR) #endif #ifdef CONFIG_ARCH_MX2 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mx2x.h> -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX2x_UART1_BASE_ADDR #endif #ifdef CONFIG_ARCH_MX3 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mx3x.h> -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX3x_UART1_BASE_ADDR #endif #ifdef CONFIG_ARCH_MX5 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mx51.h> #define UART_PADDR MX51_UART1_BASE_ADDR -#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR) #endif #ifdef CONFIG_ARCH_MXC91231 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mxc91231.h> #define UART_PADDR MXC91231_UART2_BASE_ADDR -#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) #endif + +#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) + .macro addruart, rp, rv ldr \rp, =UART_PADDR @ physical ldr \rv, =UART_VADDR @ virtual diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 8c6896f..8658c9c 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -10,9 +10,19 @@ #include <linux/platform_device.h> #include <linux/init.h> -struct platform_device *imx_add_platform_device(const char *name, int id, +struct platform_device *imx_add_platform_device_dmamask( + const char *name, int id, const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data); + const void *data, size_t size_data, u64 dmamask); + +static inline struct platform_device *imx_add_platform_device( + const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data) +{ + return imx_add_platform_device_dmamask( + name, id, res, num_resources, data, size_data, 0); +} #include <linux/fec.h> struct imx_fec_data { @@ -24,15 +34,63 @@ struct platform_device *__init imx_add_fec( const struct fec_platform_data *pdata); #include <linux/can/platform/flexcan.h> -struct platform_device *__init imx_add_flexcan(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, +struct imx_flexcan_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_flexcan( + const struct imx_flexcan_data *data, const struct flexcan_platform_data *pdata); +#include <linux/fsl_devices.h> +struct imx_fsl_usb2_udc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_fsl_usb2_udc( + const struct imx_fsl_usb2_udc_data *data, + const struct fsl_usb2_platform_data *pdata); + #include <linux/gpio_keys.h> struct platform_device *__init imx_add_gpio_keys( const struct gpio_keys_platform_data *pdata); +#include <mach/mx21-usbhost.h> +struct imx_imx21_hcd_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx21_hcd( + const struct imx_imx21_hcd_data *data, + const struct mx21_usbh_platform_data *pdata); + +struct imx_imx2_wdt_data { + int id; + resource_size_t iobase; + resource_size_t iosize; +}; +struct platform_device *__init imx_add_imx2_wdt( + const struct imx_imx2_wdt_data *data); + +struct imx_imxdi_rtc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imxdi_rtc( + const struct imx_imxdi_rtc_data *data); + +#include <mach/imxfb.h> +struct imx_imx_fb_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_fb( + const struct imx_imx_fb_data *data, + const struct imx_fb_platform_data *pdata); + #include <mach/i2c.h> struct imx_imx_i2c_data { int id; @@ -44,6 +102,16 @@ struct platform_device *__init imx_add_imx_i2c( const struct imx_imx_i2c_data *data, const struct imxi2c_platform_data *pdata); +#include <linux/input/matrix_keypad.h> +struct imx_imx_keypad_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_keypad( + const struct imx_imx_keypad_data *data, + const struct matrix_keymap_data *pdata); + #include <mach/ssi.h> struct imx_imx_ssi_data { int id; @@ -82,6 +150,67 @@ struct platform_device *__init imx_add_imx_uart_1irq( const struct imx_imx_uart_1irq_data *data, const struct imxuart_platform_data *pdata); +#include <mach/usb.h> +struct imx_imx_udc_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq0; + resource_size_t irq1; + resource_size_t irq2; + resource_size_t irq3; + resource_size_t irq4; + resource_size_t irq5; + resource_size_t irq6; +}; +struct platform_device *__init imx_add_imx_udc( + const struct imx_imx_udc_data *data, + const struct imxusb_platform_data *pdata); + +#include <mach/mx1_camera.h> +struct imx_mx1_camera_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mx1_camera( + const struct imx_mx1_camera_data *data, + const struct mx1_camera_pdata *pdata); + +#include <mach/mx2_cam.h> +struct imx_mx2_camera_data { + resource_size_t iobasecsi; + resource_size_t iosizecsi; + resource_size_t irqcsi; + resource_size_t iobaseemmaprp; + resource_size_t iosizeemmaprp; + resource_size_t irqemmaprp; +}; +struct platform_device *__init imx_add_mx2_camera( + const struct imx_mx2_camera_data *data, + const struct mx2_camera_platform_data *pdata); + +#include <mach/mxc_ehci.h> +struct imx_mxc_ehci_data { + int id; + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mxc_ehci( + const struct imx_mxc_ehci_data *data, + const struct mxc_usbh_platform_data *pdata); + +#include <mach/mmc.h> +struct imx_mxc_mmc_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; + resource_size_t dmareq; +}; +struct platform_device *__init imx_add_mxc_mmc( + const struct imx_mxc_mmc_data *data, + const struct imxmmc_platform_data *pdata); + #include <mach/mxc_nand.h> struct imx_mxc_nand_data { /* @@ -99,24 +228,39 @@ struct platform_device *__init imx_add_mxc_nand( const struct imx_mxc_nand_data *data, const struct mxc_nand_platform_data *pdata); -#include <mach/spi.h> -struct imx_spi_imx_data { - const char *devid; +struct imx_mxc_pwm_data { int id; resource_size_t iobase; resource_size_t iosize; - int irq; + resource_size_t irq; }; -struct platform_device *__init imx_add_spi_imx( - const struct imx_spi_imx_data *data, - const struct spi_imx_master *pdata); +struct platform_device *__init imx_add_mxc_pwm( + const struct imx_mxc_pwm_data *data); + +struct imx_mxc_w1_data { + resource_size_t iobase; +}; +struct platform_device *__init imx_add_mxc_w1( + const struct imx_mxc_w1_data *data); #include <mach/esdhc.h> -struct imx_esdhc_imx_data { +struct imx_sdhci_esdhc_imx_data { int id; resource_size_t iobase; resource_size_t irq; }; -struct platform_device *__init imx_add_esdhc( - const struct imx_esdhc_imx_data *data, +struct platform_device *__init imx_add_sdhci_esdhc_imx( + const struct imx_sdhci_esdhc_imx_data *data, const struct esdhc_platform_data *pdata); + +#include <mach/spi.h> +struct imx_spi_imx_data { + const char *devid; + int id; + resource_size_t iobase; + resource_size_t iosize; + int irq; +}; +struct platform_device *__init imx_add_spi_imx( + const struct imx_spi_imx_data *data, + const struct spi_imx_master *pdata); diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index aeb0869..bd9bb97 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S @@ -54,15 +54,15 @@ #elif defined CONFIG_MXC_TZIC @ Load offset & priority of the highest priority @ interrupt pending. + @ 0x080 is INTSEC0 register @ 0xD80 is HIPND0 register mov \irqnr, #0 - mov \irqstat, #0x0D80 -1000: - ldr \tmp, [\irqstat, \base] - cmp \tmp, #0 - bne 1001f - addeq \irqnr, \irqnr, #32 - addeq \irqstat, \irqstat, #4 +1000: add \irqstat, \base, \irqnr, lsr #3 + ldr \tmp, [\irqstat, #0xd80] + ldr \irqstat, [\irqstat, #0x080] + ands \tmp, \tmp, \irqstat + bne 1001f + add \irqnr, \irqnr, #32 cmp \irqnr, #128 blo 1000b b 2001f diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index af33b74..0044e2f 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -23,6 +23,11 @@ #include <mach/hardware.h> #include <asm-generic/gpio.h> + +/* There's a off-by-one betweem the gpio bank number and the gpiochip */ +/* range e.g. GPIO_1_5 is gpio 5 under linux */ +#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) + /* use gpiolib dispatchers */ #define gpio_get_value __gpio_get_value #define gpio_set_value __gpio_set_value diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index ebadf4a..26bb1ba 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -22,13 +22,92 @@ #include <asm/sizes.h> -#define IMX_IO_ADDRESS(addr, module) \ - ((void __force __iomem *) \ - (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ - (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) +#ifdef __ASSEMBLER__ +#define IOMEM(addr) (addr) +#else +#define IOMEM(addr) ((void __force __iomem *)(addr)) +#endif + +#define IMX_IO_P2V_MODULE(addr, module) \ + (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \ + (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0) + +/* + * This is rather complicated for humans and ugly to verify, but for a machine + * it's OK. Still more as it is usually only applied to constants. The upsides + * on using this approach are: + * + * - same mapping on all i.MX machines + * - works for assembler, too + * - no need to nurture #defines for virtual addresses + * + * The downside it, it's hard to verify (but I have a script for that). + * + * Obviously this needs to be injective for each SoC. In general it maps the + * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff] + * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there). + * + * It applies the following mappings for the different SoCs: + * + * mx1: + * IO 0x00200000+0x100000 -> 0xf4000000+0x100000 + * mx21: + * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 + * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 + * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000 + * mx25: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * mx27: + * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 + * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 + * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000 + * mx31: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * mx35: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * mx50: + * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 + * mx51: + * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 + * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000 + * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 + * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 + * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 + * mxc91231: + * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000 + * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000 + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + */ +#define IMX_IO_P2V(x) ( \ + 0xf4000000 + \ + (((x) & 0x50000000) >> 6) + \ + (((x) & 0x0b000000) >> 4) + \ + (((x) & 0x000fffff))) + +#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) #ifdef CONFIG_ARCH_MX5 +#include <mach/mx50.h> #include <mach/mx51.h> +#include <mach/mx53.h> #endif #ifdef CONFIG_ARCH_MX3 @@ -61,4 +140,11 @@ #include <mach/mxc.h> +#define imx_map_entry(soc, name, _type) { \ + .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ + .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ + .length = soc ## _ ## name ## _SIZE, \ + .type = _type, \ +} + #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h index 5263506..9de8f06 100644 --- a/arch/arm/plat-mxc/include/mach/imxfb.h +++ b/arch/arm/plat-mxc/include/mach/imxfb.h @@ -1,6 +1,8 @@ /* * This structure describes the machine which we are running on. */ +#ifndef __MACH_IMXFB_H__ +#define __MACH_IMXFB_H__ #include <linux/fb.h> @@ -79,3 +81,4 @@ struct imx_fb_platform_data { }; void set_imx_fb_info(struct imx_fb_platform_data *); +#endif /* ifndef __MACH_IMXFB_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h new file mode 100644 index 0000000..058a922 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h @@ -0,0 +1,977 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX50_H__ +#define __MACH_IOMUX_MX50_H__ + +#include <mach/iomux-v3.h> + +#define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH) + +#define MX50_SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) + +#define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE) + +#define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) + +#define MX50_USB_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP) + +#define MX50_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH) + +#define MX50_OWIRE_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) + +#define MX50_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) + +#define MX50_CSPI_SS_PAD (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL0__GPIO_4_0 IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL0__NANDF_CLE IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_ROW0__GPIO_4_1 IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__NANDF_ALE IOMUX_PAD(0x2D0, 0x24, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__GPIO_4_2 IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__NANDF_CE0 IOMUX_PAD(0x2D4, 0x28, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_ROW1__GPIO_4_3 IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__NANDF_CE1 IOMUX_PAD(0x2D8, 0x2C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_COL2__GPIO_4_4 IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL2__NANDF_CE2 IOMUX_PAD(0x2DC, 0x30, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_ROW2__GPIO_4_5 IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__NANDF_CE3 IOMUX_PAD(0x2E0, 0x34, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__GPIO_4_6 IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__NANDF_READY IOMUX_PAD(0x2E4, 0x38, 2, 0x7b4, 0, PAD_CTL_PKE | \ + PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define MX50_PAD_KEY_COL3__SDMA_EXT0 IOMUX_PAD(0x2E4, 0x38, 6, 0x7b8, 0, NO_PAD_CTRL) + +#define MX50_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_ROW3__GPIO_4_7 IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__NANDF_DQS IOMUX_PAD(0x2E8, 0x3C, 2, 0x7b0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_KEY_ROW3__SDMA_EXT1 IOMUX_PAD(0x2E8, 0x3C, 6, 0x7bc, 0, NO_PAD_CTRL) + +#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x7cc, 0, MX50_UART_PAD_CTRL) + +#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__GPIO_6_19 IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__UART2_RXD IOMUX_PAD(0x2F0, 0x44, 2, 0x7cc, 1, MX50_UART_PAD_CTRL) + +#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x7c8, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__GPIO_6_21 IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__UART2_RTS IOMUX_PAD(0x2F8, 0x4C, 2, 0x7c8, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__PWRSTABLE IOMUX_PAD(0x2F8, 0x4C, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x50, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__GPIO_6_22 IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__FEC_MDC IOMUX_PAD(0x2FC, 0x50, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_I2C3_SCL__PMIC_RDY IOMUX_PAD(0x2FC, 0x50, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 IOMUX_PAD(0x2FC, 0x50, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__USBOTG_OC IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, MX50_USB_PAD_CTRL) + +#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x54, IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__GPIO_6_23 IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__FEC_MDIO IOMUX_PAD(0x300, 0x54, 2, 0x774, 0, MX50_FEC_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__PWRFAIL_INT IOMUX_PAD(0x300, 0x54, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__ALARM_DEB IOMUX_PAD(0x300, 0x54, 4, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__GPT_CAPIN1 IOMUX_PAD(0x300, 0x54, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__USBOTG_PWR IOMUX_PAD(0x300, 0x54, 7, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) + +#define MX50_PAD_PWM1__PWM1_PWMO IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__GPIO_6_24 IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__USBOTG_OC IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, MX50_USB_PAD_CTRL) +#define MX50_PAD_PWM1__GPT_CMPOUT1 IOMUX_PAD(0x304, 0x58, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PWM2__PWM2_PWMO IOMUX_PAD(0x308, 0x5C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__GPIO_6_25 IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__USBOTG_PWR IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) +#define MX50_PAD_PWM2__DCDC_PWM IOMUX_PAD(0x308, 0x5C, 4, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__GPT_CMPOUT2 IOMUX_PAD(0x308, 0x5C, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__ANY_PU_RST IOMUX_PAD(0x308, 0x5C, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_OWIRE__OWIRE IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, MX50_OWIRE_PAD_CTRL) +#define MX50_PAD_OWIRE__GPIO_6_26 IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__USBH1_OC IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, MX50_USB_PAD_CTRL) +#define MX50_PAD_OWIRE__SSI_EXT1_CLK IOMUX_PAD(0x30C, 0x60, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__EPDC_PWRIRQ IOMUX_PAD(0x30C, 0x60, 4, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__GPT_CMPOUT3 IOMUX_PAD(0x30C, 0x60, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPITO__EPITO IOMUX_PAD(0x310, 0x64, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__GPIO_6_27 IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__USBH1_PWR IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) +#define MX50_PAD_EPITO__SSI_EXT2_CLK IOMUX_PAD(0x310, 0x64, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__TOG_EN IOMUX_PAD(0x310, 0x64, 4, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__GPT_CLKIN IOMUX_PAD(0x310, 0x64, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_WDOG__WDOG IOMUX_PAD(0x314, 0x68, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__GPIO_6_28 IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__WDOG_RST IOMUX_PAD(0x314, 0x68, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__XTAL32K IOMUX_PAD(0x314, 0x68, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SSI_TXFS__SSI_TXFS IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXFS__GPIO_6_0 IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SSI_TXC__SSI_TXC IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXC__GPIO_6_1 IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SSI_TXD__SSI_TXD IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__GPIO_6_2 IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__CSPI_RDY IOMUX_PAD(0x320, 0x74, 4, 0x6e8, 0, NO_PAD_CTRL) + +#define MX50_PAD_SSI_RXD__SSI_RXD IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__GPIO_6_3 IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__CSPI_SS3 IOMUX_PAD(0x324, 0x78, 4, 0x6f4, 0, MX50_CSPI_SS_PAD) + +#define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x7e4, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_SSI_RXC__AUD3_RXC IOMUX_PAD(0x32C, 0x80, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__GPIO_6_5 IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__UART5_RXD IOMUX_PAD(0x32C, 0x80, 2, 0x7e4, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_SSI_RXC__WEIM_D7 IOMUX_PAD(0x32C, 0x80, 3, 0x808, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__CSPI_SS1 IOMUX_PAD(0x32C, 0x80, 4, 0x6ec, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL) + +#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x7c4, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x7c0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x7e4, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x0, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x0, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x7cc, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RXD__GPIO_6_11 IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x7c8, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RTS__GPIO_6_13 IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL) + +#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x7d4, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_TXD__SD2_WP IOMUX_PAD(0x350, 0xA4, 5, 0x744, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_TXD__WEIM_D12 IOMUX_PAD(0x350, 0xA4, 6, 0x81c, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x354, 0xA8, 0, 0x7d4, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART3_RXD__GPIO_6_15 IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_RXD__SD1_D5 IOMUX_PAD(0x354, 0xA8, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_RXD__SD4_D1 IOMUX_PAD(0x354, 0xA8, 4, 0x754, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x7dc, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x7d0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_TXD__WEIM_D14 IOMUX_PAD(0x358, 0xAC, 6, 0x824, 0, NO_PAD_CTRL) + +#define MX50_PAD_UART4_RXD__UART4_RXD IOMUX_PAD(0x35C, 0xB0, 0, 0x7dc, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_RXD__GPIO_6_17 IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_RXD__UART3_RTS IOMUX_PAD(0x35C, 0xB0, 2, 0x7d0, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_UART4_RXD__SD1_D7 IOMUX_PAD(0x35C, 0xB0, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_RXD__SD4_D3 IOMUX_PAD(0x35C, 0xB0, 4, 0x75c, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_RXD__SD1_LCTL IOMUX_PAD(0x35C, 0xB0, 5, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_UART4_RXD__WEIM_D15 IOMUX_PAD(0x35C, 0xB0, 6, 0x828, 0, NO_PAD_CTRL) + +#define MX50_PAD_CSPI_SCLK__CSPI_SCLK IOMUX_PAD(0x360, 0xB4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_SCLK__GPIO_4_8 IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MOSI__GPIO_4_9 IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MISO__GPIO_4_10 IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_CSPI_SS0__GPIO_4_11 IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x370, 0xC4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12 IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY IOMUX_PAD(0x370, 0xC4, 2, 0x6e8, 1, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY IOMUX_PAD(0x370, 0xC4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__UART3_RTS IOMUX_PAD(0x370, 0xC4, 4, 0x7d0, 2, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE6 IOMUX_PAD(0x370, 0xC4, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__WEIM_D8 IOMUX_PAD(0x370, 0xC4, 7, 0x80c, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x374, 0xC8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x7d0, 3, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x378, 0xCC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__GPIO_4_14 IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 IOMUX_PAD(0x378, 0xCC, 2, 0x6f0, 1, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 IOMUX_PAD(0x378, 0xCC, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_MISO__UART4_RTS IOMUX_PAD(0x378, 0xCC, 4, 0x7d8, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE8 IOMUX_PAD(0x378, 0xCC, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__WEIM_D10 IOMUX_PAD(0x378, 0xCC, 7, 0x814, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x37C, 0xD0, 0, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x7d8, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK IOMUX_PAD(0x380, 0xD4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16 IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR IOMUX_PAD(0x380, 0xD4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY IOMUX_PAD(0x380, 0xD4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__UART5_RTS IOMUX_PAD(0x380, 0xD4, 4, 0x7e0, 0, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK IOMUX_PAD(0x380, 0xD4, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__NANDF_CEN4 IOMUX_PAD(0x380, 0xD4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SCLK__WEIM_D8 IOMUX_PAD(0x380, 0xD4, 7, 0x80c, 1, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI IOMUX_PAD(0x384, 0xD8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x7e0, 1, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x73c, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x7e4, 4, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL) + +#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 IOMUX_PAD(0x38C, 0xE0, 0, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI2_SS0__GPIO_4_19 IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS IOMUX_PAD(0x38C, 0xE0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__ECSPI1_SS3 IOMUX_PAD(0x38C, 0xE0, 3, 0x0, 0, MX50_CSPI_SS_PAD) +#define MX50_PAD_ECSPI2_SS0__UART5_RXD IOMUX_PAD(0x38C, 0xE0, 4, 0x7e4, 5, MX50_UART_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC IOMUX_PAD(0x38C, 0xE0, 5, 0x6f8, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__NANDF_CEN7 IOMUX_PAD(0x38C, 0xE0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_SS0__WEIM_D11 IOMUX_PAD(0x38C, 0xE0, 7, 0x818, 1, NO_PAD_CTRL) + +#define MX50_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x390, 0xE4, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_CLK__GPIO_5_0 IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_CLK__CLKO IOMUX_PAD(0x390, 0xE4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x394, 0xE8, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_CMD__GPIO_5_1 IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_CMD__CLKO2 IOMUX_PAD(0x394, 0xE8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_D0__SD1_D0 IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D0__GPIO_5_2 IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D0__PLL1_BYP IOMUX_PAD(0x398, 0xEC, 7, 0x6dc, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_D1__SD1_D1 IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D1__GPIO_5_3 IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D1__PLL2_BYP IOMUX_PAD(0x39C, 0xF0, 7, 0x6e0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_D2__SD1_D2 IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D2__GPIO_5_4 IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D2__PLL3_BYP IOMUX_PAD(0x3A0, 0xF4, 7, 0x6e4, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD1_D3__SD1_D3 IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D3__GPIO_5_5 IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x3A8, 0xFC, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CLK__GPIO_5_6 IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CLK__MSHC_SCLK IOMUX_PAD(0x3A8, 0xFC, 2, 0x0, 0, MX50_SD_PAD_CTRL) + +#define MX50_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x3AC, 0x100, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CMD__GPIO_5_7 IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CMD__MSHC_BS IOMUX_PAD(0x3AC, 0x100, 2, 0x0, 0, MX50_SD_PAD_CTRL) + +#define MX50_PAD_SD2_D0__SD2_D0 IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D0__GPIO_5_8 IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D0__MSHC_D0 IOMUX_PAD(0x3B0, 0x104, 2, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D0__KEY_COL4 IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D1__SD2_D1 IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D1__GPIO_5_9 IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D1__MSHC_D1 IOMUX_PAD(0x3B4, 0x108, 2, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D1__KEY_ROW4 IOMUX_PAD(0x3B4, 0x108, 3, 0x7a0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D2__SD2_D2 IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D2__GPIO_5_10 IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D2__MSHC_D2 IOMUX_PAD(0x3B8, 0x10C, 2, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D2__KEY_COL5 IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D3__SD2_D3 IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D3__GPIO_5_11 IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D3__MSHC_D3 IOMUX_PAD(0x3BC, 0x110, 2, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D3__KEY_ROW5 IOMUX_PAD(0x3BC, 0x110, 3, 0x7a4, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D4__SD2_D4 IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D4__GPIO_5_12 IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__AUD4_RXFS IOMUX_PAD(0x3C0, 0x114, 2, 0x6d0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__KEY_COL6 IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__WEIM_D0 IOMUX_PAD(0x3C0, 0x114, 4, 0x7ec, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__CCM_OUT0 IOMUX_PAD(0x3C0, 0x114, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D5__SD2_D5 IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D5__GPIO_5_13 IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__AUD4_RXC IOMUX_PAD(0x3C4, 0x118, 2, 0x6cc, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__KEY_ROW6 IOMUX_PAD(0x3C4, 0x118, 3, 0x7a8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__WEIM_D1 IOMUX_PAD(0x3C4, 0x118, 4, 0x7f0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__CCM_OUT1 IOMUX_PAD(0x3C4, 0x118, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D6__SD2_D6 IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D6__GPIO_5_14 IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__AUD4_RXD IOMUX_PAD(0x3C8, 0x11C, 2, 0x6c4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__KEY_COL7 IOMUX_PAD(0x3C8, 0x11C, 3, 0x79c, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__WEIM_D2 IOMUX_PAD(0x3C8, 0x11C, 4, 0x7f4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__CCM_OUT2 IOMUX_PAD(0x3C8, 0x11C, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_D7__SD2_D7 IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D7__GPIO_5_15 IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__AUD4_TXFS IOMUX_PAD(0x3CC, 0x120, 2, 0x6d8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__KEY_ROW7 IOMUX_PAD(0x3CC, 0x120, 3, 0x7ac, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__WEIM_D3 IOMUX_PAD(0x3CC, 0x120, 4, 0x7f8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__CCM_STOP IOMUX_PAD(0x3CC, 0x120, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_WP__SD2_WP IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_WP__GPIO_5_16 IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__AUD4_TXD IOMUX_PAD(0x3D0, 0x124, 2, 0x6c8, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__WEIM_D4 IOMUX_PAD(0x3D0, 0x124, 4, 0x7fc, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__CCM_WAIT IOMUX_PAD(0x3D0, 0x124, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD2_CD__SD2_CD IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CD__GPIO_5_17 IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CD__AUD4_TXC IOMUX_PAD(0x3D4, 0x128, 2, 0x6d4, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CD__WEIM_D5 IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CD__CCM_REF_EN IOMUX_PAD(0x3D4, 0x128, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x3D8, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x3DC, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B IOMUX_PAD(0x3E0, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1 IOMUX_PAD(0x3E4, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B IOMUX_PAD(0x3E8, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0 IOMUX_PAD(0x3EC, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS IOMUX_PAD(0x3F4, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD IOMUX_PAD(0x3F8, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB IOMUX_PAD(0x3FC, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI IOMUX_PAD(0x400, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK IOMUX_PAD(0x404, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO IOMUX_PAD(0x408, 0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D0__DISP_D0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D0__GPIO_2_0 IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D0__FEC_TXCLK IOMUX_PAD(0x40C, 0x12C, 2, 0x78c, 0, PAD_CTL_HYS | PAD_CTL_PKE) + +#define MX50_PAD_DISP_D1__DISP_D1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D1__GPIO_2_1 IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D1__FEC_RX_ER IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D1__WEIM_A17 IOMUX_PAD(0x410, 0x130, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D2__DISP_D2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D2__GPIO_2_2 IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D2__WEIM_A18 IOMUX_PAD(0x414, 0x134, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D3__DISP_D3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D3__GPIO_2_3 IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__FEC_RXD1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D3__WEIM_A19 IOMUX_PAD(0x418, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__FEC_COL IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D4__DISP_D4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D4__GPIO_2_4 IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D4__FEC_RXD0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D4__WEIM_A20 IOMUX_PAD(0x41C, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D5__DISP_D5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D5__GPIO_2_5 IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D5__WEIM_A21 IOMUX_PAD(0x420, 0x140, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D6__DISP_D6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D6__GPIO_2_6 IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__FEC_TXD1 IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D6__WEIM_A22 IOMUX_PAD(0x424, 0x144, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__FEC_RX_CLK IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D7__DISP_D7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D7__GPIO_2_7 IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D7__FEC_TXD0 IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D7__WEIM_A23 IOMUX_PAD(0x428, 0x148, 3, 0x0, 0, NO_PAD_CTRL) + + +#define MX50_PAD_DISP_WR__ELCDIF_WR IOMUX_PAD(0x42C, 0x14C, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_WR__GPIO_2_16 IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_WR__WEIM_A24 IOMUX_PAD(0x42C, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_RD__ELCDIF_RD IOMUX_PAD(0x430, 0x150, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RD__GPIO_2_19 IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_CS__ELCDIF_CS IOMUX_PAD(0x438, 0x158, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_CS__GPIO_2_21 IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x6f8, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_CS__WEIM_A27 IOMUX_PAD(0x438, 0x158, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__WEIM_CS3 IOMUX_PAD(0x438, 0x158, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__GPIO_2_18 IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__WEIM_CS3 IOMUX_PAD(0x43C, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_RESET__ELCDIF_RST IOMUX_PAD(0x440, 0x160, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RESET__GPIO_2_20 IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RESET__WEIM_CS3 IOMUX_PAD(0x440, 0x160, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_CMD__SD3_CMD IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_CMD__GPIO_5_18 IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_CMD__NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_CMD__SSP_CMD IOMUX_PAD(0x444, 0x164, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_CLK__SD3_CLK IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_CLK__GPIO_5_19 IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_CLK__NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_CLK__SSP_CLK IOMUX_PAD(0x448, 0x168, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D0__SD3_D0 IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D0__GPIO_5_20 IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D0__NANDF_D4 IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D0__SSP_D0 IOMUX_PAD(0x44C, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D0__PLL1_BYP IOMUX_PAD(0x44C, 0x16C, 7, 0x6dc, 1, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D1__SD3_D1 IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D1__GPIO_5_21 IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D1__NANDF_D5 IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D1__PLL2_BYP IOMUX_PAD(0x450, 0x170, 7, 0x6e0, 1, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D2__SD3_D2 IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D2__GPIO_5_22 IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D2__NANDF_D6 IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D2__SSP_D2 IOMUX_PAD(0x454, 0x174, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D2__PLL3_BYP IOMUX_PAD(0x454, 0x174, 7, 0x6e4, 1, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D3__SD3_D3 IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D3__GPIO_5_23 IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D3__NANDF_D7 IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D3__SSP_D3 IOMUX_PAD(0x458, 0x178, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D4__SD3_D4 IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D4__GPIO_5_24 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D4__NANDF_D0 IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D4__SSP_D4 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D5__SD3_D5 IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D5__GPIO_5_25 IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D5__NANDF_D1 IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D5__SSP_D5 IOMUX_PAD(0x460, 0x180, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D6__SD3_D6 IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D6__GPIO_5_26 IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D6__NANDF_D2 IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D6__SSP_D6 IOMUX_PAD(0x464, 0x184, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_D7__SD3_D7 IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_D7__GPIO_5_27 IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_D7__NANDF_D3 IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_D7__SSP_D7 IOMUX_PAD(0x468, 0x188, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_SD3_WP__SD3_WP IOMUX_PAD(0x46C, 0x18C, 0, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_WP__GPIO_5_28 IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_SD3_WP__NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_SD3_WP__SSP_CD IOMUX_PAD(0x46C, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_WP__SD4_LCTL IOMUX_PAD(0x46C, 0x18C, 4, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD3_WP__WEIM_CS3 IOMUX_PAD(0x46C, 0x18C, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D8__DISP_D8 IOMUX_PAD(0x470, 0x190, 0, 0x71c, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D8__GPIO_2_8 IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__NANDF_CLE IOMUX_PAD(0x470, 0x190, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__SD1_LCTL IOMUX_PAD(0x470, 0x190, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D8__SD4_CMD IOMUX_PAD(0x470, 0x190, 4, 0x74c, 2, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D8__KEY_COL4 IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__FEC_TX_CLK IOMUX_PAD(0x470, 0x190, 6, 0x78c, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D9__DISP_D9 IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D9__GPIO_2_9 IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__NANDF_ALE IOMUX_PAD(0x474, 0x194, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__SD2_LCTL IOMUX_PAD(0x474, 0x194, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D9__SD4_CLK IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D9__KEY_ROW4 IOMUX_PAD(0x474, 0x194, 5, 0x7a0, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__FEC_RX_ER IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D10__DISP_D10 IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D10__GPIO_2_10 IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__NANDF_CEN0 IOMUX_PAD(0x478, 0x198, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__SD3_LCTL IOMUX_PAD(0x478, 0x198, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D10__SD4_D0 IOMUX_PAD(0x478, 0x198, 4, 0x750, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D10__KEY_COL5 IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__FEC_RX_DV IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D11__DISP_D11 IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D11__GPIO_2_11 IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__NANDF_CEN1 IOMUX_PAD(0x47C, 0x19C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__SD4_D1 IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D11__KEY_ROW5 IOMUX_PAD(0x47C, 0x19C, 5, 0x7a4, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__FEC_RDAT1 IOMUX_PAD(0x47C, 0x19C, 6, 0x77c, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D12__DISP_D12 IOMUX_PAD(0x480, 0x1A0, 0, 0x72c, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D12__GPIO_2_12 IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__NANDF_CEN2 IOMUX_PAD(0x480, 0x1A0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__SD1_CD IOMUX_PAD(0x480, 0x1A0, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D12__SD4_D2 IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D12__KEY_COL6 IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__FEC_RDAT0 IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D13__DISP_D13 IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D13__GPIO_2_13 IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__NANDF_CEN3 IOMUX_PAD(0x484, 0x1A4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__SD3_CD IOMUX_PAD(0x484, 0x1A4, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D13__SD4_D3 IOMUX_PAD(0x484, 0x1A4, 4, 0x75c, 1, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D13__KEY_ROW6 IOMUX_PAD(0x484, 0x1A4, 5, 0x7a8, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__FEC_TX_EN IOMUX_PAD(0x484, 0x1A4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D14__DISP_D14 IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D14__GPIO_2_14 IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__NANDF_RDY0 IOMUX_PAD(0x488, 0x1A8, 2, 0x7b4, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__SD1_WP IOMUX_PAD(0x488, 0x1A8, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D14__SD4_WP IOMUX_PAD(0x488, 0x1A8, 4, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D14__KEY_COL7 IOMUX_PAD(0x488, 0x1A8, 5, 0x79c, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__FEC_TDAT1 IOMUX_PAD(0x488, 0x1A8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D15__DISP_D15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D15__GPIO_2_15 IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__NANDF_DQS IOMUX_PAD(0x48C, 0x1AC, 2, 0x7b0, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__SD3_RST IOMUX_PAD(0x48C, 0x1AC, 3, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D15__SD4_CD IOMUX_PAD(0x48C, 0x1AC, 4, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_DISP_D15__KEY_ROW7 IOMUX_PAD(0x48C, 0x1AC, 5, 0x7ac, 1, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__FEC_TDAT0 IOMUX_PAD(0x48C, 0x1AC, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D0__EPDC_D0 IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__GPIO_3_0 IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__WEIM_D0 IOMUX_PAD(0x54C, 0x1B0, 2, 0x7ec, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D0__ELCDIF_RS IOMUX_PAD(0x54C, 0x1B0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D0__ELCDIF_PIXCLK IOMUX_PAD(0x54C, 0x1B0, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D1__EPDC_D1 IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__GPIO_3_1 IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__WEIM_D1 IOMUX_PAD(0x550, 0x1B4, 2, 0x7f0, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__ELCDIF_CS IOMUX_PAD(0x550, 0x1B4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D1__ELCDIF_EN IOMUX_PAD(0x550, 0x1B4, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D2__EPDC_D2 IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__GPIO_3_2 IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__WEIM_D2 IOMUX_PAD(0x554, 0x1B8, 2, 0x7f4, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__ELCDIF_WR IOMUX_PAD(0x554, 0x1B8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC IOMUX_PAD(0x554, 0x1B8, 4, 0x73c, 2, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D3__EPDC_D3 IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__GPIO_3_3 IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__WEIM_D3 IOMUX_PAD(0x558, 0x1BC, 2, 0x7f8, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__ELCDIF_RD IOMUX_PAD(0x558, 0x1BC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC IOMUX_PAD(0x558, 0x1BC, 4, 0x6f8, 3, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D4__EPDC_D4 IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__GPIO_3_4 IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__WEIM_D4 IOMUX_PAD(0x55C, 0x1C0, 2, 0x7fc, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D5__EPDC_D5 IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__GPIO_3_5 IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__WEIM_D5 IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D6__EPDC_D6 IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__GPIO_3_6 IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__WEIM_D6 IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D7__EPDC_D7 IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__GPIO_3_7 IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__WEIM_D7 IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D8__EPDC_D8 IOMUX_PAD(0x56C, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__GPIO_3_8 IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__WEIM_D8 IOMUX_PAD(0x56C, 0x1D0, 2, 0x80c, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__ELCDIF_D24 IOMUX_PAD(0x56C, 0x1D0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x810, 2, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__WEIM_D10 IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__ELCDIF_D26 IOMUX_PAD(0x574, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D11__EPDC_D11 IOMUX_PAD(0x578, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__GPIO_3_11 IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__WEIM_D11 IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__ELCDIF_D27 IOMUX_PAD(0x578, 0x1DC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D12__EPDC_D12 IOMUX_PAD(0x57C, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__GPIO_3_12 IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__WEIM_D12 IOMUX_PAD(0x57C, 0x1E0, 2, 0x81c, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__ELCDIF_D28 IOMUX_PAD(0x57C, 0x1E0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D13__EPDC_D13 IOMUX_PAD(0x580, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__GPIO_3_13 IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__WEIM_D13 IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__ELCDIF_D29 IOMUX_PAD(0x580, 0x1E4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_D14__EPDC_D14 IOMUX_PAD(0x584, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__GPIO_3_14 IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__WEIM_D14 IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__ELCDIF_D30 IOMUX_PAD(0x584, 0x1E8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D14__AUD6_TXD IOMUX_PAD(0x584, 0x1E8, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D15__EPDC_D15 IOMUX_PAD(0x588, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__GPIO_3_15 IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__WEIM_D15 IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__ELCDIF_D31 IOMUX_PAD(0x588, 0x1EC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_D15__AUD6_TXC IOMUX_PAD(0x588, 0x1EC, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__GPIO_3_16 IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__WEIM_D16 IOMUX_PAD(0x58C, 0x1F0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__ELCDIF_D16 IOMUX_PAD(0x58C, 0x1F0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__AUD6_TXFS IOMUX_PAD(0x58C, 0x1F0, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__GPIO_3_17 IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__WEIM_D17 IOMUX_PAD(0x590, 0x1F4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__ELCDIF_D17 IOMUX_PAD(0x590, 0x1F4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__AUD6_RXD IOMUX_PAD(0x590, 0x1F4, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__GPIO_3_18 IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__WEIM_D18 IOMUX_PAD(0x594, 0x1F8, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__ELCDIF_D18 IOMUX_PAD(0x594, 0x1F8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__AUD6_RXC IOMUX_PAD(0x594, 0x1F8, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__GPIO_3_19 IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__WEIM_D19 IOMUX_PAD(0x598, 0x1FC, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__ELCDIF_D19 IOMUX_PAD(0x598, 0x1FC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__AUD6_RXFS IOMUX_PAD(0x598, 0x1FC, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__GPIO_3_20 IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__WEIM_D20 IOMUX_PAD(0x59C, 0x200, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__ELCDIF_D20 IOMUX_PAD(0x59C, 0x200, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__AUD5_TXD IOMUX_PAD(0x59C, 0x200, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDOEZ__EPDC_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21 IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__WEIM_D21 IOMUX_PAD(0x5A0, 0x204, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__ELCDIF_D21 IOMUX_PAD(0x5A0, 0x204, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__AUD5_TXC IOMUX_PAD(0x5A0, 0x204, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDOED__EPDC_SDOED IOMUX_PAD(0x5A4, 0x208, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__GPIO_3_22 IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__WEIM_D22 IOMUX_PAD(0x5A4, 0x208, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__ELCDIF_D22 IOMUX_PAD(0x5A4, 0x208, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__AUD5_TXFS IOMUX_PAD(0x5A4, 0x208, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__GPIO_3_23 IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__WEIM_D23 IOMUX_PAD(0x5A8, 0x20C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__ELCDIF_D23 IOMUX_PAD(0x5A8, 0x20C, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__AUD5_RXD IOMUX_PAD(0x5A8, 0x20C, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__GPIO_3_24 IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__WEIM_D24 IOMUX_PAD(0x5AC, 0x210, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__ELCDIF_D8 IOMUX_PAD(0x5AC, 0x210, 3, 0x71c, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__AUD5_RXC IOMUX_PAD(0x5AC, 0x210, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCLKN__EPDC_SDCLKN IOMUX_PAD(0x5B0, 0x214, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25 IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__WEIM_D25 IOMUX_PAD(0x5B0, 0x214, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__ELCDIF_D9 IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__AUD5_RXFS IOMUX_PAD(0x5B0, 0x214, 4, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__GPIO_3_26 IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__WEIM_D26 IOMUX_PAD(0x5B4, 0x218, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__ELCDIF_D10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__AUD4_TXD IOMUX_PAD(0x5B4, 0x218, 4, 0x6c8, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCOM__EPDC_PWRCOM IOMUX_PAD(0x5B8, 0x21C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27 IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__WEIM_D27 IOMUX_PAD(0x5B8, 0x21C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__ELCDIF_D11 IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__AUD4_TXC IOMUX_PAD(0x5B8, 0x21C, 4, 0x6d4, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT IOMUX_PAD(0x5BC, 0x220, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28 IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__WEIM_D28 IOMUX_PAD(0x5BC, 0x220, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_D12 IOMUX_PAD(0x5BC, 0x220, 3, 0x72c, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__AUD4_TXFS IOMUX_PAD(0x5BC, 0x220, 4, 0x6d8, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL0 IOMUX_PAD(0x5C0, 0x224, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29 IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__WEIM_D29 IOMUX_PAD(0x5C0, 0x224, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_D13 IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL0__AUD4_RXD IOMUX_PAD(0x5C0, 0x224, 4, 0x6c4, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL1 IOMUX_PAD(0x5C4, 0x228, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30 IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__WEIM_D30 IOMUX_PAD(0x5C4, 0x228, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_D14 IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__AUD4_RXC IOMUX_PAD(0x5C4, 0x228, 4, 0x6cc, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL2 IOMUX_PAD(0x5C8, 0x22C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31 IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__WEIM_D31 IOMUX_PAD(0x5C8, 0x22C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_D15 IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__AUD4_RXFS IOMUX_PAD(0x5C8, 0x22C, 4, 0x6d0, 1, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT0 IOMUX_PAD(0x5C8, 0x22C, 6, 0x7b8, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_PWRCTRL3__PWRCTRL3 IOMUX_PAD(0x5CC, 0x230, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20 IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__WEIM_EB2 IOMUX_PAD(0x5CC, 0x230, 2, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT1 IOMUX_PAD(0x5CC, 0x230, 6, 0x7bc, 1, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_VCOM0__EPDC_VCOM0 IOMUX_PAD(0x5D0, 0x234, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM0__GPIO_4_21 IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM0__WEIM_EB3 IOMUX_PAD(0x5D0, 0x234, 2, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_VCOM1__EPDC_VCOM1 IOMUX_PAD(0x5D4, 0x238, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM1__GPIO_4_22 IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM1__WEIM_CS3 IOMUX_PAD(0x5D4, 0x238, 2, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_BDR0__EPDC_BDR0 IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__GPIO_4_23 IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__ELCDIF_D7 IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_BDR1__EPDC_BDR1 IOMUX_PAD(0x5DC, 0x240, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR1__GPIO_4_24 IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR1__ELCDIF_D6 IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__GPIO_4_25 IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__ELCDIF_D5 IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__GPIO_4_26 IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__ELCDIF_D4 IOMUX_PAD(0x5E4, 0x248, 2, 0x70c, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2 IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__GPIO_4_27 IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT3 IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE3__EPDC_SDCE3 IOMUX_PAD(0x5EC, 0x250, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE3__GPIO_4_28 IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE3__ELCDIF_D2 IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE4__EPDC_SDCE4 IOMUX_PAD(0x5F0, 0x254, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE4__GPIO_4_29 IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE4__ELCDIF_D1 IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EPDC_SDCE5__EPDC_SDCE5 IOMUX_PAD(0x5F4, 0x258, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE5__GPIO_4_30 IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE5__ELCDIF_D0 IOMUX_PAD(0x5F4, 0x258, 3, 0x6fc, 1, MX50_ELCDIF_PAD_CTRL) + +#define MX50_PAD_EIM_DA0__WEIM_A0 IOMUX_PAD(0x5F8, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__GPIO_1_0 IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__KEY_COL4 IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA1__WEIM_A1 IOMUX_PAD(0x5FC, 0x260, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__GPIO_1_1 IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__KEY_ROW4 IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, MX50_KEYPAD_CTRL) + +#define MX50_PAD_EIM_DA2__WEIM_A2 IOMUX_PAD(0x600, 0x264, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA2__GPIO_1_2 IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA2__KEY_COL5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA3__WEIM_A3 IOMUX_PAD(0x604, 0x268, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__GPIO_1_3 IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__KEY_ROW5 IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, MX50_KEYPAD_CTRL) + +#define MX50_PAD_EIM_DA4__WEIM_A4 IOMUX_PAD(0x608, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA4__GPIO_1_4 IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA4__KEY_COL6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA5__WEIM_A5 IOMUX_PAD(0x60C, 0x270, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__GPIO_1_5 IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__KEY_ROW6 IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, MX50_KEYPAD_CTRL) + +#define MX50_PAD_EIM_DA6__WEIM_A6 IOMUX_PAD(0x610, 0x274, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA6__GPIO_1_6 IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA6__KEY_COL7 IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA7__WEIM_A7 IOMUX_PAD(0x614, 0x278, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__GPIO_1_7 IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__KEY_ROW7 IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, MX50_KEYPAD_CTRL) + +#define MX50_PAD_EIM_DA8__WEIM_A8 IOMUX_PAD(0x618, 0x27C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA8__GPIO_1_8 IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA8__NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_EIM_DA9__WEIM_A9 IOMUX_PAD(0x61C, 0x280, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA9__GPIO_1_9 IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA9__NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_EIM_DA10__WEIM_A10 IOMUX_PAD(0x620, 0x284, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA10__GPIO_1_10 IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA10__NANDF_CE0 IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_EIM_DA11__WEIM_A11 IOMUX_PAD(0x624, 0x288, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA11__GPIO_1_11 IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA11__NANDF_CE1 IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX50_PAD_EIM_DA12__WEIM_A12 IOMUX_PAD(0x628, 0x28C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA12__GPIO_1_12 IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA12__NANDF_CE2 IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PAD_EIM_DA12__EPDC_SDCE6 IOMUX_PAD(0x628, 0x28C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA13__WEIM_A13 IOMUX_PAD(0x62C, 0x290, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA13__GPIO_1_13 IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA13__NANDF_CE3 IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA13__EPDC_SDCE7 IOMUX_PAD(0x62C, 0x290, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA14__WEIM_A14 IOMUX_PAD(0x630, 0x294, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA14__GPIO_1_14 IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA14__NANDF_READY IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, PAD_CTL_PKE | \ + PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define MX50_PAD_EIM_DA14__EPDC_SDCE8 IOMUX_PAD(0x630, 0x294, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_DA15__WEIM_A15 IOMUX_PAD(0x634, 0x298, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA15__GPIO_1_15 IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PIN_EIM_DA15__NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, PAD_CTL_DSE_HIGH) +#define MX50_PAD_EIM_DA15__EPDC_SDCE9 IOMUX_PAD(0x634, 0x298, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_CS2__WEIM_CS2 IOMUX_PAD(0x638, 0x29C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS2__GPIO_1_16 IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS2__WEIM_A27 IOMUX_PAD(0x638, 0x29C, 2, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_CS1__WEIM_CS1 IOMUX_PAD(0x63C, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS1__GPIO_1_17 IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_CS0__WEIM_CS0 IOMUX_PAD(0x640, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CS0__GPIO_1_18 IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_EB0__WEIM_EB0 IOMUX_PAD(0x644, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB0__GPIO_1_19 IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_EB1__WEIM_EB1 IOMUX_PAD(0x648, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_EB1__GPIO_1_20 IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_WAIT__WEIM_WAIT IOMUX_PAD(0x64C, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_WAIT__GPIO_1_21 IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_BCLK__WEIM_BCLK IOMUX_PAD(0x650, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_BCLK__GPIO_1_22 IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_RDY__WEIM_RDY IOMUX_PAD(0x654, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RDY__GPIO_1_23 IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_OE__WEIM_OE IOMUX_PAD(0x658, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_OE__GPIO_1_24 IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_RW__WEIM_RW IOMUX_PAD(0x65C, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_RW__GPIO_1_25 IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_LBA__WEIM_LBA IOMUX_PAD(0x660, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_LBA__GPIO_1_26 IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EIM_CRE__WEIM_CRE IOMUX_PAD(0x664, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_CRE__GPIO_1_27 IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX50_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index d7a41e9..b6767f9 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -15,373 +15,1553 @@ #include <mach/iomux-v3.h> -/* - * various IOMUX alternate output functions (1-7) - */ -typedef enum iomux_config { - IOMUX_CONFIG_ALT0, - IOMUX_CONFIG_ALT1, - IOMUX_CONFIG_ALT2, - IOMUX_CONFIG_ALT3, - IOMUX_CONFIG_ALT4, - IOMUX_CONFIG_ALT5, - IOMUX_CONFIG_ALT6, - IOMUX_CONFIG_ALT7, - IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ - IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ -} iomux_pin_cfg_t; - /* Pad control groupings */ -#define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_DSE_HIGH) -#define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ - PAD_CTL_SRE_FAST) -#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ - PAD_CTL_SRE_FAST) +#define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_HYS | PAD_CTL_SRE_FAST) #define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) -#define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_PKE | PAD_CTL_HYS) -#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ - PAD_CTL_SRE_FAST) -#define MX51_GPIO_PAD_CTRL_2 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ - PAD_CTL_SRE_FAST) -#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_SRE_FAST | \ - PAD_CTL_DVS) + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS) +#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS) +#define MX51_USBH1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS | PAD_CTL_PUE) +#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) +#define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \ + PAD_CTL_SRE_FAST | PAD_CTL_DVS) +#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) -#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) -#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE) -#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) -#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE) -#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) +#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) +#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) /* * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> + * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num> * See also iomux-v3.h */ -/* PAD MUX ALT INPSE PATH PADCTRL */ -#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D16__GPIO_2_0 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \ - 0x09b4, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_EIM_D17__GPIO_2_1 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D18__GPIO_2_2 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D19__GPIO_2_3 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \ - 0x09b0, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_EIM_D20__GPIO_2_4 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D22__GPIO_2_6 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D23__GPIO_2_7 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, 0x0, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, 0x0, 0, MX51_UART2_PAD_CTRL) -#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, 0x0, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL) -#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL) -#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A16__GPIO_2_10 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A17__GPIO_2_11 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A18__GPIO_2_12 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A19__GPIO_2_13 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A20__GPIO_2_14 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A21__GPIO_2_15 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A23__GPIO_2_17 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A24__GPIO_2_18 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A25__GPIO_2_19 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A26__GPIO_2_20 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A27__GPIO_2_21 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) -#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WE_B__GPIO_3_3 IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RE_B__GPIO_3_4 IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_ALE__GPIO_3_5 IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CLE__GPIO_3_6 IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WP_B__GPIO_3_7 IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4) -#define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4) -#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53C, 0x154, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D11__GPIO_3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D10__GPIO_3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D9__GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D8__GPIO_4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D7__GPIO_4_1 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D6__GPIO_4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D5__GPIO_4_3 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D4__GPIO_4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D3__GPIO_4_5 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D2__GPIO_4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D1__GPIO_4_7 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D0__GPIO_4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D8__GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D9__GPIO_3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x000, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x000, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x000, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D12__GPIO_4_9 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D13__GPIO_4_10 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D14__GPIO_4_11 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D15__GPIO_4_12 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D16__GPIO_4_11 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D17__GPIO_4_12 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D18__GPIO_4_11 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D19__GPIO_4_12 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_VSYNC__GPIO_4_13 IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_HSYNC__GPIO_4_14 IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15 IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_I2C1_CLK__GPIO_4_16 IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) -#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) -#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL) -#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0, 0, MX51_UART1_PAD_CTRL) -#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL) -#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, 0, 0x0, 0, MX51_UART2_PAD_CTRL) -#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL) -#define MX51_PAD_UART3_RXD__GPIO_1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_UART3_TXD__GPIO_1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_OWIRE_LINE__GPIO_1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65C, 0x26C, 2, 0x9f0, 4, MX51_UART3_PAD_CTRL) -#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \ - 0x09b8, 1, MX51_I2C_PAD_CTRL) -#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0, 0, MX51_UART3_PAD_CTRL) -#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \ - 0x09bc, 1, MX51_I2C_PAD_CTRL) -#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x978, 1, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x97c, 1, NO_PAD_CTRL) -#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x980, 1, NO_PAD_CTRL) -#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x98c, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x990, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT6__GPIO_1_19 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT7__GPIO_1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT8__GPIO_1_30 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT9__GPIO_1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) -#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL) -#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 1, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \ - MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ - 0x9b8, 3, MX51_I2C_PAD_CTRL) -#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \ - 0x9bc, 3, MX51_I2C_PAD_CTRL) -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +/* Raw pin modes without pad control */ +/* PAD MUX ALT INPSE PATH PADCTRL */ +#define _MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x5c, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x5c, 7, 0x08d8, 0, 0) +#define _MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x5c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x5c, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x5c, 0x14, 0x09b4, 0, 0) +#define _MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x5c, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x5c, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x60, 7, 0x08d4, 0, 0) +#define _MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x60, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x60, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x60, 3, 0x09ec, 0, 0) +#define _MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x60, 4, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x60, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x64, 7, 0x08e4, 0, 0) +#define _MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x64, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x64, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x64, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x64, 4, 0x09f0, 1, 0) +#define _MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x64, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x68, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x68, 7, 0x08e8, 0, 0) +#define _MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x68, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x68, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x68, 0x14, 0x09b0, 0, 0) +#define _MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x68, 3, 0x09e8, 1, 0) +#define _MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x68, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x6c, 5, 0x08c8, 0, 0) +#define _MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x6c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x6c, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x6c, 4, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x6c, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x70, 5, 0x08c4, 0, 0) +#define _MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x70, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x70, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x70, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x70, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x74, 5, 0x08cc, 0, 0) +#define _MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x74, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x74, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x74, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x78, 5, 0x08d0, 0, 0) +#define _MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x78, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x78, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x78, 4, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x78, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x7c, 5, 0x08f8, 0, 0) +#define _MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x7c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x7c, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x7c, 0x14, 0x09bc, 0, 0) +#define _MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x7c, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x7c, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x80, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x80, 1, 0x09c8, 0, 0) +#define _MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x80, 4, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x80, 3, 0x09f4, 0, 0) +#define _MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x80, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x84, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x84, 1, 0x09cc, 0, 0) +#define _MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x84, 4, 0x09e8, 3, 0) +#define _MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x84, 3, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x84, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x88, 5, 0x08f4, 0, 0) +#define _MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x88, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x88, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x88, 0x14, 0x09b8, 0, 0) +#define _MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x88, 3, 0x09f0, 3, 0) +#define _MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x88, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x8c, 5, 0x08f0, 0, 0) +#define _MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x8c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x8c, 1, 0x09d0, 0, 0) +#define _MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x8c, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x90, 5, 0x08ec, 0, 0) +#define _MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x90, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x90, 1, 0x09d4, 0, 0) +#define _MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x90, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x94, 5, 0x08fc, 0, 0) +#define _MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x94, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x94, 1, 0x09d8, 0, 0) +#define _MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x94, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x98, 5, 0x0900, 0, 0) +#define _MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x98, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x98, 1, 0x09dc, 0, 0) +#define _MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x98, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x9c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x9c, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x9c, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0xa0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0xa0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0xa0, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0xa4, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0xa4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0xa4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0xa8, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0xa8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0xa8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0xac, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0xac, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0xac, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0xb0, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0xb0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0xb0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0xb4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0xb4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0xb8, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0xb8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0xb8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0xbc, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0xbc, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0xbc, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0xc0, 6, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0xc0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0xc0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0xc0, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0xc4, 5, 0x09a0, 0, 0) +#define _MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0xc4, 6, 0x0908, 0, 0) +#define _MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0xc4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0xc4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0xc4, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0xc8, 5, 0x099c, 0, 0) +#define _MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0xc8, 6, 0x09a4, 0, 0) +#define _MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0xc8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0xc8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0xc8, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0xcc, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0xd0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0xd4, 6, 0x08e0, 0, 0) +#define _MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0xd4, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0xd4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0xd4, 3, 0x0954, 0, 0) +#define _MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0xd4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0xd4, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0xd8, 6, 0x08dc, 0, 0) +#define _MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0xd8, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0xd8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0xd8, 3, 0x095c, 0, 0) +#define _MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0xd8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0xd8, 7, 0x0000, 0, 0) +#define _MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0xdc, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0xdc, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0xe0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0xe0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0xe4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0xe4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0xe8, 6, 0x08d8, 1, 0) +#define _MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0xe8, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0xe8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0xe8, 3, 0x0960, 0, 0) +#define _MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0xe8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0xe8, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0xec, 6, 0x08d4, 1, 0) +#define _MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0xec, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0xec, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0xec, 3, 0x0964, 0, 0) +#define _MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0xec, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0xec, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0xf0, 6, 0x08e4, 1, 0) +#define _MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0xf0, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0xf0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0xf0, 3, 0x0970, 0, 0) +#define _MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0xf0, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0xf0, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0xf4, 6, 0x08e8, 1, 0) +#define _MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0xf4, 5, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0xf4, 4, 0x0904, 0, 0) +#define _MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0xf4, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0xf4, 3, 0x0950, 0, 0) +#define _MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0xf4, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0xf4, 2, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0xf8, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0xf8, 1, 0x0000, 0, 0) +#define _MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0xfc, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0xfc, 1, 0x0978, 0, 0) +#define _MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x097c, 0, 0) +#define _MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x0980, 0, 0) +#define _MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x093c, 0, 0) +#define _MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x0984, 0, 0) +#define _MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x0940, 0, 0) +#define _MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x0988, 0, 0) +#define _MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x098c, 0, 0) +#define _MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x0990, 0, 0) +#define _MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x0944, 0, 0) +#define _MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x0930, 0, 0) +#define _MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x0994, 0, 0) +#define _MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x0948, 0, 0) +#define _MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x091c, 0, 0) +#define _MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x09a8, 0, 0) +#define _MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x094c, 0, 0) +#define _MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0x0a20, 0, 0) +#define _MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x0968, 0, 0) +#define _MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x09f8, 0, 0) +#define _MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, 0x0000, 0, 0) +#define _MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x0998, 0, 0) +#define _MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x0914, 0, 0) +#define _MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0x0a24, 0, 0) +#define _MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0x0a1c, 0, 0) +#define _MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x0928, 0, 0) +#define _MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0974, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x0938, 0, 0) +#define _MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x0934, 0, 0) +#define _MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x0930, 1, 0) +#define _MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x096c, 0, 0) +#define _MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x0948, 1, 0) +#define _MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x0944, 1, 0) +#define _MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x0958, 0, 0) +#define _MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x0940, 1, 0) +#define _MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x093c, 1, 0) +#define _MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x09fc, 0, 0) +#define _MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0x0a00, 0, 0) +#define _MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0x0a04, 0, 0) +#define _MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0x0a08, 0, 0) +#define _MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0x0a0c, 0, 0) +#define _MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0x0a10, 0, 0) +#define _MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0x0a14, 0, 0) +#define _MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, 0x0000, 0, 0) +#define _MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0x0a18, 0, 0) +#define _MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x0998, 1, 0) +#define _MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, 0x000, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, 0x000, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, 0x0000, 0, 0) +#define _MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, 0x0000, 0, 0) +#define _MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, 0x0000, 0, 0) +#define _MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x09f4, 2, 0) +#define _MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, 0x0000, 0, 0) +#define _MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x09b4, 1, 0) +#define _MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x08c4, 1, 0) +#define _MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x08cc, 1, 0) +#define _MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x08c8, 1, 0) +#define _MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x08d0, 1, 0) +#define _MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0000, 0, 0) +#define _MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x09b0, 1, 0) +#define _MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x09e4, 0, 0) +#define _MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, 0x0000, 0, 0) +#define _MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, 0x0000, 0, 0) +#define _MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x09e0, 0, 0) +#define _MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0000, 0, 0) +#define _MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, 0x0000, 0, 0) +#define _MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0) +#define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0) +#define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x09ec, 3, 0) +#define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0) +#define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0) +#define _MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x09f4, 4, 0) +#define _MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, 0x0000, 0, 0) +#define _MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0000, 0, 0) +#define _MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, 0x0000, 0, 0) +#define _MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0000, 0, 0) +#define _MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0000, 0, 0) +#define _MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, 0x0000, 0, 0) +#define _MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, 0x0000, 0, 0) +#define _MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x090c, 0, 0) +#define _MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x0910, 0, 0) +#define _MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x09b8, 1, 0) +#define _MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x09f0, 4, 0) +#define _MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x09bc, 1, 0) +#define _MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, 0x0000, 0, 0) +#define _MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x0914, 1, 0) +#define _MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x09b8, 2, 0) +#define _MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x091c, 1, 0) +#define _MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x09bc, 2, 0) +#define _MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x09f4, 6, 0) +#define _MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x0918, 0, 0) +#define _MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0) +#define _MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x09ec, 5, 0) +#define _MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0) +#define _MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x0920, 0, 0) +#define _MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x0928, 1, 0) +#define _MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x0934, 1, 0) +#define _MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, 0x0000, 0, 0) +#define _MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x0978, 1, 0) +#define _MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x097c, 1, 0) +#define _MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x0980, 1, 0) +#define _MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, 0x0000, 0, 0) +#define _MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, 0x0000, 0, 0) +#define _MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x0984, 1, 0) +#define _MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x09a4, 1, 0) +#define _MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x09c4, 0, 0) +#define _MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x0988, 1, 0) +#define _MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x09c4, 1, 0) +#define _MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x098c, 1, 0) +#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x0990, 1, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x0994, 1, 0) +#define _MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x09a8, 1, 0) +#define _MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x09a0, 1, 0) +#define _MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x09c0, 0, 0) +#define _MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x099c, 1, 0) +#define _MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x0950, 1, 0) +#define _MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x0954, 1, 0) +#define _MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x095c, 1, 0) +#define _MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, 0x0000, 0, 0) +#define _MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x09c0, 1, 0) +#define _MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, 0x0000, 0, 0) +#define _MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x0960, 1, 0) +#define _MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x0964, 1, 0) +#define _MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x09c8, 1, 0) +#define _MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x09f4, 8, 0) +#define _MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x09f8, 1, 0) +#define _MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x0970, 1, 0) +#define _MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x09cc, 1, 0) +#define _MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0x0a1c, 1, 0) +#define _MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x09d0, 1, 0) +#define _MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0x0a24, 1, 0) +#define _MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x09d4, 1, 0) +#define _MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0x0a20, 1, 0) +#define _MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x09d8, 1, 0) +#define _MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x09fc, 1, 0) +#define _MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x08f4, 1, 0) +#define _MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0x0a00, 1, 0) +#define _MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x094c, 1, 0) +#define _MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x09dc, 1, 0) +#define _MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0x0a04, 1, 0) +#define _MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x08f0, 1, 0) +#define _MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x0968, 1, 0) +#define _MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0x0a08, 1, 0) +#define _MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x08ec, 1, 0) +#define _MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x096c, 1, 0) +#define _MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0x0a0c, 1, 0) +#define _MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x08fc, 1, 0) +#define _MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x0974, 1, 0) +#define _MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0x0a10, 1, 0) +#define _MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x0900, 1, 0) +#define _MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x0958, 1, 0) +#define _MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0x0a14, 1, 0) +#define _MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x08f8, 1, 0) +#define _MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, 0x0000, 0, 0) +#define _MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0x0a18, 1, 0) +#define _MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x08e0, 1, 0) +#define _MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x091c, 2, 0) +#define _MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x08dc, 1, 0) +#define _MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x0914, 2, 0) +#define _MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x08d8, 2, 0) +#define _MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x0918, 1, 0) +#define _MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x000, 0x01c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x000, 0x020, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x000, 0x024, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x000, 0x028, 0, 0x0000, 0, 0) +#define _MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x08d4, 2, 0) +#define _MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x000, 0x02c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x000, 0x030, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x000, 0x034, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x000, 0x038, 0, 0x0000, 0, 0) +#define _MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x08e4, 2, 0) +#define _MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x000, 0x044, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x000, 0x048, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x000, 0x03c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x000, 0x040, 0, 0x0000, 0, 0) +#define _MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x08e8, 2, 0) +#define _MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x0920, 1, 0) +#define _MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x0924, 0, 0) +#define _MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x0918, 2, 0) +#define _MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x000, 0x04c, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x000, 0x050, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x000, 0x054, 0, 0x0000, 0, 0) +#define _MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x000, 0x058, 0, 0x0000, 0, 0) +#define _MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x000, 0x3b4, 2, 0x091c, 3, 0) +#define _MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x09b0, 2, 0) +#define _MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x0914, 3, 0) +#define _MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x09b4, 2, 0) +#define _MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x0918, 3, 0) +#define _MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x0924, 1, 0) +#define _MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, 0x0000, 0, 0) +#define _MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x09b8, 3, 0) +#define _MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x090c, 1, 0) +#define _MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x09bc, 3, 0) +#define _MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x0910, 1, 0) +#define _MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, 0x0000, 0, 0) +#define _MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, 0x0000, 0, 0) +#define _MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x0908, 1, 0) +#define _MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x0938, 1, 0) +#define _MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x099c, 2, 0) +#define _MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, 0x0000, 0, 0) +#define _MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, 0x0000, 0, 0) + +/* The same pins as above but with the default pad control values applied */ +#define MX51_PAD_EIM_D16__AUD4_RXFS (_MX51_PAD_EIM_D16__AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D16__AUD5_TXD (_MX51_PAD_EIM_D16__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D16__EIM_D16 (_MX51_PAD_EIM_D16__EIM_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D16__GPIO2_0 (_MX51_PAD_EIM_D16__GPIO2_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D16__I2C1_SDA (_MX51_PAD_EIM_D16__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_EIM_D16__UART2_CTS (_MX51_PAD_EIM_D16__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D16__USBH2_DATA0 (_MX51_PAD_EIM_D16__USBH2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D17__AUD5_RXD (_MX51_PAD_EIM_D17__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D17__EIM_D17 (_MX51_PAD_EIM_D17__EIM_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D17__GPIO2_1 (_MX51_PAD_EIM_D17__GPIO2_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D17__UART2_RXD (_MX51_PAD_EIM_D17__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D17__UART3_CTS (_MX51_PAD_EIM_D17__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D17__USBH2_DATA1 (_MX51_PAD_EIM_D17__USBH2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D18__AUD5_TXC (_MX51_PAD_EIM_D18__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D18__EIM_D18 (_MX51_PAD_EIM_D18__EIM_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D18__GPIO2_2 (_MX51_PAD_EIM_D18__GPIO2_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D18__UART2_TXD (_MX51_PAD_EIM_D18__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D18__UART3_RTS (_MX51_PAD_EIM_D18__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D18__USBH2_DATA2 (_MX51_PAD_EIM_D18__USBH2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__AUD4_RXC (_MX51_PAD_EIM_D19__AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__AUD5_TXFS (_MX51_PAD_EIM_D19__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__EIM_D19 (_MX51_PAD_EIM_D19__EIM_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__GPIO2_3 (_MX51_PAD_EIM_D19__GPIO2_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D19__I2C1_SCL (_MX51_PAD_EIM_D19__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_EIM_D19__UART2_RTS (_MX51_PAD_EIM_D19__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D19__USBH2_DATA3 (_MX51_PAD_EIM_D19__USBH2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__AUD4_TXD (_MX51_PAD_EIM_D20__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__EIM_D20 (_MX51_PAD_EIM_D20__EIM_D20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__GPIO2_4 (_MX51_PAD_EIM_D20__GPIO2_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB (_MX51_PAD_EIM_D20__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D20__USBH2_DATA4 (_MX51_PAD_EIM_D20__USBH2_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__AUD4_RXD (_MX51_PAD_EIM_D21__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__EIM_D21 (_MX51_PAD_EIM_D21__EIM_D21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__GPIO2_5 (_MX51_PAD_EIM_D21__GPIO2_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB (_MX51_PAD_EIM_D21__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D21__USBH2_DATA5 (_MX51_PAD_EIM_D21__USBH2_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D22__AUD4_TXC (_MX51_PAD_EIM_D22__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D22__EIM_D22 (_MX51_PAD_EIM_D22__EIM_D22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D22__GPIO2_6 (_MX51_PAD_EIM_D22__GPIO2_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D22__USBH2_DATA6 (_MX51_PAD_EIM_D22__USBH2_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__AUD4_TXFS (_MX51_PAD_EIM_D23__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__EIM_D23 (_MX51_PAD_EIM_D23__EIM_D23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__GPIO2_7 (_MX51_PAD_EIM_D23__GPIO2_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__SPDIF_OUT1 (_MX51_PAD_EIM_D23__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D23__USBH2_DATA7 (_MX51_PAD_EIM_D23__USBH2_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D24__AUD6_RXFS (_MX51_PAD_EIM_D24__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D24__EIM_D24 (_MX51_PAD_EIM_D24__EIM_D24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D24__GPIO2_8 (_MX51_PAD_EIM_D24__GPIO2_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D24__I2C2_SDA (_MX51_PAD_EIM_D24__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_EIM_D24__UART3_CTS (_MX51_PAD_EIM_D24__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D24__USBOTG_DATA0 (_MX51_PAD_EIM_D24__USBOTG_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D25__EIM_D25 (_MX51_PAD_EIM_D25__EIM_D25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D25__KEY_COL6 (_MX51_PAD_EIM_D25__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D25__UART2_CTS (_MX51_PAD_EIM_D25__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D25__UART3_RXD (_MX51_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D25__USBOTG_DATA1 (_MX51_PAD_EIM_D25__USBOTG_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D26__EIM_D26 (_MX51_PAD_EIM_D26__EIM_D26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D26__KEY_COL7 (_MX51_PAD_EIM_D26__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D26__UART2_RTS (_MX51_PAD_EIM_D26__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D26__UART3_TXD (_MX51_PAD_EIM_D26__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D26__USBOTG_DATA2 (_MX51_PAD_EIM_D26__USBOTG_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D27__AUD6_RXC (_MX51_PAD_EIM_D27__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D27__EIM_D27 (_MX51_PAD_EIM_D27__EIM_D27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D27__GPIO2_9 (_MX51_PAD_EIM_D27__GPIO2_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_D27__I2C2_SCL (_MX51_PAD_EIM_D27__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_EIM_D27__UART3_RTS (_MX51_PAD_EIM_D27__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_EIM_D27__USBOTG_DATA3 (_MX51_PAD_EIM_D27__USBOTG_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D28__AUD6_TXD (_MX51_PAD_EIM_D28__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D28__EIM_D28 (_MX51_PAD_EIM_D28__EIM_D28 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D28__KEY_ROW4 (_MX51_PAD_EIM_D28__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D28__USBOTG_DATA4 (_MX51_PAD_EIM_D28__USBOTG_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D29__AUD6_RXD (_MX51_PAD_EIM_D29__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D29__EIM_D29 (_MX51_PAD_EIM_D29__EIM_D29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D29__KEY_ROW5 (_MX51_PAD_EIM_D29__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D29__USBOTG_DATA5 (_MX51_PAD_EIM_D29__USBOTG_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D30__AUD6_TXC (_MX51_PAD_EIM_D30__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D30__EIM_D30 (_MX51_PAD_EIM_D30__EIM_D30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D30__KEY_ROW6 (_MX51_PAD_EIM_D30__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D30__USBOTG_DATA6 (_MX51_PAD_EIM_D30__USBOTG_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D31__AUD6_TXFS (_MX51_PAD_EIM_D31__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D31__EIM_D31 (_MX51_PAD_EIM_D31__EIM_D31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D31__KEY_ROW7 (_MX51_PAD_EIM_D31__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_D31__USBOTG_DATA7 (_MX51_PAD_EIM_D31__USBOTG_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A16__EIM_A16 (_MX51_PAD_EIM_A16__EIM_A16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A16__GPIO2_10 (_MX51_PAD_EIM_A16__GPIO2_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 (_MX51_PAD_EIM_A16__OSC_FREQ_SEL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A17__EIM_A17 (_MX51_PAD_EIM_A17__EIM_A17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A17__GPIO2_11 (_MX51_PAD_EIM_A17__GPIO2_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 (_MX51_PAD_EIM_A17__OSC_FREQ_SEL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A18__BOOT_LPB0 (_MX51_PAD_EIM_A18__BOOT_LPB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A18__EIM_A18 (_MX51_PAD_EIM_A18__EIM_A18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A18__GPIO2_12 (_MX51_PAD_EIM_A18__GPIO2_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A19__BOOT_LPB1 (_MX51_PAD_EIM_A19__BOOT_LPB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A19__EIM_A19 (_MX51_PAD_EIM_A19__EIM_A19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A19__GPIO2_13 (_MX51_PAD_EIM_A19__GPIO2_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 (_MX51_PAD_EIM_A20__BOOT_UART_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A20__EIM_A20 (_MX51_PAD_EIM_A20__EIM_A20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A20__GPIO2_14 (_MX51_PAD_EIM_A20__GPIO2_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 (_MX51_PAD_EIM_A21__BOOT_UART_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A21__EIM_A21 (_MX51_PAD_EIM_A21__EIM_A21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A21__GPIO2_15 (_MX51_PAD_EIM_A21__GPIO2_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A22__EIM_A22 (_MX51_PAD_EIM_A22__EIM_A22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A22__GPIO2_16 (_MX51_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A23__BOOT_HPN_EN (_MX51_PAD_EIM_A23__BOOT_HPN_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A23__EIM_A23 (_MX51_PAD_EIM_A23__EIM_A23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A23__GPIO2_17 (_MX51_PAD_EIM_A23__GPIO2_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A24__EIM_A24 (_MX51_PAD_EIM_A24__EIM_A24 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A24__GPIO2_18 (_MX51_PAD_EIM_A24__GPIO2_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A24__USBH2_CLK (_MX51_PAD_EIM_A24__USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A25__DISP1_PIN4 (_MX51_PAD_EIM_A25__DISP1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A25__EIM_A25 (_MX51_PAD_EIM_A25__EIM_A25 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A25__GPIO2_19 (_MX51_PAD_EIM_A25__GPIO2_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A25__USBH2_DIR (_MX51_PAD_EIM_A25__USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__CSI1_DATA_EN (_MX51_PAD_EIM_A26__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__DISP2_EXT_CLK (_MX51_PAD_EIM_A26__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__EIM_A26 (_MX51_PAD_EIM_A26__EIM_A26 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__GPIO2_20 (_MX51_PAD_EIM_A26__GPIO2_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A26__USBH2_STP (_MX51_PAD_EIM_A26__USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__CSI2_DATA_EN (_MX51_PAD_EIM_A27__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__DISP1_PIN1 (_MX51_PAD_EIM_A27__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__EIM_A27 (_MX51_PAD_EIM_A27__EIM_A27 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__GPIO2_21 (_MX51_PAD_EIM_A27__GPIO2_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_A27__USBH2_NXT (_MX51_PAD_EIM_A27__USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB0__EIM_EB0 (_MX51_PAD_EIM_EB0__EIM_EB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB1__EIM_EB1 (_MX51_PAD_EIM_EB1__EIM_EB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__AUD5_RXFS (_MX51_PAD_EIM_EB2__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__CSI1_D2 (_MX51_PAD_EIM_EB2__CSI1_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__EIM_EB2 (_MX51_PAD_EIM_EB2__EIM_EB2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__FEC_MDIO (_MX51_PAD_EIM_EB2__FEC_MDIO | \ + MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS)) +#define MX51_PAD_EIM_EB2__GPIO2_22 (_MX51_PAD_EIM_EB2__GPIO2_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 (_MX51_PAD_EIM_EB2__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__AUD5_RXC (_MX51_PAD_EIM_EB3__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__CSI1_D3 (_MX51_PAD_EIM_EB3__CSI1_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__EIM_EB3 (_MX51_PAD_EIM_EB3__EIM_EB3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__FEC_RDATA1 (_MX51_PAD_EIM_EB3__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__GPIO2_23 (_MX51_PAD_EIM_EB3__GPIO2_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 (_MX51_PAD_EIM_EB3__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_OE__EIM_OE (_MX51_PAD_EIM_OE__EIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_OE__GPIO2_24 (_MX51_PAD_EIM_OE__GPIO2_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS0__EIM_CS0 (_MX51_PAD_EIM_CS0__EIM_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS0__GPIO2_25 (_MX51_PAD_EIM_CS0__GPIO2_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS1__EIM_CS1 (_MX51_PAD_EIM_CS1__EIM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS1__GPIO2_26 (_MX51_PAD_EIM_CS1__GPIO2_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__AUD5_TXD (_MX51_PAD_EIM_CS2__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__CSI1_D4 (_MX51_PAD_EIM_CS2__CSI1_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__EIM_CS2 (_MX51_PAD_EIM_CS2__EIM_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__FEC_RDATA2 (_MX51_PAD_EIM_CS2__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__GPIO2_27 (_MX51_PAD_EIM_CS2__GPIO2_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS2__USBOTG_STP (_MX51_PAD_EIM_CS2__USBOTG_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__AUD5_RXD (_MX51_PAD_EIM_CS3__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__CSI1_D5 (_MX51_PAD_EIM_CS3__CSI1_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__EIM_CS3 (_MX51_PAD_EIM_CS3__EIM_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__FEC_RDATA3 (_MX51_PAD_EIM_CS3__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__GPIO2_28 (_MX51_PAD_EIM_CS3__GPIO2_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS3__USBOTG_NXT (_MX51_PAD_EIM_CS3__USBOTG_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__AUD5_TXC (_MX51_PAD_EIM_CS4__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__CSI1_D6 (_MX51_PAD_EIM_CS4__CSI1_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__EIM_CS4 (_MX51_PAD_EIM_CS4__EIM_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__FEC_RX_ER (_MX51_PAD_EIM_CS4__FEC_RX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_EIM_CS4__GPIO2_29 (_MX51_PAD_EIM_CS4__GPIO2_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS4__USBOTG_CLK (_MX51_PAD_EIM_CS4__USBOTG_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__AUD5_TXFS (_MX51_PAD_EIM_CS5__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__CSI1_D7 (_MX51_PAD_EIM_CS5__CSI1_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK (_MX51_PAD_EIM_CS5__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__EIM_CS5 (_MX51_PAD_EIM_CS5__EIM_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__FEC_CRS (_MX51_PAD_EIM_CS5__FEC_CRS | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_EIM_CS5__GPIO2_30 (_MX51_PAD_EIM_CS5__GPIO2_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CS5__USBOTG_DIR (_MX51_PAD_EIM_CS5__USBOTG_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DTACK__EIM_DTACK (_MX51_PAD_EIM_DTACK__EIM_DTACK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DTACK__GPIO2_31 (_MX51_PAD_EIM_DTACK__GPIO2_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_LBA__EIM_LBA (_MX51_PAD_EIM_LBA__EIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_LBA__GPIO3_1 (_MX51_PAD_EIM_LBA__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_EIM_CRE__EIM_CRE (_MX51_PAD_EIM_CRE__EIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_CRE__GPIO3_2 (_MX51_PAD_EIM_CRE__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DRAM_CS1__DRAM_CS1 (_MX51_PAD_DRAM_CS1__DRAM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CLE__GPIO3_6 (_MX51_PAD_NANDF_CLE__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CLE__NANDF_CLE (_MX51_PAD_NANDF_CLE__NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CLE__PATA_RESET_B (_MX51_PAD_NANDF_CLE__PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__ECSPI2_RDY (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__GPIO3_9 (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__NANDF_RB1 (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__PATA_IORDY (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_NANDF_RB2__GPIO3_10 (_MX51_PAD_NANDF_RB2__GPIO3_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__NANDF_RB2 (_MX51_PAD_NANDF_RB2__NANDF_RB2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__USBH3_H3_DP (_MX51_PAD_NANDF_RB2__USBH3_H3_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB2__USBH3_NXT (_MX51_PAD_NANDF_RB2__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__DISP1_WAIT (_MX51_PAD_NANDF_RB3__DISP1_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__ECSPI2_MISO (_MX51_PAD_NANDF_RB3__ECSPI2_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__FEC_RX_CLK (_MX51_PAD_NANDF_RB3__FEC_RX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) +#define MX51_PAD_NANDF_RB3__GPIO3_11 (_MX51_PAD_NANDF_RB3__GPIO3_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__NANDF_RB3 (_MX51_PAD_NANDF_RB3__NANDF_RB3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__USBH3_CLK (_MX51_PAD_NANDF_RB3__USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RB3__USBH3_H3_DM (_MX51_PAD_NANDF_RB3__USBH3_H3_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO_NAND__GPIO_NAND (_MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_GPIO_NAND__PATA_INTRQ (_MX51_PAD_GPIO_NAND__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS0__GPIO3_16 (_MX51_PAD_NANDF_CS0__GPIO3_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS0__NANDF_CS0 (_MX51_PAD_NANDF_CS0__NANDF_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS1__GPIO3_17 (_MX51_PAD_NANDF_CS1__GPIO3_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS1__NANDF_CS1 (_MX51_PAD_NANDF_CS1__NANDF_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__CSPI_SCLK (_MX51_PAD_NANDF_CS2__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__FEC_TX_ER (_MX51_PAD_NANDF_CS2__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS2__GPIO3_18 (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__NANDF_CS2 (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__PATA_CS_0 (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS2__USBH3_H1_DP (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__FEC_MDC (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS3__GPIO3_19 (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__NANDF_CS3 (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__PATA_CS_1 (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS3__USBH3_H1_DM (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__FEC_TDATA1 (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS4__GPIO3_20 (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__NANDF_CS4 (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__PATA_DA_0 (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS4__USBH3_STP (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__FEC_TDATA2 (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS5__GPIO3_21 (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__NANDF_CS5 (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__PATA_DA_1 (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS5__USBH3_DIR (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__CSPI_SS3 (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__FEC_TDATA3 (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS6__GPIO3_22 (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__NANDF_CS6 (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__PATA_DA_2 (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS7__FEC_TX_EN (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_CS7__GPIO3_23 (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS7__NANDF_CS7 (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) +#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__PATA_DATA15 (_MX51_PAD_NANDF_D15__PATA_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D15__SD3_DAT7 (_MX51_PAD_NANDF_D15__SD3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__ECSPI2_SS3 (_MX51_PAD_NANDF_D14__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__GPIO3_26 (_MX51_PAD_NANDF_D14__GPIO3_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__NANDF_D14 (_MX51_PAD_NANDF_D14__NANDF_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__PATA_DATA14 (_MX51_PAD_NANDF_D14__PATA_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D14__SD3_DAT6 (_MX51_PAD_NANDF_D14__SD3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__ECSPI2_SS2 (_MX51_PAD_NANDF_D13__ECSPI2_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__GPIO3_27 (_MX51_PAD_NANDF_D13__GPIO3_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__NANDF_D13 (_MX51_PAD_NANDF_D13__NANDF_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__PATA_DATA13 (_MX51_PAD_NANDF_D13__PATA_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D13__SD3_DAT5 (_MX51_PAD_NANDF_D13__SD3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__ECSPI2_SS1 (_MX51_PAD_NANDF_D12__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__GPIO3_28 (_MX51_PAD_NANDF_D12__GPIO3_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__NANDF_D12 (_MX51_PAD_NANDF_D12__NANDF_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__PATA_DATA12 (_MX51_PAD_NANDF_D12__PATA_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D12__SD3_DAT4 (_MX51_PAD_NANDF_D12__SD3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__FEC_RX_DV (_MX51_PAD_NANDF_D11__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__GPIO3_29 (_MX51_PAD_NANDF_D11__GPIO3_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__NANDF_D11 (_MX51_PAD_NANDF_D11__NANDF_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__PATA_DATA11 (_MX51_PAD_NANDF_D11__PATA_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D11__SD3_DATA3 (_MX51_PAD_NANDF_D11__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D10__GPIO3_30 (_MX51_PAD_NANDF_D10__GPIO3_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D10__NANDF_D10 (_MX51_PAD_NANDF_D10__NANDF_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D10__PATA_DATA10 (_MX51_PAD_NANDF_D10__PATA_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D10__SD3_DATA2 (_MX51_PAD_NANDF_D10__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D9__FEC_RDATA0 (_MX51_PAD_NANDF_D9__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) +#define MX51_PAD_NANDF_D9__GPIO3_31 (_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D9__NANDF_D9 (_MX51_PAD_NANDF_D9__NANDF_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D9__PATA_DATA9 (_MX51_PAD_NANDF_D9__PATA_DATA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D9__SD3_DATA1 (_MX51_PAD_NANDF_D9__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D8__FEC_TDATA0 (_MX51_PAD_NANDF_D8__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_NANDF_D8__GPIO4_0 (_MX51_PAD_NANDF_D8__GPIO4_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D8__NANDF_D8 (_MX51_PAD_NANDF_D8__NANDF_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D8__PATA_DATA8 (_MX51_PAD_NANDF_D8__PATA_DATA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D8__SD3_DATA0 (_MX51_PAD_NANDF_D8__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D7__GPIO4_1 (_MX51_PAD_NANDF_D7__GPIO4_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D7__NANDF_D7 (_MX51_PAD_NANDF_D7__NANDF_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D7__PATA_DATA7 (_MX51_PAD_NANDF_D7__PATA_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D7__USBH3_DATA0 (_MX51_PAD_NANDF_D7__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__GPIO4_2 (_MX51_PAD_NANDF_D6__GPIO4_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__NANDF_D6 (_MX51_PAD_NANDF_D6__NANDF_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__PATA_DATA6 (_MX51_PAD_NANDF_D6__PATA_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__SD4_LCTL (_MX51_PAD_NANDF_D6__SD4_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D6__USBH3_DATA1 (_MX51_PAD_NANDF_D6__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__GPIO4_3 (_MX51_PAD_NANDF_D5__GPIO4_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__NANDF_D5 (_MX51_PAD_NANDF_D5__NANDF_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__PATA_DATA5 (_MX51_PAD_NANDF_D5__PATA_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__SD4_WP (_MX51_PAD_NANDF_D5__SD4_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D5__USBH3_DATA2 (_MX51_PAD_NANDF_D5__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__GPIO4_4 (_MX51_PAD_NANDF_D4__GPIO4_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__NANDF_D4 (_MX51_PAD_NANDF_D4__NANDF_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__PATA_DATA4 (_MX51_PAD_NANDF_D4__PATA_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__SD4_CD (_MX51_PAD_NANDF_D4__SD4_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D4__USBH3_DATA3 (_MX51_PAD_NANDF_D4__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__GPIO4_5 (_MX51_PAD_NANDF_D3__GPIO4_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__NANDF_D3 (_MX51_PAD_NANDF_D3__NANDF_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__PATA_DATA3 (_MX51_PAD_NANDF_D3__PATA_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__SD4_DAT4 (_MX51_PAD_NANDF_D3__SD4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D3__USBH3_DATA4 (_MX51_PAD_NANDF_D3__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__GPIO4_6 (_MX51_PAD_NANDF_D2__GPIO4_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__NANDF_D2 (_MX51_PAD_NANDF_D2__NANDF_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__PATA_DATA2 (_MX51_PAD_NANDF_D2__PATA_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__SD4_DAT5 (_MX51_PAD_NANDF_D2__SD4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D2__USBH3_DATA5 (_MX51_PAD_NANDF_D2__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__GPIO4_7 (_MX51_PAD_NANDF_D1__GPIO4_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__NANDF_D1 (_MX51_PAD_NANDF_D1__NANDF_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__PATA_DATA1 (_MX51_PAD_NANDF_D1__PATA_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__SD4_DAT6 (_MX51_PAD_NANDF_D1__SD4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D1__USBH3_DATA6 (_MX51_PAD_NANDF_D1__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__GPIO4_8 (_MX51_PAD_NANDF_D0__GPIO4_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__NANDF_D0 (_MX51_PAD_NANDF_D0__NANDF_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__PATA_DATA0 (_MX51_PAD_NANDF_D0__PATA_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__SD4_DAT7 (_MX51_PAD_NANDF_D0__SD4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_NANDF_D0__USBH3_DATA7 (_MX51_PAD_NANDF_D0__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D8__CSI1_D8 (_MX51_PAD_CSI1_D8__CSI1_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D8__GPIO3_12 (_MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI1_D9__CSI1_D9 (_MX51_PAD_CSI1_D9__CSI1_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D9__GPIO3_13 (_MX51_PAD_CSI1_D9__GPIO3_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI1_D10__CSI1_D10 (_MX51_PAD_CSI1_D10__CSI1_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D11__CSI1_D11 (_MX51_PAD_CSI1_D11__CSI1_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D12__CSI1_D12 (_MX51_PAD_CSI1_D12__CSI1_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D13__CSI1_D13 (_MX51_PAD_CSI1_D13__CSI1_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D14__CSI1_D14 (_MX51_PAD_CSI1_D14__CSI1_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D15__CSI1_D15 (_MX51_PAD_CSI1_D15__CSI1_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D16__CSI1_D16 (_MX51_PAD_CSI1_D16__CSI1_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D17__CSI1_D17 (_MX51_PAD_CSI1_D17__CSI1_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D18__CSI1_D18 (_MX51_PAD_CSI1_D18__CSI1_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_D19__CSI1_D19 (_MX51_PAD_CSI1_D19__CSI1_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC (_MX51_PAD_CSI1_VSYNC__CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_VSYNC__GPIO3_14 (_MX51_PAD_CSI1_VSYNC__GPIO3_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC (_MX51_PAD_CSI1_HSYNC__CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_HSYNC__GPIO3_15 (_MX51_PAD_CSI1_HSYNC__GPIO3_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK (_MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI1_MCLK__CSI1_MCLK (_MX51_PAD_CSI1_MCLK__CSI1_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D12__CSI2_D12 (_MX51_PAD_CSI2_D12__CSI2_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D12__GPIO4_9 (_MX51_PAD_CSI2_D12__GPIO4_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_D13__CSI2_D13 (_MX51_PAD_CSI2_D13__CSI2_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D13__GPIO4_10 (_MX51_PAD_CSI2_D13__GPIO4_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_D14__CSI2_D14 (_MX51_PAD_CSI2_D14__CSI2_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D15__CSI2_D15 (_MX51_PAD_CSI2_D15__CSI2_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D16__CSI2_D16 (_MX51_PAD_CSI2_D16__CSI2_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D17__CSI2_D17 (_MX51_PAD_CSI2_D17__CSI2_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D18__CSI2_D18 (_MX51_PAD_CSI2_D18__CSI2_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D18__GPIO4_11 (_MX51_PAD_CSI2_D18__GPIO4_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_D19__CSI2_D19 (_MX51_PAD_CSI2_D19__CSI2_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_D19__GPIO4_12 (_MX51_PAD_CSI2_D19__GPIO4_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC (_MX51_PAD_CSI2_VSYNC__CSI2_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_VSYNC__GPIO4_13 (_MX51_PAD_CSI2_VSYNC__GPIO4_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC (_MX51_PAD_CSI2_HSYNC__CSI2_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_HSYNC__GPIO4_14 (_MX51_PAD_CSI2_HSYNC__GPIO4_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK (_MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 (_MX51_PAD_CSI2_PIXCLK__GPIO4_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_I2C1_CLK__GPIO4_16 (_MX51_PAD_I2C1_CLK__GPIO4_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_I2C1_CLK__I2C1_CLK (_MX51_PAD_I2C1_CLK__I2C1_CLK | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_I2C1_DAT__GPIO4_17 (_MX51_PAD_I2C1_DAT__GPIO4_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_I2C1_DAT__I2C1_DAT (_MX51_PAD_I2C1_DAT__I2C1_DAT | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD (_MX51_PAD_AUD3_BB_TXD__AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 (_MX51_PAD_AUD3_BB_TXD__GPIO4_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD (_MX51_PAD_AUD3_BB_RXD__AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 (_MX51_PAD_AUD3_BB_RXD__GPIO4_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_RXD__UART3_RXD (_MX51_PAD_AUD3_BB_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_CK__AUD3_TXC (_MX51_PAD_AUD3_BB_CK__AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_CK__GPIO4_20 (_MX51_PAD_AUD3_BB_CK__GPIO4_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS (_MX51_PAD_AUD3_BB_FS__AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_FS__GPIO4_21 (_MX51_PAD_AUD3_BB_FS__GPIO4_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_AUD3_BB_FS__UART3_TXD (_MX51_PAD_AUD3_BB_FS__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI (_MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_MOSI__GPIO4_22 (_MX51_PAD_CSPI1_MOSI__GPIO4_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_MOSI__I2C1_SDA (_MX51_PAD_CSPI1_MOSI__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_CSPI1_MISO__AUD4_RXD (_MX51_PAD_CSPI1_MISO__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO (_MX51_PAD_CSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_MISO__GPIO4_23 (_MX51_PAD_CSPI1_MISO__GPIO4_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS0__AUD4_TXC (_MX51_PAD_CSPI1_SS0__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 (_MX51_PAD_CSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS0__GPIO4_24 (_MX51_PAD_CSPI1_SS0__GPIO4_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS1__AUD4_TXD (_MX51_PAD_CSPI1_SS1__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 (_MX51_PAD_CSPI1_SS1__ECSPI1_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_SS1__GPIO4_25 (_MX51_PAD_CSPI1_SS1__GPIO4_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_RDY__AUD4_TXFS (_MX51_PAD_CSPI1_RDY__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY (_MX51_PAD_CSPI1_RDY__ECSPI1_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_RDY__GPIO4_26 (_MX51_PAD_CSPI1_RDY__GPIO4_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK (_MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_CSPI1_SCLK__GPIO4_27 (_MX51_PAD_CSPI1_SCLK__GPIO4_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_CSPI1_SCLK__I2C1_SCL (_MX51_PAD_CSPI1_SCLK__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_UART1_RXD__GPIO4_28 (_MX51_PAD_UART1_RXD__GPIO4_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART1_RXD__UART1_RXD (_MX51_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART1_TXD__GPIO4_29 (_MX51_PAD_UART1_TXD__GPIO4_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART1_TXD__PWM2_PWMO (_MX51_PAD_UART1_TXD__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART1_TXD__UART1_TXD (_MX51_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART1_RTS__GPIO4_30 (_MX51_PAD_UART1_RTS__GPIO4_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART1_RTS__UART1_RTS (_MX51_PAD_UART1_RTS__UART1_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART1_CTS__GPIO4_31 (_MX51_PAD_UART1_CTS__GPIO4_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART1_CTS__UART1_CTS (_MX51_PAD_UART1_CTS__UART1_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART2_RXD__FIRI_TXD (_MX51_PAD_UART2_RXD__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART2_RXD__GPIO1_20 (_MX51_PAD_UART2_RXD__GPIO1_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART2_RXD__UART2_RXD (_MX51_PAD_UART2_RXD__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART2_TXD__FIRI_RXD (_MX51_PAD_UART2_TXD__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART2_TXD__GPIO1_21 (_MX51_PAD_UART2_TXD__GPIO1_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART2_TXD__UART2_TXD (_MX51_PAD_UART2_TXD__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART3_RXD__CSI1_D0 (_MX51_PAD_UART3_RXD__CSI1_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART3_RXD__GPIO1_22 (_MX51_PAD_UART3_RXD__GPIO1_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART3_RXD__UART1_DTR (_MX51_PAD_UART3_RXD__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART3_RXD__UART3_RXD (_MX51_PAD_UART3_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART3_TXD__CSI1_D1 (_MX51_PAD_UART3_TXD__CSI1_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_UART3_TXD__GPIO1_23 (_MX51_PAD_UART3_TXD__GPIO1_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_UART3_TXD__UART1_DSR (_MX51_PAD_UART3_TXD__UART1_DSR | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_UART3_TXD__UART3_TXD (_MX51_PAD_UART3_TXD__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_OWIRE_LINE__GPIO1_24 (_MX51_PAD_OWIRE_LINE__GPIO1_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_OWIRE_LINE__OWIRE_LINE (_MX51_PAD_OWIRE_LINE__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_OWIRE_LINE__SPDIF_OUT (_MX51_PAD_OWIRE_LINE__SPDIF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_ROW0__KEY_ROW0 (_MX51_PAD_KEY_ROW0__KEY_ROW0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_ROW1__KEY_ROW1 (_MX51_PAD_KEY_ROW1__KEY_ROW1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_ROW2__KEY_ROW2 (_MX51_PAD_KEY_ROW2__KEY_ROW2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_ROW3__KEY_ROW3 (_MX51_PAD_KEY_ROW3__KEY_ROW3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL0__KEY_COL0 (_MX51_PAD_KEY_COL0__KEY_COL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL0__PLL1_BYP (_MX51_PAD_KEY_COL0__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL1__KEY_COL1 (_MX51_PAD_KEY_COL1__KEY_COL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL1__PLL2_BYP (_MX51_PAD_KEY_COL1__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL2__KEY_COL2 (_MX51_PAD_KEY_COL2__KEY_COL2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL2__PLL3_BYP (_MX51_PAD_KEY_COL2__PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL3__KEY_COL3 (_MX51_PAD_KEY_COL3__KEY_COL3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__I2C2_SCL (_MX51_PAD_KEY_COL4__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__KEY_COL4 (_MX51_PAD_KEY_COL4__KEY_COL4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__SPDIF_OUT1 (_MX51_PAD_KEY_COL4__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__UART1_RI (_MX51_PAD_KEY_COL4__UART1_RI | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_KEY_COL4__UART3_RTS (_MX51_PAD_KEY_COL4__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_KEY_COL5__I2C2_SDA (_MX51_PAD_KEY_COL5__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_KEY_COL5__KEY_COL5 (_MX51_PAD_KEY_COL5__KEY_COL5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_KEY_COL5__UART1_DCD (_MX51_PAD_KEY_COL5__UART1_DCD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_KEY_COL5__UART3_CTS (_MX51_PAD_KEY_COL5__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_CLK__CSPI_SCLK (_MX51_PAD_USBH1_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_CLK__GPIO1_25 (_MX51_PAD_USBH1_CLK__GPIO1_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_CLK__I2C2_SCL (_MX51_PAD_USBH1_CLK__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_USBH1_CLK__USBH1_CLK (_MX51_PAD_USBH1_CLK__USBH1_CLK | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DIR__CSPI_MOSI (_MX51_PAD_USBH1_DIR__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DIR__GPIO1_26 (_MX51_PAD_USBH1_DIR__GPIO1_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DIR__I2C2_SDA (_MX51_PAD_USBH1_DIR__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_USBH1_DIR__USBH1_DIR (_MX51_PAD_USBH1_DIR__USBH1_DIR | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_STP__CSPI_RDY (_MX51_PAD_USBH1_STP__CSPI_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_STP__GPIO1_27 (_MX51_PAD_USBH1_STP__GPIO1_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_STP__UART3_RXD (_MX51_PAD_USBH1_STP__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_STP__USBH1_STP (_MX51_PAD_USBH1_STP__USBH1_STP | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_NXT__CSPI_MISO (_MX51_PAD_USBH1_NXT__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_NXT__GPIO1_28 (_MX51_PAD_USBH1_NXT__GPIO1_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_NXT__UART3_TXD (_MX51_PAD_USBH1_NXT__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_NXT__USBH1_NXT (_MX51_PAD_USBH1_NXT__USBH1_NXT | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA0__GPIO1_11 (_MX51_PAD_USBH1_DATA0__GPIO1_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA0__UART2_CTS (_MX51_PAD_USBH1_DATA0__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 (_MX51_PAD_USBH1_DATA0__USBH1_DATA0 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA1__GPIO1_12 (_MX51_PAD_USBH1_DATA1__GPIO1_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA1__UART2_RXD (_MX51_PAD_USBH1_DATA1__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 (_MX51_PAD_USBH1_DATA1__USBH1_DATA1 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA2__GPIO1_13 (_MX51_PAD_USBH1_DATA2__GPIO1_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA2__UART2_TXD (_MX51_PAD_USBH1_DATA2__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 (_MX51_PAD_USBH1_DATA2__USBH1_DATA2 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA3__GPIO1_14 (_MX51_PAD_USBH1_DATA3__GPIO1_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA3__UART2_RTS (_MX51_PAD_USBH1_DATA3__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 (_MX51_PAD_USBH1_DATA3__USBH1_DATA3 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA4__CSPI_SS0 (_MX51_PAD_USBH1_DATA4__CSPI_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA4__GPIO1_15 (_MX51_PAD_USBH1_DATA4__GPIO1_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 (_MX51_PAD_USBH1_DATA4__USBH1_DATA4 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA5__CSPI_SS1 (_MX51_PAD_USBH1_DATA5__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA5__GPIO1_16 (_MX51_PAD_USBH1_DATA5__GPIO1_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 (_MX51_PAD_USBH1_DATA5__USBH1_DATA5 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA6__CSPI_SS3 (_MX51_PAD_USBH1_DATA6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA6__GPIO1_17 (_MX51_PAD_USBH1_DATA6__GPIO1_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 (_MX51_PAD_USBH1_DATA6__USBH1_DATA6 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI1_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA7__GPIO1_18 (_MX51_PAD_USBH1_DATA7__GPIO1_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 (_MX51_PAD_USBH1_DATA7__USBH1_DATA7 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) +#define MX51_PAD_DI1_PIN11__DI1_PIN11 (_MX51_PAD_DI1_PIN11__DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 (_MX51_PAD_DI1_PIN11__ECSPI1_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_DI1_PIN11__GPIO3_0 (_MX51_PAD_DI1_PIN11__GPIO3_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN12__DI1_PIN12 (_MX51_PAD_DI1_PIN12__DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN12__GPIO3_1 (_MX51_PAD_DI1_PIN12__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN13__DI1_PIN13 (_MX51_PAD_DI1_PIN13__DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN13__GPIO3_2 (_MX51_PAD_DI1_PIN13__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_D0_CS__DI1_D0_CS (_MX51_PAD_DI1_D0_CS__DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_D0_CS__GPIO3_3 (_MX51_PAD_DI1_D0_CS__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DI1_D1_CS__DI1_D1_CS (_MX51_PAD_DI1_D1_CS__DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 (_MX51_PAD_DI1_D1_CS__DISP1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 (_MX51_PAD_DI1_D1_CS__DISP1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_D1_CS__GPIO3_4 (_MX51_PAD_DI1_D1_CS__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 (_MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN (_MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 (_MX51_PAD_DISPB2_SER_DIN__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 (_MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO (_MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 (_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK (_MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 (_MX51_PAD_DISPB2_SER_CLK__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK (_MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 (_MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 (_MX51_PAD_DISP1_DAT0__DISP1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 (_MX51_PAD_DISP1_DAT1__DISP1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 (_MX51_PAD_DISP1_DAT2__DISP1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 (_MX51_PAD_DISP1_DAT3__DISP1_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 (_MX51_PAD_DISP1_DAT4__DISP1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 (_MX51_PAD_DISP1_DAT5__DISP1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC (_MX51_PAD_DISP1_DAT6__BOOT_USB_SRC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 (_MX51_PAD_DISP1_DAT6__DISP1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG (_MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 (_MX51_PAD_DISP1_DAT7__DISP1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 (_MX51_PAD_DISP1_DAT8__BOOT_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 (_MX51_PAD_DISP1_DAT8__DISP1_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 (_MX51_PAD_DISP1_DAT9__BOOT_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 (_MX51_PAD_DISP1_DAT9__DISP1_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE (_MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 (_MX51_PAD_DISP1_DAT10__DISP1_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 (_MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 (_MX51_PAD_DISP1_DAT11__DISP1_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL (_MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 (_MX51_PAD_DISP1_DAT12__DISP1_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 (_MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 (_MX51_PAD_DISP1_DAT13__DISP1_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 (_MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 (_MX51_PAD_DISP1_DAT14__DISP1_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH (_MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 (_MX51_PAD_DISP1_DAT15__DISP1_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 (_MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 (_MX51_PAD_DISP1_DAT16__DISP1_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 (_MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 (_MX51_PAD_DISP1_DAT17__DISP1_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 (_MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 (_MX51_PAD_DISP1_DAT18__DISP1_DAT18 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 (_MX51_PAD_DISP1_DAT18__DISP2_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 (_MX51_PAD_DISP1_DAT18__DISP2_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 (_MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 (_MX51_PAD_DISP1_DAT19__DISP1_DAT19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 (_MX51_PAD_DISP1_DAT19__DISP2_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 (_MX51_PAD_DISP1_DAT19__DISP2_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 (_MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 (_MX51_PAD_DISP1_DAT20__DISP1_DAT20 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 (_MX51_PAD_DISP1_DAT20__DISP2_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 (_MX51_PAD_DISP1_DAT20__DISP2_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 (_MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 (_MX51_PAD_DISP1_DAT21__DISP1_DAT21 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 (_MX51_PAD_DISP1_DAT21__DISP2_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 (_MX51_PAD_DISP1_DAT21__DISP2_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 (_MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 (_MX51_PAD_DISP1_DAT22__DISP1_DAT22 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS (_MX51_PAD_DISP1_DAT22__DISP2_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 (_MX51_PAD_DISP1_DAT22__DISP2_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 (_MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 (_MX51_PAD_DISP1_DAT23__DISP1_DAT23 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS (_MX51_PAD_DISP1_DAT23__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 (_MX51_PAD_DISP1_DAT23__DISP2_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS (_MX51_PAD_DISP1_DAT23__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN3__DI1_PIN3 (_MX51_PAD_DI1_PIN3__DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI1_PIN2__DI1_PIN2 (_MX51_PAD_DI1_PIN2__DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP2__DISP1_SER_CLK (_MX51_PAD_DI_GP2__DISP1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP2__DISP2_WAIT (_MX51_PAD_DI_GP2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP3__CSI1_DATA_EN (_MX51_PAD_DI_GP3__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP3__DISP1_SER_DIO (_MX51_PAD_DI_GP3__DISP1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP3__FEC_TX_ER (_MX51_PAD_DI_GP3__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN (_MX51_PAD_DI2_PIN4__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN4__DI2_PIN4 (_MX51_PAD_DI2_PIN4__DI2_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN4__FEC_CRS (_MX51_PAD_DI2_PIN4__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN2__DI2_PIN2 (_MX51_PAD_DI2_PIN2__DI2_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN2__FEC_MDC (_MX51_PAD_DI2_PIN2__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DI2_PIN3__DI2_PIN3 (_MX51_PAD_DI2_PIN3__DI2_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_PIN3__FEC_MDIO (_MX51_PAD_DI2_PIN3__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK (_MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 (_MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP4__DI2_PIN15 (_MX51_PAD_DI_GP4__DI2_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP4__DISP1_SER_DIN (_MX51_PAD_DI_GP4__DISP1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP4__DISP2_PIN1 (_MX51_PAD_DI_GP4__DISP2_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DI_GP4__FEC_RDATA2 (_MX51_PAD_DI_GP4__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 (_MX51_PAD_DISP2_DAT0__DISP2_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 (_MX51_PAD_DISP2_DAT0__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__KEY_COL6 (_MX51_PAD_DISP2_DAT0__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__UART3_RXD (_MX51_PAD_DISP2_DAT0__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT0__USBH3_CLK (_MX51_PAD_DISP2_DAT0__USBH3_CLK | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 (_MX51_PAD_DISP2_DAT1__DISP2_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__FEC_RX_ER (_MX51_PAD_DISP2_DAT1__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__KEY_COL7 (_MX51_PAD_DISP2_DAT1__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__UART3_TXD (_MX51_PAD_DISP2_DAT1__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT1__USBH3_DIR (_MX51_PAD_DISP2_DAT1__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 (_MX51_PAD_DISP2_DAT2__DISP2_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 (_MX51_PAD_DISP2_DAT3__DISP2_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 (_MX51_PAD_DISP2_DAT4__DISP2_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 (_MX51_PAD_DISP2_DAT5__DISP2_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 (_MX51_PAD_DISP2_DAT6__DISP2_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 (_MX51_PAD_DISP2_DAT6__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT6__GPIO1_19 (_MX51_PAD_DISP2_DAT6__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT6__KEY_ROW4 (_MX51_PAD_DISP2_DAT6__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT6__USBH3_STP (_MX51_PAD_DISP2_DAT6__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 (_MX51_PAD_DISP2_DAT7__DISP2_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 (_MX51_PAD_DISP2_DAT7__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT7__GPIO1_29 (_MX51_PAD_DISP2_DAT7__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT7__KEY_ROW5 (_MX51_PAD_DISP2_DAT7__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT7__USBH3_NXT (_MX51_PAD_DISP2_DAT7__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 (_MX51_PAD_DISP2_DAT8__DISP2_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 (_MX51_PAD_DISP2_DAT8__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT8__GPIO1_30 (_MX51_PAD_DISP2_DAT8__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT8__KEY_ROW6 (_MX51_PAD_DISP2_DAT8__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 (_MX51_PAD_DISP2_DAT8__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT9__AUD6_RXC (_MX51_PAD_DISP2_DAT9__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 (_MX51_PAD_DISP2_DAT9__DISP2_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT9__FEC_TX_EN (_MX51_PAD_DISP2_DAT9__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT9__GPIO1_31 (_MX51_PAD_DISP2_DAT9__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 (_MX51_PAD_DISP2_DAT9__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 (_MX51_PAD_DISP2_DAT10__DISP2_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS (_MX51_PAD_DISP2_DAT10__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__FEC_COL (_MX51_PAD_DISP2_DAT10__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__KEY_ROW7 (_MX51_PAD_DISP2_DAT10__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 (_MX51_PAD_DISP2_DAT10__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__AUD6_TXD (_MX51_PAD_DISP2_DAT11__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 (_MX51_PAD_DISP2_DAT11__DISP2_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK (_MX51_PAD_DISP2_DAT11__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__GPIO1_10 (_MX51_PAD_DISP2_DAT11__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 (_MX51_PAD_DISP2_DAT11__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT12__AUD6_RXD (_MX51_PAD_DISP2_DAT12__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 (_MX51_PAD_DISP2_DAT12__DISP2_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT12__FEC_RX_DV (_MX51_PAD_DISP2_DAT12__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 (_MX51_PAD_DISP2_DAT12__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT13__AUD6_TXC (_MX51_PAD_DISP2_DAT13__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 (_MX51_PAD_DISP2_DAT13__DISP2_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK (_MX51_PAD_DISP2_DAT13__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) +#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 (_MX51_PAD_DISP2_DAT13__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT14__AUD6_TXFS (_MX51_PAD_DISP2_DAT14__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 (_MX51_PAD_DISP2_DAT14__DISP2_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 (_MX51_PAD_DISP2_DAT14__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) +#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 (_MX51_PAD_DISP2_DAT14__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT15__AUD6_RXFS (_MX51_PAD_DISP2_DAT15__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS (_MX51_PAD_DISP2_DAT15__DISP1_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 (_MX51_PAD_DISP2_DAT15__DISP2_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 (_MX51_PAD_DISP2_DAT15__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) +#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 (_MX51_PAD_DISP2_DAT15__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CMD__AUD5_RXFS (_MX51_PAD_SD1_CMD__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CMD__CSPI_MOSI (_MX51_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CMD__SD1_CMD (_MX51_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_SD1_CLK__AUD5_RXC (_MX51_PAD_SD1_CLK__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CLK__CSPI_SCLK (_MX51_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_CLK__SD1_CLK (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) +#define MX51_PAD_SD1_DATA0__AUD5_TXD (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA0__CSPI_MISO (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA0__EIM_DA0 (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA1__EIM_DA1 (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA2__EIM_DA2 (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA3__EIM_DA3 (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA1__AUD5_RXD (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA4__EIM_DA4 (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA5__EIM_DA5 (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA6__EIM_DA6 (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA7__EIM_DA7 (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA2__AUD5_TXC (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA10__EIM_DA10 (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA11__EIM_DA11 (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA8__EIM_DA8 (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA9__EIM_DA9 (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA3__AUD5_TXFS (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) +#define MX51_PAD_GPIO1_1__CSPI_MISO (_MX51_PAD_GPIO1_1__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_GPIO1_1__GPIO1_1 (_MX51_PAD_GPIO1_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_1__SD1_WP (_MX51_PAD_GPIO1_1__SD1_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) +#define MX51_PAD_EIM_DA12__EIM_DA12 (_MX51_PAD_EIM_DA12__EIM_DA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA13__EIM_DA13 (_MX51_PAD_EIM_DA13__EIM_DA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA14__EIM_DA14 (_MX51_PAD_EIM_DA14__EIM_DA14 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_EIM_DA15__EIM_DA15 (_MX51_PAD_EIM_DA15__EIM_DA15 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_CMD__CSPI_MOSI (_MX51_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD2_CMD__I2C1_SCL (_MX51_PAD_SD2_CMD__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_SD2_CMD__SD2_CMD (_MX51_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) +#define MX51_PAD_SD2_CLK__CSPI_SCLK (_MX51_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD2_CLK__I2C1_SDA (_MX51_PAD_SD2_CLK__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_SD2_CLK__SD2_CLK (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) +#define MX51_PAD_SD2_DATA0__CSPI_MISO (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD2_DATA0__SD1_DAT4 (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA1__SD1_DAT5 (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA1__USBH3_H2_DP (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA2__SD1_DAT6 (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA2__USBH3_H2_DM (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA3__CSPI_SS2 (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) +#define MX51_PAD_SD2_DATA3__SD1_DAT7 (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__CCM_OUT_2 (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__GPIO1_2 (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__PLL1_BYP (_MX51_PAD_GPIO1_2__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_2__PWM1_PWMO (_MX51_PAD_GPIO1_2__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_3__GPIO1_3 (_MX51_PAD_GPIO1_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_3__I2C2_SDA (_MX51_PAD_GPIO1_3__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) +#define MX51_PAD_GPIO1_3__PLL2_BYP (_MX51_PAD_GPIO1_3__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_3__PWM2_PWMO (_MX51_PAD_GPIO1_3__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ (_MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B (_MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK (_MX51_PAD_GPIO1_4__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_4__EIM_RDY (_MX51_PAD_GPIO1_4__EIM_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_4__GPIO1_4 (_MX51_PAD_GPIO1_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B (_MX51_PAD_GPIO1_4__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_5__CSI2_MCLK (_MX51_PAD_GPIO1_5__CSI2_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_5__DISP2_PIN16 (_MX51_PAD_GPIO1_5__DISP2_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_5__GPIO1_5 (_MX51_PAD_GPIO1_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B (_MX51_PAD_GPIO1_5__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_6__DISP2_PIN17 (_MX51_PAD_GPIO1_6__DISP2_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_6__GPIO1_6 (_MX51_PAD_GPIO1_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_6__REF_EN_B (_MX51_PAD_GPIO1_6__REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_7__CCM_OUT_0 (_MX51_PAD_GPIO1_7__CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_7__GPIO1_7 (_MX51_PAD_GPIO1_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_7__SD2_WP (_MX51_PAD_GPIO1_7__SD2_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) +#define MX51_PAD_GPIO1_7__SPDIF_OUT1 (_MX51_PAD_GPIO1_7__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_8__CSI2_DATA_EN (_MX51_PAD_GPIO1_8__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_8__GPIO1_8 (_MX51_PAD_GPIO1_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_8__SD2_CD (_MX51_PAD_GPIO1_8__SD2_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) +#define MX51_PAD_GPIO1_8__USBH3_PWR (_MX51_PAD_GPIO1_8__USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__CCM_OUT_1 (_MX51_PAD_GPIO1_9__CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__DISP2_D1_CS (_MX51_PAD_GPIO1_9__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__DISP2_SER_CS (_MX51_PAD_GPIO1_9__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__GPIO1_9 (_MX51_PAD_GPIO1_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__SD2_LCTL (_MX51_PAD_GPIO1_9__SD2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX51_PAD_GPIO1_9__USBH3_OC (_MX51_PAD_GPIO1_9__USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) #endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h new file mode 100644 index 0000000..5deee01 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -0,0 +1,323 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc.. + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX53_H__ +#define __MACH_IOMUX_MX53_H__ + +#include <mach/iomux-v3.h> + +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +/* These 2 defines are for pins that may not have a mux register, but could + * have a pad setting register, and vice-versa. */ +#define NON_MUX_I 0x00 +#define NON_PAD_I 0x00 + +#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +/* UART1 */ +#define MX53_PAD_CSI0_D10__UART1_TXD IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_D11__UART1_RXD IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DIOW__UART1_TXD IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DMACK__UART1_RXD IOMUX_PAD(0x5F4, 0x274, 3, 0x880, 3, MX53_UART_PAD_CTRL) + +/* UART2 */ +#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DMARQ__UART2_TXD IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, MX53_UART_PAD_CTRL) + +/* UART3 */ +#define MX53_PAD_ATA_CS_0__UART3_TXD IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_CS_1__UART3_RXD IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL) + +#define MX53_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x348, 0x20,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x34C, 0x24,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x350, 0x28,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x354, 0x2C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x358, 0x30,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x35C, 0x34,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x360, 0x38,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x364, 0x3C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x368, 0x40,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x36C, 0x44,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x370, 0x48,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD IOMUX_PAD(0x374, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x378, 0x4C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x37C, 0x50,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x380, 0x54,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x384, 0x58,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x388, 0x5C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x38C, 0x60,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x390, 0x64,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x394, 0x68,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x398, 0x6C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x39C, 0x70,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x3A0, 0x74,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x3A4, 0x78,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x3A8, 0x7C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x3AC, 0x80,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x3B0, 0x84,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x3B8, 0x8C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x3BC, 0x90,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x3C0, 0x94,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x3C4, 0x98,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x3C8, 0x9C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x3F0, 0xC4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x3F4, 0xC8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x3F8, 0xCC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D4__GPIO_5_22 IOMUX_PAD(0x3FC, 0xD0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D5__GPIO_5_23 IOMUX_PAD(0x400, 0xD4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D6__GPIO_5_24 IOMUX_PAD(0x404, 0xD8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D7__GPIO_5_25 IOMUX_PAD(0x408, 0xDC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D8__GPIO_5_26 IOMUX_PAD(0x40C, 0xE0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D9__GPIO_5_27 IOMUX_PAD(0x410, 0xE4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D10__GPIO_5_28 IOMUX_PAD(0x414, 0xE8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D11__GPIO_5_29 IOMUX_PAD(0x418, 0xEC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D12__GPIO_5_30 IOMUX_PAD(0x41C, 0xF0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D13__GPIO_5_31 IOMUX_PAD(0x420, 0xF4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D14__GPIO_6_0 IOMUX_PAD(0x424, 0xF8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D15__GPIO_6_1 IOMUX_PAD(0x428, 0xFC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D16__GPIO_6_2 IOMUX_PAD(0x42C, 0x100,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D17__GPIO_6_3 IOMUX_PAD(0x430, 0x104,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D18__GPIO_6_4 IOMUX_PAD(0x434, 0x108,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D19__GPIO_6_5 IOMUX_PAD(0x438, 0x10C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_CSI0__NVCC_CSI0 IOMUX_PAD(0x43C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TMS__JTAG_TMS IOMUX_PAD(0x440, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_MOD__JTAG_MOD IOMUX_PAD(0x444, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TDI__JTAG_TDI IOMUX_PAD(0x44C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TCK__JTAG_TCK IOMUX_PAD(0x450, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TDO__JTAG_TDO IOMUX_PAD(0x454, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x458, 0x110,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x45C, 0x114,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x478, 0x130,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x47C, 0x134,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x480, 0x138,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x484, 0x13C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x488, 0x140,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x48C, 0x144,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x490, 0x148,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x494, 0x14C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x498, 0x150,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x49C, 0x154,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x4A0, 0x158,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM1__NVCC_EIM1 IOMUX_PAD(0x4A4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x4AC, 0x160,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x4B0, 0x164,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x4B4, 0x168,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x4B8, 0x16C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x4BC, 0x170,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x4C0, 0x174,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x4C4, 0x178,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x4C8, 0x17C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x4CC, 0x180,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x4D0, 0x184,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x4D4, 0x188,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x4D8, 0x18C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x4DC, 0x190,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM4__NVCC_EIM4 IOMUX_PAD(0x4E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x4E4, 0x194,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x4E8, 0x198,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x4EC, 0x19C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x4F0, 0x1A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x4F4, 0x1A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x4F8, 0x1A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x4FC, 0x1AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x500, 0x1B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x504, 0x1B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x508, 0x1B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x50C, 0x1BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x510, 0x1C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x514, 0x1C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x518, 0x1C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x51C, 0x1CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x520, 0x1D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x524, 0x1D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x528, 0x1D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WE_B__GPIO_6_12 IOMUX_PAD(0x52C, 0x1DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RE_B__GPIO_6_13 IOMUX_PAD(0x530, 0x1E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x534, 0x1E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM7__NVCC_EIM7 IOMUX_PAD(0x53C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_10__GPIO_4_0 IOMUX_PAD(0x540, 0x214, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_11__GPIO_4_1 IOMUX_PAD(0x544, 0x218, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_12__GPIO_4_2 IOMUX_PAD(0x548, 0x21C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_13__GPIO_4_3 IOMUX_PAD(0x54C, 0x220, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_14__GPIO_4_4 IOMUX_PAD(0x550, 0x224, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM3__DRAM_DQM3 IOMUX_PAD(0x554, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1 IOMUX_PAD(0x55C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM2__DRAM_DQM2 IOMUX_PAD(0x560, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1 IOMUX_PAD(0x564, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1 IOMUX_PAD(0x570, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_CAS__DRAM_CAS IOMUX_PAD(0x574, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0 IOMUX_PAD(0x578, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0 IOMUX_PAD(0x580, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM0__DRAM_DQM0 IOMUX_PAD(0x584, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_RAS__DRAM_RAS IOMUX_PAD(0x588, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0 IOMUX_PAD(0x58C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM1__DRAM_DQM1 IOMUX_PAD(0x594, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x598, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x59C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x5A0, 0x228,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x5A4, 0x22C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x5A8, 0x230,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x5AC, 0x234,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x5B0, 0x238,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x5B4, 0x23C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x5B8, 0x240,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x5BC, 0x244,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__GPIO_1_22 IOMUX_PAD(0x5C4, 0x248,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__GPIO_1_24 IOMUX_PAD(0x5CC, 0x250,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__GPIO_1_25 IOMUX_PAD(0x5D0, 0x254,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__GPIO_1_26 IOMUX_PAD(0x5D4, 0x258,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__GPIO_1_27 IOMUX_PAD(0x5D8, 0x25C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__GPIO_1_28 IOMUX_PAD(0x5DC, 0x260,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__GPIO_1_29 IOMUX_PAD(0x5E0, 0x264,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__GPIO_1_30 IOMUX_PAD(0x5E4, 0x268,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__GPIO_1_31 IOMUX_PAD(0x5E8, 0x26C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_FEC__NVCC_FEC IOMUX_PAD(0x5EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DIOW__GPIO_6_17 IOMUX_PAD(0x5F0, 0x270,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DMACK__GPIO_6_18 IOMUX_PAD(0x5F4, 0x274,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DMARQ__GPIO_7_0 IOMUX_PAD(0x5F8, 0x278,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1 IOMUX_PAD(0x5FC, 0x27C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_INTRQ__GPIO_7_2 IOMUX_PAD(0x600, 0x280,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DIOR__GPIO_7_3 IOMUX_PAD(0x604, 0x284,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_RESET_B__GPIO_7_4 IOMUX_PAD(0x608, 0x288,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_IORDY__GPIO_7_5 IOMUX_PAD(0x60C, 0x28C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_0__GPIO_7_6 IOMUX_PAD(0x610, 0x290,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_1__GPIO_7_7 IOMUX_PAD(0x614, 0x294,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_2__GPIO_7_8 IOMUX_PAD(0x618, 0x298,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_CS_0__GPIO_7_9 IOMUX_PAD(0x61C, 0x29C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_CS_1__GPIO_7_10 IOMUX_PAD(0x620, 0x2A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_ATA2__NVCC_ATA2 IOMUX_PAD(0x624, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA0__GPIO_2_0 IOMUX_PAD(0x628, 0x2A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA1__GPIO_2_1 IOMUX_PAD(0x62C, 0x2A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA2__GPIO_2_2 IOMUX_PAD(0x630, 0x2AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA3__GPIO_2_3 IOMUX_PAD(0x634, 0x2B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA4__GPIO_2_4 IOMUX_PAD(0x638, 0x2B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA5__GPIO_2_5 IOMUX_PAD(0x63C, 0x2B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA6__GPIO_2_6 IOMUX_PAD(0x640, 0x2BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA7__GPIO_2_7 IOMUX_PAD(0x644, 0x2C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA8__GPIO_2_8 IOMUX_PAD(0x648, 0x2C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA9__GPIO_2_9 IOMUX_PAD(0x64C, 0x2C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA10__GPIO_2_10 IOMUX_PAD(0x650, 0x2CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA11__GPIO_2_11 IOMUX_PAD(0x654, 0x2D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA12__GPIO_2_12 IOMUX_PAD(0x658, 0x2D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA13__GPIO_2_13 IOMUX_PAD(0x65C, 0x2D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA14__GPIO_2_14 IOMUX_PAD(0x660, 0x2DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA15__GPIO_2_15 IOMUX_PAD(0x664, 0x2E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_ATA0__NVCC_ATA0 IOMUX_PAD(0x668, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__GPIO_1_16 IOMUX_PAD(0x66C, 0x2E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__GPIO_1_17 IOMUX_PAD(0x670, 0x2E8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x674, 0x2EC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__GPIO_1_19 IOMUX_PAD(0x678, 0x2F0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x67C, 0x2F4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__GPIO_1_21 IOMUX_PAD(0x680, 0x2F8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_SD1__NVCC_SD1 IOMUX_PAD(0x684, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x688, 0x2FC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x68C, 0x300,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__GPIO_1_12 IOMUX_PAD(0x690, 0x304,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__GPIO_1_13 IOMUX_PAD(0x694, 0x308,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__GPIO_1_14 IOMUX_PAD(0x698, 0x30C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__GPIO_1_15 IOMUX_PAD(0x69C, 0x310,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_SD2__NVCC_SD2 IOMUX_PAD(0x6A0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x6A4, 0x314,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x6A8, 0x318,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x6AC, 0x31C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x6B0, 0x320,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x6B4, 0x324,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x6B8, 0x328,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x6BC, 0x32C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x6C0, 0x330,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x6C4, 0x334,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x6C8, 0x338,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x6CC, 0x33C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x6D0, 0x340,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x6D4, 0x344,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_GPIO__NVCC_GPIO IOMUX_PAD(0x6D8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_POR_B__POR_B IOMUX_PAD(0x6DC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_TEST_MODE__TEST_MODE IOMUX_PAD(0x6EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_ADDDS__GRP_ADDDS IOMUX_PAD(0x6F0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL IOMUX_PAD(0x6F4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRPK__GRP_DDRPK IOMUX_PAD(0x708, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3 IOMUX_PAD(0x70C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE IOMUX_PAD(0x714, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B0DS__GRP_B0DS IOMUX_PAD(0x718, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B1DS__GRP_B1DS IOMUX_PAD(0x71C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_CTLDS__GRP_CTLDS IOMUX_PAD(0x720, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE IOMUX_PAD(0x724, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B2DS__GRP_B2DS IOMUX_PAD(0x728, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B3DS__GRP_B3DS IOMUX_PAD(0x72C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index 0880a4a..2277b01 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -42,28 +42,44 @@ * If <padname> or <padmode> refers to a GPIO, it is named * GPIO_<unit>_<num> * - */ - -struct pad_desc { - unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */ - unsigned mux_mode:8; - unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */ -#define NO_PAD_CTRL (1 << 16) - unsigned pad_ctrl:17; - unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */ - unsigned select_input:3; -}; - -#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \ - _select_input, _pad_ctrl) \ - { \ - .mux_ctrl_ofs = _mux_ctrl_ofs, \ - .mux_mode = _mux_mode, \ - .pad_ctrl_ofs = _pad_ctrl_ofs, \ - .pad_ctrl = _pad_ctrl, \ - .select_input_ofs = _select_input_ofs, \ - .select_input = _select_input, \ - } + * IOMUX/PAD Bit field definitions + * + * MUX_CTRL_OFS: 0..11 (12) + * PAD_CTRL_OFS: 12..23 (12) + * SEL_INPUT_OFS: 24..35 (12) + * MUX_MODE + SION: 36..40 (5) + * PAD_CTRL + NO_PAD_CTRL: 41..57 (17) + * SEL_INP: 58..61 (4) + * reserved: 63 (1) +*/ + +typedef u64 iomux_v3_cfg_t; + +#define MUX_CTRL_OFS_SHIFT 0 +#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) +#define MUX_PAD_CTRL_OFS_SHIFT 12 +#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT) +#define MUX_SEL_INPUT_OFS_SHIFT 24 +#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT) + +#define MUX_MODE_SHIFT 36 +#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) +#define MUX_PAD_CTRL_SHIFT 41 +#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT) +#define NO_PAD_CTRL ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 16)) +#define MUX_SEL_INPUT_SHIFT 58 +#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) + +#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) + +#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \ + _sel_input, _pad_ctrl) \ + (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \ + ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ + ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \ + ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT)) /* * Use to set PAD control @@ -107,13 +123,13 @@ struct pad_desc { /* * setups a single pad in the iomuxer */ -int mxc_iomux_v3_setup_pad(struct pad_desc *pad); +int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad); /* * setups mutliple pads * convenient way to call the above function with tables */ -int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); +int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); /* * Initialise the iomux controller diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 86781f7..58a49cc 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -23,13 +23,17 @@ #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS /* these are ordered by size to support multi-SoC kernels */ -#if defined CONFIG_ARCH_MX2 +#if defined CONFIG_ARCH_MX53 +#define MXC_GPIO_IRQS (32 * 7) +#elif defined CONFIG_ARCH_MX2 +#define MXC_GPIO_IRQS (32 * 6) +#elif defined CONFIG_ARCH_MX50 #define MXC_GPIO_IRQS (32 * 6) #elif defined CONFIG_ARCH_MX1 #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MX25 #define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MX5 +#elif defined CONFIG_ARCH_MX51 #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MXC91231 #define MXC_GPIO_IRQS (32 * 4) diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 564ec9d..8386140 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -16,7 +16,9 @@ #define MX25_PHYS_OFFSET UL(0x80000000) #define MX27_PHYS_OFFSET UL(0xa0000000) #define MX3x_PHYS_OFFSET UL(0x80000000) +#define MX50_PHYS_OFFSET UL(0x70000000) #define MX51_PHYS_OFFSET UL(0x90000000) +#define MX53_PHYS_OFFSET UL(0x70000000) #define MXC91231_PHYS_OFFSET UL(0x90000000) #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) @@ -32,8 +34,12 @@ # define PHYS_OFFSET MX3x_PHYS_OFFSET # elif defined CONFIG_ARCH_MXC91231 # define PHYS_OFFSET MXC91231_PHYS_OFFSET -# elif defined CONFIG_ARCH_MX5 +# elif defined CONFIG_ARCH_MX50 +# define PHYS_OFFSET MX50_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX51 # define PHYS_OFFSET MX51_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX53 +# define PHYS_OFFSET MX53_PHYS_OFFSET # endif #endif diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 641b246..75d9621 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -19,7 +19,6 @@ */ #define MX1_IO_BASE_ADDR 0x00200000 #define MX1_IO_SIZE SZ_1M -#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END #define MX1_CS0_PHYS 0x10000000 #define MX1_CS0_SIZE 0x02000000 @@ -66,6 +65,10 @@ #define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) #define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) #define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR) +#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR) +#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR) #define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) #define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) #define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) @@ -73,12 +76,12 @@ #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) /* macro to get at IO space when running virtually */ -#define MX1_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX1_IO)) +#define MX1_IO_P2V(x) IMX_IO_P2V(x) +#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) /* fixed interrput numbers */ #define MX1_INT_SOFTINT 0 -#define MX1_CSI_INT 6 +#define MX1_INT_CSI 6 #define MX1_DSPA_MAC_INT 7 #define MX1_DSPA_INT 8 #define MX1_COMP_INT 9 @@ -115,13 +118,13 @@ #define MX1_SSI_RX_INT 44 #define MX1_SSI_RX_ERR_INT 45 #define MX1_TOUCH_INT 46 -#define MX1_USBD_INT0 47 -#define MX1_USBD_INT1 48 -#define MX1_USBD_INT2 49 -#define MX1_USBD_INT3 50 -#define MX1_USBD_INT4 51 -#define MX1_USBD_INT5 52 -#define MX1_USBD_INT6 53 +#define MX1_INT_USBD0 47 +#define MX1_INT_USBD1 48 +#define MX1_INT_USBD2 49 +#define MX1_INT_USBD3 50 +#define MX1_INT_USBD4 51 +#define MX1_INT_USBD5 52 +#define MX1_INT_USBD6 53 #define MX1_BTSYS_INT 55 #define MX1_BTTIM_INT 56 #define MX1_BTWUI_INT 57 @@ -164,134 +167,6 @@ * to not break drivers/usb/gadget/imx_udc. Should go * away after this driver uses the new name. */ -#define USBD_INT0 MX1_USBD_INT0 - -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define IMX_IO_PHYS MX1_IO_BASE_ADDR -#define IMX_IO_SIZE MX1_IO_SIZE -#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT -#define IMX_CS0_PHYS MX1_CS0_PHYS -#define IMX_CS0_SIZE MX1_CS0_SIZE -#define IMX_CS1_PHYS MX1_CS1_PHYS -#define IMX_CS1_SIZE MX1_CS1_SIZE -#define IMX_CS2_PHYS MX1_CS2_PHYS -#define IMX_CS2_SIZE MX1_CS2_SIZE -#define IMX_CS3_PHYS MX1_CS3_PHYS -#define IMX_CS3_SIZE MX1_CS3_SIZE -#define IMX_CS4_PHYS MX1_CS4_PHYS -#define IMX_CS4_SIZE MX1_CS4_SIZE -#define IMX_CS5_PHYS MX1_CS5_PHYS -#define IMX_CS5_SIZE MX1_CS5_SIZE -#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR -#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR -#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR -#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR -#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR -#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR -#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR -#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR -#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR -#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR -#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR -#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR -#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR -#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR -#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR -#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR -#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR -#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR -#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR -#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR -#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR -#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR -#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR -#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR -#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR -#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR -#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR -#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR -#define IO_ADDRESS(x) MX1_IO_ADDRESS(x) -#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) -#define INT_SOFTINT MX1_INT_SOFTINT -#define CSI_INT MX1_CSI_INT -#define DSPA_MAC_INT MX1_DSPA_MAC_INT -#define DSPA_INT MX1_DSPA_INT -#define COMP_INT MX1_COMP_INT -#define MSHC_XINT MX1_MSHC_XINT -#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA -#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB -#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC -#define LCDC_INT MX1_LCDC_INT -#define SIM_INT MX1_SIM_INT -#define SIM_DATA_INT MX1_SIM_DATA_INT -#define RTC_INT MX1_RTC_INT -#define RTC_SAMINT MX1_RTC_SAMINT -#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR -#define UART2_MINT_RTS MX1_UART2_MINT_RTS -#define UART2_MINT_DTR MX1_UART2_MINT_DTR -#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC -#define UART2_MINT_TX MX1_UART2_MINT_TX -#define UART2_MINT_RX MX1_UART2_MINT_RX -#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR -#define UART1_MINT_RTS MX1_UART1_MINT_RTS -#define UART1_MINT_DTR MX1_UART1_MINT_DTR -#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC -#define UART1_MINT_TX MX1_UART1_MINT_TX -#define UART1_MINT_RX MX1_UART1_MINT_RX -#define VOICE_DAC_INT MX1_VOICE_DAC_INT -#define VOICE_ADC_INT MX1_VOICE_ADC_INT -#define PEN_DATA_INT MX1_PEN_DATA_INT -#define PWM_INT MX1_PWM_INT -#define SDHC_INT MX1_SDHC_INT -#define I2C_INT MX1_INT_I2C -#define CSPI_INT MX1_CSPI_INT -#define SSI_TX_INT MX1_SSI_TX_INT -#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT -#define SSI_RX_INT MX1_SSI_RX_INT -#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT -#define TOUCH_INT MX1_TOUCH_INT -#define USBD_INT1 MX1_USBD_INT1 -#define USBD_INT2 MX1_USBD_INT2 -#define USBD_INT3 MX1_USBD_INT3 -#define USBD_INT4 MX1_USBD_INT4 -#define USBD_INT5 MX1_USBD_INT5 -#define USBD_INT6 MX1_USBD_INT6 -#define BTSYS_INT MX1_BTSYS_INT -#define BTTIM_INT MX1_BTTIM_INT -#define BTWUI_INT MX1_BTWUI_INT -#define TIM2_INT MX1_TIM2_INT -#define TIM1_INT MX1_TIM1_INT -#define DMA_ERR MX1_DMA_ERR -#define DMA_INT MX1_DMA_INT -#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD -#define WDT_INT MX1_WDT_INT -#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T -#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R -#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T -#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R -#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT -#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R -#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC -#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT -#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN -#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC -#define DMA_REQ_EXT MX1_DMA_REQ_EXT -#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC -#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R -#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T -#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T -#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R -#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC -#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC -#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x) -#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R -#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T -#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T -#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R -#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T -#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R -#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */ +#define USBD_INT0 MX1_INT_USBD0 #endif /* ifndef __MACH_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 8bc5972..6cd049e 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -26,7 +26,6 @@ #define __MACH_MX21_H__ #define MX21_AIPI_BASE_ADDR 0x10000000 -#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX21_AIPI_SIZE SZ_1M #define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) #define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) @@ -49,6 +48,12 @@ #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) +#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) +#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) +#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) +#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) +#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) +#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) @@ -64,7 +69,6 @@ #define MX21_AVIC_BASE_ADDR 0x10040000 #define MX21_SAHB1_BASE_ADDR 0x80000000 -#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000 #define MX21_SAHB1_SIZE SZ_1M #define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) @@ -82,7 +86,6 @@ /* NAND, SDRAM, WEIM etc controllers */ #define MX21_X_MEMC_BASE_ADDR 0xdf000000 -#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000 #define MX21_X_MEMC_SIZE SZ_256K #define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) @@ -92,10 +95,8 @@ #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ -#define MX21_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX21_AIPI) ?: \ - IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \ - IMX_IO_ADDRESS(x, MX21_X_MEMC)) +#define MX21_IO_P2V(x) IMX_IO_P2V(x) +#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) /* fixed interrupt numbers */ #define MX21_INT_CSPI3 6 @@ -184,39 +185,4 @@ #define MX21_DMA_REQ_CSI_STAT 30 #define MX21_DMA_REQ_CSI_RX 31 -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR -#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR -#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR -#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR -#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR -#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR -#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR -#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR -#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR -#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR -#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT -#define X_MEMC_SIZE MX21_X_MEMC_SIZE -#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR -#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR -#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR -#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR -#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR -#define MXC_INT_FIRI MX21_INT_FIRI -#define MXC_INT_BMI MX21_INT_BMI -#define MXC_INT_EMMAENC MX21_INT_EMMAENC -#define MXC_INT_EMMADEC MX21_INT_EMMADEC -#define MXC_INT_USBWKUP MX21_INT_USBWKUP -#define MXC_INT_USBDMA MX21_INT_USBDMA -#define MXC_INT_USBHOST MX21_INT_USBHOST -#define MXC_INT_USBFUNC MX21_INT_USBFUNC -#define MXC_INT_USBMNP MX21_INT_USBMNP -#define MXC_INT_USBCTRL MX21_INT_USBCTRL -#define MXC_INT_USBCTRL MX21_INT_USBCTRL -#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX -#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX -#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX -#endif - #endif /* ifndef __MACH_MX21_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index cf46a45..087cd7a 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -2,13 +2,10 @@ #define __MACH_MX25_H__ #define MX25_AIPS1_BASE_ADDR 0x43f00000 -#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX25_AIPS1_SIZE SZ_1M #define MX25_AIPS2_BASE_ADDR 0x53f00000 -#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX25_AIPS2_SIZE SZ_1M #define MX25_AVIC_BASE_ADDR 0x68000000 -#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX25_AVIC_SIZE SZ_1M #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) @@ -21,20 +18,15 @@ #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) +#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) +#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) +#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) +#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) +#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) +#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) +#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) - -#define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000) -#define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000) -#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) -#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) - -#define MX25_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ - IMX_IO_ADDRESS(x, MX25_AVIC)) - -#define MX25_AIPS1_IO_ADDRESS(x) \ - (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) +#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) #define MX25_UART1_BASE_ADDR 0x43f90000 #define MX25_UART2_BASE_ADDR 0x43f94000 @@ -55,9 +47,19 @@ #define MX25_LCDC_BASE_ADDR 0x53fbc000 #define MX25_KPP_BASE_ADDR 0x43fa8000 #define MX25_SDMA_BASE_ADDR 0x53fd4000 -#define MX25_OTG_BASE_ADDR 0x53ff4000 +#define MX25_USB_BASE_ADDR 0x53ff4000 +#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) +/* + * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200 + * for the host controller. Early documentation drafts specified 0x400 and + * Freescale internal sources confirm only the latter value to work. + */ +#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400) #define MX25_CSI_BASE_ADDR 0x53ff8000 +#define MX25_IO_P2V(x) IMX_IO_P2V(x) +#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) + #define MX25_INT_CSPI3 0 #define MX25_INT_I2C1 3 #define MX25_INT_I2C2 4 @@ -69,18 +71,28 @@ #define MX25_INT_SSI1 12 #define MX25_INT_CSPI2 13 #define MX25_INT_CSPI1 14 +#define MX25_INT_GPIO3 16 #define MX25_INT_CSI 17 #define MX25_INT_UART3 18 +#define MX25_INT_GPIO4 23 #define MX25_INT_KPP 24 #define MX25_INT_DRYICE 25 +#define MX25_INT_PWM1 26 #define MX25_INT_UART2 32 #define MX25_INT_NFC 33 #define MX25_INT_SDMA 34 +#define MX25_INT_USB_HS 35 +#define MX25_INT_PWM2 36 +#define MX25_INT_USB_OTG 37 #define MX25_INT_LCDC 39 #define MX25_INT_UART5 40 +#define MX25_INT_PWM3 41 +#define MX25_INT_PWM4 42 #define MX25_INT_CAN1 43 #define MX25_INT_CAN2 44 #define MX25_INT_UART1 45 +#define MX25_INT_GPIO2 51 +#define MX25_INT_GPIO1 52 #define MX25_INT_FEC 57 #define MX25_DMA_REQ_SSI2_RX1 22 diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 2237ba2..cbc43ad 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -29,7 +29,6 @@ #endif #define MX27_AIPI_BASE_ADDR 0x10000000 -#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX27_AIPI_SIZE SZ_1M #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) @@ -52,6 +51,12 @@ #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) +#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) +#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) +#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) +#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) +#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) +#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) @@ -65,11 +70,13 @@ #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) -#define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) -#define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR +#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) +#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) +#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) +#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) -#define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) -#define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) +#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) +#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) @@ -87,7 +94,6 @@ #define MX27_ROMP_BASE_ADDR 0x10041000 #define MX27_SAHB1_BASE_ADDR 0x80000000 -#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000 #define MX27_SAHB1_SIZE SZ_1M #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) @@ -105,7 +111,6 @@ /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX27_X_MEMC_BASE_ADDR 0xd8000000 -#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000 #define MX27_X_MEMC_SIZE SZ_1M #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) @@ -123,10 +128,8 @@ /* IRAM */ #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ -#define MX27_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX27_AIPI) ?: \ - IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \ - IMX_IO_ADDRESS(x, MX27_X_MEMC)) +#define MX27_IO_P2V(x) IMX_IO_P2V(x) +#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) #ifndef __ASSEMBLER__ static inline void mx27_setup_weimcs(size_t cs, @@ -192,9 +195,9 @@ static inline void mx27_setup_weimcs(size_t cs, #define MX27_INT_EMMAPRP 51 #define MX27_INT_EMMAPP 52 #define MX27_INT_VPU 53 -#define MX27_INT_USB1 54 -#define MX27_INT_USB2 55 -#define MX27_INT_USB3 56 +#define MX27_INT_USB_HS1 54 +#define MX27_INT_USB_HS2 55 +#define MX27_INT_USB_OTG 56 #define MX27_INT_SCC_SMN 57 #define MX27_INT_SCC_SCM 58 #define MX27_INT_SAHARA 59 @@ -241,82 +244,8 @@ static inline void mx27_setup_weimcs(size_t cs, #define MX27_DMA_REQ_SDHC3 36 #define MX27_DMA_REQ_NFC 37 -/* silicon revisions specific to i.MX27 */ -#define CHIP_REV_1_0 0x00 -#define CHIP_REV_2_0 0x01 - #ifndef __ASSEMBLY__ extern int mx27_revision(void); #endif -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR -#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR -#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR -#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR -#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR -#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR -#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR -#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR -#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR -#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR -#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR -#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR -#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR -#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR -#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR -#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR -#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR -#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR -#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR -#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR -#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR -#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR -#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR -#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR -#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR -#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR -#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR -#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR -#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT -#define X_MEMC_SIZE MX27_X_MEMC_SIZE -#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR -#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR -#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR -#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR -#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR -#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR -#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR -#define MXC_INT_I2C2 MX27_INT_I2C2 -#define MXC_INT_GPT6 MX27_INT_GPT6 -#define MXC_INT_GPT5 MX27_INT_GPT5 -#define MXC_INT_GPT4 MX27_INT_GPT4 -#define MXC_INT_RTIC MX27_INT_RTIC -#define MXC_INT_SDHC MX27_INT_SDHC -#define MXC_INT_SDHC3 MX27_INT_SDHC3 -#define MXC_INT_ATA MX27_INT_ATA -#define MXC_INT_UART6 MX27_INT_UART6 -#define MXC_INT_UART5 MX27_INT_UART5 -#define MXC_INT_FEC MX27_INT_FEC -#define MXC_INT_VPU MX27_INT_VPU -#define MXC_INT_USB1 MX27_INT_USB1 -#define MXC_INT_USB2 MX27_INT_USB2 -#define MXC_INT_USB3 MX27_INT_USB3 -#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN -#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM -#define MXC_INT_SAHARA MX27_INT_SAHARA -#define MXC_INT_IIM MX27_INT_IIM -#define MXC_INT_CCM MX27_INT_CCM -#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC -#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX -#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV -#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX -#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX -#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX -#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX -#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 -#define DMA_REQ_NFC MX27_DMA_REQ_NFC -#endif - #endif /* ifndef __MACH_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index afb895a..6d07839 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -27,7 +27,6 @@ /* Register offsets */ #define MX2x_AIPI_BASE_ADDR 0x10000000 -#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX2x_AIPI_SIZE SZ_1M #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) @@ -65,43 +64,9 @@ #define MX2x_AVIC_BASE_ADDR 0x10040000 #define MX2x_SAHB1_BASE_ADDR 0x80000000 -#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000 #define MX2x_SAHB1_SIZE SZ_1M #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) -/* - * This macro defines the physical to virtual address mapping for all the - * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. If the physical address is not mapped, - * it returns 0xDEADBEEF - */ -#define IO_ADDRESS(x) \ - (void __force __iomem *) \ - (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ - AIPI_IO_ADDRESS(x) : \ - ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ - SAHB1_IO_ADDRESS(x) : \ - ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \ - X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF) - -/* define the address mapping macros: in physical address order */ -#define AIPI_IO_ADDRESS(x) \ - (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) - -#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x) - -#define SAHB1_IO_ADDRESS(x) \ - (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT) - -#define CS4_IO_ADDRESS(x) \ - (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) - -#define X_MEMC_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - -#define PCMCIA_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - /* fixed interrupt numbers */ #define MX2x_INT_CSPI3 6 #define MX2x_INT_GPIO 8 @@ -176,118 +141,4 @@ #define MX2x_DMA_REQ_CSI_STAT 30 #define MX2x_DMA_REQ_CSI_RX 31 -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR -#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT -#define AIPI_SIZE MX2x_AIPI_SIZE -#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR -#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR -#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR -#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR -#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR -#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR -#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR -#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR -#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR -#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR -#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR -#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR -#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR -#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR -#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR -#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR -#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR -#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR -#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR -#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR -#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR -#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR -#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR -#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR -#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR -#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR -#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR -#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR -#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR -#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR -#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR -#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR -#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR -#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT -#define SAHB1_SIZE MX2x_SAHB1_SIZE -#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR -#define MXC_INT_CSPI3 MX2x_INT_CSPI3 -#define MXC_INT_GPIO MX2x_INT_GPIO -#define MXC_INT_SDHC2 MX2x_INT_SDHC2 -#define MXC_INT_SDHC1 MX2x_INT_SDHC1 -#define MXC_INT_I2C MX2x_INT_I2C -#define MXC_INT_SSI2 MX2x_INT_SSI2 -#define MXC_INT_SSI1 MX2x_INT_SSI1 -#define MXC_INT_CSPI2 MX2x_INT_CSPI2 -#define MXC_INT_CSPI1 MX2x_INT_CSPI1 -#define MXC_INT_UART4 MX2x_INT_UART4 -#define MXC_INT_UART3 MX2x_INT_UART3 -#define MXC_INT_UART2 MX2x_INT_UART2 -#define MXC_INT_UART1 MX2x_INT_UART1 -#define MXC_INT_KPP MX2x_INT_KPP -#define MXC_INT_RTC MX2x_INT_RTC -#define MXC_INT_PWM MX2x_INT_PWM -#define MXC_INT_GPT3 MX2x_INT_GPT3 -#define MXC_INT_GPT2 MX2x_INT_GPT2 -#define MXC_INT_GPT1 MX2x_INT_GPT1 -#define MXC_INT_WDOG MX2x_INT_WDOG -#define MXC_INT_PCMCIA MX2x_INT_PCMCIA -#define MXC_INT_NANDFC MX2x_INT_NANDFC -#define MXC_INT_CSI MX2x_INT_CSI -#define MXC_INT_DMACH0 MX2x_INT_DMACH0 -#define MXC_INT_DMACH1 MX2x_INT_DMACH1 -#define MXC_INT_DMACH2 MX2x_INT_DMACH2 -#define MXC_INT_DMACH3 MX2x_INT_DMACH3 -#define MXC_INT_DMACH4 MX2x_INT_DMACH4 -#define MXC_INT_DMACH5 MX2x_INT_DMACH5 -#define MXC_INT_DMACH6 MX2x_INT_DMACH6 -#define MXC_INT_DMACH7 MX2x_INT_DMACH7 -#define MXC_INT_DMACH8 MX2x_INT_DMACH8 -#define MXC_INT_DMACH9 MX2x_INT_DMACH9 -#define MXC_INT_DMACH10 MX2x_INT_DMACH10 -#define MXC_INT_DMACH11 MX2x_INT_DMACH11 -#define MXC_INT_DMACH12 MX2x_INT_DMACH12 -#define MXC_INT_DMACH13 MX2x_INT_DMACH13 -#define MXC_INT_DMACH14 MX2x_INT_DMACH14 -#define MXC_INT_DMACH15 MX2x_INT_DMACH15 -#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP -#define MXC_INT_EMMAPP MX2x_INT_EMMAPP -#define MXC_INT_SLCDC MX2x_INT_SLCDC -#define MXC_INT_LCDC MX2x_INT_LCDC -#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX -#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX -#define DMA_REQ_EXT MX2x_DMA_REQ_EXT -#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2 -#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1 -#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0 -#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0 -#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1 -#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1 -#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0 -#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0 -#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1 -#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1 -#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX -#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX -#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX -#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX -#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX -#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX -#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX -#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX -#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX -#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX -#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX -#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX -#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT -#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX -#endif - #endif /* ifndef __MACH_MX2x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 61cfe82..79e7fc0 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -15,7 +15,6 @@ #define MX31_L2CC_SIZE SZ_1M #define MX31_AIPS1_BASE_ADDR 0x43f00000 -#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX31_AIPS1_SIZE SZ_1M #define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) #define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) @@ -25,7 +24,10 @@ #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) #define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) -#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) +#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) +#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) @@ -41,10 +43,9 @@ #define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) #define MX31_SPBA0_BASE_ADDR 0x50000000 -#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000 #define MX31_SPBA0_SIZE SZ_1M -#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) -#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) +#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) +#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) #define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) #define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) #define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) @@ -55,7 +56,6 @@ #define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) #define MX31_AIPS2_BASE_ADDR 0x53f00000 -#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX31_AIPS2_SIZE SZ_1M #define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) #define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) @@ -84,7 +84,6 @@ #define MX31_ROMP_SIZE SZ_1M #define MX31_AVIC_BASE_ADDR 0x68000000 -#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX31_AVIC_SIZE SZ_1M #define MX31_IPU_MEM_BASE_ADDR 0x70000000 @@ -97,15 +96,14 @@ #define MX31_CS3_BASE_ADDR 0xb2000000 #define MX31_CS4_BASE_ADDR 0xb4000000 -#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000 #define MX31_CS4_SIZE SZ_32M #define MX31_CS5_BASE_ADDR 0xb6000000 -#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000 #define MX31_CS5_SIZE SZ_32M #define MX31_X_MEMC_BASE_ADDR 0xb8000000 -#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000 #define MX31_X_MEMC_SIZE SZ_64K #define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) #define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) @@ -121,12 +119,8 @@ #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 -#define MX31_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \ - IMX_IO_ADDRESS(x, MX31_AVIC) ?: \ - IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \ - IMX_IO_ADDRESS(x, MX31_SPBA0)) +#define MX31_IO_P2V(x) IMX_IO_P2V(x) +#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) #ifndef __ASSEMBLER__ static inline void mx31_setup_weimcs(size_t cs, @@ -143,8 +137,8 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_MPEG4_ENCODER 5 #define MX31_INT_RTIC 6 #define MX31_INT_FIRI 7 -#define MX31_INT_MMC_SDHC2 8 -#define MX31_INT_MMC_SDHC1 9 +#define MX31_INT_SDHC2 8 +#define MX31_INT_SDHC1 9 #define MX31_INT_I2C1 10 #define MX31_INT_SSI2 11 #define MX31_INT_SSI1 12 @@ -170,10 +164,9 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_UART2 32 #define MX31_INT_NFC 33 #define MX31_INT_SDMA 34 -#define MX31_INT_USB1 35 -#define MX31_INT_USB2 36 -#define MX31_INT_USB3 37 -#define MX31_INT_USB4 38 +#define MX31_INT_USB_HS1 35 +#define MX31_INT_USB_HS2 36 +#define MX31_INT_USB_OTG 37 #define MX31_INT_MSHC1 39 #define MX31_INT_MSHC2 40 #define MX31_INT_IPU_ERR 41 @@ -197,6 +190,8 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_EXT_WDOG 62 #define MX31_INT_EXT_TV 63 +#define MX31_DMA_REQ_SDHC1 20 +#define MX31_DMA_REQ_SDHC2 21 #define MX31_DMA_REQ_SSI2_RX1 22 #define MX31_DMA_REQ_SSI2_TX1 23 #define MX31_DMA_REQ_SSI2_RX0 24 @@ -208,52 +203,4 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ -/* silicon revisions specific to i.MX31 */ -#define MX31_CHIP_REV_1_0 0x10 -#define MX31_CHIP_REV_1_1 0x11 -#define MX31_CHIP_REV_1_2 0x12 -#define MX31_CHIP_REV_1_3 0x13 -#define MX31_CHIP_REV_2_0 0x20 -#define MX31_CHIP_REV_2_1 0x21 -#define MX31_CHIP_REV_2_2 0x22 -#define MX31_CHIP_REV_2_3 0x23 -#define MX31_CHIP_REV_3_0 0x30 -#define MX31_CHIP_REV_3_1 0x31 -#define MX31_CHIP_REV_3_2 0x32 - -#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 -#define MX31_SYSTEM_REV_NUM 3 - -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR -#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR -#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR -#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR -#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR -#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR -#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR -#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR -#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR -#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR -#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR -#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR -#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER -#define MXC_INT_FIRI MX31_INT_FIRI -#define MXC_INT_MBX MX31_INT_MBX -#define MXC_INT_CSPI3 MX31_INT_CSPI3 -#define MXC_INT_SIM2 MX31_INT_SIM2 -#define MXC_INT_SIM1 MX31_INT_SIM1 -#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS -#define MXC_INT_USB1 MX31_INT_USB1 -#define MXC_INT_USB2 MX31_INT_USB2 -#define MXC_INT_USB3 MX31_INT_USB3 -#define MXC_INT_USB4 MX31_INT_USB4 -#define MXC_INT_MSHC2 MX31_INT_MSHC2 -#define MXC_INT_UART4 MX31_INT_UART4 -#define MXC_INT_UART5 MX31_INT_UART5 -#define MXC_INT_CCM MX31_INT_CCM -#define MXC_INT_PCMCIA MX31_INT_PCMCIA -#endif - #endif /* ifndef __MACH_MX31_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 6267cff..d13dbfe 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -11,7 +11,6 @@ #define MX35_L2CC_SIZE SZ_1M #define MX35_AIPS1_BASE_ADDR 0x43f00000 -#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX35_AIPS1_SIZE SZ_1M #define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) #define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) @@ -33,7 +32,6 @@ #define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) #define MX35_SPBA0_BASE_ADDR 0x50000000 -#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000 #define MX35_SPBA0_SIZE SZ_1M #define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) #define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) @@ -44,7 +42,6 @@ #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) #define MX35_AIPS2_BASE_ADDR 0x53f00000 -#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX35_AIPS2_SIZE SZ_1M #define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) #define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) @@ -68,15 +65,19 @@ #define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) #define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) - -#define MX35_OTG_BASE_ADDR 0x53ff4000 +#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000) +#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000) +/* + * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for + * HS. When host support was implemented only a preliminary document was + * available, which told 0x400. This works fine. + */ +#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400) #define MX35_ROMP_BASE_ADDR 0x60000000 -#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000 #define MX35_ROMP_SIZE SZ_1M #define MX35_AVIC_BASE_ADDR 0x68000000 -#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX35_AVIC_SIZE SZ_1M /* @@ -92,18 +93,17 @@ #define MX35_CS3_BASE_ADDR 0xb2000000 #define MX35_CS4_BASE_ADDR 0xb4000000 -#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000 #define MX35_CS4_SIZE SZ_32M #define MX35_CS5_BASE_ADDR 0xb6000000 -#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000 #define MX35_CS5_SIZE SZ_32M /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX35_X_MEMC_BASE_ADDR 0xb8000000 -#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000 #define MX35_X_MEMC_SIZE SZ_64K #define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) #define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) @@ -114,12 +114,8 @@ #define MX35_NFC_BASE_ADDR 0xbb000000 #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 -#define MX35_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \ - IMX_IO_ADDRESS(x, MX35_AVIC) ?: \ - IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \ - IMX_IO_ADDRESS(x, MX35_SPBA0)) +#define MX35_IO_P2V(x) IMX_IO_P2V(x) +#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) /* * Interrupt numbers @@ -153,8 +149,8 @@ #define MX35_INT_UART2 32 #define MX35_INT_NFC 33 #define MX35_INT_SDMA 34 -#define MX35_INT_USBHS 35 -#define MX35_INT_USBOTG 37 +#define MX35_INT_USB_HS 35 +#define MX35_INT_USB_OTG 37 #define MX35_INT_MSHC1 39 #define MX35_INT_ESAI 40 #define MX35_INT_IPU_ERR 41 @@ -190,23 +186,4 @@ #define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ -#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 -#define MX35_SYSTEM_REV_NUM 3 - -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR -#define MXC_INT_OWIRE MX35_INT_OWIRE -#define MXC_INT_GPU2D MX35_INT_GPU2D -#define MXC_INT_ASRC MX35_INT_ASRC -#define MXC_INT_USBHS MX35_INT_USBHS -#define MXC_INT_USBOTG MX35_INT_USBOTG -#define MXC_INT_ESAI MX35_INT_ESAI -#define MXC_INT_CAN1 MX35_INT_CAN1 -#define MXC_INT_CAN2 MX35_INT_CAN2 -#define MXC_INT_MLB MX35_INT_MLB -#define MXC_INT_SPDIF MX35_INT_SPDIF -#define MXC_INT_FEC MX35_INT_FEC -#endif - #endif /* ifndef __MACH_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index d1bd26d..388a407 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -44,7 +44,6 @@ * AIPS 1 */ #define MX3x_AIPS1_BASE_ADDR 0x43f00000 -#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX3x_AIPS1_SIZE SZ_1M #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) @@ -69,7 +68,6 @@ * SPBA global module enabled #0 */ #define MX3x_SPBA0_BASE_ADDR 0x50000000 -#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000 #define MX3x_SPBA0_SIZE SZ_1M #define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) #define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) @@ -82,7 +80,6 @@ * AIPS 2 */ #define MX3x_AIPS2_BASE_ADDR 0x53f00000 -#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX3x_AIPS2_SIZE SZ_1M #define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) #define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) @@ -105,11 +102,9 @@ * ROMP and AVIC */ #define MX3x_ROMP_BASE_ADDR 0x60000000 -#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000 #define MX3x_ROMP_SIZE SZ_1M #define MX3x_AVIC_BASE_ADDR 0x68000000 -#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX3x_AVIC_SIZE SZ_1M /* @@ -125,18 +120,17 @@ #define MX3x_CS3_BASE_ADDR 0xb2000000 #define MX3x_CS4_BASE_ADDR 0xb4000000 -#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000 #define MX3x_CS4_SIZE SZ_32M #define MX3x_CS5_BASE_ADDR 0xb6000000 -#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000 #define MX3x_CS5_SIZE SZ_32M /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX3x_X_MEMC_BASE_ADDR 0xb8000000 -#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000 #define MX3x_X_MEMC_SIZE SZ_64K #define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) #define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) @@ -146,56 +140,6 @@ #define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 -/*! - * This macro defines the physical to virtual address mapping for all the - * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. If the physical address is not mapped, - * it returns 0xDEADBEEF - */ -#define IO_ADDRESS(x) \ - (void __force __iomem *) \ - (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ - ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ - ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ - ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ - ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ - ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ - ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ - 0xDEADBEEF) - -/* - * define the address mapping macros: in physical address order - */ -#define L2CC_IO_ADDRESS(x) \ - (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) - -#define AIPS1_IO_ADDRESS(x) \ - (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) - -#define SPBA0_IO_ADDRESS(x) \ - (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) - -#define AIPS2_IO_ADDRESS(x) \ - (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) - -#define ROMP_IO_ADDRESS(x) \ - (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) - -#define AVIC_IO_ADDRESS(x) \ - (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) - -#define CS4_IO_ADDRESS(x) \ - (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) - -#define CS5_IO_ADDRESS(x) \ - (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT) - -#define X_MEMC_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - -#define PCMCIA_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - /* * Interrupt numbers */ @@ -240,22 +184,6 @@ #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ -/* silicon revisions specific to i.MX31 and i.MX35 */ -#define MX3x_CHIP_REV_1_0 0x10 -#define MX3x_CHIP_REV_1_1 0x11 -#define MX3x_CHIP_REV_1_2 0x12 -#define MX3x_CHIP_REV_1_3 0x13 -#define MX3x_CHIP_REV_2_0 0x20 -#define MX3x_CHIP_REV_2_1 0x21 -#define MX3x_CHIP_REV_2_2 0x22 -#define MX3x_CHIP_REV_2_3 0x23 -#define MX3x_CHIP_REV_3_0 0x30 -#define MX3x_CHIP_REV_3_1 0x31 -#define MX3x_CHIP_REV_3_2 0x32 - -#define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 -#define MX3x_SYSTEM_REV_NUM 3 - /* Mandatory defines used globally */ #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) @@ -277,126 +205,4 @@ static inline int mx35_revision(void) } #endif -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR -#define L2CC_SIZE MX3x_L2CC_SIZE -#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR -#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT -#define AIPS1_SIZE MX3x_AIPS1_SIZE -#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR -#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR -#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR -#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR -#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR -#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR -#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR -#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR -#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR -#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR -#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR -#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR -#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR -#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR -#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR -#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR -#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR -#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR -#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT -#define SPBA0_SIZE MX3x_SPBA0_SIZE -#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR -#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR -#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR -#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR -#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR -#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR -#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR -#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT -#define AIPS2_SIZE MX3x_AIPS2_SIZE -#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR -#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR -#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR -#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR -#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR -#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR -#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR -#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR -#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR -#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR -#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR -#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR -#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR -#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR -#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR -#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR -#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR -#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT -#define ROMP_SIZE MX3x_ROMP_SIZE -#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR -#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT -#define AVIC_SIZE MX3x_AVIC_SIZE -#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR -#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR -#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR -#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR -#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR -#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR -#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR -#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR -#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT -#define CS4_SIZE MX3x_CS4_SIZE -#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR -#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT -#define CS5_SIZE MX3x_CS5_SIZE -#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR -#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT -#define X_MEMC_SIZE MX3x_X_MEMC_SIZE -#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR -#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR -#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR -#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR -#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR -#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR -#define MXC_INT_I2C3 MX3x_INT_I2C3 -#define MXC_INT_I2C2 MX3x_INT_I2C2 -#define MXC_INT_RTIC MX3x_INT_RTIC -#define MXC_INT_I2C MX3x_INT_I2C -#define MXC_INT_CSPI2 MX3x_INT_CSPI2 -#define MXC_INT_CSPI1 MX3x_INT_CSPI1 -#define MXC_INT_ATA MX3x_INT_ATA -#define MXC_INT_UART3 MX3x_INT_UART3 -#define MXC_INT_IIM MX3x_INT_IIM -#define MXC_INT_RNGA MX3x_INT_RNGA -#define MXC_INT_EVTMON MX3x_INT_EVTMON -#define MXC_INT_KPP MX3x_INT_KPP -#define MXC_INT_RTC MX3x_INT_RTC -#define MXC_INT_PWM MX3x_INT_PWM -#define MXC_INT_EPIT2 MX3x_INT_EPIT2 -#define MXC_INT_EPIT1 MX3x_INT_EPIT1 -#define MXC_INT_GPT MX3x_INT_GPT -#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL -#define MXC_INT_UART2 MX3x_INT_UART2 -#define MXC_INT_NANDFC MX3x_INT_NANDFC -#define MXC_INT_SDMA MX3x_INT_SDMA -#define MXC_INT_MSHC1 MX3x_INT_MSHC1 -#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR -#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN -#define MXC_INT_UART1 MX3x_INT_UART1 -#define MXC_INT_ECT MX3x_INT_ECT -#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM -#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN -#define MXC_INT_GPIO2 MX3x_INT_GPIO2 -#define MXC_INT_GPIO1 MX3x_INT_GPIO1 -#define MXC_INT_WDOG MX3x_INT_WDOG -#define MXC_INT_GPIO3 MX3x_INT_GPIO3 -#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER -#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER -#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60 -#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61 -#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG -#define MXC_INT_EXT_TV MX3x_INT_EXT_TV -#define PROD_SIGNATURE MX3x_PROD_SIGNATURE -#endif - #endif /* ifndef __MACH_MX3x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h new file mode 100644 index 0000000..aaec2a6 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx50.h @@ -0,0 +1,285 @@ +#ifndef __MACH_MX50_H__ +#define __MACH_MX50_H__ + +/* + * IROM + */ +#define MX50_IROM_BASE_ADDR 0x0 +#define MX50_IROM_SIZE SZ_64K + +/* TZIC */ +#define MX50_TZIC_BASE_ADDR 0x0fffc000 +#define MX50_TZIC_SIZE SZ_16K + +/* + * IRAM + */ +#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */ +#define MX50_IRAM_PARTITIONS 16 +#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */ + +/* + * Databahn + */ +#define MX50_DATABAHN_BASE_ADDR 0x14000000 + +/* + * Graphics Memory of GPU + */ +#define MX50_GPU2D_BASE_ADDR 0x20000000 + +#define MX50_DEBUG_BASE_ADDR 0x40000000 +#define MX50_DEBUG_SIZE SZ_1M +#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000) +#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000) +#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000) +#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000) +#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000) +#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000) +#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000) +#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000) + +#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000) +#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000) +#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000) +#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000) +#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000) +#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000) +#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000) +#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000) +#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000) +#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000) +#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000) +#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000) +#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000) +#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000) + +/* + * SPBA global module enabled #0 + */ +#define MX50_SPBA0_BASE_ADDR 0x50000000 +#define MX50_SPBA0_SIZE SZ_1M + +#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000) +#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000) +#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000) +#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000) +#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000) +#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000) +#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000) + +/* + * AIPS 1 + */ +#define MX50_AIPS1_BASE_ADDR 0x53f00000 +#define MX50_AIPS1_SIZE SZ_1M + +#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000) +#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000) +#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000) +#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000) +#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000) +#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000) +#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000) +#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000) +#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000) +#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000) +#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000) +#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000) +#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000) +#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000) +#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000) +#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000) +#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000) +#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000) +#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000) +#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000) +#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000) +#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000) + +#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000) +#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000) + +/* + * AIPS 2 + */ +#define MX50_AIPS2_BASE_ADDR 0x63f00000 +#define MX50_AIPS2_SIZE SZ_1M + +#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000) +#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000) +#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000) +#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000) +#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000) +#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000) +#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000) +#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000) +#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000) +#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000) +#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000) +#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000) +#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000) +#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000) +#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000) +#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000) +#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000) + +/* + * Memory regions and CS + */ +#define MX50_CSD0_BASE_ADDR 0x70000000 +#define MX50_CSD1_BASE_ADDR 0xb0000000 +#define MX50_CS0_BASE_ADDR 0xf0000000 + +#define MX50_IO_P2V(x) IMX_IO_P2V(x) +#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x)) + +/* + * defines for SPBA modules + */ +#define MX50_SPBA_SDHC1 0x04 +#define MX50_SPBA_SDHC2 0x08 +#define MX50_SPBA_UART3 0x0c +#define MX50_SPBA_CSPI1 0x10 +#define MX50_SPBA_SSI2 0x14 +#define MX50_SPBA_SDHC3 0x20 +#define MX50_SPBA_SDHC4 0x24 +#define MX50_SPBA_SPDIF 0x28 +#define MX50_SPBA_ATA 0x30 +#define MX50_SPBA_SLIM 0x34 +#define MX50_SPBA_HSI2C 0x38 +#define MX50_SPBA_CTRL 0x3c + +/* + * DMA request assignments + */ +#define MX50_DMA_REQ_GPC 1 +#define MX50_DMA_REQ_ATA_UART4_RX 2 +#define MX50_DMA_REQ_ATA_UART4_TX 3 +#define MX50_DMA_REQ_CSPI1_RX 6 +#define MX50_DMA_REQ_CSPI1_TX 7 +#define MX50_DMA_REQ_CSPI2_RX 8 +#define MX50_DMA_REQ_CSPI2_TX 9 +#define MX50_DMA_REQ_I2C3_SDHC3 10 +#define MX50_DMA_REQ_SDHC4 11 +#define MX50_DMA_REQ_UART2_FIRI_RX 12 +#define MX50_DMA_REQ_UART2_FIRI_TX 13 +#define MX50_DMA_REQ_EXT0 14 +#define MX50_DMA_REQ_EXT1 15 +#define MX50_DMA_REQ_UART5_RX 16 +#define MX50_DMA_REQ_UART5_TX 17 +#define MX50_DMA_REQ_UART1_RX 18 +#define MX50_DMA_REQ_UART1_TX 19 +#define MX50_DMA_REQ_I2C1_SDHC1 20 +#define MX50_DMA_REQ_I2C2_SDHC2 21 +#define MX50_DMA_REQ_SSI2_RX2 22 +#define MX50_DMA_REQ_SSI2_TX2 23 +#define MX50_DMA_REQ_SSI2_RX1 24 +#define MX50_DMA_REQ_SSI2_TX1 25 +#define MX50_DMA_REQ_SSI1_RX2 26 +#define MX50_DMA_REQ_SSI1_TX2 27 +#define MX50_DMA_REQ_SSI1_RX1 28 +#define MX50_DMA_REQ_SSI1_TX1 29 +#define MX50_DMA_REQ_CSPI_RX 38 +#define MX50_DMA_REQ_CSPI_TX 39 +#define MX50_DMA_REQ_UART3_RX 42 +#define MX50_DMA_REQ_UART3_TX 43 + +/* + * Interrupt numbers + */ +#define MX50_INT_MMC_SDHC1 1 +#define MX50_INT_MMC_SDHC2 2 +#define MX50_INT_MMC_SDHC3 3 +#define MX50_INT_MMC_SDHC4 4 +#define MX50_INT_DAP 5 +#define MX50_INT_SDMA 6 +#define MX50_INT_IOMUX 7 +#define MX50_INT_UART4 13 +#define MX50_INT_USB_H1 14 +#define MX50_INT_USB_OTG 18 +#define MX50_INT_DATABAHN 19 +#define MX50_INT_ELCDIF 20 +#define MX50_INT_EPXP 21 +#define MX50_INT_SRTC_NTZ 24 +#define MX50_INT_SRTC_TZ 25 +#define MX50_INT_EPDC 27 +#define MX50_INT_NIC 28 +#define MX50_INT_SSI1 29 +#define MX50_INT_SSI2 30 +#define MX50_INT_UART1 31 +#define MX50_INT_UART2 32 +#define MX50_INT_UART3 33 +#define MX50_INT_RESV34 34 +#define MX50_INT_RESV35 35 +#define MX50_INT_CSPI1 36 +#define MX50_INT_CSPI2 37 +#define MX50_INT_CSPI 38 +#define MX50_INT_GPT 39 +#define MX50_INT_EPIT1 40 +#define MX50_INT_GPIO1_INT7 42 +#define MX50_INT_GPIO1_INT6 43 +#define MX50_INT_GPIO1_INT5 44 +#define MX50_INT_GPIO1_INT4 45 +#define MX50_INT_GPIO1_INT3 46 +#define MX50_INT_GPIO1_INT2 47 +#define MX50_INT_GPIO1_INT1 48 +#define MX50_INT_GPIO1_INT0 49 +#define MX50_INT_GPIO1_LOW 50 +#define MX50_INT_GPIO1_HIGH 51 +#define MX50_INT_GPIO2_LOW 52 +#define MX50_INT_GPIO2_HIGH 53 +#define MX50_INT_GPIO3_LOW 54 +#define MX50_INT_GPIO3_HIGH 55 +#define MX50_INT_GPIO4_LOW 56 +#define MX50_INT_GPIO4_HIGH 57 +#define MX50_INT_WDOG1 58 +#define MX50_INT_KPP 60 +#define MX50_INT_PWM1 61 +#define MX50_INT_I2C1 62 +#define MX50_INT_I2C2 63 +#define MX50_INT_I2C3 64 +#define MX50_INT_RESV65 65 +#define MX50_INT_DCDC 66 +#define MX50_INT_THERMAL_ALARM 67 +#define MX50_INT_ANA3 68 +#define MX50_INT_ANA4 69 +#define MX50_INT_CCM1 71 +#define MX50_INT_CCM2 72 +#define MX50_INT_GPC1 73 +#define MX50_INT_GPC2 74 +#define MX50_INT_SRC 75 +#define MX50_INT_NM 76 +#define MX50_INT_PMU 77 +#define MX50_INT_CTI_IRQ 78 +#define MX50_INT_CTI1_TG0 79 +#define MX50_INT_CTI1_TG1 80 +#define MX50_INT_GPU2_IRQ 84 +#define MX50_INT_GPU2_BUSY 85 +#define MX50_INT_UART5 86 +#define MX50_INT_FEC 87 +#define MX50_INT_OWIRE 88 +#define MX50_INT_CTI1_TG2 89 +#define MX50_INT_SJC 90 +#define MX50_INT_DCP_CHAN1_3 91 +#define MX50_INT_DCP_CHAN0 92 +#define MX50_INT_PWM2 94 +#define MX50_INT_RNGB 97 +#define MX50_INT_CTI1_TG3 98 +#define MX50_INT_RAWNAND_BCH 100 +#define MX50_INT_RAWNAND_GPMI 102 +#define MX50_INT_GPIO5_LOW 103 +#define MX50_INT_GPIO5_HIGH 104 +#define MX50_INT_GPIO6_LOW 105 +#define MX50_INT_GPIO6_HIGH 106 +#define MX50_INT_MSHC 109 +#define MX50_INT_APBHDMA_CHAN0 110 +#define MX50_INT_APBHDMA_CHAN1 111 +#define MX50_INT_APBHDMA_CHAN2 112 +#define MX50_INT_APBHDMA_CHAN3 113 +#define MX50_INT_APBHDMA_CHAN4 114 +#define MX50_INT_APBHDMA_CHAN5 115 +#define MX50_INT_APBHDMA_CHAN6 116 +#define MX50_INT_APBHDMA_CHAN7 117 + +#endif /* ifndef __MACH_MX50_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 2af7a10..873807f 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -2,31 +2,6 @@ #define __MACH_MX51_H__ /* - * MX51 memory map: - * - * - * Virt Phys Size What - * --------------------------------------------------------------------------- - * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM) - * 30000000 256M GPU - * 40000000 512M IPU - * fa200000 60000000 1M DEBUG - * fb100000 70000000 1M SPBA 0 - * fb000000 73f00000 1M AIPS 1 - * fb200000 83f00000 1M AIPS 2 - * 8fffc000 16K TZIC (interrupt controller) - * 90000000 256M CSD0 SDRAM/DDR - * a0000000 256M CSD1 SDRAM/DDR - * b0000000 128M CS0 Flash - * b8000000 128M CS1 Flash - * c0000000 128M CS2 Flash - * c8000000 64M CS3 Flash - * cc000000 32M CS4 SRAM - * ce000000 32M CS5 SRAM - * cfff0000 64K NFC (NAND Flash AXI) - */ - -/* * IROM */ #define MX51_IROM_BASE_ADDR 0x0 @@ -36,7 +11,6 @@ * IRAM */ #define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ -#define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000 #define MX51_IRAM_PARTITIONS 16 #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ @@ -45,7 +19,6 @@ #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 #define MX51_DEBUG_BASE_ADDR 0x60000000 -#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000 #define MX51_DEBUG_SIZE SZ_1M #define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) @@ -61,7 +34,6 @@ * SPBA global module enabled #0 */ #define MX51_SPBA0_BASE_ADDR 0x70000000 -#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000 #define MX51_SPBA0_SIZE SZ_1M #define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) @@ -81,7 +53,6 @@ * AIPS 1 */ #define MX51_AIPS1_BASE_ADDR 0x73f00000 -#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000 #define MX51_AIPS1_SIZE SZ_1M #define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) @@ -90,7 +61,7 @@ #define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) #define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) #define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) -#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) +#define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) #define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) #define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) #define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) @@ -109,7 +80,6 @@ * AIPS 2 */ #define MX51_AIPS2_BASE_ADDR 0x83f00000 -#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000 #define MX51_AIPS2_SIZE SZ_1M #define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) @@ -139,7 +109,7 @@ #define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) #define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) #define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) -#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) +#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) #define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) #define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) #define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) @@ -163,16 +133,8 @@ #define MX51_GPU2D_BASE_ADDR 0xd0000000 #define MX51_TZIC_BASE_ADDR 0xe0000000 -#define MX51_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX51_IRAM) ?: \ - IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \ - IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \ - IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX51_AIPS2)) - -/* This is currently used in <mach/debug-macro.S>, but should go away */ -#define MX51_AIPS1_IO_ADDRESS(x) \ - (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT) +#define MX51_IO_P2V(x) IMX_IO_P2V(x) +#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) /* * defines for SPBA modules @@ -261,9 +223,9 @@ #define MX51_DMA_REQ_EMI_WR 32 #define MX51_DMA_REQ_CTI2_1 33 #define MX51_DMA_REQ_EPIT2 34 -#define MX51_DMA_REQ_SSI3_RX2 35 +#define MX51_DMA_REQ_SSI3_RX1 35 #define MX51_DMA_REQ_IPU 36 -#define MX51_DMA_REQ_SSI3_TX2 37 +#define MX51_DMA_REQ_SSI3_TX1 37 #define MX51_DMA_REQ_CSPI_RX 38 #define MX51_DMA_REQ_CSPI_TX 39 #define MX51_DMA_REQ_SDHC3 40 @@ -272,8 +234,8 @@ #define MX51_DMA_REQ_UART3_RX 43 #define MX51_DMA_REQ_UART3_TX 44 #define MX51_DMA_REQ_SPDIF 45 -#define MX51_DMA_REQ_SSI3_RX1 46 -#define MX51_DMA_REQ_SSI3_TX1 47 +#define MX51_DMA_REQ_SSI3_RX0 46 +#define MX51_DMA_REQ_SSI3_TX0 47 /* * Interrupt numbers @@ -289,8 +251,8 @@ #define MX51_MXC_INT_IOMUX 7 #define MX51_INT_NFC 8 #define MX51_MXC_INT_VPU 9 -#define MX51_MXC_INT_IPU_ERR 10 -#define MX51_MXC_INT_IPU_SYN 11 +#define MX51_INT_IPU_ERR 10 +#define MX51_INT_IPU_SYN 11 #define MX51_MXC_INT_GPU 12 #define MX51_MXC_INT_RESV13 13 #define MX51_MXC_INT_USB_H1 14 @@ -375,7 +337,7 @@ #define MX51_MXC_INT_FIRI 93 #define MX51_MXC_INT_PWM2 94 #define MX51_MXC_INT_SLIM_EXP 95 -#define MX51_MXC_INT_SSI3 96 +#define MX51_INT_SSI3 96 #define MX51_MXC_INT_EMI_BOOT 97 #define MX51_MXC_INT_CTI1_TG3 98 #define MX51_MXC_INT_SMC_RX 99 @@ -383,19 +345,6 @@ #define MX51_MXC_INT_EMI_NFC 101 #define MX51_MXC_INT_GPU_IDLE 102 -/* silicon revisions specific to i.MX51 */ -#define MX51_CHIP_REV_1_0 0x10 -#define MX51_CHIP_REV_1_1 0x11 -#define MX51_CHIP_REV_1_2 0x12 -#define MX51_CHIP_REV_1_3 0x13 -#define MX51_CHIP_REV_2_0 0x20 -#define MX51_CHIP_REV_2_1 0x21 -#define MX51_CHIP_REV_2_2 0x22 -#define MX51_CHIP_REV_2_3 0x23 -#define MX51_CHIP_REV_3_0 0x30 -#define MX51_CHIP_REV_3_1 0x31 -#define MX51_CHIP_REV_3_2 0x32 - #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) extern int mx51_revision(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h new file mode 100644 index 0000000..9577cdb --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -0,0 +1,353 @@ +#ifndef __MACH_MX53_H__ +#define __MACH_MX53_H__ + +/* + * IROM + */ +#define MX53_IROM_BASE_ADDR 0x0 +#define MX53_IROM_SIZE SZ_64K + +/* TZIC */ +#define MX53_TZIC_BASE_ADDR 0x0FFFC000 + +/* + * AHCI SATA + */ +#define MX53_SATA_BASE_ADDR 0x10000000 + +/* + * NFC + */ +#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */ +#define MX53_NFC_AXI_SIZE SZ_64K + +/* + * IRAM + */ +#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */ +#define MX53_IRAM_PARTITIONS 16 +#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */ + +/* + * Graphics Memory of GPU + */ +#define MX53_IPU_CTRL_BASE_ADDR 0x18000000 +#define MX53_GPU2D_BASE_ADDR 0x20000000 +#define MX53_GPU_BASE_ADDR 0x30000000 +#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000 + +#define MX53_DEBUG_BASE_ADDR 0x40000000 +#define MX53_DEBUG_SIZE SZ_1M +#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000) +#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000) +#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000) +#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000) +#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000) +#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000) +#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000) +#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000) + +/* + * SPBA global module enabled #0 + */ +#define MX53_SPBA0_BASE_ADDR 0x50000000 +#define MX53_SPBA0_SIZE SZ_1M + +#define MX53_MMC_SDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) +#define MX53_MMC_SDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) +#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) +#define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) +#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) +#define MX53_MMC_SDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) +#define MX53_MMC_SDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) +#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) +#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) +#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) +#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000) +#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000) +#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000) + +/* + * AIPS 1 + */ +#define MX53_AIPS1_BASE_ADDR 0x53F00000 +#define MX53_AIPS1_SIZE SZ_1M + +#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000) +#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000) +#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000) +#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) +#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) +#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) +#define MX53_WDOG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) +#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) +#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) +#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) +#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000) +#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000) +#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000) +#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000) +#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000) +#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000) +#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000) +#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000) +#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000) +#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000) +#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000) +#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000) +#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000) +#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000) +#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000) +#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000) + +/* + * AIPS 2 + */ +#define MX53_AIPS2_BASE_ADDR 0x63F00000 +#define MX53_AIPS2_SIZE SZ_1M + +#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000) +#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000) +#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000) +#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000) +#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000) +#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000) +#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000) +#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000) +#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) +#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) +#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) +#define MX53_CSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) +#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) +#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) +#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) +#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) +#define MX53_CSPI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) +#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) +#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) +#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) +#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000) +#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000) +#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000) +#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000) +#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000) +#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000) +#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00) +#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000) +#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000) +#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000) +#define MX53_MXC_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) +#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000) +#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000) +#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000) +#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000) + +/* + * Memory regions and CS + */ +#define MX53_CSD0_BASE_ADDR 0x90000000 +#define MX53_CSD1_BASE_ADDR 0xA0000000 +#define MX53_CS0_BASE_ADDR 0xB0000000 +#define MX53_CS1_BASE_ADDR 0xB8000000 +#define MX53_CS2_BASE_ADDR 0xC0000000 +#define MX53_CS3_BASE_ADDR 0xC8000000 +#define MX53_CS4_BASE_ADDR 0xCC000000 +#define MX53_CS5_BASE_ADDR 0xCE000000 + +#define MX53_IO_P2V(x) IMX_IO_P2V(x) +#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x)) + +/* + * defines for SPBA modules + */ +#define MX53_SPBA_SDHC1 0x04 +#define MX53_SPBA_SDHC2 0x08 +#define MX53_SPBA_UART3 0x0C +#define MX53_SPBA_CSPI1 0x10 +#define MX53_SPBA_SSI2 0x14 +#define MX53_SPBA_SDHC3 0x20 +#define MX53_SPBA_SDHC4 0x24 +#define MX53_SPBA_SPDIF 0x28 +#define MX53_SPBA_ATA 0x30 +#define MX53_SPBA_SLIM 0x34 +#define MX53_SPBA_HSI2C 0x38 +#define MX53_SPBA_CTRL 0x3C + +/* + * DMA request assignments + */ +#define MX53_DMA_REQ_SSI3_TX1 47 +#define MX53_DMA_REQ_SSI3_RX1 46 +#define MX53_DMA_REQ_SSI3_TX2 45 +#define MX53_DMA_REQ_SSI3_RX2 44 +#define MX53_DMA_REQ_UART3_TX 43 +#define MX53_DMA_REQ_UART3_RX 42 +#define MX53_DMA_REQ_ESAI_TX 41 +#define MX53_DMA_REQ_ESAI_RX 40 +#define MX53_DMA_REQ_CSPI_TX 39 +#define MX53_DMA_REQ_CSPI_RX 38 +#define MX53_DMA_REQ_ASRC_DMA6 37 +#define MX53_DMA_REQ_ASRC_DMA5 36 +#define MX53_DMA_REQ_ASRC_DMA4 35 +#define MX53_DMA_REQ_ASRC_DMA3 34 +#define MX53_DMA_REQ_ASRC_DMA2 33 +#define MX53_DMA_REQ_ASRC_DMA1 32 +#define MX53_DMA_REQ_EMI_WR 31 +#define MX53_DMA_REQ_EMI_RD 30 +#define MX53_DMA_REQ_SSI1_TX1 29 +#define MX53_DMA_REQ_SSI1_RX1 28 +#define MX53_DMA_REQ_SSI1_TX2 27 +#define MX53_DMA_REQ_SSI1_RX2 26 +#define MX53_DMA_REQ_SSI2_TX1 25 +#define MX53_DMA_REQ_SSI2_RX1 24 +#define MX53_DMA_REQ_SSI2_TX2 23 +#define MX53_DMA_REQ_SSI2_RX2 22 +#define MX53_DMA_REQ_I2C2_SDHC2 21 +#define MX53_DMA_REQ_I2C1_SDHC1 20 +#define MX53_DMA_REQ_UART1_TX 19 +#define MX53_DMA_REQ_UART1_RX 18 +#define MX53_DMA_REQ_UART5_TX 17 +#define MX53_DMA_REQ_UART5_RX 16 +#define MX53_DMA_REQ_SPDIF_TX 15 +#define MX53_DMA_REQ_SPDIF_RX 14 +#define MX53_DMA_REQ_UART2_FIRI_TX 13 +#define MX53_DMA_REQ_UART2_FIRI_RX 12 +#define MX53_DMA_REQ_SDHC4 11 +#define MX53_DMA_REQ_I2C3_SDHC3 10 +#define MX53_DMA_REQ_CSPI2_TX 9 +#define MX53_DMA_REQ_CSPI2_RX 8 +#define MX53_DMA_REQ_CSPI1_TX 7 +#define MX53_DMA_REQ_CSPI1_RX 6 +#define MX53_DMA_REQ_IPU 5 +#define MX53_DMA_REQ_ATA_TX_END 4 +#define MX53_DMA_REQ_ATA_UART4_TX 3 +#define MX53_DMA_REQ_ATA_UART4_RX 2 +#define MX53_DMA_REQ_GPC 1 +#define MX53_DMA_REQ_VPU 0 + +/* + * Interrupt numbers + */ +#define MX53_INT_RESV0 0 +#define MX53_INT_MMC_SDHC1 1 +#define MX53_INT_MMC_SDHC2 2 +#define MX53_INT_MMC_SDHC3 3 +#define MX53_INT_MMC_SDHC4 4 +#define MX53_INT_RESV5 5 +#define MX53_INT_SDMA 6 +#define MX53_INT_IOMUX 7 +#define MX53_INT_NFC 8 +#define MX53_INT_VPU 9 +#define MX53_INT_IPU_ERR 10 +#define MX53_INT_IPU_SYN 11 +#define MX53_INT_GPU 12 +#define MX53_INT_RESV13 13 +#define MX53_INT_USB_H1 14 +#define MX53_INT_EMI 15 +#define MX53_INT_USB_H2 16 +#define MX53_INT_USB_H3 17 +#define MX53_INT_USB_OTG 18 +#define MX53_INT_SAHARA_H0 19 +#define MX53_INT_SAHARA_H1 20 +#define MX53_INT_SCC_SMN 21 +#define MX53_INT_SCC_STZ 22 +#define MX53_INT_SCC_SCM 23 +#define MX53_INT_SRTC_NTZ 24 +#define MX53_INT_SRTC_TZ 25 +#define MX53_INT_RTIC 26 +#define MX53_INT_CSU 27 +#define MX53_INT_SATA 28 +#define MX53_INT_SSI1 29 +#define MX53_INT_SSI2 30 +#define MX53_INT_UART1 31 +#define MX53_INT_UART2 32 +#define MX53_INT_UART3 33 +#define MX53_INT_RESV34 34 +#define MX53_INT_RESV35 35 +#define MX53_INT_CSPI1 36 +#define MX53_INT_CSPI2 37 +#define MX53_INT_CSPI 38 +#define MX53_INT_GPT 39 +#define MX53_INT_EPIT1 40 +#define MX53_INT_EPIT2 41 +#define MX53_INT_GPIO1_INT7 42 +#define MX53_INT_GPIO1_INT6 43 +#define MX53_INT_GPIO1_INT5 44 +#define MX53_INT_GPIO1_INT4 45 +#define MX53_INT_GPIO1_INT3 46 +#define MX53_INT_GPIO1_INT2 47 +#define MX53_INT_GPIO1_INT1 48 +#define MX53_INT_GPIO1_INT0 49 +#define MX53_INT_GPIO1_LOW 50 +#define MX53_INT_GPIO1_HIGH 51 +#define MX53_INT_GPIO2_LOW 52 +#define MX53_INT_GPIO2_HIGH 53 +#define MX53_INT_GPIO3_LOW 54 +#define MX53_INT_GPIO3_HIGH 55 +#define MX53_INT_GPIO4_LOW 56 +#define MX53_INT_GPIO4_HIGH 57 +#define MX53_INT_WDOG1 58 +#define MX53_INT_WDOG2 59 +#define MX53_INT_KPP 60 +#define MX53_INT_PWM1 61 +#define MX53_INT_I2C1 62 +#define MX53_INT_I2C2 63 +#define MX53_INT_I2C3 64 +#define MX53_INT_RESV65 65 +#define MX53_INT_RESV66 66 +#define MX53_INT_SPDIF 67 +#define MX53_INT_SIM_DAT 68 +#define MX53_INT_IIM 69 +#define MX53_INT_ATA 70 +#define MX53_INT_CCM1 71 +#define MX53_INT_CCM2 72 +#define MX53_INT_GPC1 73 +#define MX53_INT_GPC2 74 +#define MX53_INT_SRC 75 +#define MX53_INT_NM 76 +#define MX53_INT_PMU 77 +#define MX53_INT_CTI_IRQ 78 +#define MX53_INT_CTI1_TG0 79 +#define MX53_INT_CTI1_TG1 80 +#define MX53_INT_ESAI 81 +#define MX53_INT_CAN1 82 +#define MX53_INT_CAN2 83 +#define MX53_INT_GPU2_IRQ 84 +#define MX53_INT_GPU2_BUSY 85 +#define MX53_INT_RESV86 86 +#define MX53_INT_FEC 87 +#define MX53_INT_OWIRE 88 +#define MX53_INT_CTI1_TG2 89 +#define MX53_INT_SJC 90 +#define MX53_INT_TVE 92 +#define MX53_INT_FIRI 93 +#define MX53_INT_PWM2 94 +#define MX53_INT_SLIM_EXP 95 +#define MX53_INT_SSI3 96 +#define MX53_INT_EMI_BOOT 97 +#define MX53_INT_CTI1_TG3 98 +#define MX53_INT_SMC_RX 99 +#define MX53_INT_VPU_IDLE 100 +#define MX53_INT_EMI_NFC 101 +#define MX53_INT_GPU_IDLE 102 +#define MX53_INT_GPIO5_LOW 103 +#define MX53_INT_GPIO5_HIGH 104 +#define MX53_INT_GPIO6_LOW 105 +#define MX53_INT_GPIO6_HIGH 106 +#define MX53_INT_GPIO7_LOW 107 +#define MX53_INT_GPIO7_HIGH 108 + +/* silicon revisions specific to i.MX53 */ +#define MX53_CHIP_REV_1_0 0x10 +#define MX53_CHIP_REV_1_1 0x11 +#define MX53_CHIP_REV_1_2 0x12 +#define MX53_CHIP_REV_1_3 0x13 +#define MX53_CHIP_REV_2_0 0x20 +#define MX53_CHIP_REV_2_1 0x21 +#define MX53_CHIP_REV_2_2 0x22 +#define MX53_CHIP_REV_2_3 0x23 +#define MX53_CHIP_REV_3_0 0x30 +#define MX53_CHIP_REV_3_1 0x31 +#define MX53_CHIP_REV_3_2 0x32 + +#endif /* ifndef __MACH_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index a42c720..04c7a26 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -32,9 +32,25 @@ #define MXC_CPU_MX27 27 #define MXC_CPU_MX31 31 #define MXC_CPU_MX35 35 +#define MXC_CPU_MX50 50 #define MXC_CPU_MX51 51 +#define MXC_CPU_MX53 53 #define MXC_CPU_MXC91231 91231 +#define IMX_CHIP_REVISION_1_0 0x10 +#define IMX_CHIP_REVISION_1_1 0x11 +#define IMX_CHIP_REVISION_1_2 0x12 +#define IMX_CHIP_REVISION_1_3 0x13 +#define IMX_CHIP_REVISION_2_0 0x20 +#define IMX_CHIP_REVISION_2_1 0x21 +#define IMX_CHIP_REVISION_2_2 0x22 +#define IMX_CHIP_REVISION_2_3 0x23 +#define IMX_CHIP_REVISION_3_0 0x30 +#define IMX_CHIP_REVISION_3_1 0x31 +#define IMX_CHIP_REVISION_3_2 0x32 +#define IMX_CHIP_REVISION_3_3 0x33 +#define IMX_CHIP_REVISION_UNKNOWN 0xff + #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; #endif @@ -111,7 +127,19 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx35() (0) #endif -#ifdef CONFIG_ARCH_MX5 +#ifdef CONFIG_ARCH_MX50 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX50 +# endif +# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50) +#else +# define cpu_is_mx50() (0) +#endif + +#ifdef CONFIG_ARCH_MX51 # ifdef mxc_cpu_type # undef mxc_cpu_type # define mxc_cpu_type __mxc_cpu_type @@ -123,6 +151,18 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx51() (0) #endif +#ifdef CONFIG_ARCH_MX53 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX53 +# endif +# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) +#else +# define cpu_is_mx53() (0) +#endif + #ifdef CONFIG_ARCH_MXC91231 # ifdef mxc_cpu_type # undef mxc_cpu_type diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 0ca3101..765190f 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h @@ -21,14 +21,12 @@ * L2CC */ #define MXC91231_L2CC_BASE_ADDR 0x30000000 -#define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000 #define MXC91231_L2CC_SIZE SZ_64K /* * AIPS 1 */ #define MXC91231_AIPS1_BASE_ADDR 0x43F00000 -#define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000 #define MXC91231_AIPS1_SIZE SZ_1M #define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR @@ -53,7 +51,6 @@ * AIPS 2 */ #define MXC91231_AIPS2_BASE_ADDR 0x53F00000 -#define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000 #define MXC91231_AIPS2_SIZE SZ_1M #define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) @@ -79,7 +76,6 @@ * SPBA global module 0 */ #define MXC91231_SPBA0_BASE_ADDR 0x50000000 -#define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000 #define MXC91231_SPBA0_SIZE SZ_1M #define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) @@ -109,7 +105,6 @@ * SPBA global module 1 */ #define MXC91231_SPBA1_BASE_ADDR 0x52000000 -#define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000 #define MXC91231_SPBA1_SIZE SZ_1M #define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) @@ -144,18 +139,15 @@ * ROMP and AVIC */ #define MXC91231_ROMP_BASE_ADDR 0x60000000 -#define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000 #define MXC91231_ROMP_SIZE SZ_64K #define MXC91231_AVIC_BASE_ADDR 0x68000000 -#define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000 #define MXC91231_AVIC_SIZE SZ_64K /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 -#define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000 #define MXC91231_X_MEMC_SIZE SZ_64K #define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) @@ -183,19 +175,10 @@ /* * This macro defines the physical to virtual address mapping for all the * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. If the physical address is not mapped, - * it returns 0. + * and returning the virtual address. */ - -#define MXC91231_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \ - IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \ - IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \ - IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \ - IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \ - IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \ - IMX_IO_ADDRESS(x, MXC91231_AIPS2)) +#define MXC91231_IO_P2V(x) IMX_IO_P2V(x) +#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x)) /* * Interrupt numbers diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h index 7fc5f99..a523a40 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h +++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h @@ -31,6 +31,7 @@ #define MXC_USBCTRL_OFFSET 0 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc +#define MXC_USBH2CTRL_OFFSET 0x14 #define MX5_USBOTHER_REGS_OFFSET 0x800 diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h index 9be1122..913e043 100644 --- a/arch/arm/plat-mxc/include/mach/sdma.h +++ b/arch/arm/plat-mxc/include/mach/sdma.h @@ -2,16 +2,62 @@ #define __MACH_MXC_SDMA_H__ /** + * struct sdma_script_start_addrs - SDMA script start pointers + * + * start addresses of the different functions in the physical + * address space of the SDMA engine. + */ +struct sdma_script_start_addrs { + s32 ap_2_ap_addr; + s32 ap_2_bp_addr; + s32 ap_2_ap_fixed_addr; + s32 bp_2_ap_addr; + s32 loopback_on_dsp_side_addr; + s32 mcu_interrupt_only_addr; + s32 firi_2_per_addr; + s32 firi_2_mcu_addr; + s32 per_2_firi_addr; + s32 mcu_2_firi_addr; + s32 uart_2_per_addr; + s32 uart_2_mcu_addr; + s32 per_2_app_addr; + s32 mcu_2_app_addr; + s32 per_2_per_addr; + s32 uartsh_2_per_addr; + s32 uartsh_2_mcu_addr; + s32 per_2_shp_addr; + s32 mcu_2_shp_addr; + s32 ata_2_mcu_addr; + s32 mcu_2_ata_addr; + s32 app_2_per_addr; + s32 app_2_mcu_addr; + s32 shp_2_per_addr; + s32 shp_2_mcu_addr; + s32 mshc_2_mcu_addr; + s32 mcu_2_mshc_addr; + s32 spdif_2_mcu_addr; + s32 mcu_2_spdif_addr; + s32 asrc_2_mcu_addr; + s32 ext_mem_2_ipu_addr; + s32 descrambler_addr; + s32 dptc_dvfs_addr; + s32 utra_addr; + s32 ram_code_start_addr; +}; + +/** * struct sdma_platform_data - platform specific data for SDMA engine * * @sdma_version The version of this SDMA engine * @cpu_name used to generate the firmware name * @to_version CPU Tape out version + * @script_addrs SDMA scripts addresses in SDMA ROM */ struct sdma_platform_data { int sdma_version; char *cpu_name; int to_version; + struct sdma_script_start_addrs *script_addrs; }; #endif /* __MACH_MXC_SDMA_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 9dd9c20..3a70ebf 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -63,6 +63,8 @@ static inline void flush(void) #define MX3X_UART1_BASE_ADDR 0x43F90000 #define MX3X_UART2_BASE_ADDR 0x43F94000 #define MX51_UART1_BASE_ADDR 0x73fbc000 +#define MX50_UART1_BASE_ADDR 0x53fbc000 +#define MX53_UART1_BASE_ADDR 0x53fbc000 static __inline__ void __arch_decomp_setup(unsigned long arch_id) { @@ -102,6 +104,12 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_EUKREA_CPUIMX51SD: uart_base = MX51_UART1_BASE_ADDR; break; + case MACH_TYPE_MX50_RDP: + uart_base = MX50_UART1_BASE_ADDR; + break; + case MACH_TYPE_MX53_EVK: + uart_base = MX53_UART1_BASE_ADDR; + break; default: break; } diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c index b318c6a..99a9cdb 100644 --- a/arch/arm/plat-mxc/iomux-v3.c +++ b/arch/arm/plat-mxc/iomux-v3.c @@ -32,31 +32,38 @@ static void __iomem *base; /* - * setups a single pad in the iomuxer + * configures a single pad in the iomuxer */ -int mxc_iomux_v3_setup_pad(struct pad_desc *pad) +int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad) { - if (pad->mux_ctrl_ofs) - __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs); + u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; + u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; + u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; + u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; + u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; + u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; - if (pad->select_input_ofs) - __raw_writel(pad->select_input, - base + pad->select_input_ofs); + if (mux_ctrl_ofs) + __raw_writel(mux_mode, base + mux_ctrl_ofs); + + if (sel_input_ofs) + __raw_writel(sel_input, base + sel_input_ofs); + + if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) + __raw_writel(pad_ctrl, base + pad_ctrl_ofs); - if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs) - __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs); return 0; } EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); -int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count) +int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) { - struct pad_desc *p = pad_list; + iomux_v3_cfg_t *p = pad_list; int i; int ret; for (i = 0; i < count; i++) { - ret = mxc_iomux_v3_setup_pad(p); + ret = mxc_iomux_v3_setup_pad(*p); if (ret) return ret; p++; diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c new file mode 100644 index 0000000..0c799ac --- /dev/null +++ b/arch/arm/plat-mxc/irq-common.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) BitBox Ltd 2010 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/module.h> +#include <linux/irq.h> + +#include "irq-common.h" + +int imx_irq_set_priority(unsigned char irq, unsigned char prio) +{ + struct mxc_irq_chip *chip; + struct irq_chip *base; + int ret; + + ret = -ENOSYS; + + base = get_irq_chip(irq); + if (base) { + chip = container_of(base, struct mxc_irq_chip, base); + if (chip->set_priority) + ret = chip->set_priority(irq, prio); + } + + return ret; +} +EXPORT_SYMBOL(imx_irq_set_priority); + +int mxc_set_irq_fiq(unsigned int irq, unsigned int type) +{ + struct mxc_irq_chip *chip; + struct irq_chip *base; + int ret; + + ret = -ENOSYS; + + base = get_irq_chip(irq); + if (base) { + chip = container_of(base, struct mxc_irq_chip, base); + if (chip->set_irq_fiq) + ret = chip->set_irq_fiq(irq, type); + } + + return ret; +} +EXPORT_SYMBOL(mxc_set_irq_fiq); diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h new file mode 100644 index 0000000..7203543 --- /dev/null +++ b/arch/arm/plat-mxc/irq-common.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) BitBox Ltd 2010 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __PLAT_MXC_IRQ_COMMON_H__ +#define __PLAT_MXC_IRQ_COMMON_H__ + +struct mxc_irq_chip +{ + struct irq_chip base; + int (*set_priority)(unsigned char irq, unsigned char prio); + int (*set_irq_fiq)(unsigned int irq, unsigned int type); +}; + +#endif diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 925bce4..3455fc0 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -26,6 +26,7 @@ #include <mach/common.h> #include <asm/proc-fns.h> #include <asm/system.h> +#include <asm/mach-types.h> static void __iomem *wdog_base; @@ -42,12 +43,19 @@ void arch_reset(char mode, const char *cmd) return; } #endif +#ifdef CONFIG_MACH_MX51_EFIKAMX + if (machine_is_mx51_efikamx()) { + mx51_efikamx_reset(); + return; + } +#endif + if (cpu_is_mx1()) { wcr_enable = (1 << 0); } else { struct clk *clk; - clk = clk_get_sys("imx-wdt.0", NULL); + clk = clk_get_sys("imx2-wdt.0", NULL); if (!IS_ERR(clk)) clk_enable(clk); wcr_enable = (1 << 2); diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 3703ab2..e69ed8a 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -21,6 +21,8 @@ #include <mach/hardware.h> #include <mach/common.h> +#include "irq-common.h" + /* ***************************************** * TZIC Registers * @@ -47,6 +49,25 @@ void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ +#ifdef CONFIG_FIQ +static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) +{ + unsigned int index, mask, value; + + index = irq >> 5; + if (unlikely(index >= 4)) + return -EINVAL; + mask = 1U << (irq & 0x1F); + + value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask; + if (type) + value &= ~mask; + __raw_writel(value, tzic_base + TZIC_INTSEC0(index)); + + return 0; +} +#endif + /** * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC * @@ -104,12 +125,17 @@ static int tzic_set_wake_irq(unsigned int irq, unsigned int enable) return 0; } -static struct irq_chip mxc_tzic_chip = { - .name = "MXC_TZIC", - .ack = tzic_mask_irq, - .mask = tzic_mask_irq, - .unmask = tzic_unmask_irq, - .set_wake = tzic_set_wake_irq, +static struct mxc_irq_chip mxc_tzic_chip = { + .base = { + .name = "MXC_TZIC", + .ack = tzic_mask_irq, + .mask = tzic_mask_irq, + .unmask = tzic_unmask_irq, + .set_wake = tzic_set_wake_irq, + }, +#ifdef CONFIG_FIQ + .set_irq_fiq = tzic_set_irq_fiq, +#endif }; /* @@ -141,10 +167,16 @@ void __init tzic_init_irq(void __iomem *irqbase) /* all IRQ no FIQ Warning :: No selection */ for (i = 0; i < MXC_INTERNAL_IRQS; i++) { - set_irq_chip(i, &mxc_tzic_chip); + set_irq_chip(i, &mxc_tzic_chip.base); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } + +#ifdef CONFIG_FIQ + /* Initialize FIQ */ + init_FIQ(); +#endif + pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); } diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index 85e6fd21..eda4e3a 100644 --- a/arch/arm/plat-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c @@ -119,7 +119,7 @@ static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, } static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, - pin_cfg_t cfg) + pin_cfg_t cfg, bool sleep) { static const char *afnames[] = { [NMK_GPIO_ALT_GPIO] = "GPIO", @@ -145,11 +145,34 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, int output = PIN_DIR(cfg); int val = PIN_VAL(cfg); - dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s (%s%s)\n", - pin, afnames[af], pullnames[pull], slpmnames[slpm], + dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", + pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], output ? "output " : "input", output ? (val ? "high" : "low") : ""); + if (sleep) { + int slpm_pull = PIN_SLPM_PULL(cfg); + int slpm_output = PIN_SLPM_DIR(cfg); + int slpm_val = PIN_SLPM_VAL(cfg); + + /* + * The SLPM_* values are normal values + 1 to allow zero to + * mean "same as normal". + */ + if (slpm_pull) + pull = slpm_pull - 1; + if (slpm_output) + output = slpm_output - 1; + if (slpm_val) + val = slpm_val - 1; + + dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", + pin, + slpm_pull ? pullnames[pull] : "same", + slpm_output ? (output ? "output" : "input") : "same", + slpm_val ? (val ? "high" : "low") : "same"); + } + if (output) __nmk_gpio_make_output(nmk_chip, offset, val); else { @@ -175,7 +198,7 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, * side-effects. The gpio can be manipulated later using standard GPIO API * calls. */ -int nmk_config_pin(pin_cfg_t cfg) +int nmk_config_pin(pin_cfg_t cfg, bool sleep) { struct nmk_gpio_chip *nmk_chip; int gpio = PIN_NUM(cfg); @@ -186,7 +209,7 @@ int nmk_config_pin(pin_cfg_t cfg) return -EINVAL; spin_lock_irqsave(&nmk_chip->lock, flags); - __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg); + __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg, sleep); spin_unlock_irqrestore(&nmk_chip->lock, flags); return 0; @@ -207,7 +230,7 @@ int nmk_config_pins(pin_cfg_t *cfgs, int num) int i; for (i = 0; i < num; i++) { - int ret = nmk_config_pin(cfgs[i]); + ret = nmk_config_pin(cfgs[i], false); if (ret) break; } @@ -216,6 +239,21 @@ int nmk_config_pins(pin_cfg_t *cfgs, int num) } EXPORT_SYMBOL(nmk_config_pins); +int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) +{ + int ret = 0; + int i; + + for (i = 0; i < num; i++) { + ret = nmk_config_pin(cfgs[i], true); + if (ret) + break; + } + + return ret; +} +EXPORT_SYMBOL(nmk_config_pins_sleep); + /** * nmk_gpio_set_slpm() - configure the sleep mode of a pin * @gpio: pin number @@ -634,7 +672,7 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) chip = &nmk_chip->chip; chip->base = pdata->first_gpio; - chip->label = pdata->name; + chip->label = pdata->name ?: dev_name(&dev->dev); chip->dev = &dev->dev; chip->owner = THIS_MODULE; diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h index 8c5ae3f..05a3936 100644 --- a/arch/arm/plat-nomadik/include/plat/pincfg.h +++ b/arch/arm/plat-nomadik/include/plat/pincfg.h @@ -19,16 +19,22 @@ * bit 9..10 - Alternate Function Selection * bit 11..12 - Pull up/down state * bit 13 - Sleep mode behaviour - * bit 14 - (sleep mode) Direction - * bit 15 - (sleep mode) Value (if output) + * bit 14 - Direction + * bit 15 - Value (if output) + * bit 16..18 - SLPM pull up/down state + * bit 19..20 - SLPM direction + * bit 21..22 - SLPM Value (if output) * * to facilitate the definition, the following macros are provided * * PIN_CFG_DEFAULT - default config (0): * pull up/down = disabled * sleep mode = input/wakeup - * (sleep mode) direction = input - * (sleep mode) value = low + * direction = input + * value = low + * SLPM direction = same as normal + * SLPM pull = same as normal + * SLPM value = same as normal * * PIN_CFG - default config with alternate function * PIN_CFG_PULL - default config with alternate function and pull up/down @@ -75,30 +81,64 @@ typedef unsigned long pin_cfg_t; #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) -/* Shortcuts. Use these instead of separate DIR and VAL. */ -#define PIN_INPUT PIN_DIR_INPUT +#define PIN_SLPM_PULL_SHIFT 16 +#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL(x) \ + (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_NONE \ + ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_UP \ + ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_DOWN \ + ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) + +#define PIN_SLPM_DIR_SHIFT 19 +#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR(x) \ + (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) + +#define PIN_SLPM_VAL_SHIFT 21 +#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL(x) \ + (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) + +/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ +#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) +#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) +#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) -/* - * These are the same as the ones above, but should make more sense to the - * reader when seen along with a setting a pin to AF mode. - */ -#define PIN_SLPM_INPUT PIN_INPUT -#define PIN_SLPM_OUTPUT_LOW PIN_OUTPUT_LOW -#define PIN_SLPM_OUTPUT_HIGH PIN_OUTPUT_HIGH +#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) +#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) +#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) +#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) +#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) -#define PIN_CFG_DEFAULT (PIN_PULL_NONE | PIN_SLPM_INPUT) +#define PIN_CFG_DEFAULT (0) #define PIN_CFG(num, alt) \ (PIN_CFG_DEFAULT |\ (PIN_NUM(num) | PIN_##alt)) +#define PIN_CFG_INPUT(num, alt, pull) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) + +#define PIN_CFG_OUTPUT(num, alt, val) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) + #define PIN_CFG_PULL(num, alt, pull) \ ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\ (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull)) -extern int nmk_config_pin(pin_cfg_t cfg); +extern int nmk_config_pin(pin_cfg_t cfg, bool sleep); extern int nmk_config_pins(pin_cfg_t *cfgs, int num); +extern int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num); #endif diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile index 4aacdd1..3aca5ba 100644 --- a/arch/arm/plat-pxa/Makefile +++ b/arch/arm/plat-pxa/Makefile @@ -6,6 +6,7 @@ obj-y := dma.o obj-$(CONFIG_GENERIC_GPIO) += gpio.o obj-$(CONFIG_PXA3xx) += mfp.o +obj-$(CONFIG_PXA95x) += mfp.o obj-$(CONFIG_ARCH_MMP) += mfp.o obj-$(CONFIG_HAVE_PWM) += pwm.o diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h index 9e604c8..75f6564 100644 --- a/arch/arm/plat-pxa/include/plat/mfp.h +++ b/arch/arm/plat-pxa/include/plat/mfp.h @@ -423,7 +423,7 @@ typedef unsigned long mfp_cfg_t; ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) -#if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP) +#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) || defined(CONFIG_ARCH_MMP) /* * each MFP pin will have a MFPR register, since the offset of the * register varies between processors, the processor specific code @@ -470,6 +470,6 @@ void mfp_write(int mfp, unsigned long mfpr_val); void mfp_config(unsigned long *mfp_cfgs, int num); void mfp_config_run(void); void mfp_config_lpm(void); -#endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */ +#endif /* CONFIG_PXA3xx || CONFIG_PXA95x || CONFIG_ARCH_MMP */ #endif /* __ASM_PLAT_MFP_H */ diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index d0602dd..d5a5d4d 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -273,50 +273,6 @@ struct sdma_channel { #define MXC_SDMA_MIN_PRIORITY 1 #define MXC_SDMA_MAX_PRIORITY 7 -/** - * struct sdma_script_start_addrs - SDMA script start pointers - * - * start addresses of the different functions in the physical - * address space of the SDMA engine. - */ -struct sdma_script_start_addrs { - u32 ap_2_ap_addr; - u32 ap_2_bp_addr; - u32 ap_2_ap_fixed_addr; - u32 bp_2_ap_addr; - u32 loopback_on_dsp_side_addr; - u32 mcu_interrupt_only_addr; - u32 firi_2_per_addr; - u32 firi_2_mcu_addr; - u32 per_2_firi_addr; - u32 mcu_2_firi_addr; - u32 uart_2_per_addr; - u32 uart_2_mcu_addr; - u32 per_2_app_addr; - u32 mcu_2_app_addr; - u32 per_2_per_addr; - u32 uartsh_2_per_addr; - u32 uartsh_2_mcu_addr; - u32 per_2_shp_addr; - u32 mcu_2_shp_addr; - u32 ata_2_mcu_addr; - u32 mcu_2_ata_addr; - u32 app_2_per_addr; - u32 app_2_mcu_addr; - u32 shp_2_per_addr; - u32 shp_2_mcu_addr; - u32 mshc_2_mcu_addr; - u32 mcu_2_mshc_addr; - u32 spdif_2_mcu_addr; - u32 mcu_2_spdif_addr; - u32 asrc_2_mcu_addr; - u32 ext_mem_2_ipu_addr; - u32 descrambler_addr; - u32 dptc_dvfs_addr; - u32 utra_addr; - u32 ram_code_start_addr; -}; - #define SDMA_FIRMWARE_MAGIC 0x414d4453 /** @@ -1127,8 +1083,74 @@ static void sdma_issue_pending(struct dma_chan *chan) */ } -static int __init sdma_init(struct sdma_engine *sdma, - void *ram_code, int ram_code_size) +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 + +static void sdma_add_scripts(struct sdma_engine *sdma, + const struct sdma_script_start_addrs *addr) +{ + s32 *addr_arr = (u32 *)addr; + s32 *saddr_arr = (u32 *)sdma->script_addrs; + int i; + + for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) + if (addr_arr[i] > 0) + saddr_arr[i] = addr_arr[i]; +} + +static int __init sdma_get_firmware(struct sdma_engine *sdma, + const char *cpu_name, int to_version) +{ + const struct firmware *fw; + char *fwname; + const struct sdma_firmware_header *header; + int ret; + const struct sdma_script_start_addrs *addr; + unsigned short *ram_code; + + fwname = kasprintf(GFP_KERNEL, "sdma-%s-to%d.bin", cpu_name, to_version); + if (!fwname) + return -ENOMEM; + + ret = request_firmware(&fw, fwname, sdma->dev); + if (ret) { + kfree(fwname); + return ret; + } + kfree(fwname); + + if (fw->size < sizeof(*header)) + goto err_firmware; + + header = (struct sdma_firmware_header *)fw->data; + + if (header->magic != SDMA_FIRMWARE_MAGIC) + goto err_firmware; + if (header->ram_code_start + header->ram_code_size > fw->size) + goto err_firmware; + + addr = (void *)header + header->script_addrs_start; + ram_code = (void *)header + header->ram_code_start; + + clk_enable(sdma->clk); + /* download the RAM image for SDMA */ + sdma_load_script(sdma, ram_code, + header->ram_code_size, + sdma->script_addrs->ram_code_start_addr); + clk_disable(sdma->clk); + + sdma_add_scripts(sdma, addr); + + dev_info(sdma->dev, "loaded firmware %d.%d\n", + header->version_major, + header->version_minor); + +err_firmware: + release_firmware(fw); + + return ret; +} + +static int __init sdma_init(struct sdma_engine *sdma) { int i, ret; dma_addr_t ccb_phys; @@ -1192,11 +1214,6 @@ static int __init sdma_init(struct sdma_engine *sdma, __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR); - /* download the RAM image for SDMA */ - sdma_load_script(sdma, ram_code, - ram_code_size, - sdma->script_addrs->ram_code_start_addr); - /* Set bits of CONFIG register with given context switching mode */ __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); @@ -1216,14 +1233,9 @@ err_dma_alloc: static int __init sdma_probe(struct platform_device *pdev) { int ret; - const struct firmware *fw; - const struct sdma_firmware_header *header; - const struct sdma_script_start_addrs *addr; int irq; - unsigned short *ram_code; struct resource *iores; struct sdma_platform_data *pdata = pdev->dev.platform_data; - char *fwname; int i; dma_cap_mask_t mask; struct sdma_engine *sdma; @@ -1262,38 +1274,9 @@ static int __init sdma_probe(struct platform_device *pdev) if (ret) goto err_request_irq; - fwname = kasprintf(GFP_KERNEL, "sdma-%s-to%d.bin", - pdata->cpu_name, pdata->to_version); - if (!fwname) { - ret = -ENOMEM; - goto err_cputype; - } - - ret = request_firmware(&fw, fwname, &pdev->dev); - if (ret) { - dev_err(&pdev->dev, "request firmware \"%s\" failed with %d\n", - fwname, ret); - kfree(fwname); - goto err_cputype; - } - kfree(fwname); - - if (fw->size < sizeof(*header)) - goto err_firmware; - - header = (struct sdma_firmware_header *)fw->data; - - if (header->magic != SDMA_FIRMWARE_MAGIC) - goto err_firmware; - if (header->ram_code_start + header->ram_code_size > fw->size) - goto err_firmware; - - addr = (void *)header + header->script_addrs_start; - ram_code = (void *)header + header->ram_code_start; - sdma->script_addrs = kmalloc(sizeof(*addr), GFP_KERNEL); + sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); if (!sdma->script_addrs) - goto err_firmware; - memcpy(sdma->script_addrs, addr, sizeof(*addr)); + goto err_alloc; sdma->version = pdata->sdma_version; @@ -1316,10 +1299,15 @@ static int __init sdma_probe(struct platform_device *pdev) list_add_tail(&sdmac->chan.device_node, &sdma->dma_device.channels); } - ret = sdma_init(sdma, ram_code, header->ram_code_size); + ret = sdma_init(sdma); if (ret) goto err_init; + if (pdata->script_addrs) + sdma_add_scripts(sdma, pdata->script_addrs); + + sdma_get_firmware(sdma, pdata->cpu_name, pdata->to_version); + sdma->dma_device.dev = &pdev->dev; sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; @@ -1336,10 +1324,6 @@ static int __init sdma_probe(struct platform_device *pdev) goto err_init; } - dev_info(&pdev->dev, "initialized (firmware %d.%d)\n", - header->version_major, - header->version_minor); - /* request channel 0. This is an internal control channel * to the SDMA engine and not available to clients. */ @@ -1347,15 +1331,13 @@ static int __init sdma_probe(struct platform_device *pdev) dma_cap_set(DMA_SLAVE, mask); dma_request_channel(mask, NULL, NULL); - release_firmware(fw); + dev_info(sdma->dev, "initialized\n"); return 0; err_init: kfree(sdma->script_addrs); -err_firmware: - release_firmware(fw); -err_cputype: +err_alloc: free_irq(irq, sdma); err_request_irq: iounmap(sdma->regs); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 3143ac7..082495b 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -230,11 +230,11 @@ config GPIO_STMPE This enables support for the GPIOs found on the STMPE I/O Expanders. -config GPIO_TC35892 - bool "TC35892 GPIOs" - depends on MFD_TC35892 +config GPIO_TC3589X + bool "TC3589X GPIOs" + depends on MFD_TC3589X help - This enables support for the GPIOs found on the TC35892 + This enables support for the GPIOs found on the TC3589X I/O Expander. config GPIO_TWL4030 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index bdf3dde..39bfd7a 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -24,7 +24,7 @@ obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o obj-$(CONFIG_GPIO_PCH) += pch_gpio.o obj-$(CONFIG_GPIO_PL061) += pl061.o obj-$(CONFIG_GPIO_STMPE) += stmpe-gpio.o -obj-$(CONFIG_GPIO_TC35892) += tc35892-gpio.o +obj-$(CONFIG_GPIO_TC3589X) += tc3589x-gpio.o obj-$(CONFIG_GPIO_TIMBERDALE) += timbgpio.o obj-$(CONFIG_GPIO_TWL4030) += twl4030-gpio.o obj-$(CONFIG_GPIO_UCB1400) += ucb1400_gpio.o diff --git a/drivers/gpio/tc35892-gpio.c b/drivers/gpio/tc35892-gpio.c deleted file mode 100644 index 7e10c93..0000000 --- a/drivers/gpio/tc35892-gpio.c +++ /dev/null @@ -1,389 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License Terms: GNU General Public License, version 2 - * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - */ - -#include <linux/module.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/gpio.h> -#include <linux/irq.h> -#include <linux/interrupt.h> -#include <linux/mfd/tc35892.h> - -/* - * These registers are modified under the irq bus lock and cached to avoid - * unnecessary writes in bus_sync_unlock. - */ -enum { REG_IBE, REG_IEV, REG_IS, REG_IE }; - -#define CACHE_NR_REGS 4 -#define CACHE_NR_BANKS 3 - -struct tc35892_gpio { - struct gpio_chip chip; - struct tc35892 *tc35892; - struct device *dev; - struct mutex irq_lock; - - int irq_base; - - /* Caches of interrupt control registers for bus_lock */ - u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; - u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; -}; - -static inline struct tc35892_gpio *to_tc35892_gpio(struct gpio_chip *chip) -{ - return container_of(chip, struct tc35892_gpio, chip); -} - -static int tc35892_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip); - struct tc35892 *tc35892 = tc35892_gpio->tc35892; - u8 reg = TC35892_GPIODATA0 + (offset / 8) * 2; - u8 mask = 1 << (offset % 8); - int ret; - - ret = tc35892_reg_read(tc35892, reg); - if (ret < 0) - return ret; - - return ret & mask; -} - -static void tc35892_gpio_set(struct gpio_chip *chip, unsigned offset, int val) -{ - struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip); - struct tc35892 *tc35892 = tc35892_gpio->tc35892; - u8 reg = TC35892_GPIODATA0 + (offset / 8) * 2; - unsigned pos = offset % 8; - u8 data[] = {!!val << pos, 1 << pos}; - - tc35892_block_write(tc35892, reg, ARRAY_SIZE(data), data); -} - -static int tc35892_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int val) -{ - struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip); - struct tc35892 *tc35892 = tc35892_gpio->tc35892; - u8 reg = TC35892_GPIODIR0 + offset / 8; - unsigned pos = offset % 8; - - tc35892_gpio_set(chip, offset, val); - - return tc35892_set_bits(tc35892, reg, 1 << pos, 1 << pos); -} - -static int tc35892_gpio_direction_input(struct gpio_chip *chip, - unsigned offset) -{ - struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip); - struct tc35892 *tc35892 = tc35892_gpio->tc35892; - u8 reg = TC35892_GPIODIR0 + offset / 8; - unsigned pos = offset % 8; - - return tc35892_set_bits(tc35892, reg, 1 << pos, 0); -} - -static int tc35892_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct tc35892_gpio *tc35892_gpio = to_tc35892_gpio(chip); - - return tc35892_gpio->irq_base + offset; -} - -static struct gpio_chip template_chip = { - .label = "tc35892", - .owner = THIS_MODULE, - .direction_input = tc35892_gpio_direction_input, - .get = tc35892_gpio_get, - .direction_output = tc35892_gpio_direction_output, - .set = tc35892_gpio_set, - .to_irq = tc35892_gpio_to_irq, - .can_sleep = 1, -}; - -static int tc35892_gpio_irq_set_type(unsigned int irq, unsigned int type) -{ - struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq); - int offset = irq - tc35892_gpio->irq_base; - int regoffset = offset / 8; - int mask = 1 << (offset % 8); - - if (type == IRQ_TYPE_EDGE_BOTH) { - tc35892_gpio->regs[REG_IBE][regoffset] |= mask; - return 0; - } - - tc35892_gpio->regs[REG_IBE][regoffset] &= ~mask; - - if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) - tc35892_gpio->regs[REG_IS][regoffset] |= mask; - else - tc35892_gpio->regs[REG_IS][regoffset] &= ~mask; - - if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) - tc35892_gpio->regs[REG_IEV][regoffset] |= mask; - else - tc35892_gpio->regs[REG_IEV][regoffset] &= ~mask; - - return 0; -} - -static void tc35892_gpio_irq_lock(unsigned int irq) -{ - struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq); - - mutex_lock(&tc35892_gpio->irq_lock); -} - -static void tc35892_gpio_irq_sync_unlock(unsigned int irq) -{ - struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq); - struct tc35892 *tc35892 = tc35892_gpio->tc35892; - static const u8 regmap[] = { - [REG_IBE] = TC35892_GPIOIBE0, - [REG_IEV] = TC35892_GPIOIEV0, - [REG_IS] = TC35892_GPIOIS0, - [REG_IE] = TC35892_GPIOIE0, - }; - int i, j; - - for (i = 0; i < CACHE_NR_REGS; i++) { - for (j = 0; j < CACHE_NR_BANKS; j++) { - u8 old = tc35892_gpio->oldregs[i][j]; - u8 new = tc35892_gpio->regs[i][j]; - - if (new == old) - continue; - - tc35892_gpio->oldregs[i][j] = new; - tc35892_reg_write(tc35892, regmap[i] + j * 8, new); - } - } - - mutex_unlock(&tc35892_gpio->irq_lock); -} - -static void tc35892_gpio_irq_mask(unsigned int irq) -{ - struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq); - int offset = irq - tc35892_gpio->irq_base; - int regoffset = offset / 8; - int mask = 1 << (offset % 8); - - tc35892_gpio->regs[REG_IE][regoffset] &= ~mask; -} - -static void tc35892_gpio_irq_unmask(unsigned int irq) -{ - struct tc35892_gpio *tc35892_gpio = get_irq_chip_data(irq); - int offset = irq - tc35892_gpio->irq_base; - int regoffset = offset / 8; - int mask = 1 << (offset % 8); - - tc35892_gpio->regs[REG_IE][regoffset] |= mask; -} - -static struct irq_chip tc35892_gpio_irq_chip = { - .name = "tc35892-gpio", - .bus_lock = tc35892_gpio_irq_lock, - .bus_sync_unlock = tc35892_gpio_irq_sync_unlock, - .mask = tc35892_gpio_irq_mask, - .unmask = tc35892_gpio_irq_unmask, - .set_type = tc35892_gpio_irq_set_type, -}; - -static irqreturn_t tc35892_gpio_irq(int irq, void *dev) -{ - struct tc35892_gpio *tc35892_gpio = dev; - struct tc35892 *tc35892 = tc35892_gpio->tc35892; - u8 status[CACHE_NR_BANKS]; - int ret; - int i; - - ret = tc35892_block_read(tc35892, TC35892_GPIOMIS0, - ARRAY_SIZE(status), status); - if (ret < 0) - return IRQ_NONE; - - for (i = 0; i < ARRAY_SIZE(status); i++) { - unsigned int stat = status[i]; - if (!stat) - continue; - - while (stat) { - int bit = __ffs(stat); - int line = i * 8 + bit; - - handle_nested_irq(tc35892_gpio->irq_base + line); - stat &= ~(1 << bit); - } - - tc35892_reg_write(tc35892, TC35892_GPIOIC0 + i, status[i]); - } - - return IRQ_HANDLED; -} - -static int tc35892_gpio_irq_init(struct tc35892_gpio *tc35892_gpio) -{ - int base = tc35892_gpio->irq_base; - int irq; - - for (irq = base; irq < base + tc35892_gpio->chip.ngpio; irq++) { - set_irq_chip_data(irq, tc35892_gpio); - set_irq_chip_and_handler(irq, &tc35892_gpio_irq_chip, - handle_simple_irq); - set_irq_nested_thread(irq, 1); -#ifdef CONFIG_ARM - set_irq_flags(irq, IRQF_VALID); -#else - set_irq_noprobe(irq); -#endif - } - - return 0; -} - -static void tc35892_gpio_irq_remove(struct tc35892_gpio *tc35892_gpio) -{ - int base = tc35892_gpio->irq_base; - int irq; - - for (irq = base; irq < base + tc35892_gpio->chip.ngpio; irq++) { -#ifdef CONFIG_ARM - set_irq_flags(irq, 0); -#endif - set_irq_chip_and_handler(irq, NULL, NULL); - set_irq_chip_data(irq, NULL); - } -} - -static int __devinit tc35892_gpio_probe(struct platform_device *pdev) -{ - struct tc35892 *tc35892 = dev_get_drvdata(pdev->dev.parent); - struct tc35892_gpio_platform_data *pdata; - struct tc35892_gpio *tc35892_gpio; - int ret; - int irq; - - pdata = tc35892->pdata->gpio; - if (!pdata) - return -ENODEV; - - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - - tc35892_gpio = kzalloc(sizeof(struct tc35892_gpio), GFP_KERNEL); - if (!tc35892_gpio) - return -ENOMEM; - - mutex_init(&tc35892_gpio->irq_lock); - - tc35892_gpio->dev = &pdev->dev; - tc35892_gpio->tc35892 = tc35892; - - tc35892_gpio->chip = template_chip; - tc35892_gpio->chip.ngpio = tc35892->num_gpio; - tc35892_gpio->chip.dev = &pdev->dev; - tc35892_gpio->chip.base = pdata->gpio_base; - - tc35892_gpio->irq_base = tc35892->irq_base + TC35892_INT_GPIO(0); - - /* Bring the GPIO module out of reset */ - ret = tc35892_set_bits(tc35892, TC35892_RSTCTRL, - TC35892_RSTCTRL_GPIRST, 0); - if (ret < 0) - goto out_free; - - ret = tc35892_gpio_irq_init(tc35892_gpio); - if (ret) - goto out_free; - - ret = request_threaded_irq(irq, NULL, tc35892_gpio_irq, IRQF_ONESHOT, - "tc35892-gpio", tc35892_gpio); - if (ret) { - dev_err(&pdev->dev, "unable to get irq: %d\n", ret); - goto out_removeirq; - } - - ret = gpiochip_add(&tc35892_gpio->chip); - if (ret) { - dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); - goto out_freeirq; - } - - if (pdata->setup) - pdata->setup(tc35892, tc35892_gpio->chip.base); - - platform_set_drvdata(pdev, tc35892_gpio); - - return 0; - -out_freeirq: - free_irq(irq, tc35892_gpio); -out_removeirq: - tc35892_gpio_irq_remove(tc35892_gpio); -out_free: - kfree(tc35892_gpio); - return ret; -} - -static int __devexit tc35892_gpio_remove(struct platform_device *pdev) -{ - struct tc35892_gpio *tc35892_gpio = platform_get_drvdata(pdev); - struct tc35892 *tc35892 = tc35892_gpio->tc35892; - struct tc35892_gpio_platform_data *pdata = tc35892->pdata->gpio; - int irq = platform_get_irq(pdev, 0); - int ret; - - if (pdata->remove) - pdata->remove(tc35892, tc35892_gpio->chip.base); - - ret = gpiochip_remove(&tc35892_gpio->chip); - if (ret < 0) { - dev_err(tc35892_gpio->dev, - "unable to remove gpiochip: %d\n", ret); - return ret; - } - - free_irq(irq, tc35892_gpio); - tc35892_gpio_irq_remove(tc35892_gpio); - - platform_set_drvdata(pdev, NULL); - kfree(tc35892_gpio); - - return 0; -} - -static struct platform_driver tc35892_gpio_driver = { - .driver.name = "tc35892-gpio", - .driver.owner = THIS_MODULE, - .probe = tc35892_gpio_probe, - .remove = __devexit_p(tc35892_gpio_remove), -}; - -static int __init tc35892_gpio_init(void) -{ - return platform_driver_register(&tc35892_gpio_driver); -} -subsys_initcall(tc35892_gpio_init); - -static void __exit tc35892_gpio_exit(void) -{ - platform_driver_unregister(&tc35892_gpio_driver); -} -module_exit(tc35892_gpio_exit); - -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("TC35892 GPIO driver"); -MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent"); diff --git a/drivers/gpio/tc3589x-gpio.c b/drivers/gpio/tc3589x-gpio.c new file mode 100644 index 0000000..180d584 --- /dev/null +++ b/drivers/gpio/tc3589x-gpio.c @@ -0,0 +1,389 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License, version 2 + * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/gpio.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/mfd/tc3589x.h> + +/* + * These registers are modified under the irq bus lock and cached to avoid + * unnecessary writes in bus_sync_unlock. + */ +enum { REG_IBE, REG_IEV, REG_IS, REG_IE }; + +#define CACHE_NR_REGS 4 +#define CACHE_NR_BANKS 3 + +struct tc3589x_gpio { + struct gpio_chip chip; + struct tc3589x *tc3589x; + struct device *dev; + struct mutex irq_lock; + + int irq_base; + + /* Caches of interrupt control registers for bus_lock */ + u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; + u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; +}; + +static inline struct tc3589x_gpio *to_tc3589x_gpio(struct gpio_chip *chip) +{ + return container_of(chip, struct tc3589x_gpio, chip); +} + +static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip); + struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; + u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2; + u8 mask = 1 << (offset % 8); + int ret; + + ret = tc3589x_reg_read(tc3589x, reg); + if (ret < 0) + return ret; + + return ret & mask; +} + +static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val) +{ + struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip); + struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; + u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2; + unsigned pos = offset % 8; + u8 data[] = {!!val << pos, 1 << pos}; + + tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data); +} + +static int tc3589x_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int val) +{ + struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip); + struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; + u8 reg = TC3589x_GPIODIR0 + offset / 8; + unsigned pos = offset % 8; + + tc3589x_gpio_set(chip, offset, val); + + return tc3589x_set_bits(tc3589x, reg, 1 << pos, 1 << pos); +} + +static int tc3589x_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip); + struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; + u8 reg = TC3589x_GPIODIR0 + offset / 8; + unsigned pos = offset % 8; + + return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0); +} + +static int tc3589x_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip); + + return tc3589x_gpio->irq_base + offset; +} + +static struct gpio_chip template_chip = { + .label = "tc3589x", + .owner = THIS_MODULE, + .direction_input = tc3589x_gpio_direction_input, + .get = tc3589x_gpio_get, + .direction_output = tc3589x_gpio_direction_output, + .set = tc3589x_gpio_set, + .to_irq = tc3589x_gpio_to_irq, + .can_sleep = 1, +}; + +static int tc3589x_gpio_irq_set_type(unsigned int irq, unsigned int type) +{ + struct tc3589x_gpio *tc3589x_gpio = get_irq_chip_data(irq); + int offset = irq - tc3589x_gpio->irq_base; + int regoffset = offset / 8; + int mask = 1 << (offset % 8); + + if (type == IRQ_TYPE_EDGE_BOTH) { + tc3589x_gpio->regs[REG_IBE][regoffset] |= mask; + return 0; + } + + tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask; + + if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) + tc3589x_gpio->regs[REG_IS][regoffset] |= mask; + else + tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask; + + if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) + tc3589x_gpio->regs[REG_IEV][regoffset] |= mask; + else + tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask; + + return 0; +} + +static void tc3589x_gpio_irq_lock(unsigned int irq) +{ + struct tc3589x_gpio *tc3589x_gpio = get_irq_chip_data(irq); + + mutex_lock(&tc3589x_gpio->irq_lock); +} + +static void tc3589x_gpio_irq_sync_unlock(unsigned int irq) +{ + struct tc3589x_gpio *tc3589x_gpio = get_irq_chip_data(irq); + struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; + static const u8 regmap[] = { + [REG_IBE] = TC3589x_GPIOIBE0, + [REG_IEV] = TC3589x_GPIOIEV0, + [REG_IS] = TC3589x_GPIOIS0, + [REG_IE] = TC3589x_GPIOIE0, + }; + int i, j; + + for (i = 0; i < CACHE_NR_REGS; i++) { + for (j = 0; j < CACHE_NR_BANKS; j++) { + u8 old = tc3589x_gpio->oldregs[i][j]; + u8 new = tc3589x_gpio->regs[i][j]; + + if (new == old) + continue; + + tc3589x_gpio->oldregs[i][j] = new; + tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new); + } + } + + mutex_unlock(&tc3589x_gpio->irq_lock); +} + +static void tc3589x_gpio_irq_mask(unsigned int irq) +{ + struct tc3589x_gpio *tc3589x_gpio = get_irq_chip_data(irq); + int offset = irq - tc3589x_gpio->irq_base; + int regoffset = offset / 8; + int mask = 1 << (offset % 8); + + tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask; +} + +static void tc3589x_gpio_irq_unmask(unsigned int irq) +{ + struct tc3589x_gpio *tc3589x_gpio = get_irq_chip_data(irq); + int offset = irq - tc3589x_gpio->irq_base; + int regoffset = offset / 8; + int mask = 1 << (offset % 8); + + tc3589x_gpio->regs[REG_IE][regoffset] |= mask; +} + +static struct irq_chip tc3589x_gpio_irq_chip = { + .name = "tc3589x-gpio", + .bus_lock = tc3589x_gpio_irq_lock, + .bus_sync_unlock = tc3589x_gpio_irq_sync_unlock, + .mask = tc3589x_gpio_irq_mask, + .unmask = tc3589x_gpio_irq_unmask, + .set_type = tc3589x_gpio_irq_set_type, +}; + +static irqreturn_t tc3589x_gpio_irq(int irq, void *dev) +{ + struct tc3589x_gpio *tc3589x_gpio = dev; + struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; + u8 status[CACHE_NR_BANKS]; + int ret; + int i; + + ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0, + ARRAY_SIZE(status), status); + if (ret < 0) + return IRQ_NONE; + + for (i = 0; i < ARRAY_SIZE(status); i++) { + unsigned int stat = status[i]; + if (!stat) + continue; + + while (stat) { + int bit = __ffs(stat); + int line = i * 8 + bit; + + handle_nested_irq(tc3589x_gpio->irq_base + line); + stat &= ~(1 << bit); + } + + tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]); + } + + return IRQ_HANDLED; +} + +static int tc3589x_gpio_irq_init(struct tc3589x_gpio *tc3589x_gpio) +{ + int base = tc3589x_gpio->irq_base; + int irq; + + for (irq = base; irq < base + tc3589x_gpio->chip.ngpio; irq++) { + set_irq_chip_data(irq, tc3589x_gpio); + set_irq_chip_and_handler(irq, &tc3589x_gpio_irq_chip, + handle_simple_irq); + set_irq_nested_thread(irq, 1); +#ifdef CONFIG_ARM + set_irq_flags(irq, IRQF_VALID); +#else + set_irq_noprobe(irq); +#endif + } + + return 0; +} + +static void tc3589x_gpio_irq_remove(struct tc3589x_gpio *tc3589x_gpio) +{ + int base = tc3589x_gpio->irq_base; + int irq; + + for (irq = base; irq < base + tc3589x_gpio->chip.ngpio; irq++) { +#ifdef CONFIG_ARM + set_irq_flags(irq, 0); +#endif + set_irq_chip_and_handler(irq, NULL, NULL); + set_irq_chip_data(irq, NULL); + } +} + +static int __devinit tc3589x_gpio_probe(struct platform_device *pdev) +{ + struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent); + struct tc3589x_gpio_platform_data *pdata; + struct tc3589x_gpio *tc3589x_gpio; + int ret; + int irq; + + pdata = tc3589x->pdata->gpio; + if (!pdata) + return -ENODEV; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + tc3589x_gpio = kzalloc(sizeof(struct tc3589x_gpio), GFP_KERNEL); + if (!tc3589x_gpio) + return -ENOMEM; + + mutex_init(&tc3589x_gpio->irq_lock); + + tc3589x_gpio->dev = &pdev->dev; + tc3589x_gpio->tc3589x = tc3589x; + + tc3589x_gpio->chip = template_chip; + tc3589x_gpio->chip.ngpio = tc3589x->num_gpio; + tc3589x_gpio->chip.dev = &pdev->dev; + tc3589x_gpio->chip.base = pdata->gpio_base; + + tc3589x_gpio->irq_base = tc3589x->irq_base + TC3589x_INT_GPIO(0); + + /* Bring the GPIO module out of reset */ + ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL, + TC3589x_RSTCTRL_GPIRST, 0); + if (ret < 0) + goto out_free; + + ret = tc3589x_gpio_irq_init(tc3589x_gpio); + if (ret) + goto out_free; + + ret = request_threaded_irq(irq, NULL, tc3589x_gpio_irq, IRQF_ONESHOT, + "tc3589x-gpio", tc3589x_gpio); + if (ret) { + dev_err(&pdev->dev, "unable to get irq: %d\n", ret); + goto out_removeirq; + } + + ret = gpiochip_add(&tc3589x_gpio->chip); + if (ret) { + dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); + goto out_freeirq; + } + + if (pdata->setup) + pdata->setup(tc3589x, tc3589x_gpio->chip.base); + + platform_set_drvdata(pdev, tc3589x_gpio); + + return 0; + +out_freeirq: + free_irq(irq, tc3589x_gpio); +out_removeirq: + tc3589x_gpio_irq_remove(tc3589x_gpio); +out_free: + kfree(tc3589x_gpio); + return ret; +} + +static int __devexit tc3589x_gpio_remove(struct platform_device *pdev) +{ + struct tc3589x_gpio *tc3589x_gpio = platform_get_drvdata(pdev); + struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; + struct tc3589x_gpio_platform_data *pdata = tc3589x->pdata->gpio; + int irq = platform_get_irq(pdev, 0); + int ret; + + if (pdata->remove) + pdata->remove(tc3589x, tc3589x_gpio->chip.base); + + ret = gpiochip_remove(&tc3589x_gpio->chip); + if (ret < 0) { + dev_err(tc3589x_gpio->dev, + "unable to remove gpiochip: %d\n", ret); + return ret; + } + + free_irq(irq, tc3589x_gpio); + tc3589x_gpio_irq_remove(tc3589x_gpio); + + platform_set_drvdata(pdev, NULL); + kfree(tc3589x_gpio); + + return 0; +} + +static struct platform_driver tc3589x_gpio_driver = { + .driver.name = "tc3589x-gpio", + .driver.owner = THIS_MODULE, + .probe = tc3589x_gpio_probe, + .remove = __devexit_p(tc3589x_gpio_remove), +}; + +static int __init tc3589x_gpio_init(void) +{ + return platform_driver_register(&tc3589x_gpio_driver); +} +subsys_initcall(tc3589x_gpio_init); + +static void __exit tc3589x_gpio_exit(void) +{ + platform_driver_unregister(&tc3589x_gpio_driver); +} +module_exit(tc3589x_gpio_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("TC3589x GPIO driver"); +MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent"); diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig index 3a87f3ba..c76bd31 100644 --- a/drivers/input/keyboard/Kconfig +++ b/drivers/input/keyboard/Kconfig @@ -459,6 +459,16 @@ config KEYBOARD_OMAP4 To compile this driver as a module, choose M here: the module will be called omap4-keypad. +config KEYBOARD_TC3589X + tristate "TC3589X Keypad support" + depends on MFD_TC3589X + help + Say Y here if you want to use the keypad controller on + TC35892/3 I/O expander. + + To compile this driver as a module, choose M here: the + module will be called tc3589x-keypad. + config KEYBOARD_TNETV107X tristate "TI TNETV107X keypad support" depends on ARCH_DAVINCI_TNETV107X diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile index 622de73..2aa6ce2 100644 --- a/drivers/input/keyboard/Makefile +++ b/drivers/input/keyboard/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_KEYBOARD_SH_KEYSC) += sh_keysc.o obj-$(CONFIG_KEYBOARD_STMPE) += stmpe-keypad.o obj-$(CONFIG_KEYBOARD_STOWAWAY) += stowaway.o obj-$(CONFIG_KEYBOARD_SUNKBD) += sunkbd.o +obj-$(CONFIG_KEYBOARD_TC3589X) += tc3589x-keypad.o obj-$(CONFIG_KEYBOARD_TNETV107X) += tnetv107x-keypad.o obj-$(CONFIG_KEYBOARD_TWL4030) += twl4030_keypad.o obj-$(CONFIG_KEYBOARD_XTKBD) += xtkbd.o diff --git a/drivers/input/keyboard/tc3589x-keypad.c b/drivers/input/keyboard/tc3589x-keypad.c new file mode 100644 index 0000000..69dc0cb --- /dev/null +++ b/drivers/input/keyboard/tc3589x-keypad.c @@ -0,0 +1,472 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Jayeeta Banerjee <jayeeta.banerjee@stericsson.com> + * Author: Sundar Iyer <sundar.iyer@stericsson.com> + * + * License Terms: GNU General Public License, version 2 + * + * TC35893 MFD Keypad Controller driver + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/input.h> +#include <linux/platform_device.h> +#include <linux/input/matrix_keypad.h> +#include <linux/i2c.h> +#include <linux/slab.h> +#include <linux/mfd/tc3589x.h> + +/* Maximum supported keypad matrix row/columns size */ +#define TC3589x_MAX_KPROW 8 +#define TC3589x_MAX_KPCOL 12 + +/* keypad related Constants */ +#define TC3589x_MAX_DEBOUNCE_SETTLE 0xFF +#define DEDICATED_KEY_VAL 0xFF + +/* Pull up/down masks */ +#define TC3589x_NO_PULL_MASK 0x0 +#define TC3589x_PULL_DOWN_MASK 0x1 +#define TC3589x_PULL_UP_MASK 0x2 +#define TC3589x_PULLUP_ALL_MASK 0xAA +#define TC3589x_IO_PULL_VAL(index, mask) ((mask)<<((index)%4)*2)) + +/* Bit masks for IOCFG register */ +#define IOCFG_BALLCFG 0x01 +#define IOCFG_IG 0x08 + +#define KP_EVCODE_COL_MASK 0x0F +#define KP_EVCODE_ROW_MASK 0x70 +#define KP_RELEASE_EVT_MASK 0x80 + +#define KP_ROW_SHIFT 4 + +#define KP_NO_VALID_KEY_MASK 0x7F + +/* bit masks for RESTCTRL register */ +#define TC3589x_KBDRST 0x2 +#define TC3589x_IRQRST 0x10 +#define TC3589x_RESET_ALL 0x1B + +/* KBDMFS register bit mask */ +#define TC3589x_KBDMFS_EN 0x1 + +/* CLKEN register bitmask */ +#define KPD_CLK_EN 0x1 + +/* RSTINTCLR register bit mask */ +#define IRQ_CLEAR 0x1 + +/* bit masks for keyboard interrupts*/ +#define TC3589x_EVT_LOSS_INT 0x8 +#define TC3589x_EVT_INT 0x4 +#define TC3589x_KBD_LOSS_INT 0x2 +#define TC3589x_KBD_INT 0x1 + +/* bit masks for keyboard interrupt clear*/ +#define TC3589x_EVT_INT_CLR 0x2 +#define TC3589x_KBD_INT_CLR 0x1 + +#define TC3589x_KBD_KEYMAP_SIZE 64 + +/** + * struct tc_keypad - data structure used by keypad driver + * @input: pointer to input device object + * @board: keypad platform device + * @krow: number of rows + * @kcol: number of coloumns + * @keymap: matrix scan code table for keycodes + */ +struct tc_keypad { + struct tc3589x *tc3589x; + struct input_dev *input; + const struct tc3589x_keypad_platform_data *board; + unsigned int krow; + unsigned int kcol; + unsigned short keymap[TC3589x_KBD_KEYMAP_SIZE]; + bool keypad_stopped; +}; + +static int __devinit tc3589x_keypad_init_key_hardware(struct tc_keypad *keypad) +{ + int ret; + struct tc3589x *tc3589x = keypad->tc3589x; + u8 settle_time = keypad->board->settle_time; + u8 dbounce_period = keypad->board->debounce_period; + u8 rows = keypad->board->krow & 0xf; /* mask out the nibble */ + u8 column = keypad->board->kcol & 0xf; /* mask out the nibble */ + + /* validate platform configurations */ + if (keypad->board->kcol > TC3589x_MAX_KPCOL || + keypad->board->krow > TC3589x_MAX_KPROW || + keypad->board->debounce_period > TC3589x_MAX_DEBOUNCE_SETTLE || + keypad->board->settle_time > TC3589x_MAX_DEBOUNCE_SETTLE) + return -EINVAL; + + /* configure KBDSIZE 4 LSbits for cols and 4 MSbits for rows */ + ret = tc3589x_reg_write(tc3589x, TC3589x_KBDSIZE, + (rows << KP_ROW_SHIFT) | column); + if (ret < 0) + return ret; + + /* configure dedicated key config, no dedicated key selected */ + ret = tc3589x_reg_write(tc3589x, TC3589x_KBCFG_LSB, DEDICATED_KEY_VAL); + if (ret < 0) + return ret; + + ret = tc3589x_reg_write(tc3589x, TC3589x_KBCFG_MSB, DEDICATED_KEY_VAL); + if (ret < 0) + return ret; + + /* Configure settle time */ + ret = tc3589x_reg_write(tc3589x, TC3589x_KBDSETTLE_REG, settle_time); + if (ret < 0) + return ret; + + /* Configure debounce time */ + ret = tc3589x_reg_write(tc3589x, TC3589x_KBDBOUNCE, dbounce_period); + if (ret < 0) + return ret; + + /* Start of initialise keypad GPIOs */ + ret = tc3589x_set_bits(tc3589x, TC3589x_IOCFG, 0x0, IOCFG_IG); + if (ret < 0) + return ret; + + /* Configure pull-up resistors for all row GPIOs */ + ret = tc3589x_reg_write(tc3589x, TC3589x_IOPULLCFG0_LSB, + TC3589x_PULLUP_ALL_MASK); + if (ret < 0) + return ret; + + ret = tc3589x_reg_write(tc3589x, TC3589x_IOPULLCFG0_MSB, + TC3589x_PULLUP_ALL_MASK); + if (ret < 0) + return ret; + + /* Configure pull-up resistors for all column GPIOs */ + ret = tc3589x_reg_write(tc3589x, TC3589x_IOPULLCFG1_LSB, + TC3589x_PULLUP_ALL_MASK); + if (ret < 0) + return ret; + + ret = tc3589x_reg_write(tc3589x, TC3589x_IOPULLCFG1_MSB, + TC3589x_PULLUP_ALL_MASK); + if (ret < 0) + return ret; + + ret = tc3589x_reg_write(tc3589x, TC3589x_IOPULLCFG2_LSB, + TC3589x_PULLUP_ALL_MASK); + + return ret; +} + +#define TC35893_DATA_REGS 4 +#define TC35893_KEYCODE_FIFO_EMPTY 0x7f +#define TC35893_KEYCODE_FIFO_CLEAR 0xff +#define TC35893_KEYPAD_ROW_SHIFT 0x3 + +static irqreturn_t tc3589x_keypad_irq(int irq, void *dev) +{ + struct tc_keypad *keypad = dev; + struct tc3589x *tc3589x = keypad->tc3589x; + u8 i, row_index, col_index, kbd_code, up; + u8 code; + + for (i = 0; i < TC35893_DATA_REGS * 2; i++) { + kbd_code = tc3589x_reg_read(tc3589x, TC3589x_EVTCODE_FIFO); + + /* loop till fifo is empty and no more keys are pressed */ + if (kbd_code == TC35893_KEYCODE_FIFO_EMPTY || + kbd_code == TC35893_KEYCODE_FIFO_CLEAR) + continue; + + /* valid key is found */ + col_index = kbd_code & KP_EVCODE_COL_MASK; + row_index = (kbd_code & KP_EVCODE_ROW_MASK) >> KP_ROW_SHIFT; + code = MATRIX_SCAN_CODE(row_index, col_index, + TC35893_KEYPAD_ROW_SHIFT); + up = kbd_code & KP_RELEASE_EVT_MASK; + + input_event(keypad->input, EV_MSC, MSC_SCAN, code); + input_report_key(keypad->input, keypad->keymap[code], !up); + input_sync(keypad->input); + } + + /* clear IRQ */ + tc3589x_set_bits(tc3589x, TC3589x_KBDIC, + 0x0, TC3589x_EVT_INT_CLR | TC3589x_KBD_INT_CLR); + /* enable IRQ */ + tc3589x_set_bits(tc3589x, TC3589x_KBDMSK, + 0x0, TC3589x_EVT_LOSS_INT | TC3589x_EVT_INT); + + return IRQ_HANDLED; +} + +static int tc3589x_keypad_enable(struct tc_keypad *keypad) +{ + struct tc3589x *tc3589x = keypad->tc3589x; + int ret; + + /* pull the keypad module out of reset */ + ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL, TC3589x_KBDRST, 0x0); + if (ret < 0) + return ret; + + /* configure KBDMFS */ + ret = tc3589x_set_bits(tc3589x, TC3589x_KBDMFS, 0x0, TC3589x_KBDMFS_EN); + if (ret < 0) + return ret; + + /* enable the keypad clock */ + ret = tc3589x_set_bits(tc3589x, TC3589x_CLKEN, 0x0, KPD_CLK_EN); + if (ret < 0) + return ret; + + /* clear pending IRQs */ + ret = tc3589x_set_bits(tc3589x, TC3589x_RSTINTCLR, 0x0, 0x1); + if (ret < 0) + return ret; + + /* enable the IRQs */ + ret = tc3589x_set_bits(tc3589x, TC3589x_KBDMSK, 0x0, + TC3589x_EVT_LOSS_INT | TC3589x_EVT_INT); + if (ret < 0) + return ret; + + keypad->keypad_stopped = false; + + return ret; +} + +static int tc3589x_keypad_disable(struct tc_keypad *keypad) +{ + struct tc3589x *tc3589x = keypad->tc3589x; + int ret; + + /* clear IRQ */ + ret = tc3589x_set_bits(tc3589x, TC3589x_KBDIC, + 0x0, TC3589x_EVT_INT_CLR | TC3589x_KBD_INT_CLR); + if (ret < 0) + return ret; + + /* disable all interrupts */ + ret = tc3589x_set_bits(tc3589x, TC3589x_KBDMSK, + ~(TC3589x_EVT_LOSS_INT | TC3589x_EVT_INT), 0x0); + if (ret < 0) + return ret; + + /* disable the keypad module */ + ret = tc3589x_set_bits(tc3589x, TC3589x_CLKEN, 0x1, 0x0); + if (ret < 0) + return ret; + + /* put the keypad module into reset */ + ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL, TC3589x_KBDRST, 0x1); + + keypad->keypad_stopped = true; + + return ret; +} + +static int tc3589x_keypad_open(struct input_dev *input) +{ + int error; + struct tc_keypad *keypad = input_get_drvdata(input); + + /* enable the keypad module */ + error = tc3589x_keypad_enable(keypad); + if (error < 0) { + dev_err(&input->dev, "failed to enable keypad module\n"); + return error; + } + + error = tc3589x_keypad_init_key_hardware(keypad); + if (error < 0) { + dev_err(&input->dev, "failed to configure keypad module\n"); + return error; + } + + return 0; +} + +static void tc3589x_keypad_close(struct input_dev *input) +{ + struct tc_keypad *keypad = input_get_drvdata(input); + + /* disable the keypad module */ + tc3589x_keypad_disable(keypad); +} + +static int __devinit tc3589x_keypad_probe(struct platform_device *pdev) +{ + struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent); + struct tc_keypad *keypad; + struct input_dev *input; + const struct tc3589x_keypad_platform_data *plat; + int error, irq; + + plat = tc3589x->pdata->keypad; + if (!plat) { + dev_err(&pdev->dev, "invalid keypad platform data\n"); + return -EINVAL; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + keypad = kzalloc(sizeof(struct tc_keypad), GFP_KERNEL); + input = input_allocate_device(); + if (!keypad || !input) { + dev_err(&pdev->dev, "failed to allocate keypad memory\n"); + error = -ENOMEM; + goto err_free_mem; + } + + keypad->board = plat; + keypad->input = input; + keypad->tc3589x = tc3589x; + + input->id.bustype = BUS_I2C; + input->name = pdev->name; + input->dev.parent = &pdev->dev; + + input->keycode = keypad->keymap; + input->keycodesize = sizeof(keypad->keymap[0]); + input->keycodemax = ARRAY_SIZE(keypad->keymap); + + input->open = tc3589x_keypad_open; + input->close = tc3589x_keypad_close; + + input_set_drvdata(input, keypad); + + input_set_capability(input, EV_MSC, MSC_SCAN); + + __set_bit(EV_KEY, input->evbit); + if (!plat->no_autorepeat) + __set_bit(EV_REP, input->evbit); + + matrix_keypad_build_keymap(plat->keymap_data, 0x3, + input->keycode, input->keybit); + + error = request_threaded_irq(irq, NULL, + tc3589x_keypad_irq, plat->irqtype, + "tc3589x-keypad", keypad); + if (error < 0) { + dev_err(&pdev->dev, + "Could not allocate irq %d,error %d\n", + irq, error); + goto err_free_mem; + } + + error = input_register_device(input); + if (error) { + dev_err(&pdev->dev, "Could not register input device\n"); + goto err_free_irq; + } + + /* let platform decide if keypad is a wakeup source or not */ + device_init_wakeup(&pdev->dev, plat->enable_wakeup); + device_set_wakeup_capable(&pdev->dev, plat->enable_wakeup); + + platform_set_drvdata(pdev, keypad); + + return 0; + +err_free_irq: + free_irq(irq, keypad); +err_free_mem: + input_free_device(input); + kfree(keypad); + return error; +} + +static int __devexit tc3589x_keypad_remove(struct platform_device *pdev) +{ + struct tc_keypad *keypad = platform_get_drvdata(pdev); + int irq = platform_get_irq(pdev, 0); + + if (!keypad->keypad_stopped) + tc3589x_keypad_disable(keypad); + + free_irq(irq, keypad); + + input_unregister_device(keypad->input); + + kfree(keypad); + + return 0; +} + +#ifdef CONFIG_PM +static int tc3589x_keypad_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct tc_keypad *keypad = platform_get_drvdata(pdev); + int irq = platform_get_irq(pdev, 0); + + /* keypad is already off; we do nothing */ + if (keypad->keypad_stopped) + return 0; + + /* if device is not a wakeup source, disable it for powersave */ + if (!device_may_wakeup(&pdev->dev)) + tc3589x_keypad_disable(keypad); + else + enable_irq_wake(irq); + + return 0; +} + +static int tc3589x_keypad_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct tc_keypad *keypad = platform_get_drvdata(pdev); + int irq = platform_get_irq(pdev, 0); + + if (!keypad->keypad_stopped) + return 0; + + /* enable the device to resume normal operations */ + if (!device_may_wakeup(&pdev->dev)) + tc3589x_keypad_enable(keypad); + else + disable_irq_wake(irq); + + return 0; +} + +static const SIMPLE_DEV_PM_OPS(tc3589x_keypad_dev_pm_ops, + tc3589x_keypad_suspend, tc3589x_keypad_resume); +#endif + +static struct platform_driver tc3589x_keypad_driver = { + .driver.name = "tc3589x-keypad", + .driver.owner = THIS_MODULE, +#ifdef CONFIG_PM + .driver.pm = &tc3589x_keypad_dev_pm_ops, +#endif + .probe = tc3589x_keypad_probe, + .remove = __devexit_p(tc3589x_keypad_remove), +}; + +static int __init tc3589x_keypad_init(void) +{ + return platform_driver_register(&tc3589x_keypad_driver); +} +module_init(tc3589x_keypad_init); + +static void __exit tc3589x_keypad_exit(void) +{ + return platform_driver_unregister(&tc3589x_keypad_driver); +} +module_exit(tc3589x_keypad_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Jayeeta Banerjee/Sundar Iyer"); +MODULE_DESCRIPTION("TC35893 Keypad Driver"); +MODULE_ALIAS("platform:tc3589x-keypad") diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 3a1493b..e8e704f 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -218,12 +218,12 @@ config MFD_STMPE Keypad: stmpe-keypad Touchscreen: stmpe-ts -config MFD_TC35892 - bool "Support Toshiba TC35892" +config MFD_TC3589X + bool "Support Toshiba TC35892 and variants" depends on I2C=y && GENERIC_HARDIRQS select MFD_CORE help - Support for the Toshiba TC35892 I/O Expander. + Support for the Toshiba TC35892 and variants I/O Expander. This driver provides common support for accessing the device, additional drivers must be enabled in order to use the diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index f54b365..e590d1e 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_MFD_DAVINCI_VOICECODEC) += davinci_voicecodec.o obj-$(CONFIG_MFD_DM355EVM_MSP) += dm355evm_msp.o obj-$(CONFIG_MFD_STMPE) += stmpe.o -obj-$(CONFIG_MFD_TC35892) += tc35892.o +obj-$(CONFIG_MFD_TC3589X) += tc3589x.o obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o tmio_core.o obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o tmio_core.o obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o tmio_core.o diff --git a/drivers/mfd/tc35892.c b/drivers/mfd/tc35892.c deleted file mode 100644 index e619e2a..0000000 --- a/drivers/mfd/tc35892.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License Terms: GNU General Public License, version 2 - * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - */ - -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/slab.h> -#include <linux/i2c.h> -#include <linux/mfd/core.h> -#include <linux/mfd/tc35892.h> - -/** - * tc35892_reg_read() - read a single TC35892 register - * @tc35892: Device to read from - * @reg: Register to read - */ -int tc35892_reg_read(struct tc35892 *tc35892, u8 reg) -{ - int ret; - - ret = i2c_smbus_read_byte_data(tc35892->i2c, reg); - if (ret < 0) - dev_err(tc35892->dev, "failed to read reg %#x: %d\n", - reg, ret); - - return ret; -} -EXPORT_SYMBOL_GPL(tc35892_reg_read); - -/** - * tc35892_reg_read() - write a single TC35892 register - * @tc35892: Device to write to - * @reg: Register to read - * @data: Value to write - */ -int tc35892_reg_write(struct tc35892 *tc35892, u8 reg, u8 data) -{ - int ret; - - ret = i2c_smbus_write_byte_data(tc35892->i2c, reg, data); - if (ret < 0) - dev_err(tc35892->dev, "failed to write reg %#x: %d\n", - reg, ret); - - return ret; -} -EXPORT_SYMBOL_GPL(tc35892_reg_write); - -/** - * tc35892_block_read() - read multiple TC35892 registers - * @tc35892: Device to read from - * @reg: First register - * @length: Number of registers - * @values: Buffer to write to - */ -int tc35892_block_read(struct tc35892 *tc35892, u8 reg, u8 length, u8 *values) -{ - int ret; - - ret = i2c_smbus_read_i2c_block_data(tc35892->i2c, reg, length, values); - if (ret < 0) - dev_err(tc35892->dev, "failed to read regs %#x: %d\n", - reg, ret); - - return ret; -} -EXPORT_SYMBOL_GPL(tc35892_block_read); - -/** - * tc35892_block_write() - write multiple TC35892 registers - * @tc35892: Device to write to - * @reg: First register - * @length: Number of registers - * @values: Values to write - */ -int tc35892_block_write(struct tc35892 *tc35892, u8 reg, u8 length, - const u8 *values) -{ - int ret; - - ret = i2c_smbus_write_i2c_block_data(tc35892->i2c, reg, length, - values); - if (ret < 0) - dev_err(tc35892->dev, "failed to write regs %#x: %d\n", - reg, ret); - - return ret; -} -EXPORT_SYMBOL_GPL(tc35892_block_write); - -/** - * tc35892_set_bits() - set the value of a bitfield in a TC35892 register - * @tc35892: Device to write to - * @reg: Register to write - * @mask: Mask of bits to set - * @values: Value to set - */ -int tc35892_set_bits(struct tc35892 *tc35892, u8 reg, u8 mask, u8 val) -{ - int ret; - - mutex_lock(&tc35892->lock); - - ret = tc35892_reg_read(tc35892, reg); - if (ret < 0) - goto out; - - ret &= ~mask; - ret |= val; - - ret = tc35892_reg_write(tc35892, reg, ret); - -out: - mutex_unlock(&tc35892->lock); - return ret; -} -EXPORT_SYMBOL_GPL(tc35892_set_bits); - -static struct resource gpio_resources[] = { - { - .start = TC35892_INT_GPIIRQ, - .end = TC35892_INT_GPIIRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mfd_cell tc35892_devs[] = { - { - .name = "tc35892-gpio", - .num_resources = ARRAY_SIZE(gpio_resources), - .resources = &gpio_resources[0], - }, -}; - -static irqreturn_t tc35892_irq(int irq, void *data) -{ - struct tc35892 *tc35892 = data; - int status; - - status = tc35892_reg_read(tc35892, TC35892_IRQST); - if (status < 0) - return IRQ_NONE; - - while (status) { - int bit = __ffs(status); - - handle_nested_irq(tc35892->irq_base + bit); - status &= ~(1 << bit); - } - - /* - * A dummy read or write (to any register) appears to be necessary to - * have the last interrupt clear (for example, GPIO IC write) take - * effect. - */ - tc35892_reg_read(tc35892, TC35892_IRQST); - - return IRQ_HANDLED; -} - -static void tc35892_irq_dummy(unsigned int irq) -{ - /* No mask/unmask at this level */ -} - -static struct irq_chip tc35892_irq_chip = { - .name = "tc35892", - .mask = tc35892_irq_dummy, - .unmask = tc35892_irq_dummy, -}; - -static int tc35892_irq_init(struct tc35892 *tc35892) -{ - int base = tc35892->irq_base; - int irq; - - for (irq = base; irq < base + TC35892_NR_INTERNAL_IRQS; irq++) { - set_irq_chip_data(irq, tc35892); - set_irq_chip_and_handler(irq, &tc35892_irq_chip, - handle_edge_irq); - set_irq_nested_thread(irq, 1); -#ifdef CONFIG_ARM - set_irq_flags(irq, IRQF_VALID); -#else - set_irq_noprobe(irq); -#endif - } - - return 0; -} - -static void tc35892_irq_remove(struct tc35892 *tc35892) -{ - int base = tc35892->irq_base; - int irq; - - for (irq = base; irq < base + TC35892_NR_INTERNAL_IRQS; irq++) { -#ifdef CONFIG_ARM - set_irq_flags(irq, 0); -#endif - set_irq_chip_and_handler(irq, NULL, NULL); - set_irq_chip_data(irq, NULL); - } -} - -static int tc35892_chip_init(struct tc35892 *tc35892) -{ - int manf, ver, ret; - - manf = tc35892_reg_read(tc35892, TC35892_MANFCODE); - if (manf < 0) - return manf; - - ver = tc35892_reg_read(tc35892, TC35892_VERSION); - if (ver < 0) - return ver; - - if (manf != TC35892_MANFCODE_MAGIC) { - dev_err(tc35892->dev, "unknown manufacturer: %#x\n", manf); - return -EINVAL; - } - - dev_info(tc35892->dev, "manufacturer: %#x, version: %#x\n", manf, ver); - - /* Put everything except the IRQ module into reset */ - ret = tc35892_reg_write(tc35892, TC35892_RSTCTRL, - TC35892_RSTCTRL_TIMRST - | TC35892_RSTCTRL_ROTRST - | TC35892_RSTCTRL_KBDRST - | TC35892_RSTCTRL_GPIRST); - if (ret < 0) - return ret; - - /* Clear the reset interrupt. */ - return tc35892_reg_write(tc35892, TC35892_RSTINTCLR, 0x1); -} - -static int __devinit tc35892_probe(struct i2c_client *i2c, - const struct i2c_device_id *id) -{ - struct tc35892_platform_data *pdata = i2c->dev.platform_data; - struct tc35892 *tc35892; - int ret; - - if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_BYTE_DATA - | I2C_FUNC_SMBUS_I2C_BLOCK)) - return -EIO; - - tc35892 = kzalloc(sizeof(struct tc35892), GFP_KERNEL); - if (!tc35892) - return -ENOMEM; - - mutex_init(&tc35892->lock); - - tc35892->dev = &i2c->dev; - tc35892->i2c = i2c; - tc35892->pdata = pdata; - tc35892->irq_base = pdata->irq_base; - tc35892->num_gpio = id->driver_data; - - i2c_set_clientdata(i2c, tc35892); - - ret = tc35892_chip_init(tc35892); - if (ret) - goto out_free; - - ret = tc35892_irq_init(tc35892); - if (ret) - goto out_free; - - ret = request_threaded_irq(tc35892->i2c->irq, NULL, tc35892_irq, - IRQF_TRIGGER_FALLING | IRQF_ONESHOT, - "tc35892", tc35892); - if (ret) { - dev_err(tc35892->dev, "failed to request IRQ: %d\n", ret); - goto out_removeirq; - } - - ret = mfd_add_devices(tc35892->dev, -1, tc35892_devs, - ARRAY_SIZE(tc35892_devs), NULL, - tc35892->irq_base); - if (ret) { - dev_err(tc35892->dev, "failed to add children\n"); - goto out_freeirq; - } - - return 0; - -out_freeirq: - free_irq(tc35892->i2c->irq, tc35892); -out_removeirq: - tc35892_irq_remove(tc35892); -out_free: - kfree(tc35892); - return ret; -} - -static int __devexit tc35892_remove(struct i2c_client *client) -{ - struct tc35892 *tc35892 = i2c_get_clientdata(client); - - mfd_remove_devices(tc35892->dev); - - free_irq(tc35892->i2c->irq, tc35892); - tc35892_irq_remove(tc35892); - - kfree(tc35892); - - return 0; -} - -static const struct i2c_device_id tc35892_id[] = { - { "tc35892", 24 }, - { } -}; -MODULE_DEVICE_TABLE(i2c, tc35892_id); - -static struct i2c_driver tc35892_driver = { - .driver.name = "tc35892", - .driver.owner = THIS_MODULE, - .probe = tc35892_probe, - .remove = __devexit_p(tc35892_remove), - .id_table = tc35892_id, -}; - -static int __init tc35892_init(void) -{ - return i2c_add_driver(&tc35892_driver); -} -subsys_initcall(tc35892_init); - -static void __exit tc35892_exit(void) -{ - i2c_del_driver(&tc35892_driver); -} -module_exit(tc35892_exit); - -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("TC35892 MFD core driver"); -MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent"); diff --git a/drivers/mfd/tc3589x.c b/drivers/mfd/tc3589x.c new file mode 100644 index 0000000..729dbee --- /dev/null +++ b/drivers/mfd/tc3589x.c @@ -0,0 +1,422 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License, version 2 + * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + */ + +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/slab.h> +#include <linux/i2c.h> +#include <linux/mfd/core.h> +#include <linux/mfd/tc3589x.h> + +#define TC3589x_CLKMODE_MODCTL_SLEEP 0x0 +#define TC3589x_CLKMODE_MODCTL_OPERATION (1 << 0) + +/** + * tc3589x_reg_read() - read a single TC3589x register + * @tc3589x: Device to read from + * @reg: Register to read + */ +int tc3589x_reg_read(struct tc3589x *tc3589x, u8 reg) +{ + int ret; + + ret = i2c_smbus_read_byte_data(tc3589x->i2c, reg); + if (ret < 0) + dev_err(tc3589x->dev, "failed to read reg %#x: %d\n", + reg, ret); + + return ret; +} +EXPORT_SYMBOL_GPL(tc3589x_reg_read); + +/** + * tc3589x_reg_read() - write a single TC3589x register + * @tc3589x: Device to write to + * @reg: Register to read + * @data: Value to write + */ +int tc3589x_reg_write(struct tc3589x *tc3589x, u8 reg, u8 data) +{ + int ret; + + ret = i2c_smbus_write_byte_data(tc3589x->i2c, reg, data); + if (ret < 0) + dev_err(tc3589x->dev, "failed to write reg %#x: %d\n", + reg, ret); + + return ret; +} +EXPORT_SYMBOL_GPL(tc3589x_reg_write); + +/** + * tc3589x_block_read() - read multiple TC3589x registers + * @tc3589x: Device to read from + * @reg: First register + * @length: Number of registers + * @values: Buffer to write to + */ +int tc3589x_block_read(struct tc3589x *tc3589x, u8 reg, u8 length, u8 *values) +{ + int ret; + + ret = i2c_smbus_read_i2c_block_data(tc3589x->i2c, reg, length, values); + if (ret < 0) + dev_err(tc3589x->dev, "failed to read regs %#x: %d\n", + reg, ret); + + return ret; +} +EXPORT_SYMBOL_GPL(tc3589x_block_read); + +/** + * tc3589x_block_write() - write multiple TC3589x registers + * @tc3589x: Device to write to + * @reg: First register + * @length: Number of registers + * @values: Values to write + */ +int tc3589x_block_write(struct tc3589x *tc3589x, u8 reg, u8 length, + const u8 *values) +{ + int ret; + + ret = i2c_smbus_write_i2c_block_data(tc3589x->i2c, reg, length, + values); + if (ret < 0) + dev_err(tc3589x->dev, "failed to write regs %#x: %d\n", + reg, ret); + + return ret; +} +EXPORT_SYMBOL_GPL(tc3589x_block_write); + +/** + * tc3589x_set_bits() - set the value of a bitfield in a TC3589x register + * @tc3589x: Device to write to + * @reg: Register to write + * @mask: Mask of bits to set + * @values: Value to set + */ +int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val) +{ + int ret; + + mutex_lock(&tc3589x->lock); + + ret = tc3589x_reg_read(tc3589x, reg); + if (ret < 0) + goto out; + + ret &= ~mask; + ret |= val; + + ret = tc3589x_reg_write(tc3589x, reg, ret); + +out: + mutex_unlock(&tc3589x->lock); + return ret; +} +EXPORT_SYMBOL_GPL(tc3589x_set_bits); + +static struct resource gpio_resources[] = { + { + .start = TC3589x_INT_GPIIRQ, + .end = TC3589x_INT_GPIIRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource keypad_resources[] = { + { + .start = TC3589x_INT_KBDIRQ, + .end = TC3589x_INT_KBDIRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mfd_cell tc3589x_dev_gpio[] = { + { + .name = "tc3589x-gpio", + .num_resources = ARRAY_SIZE(gpio_resources), + .resources = &gpio_resources[0], + }, +}; + +static struct mfd_cell tc3589x_dev_keypad[] = { + { + .name = "tc3589x-keypad", + .num_resources = ARRAY_SIZE(keypad_resources), + .resources = &keypad_resources[0], + }, +}; + +static irqreturn_t tc3589x_irq(int irq, void *data) +{ + struct tc3589x *tc3589x = data; + int status; + +again: + status = tc3589x_reg_read(tc3589x, TC3589x_IRQST); + if (status < 0) + return IRQ_NONE; + + while (status) { + int bit = __ffs(status); + + handle_nested_irq(tc3589x->irq_base + bit); + status &= ~(1 << bit); + } + + /* + * A dummy read or write (to any register) appears to be necessary to + * have the last interrupt clear (for example, GPIO IC write) take + * effect. In such a case, recheck for any interrupt which is still + * pending. + */ + status = tc3589x_reg_read(tc3589x, TC3589x_IRQST); + if (status) + goto again; + + return IRQ_HANDLED; +} + +static int tc3589x_irq_init(struct tc3589x *tc3589x) +{ + int base = tc3589x->irq_base; + int irq; + + for (irq = base; irq < base + TC3589x_NR_INTERNAL_IRQS; irq++) { + set_irq_chip_data(irq, tc3589x); + set_irq_chip_and_handler(irq, &dummy_irq_chip, + handle_edge_irq); + set_irq_nested_thread(irq, 1); +#ifdef CONFIG_ARM + set_irq_flags(irq, IRQF_VALID); +#else + set_irq_noprobe(irq); +#endif + } + + return 0; +} + +static void tc3589x_irq_remove(struct tc3589x *tc3589x) +{ + int base = tc3589x->irq_base; + int irq; + + for (irq = base; irq < base + TC3589x_NR_INTERNAL_IRQS; irq++) { +#ifdef CONFIG_ARM + set_irq_flags(irq, 0); +#endif + set_irq_chip_and_handler(irq, NULL, NULL); + set_irq_chip_data(irq, NULL); + } +} + +static int tc3589x_chip_init(struct tc3589x *tc3589x) +{ + int manf, ver, ret; + + manf = tc3589x_reg_read(tc3589x, TC3589x_MANFCODE); + if (manf < 0) + return manf; + + ver = tc3589x_reg_read(tc3589x, TC3589x_VERSION); + if (ver < 0) + return ver; + + if (manf != TC3589x_MANFCODE_MAGIC) { + dev_err(tc3589x->dev, "unknown manufacturer: %#x\n", manf); + return -EINVAL; + } + + dev_info(tc3589x->dev, "manufacturer: %#x, version: %#x\n", manf, ver); + + /* + * Put everything except the IRQ module into reset; + * also spare the GPIO module for any pin initialization + * done during pre-kernel boot + */ + ret = tc3589x_reg_write(tc3589x, TC3589x_RSTCTRL, + TC3589x_RSTCTRL_TIMRST + | TC3589x_RSTCTRL_ROTRST + | TC3589x_RSTCTRL_KBDRST); + if (ret < 0) + return ret; + + /* Clear the reset interrupt. */ + return tc3589x_reg_write(tc3589x, TC3589x_RSTINTCLR, 0x1); +} + +static int __devinit tc3589x_device_init(struct tc3589x *tc3589x) +{ + int ret = 0; + unsigned int blocks = tc3589x->pdata->block; + + if (blocks & TC3589x_BLOCK_GPIO) { + ret = mfd_add_devices(tc3589x->dev, -1, tc3589x_dev_gpio, + ARRAY_SIZE(tc3589x_dev_gpio), NULL, + tc3589x->irq_base); + if (ret) { + dev_err(tc3589x->dev, "failed to add gpio child\n"); + return ret; + } + dev_info(tc3589x->dev, "added gpio block\n"); + } + + if (blocks & TC3589x_BLOCK_KEYPAD) { + ret = mfd_add_devices(tc3589x->dev, -1, tc3589x_dev_keypad, + ARRAY_SIZE(tc3589x_dev_keypad), NULL, + tc3589x->irq_base); + if (ret) { + dev_err(tc3589x->dev, "failed to keypad child\n"); + return ret; + } + dev_info(tc3589x->dev, "added keypad block\n"); + } + + return ret; +} + +static int __devinit tc3589x_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct tc3589x_platform_data *pdata = i2c->dev.platform_data; + struct tc3589x *tc3589x; + int ret; + + if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_BYTE_DATA + | I2C_FUNC_SMBUS_I2C_BLOCK)) + return -EIO; + + tc3589x = kzalloc(sizeof(struct tc3589x), GFP_KERNEL); + if (!tc3589x) + return -ENOMEM; + + mutex_init(&tc3589x->lock); + + tc3589x->dev = &i2c->dev; + tc3589x->i2c = i2c; + tc3589x->pdata = pdata; + tc3589x->irq_base = pdata->irq_base; + tc3589x->num_gpio = id->driver_data; + + i2c_set_clientdata(i2c, tc3589x); + + ret = tc3589x_chip_init(tc3589x); + if (ret) + goto out_free; + + ret = tc3589x_irq_init(tc3589x); + if (ret) + goto out_free; + + ret = request_threaded_irq(tc3589x->i2c->irq, NULL, tc3589x_irq, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + "tc3589x", tc3589x); + if (ret) { + dev_err(tc3589x->dev, "failed to request IRQ: %d\n", ret); + goto out_removeirq; + } + + ret = tc3589x_device_init(tc3589x); + if (ret) { + dev_err(tc3589x->dev, "failed to add child devices\n"); + goto out_freeirq; + } + + return 0; + +out_freeirq: + free_irq(tc3589x->i2c->irq, tc3589x); +out_removeirq: + tc3589x_irq_remove(tc3589x); +out_free: + kfree(tc3589x); + return ret; +} + +static int __devexit tc3589x_remove(struct i2c_client *client) +{ + struct tc3589x *tc3589x = i2c_get_clientdata(client); + + mfd_remove_devices(tc3589x->dev); + + free_irq(tc3589x->i2c->irq, tc3589x); + tc3589x_irq_remove(tc3589x); + + kfree(tc3589x); + + return 0; +} + +static int tc3589x_suspend(struct device *dev) +{ + struct tc3589x *tc3589x = dev_get_drvdata(dev); + struct i2c_client *client = tc3589x->i2c; + int ret = 0; + + /* put the system to sleep mode */ + if (!device_may_wakeup(&client->dev)) + ret = tc3589x_reg_write(tc3589x, TC3589x_CLKMODE, + TC3589x_CLKMODE_MODCTL_SLEEP); + + return ret; +} + +static int tc3589x_resume(struct device *dev) +{ + struct tc3589x *tc3589x = dev_get_drvdata(dev); + struct i2c_client *client = tc3589x->i2c; + int ret = 0; + + /* enable the system into operation */ + if (!device_may_wakeup(&client->dev)) + ret = tc3589x_reg_write(tc3589x, TC3589x_CLKMODE, + TC3589x_CLKMODE_MODCTL_OPERATION); + + return ret; +} + +static const SIMPLE_DEV_PM_OPS(tc3589x_dev_pm_ops, tc3589x_suspend, + tc3589x_resume); + +static const struct i2c_device_id tc3589x_id[] = { + { "tc3589x", 24 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, tc3589x_id); + +static struct i2c_driver tc3589x_driver = { + .driver.name = "tc3589x", + .driver.owner = THIS_MODULE, +#ifdef CONFIG_PM + .driver.pm = &tc3589x_dev_pm_ops, +#endif + .probe = tc3589x_probe, + .remove = __devexit_p(tc3589x_remove), + .id_table = tc3589x_id, +}; + +static int __init tc3589x_init(void) +{ + return i2c_add_driver(&tc3589x_driver); +} +subsys_initcall(tc3589x_init); + +static void __exit tc3589x_exit(void) +{ + i2c_del_driver(&tc3589x_driver); +} +module_exit(tc3589x_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("TC3589x MFD core driver"); +MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent"); diff --git a/drivers/net/caif/caif_shm_u5500.c b/drivers/net/caif/caif_shm_u5500.c index 32b1c6f..5f771ab 100644 --- a/drivers/net/caif/caif_shm_u5500.c +++ b/drivers/net/caif/caif_shm_u5500.c @@ -11,7 +11,7 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/netdevice.h> -#include <mach/mbox.h> +#include <mach/mbox-db5500.h> #include <net/caif/caif_shm.h> MODULE_LICENSE("GPL"); diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index c80a7a6..de886f3 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -215,7 +215,8 @@ config PCMCIA_PXA2XX depends on (ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL \ || MACH_ARMCORE || ARCH_PXA_PALM || TRIZEPS_PCMCIA \ || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2 \ - || MACH_VPAC270 || MACH_BALLOON3) + || MACH_VPAC270 || MACH_BALLOON3 || MACH_COLIBRI \ + || MACH_COLIBRI320) select PCMCIA_SOC_COMMON help Say Y here to include support for the PXA2xx PCMCIA controller diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index a565300..29935ea 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -71,6 +71,8 @@ pxa2xx-obj-$(CONFIG_MACH_E740) += pxa2xx_e740.o pxa2xx-obj-$(CONFIG_MACH_STARGATE2) += pxa2xx_stargate2.o pxa2xx-obj-$(CONFIG_MACH_VPAC270) += pxa2xx_vpac270.o pxa2xx-obj-$(CONFIG_MACH_BALLOON3) += pxa2xx_balloon3.o +pxa2xx-obj-$(CONFIG_MACH_COLIBRI) += pxa2xx_colibri.o +pxa2xx-obj-$(CONFIG_MACH_COLIBRI320) += pxa2xx_colibri.o obj-$(CONFIG_PCMCIA_PXA2XX) += pxa2xx_base.o $(pxa2xx-obj-y) diff --git a/drivers/pcmcia/pxa2xx_balloon3.c b/drivers/pcmcia/pxa2xx_balloon3.c index dbbdd00..453c54c 100644 --- a/drivers/pcmcia/pxa2xx_balloon3.c +++ b/drivers/pcmcia/pxa2xx_balloon3.c @@ -39,12 +39,10 @@ static struct pcmcia_irqs irqs[] = { static int balloon3_pcmcia_hw_init(struct soc_pcmcia_socket *skt) { uint16_t ver; - int ret; - static void __iomem *fpga_ver; ver = __raw_readw(BALLOON3_FPGA_VER); - if (ver > 0x0201) - pr_warn("The FPGA code, version 0x%04x, is newer than rel-0.3. " + if (ver < 0x4f08) + pr_warn("The FPGA code, version 0x%04x, is too old. " "PCMCIA/CF support might be broken in this version!", ver); @@ -97,8 +95,9 @@ static void balloon3_pcmcia_socket_state(struct soc_pcmcia_socket *skt, static int balloon3_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state) { - __raw_writew((state->flags & SS_RESET) ? BALLOON3_CF_RESET : 0, - BALLOON3_CF_CONTROL_REG); + __raw_writew(BALLOON3_CF_RESET, BALLOON3_CF_CONTROL_REG | + ((state->flags & SS_RESET) ? + BALLOON3_FPGA_SETnCLR : 0)); return 0; } diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c index ae07b4d..3755e7c 100644 --- a/drivers/pcmcia/pxa2xx_base.c +++ b/drivers/pcmcia/pxa2xx_base.c @@ -26,6 +26,7 @@ #include <linux/platform_device.h> #include <mach/hardware.h> +#include <mach/smemc.h> #include <asm/io.h> #include <asm/irq.h> #include <asm/system.h> @@ -116,37 +117,49 @@ static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz, static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock ) { - MCMEM(sock) = ((pxa2xx_mcxx_setup(speed, clock) + uint32_t val; + + val = ((pxa2xx_mcxx_setup(speed, clock) & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT) | ((pxa2xx_mcxx_asst(speed, clock) & MCXX_ASST_MASK) << MCXX_ASST_SHIFT) | ((pxa2xx_mcxx_hold(speed, clock) & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT); + __raw_writel(val, MCMEM(sock)); + return 0; } static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock ) { - MCIO(sock) = ((pxa2xx_mcxx_setup(speed, clock) + uint32_t val; + + val = ((pxa2xx_mcxx_setup(speed, clock) & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT) | ((pxa2xx_mcxx_asst(speed, clock) & MCXX_ASST_MASK) << MCXX_ASST_SHIFT) | ((pxa2xx_mcxx_hold(speed, clock) & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT); + __raw_writel(val, MCIO(sock)); + return 0; } static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock ) { - MCATT(sock) = ((pxa2xx_mcxx_setup(speed, clock) + uint32_t val; + + val = ((pxa2xx_mcxx_setup(speed, clock) & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT) | ((pxa2xx_mcxx_asst(speed, clock) & MCXX_ASST_MASK) << MCXX_ASST_SHIFT) | ((pxa2xx_mcxx_hold(speed, clock) & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT); + __raw_writel(val, MCATT(sock)); + return 0; } @@ -166,8 +179,8 @@ static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int cl static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt) { - unsigned int clk = get_memclk_frequency_10khz(); - return pxa2xx_pcmcia_set_mcxx(skt, clk); + unsigned long clk = clk_get_rate(skt->clk); + return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000); } #ifdef CONFIG_CPU_FREQ @@ -205,19 +218,18 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt, static void pxa2xx_configure_sockets(struct device *dev) { struct pcmcia_low_level *ops = dev->platform_data; - /* * We have at least one socket, so set MECR:CIT * (Card Is There) */ - MECR |= MECR_CIT; + uint32_t mecr = MECR_CIT; /* Set MECR:NOS (Number Of Sockets) */ if ((ops->first + ops->nr) > 1 || machine_is_viper() || machine_is_arcom_zeus()) - MECR |= MECR_NOS; - else - MECR &= ~MECR_NOS; + mecr |= MECR_NOS; + + __raw_writel(mecr, MECR); } static const char *skt_names[] = { @@ -270,24 +282,41 @@ static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev) struct pcmcia_low_level *ops; struct skt_dev_info *sinfo; struct soc_pcmcia_socket *skt; + struct clk *clk; ops = (struct pcmcia_low_level *)dev->dev.platform_data; - if (!ops) + if (!ops) { + ret = -ENODEV; + goto err0; + } + + if (cpu_is_pxa320() && ops->nr > 1) { + dev_err(&dev->dev, "pxa320 supports only one pcmcia slot"); + ret = -EINVAL; + goto err0; + } + + clk = clk_get(&dev->dev, NULL); + if (!clk) return -ENODEV; pxa2xx_drv_pcmcia_ops(ops); sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL); - if (!sinfo) + if (!sinfo) { + clk_put(clk); return -ENOMEM; + } sinfo->nskt = ops->nr; + sinfo->clk = clk; /* Initialize processor specific parameters */ for (i = 0; i < ops->nr; i++) { skt = &sinfo->skt[i]; skt->nr = ops->first + i; + skt->clk = clk; skt->ops = ops; skt->socket.owner = ops->owner; skt->socket.dev.parent = &dev->dev; @@ -295,18 +324,26 @@ static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev) ret = pxa2xx_drv_pcmcia_add_one(skt); if (ret) - break; + goto err1; } if (ret) { while (--i >= 0) soc_pcmcia_remove_one(&sinfo->skt[i]); kfree(sinfo); + clk_put(clk); } else { pxa2xx_configure_sockets(&dev->dev); dev_set_drvdata(&dev->dev, sinfo); } + return 0; + +err1: + while (--i >= 0) + soc_pcmcia_remove_one(&sinfo->skt[i]); + kfree(sinfo); +err0: return ret; } @@ -320,6 +357,7 @@ static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev) for (i = 0; i < sinfo->nskt; i++) soc_pcmcia_remove_one(&sinfo->skt[i]); + clk_put(sinfo->clk); kfree(sinfo); return 0; } diff --git a/drivers/pcmcia/pxa2xx_colibri.c b/drivers/pcmcia/pxa2xx_colibri.c new file mode 100644 index 0000000..c3f7219 --- /dev/null +++ b/drivers/pcmcia/pxa2xx_colibri.c @@ -0,0 +1,229 @@ +/* + * linux/drivers/pcmcia/pxa2xx_colibri.c + * + * Driver for Toradex Colibri PXA270 CF socket + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/gpio.h> + +#include <asm/mach-types.h> + +#include "soc_common.h" + +#define COLIBRI270_RESET_GPIO 53 +#define COLIBRI270_PPEN_GPIO 107 +#define COLIBRI270_BVD1_GPIO 83 +#define COLIBRI270_BVD2_GPIO 82 +#define COLIBRI270_DETECT_GPIO 84 +#define COLIBRI270_READY_GPIO 1 + +#define COLIBRI320_RESET_GPIO 77 +#define COLIBRI320_PPEN_GPIO 57 +#define COLIBRI320_BVD1_GPIO 53 +#define COLIBRI320_BVD2_GPIO 79 +#define COLIBRI320_DETECT_GPIO 81 +#define COLIBRI320_READY_GPIO 29 + +static struct { + int reset_gpio; + int ppen_gpio; + int bvd1_gpio; + int bvd2_gpio; + int detect_gpio; + int ready_gpio; +} colibri_pcmcia_gpio; + +static struct pcmcia_irqs colibri_irqs[] = { + { + .sock = 0, + .str = "PCMCIA CD" + }, +}; + +static int colibri_pcmcia_hw_init(struct soc_pcmcia_socket *skt) +{ + int ret; + + ret = gpio_request(colibri_pcmcia_gpio.detect_gpio, "DETECT"); + if (ret) + goto err1; + ret = gpio_direction_input(colibri_pcmcia_gpio.detect_gpio); + if (ret) + goto err2; + + ret = gpio_request(colibri_pcmcia_gpio.ready_gpio, "READY"); + if (ret) + goto err2; + ret = gpio_direction_input(colibri_pcmcia_gpio.ready_gpio); + if (ret) + goto err3; + + ret = gpio_request(colibri_pcmcia_gpio.bvd1_gpio, "BVD1"); + if (ret) + goto err3; + ret = gpio_direction_input(colibri_pcmcia_gpio.bvd1_gpio); + if (ret) + goto err4; + + ret = gpio_request(colibri_pcmcia_gpio.bvd2_gpio, "BVD2"); + if (ret) + goto err4; + ret = gpio_direction_input(colibri_pcmcia_gpio.bvd2_gpio); + if (ret) + goto err5; + + ret = gpio_request(colibri_pcmcia_gpio.ppen_gpio, "PPEN"); + if (ret) + goto err5; + ret = gpio_direction_output(colibri_pcmcia_gpio.ppen_gpio, 0); + if (ret) + goto err6; + + ret = gpio_request(colibri_pcmcia_gpio.reset_gpio, "RESET"); + if (ret) + goto err6; + ret = gpio_direction_output(colibri_pcmcia_gpio.reset_gpio, 1); + if (ret) + goto err7; + + colibri_irqs[0].irq = gpio_to_irq(colibri_pcmcia_gpio.detect_gpio); + skt->socket.pci_irq = gpio_to_irq(colibri_pcmcia_gpio.ready_gpio); + + return soc_pcmcia_request_irqs(skt, colibri_irqs, + ARRAY_SIZE(colibri_irqs)); + +err7: + gpio_free(colibri_pcmcia_gpio.detect_gpio); +err6: + gpio_free(colibri_pcmcia_gpio.ready_gpio); +err5: + gpio_free(colibri_pcmcia_gpio.bvd1_gpio); +err4: + gpio_free(colibri_pcmcia_gpio.bvd2_gpio); +err3: + gpio_free(colibri_pcmcia_gpio.reset_gpio); +err2: + gpio_free(colibri_pcmcia_gpio.ppen_gpio); +err1: + return ret; +} + +static void colibri_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) +{ + gpio_free(colibri_pcmcia_gpio.detect_gpio); + gpio_free(colibri_pcmcia_gpio.ready_gpio); + gpio_free(colibri_pcmcia_gpio.bvd1_gpio); + gpio_free(colibri_pcmcia_gpio.bvd2_gpio); + gpio_free(colibri_pcmcia_gpio.reset_gpio); + gpio_free(colibri_pcmcia_gpio.ppen_gpio); +} + +static void colibri_pcmcia_socket_state(struct soc_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + + state->detect = !!gpio_get_value(colibri_pcmcia_gpio.detect_gpio); + state->ready = !!gpio_get_value(colibri_pcmcia_gpio.ready_gpio); + state->bvd1 = !!gpio_get_value(colibri_pcmcia_gpio.bvd1_gpio); + state->bvd2 = !!gpio_get_value(colibri_pcmcia_gpio.bvd2_gpio); + state->wrprot = 0; + state->vs_3v = 1; + state->vs_Xv = 0; +} + +static int +colibri_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, + const socket_state_t *state) +{ + gpio_set_value(colibri_pcmcia_gpio.ppen_gpio, + !(state->Vcc == 33 && state->Vpp < 50)); + gpio_set_value(colibri_pcmcia_gpio.reset_gpio, state->flags & SS_RESET); + return 0; +} + +static void colibri_pcmcia_socket_init(struct soc_pcmcia_socket *skt) +{ +} + +static void colibri_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) +{ +} + +static struct pcmcia_low_level colibri_pcmcia_ops = { + .owner = THIS_MODULE, + + .first = 0, + .nr = 1, + + .hw_init = colibri_pcmcia_hw_init, + .hw_shutdown = colibri_pcmcia_hw_shutdown, + + .socket_state = colibri_pcmcia_socket_state, + .configure_socket = colibri_pcmcia_configure_socket, + + .socket_init = colibri_pcmcia_socket_init, + .socket_suspend = colibri_pcmcia_socket_suspend, +}; + +static struct platform_device *colibri_pcmcia_device; + +static int __init colibri_pcmcia_init(void) +{ + int ret; + + colibri_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); + if (!colibri_pcmcia_device) + return -ENOMEM; + + /* Colibri PXA270 */ + if (machine_is_colibri()) { + colibri_pcmcia_gpio.reset_gpio = COLIBRI270_RESET_GPIO; + colibri_pcmcia_gpio.ppen_gpio = COLIBRI270_PPEN_GPIO; + colibri_pcmcia_gpio.bvd1_gpio = COLIBRI270_BVD1_GPIO; + colibri_pcmcia_gpio.bvd2_gpio = COLIBRI270_BVD2_GPIO; + colibri_pcmcia_gpio.detect_gpio = COLIBRI270_DETECT_GPIO; + colibri_pcmcia_gpio.ready_gpio = COLIBRI270_READY_GPIO; + /* Colibri PXA320 */ + } else if (machine_is_colibri320()) { + colibri_pcmcia_gpio.reset_gpio = COLIBRI320_RESET_GPIO; + colibri_pcmcia_gpio.ppen_gpio = COLIBRI320_PPEN_GPIO; + colibri_pcmcia_gpio.bvd1_gpio = COLIBRI320_BVD1_GPIO; + colibri_pcmcia_gpio.bvd2_gpio = COLIBRI320_BVD2_GPIO; + colibri_pcmcia_gpio.detect_gpio = COLIBRI320_DETECT_GPIO; + colibri_pcmcia_gpio.ready_gpio = COLIBRI320_READY_GPIO; + } + + ret = platform_device_add_data(colibri_pcmcia_device, + &colibri_pcmcia_ops, sizeof(colibri_pcmcia_ops)); + + if (!ret) + ret = platform_device_add(colibri_pcmcia_device); + + if (ret) + platform_device_put(colibri_pcmcia_device); + + return ret; +} + +static void __exit colibri_pcmcia_exit(void) +{ + platform_device_unregister(colibri_pcmcia_device); +} + +module_init(colibri_pcmcia_init); +module_exit(colibri_pcmcia_exit); + +MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>"); +MODULE_DESCRIPTION("PCMCIA support for Toradex Colibri PXA270/PXA320"); +MODULE_ALIAS("platform:pxa2xx-pcmcia"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pcmcia/soc_common.h b/drivers/pcmcia/soc_common.h index bbcd538..9daa736 100644 --- a/drivers/pcmcia/soc_common.h +++ b/drivers/pcmcia/soc_common.h @@ -10,6 +10,7 @@ #define _ASM_ARCH_PCMCIA /* include the world */ +#include <linux/clk.h> #include <linux/cpufreq.h> #include <pcmcia/ss.h> #include <pcmcia/cistpl.h> @@ -29,6 +30,7 @@ struct soc_pcmcia_socket { * Info from low level handler */ unsigned int nr; + struct clk *clk; /* * Core PCMCIA state @@ -56,6 +58,7 @@ struct soc_pcmcia_socket { struct skt_dev_info { int nskt; + struct clk *clk; struct soc_pcmcia_socket skt[0]; }; diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 67eb377..5a7c8f1 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -41,6 +41,7 @@ config USB_ARCH_HAS_OHCI default y if MFD_TC6393XB default y if ARCH_W90X900 default y if ARCH_DAVINCI_DA8XX + default y if ARCH_CNS3XXX # PPC: default y if STB03xxx default y if PPC_MPC52xx @@ -66,6 +67,7 @@ config USB_ARCH_HAS_EHCI default y if ARCH_AT91SAM9G45 default y if ARCH_MXC default y if ARCH_OMAP3 + default y if ARCH_CNS3XXX default PCI # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface. diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c index 5bdbfe6..77b1eb5 100644 --- a/drivers/usb/gadget/fsl_mxc_udc.c +++ b/drivers/usb/gadget/fsl_mxc_udc.c @@ -93,9 +93,9 @@ void fsl_udc_clk_finalize(struct platform_device *pdev) /* workaround ENGcm09152 for i.MX35 */ if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) { - v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBPHYCTRL_OTGBASE_OFFSET)); - writel(v | USBPHYCTRL_EVDO, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + writel(v | USBPHYCTRL_EVDO, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBPHYCTRL_OTGBASE_OFFSET)); } #endif diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 6f4f8e6..f8970d1 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -147,6 +147,14 @@ config USB_W90X900_EHCI ---help--- Enables support for the W90X900 USB controller +config USB_CNS3XXX_EHCI + bool "Cavium CNS3XXX EHCI Module" + depends on USB_EHCI_HCD && ARCH_CNS3XXX + ---help--- + Enable support for the CNS3XXX SOC's on-chip EHCI controller. + It is needed for high-speed (480Mbit/sec) USB 2.0 device + support. + config USB_OXU210HP_HCD tristate "OXU210HP HCD support" depends on USB @@ -286,6 +294,13 @@ config USB_OHCI_HCD_SSB If unsure, say N. +config USB_CNS3XXX_OHCI + bool "Cavium CNS3XXX OHCI Module" + depends on USB_OHCI_HCD && ARCH_CNS3XXX + ---help--- + Enable support for the CNS3XXX SOC's on-chip OHCI controller. + It is needed for low-speed USB 1.0 device support. + config USB_OHCI_BIG_ENDIAN_DESC bool depends on USB_OHCI_HCD diff --git a/drivers/usb/host/ehci-cns3xxx.c b/drivers/usb/host/ehci-cns3xxx.c new file mode 100644 index 0000000..708a05b --- /dev/null +++ b/drivers/usb/host/ehci-cns3xxx.c @@ -0,0 +1,171 @@ +/* + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/atomic.h> +#include <mach/cns3xxx.h> +#include <mach/pm.h> + +static int cns3xxx_ehci_init(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + int retval; + + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + * + * Set USB AHB INCR length to 16 + */ + if (atomic_inc_return(&usb_pwr_ref) == 1) { + cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); + cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); + cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); + __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), + MISC_CHIP_CONFIG_REG); + } + + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + + hcd->has_tt = 0; + ehci_reset(ehci); + + retval = ehci_init(hcd); + if (retval) + return retval; + + ehci_port_power(ehci, 0); + + return retval; +} + +static const struct hc_driver cns3xxx_ehci_hc_driver = { + .description = hcd_name, + .product_desc = "CNS3XXX EHCI Host Controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + .reset = cns3xxx_ehci_init, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + .get_frame_number = ehci_get_frame, + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, +#ifdef CONFIG_PM + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, +#endif + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int cns3xxx_ehci_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct usb_hcd *hcd; + const struct hc_driver *driver = &cns3xxx_ehci_hc_driver; + struct resource *res; + int irq; + int retval; + + if (usb_disabled()) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(dev, "Found HC with no IRQ.\n"); + return -ENODEV; + } + irq = res->start; + + hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); + if (!hcd) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "Found HC with no register addr.\n"); + retval = -ENODEV; + goto err1; + } + + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, + driver->description)) { + dev_dbg(dev, "controller already in use\n"); + retval = -EBUSY; + goto err1; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (hcd->regs == NULL) { + dev_dbg(dev, "error mapping memory\n"); + retval = -EFAULT; + goto err2; + } + + retval = usb_add_hcd(hcd, irq, IRQF_SHARED); + if (retval == 0) + return retval; + + iounmap(hcd->regs); +err2: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err1: + usb_put_hcd(hcd); + + return retval; +} + +static int cns3xxx_ehci_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + */ + if (atomic_dec_return(&usb_pwr_ref) == 0) + cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); + + usb_put_hcd(hcd); + + platform_set_drvdata(pdev, NULL); + + return 0; +} + +MODULE_ALIAS("platform:cns3xxx-ehci"); + +static struct platform_driver cns3xxx_ehci_driver = { + .probe = cns3xxx_ehci_probe, + .remove = cns3xxx_ehci_remove, + .driver = { + .name = "cns3xxx-ehci", + }, +}; diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index e906280..d0c8f7c 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1216,6 +1216,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_octeon_driver #endif +#ifdef CONFIG_USB_CNS3XXX_EHCI +#include "ehci-cns3xxx.c" +#define PLATFORM_DRIVER cns3xxx_ehci_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ !defined(XILINX_OF_PLATFORM_DRIVER) diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index bce8505..a22d2df 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -28,7 +28,7 @@ #define ULPI_VIEWPORT_OFFSET 0x170 struct ehci_mxc_priv { - struct clk *usbclk, *ahbclk; + struct clk *usbclk, *ahbclk, *phy1clk; struct usb_hcd *hcd; }; @@ -168,17 +168,6 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev) goto err_ioremap; } - /* call platform specific init function */ - if (pdata->init) { - ret = pdata->init(pdev); - if (ret) { - dev_err(dev, "platform init failed\n"); - goto err_init; - } - /* platforms need some time to settle changed IO settings */ - mdelay(10); - } - /* enable clocks */ priv->usbclk = clk_get(dev, "usb"); if (IS_ERR(priv->usbclk)) { @@ -196,6 +185,28 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev) clk_enable(priv->ahbclk); } + /* "dr" device has its own clock */ + if (pdev->id == 0) { + priv->phy1clk = clk_get(dev, "usb_phy1"); + if (IS_ERR(priv->phy1clk)) { + ret = PTR_ERR(priv->phy1clk); + goto err_clk_phy; + } + clk_enable(priv->phy1clk); + } + + + /* call platform specific init function */ + if (pdata->init) { + ret = pdata->init(pdev); + if (ret) { + dev_err(dev, "platform init failed\n"); + goto err_init; + } + /* platforms need some time to settle changed IO settings */ + mdelay(10); + } + /* setup specific usb hw */ ret = mxc_initialize_usb_hw(pdev->id, pdata->flags); if (ret < 0) @@ -230,6 +241,11 @@ err_add: if (pdata && pdata->exit) pdata->exit(pdev); err_init: + if (priv->phy1clk) { + clk_disable(priv->phy1clk); + clk_put(priv->phy1clk); + } +err_clk_phy: if (priv->ahbclk) { clk_disable(priv->ahbclk); clk_put(priv->ahbclk); @@ -273,6 +289,10 @@ static int __exit ehci_mxc_drv_remove(struct platform_device *pdev) clk_disable(priv->ahbclk); clk_put(priv->ahbclk); } + if (priv->phy1clk) { + clk_disable(priv->phy1clk); + clk_put(priv->phy1clk); + } kfree(priv); diff --git a/drivers/usb/host/ohci-cns3xxx.c b/drivers/usb/host/ohci-cns3xxx.c new file mode 100644 index 0000000..f05ef87 --- /dev/null +++ b/drivers/usb/host/ohci-cns3xxx.c @@ -0,0 +1,165 @@ +/* + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/atomic.h> +#include <mach/cns3xxx.h> +#include <mach/pm.h> + +static int __devinit +cns3xxx_ohci_start(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int ret; + + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + * + * Set USB AHB INCR length to 16 + */ + if (atomic_inc_return(&usb_pwr_ref) == 1) { + cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); + cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); + cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); + __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), + MISC_CHIP_CONFIG_REG); + } + + ret = ohci_init(ohci); + if (ret < 0) + return ret; + + ohci->num_ports = 1; + + ret = ohci_run(ohci); + if (ret < 0) { + err("can't start %s", hcd->self.bus_name); + ohci_stop(hcd); + return ret; + } + return 0; +} + +static const struct hc_driver cns3xxx_ohci_hc_driver = { + .description = hcd_name, + .product_desc = "CNS3XXX OHCI Host controller", + .hcd_priv_size = sizeof(struct ohci_hcd), + .irq = ohci_irq, + .flags = HCD_USB11 | HCD_MEMORY, + .start = cns3xxx_ohci_start, + .stop = ohci_stop, + .shutdown = ohci_shutdown, + .urb_enqueue = ohci_urb_enqueue, + .urb_dequeue = ohci_urb_dequeue, + .endpoint_disable = ohci_endpoint_disable, + .get_frame_number = ohci_get_frame, + .hub_status_data = ohci_hub_status_data, + .hub_control = ohci_hub_control, +#ifdef CONFIG_PM + .bus_suspend = ohci_bus_suspend, + .bus_resume = ohci_bus_resume, +#endif + .start_port_reset = ohci_start_port_reset, +}; + +static int cns3xxx_ohci_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct usb_hcd *hcd; + const struct hc_driver *driver = &cns3xxx_ohci_hc_driver; + struct resource *res; + int irq; + int retval; + + if (usb_disabled()) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(dev, "Found HC with no IRQ.\n"); + return -ENODEV; + } + irq = res->start; + + hcd = usb_create_hcd(driver, dev, dev_name(dev)); + if (!hcd) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "Found HC with no register addr.\n"); + retval = -ENODEV; + goto err1; + } + hcd->rsrc_start = res->start; + hcd->rsrc_len = res->end - res->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, + driver->description)) { + dev_dbg(dev, "controller already in use\n"); + retval = -EBUSY; + goto err1; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + dev_dbg(dev, "error mapping memory\n"); + retval = -EFAULT; + goto err2; + } + + ohci_hcd_init(hcd_to_ohci(hcd)); + + retval = usb_add_hcd(hcd, irq, IRQF_SHARED); + if (retval == 0) + return retval; + + iounmap(hcd->regs); +err2: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err1: + usb_put_hcd(hcd); + return retval; +} + +static int cns3xxx_ohci_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + */ + if (atomic_dec_return(&usb_pwr_ref) == 0) + cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); + + usb_put_hcd(hcd); + + platform_set_drvdata(pdev, NULL); + + return 0; +} + +MODULE_ALIAS("platform:cns3xxx-ohci"); + +static struct platform_driver ohci_hcd_cns3xxx_driver = { + .probe = cns3xxx_ohci_probe, + .remove = cns3xxx_ohci_remove, + .driver = { + .name = "cns3xxx-ohci", + }, +}; diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 5179acb..5cb6731 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1111,6 +1111,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ohci_octeon_driver #endif +#ifdef CONFIG_USB_CNS3XXX_OHCI +#include "ohci-cns3xxx.c" +#define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver +#endif + #if !defined(PCI_DRIVER) && \ !defined(PLATFORM_DRIVER) && \ !defined(OMAP1_PLATFORM_DRIVER) && \ diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 27c1fb4..ab77297 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -1850,6 +1850,16 @@ config FB_PXA_PARAMETERS <file:Documentation/fb/pxafb.txt> describes the available parameters. +config PXA3XX_GCU + tristate "PXA3xx 2D graphics accelerator driver" + depends on FB_PXA + help + Kernelspace driver for the 2D graphics controller unit (GCU) + found on PXA3xx processors. There is a counterpart driver in the + DirectFB suite, see http://www.directfb.org/ + + If you compile this as a module, it will be called pxa3xx_gcu. + config FB_MBX tristate "2700G LCD framebuffer support" depends on FB && ARCH_PXA diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 485e8ed..9260a89 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -100,6 +100,7 @@ obj-$(CONFIG_FB_CIRRUS) += cirrusfb.o obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o obj-$(CONFIG_FB_PXA) += pxafb.o obj-$(CONFIG_FB_PXA168) += pxa168fb.o +obj-$(CONFIG_PXA3XX_GCU) += pxa3xx-gcu.o obj-$(CONFIG_FB_W100) += w100fb.o obj-$(CONFIG_FB_TMIO) += tmiofb.o obj-$(CONFIG_FB_AU1100) += au1100fb.o diff --git a/drivers/video/pxa3xx-gcu.c b/drivers/video/pxa3xx-gcu.c new file mode 100644 index 0000000..b81168d --- /dev/null +++ b/drivers/video/pxa3xx-gcu.c @@ -0,0 +1,772 @@ +/* + * pxa3xx-gc.c - Linux kernel module for PXA3xx graphics controllers + * + * This driver needs a DirectFB counterpart in user space, communication + * is handled via mmap()ed memory areas and an ioctl. + * + * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> + * Copyright (c) 2009 Janine Kropp <nin@directfb.org> + * Copyright (c) 2009 Denis Oliver Kropp <dok@directfb.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * WARNING: This controller is attached to System Bus 2 of the PXA which + * needs its arbiter to be enabled explictly (CKENB & 1<<9). + * There is currently no way to do this from Linux, so you need to teach + * your bootloader for now. + */ + +#include <linux/module.h> +#include <linux/version.h> + +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/miscdevice.h> +#include <linux/interrupt.h> +#include <linux/spinlock.h> +#include <linux/uaccess.h> +#include <linux/ioctl.h> +#include <linux/delay.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/clk.h> +#include <linux/fs.h> +#include <linux/io.h> + +#include "pxa3xx-gcu.h" + +#define DRV_NAME "pxa3xx-gcu" +#define MISCDEV_MINOR 197 + +#define REG_GCCR 0x00 +#define GCCR_SYNC_CLR (1 << 9) +#define GCCR_BP_RST (1 << 8) +#define GCCR_ABORT (1 << 6) +#define GCCR_STOP (1 << 4) + +#define REG_GCISCR 0x04 +#define REG_GCIECR 0x08 +#define REG_GCRBBR 0x20 +#define REG_GCRBLR 0x24 +#define REG_GCRBHR 0x28 +#define REG_GCRBTR 0x2C +#define REG_GCRBEXHR 0x30 + +#define IE_EOB (1 << 0) +#define IE_EEOB (1 << 5) +#define IE_ALL 0xff + +#define SHARED_SIZE PAGE_ALIGN(sizeof(struct pxa3xx_gcu_shared)) + +/* #define PXA3XX_GCU_DEBUG */ +/* #define PXA3XX_GCU_DEBUG_TIMER */ + +#ifdef PXA3XX_GCU_DEBUG +#define QDUMP(msg) \ + do { \ + QPRINT(priv, KERN_DEBUG, msg); \ + } while (0) +#else +#define QDUMP(msg) do {} while (0) +#endif + +#define QERROR(msg) \ + do { \ + QPRINT(priv, KERN_ERR, msg); \ + } while (0) + +struct pxa3xx_gcu_batch { + struct pxa3xx_gcu_batch *next; + u32 *ptr; + dma_addr_t phys; + unsigned long length; +}; + +struct pxa3xx_gcu_priv { + void __iomem *mmio_base; + struct clk *clk; + struct pxa3xx_gcu_shared *shared; + dma_addr_t shared_phys; + struct resource *resource_mem; + struct miscdevice misc_dev; + struct file_operations misc_fops; + wait_queue_head_t wait_idle; + wait_queue_head_t wait_free; + spinlock_t spinlock; + struct timeval base_time; + + struct pxa3xx_gcu_batch *free; + + struct pxa3xx_gcu_batch *ready; + struct pxa3xx_gcu_batch *ready_last; + struct pxa3xx_gcu_batch *running; +}; + +static inline unsigned long +gc_readl(struct pxa3xx_gcu_priv *priv, unsigned int off) +{ + return __raw_readl(priv->mmio_base + off); +} + +static inline void +gc_writel(struct pxa3xx_gcu_priv *priv, unsigned int off, unsigned long val) +{ + __raw_writel(val, priv->mmio_base + off); +} + +#define QPRINT(priv, level, msg) \ + do { \ + struct timeval tv; \ + struct pxa3xx_gcu_shared *shared = priv->shared; \ + u32 base = gc_readl(priv, REG_GCRBBR); \ + \ + do_gettimeofday(&tv); \ + \ + printk(level "%ld.%03ld.%03ld - %-17s: %-21s (%s, " \ + "STATUS " \ + "0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, " \ + "T %5ld)\n", \ + tv.tv_sec - priv->base_time.tv_sec, \ + tv.tv_usec / 1000, tv.tv_usec % 1000, \ + __func__, msg, \ + shared->hw_running ? "running" : " idle", \ + gc_readl(priv, REG_GCISCR), \ + gc_readl(priv, REG_GCRBBR), \ + gc_readl(priv, REG_GCRBLR), \ + (gc_readl(priv, REG_GCRBEXHR) - base) / 4, \ + (gc_readl(priv, REG_GCRBHR) - base) / 4, \ + (gc_readl(priv, REG_GCRBTR) - base) / 4); \ + } while (0) + +static void +pxa3xx_gcu_reset(struct pxa3xx_gcu_priv *priv) +{ + QDUMP("RESET"); + + /* disable interrupts */ + gc_writel(priv, REG_GCIECR, 0); + + /* reset hardware */ + gc_writel(priv, REG_GCCR, GCCR_ABORT); + gc_writel(priv, REG_GCCR, 0); + + memset(priv->shared, 0, SHARED_SIZE); + priv->shared->buffer_phys = priv->shared_phys; + priv->shared->magic = PXA3XX_GCU_SHARED_MAGIC; + + do_gettimeofday(&priv->base_time); + + /* set up the ring buffer pointers */ + gc_writel(priv, REG_GCRBLR, 0); + gc_writel(priv, REG_GCRBBR, priv->shared_phys); + gc_writel(priv, REG_GCRBTR, priv->shared_phys); + + /* enable all IRQs except EOB */ + gc_writel(priv, REG_GCIECR, IE_ALL & ~IE_EOB); +} + +static void +dump_whole_state(struct pxa3xx_gcu_priv *priv) +{ + struct pxa3xx_gcu_shared *sh = priv->shared; + u32 base = gc_readl(priv, REG_GCRBBR); + + QDUMP("DUMP"); + + printk(KERN_DEBUG "== PXA3XX-GCU DUMP ==\n" + "%s, STATUS 0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, T %5ld\n", + sh->hw_running ? "running" : "idle ", + gc_readl(priv, REG_GCISCR), + gc_readl(priv, REG_GCRBBR), + gc_readl(priv, REG_GCRBLR), + (gc_readl(priv, REG_GCRBEXHR) - base) / 4, + (gc_readl(priv, REG_GCRBHR) - base) / 4, + (gc_readl(priv, REG_GCRBTR) - base) / 4); +} + +static void +flush_running(struct pxa3xx_gcu_priv *priv) +{ + struct pxa3xx_gcu_batch *running = priv->running; + struct pxa3xx_gcu_batch *next; + + while (running) { + next = running->next; + running->next = priv->free; + priv->free = running; + running = next; + } + + priv->running = NULL; +} + +static void +run_ready(struct pxa3xx_gcu_priv *priv) +{ + unsigned int num = 0; + struct pxa3xx_gcu_shared *shared = priv->shared; + struct pxa3xx_gcu_batch *ready = priv->ready; + + QDUMP("Start"); + + BUG_ON(!ready); + + shared->buffer[num++] = 0x05000000; + + while (ready) { + shared->buffer[num++] = 0x00000001; + shared->buffer[num++] = ready->phys; + ready = ready->next; + } + + shared->buffer[num++] = 0x05000000; + priv->running = priv->ready; + priv->ready = priv->ready_last = NULL; + gc_writel(priv, REG_GCRBLR, 0); + shared->hw_running = 1; + + /* ring base address */ + gc_writel(priv, REG_GCRBBR, shared->buffer_phys); + + /* ring tail address */ + gc_writel(priv, REG_GCRBTR, shared->buffer_phys + num * 4); + + /* ring length */ + gc_writel(priv, REG_GCRBLR, ((num + 63) & ~63) * 4); +} + +static irqreturn_t +pxa3xx_gcu_handle_irq(int irq, void *ctx) +{ + struct pxa3xx_gcu_priv *priv = ctx; + struct pxa3xx_gcu_shared *shared = priv->shared; + u32 status = gc_readl(priv, REG_GCISCR) & IE_ALL; + + QDUMP("-Interrupt"); + + if (!status) + return IRQ_NONE; + + spin_lock(&priv->spinlock); + shared->num_interrupts++; + + if (status & IE_EEOB) { + QDUMP(" [EEOB]"); + + flush_running(priv); + wake_up_all(&priv->wait_free); + + if (priv->ready) { + run_ready(priv); + } else { + /* There is no more data prepared by the userspace. + * Set hw_running = 0 and wait for the next userspace + * kick-off */ + shared->num_idle++; + shared->hw_running = 0; + + QDUMP(" '-> Idle."); + + /* set ring buffer length to zero */ + gc_writel(priv, REG_GCRBLR, 0); + + wake_up_all(&priv->wait_idle); + } + + shared->num_done++; + } else { + QERROR(" [???]"); + dump_whole_state(priv); + } + + /* Clear the interrupt */ + gc_writel(priv, REG_GCISCR, status); + spin_unlock(&priv->spinlock); + + return IRQ_HANDLED; +} + +static int +pxa3xx_gcu_wait_idle(struct pxa3xx_gcu_priv *priv) +{ + int ret = 0; + + QDUMP("Waiting for idle..."); + + /* Does not need to be atomic. There's a lock in user space, + * but anyhow, this is just for statistics. */ + priv->shared->num_wait_idle++; + + while (priv->shared->hw_running) { + int num = priv->shared->num_interrupts; + u32 rbexhr = gc_readl(priv, REG_GCRBEXHR); + + ret = wait_event_interruptible_timeout(priv->wait_idle, + !priv->shared->hw_running, HZ*4); + + if (ret < 0) + break; + + if (ret > 0) + continue; + + if (gc_readl(priv, REG_GCRBEXHR) == rbexhr && + priv->shared->num_interrupts == num) { + QERROR("TIMEOUT"); + ret = -ETIMEDOUT; + break; + } + } + + QDUMP("done"); + + return ret; +} + +static int +pxa3xx_gcu_wait_free(struct pxa3xx_gcu_priv *priv) +{ + int ret = 0; + + QDUMP("Waiting for free..."); + + /* Does not need to be atomic. There's a lock in user space, + * but anyhow, this is just for statistics. */ + priv->shared->num_wait_free++; + + while (!priv->free) { + u32 rbexhr = gc_readl(priv, REG_GCRBEXHR); + + ret = wait_event_interruptible_timeout(priv->wait_free, + priv->free, HZ*4); + + if (ret < 0) + break; + + if (ret > 0) + continue; + + if (gc_readl(priv, REG_GCRBEXHR) == rbexhr) { + QERROR("TIMEOUT"); + ret = -ETIMEDOUT; + break; + } + } + + QDUMP("done"); + + return ret; +} + +/* Misc device layer */ + +static ssize_t +pxa3xx_gcu_misc_write(struct file *filp, const char *buff, + size_t count, loff_t *offp) +{ + int ret; + unsigned long flags; + struct pxa3xx_gcu_batch *buffer; + struct pxa3xx_gcu_priv *priv = + container_of(filp->f_op, struct pxa3xx_gcu_priv, misc_fops); + + int words = count / 4; + + /* Does not need to be atomic. There's a lock in user space, + * but anyhow, this is just for statistics. */ + priv->shared->num_writes++; + + priv->shared->num_words += words; + + /* Last word reserved for batch buffer end command */ + if (words >= PXA3XX_GCU_BATCH_WORDS) + return -E2BIG; + + /* Wait for a free buffer */ + if (!priv->free) { + ret = pxa3xx_gcu_wait_free(priv); + if (ret < 0) + return ret; + } + + /* + * Get buffer from free list + */ + spin_lock_irqsave(&priv->spinlock, flags); + + buffer = priv->free; + priv->free = buffer->next; + + spin_unlock_irqrestore(&priv->spinlock, flags); + + + /* Copy data from user into buffer */ + ret = copy_from_user(buffer->ptr, buff, words * 4); + if (ret) { + spin_lock_irqsave(&priv->spinlock, flags); + buffer->next = priv->free; + priv->free = buffer; + spin_unlock_irqrestore(&priv->spinlock, flags); + return ret; + } + + buffer->length = words; + + /* Append batch buffer end command */ + buffer->ptr[words] = 0x01000000; + + /* + * Add buffer to ready list + */ + spin_lock_irqsave(&priv->spinlock, flags); + + buffer->next = NULL; + + if (priv->ready) { + BUG_ON(priv->ready_last == NULL); + + priv->ready_last->next = buffer; + } else + priv->ready = buffer; + + priv->ready_last = buffer; + + if (!priv->shared->hw_running) + run_ready(priv); + + spin_unlock_irqrestore(&priv->spinlock, flags); + + return words * 4; +} + + +static long +pxa3xx_gcu_misc_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + unsigned long flags; + struct pxa3xx_gcu_priv *priv = + container_of(filp->f_op, struct pxa3xx_gcu_priv, misc_fops); + + switch (cmd) { + case PXA3XX_GCU_IOCTL_RESET: + spin_lock_irqsave(&priv->spinlock, flags); + pxa3xx_gcu_reset(priv); + spin_unlock_irqrestore(&priv->spinlock, flags); + return 0; + + case PXA3XX_GCU_IOCTL_WAIT_IDLE: + return pxa3xx_gcu_wait_idle(priv); + } + + return -ENOSYS; +} + +static int +pxa3xx_gcu_misc_mmap(struct file *filp, struct vm_area_struct *vma) +{ + unsigned int size = vma->vm_end - vma->vm_start; + struct pxa3xx_gcu_priv *priv = + container_of(filp->f_op, struct pxa3xx_gcu_priv, misc_fops); + + switch (vma->vm_pgoff) { + case 0: + /* hand out the shared data area */ + if (size != SHARED_SIZE) + return -EINVAL; + + return dma_mmap_coherent(NULL, vma, + priv->shared, priv->shared_phys, size); + + case SHARED_SIZE >> PAGE_SHIFT: + /* hand out the MMIO base for direct register access + * from userspace */ + if (size != resource_size(priv->resource_mem)) + return -EINVAL; + + vma->vm_flags |= VM_IO; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + return io_remap_pfn_range(vma, vma->vm_start, + priv->resource_mem->start >> PAGE_SHIFT, + size, vma->vm_page_prot); + } + + return -EINVAL; +} + + +#ifdef PXA3XX_GCU_DEBUG_TIMER +static struct timer_list pxa3xx_gcu_debug_timer; + +static void pxa3xx_gcu_debug_timedout(unsigned long ptr) +{ + struct pxa3xx_gcu_priv *priv = (struct pxa3xx_gcu_priv *) ptr; + + QERROR("Timer DUMP"); + + /* init the timer structure */ + init_timer(&pxa3xx_gcu_debug_timer); + pxa3xx_gcu_debug_timer.function = pxa3xx_gcu_debug_timedout; + pxa3xx_gcu_debug_timer.data = ptr; + pxa3xx_gcu_debug_timer.expires = jiffies + 5*HZ; /* one second */ + + add_timer(&pxa3xx_gcu_debug_timer); +} + +static void pxa3xx_gcu_init_debug_timer(void) +{ + pxa3xx_gcu_debug_timedout((unsigned long) &pxa3xx_gcu_debug_timer); +} +#else +static inline void pxa3xx_gcu_init_debug_timer(void) {} +#endif + +static int +add_buffer(struct platform_device *dev, + struct pxa3xx_gcu_priv *priv) +{ + struct pxa3xx_gcu_batch *buffer; + + buffer = kzalloc(sizeof(struct pxa3xx_gcu_batch), GFP_KERNEL); + if (!buffer) + return -ENOMEM; + + buffer->ptr = dma_alloc_coherent(&dev->dev, PXA3XX_GCU_BATCH_WORDS * 4, + &buffer->phys, GFP_KERNEL); + if (!buffer->ptr) { + kfree(buffer); + return -ENOMEM; + } + + buffer->next = priv->free; + + priv->free = buffer; + + return 0; +} + +static void +free_buffers(struct platform_device *dev, + struct pxa3xx_gcu_priv *priv) +{ + struct pxa3xx_gcu_batch *next, *buffer = priv->free; + + while (buffer) { + next = buffer->next; + + dma_free_coherent(&dev->dev, PXA3XX_GCU_BATCH_WORDS * 4, + buffer->ptr, buffer->phys); + + kfree(buffer); + + buffer = next; + } + + priv->free = NULL; +} + +static int __devinit +pxa3xx_gcu_probe(struct platform_device *dev) +{ + int i, ret, irq; + struct resource *r; + struct pxa3xx_gcu_priv *priv; + + priv = kzalloc(sizeof(struct pxa3xx_gcu_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + for (i = 0; i < 8; i++) { + ret = add_buffer(dev, priv); + if (ret) { + dev_err(&dev->dev, "failed to allocate DMA memory\n"); + goto err_free_priv; + } + } + + init_waitqueue_head(&priv->wait_idle); + init_waitqueue_head(&priv->wait_free); + spin_lock_init(&priv->spinlock); + + /* we allocate the misc device structure as part of our own allocation, + * so we can get a pointer to our priv structure later on with + * container_of(). This isn't really necessary as we have a fixed minor + * number anyway, but this is to avoid statics. */ + + priv->misc_fops.owner = THIS_MODULE; + priv->misc_fops.write = pxa3xx_gcu_misc_write; + priv->misc_fops.unlocked_ioctl = pxa3xx_gcu_misc_ioctl; + priv->misc_fops.mmap = pxa3xx_gcu_misc_mmap; + + priv->misc_dev.minor = MISCDEV_MINOR, + priv->misc_dev.name = DRV_NAME, + priv->misc_dev.fops = &priv->misc_fops, + + /* register misc device */ + ret = misc_register(&priv->misc_dev); + if (ret < 0) { + dev_err(&dev->dev, "misc_register() for minor %d failed\n", + MISCDEV_MINOR); + goto err_free_priv; + } + + /* handle IO resources */ + r = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (r == NULL) { + dev_err(&dev->dev, "no I/O memory resource defined\n"); + ret = -ENODEV; + goto err_misc_deregister; + } + + if (!request_mem_region(r->start, resource_size(r), dev->name)) { + dev_err(&dev->dev, "failed to request I/O memory\n"); + ret = -EBUSY; + goto err_misc_deregister; + } + + priv->mmio_base = ioremap_nocache(r->start, resource_size(r)); + if (!priv->mmio_base) { + dev_err(&dev->dev, "failed to map I/O memory\n"); + ret = -EBUSY; + goto err_free_mem_region; + } + + /* allocate dma memory */ + priv->shared = dma_alloc_coherent(&dev->dev, SHARED_SIZE, + &priv->shared_phys, GFP_KERNEL); + + if (!priv->shared) { + dev_err(&dev->dev, "failed to allocate DMA memory\n"); + ret = -ENOMEM; + goto err_free_io; + } + + /* enable the clock */ + priv->clk = clk_get(&dev->dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(&dev->dev, "failed to get clock\n"); + ret = -ENODEV; + goto err_free_dma; + } + + ret = clk_enable(priv->clk); + if (ret < 0) { + dev_err(&dev->dev, "failed to enable clock\n"); + goto err_put_clk; + } + + /* request the IRQ */ + irq = platform_get_irq(dev, 0); + if (irq < 0) { + dev_err(&dev->dev, "no IRQ defined\n"); + ret = -ENODEV; + goto err_put_clk; + } + + ret = request_irq(irq, pxa3xx_gcu_handle_irq, + IRQF_DISABLED, DRV_NAME, priv); + if (ret) { + dev_err(&dev->dev, "request_irq failed\n"); + ret = -EBUSY; + goto err_put_clk; + } + + platform_set_drvdata(dev, priv); + priv->resource_mem = r; + pxa3xx_gcu_reset(priv); + pxa3xx_gcu_init_debug_timer(); + + dev_info(&dev->dev, "registered @0x%p, DMA 0x%p (%d bytes), IRQ %d\n", + (void *) r->start, (void *) priv->shared_phys, + SHARED_SIZE, irq); + return 0; + +err_put_clk: + clk_disable(priv->clk); + clk_put(priv->clk); + +err_free_dma: + dma_free_coherent(&dev->dev, SHARED_SIZE, + priv->shared, priv->shared_phys); + +err_free_io: + iounmap(priv->mmio_base); + +err_free_mem_region: + release_mem_region(r->start, resource_size(r)); + +err_misc_deregister: + misc_deregister(&priv->misc_dev); + +err_free_priv: + platform_set_drvdata(dev, NULL); + free_buffers(dev, priv); + kfree(priv); + return ret; +} + +static int __devexit +pxa3xx_gcu_remove(struct platform_device *dev) +{ + struct pxa3xx_gcu_priv *priv = platform_get_drvdata(dev); + struct resource *r = priv->resource_mem; + + pxa3xx_gcu_wait_idle(priv); + + misc_deregister(&priv->misc_dev); + dma_free_coherent(&dev->dev, SHARED_SIZE, + priv->shared, priv->shared_phys); + iounmap(priv->mmio_base); + release_mem_region(r->start, resource_size(r)); + platform_set_drvdata(dev, NULL); + clk_disable(priv->clk); + free_buffers(dev, priv); + kfree(priv); + + return 0; +} + +static struct platform_driver pxa3xx_gcu_driver = { + .probe = pxa3xx_gcu_probe, + .remove = __devexit_p(pxa3xx_gcu_remove), + .driver = { + .owner = THIS_MODULE, + .name = DRV_NAME, + }, +}; + +static int __init +pxa3xx_gcu_init(void) +{ + return platform_driver_register(&pxa3xx_gcu_driver); +} + +static void __exit +pxa3xx_gcu_exit(void) +{ + platform_driver_unregister(&pxa3xx_gcu_driver); +} + +module_init(pxa3xx_gcu_init); +module_exit(pxa3xx_gcu_exit); + +MODULE_DESCRIPTION("PXA3xx graphics controller unit driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_MISCDEV(MISCDEV_MINOR); +MODULE_AUTHOR("Janine Kropp <nin@directfb.org>, " + "Denis Oliver Kropp <dok@directfb.org>, " + "Daniel Mack <daniel@caiaq.de>"); diff --git a/drivers/video/pxa3xx-gcu.h b/drivers/video/pxa3xx-gcu.h new file mode 100644 index 0000000..0428ed0 --- /dev/null +++ b/drivers/video/pxa3xx-gcu.h @@ -0,0 +1,38 @@ +#ifndef __PXA3XX_GCU_H__ +#define __PXA3XX_GCU_H__ + +#include <linux/types.h> + +/* Number of 32bit words in display list (ring buffer). */ +#define PXA3XX_GCU_BUFFER_WORDS ((256 * 1024 - 256) / 4) + +/* To be increased when breaking the ABI */ +#define PXA3XX_GCU_SHARED_MAGIC 0x30000001 + +#define PXA3XX_GCU_BATCH_WORDS 8192 + +struct pxa3xx_gcu_shared { + u32 buffer[PXA3XX_GCU_BUFFER_WORDS]; + + bool hw_running; + + unsigned long buffer_phys; + + unsigned int num_words; + unsigned int num_writes; + unsigned int num_done; + unsigned int num_interrupts; + unsigned int num_wait_idle; + unsigned int num_wait_free; + unsigned int num_idle; + + u32 magic; +}; + +/* Initialization and synchronization. + * Hardware is started upon write(). */ +#define PXA3XX_GCU_IOCTL_RESET _IO('G', 0) +#define PXA3XX_GCU_IOCTL_WAIT_IDLE _IO('G', 2) + +#endif /* __PXA3XX_GCU_H__ */ + diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c index 2ee7dac..86f7cac 100644 --- a/drivers/watchdog/imx2_wdt.c +++ b/drivers/watchdog/imx2_wdt.c @@ -270,7 +270,7 @@ static int __init imx2_wdt_probe(struct platform_device *pdev) return -ENOMEM; } - imx2_wdt.clk = clk_get_sys("imx-wdt.0", NULL); + imx2_wdt.clk = clk_get(&pdev->dev, NULL); if (IS_ERR(imx2_wdt.clk)) { dev_err(&pdev->dev, "can't get Watchdog clock\n"); return PTR_ERR(imx2_wdt.clk); diff --git a/include/linux/mfd/tc35892.h b/include/linux/mfd/tc35892.h deleted file mode 100644 index eff3094..0000000 --- a/include/linux/mfd/tc35892.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License Terms: GNU General Public License, version 2 - */ - -#ifndef __LINUX_MFD_TC35892_H -#define __LINUX_MFD_TC35892_H - -#include <linux/device.h> - -#define TC35892_RSTCTRL_IRQRST (1 << 4) -#define TC35892_RSTCTRL_TIMRST (1 << 3) -#define TC35892_RSTCTRL_ROTRST (1 << 2) -#define TC35892_RSTCTRL_KBDRST (1 << 1) -#define TC35892_RSTCTRL_GPIRST (1 << 0) - -#define TC35892_IRQST 0x91 - -#define TC35892_MANFCODE_MAGIC 0x03 -#define TC35892_MANFCODE 0x80 -#define TC35892_VERSION 0x81 -#define TC35892_IOCFG 0xA7 - -#define TC35892_CLKMODE 0x88 -#define TC35892_CLKCFG 0x89 -#define TC35892_CLKEN 0x8A - -#define TC35892_RSTCTRL 0x82 -#define TC35892_EXTRSTN 0x83 -#define TC35892_RSTINTCLR 0x84 - -#define TC35892_GPIOIS0 0xC9 -#define TC35892_GPIOIS1 0xCA -#define TC35892_GPIOIS2 0xCB -#define TC35892_GPIOIBE0 0xCC -#define TC35892_GPIOIBE1 0xCD -#define TC35892_GPIOIBE2 0xCE -#define TC35892_GPIOIEV0 0xCF -#define TC35892_GPIOIEV1 0xD0 -#define TC35892_GPIOIEV2 0xD1 -#define TC35892_GPIOIE0 0xD2 -#define TC35892_GPIOIE1 0xD3 -#define TC35892_GPIOIE2 0xD4 -#define TC35892_GPIORIS0 0xD6 -#define TC35892_GPIORIS1 0xD7 -#define TC35892_GPIORIS2 0xD8 -#define TC35892_GPIOMIS0 0xD9 -#define TC35892_GPIOMIS1 0xDA -#define TC35892_GPIOMIS2 0xDB -#define TC35892_GPIOIC0 0xDC -#define TC35892_GPIOIC1 0xDD -#define TC35892_GPIOIC2 0xDE - -#define TC35892_GPIODATA0 0xC0 -#define TC35892_GPIOMASK0 0xc1 -#define TC35892_GPIODATA1 0xC2 -#define TC35892_GPIOMASK1 0xc3 -#define TC35892_GPIODATA2 0xC4 -#define TC35892_GPIOMASK2 0xC5 - -#define TC35892_GPIODIR0 0xC6 -#define TC35892_GPIODIR1 0xC7 -#define TC35892_GPIODIR2 0xC8 - -#define TC35892_GPIOSYNC0 0xE6 -#define TC35892_GPIOSYNC1 0xE7 -#define TC35892_GPIOSYNC2 0xE8 - -#define TC35892_GPIOWAKE0 0xE9 -#define TC35892_GPIOWAKE1 0xEA -#define TC35892_GPIOWAKE2 0xEB - -#define TC35892_GPIOODM0 0xE0 -#define TC35892_GPIOODE0 0xE1 -#define TC35892_GPIOODM1 0xE2 -#define TC35892_GPIOODE1 0xE3 -#define TC35892_GPIOODM2 0xE4 -#define TC35892_GPIOODE2 0xE5 - -#define TC35892_INT_GPIIRQ 0 -#define TC35892_INT_TI0IRQ 1 -#define TC35892_INT_TI1IRQ 2 -#define TC35892_INT_TI2IRQ 3 -#define TC35892_INT_ROTIRQ 5 -#define TC35892_INT_KBDIRQ 6 -#define TC35892_INT_PORIRQ 7 - -#define TC35892_NR_INTERNAL_IRQS 8 -#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x)) - -struct tc35892 { - struct mutex lock; - struct device *dev; - struct i2c_client *i2c; - - int irq_base; - int num_gpio; - struct tc35892_platform_data *pdata; -}; - -extern int tc35892_reg_write(struct tc35892 *tc35892, u8 reg, u8 data); -extern int tc35892_reg_read(struct tc35892 *tc35892, u8 reg); -extern int tc35892_block_read(struct tc35892 *tc35892, u8 reg, u8 length, - u8 *values); -extern int tc35892_block_write(struct tc35892 *tc35892, u8 reg, u8 length, - const u8 *values); -extern int tc35892_set_bits(struct tc35892 *tc35892, u8 reg, u8 mask, u8 val); - -/** - * struct tc35892_gpio_platform_data - TC35892 GPIO platform data - * @gpio_base: first gpio number assigned to TC35892. A maximum of - * %TC35892_NR_GPIOS GPIOs will be allocated. - * @setup: callback for board-specific initialization - * @remove: callback for board-specific teardown - */ -struct tc35892_gpio_platform_data { - int gpio_base; - void (*setup)(struct tc35892 *tc35892, unsigned gpio_base); - void (*remove)(struct tc35892 *tc35892, unsigned gpio_base); -}; - -/** - * struct tc35892_platform_data - TC35892 platform data - * @irq_base: base IRQ number. %TC35892_NR_IRQS irqs will be used. - * @gpio: GPIO-specific platform data - */ -struct tc35892_platform_data { - int irq_base; - struct tc35892_gpio_platform_data *gpio; -}; - -#define TC35892_NR_GPIOS 24 -#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS) - -#endif diff --git a/include/linux/mfd/tc3589x.h b/include/linux/mfd/tc3589x.h new file mode 100644 index 0000000..16c76e1 --- /dev/null +++ b/include/linux/mfd/tc3589x.h @@ -0,0 +1,195 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License, version 2 + */ + +#ifndef __LINUX_MFD_TC3589x_H +#define __LINUX_MFD_TC3589x_H + +#include <linux/device.h> + +enum tx3589x_block { + TC3589x_BLOCK_GPIO = 1 << 0, + TC3589x_BLOCK_KEYPAD = 1 << 1, +}; + +#define TC3589x_RSTCTRL_IRQRST (1 << 4) +#define TC3589x_RSTCTRL_TIMRST (1 << 3) +#define TC3589x_RSTCTRL_ROTRST (1 << 2) +#define TC3589x_RSTCTRL_KBDRST (1 << 1) +#define TC3589x_RSTCTRL_GPIRST (1 << 0) + +/* Keyboard Configuration Registers */ +#define TC3589x_KBDSETTLE_REG 0x01 +#define TC3589x_KBDBOUNCE 0x02 +#define TC3589x_KBDSIZE 0x03 +#define TC3589x_KBCFG_LSB 0x04 +#define TC3589x_KBCFG_MSB 0x05 +#define TC3589x_KBDIC 0x08 +#define TC3589x_KBDMSK 0x09 +#define TC3589x_EVTCODE_FIFO 0x10 +#define TC3589x_KBDMFS 0x8F + +#define TC3589x_IRQST 0x91 + +#define TC3589x_MANFCODE_MAGIC 0x03 +#define TC3589x_MANFCODE 0x80 +#define TC3589x_VERSION 0x81 +#define TC3589x_IOCFG 0xA7 + +#define TC3589x_CLKMODE 0x88 +#define TC3589x_CLKCFG 0x89 +#define TC3589x_CLKEN 0x8A + +#define TC3589x_RSTCTRL 0x82 +#define TC3589x_EXTRSTN 0x83 +#define TC3589x_RSTINTCLR 0x84 + +/* Pull up/down configuration registers */ +#define TC3589x_IOCFG 0xA7 +#define TC3589x_IOPULLCFG0_LSB 0xAA +#define TC3589x_IOPULLCFG0_MSB 0xAB +#define TC3589x_IOPULLCFG1_LSB 0xAC +#define TC3589x_IOPULLCFG1_MSB 0xAD +#define TC3589x_IOPULLCFG2_LSB 0xAE + +#define TC3589x_GPIOIS0 0xC9 +#define TC3589x_GPIOIS1 0xCA +#define TC3589x_GPIOIS2 0xCB +#define TC3589x_GPIOIBE0 0xCC +#define TC3589x_GPIOIBE1 0xCD +#define TC3589x_GPIOIBE2 0xCE +#define TC3589x_GPIOIEV0 0xCF +#define TC3589x_GPIOIEV1 0xD0 +#define TC3589x_GPIOIEV2 0xD1 +#define TC3589x_GPIOIE0 0xD2 +#define TC3589x_GPIOIE1 0xD3 +#define TC3589x_GPIOIE2 0xD4 +#define TC3589x_GPIORIS0 0xD6 +#define TC3589x_GPIORIS1 0xD7 +#define TC3589x_GPIORIS2 0xD8 +#define TC3589x_GPIOMIS0 0xD9 +#define TC3589x_GPIOMIS1 0xDA +#define TC3589x_GPIOMIS2 0xDB +#define TC3589x_GPIOIC0 0xDC +#define TC3589x_GPIOIC1 0xDD +#define TC3589x_GPIOIC2 0xDE + +#define TC3589x_GPIODATA0 0xC0 +#define TC3589x_GPIOMASK0 0xc1 +#define TC3589x_GPIODATA1 0xC2 +#define TC3589x_GPIOMASK1 0xc3 +#define TC3589x_GPIODATA2 0xC4 +#define TC3589x_GPIOMASK2 0xC5 + +#define TC3589x_GPIODIR0 0xC6 +#define TC3589x_GPIODIR1 0xC7 +#define TC3589x_GPIODIR2 0xC8 + +#define TC3589x_GPIOSYNC0 0xE6 +#define TC3589x_GPIOSYNC1 0xE7 +#define TC3589x_GPIOSYNC2 0xE8 + +#define TC3589x_GPIOWAKE0 0xE9 +#define TC3589x_GPIOWAKE1 0xEA +#define TC3589x_GPIOWAKE2 0xEB + +#define TC3589x_GPIOODM0 0xE0 +#define TC3589x_GPIOODE0 0xE1 +#define TC3589x_GPIOODM1 0xE2 +#define TC3589x_GPIOODE1 0xE3 +#define TC3589x_GPIOODM2 0xE4 +#define TC3589x_GPIOODE2 0xE5 + +#define TC3589x_INT_GPIIRQ 0 +#define TC3589x_INT_TI0IRQ 1 +#define TC3589x_INT_TI1IRQ 2 +#define TC3589x_INT_TI2IRQ 3 +#define TC3589x_INT_ROTIRQ 5 +#define TC3589x_INT_KBDIRQ 6 +#define TC3589x_INT_PORIRQ 7 + +#define TC3589x_NR_INTERNAL_IRQS 8 +#define TC3589x_INT_GPIO(x) (TC3589x_NR_INTERNAL_IRQS + (x)) + +struct tc3589x { + struct mutex lock; + struct device *dev; + struct i2c_client *i2c; + + int irq_base; + int num_gpio; + struct tc3589x_platform_data *pdata; +}; + +extern int tc3589x_reg_write(struct tc3589x *tc3589x, u8 reg, u8 data); +extern int tc3589x_reg_read(struct tc3589x *tc3589x, u8 reg); +extern int tc3589x_block_read(struct tc3589x *tc3589x, u8 reg, u8 length, + u8 *values); +extern int tc3589x_block_write(struct tc3589x *tc3589x, u8 reg, u8 length, + const u8 *values); +extern int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val); + +/* + * Keypad related platform specific constants + * These values may be modified for fine tuning + */ +#define TC_KPD_ROWS 0x8 +#define TC_KPD_COLUMNS 0x8 +#define TC_KPD_DEBOUNCE_PERIOD 0xA3 +#define TC_KPD_SETTLE_TIME 0xA3 + +/** + * struct tc35893_platform_data - data structure for platform specific data + * @keymap_data: matrix scan code table for keycodes + * @krow: mask for available rows, value is 0xFF + * @kcol: mask for available columns, value is 0xFF + * @debounce_period: platform specific debounce time + * @settle_time: platform specific settle down time + * @irqtype: type of interrupt, falling or rising edge + * @enable_wakeup: specifies if keypad event can wake up system from sleep + * @no_autorepeat: flag for auto repetition + */ +struct tc3589x_keypad_platform_data { + const struct matrix_keymap_data *keymap_data; + u8 krow; + u8 kcol; + u8 debounce_period; + u8 settle_time; + unsigned long irqtype; + bool enable_wakeup; + bool no_autorepeat; +}; + +/** + * struct tc3589x_gpio_platform_data - TC3589x GPIO platform data + * @gpio_base: first gpio number assigned to TC3589x. A maximum of + * %TC3589x_NR_GPIOS GPIOs will be allocated. + * @setup: callback for board-specific initialization + * @remove: callback for board-specific teardown + */ +struct tc3589x_gpio_platform_data { + int gpio_base; + void (*setup)(struct tc3589x *tc3589x, unsigned gpio_base); + void (*remove)(struct tc3589x *tc3589x, unsigned gpio_base); +}; + +/** + * struct tc3589x_platform_data - TC3589x platform data + * @block: bitmask of blocks to enable (use TC3589x_BLOCK_*) + * @irq_base: base IRQ number. %TC3589x_NR_IRQS irqs will be used. + * @gpio: GPIO-specific platform data + * @keypad: keypad-specific platform data + */ +struct tc3589x_platform_data { + unsigned int block; + int irq_base; + struct tc3589x_gpio_platform_data *gpio; + const struct tc3589x_keypad_platform_data *keypad; +}; + +#define TC3589x_NR_GPIOS 24 +#define TC3589x_NR_IRQS TC3589x_INT_GPIO(TC3589x_NR_GPIOS) + +#endif |
