diff options
819 files changed, 34925 insertions, 10317 deletions
diff --git a/Documentation/arm/pxa/mfp.txt b/Documentation/arm/pxa/mfp.txt new file mode 100644 index 0000000..a179e5b --- /dev/null +++ b/Documentation/arm/pxa/mfp.txt @@ -0,0 +1,286 @@ + MFP Configuration for PXA2xx/PXA3xx Processors + + Eric Miao <eric.miao@marvell.com> + +MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and +later PXA series processors. This document describes the existing MFP API, +and how board/platform driver authors could make use of it. + + Basic Concept +=============== + +Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP +mechanism is introduced from PXA3xx to completely move the pin-mux functions +out of the GPIO controller. In addition to pin-mux configurations, the MFP +also controls the low power state, driving strength, pull-up/down and event +detection of each pin. Below is a diagram of internal connections between +the MFP logic and the remaining SoC peripherals: + + +--------+ + | |--(GPIO19)--+ + | GPIO | | + | |--(GPIO...) | + +--------+ | + | +---------+ + +--------+ +------>| | + | PWM2 |--(PWM_OUT)-------->| MFP | + +--------+ +------>| |-------> to external PAD + | +---->| | + +--------+ | | +-->| | + | SSP2 |---(TXD)----+ | | +---------+ + +--------+ | | + | | + +--------+ | | + | Keypad |--(MKOUT4)----+ | + +--------+ | + | + +--------+ | + | UART2 |---(TXD)--------+ + +--------+ + +NOTE: the external pad is named as MFP_PIN_GPIO19, it doesn't necessarily +mean it's dedicated for GPIO19, only as a hint that internally this pin +can be routed from GPIO19 of the GPIO controller. + +To better understand the change from PXA25x/PXA27x GPIO alternate function +to this new MFP mechanism, here are several key points: + + 1. GPIO controller on PXA3xx is now a dedicated controller, same as other + internal controllers like PWM, SSP and UART, with 128 internal signals + which can be routed to external through one or more MFPs (e.g. GPIO<0> + can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2, + see arch/arm/mach-pxa/mach/include/mfp-pxa300.h) + + 2. Alternate function configuration is removed from this GPIO controller, + the remaining functions are pure GPIO-specific, i.e. + + - GPIO signal level control + - GPIO direction control + - GPIO level change detection + + 3. Low power state for each pin is now controlled by MFP, this means the + PGSRx registers on PXA2xx are now useless on PXA3xx + + 4. Wakeup detection is now controlled by MFP, PWER does not control the + wakeup from GPIO(s) any more, depending on the sleeping state, ADxER + (as defined in pxa3xx-regs.h) controls the wakeup from MFP + +NOTE: with such a clear separation of MFP and GPIO, by GPIO<xx> we normally +mean it is a GPIO signal, and by MFP<xxx> or pin xxx, we mean a physical +pad (or ball). + + MFP API Usage +=============== + +For board code writers, here are some guidelines: + +1. include ONE of the following header files in your <board>.c: + + - #include <mach/mfp-pxa25x.h> + - #include <mach/mfp-pxa27x.h> + - #include <mach/mfp-pxa300.h> + - #include <mach/mfp-pxa320.h> + - #include <mach/mfp-pxa930.h> + + NOTE: only one file in your <board>.c, depending on the processors used, + because pin configuration definitions may conflict in these file (i.e. + same name, different meaning and settings on different processors). E.g. + for zylonite platform, which support both PXA300/PXA310 and PXA320, two + separate files are introduced: zylonite_pxa300.c and zylonite_pxa320.c + (in addition to handle MFP configuration differences, they also handle + the other differences between the two combinations). + + NOTE: PXA300 and PXA310 are almost identical in pin configurations (with + PXA310 supporting some additional ones), thus the difference is actually + covered in a single mfp-pxa300.h. + +2. prepare an array for the initial pin configurations, e.g.: + + static unsigned long mainstone_pin_config[] __initdata = { + /* Chip Select */ + GPIO15_nCS_1, + + /* LCD - 16bpp Active TFT */ + GPIOxx_TFT_LCD_16BPP, + GPIO16_PWM0_OUT, /* Backlight */ + + /* MMC */ + GPIO32_MMC_CLK, + GPIO112_MMC_CMD, + GPIO92_MMC_DAT_0, + GPIO109_MMC_DAT_1, + GPIO110_MMC_DAT_2, + GPIO111_MMC_DAT_3, + + ... + + /* GPIO */ + GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, + }; + + a) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(), + and written to the actual registers, they are useless and may discard, + adding '__initdata' will help save some additional bytes here. + + b) when there is only one possible pin configurations for a component, + some simplified definitions can be used, e.g. GPIOxx_TFT_LCD_16BPP on + PXA25x and PXA27x processors + + c) if by board design, a pin can be configured to wake up the system + from low power state, it can be 'OR'ed with any of: + + WAKEUP_ON_EDGE_BOTH + WAKEUP_ON_EDGE_RISE + WAKEUP_ON_EDGE_FALL + WAKEUP_ON_LEVEL_HIGH - specifically for enabling of keypad GPIOs, + + to indicate that this pin has the capability of wake-up the system, + and on which edge(s). This, however, doesn't necessarily mean the + pin _will_ wakeup the system, it will only when set_irq_wake() is + invoked with the corresponding GPIO IRQ (GPIO_IRQ(xx) or gpio_to_irq()) + and eventually calls gpio_set_wake() for the actual register setting. + + d) although PXA3xx MFP supports edge detection on each pin, the + internal logic will only wakeup the system when those specific bits + in ADxER registers are set, which can be well mapped to the + corresponding peripheral, thus set_irq_wake() can be called with + the peripheral IRQ to enable the wakeup. + + + MFP on PXA3xx +=============== + +Every external I/O pad on PXA3xx (excluding those for special purpose) has +one MFP logic associated, and is controlled by one MFP register (MFPR). + +The MFPR has the following bit definitions (for PXA300/PXA310/PXA320): + + 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ + | RESERVED |PS|PU|PD| DRIVE |SS|SD|SO|EC|EF|ER|--| AF_SEL | + +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ + + Bit 3: RESERVED + Bit 4: EDGE_RISE_EN - enable detection of rising edge on this pin + Bit 5: EDGE_FALL_EN - enable detection of falling edge on this pin + Bit 6: EDGE_CLEAR - disable edge detection on this pin + Bit 7: SLEEP_OE_N - enable outputs during low power modes + Bit 8: SLEEP_DATA - output data on the pin during low power modes + Bit 9: SLEEP_SEL - selection control for low power modes signals + Bit 13: PULLDOWN_EN - enable the internal pull-down resistor on this pin + Bit 14: PULLUP_EN - enable the internal pull-up resistor on this pin + Bit 15: PULL_SEL - pull state controlled by selected alternate function + (0) or by PULL{UP,DOWN}_EN bits (1) + + Bit 0 - 2: AF_SEL - alternate function selection, 8 possibilities, from 0-7 + Bit 10-12: DRIVE - drive strength and slew rate + 0b000 - fast 1mA + 0b001 - fast 2mA + 0b002 - fast 3mA + 0b003 - fast 4mA + 0b004 - slow 6mA + 0b005 - fast 6mA + 0b006 - slow 10mA + 0b007 - fast 10mA + + MFP Design for PXA2xx/PXA3xx +============================== + +Due to the difference of pin-mux handling between PXA2xx and PXA3xx, a unified +MFP API is introduced to cover both series of processors. + +The basic idea of this design is to introduce definitions for all possible pin +configurations, these definitions are processor and platform independent, and +the actual API invoked to convert these definitions into register settings and +make them effective there-after. + + Files Involved + -------------- + + - arch/arm/mach-pxa/include/mach/mfp.h + + for + 1. Unified pin definitions - enum constants for all configurable pins + 2. processor-neutral bit definitions for a possible MFP configuration + + - arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h + + for PXA3xx specific MFPR register bit definitions and PXA3xx common pin + configurations + + - arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h + + for PXA2xx specific definitions and PXA25x/PXA27x common pin configurations + + - arch/arm/mach-pxa/include/mach/mfp-pxa25x.h + arch/arm/mach-pxa/include/mach/mfp-pxa27x.h + arch/arm/mach-pxa/include/mach/mfp-pxa300.h + arch/arm/mach-pxa/include/mach/mfp-pxa320.h + arch/arm/mach-pxa/include/mach/mfp-pxa930.h + + for processor specific definitions + + - arch/arm/mach-pxa/mfp-pxa3xx.c + - arch/arm/mach-pxa/mfp-pxa2xx.c + + for implementation of the pin configuration to take effect for the actual + processor. + + Pin Configuration + ----------------- + + The following comments are copied from mfp.h (see the actual source code + for most updated info) + + /* + * a possible MFP configuration is represented by a 32-bit integer + * + * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) + * bit 10..12 - Alternate Function Selection + * bit 13..15 - Drive Strength + * bit 16..18 - Low Power Mode State + * bit 19..20 - Low Power Mode Edge Detection + * bit 21..22 - Run Mode Pull State + * + * to facilitate the definition, the following macros are provided + * + * MFP_CFG_DEFAULT - default MFP configuration value, with + * alternate function = 0, + * drive strength = fast 3mA (MFP_DS03X) + * low power mode = default + * edge detection = none + * + * MFP_CFG - default MFPR value with alternate function + * MFP_CFG_DRV - default MFPR value with alternate function and + * pin drive strength + * MFP_CFG_LPM - default MFPR value with alternate function and + * low power mode + * MFP_CFG_X - default MFPR value with alternate function, + * pin drive strength and low power mode + */ + + Examples of pin configurations are: + + #define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) + + which reads GPIO94 can be configured as SSP3_RXD, with alternate function + selection of 1, driving strength of 0b101, and a float state in low power + modes. + + NOTE: this is the default setting of this pin being configured as SSP3_RXD + which can be modified a bit in board code, though it is not recommended to + do so, simply because this default setting is usually carefully encoded, + and is supposed to work in most cases. + + Register Settings + ----------------- + + Register settings on PXA3xx for a pin configuration is actually very + straight-forward, most bits can be converted directly into MFPR value + in a easier way. Two sets of MFPR values are calculated: the run-time + ones and the low power mode ones, to allow different settings. + + The conversion from a generic pin configuration to the actual register + settings on PXA2xx is a bit complicated: many registers are involved, + including GAFRx, GPDRx, PGSRx, PWER, PKWR, PFER and PRER. Please see + mfp-pxa2xx.c for how the conversion is made. diff --git a/Documentation/fb/pxafb.txt b/Documentation/fb/pxafb.txt index db9b850..d143a0a 100644 --- a/Documentation/fb/pxafb.txt +++ b/Documentation/fb/pxafb.txt @@ -5,9 +5,13 @@ The driver supports the following options, either via options=<OPTIONS> when modular or video=pxafb:<OPTIONS> when built in. For example: - modprobe pxafb options=mode:640x480-8,passive + modprobe pxafb options=vmem:2M,mode:640x480-8,passive or on the kernel command line - video=pxafb:mode:640x480-8,passive + video=pxafb:vmem:2M,mode:640x480-8,passive + +vmem: VIDEO_MEM_SIZE + Amount of video memory to allocate (can be suffixed with K or M + for kilobytes or megabytes) mode:XRESxYRES[-BPP] XRES == LCCR1_PPL + 1 @@ -52,3 +56,87 @@ outputen:POLARITY pixclockpol:POLARITY pixel clock polarity 0 => falling edge, 1 => rising edge + + +Overlay Support for PXA27x and later LCD controllers +==================================================== + + PXA27x and later processors support overlay1 and overlay2 on-top of the + base framebuffer (although under-neath the base is also possible). They + support palette and no-palette RGB formats, as well as YUV formats (only + available on overlay2). These overlays have dedicated DMA channels and + behave in a similar way as a framebuffer. + + However, there are some differences between these overlay framebuffers + and normal framebuffers, as listed below: + + 1. overlay can start at a 32-bit word aligned position within the base + framebuffer, which means they have a start (x, y). This information + is encoded into var->nonstd (no, var->xoffset and var->yoffset are + not for such purpose). + + 2. overlay framebuffer is allocated dynamically according to specified + 'struct fb_var_screeninfo', the amount is decided by: + + var->xres_virtual * var->yres_virtual * bpp + + bpp = 16 -- for RGB565 or RGBT555 + = 24 -- for YUV444 packed + = 24 -- for YUV444 planar + = 16 -- for YUV422 planar (1 pixel = 1 Y + 1/2 Cb + 1/2 Cr) + = 12 -- for YUV420 planar (1 pixel = 1 Y + 1/4 Cb + 1/4 Cr) + + NOTE: + + a. overlay does not support panning in x-direction, thus + var->xres_virtual will always be equal to var->xres + + b. line length of overlay(s) must be on a 32-bit word boundary, + for YUV planar modes, it is a requirement for the component + with minimum bits per pixel, e.g. for YUV420, Cr component + for one pixel is actually 2-bits, it means the line length + should be a multiple of 16-pixels + + c. starting horizontal position (XPOS) should start on a 32-bit + word boundary, otherwise the fb_check_var() will just fail. + + d. the rectangle of the overlay should be within the base plane, + otherwise fail + + Applications should follow the sequence below to operate an overlay + framebuffer: + + a. open("/dev/fb[1-2]", ...) + b. ioctl(fd, FBIOGET_VSCREENINFO, ...) + c. modify 'var' with desired parameters: + 1) var->xres and var->yres + 2) larger var->yres_virtual if more memory is required, + usually for double-buffering + 3) var->nonstd for starting (x, y) and color format + 4) var->{red, green, blue, transp} if RGB mode is to be used + d. ioctl(fd, FBIOPUT_VSCREENINFO, ...) + e. ioctl(fd, FBIOGET_FSCREENINFO, ...) + f. mmap + g. ... + + 3. for YUV planar formats, these are actually not supported within the + framebuffer framework, application has to take care of the offsets + and lengths of each component within the framebuffer. + + 4. var->nonstd is used to pass starting (x, y) position and color format, + the detailed bit fields are shown below: + + 31 23 20 10 0 + +-----------------+---+----------+----------+ + | ... unused ... |FOR| XPOS | YPOS | + +-----------------+---+----------+----------+ + + FOR - color format, as defined by OVERLAY_FORMAT_* in pxafb.h + 0 - RGB + 1 - YUV444 PACKED + 2 - YUV444 PLANAR + 3 - YUV422 PLANAR + 4 - YUR420 PLANAR + + XPOS - starting horizontal position + YPOS - starting vertical position diff --git a/MAINTAINERS b/MAINTAINERS index 08d0ab7..ceb32ee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1755,6 +1755,13 @@ L: linuxppc-dev@ozlabs.org L: linux-i2c@vger.kernel.org S: Maintained +FREESCALE IMX / MXC FRAMEBUFFER DRIVER +P: Sascha Hauer +M: kernel@pengutronix.de +L: linux-fbdev-devel@lists.sourceforge.net (moderated for non-subscribers) +L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) +S: Maintained + FREESCALE SOC FS_ENET DRIVER P: Pantelis Antoniou M: pantelis.antoniou@gmail.com diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9722f8b..d6ebe39 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -156,7 +156,6 @@ config ARCH_MTD_XIP bool config GENERIC_HARDIRQS_NO__DO_IRQ - bool def_bool y if OPROFILE @@ -201,6 +200,7 @@ choice config ARCH_AAEC2000 bool "Agilent AAEC-2000 based" + select CPU_ARM920T select ARM_AMBA select HAVE_CLK help @@ -210,6 +210,7 @@ config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" select ARM_AMBA select HAVE_CLK + select COMMON_CLKDEV select ICST525 help Support for ARM's Integrator platform. @@ -218,6 +219,7 @@ config ARCH_REALVIEW bool "ARM Ltd. RealView family" select ARM_AMBA select HAVE_CLK + select COMMON_CLKDEV select ICST307 select GENERIC_TIME select GENERIC_CLOCKEVENTS @@ -229,6 +231,7 @@ config ARCH_VERSATILE select ARM_AMBA select ARM_VIC select HAVE_CLK + select COMMON_CLKDEV select ICST307 select GENERIC_TIME select GENERIC_CLOCKEVENTS @@ -243,22 +246,15 @@ config ARCH_AT91 This enables support for systems based on the Atmel AT91RM9200, AT91SAM9 and AT91CAP9 processors. -config ARCH_CLPS7500 - bool "Cirrus CL-PS7500FE" - select TIMER_ACORN - select ISA - select NO_IOPORT - select ARCH_SPARSEMEM_ENABLE - help - Support for the Cirrus Logic PS7500FE system-on-a-chip. - config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x-based" + select CPU_ARM720T help Support for Cirrus Logic 711x/721x based boards. config ARCH_EBSA110 bool "EBSA-110" + select CPU_SA110 select ISA select NO_IOPORT help @@ -269,16 +265,19 @@ config ARCH_EBSA110 config ARCH_EP93XX bool "EP93xx-based" + select CPU_ARM920T select ARM_AMBA select ARM_VIC select GENERIC_GPIO select HAVE_CLK + select COMMON_CLKDEV select ARCH_REQUIRE_GPIOLIB help This enables support for the Cirrus EP93xx series of CPUs. config ARCH_FOOTBRIDGE bool "FootBridge" + select CPU_SA110 select FOOTBRIDGE help Support for systems based on the DC21285 companion chip @@ -286,18 +285,23 @@ config ARCH_FOOTBRIDGE config ARCH_NETX bool "Hilscher NetX based" + select CPU_ARM926T select ARM_VIC + select GENERIC_CLOCKEVENTS + select GENERIC_TIME help This enables support for systems based on the Hilscher NetX Soc config ARCH_H720X bool "Hynix HMS720x-based" + select CPU_ARM720T select ISA_DMA_API help This enables support for systems based on the Hynix HMS720x config ARCH_IMX bool "IMX" + select CPU_ARM920T select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS @@ -307,6 +311,7 @@ config ARCH_IMX config ARCH_IOP13XX bool "IOP13xx-based" depends on MMU + select CPU_XSC3 select PLAT_IOP select PCI select ARCH_SUPPORTS_MSI @@ -317,6 +322,7 @@ config ARCH_IOP13XX config ARCH_IOP32X bool "IOP32x-based" depends on MMU + select CPU_XSCALE select PLAT_IOP select PCI select GENERIC_GPIO @@ -328,6 +334,7 @@ config ARCH_IOP32X config ARCH_IOP33X bool "IOP33x-based" depends on MMU + select CPU_XSCALE select PLAT_IOP select PCI select GENERIC_GPIO @@ -338,6 +345,7 @@ config ARCH_IOP33X config ARCH_IXP23XX bool "IXP23XX-based" depends on MMU + select CPU_XSC3 select PCI help Support for Intel's IXP23xx (XScale) family of processors. @@ -345,6 +353,7 @@ config ARCH_IXP23XX config ARCH_IXP2000 bool "IXP2400/2800-based" depends on MMU + select CPU_XSCALE select PCI help Support for Intel's IXP2400/2800 (XScale) family of processors. @@ -352,6 +361,7 @@ config ARCH_IXP2000 config ARCH_IXP4XX bool "IXP4xx-based" depends on MMU + select CPU_XSCALE select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS @@ -361,6 +371,7 @@ config ARCH_IXP4XX config ARCH_L7200 bool "LinkUp-L7200" + select CPU_ARM720T select FIQ help Say Y here if you intend to run this kernel on a LinkUp Systems @@ -374,7 +385,9 @@ config ARCH_L7200 config ARCH_KIRKWOOD bool "Marvell Kirkwood" + select CPU_FEROCEON select PCI + select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION @@ -384,13 +397,16 @@ config ARCH_KIRKWOOD config ARCH_KS8695 bool "Micrel/Kendin KS8695" + select CPU_ARM922T select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB help Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based System-on-Chip devices. config ARCH_NS9XXX bool "NetSilicon NS9xxx" + select CPU_ARM926T select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS @@ -403,6 +419,7 @@ config ARCH_NS9XXX config ARCH_LOKI bool "Marvell Loki (88RC8480)" + select CPU_FEROCEON select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION @@ -411,7 +428,9 @@ config ARCH_LOKI config ARCH_MV78XX0 bool "Marvell MV78xx0" + select CPU_FEROCEON select PCI + select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS select PLAT_ORION @@ -432,6 +451,7 @@ config ARCH_MXC config ARCH_ORION5X bool "Marvell Orion" depends on MMU + select CPU_FEROCEON select PCI select GENERIC_GPIO select GENERIC_TIME @@ -444,6 +464,7 @@ config ARCH_ORION5X config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" + select CPU_ARM926T select HAVE_CLK help This enables support for Philips PNX4008 mobile platform. @@ -454,6 +475,7 @@ config ARCH_PXA select ARCH_MTD_XIP select GENERIC_GPIO select HAVE_CLK + select COMMON_CLKDEV select ARCH_REQUIRE_GPIOLIB select GENERIC_TIME select GENERIC_CLOCKEVENTS @@ -477,6 +499,7 @@ config ARCH_RPC config ARCH_SA1100 bool "SA1100-based" + select CPU_SA1100 select ISA select ARCH_SPARSEMEM_ENABLE select ARCH_MTD_XIP @@ -498,8 +521,16 @@ config ARCH_S3C2410 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the Samsung SMDK2410 development board (and derivatives). +config ARCH_S3C64XX + bool "Samsung S3C64XX" + select GENERIC_GPIO + select HAVE_CLK + help + Samsung S3C64XX series based systems + config ARCH_SHARK bool "Shark" + select CPU_SA110 select ISA select ISA_DMA select ZONE_DMA @@ -510,6 +541,7 @@ config ARCH_SHARK config ARCH_LH7A40X bool "Sharp LH7A40X" + select CPU_ARM922T select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM help @@ -520,6 +552,7 @@ config ARCH_LH7A40X config ARCH_DAVINCI bool "TI DaVinci" + select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS select GENERIC_GPIO @@ -541,6 +574,7 @@ config ARCH_OMAP config ARCH_MSM bool "Qualcomm MSM" + select CPU_V6 select GENERIC_TIME select GENERIC_CLOCKEVENTS help @@ -549,6 +583,13 @@ config ARCH_MSM interface to the ARM9 modem processor which runs the baseband stack and controls some vital subsystems (clock and power control, etc). +config ARCH_W90X900 + bool "Nuvoton W90X900 CPU" + select CPU_ARM926T + help + Support for Nuvoton (Winbond logic dept.) ARM9 processor,You + can login www.mcuos.com or www.nuvoton.com to know more. + endchoice source "arch/arm/mach-clps711x/Kconfig" @@ -590,6 +631,7 @@ source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/mach-kirkwood/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" +source "arch/arm/plat-s3c64xx/Kconfig" source "arch/arm/plat-s3c/Kconfig" if ARCH_S3C2410 @@ -601,6 +643,11 @@ source "arch/arm/mach-s3c2442/Kconfig" source "arch/arm/mach-s3c2443/Kconfig" endif +if ARCH_S3C64XX +source "arch/arm/mach-s3c6400/Kconfig" +source "arch/arm/mach-s3c6410/Kconfig" +endif + source "arch/arm/mach-lh7a40x/Kconfig" source "arch/arm/mach-imx/Kconfig" @@ -627,6 +674,8 @@ source "arch/arm/mach-ks8695/Kconfig" source "arch/arm/mach-msm/Kconfig" +source "arch/arm/mach-w90x900/Kconfig" + # Definitions to make life easier config ARCH_ACORN bool @@ -781,7 +830,7 @@ config HOTPLUG_CPU config LOCAL_TIMERS bool "Use local timer interrupts" - depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP) + depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || REALVIEW_EB_A9MP) default y help Enable support for local timers on SMP platforms, rather then the diff --git a/arch/arm/Makefile b/arch/arm/Makefile index bd6e281..24e0f01 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -76,6 +76,7 @@ tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110 tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100 tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale tune-$(CONFIG_CPU_XSC3) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale +tune-$(CONFIG_CPU_FEROCEON) :=$(call cc-option,-mtune=marvell-f,-mtune=xscale) tune-$(CONFIG_CPU_V6) :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm) ifeq ($(CONFIG_AEABI),y) @@ -96,7 +97,6 @@ textofs-y := 0x00008000 machine-$(CONFIG_ARCH_RPC) := rpc machine-$(CONFIG_ARCH_EBSA110) := ebsa110 - machine-$(CONFIG_ARCH_CLPS7500) := clps7500 machine-$(CONFIG_FOOTBRIDGE) := footbridge machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SA1100) := sa1100 @@ -121,7 +121,10 @@ endif machine-$(CONFIG_ARCH_OMAP3) := omap2 plat-$(CONFIG_ARCH_OMAP) := omap machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 + machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c + machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 + plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x machine-$(CONFIG_ARCH_VERSATILE) := versatile machine-$(CONFIG_ARCH_IMX) := imx @@ -139,11 +142,13 @@ endif plat-$(CONFIG_ARCH_MXC) := mxc machine-$(CONFIG_ARCH_MX2) := mx2 machine-$(CONFIG_ARCH_MX3) := mx3 + machine-$(CONFIG_ARCH_MX1) := mx1 machine-$(CONFIG_ARCH_ORION5X) := orion5x plat-$(CONFIG_PLAT_ORION) := orion machine-$(CONFIG_ARCH_MSM) := msm machine-$(CONFIG_ARCH_LOKI) := loki machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 + machine-$(CONFIG_ARCH_W90X900) := w90x900 ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index c47f2a3..fbe5eef 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -23,10 +23,6 @@ ifeq ($(CONFIG_ARCH_L7200),y) OBJS += head-l7200.o endif -ifeq ($(CONFIG_ARCH_CLPS7500),y) -HEAD = head-clps7500.o -endif - ifeq ($(CONFIG_ARCH_P720T),y) # Borrow this code from SA1100 OBJS += head-sa1100.o diff --git a/arch/arm/boot/compressed/head-clps7500.S b/arch/arm/boot/compressed/head-clps7500.S deleted file mode 100644 index 4f3c78a..0000000 --- a/arch/arm/boot/compressed/head-clps7500.S +++ /dev/null @@ -1,86 +0,0 @@ -/* - * linux/arch/arm/boot/compressed/head-clps7500.S - * - * Copyright (C) 1999, 2000, 2001 Nexus Electronics Ltd - */ - - - /* There are three different ways the kernel can be - booted on a 7500 system: from Angel (loaded in RAM), from - 16-bit ROM or from 32-bit Flash. Luckily, a single kernel - image does for them all. */ - /* This branch is taken if the CPU memory width matches the - actual device in use. The default at power on is 16 bits - so we must be prepared for a mismatch. */ - .section ".start", "ax" -2: - b 1f - .word 0xffff - .word 0xb632 @ mov r11, #0x03200000 - .word 0xe3a0 - .word 0x0000 @ mov r0, #0 - .word 0xe3a0 - .word 0x0080 @ strb r0, [r11, #0x80] - .word 0xe5cb - .word 0xf000 @ mov pc, #0 - .word 0xe3a0 -1: - adr r1, 2b - teq r1, #0 - bne .Langel - /* This is a direct-from-ROM boot. Copy the kernel into - RAM and run it there. */ - mov r0, #0x30 - mcr p15, 0, r0, c1, c0, 0 - mov r0, #0x13 - msr cpsr_cxsf, r0 - mov r12, #0x03000000 @ point to LEDs - orr r12, r12, #0x00020000 - orr r12, r12, #0xba00 - mov r0, #0x5500 - str r0, [r12] - mov r0, #0x10000000 - orr r0, r0, #0x8000 - mov r4, r0 - ldr r2, =_end -2: - ldr r3, [r1], #4 - str r3, [r0], #4 - teq r0, r2 - bne 2b - mov r0, #0xff00 - str r0, [r12] -1: - mov r12, #0x03000000 @ point to LEDs - orr r12, r12, #0x00020000 - orr r12, r12, #0xba00 - mov r0, #0xfe00 - str r0, [r12] - - adr lr, 1f - mov r0, #0 - mov r1, #14 /* MACH_TYPE_CLPS7500 */ - mov pc, lr -.Langel: -#ifdef CONFIG_ANGELBOOT - /* Call Angel to switch into SVC mode. */ - mov r0, #0x17 - swi 0x123456 -#endif - /* Ensure all interrupts are off and MMU disabled */ - mrs r0, cpsr - orr r0, r0, #0xc0 - msr cpsr_cxsf, r0 - - adr lr, 1b - orr lr, lr, #0x10000000 - mov r0, #0x30 @ MMU off - mcr p15, 0, r0, c1, c0, 0 - mov r0, r0 - mov pc, lr - - .ltorg - -1: -/* And the rest */ -#include "head.S" diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 84a1e04..77d61423 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -624,6 +624,12 @@ proc_types: b __armv4_mmu_cache_off b __armv4_mmu_cache_flush + .word 0x56056930 + .word 0xff0ffff0 @ PXA935 + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv4_mmu_cache_flush + .word 0x56050000 @ Feroceon .word 0xff0f0000 b __armv4_mmu_cache_on @@ -717,6 +723,9 @@ __armv7_mmu_cache_off: bl __armv7_mmu_cache_flush mov r0, #0 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB + mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC + mcr p15, 0, r0, c7, c10, 4 @ DSB + mcr p15, 0, r0, c7, c5, 4 @ ISB mov pc, r12 __arm6_mmu_cache_off: @@ -778,12 +787,13 @@ __armv6_mmu_cache_flush: __armv7_mmu_cache_flush: mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) - beq hierarchical mov r10, #0 + beq hierarchical mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D b iflush hierarchical: - stmfd sp!, {r0-r5, r7, r9-r11} + mcr p15, 0, r10, c7, c10, 5 @ DMB + stmfd sp!, {r0-r5, r7, r9, r11} mrc p15, 1, r0, c0, c0, 1 @ read clidr ands r3, r0, #0x7000000 @ extract loc from clidr mov r3, r3, lsr #23 @ left align loc bit field @@ -820,12 +830,14 @@ skip: cmp r3, r10 bgt loop1 finished: + ldmfd sp!, {r0-r5, r7, r9, r11} mov r10, #0 @ swith back to cache level 0 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - ldmfd sp!, {r0-r5, r7, r9-r11} iflush: + mcr p15, 0, r10, c7, c10, 4 @ DSB mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB - mcr p15, 0, r10, c7, c10, 4 @ drain WB + mcr p15, 0, r10, c7, c10, 4 @ DSB + mcr p15, 0, r10, c7, c5, 4 @ ISB mov pc, lr __armv5tej_mmu_cache_flush: diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index 65ce8ff..3fc0841 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c @@ -86,6 +86,8 @@ static void putstr(const char *ptr) #define __ptr_t void * +#define memzero(s,n) __memzero(s,n) + /* * Optimised C version of memzero for the ARM. */ diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index 86b5e69..a2cd9be 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -33,3 +33,6 @@ config SHARPSL_PM config SHARP_SCOOP bool + +config COMMON_CLKDEV + bool diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 325e4b6..7cb7961 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_SHARP_SCOOP) += scoop.o obj-$(CONFIG_ARCH_IXP2000) += uengine.o obj-$(CONFIG_ARCH_IXP23XX) += uengine.o obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o +obj-$(CONFIG_COMMON_CLKDEV) += clkdev.o diff --git a/arch/arm/common/clkdev.c b/arch/arm/common/clkdev.c new file mode 100644 index 0000000..17a17b4 --- /dev/null +++ b/arch/arm/common/clkdev.c @@ -0,0 +1,128 @@ +/* + * arch/arm/common/clkdev.c + * + * Copyright (C) 2008 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Helper for the clk API to assist looking up a struct clk. + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/string.h> +#include <linux/mutex.h> + +#include <asm/clkdev.h> +#include <mach/clkdev.h> + +static LIST_HEAD(clocks); +static DEFINE_MUTEX(clocks_mutex); + +static struct clk *clk_find(const char *dev_id, const char *con_id) +{ + struct clk_lookup *p; + struct clk *clk = NULL; + int match, best = 0; + + list_for_each_entry(p, &clocks, node) { + if ((p->dev_id && !dev_id) || (p->con_id && !con_id)) + continue; + match = 0; + if (p->dev_id) + match += 2 * (strcmp(p->dev_id, dev_id) == 0); + if (p->con_id) + match += 1 * (strcmp(p->con_id, con_id) == 0); + if (match == 0) + continue; + + if (match > best) { + clk = p->clk; + best = match; + } + } + return clk; +} + +struct clk *clk_get(struct device *dev, const char *con_id) +{ + const char *dev_id = dev ? dev_name(dev) : NULL; + struct clk *clk; + + mutex_lock(&clocks_mutex); + clk = clk_find(dev_id, con_id); + if (clk && !__clk_get(clk)) + clk = NULL; + mutex_unlock(&clocks_mutex); + + return clk ? clk : ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +void clk_put(struct clk *clk) +{ + __clk_put(clk); +} +EXPORT_SYMBOL(clk_put); + +void clkdev_add(struct clk_lookup *cl) +{ + mutex_lock(&clocks_mutex); + list_add_tail(&cl->node, &clocks); + mutex_unlock(&clocks_mutex); +} +EXPORT_SYMBOL(clkdev_add); + +#define MAX_DEV_ID 20 +#define MAX_CON_ID 16 + +struct clk_lookup_alloc { + struct clk_lookup cl; + char dev_id[MAX_DEV_ID]; + char con_id[MAX_CON_ID]; +}; + +struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id, + const char *dev_fmt, ...) +{ + struct clk_lookup_alloc *cla; + + cla = kzalloc(sizeof(*cla), GFP_KERNEL); + if (!cla) + return NULL; + + cla->cl.clk = clk; + if (con_id) { + strlcpy(cla->con_id, con_id, sizeof(cla->con_id)); + cla->cl.con_id = cla->con_id; + } + + if (dev_fmt) { + va_list ap; + + va_start(ap, dev_fmt); + vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap); + cla->cl.dev_id = cla->dev_id; + va_end(ap); + } + + return &cla->cl; +} +EXPORT_SYMBOL(clkdev_alloc); + +/* + * clkdev_drop - remove a clock dynamically allocated + */ +void clkdev_drop(struct clk_lookup *cl) +{ + mutex_lock(&clocks_mutex); + list_del(&cl->node); + mutex_unlock(&clocks_mutex); + kfree(cl); +} +EXPORT_SYMBOL(clkdev_drop); diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index 7c6b4b9..2293f0c 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -1108,6 +1108,7 @@ void locomo_frontlight_set(struct locomo_dev *dev, int duty, int vr, int bpwf) locomo_writel(bpwf | LOCOMO_ALC_EN, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); spin_unlock_irqrestore(&lchip->lock, flags); } +EXPORT_SYMBOL(locomo_frontlight_set); /* * LoCoMo "Register Access Bus." diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index f1e4b8f..ecf0bfb 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -69,12 +69,12 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, /* * Make sure we clear all existing interrupts */ - writel(0, base + VIC_VECT_ADDR); + writel(0, base + VIC_PL190_VECT_ADDR); for (i = 0; i < 19; i++) { unsigned int value; - value = readl(base + VIC_VECT_ADDR); - writel(value, base + VIC_VECT_ADDR); + value = readl(base + VIC_PL190_VECT_ADDR); + writel(value, base + VIC_PL190_VECT_ADDR); } for (i = 0; i < 16; i++) { @@ -82,7 +82,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, writel(VIC_VECT_CNTL_ENABLE | i, reg); } - writel(32, base + VIC_DEF_VECT_ADDR); + writel(32, base + VIC_PL190_DEF_VECT_ADDR); for (i = 0; i < 32; i++) { unsigned int irq = irq_start + i; diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig index 2307587..b6c5cbb 100644 --- a/arch/arm/configs/eseries_pxa_defconfig +++ b/arch/arm/configs/eseries_pxa_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26 -# Sat Jul 26 22:28:46 2008 +# Linux kernel version: 2.6.28-rc8 +# Wed Dec 24 23:35:45 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -22,8 +22,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_SUPPORTS_AOUT=y -CONFIG_ZONE_DMA=y CONFIG_ARCH_MTD_XIP=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 @@ -48,8 +46,7 @@ CONFIG_SYSVIPC_SYSCTL=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CGROUPS is not set # CONFIG_GROUP_SCHED is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set # CONFIG_BLK_DEV_INITRD is not set @@ -58,13 +55,12 @@ CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_KALLSYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_COMPAT_BRK=y +# CONFIG_COMPAT_BRK is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y @@ -73,6 +69,7 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set @@ -80,15 +77,10 @@ CONFIG_SLAB=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set -# CONFIG_HAVE_IOREMAP_PROT is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_ARCH_TRACEHOOK is not set -# CONFIG_HAVE_DMA_ATTRS is not set -# CONFIG_USE_GENERIC_SMP_HELPERS is not set CONFIG_HAVE_CLK=y -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set @@ -112,14 +104,15 @@ CONFIG_BLOCK=y # CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y # # System Type @@ -129,7 +122,6 @@ CONFIG_CLASSIC_RCU=y # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set @@ -160,7 +152,8 @@ CONFIG_ARCH_PXA=y # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_MSM7X00A is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_W90X900 is not set # # Intel PXA2xx/PXA3xx Implementations @@ -169,8 +162,10 @@ CONFIG_ARCH_PXA=y # CONFIG_ARCH_LUBBOCK is not set # CONFIG_MACH_LOGICPD_PXA270 is not set # CONFIG_MACH_MAINSTONE is not set +# CONFIG_MACH_MP900C is not set # CONFIG_ARCH_PXA_IDP is not set # CONFIG_PXA_SHARPSL is not set +# CONFIG_ARCH_VIPER is not set CONFIG_ARCH_PXA_ESERIES=y CONFIG_MACH_E330=y CONFIG_MACH_E350=y @@ -178,7 +173,8 @@ CONFIG_MACH_E740=y CONFIG_MACH_E750=y CONFIG_MACH_E400=y CONFIG_MACH_E800=y -# CONFIG_MACH_TRIZEPS4 is not set +# CONFIG_TRIZEPS_PXA is not set +# CONFIG_MACH_H5000 is not set # CONFIG_MACH_EM_X270 is not set # CONFIG_MACH_COLIBRI is not set # CONFIG_MACH_ZYLONITE is not set @@ -186,12 +182,15 @@ CONFIG_MACH_E800=y # CONFIG_MACH_TAVOREVB is not set # CONFIG_MACH_SAAR is not set # CONFIG_MACH_ARMCORE is not set +# CONFIG_MACH_CM_X300 is not set # CONFIG_MACH_MAGICIAN is not set +# CONFIG_MACH_MIOA701 is not set # CONFIG_MACH_PCM027 is not set # CONFIG_ARCH_PXA_PALM is not set # CONFIG_PXA_EZX is not set CONFIG_PXA25x=y # CONFIG_PXA_PWM is not set +CONFIG_PXA_HAVE_BOARD_IRQS=y # # Boot options @@ -222,6 +221,7 @@ CONFIG_CPU_CP15_MMU=y # CONFIG_OUTER_CACHE is not set CONFIG_IWMMXT=y CONFIG_XSCALE_PMU=y +CONFIG_COMMON_CLKDEV=y # # Bus support @@ -237,6 +237,7 @@ CONFIG_PCMCIA_IOCTL=y # # PC-card bridges # +CONFIG_PCMCIA_PXA2XX=m # # Kernel Features @@ -245,25 +246,30 @@ CONFIG_TICK_ONESHOT=y # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 # CONFIG_PREEMPT is not set CONFIG_HZ=100 CONFIG_AEABI=y CONFIG_OABI_COMPAT=y -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4096 # CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_ALIGNMENT_TRAP=y # @@ -277,9 +283,10 @@ CONFIG_KEXEC=y CONFIG_ATAGS_PROC=y # -# CPU Frequency scaling +# CPU Power Management # # CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set # # Floating point emulation @@ -296,6 +303,8 @@ CONFIG_FPE_NWFPE=y # Userspace binary formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_MISC=y @@ -309,10 +318,6 @@ CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y # CONFIG_APM_EMULATION is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y - -# -# Networking -# CONFIG_NET=y # @@ -339,7 +344,7 @@ CONFIG_IP_FIB_HASH=y # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set -CONFIG_INET_TUNNEL=y +# CONFIG_INET_TUNNEL is not set CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y @@ -350,25 +355,7 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=y -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_IPV6_MIP6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_INET6_XFRM_MODE_TRANSPORT=y -CONFIG_INET6_XFRM_MODE_TUNNEL=y -CONFIG_INET6_XFRM_MODE_BEET=y -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set -CONFIG_IPV6_SIT=y -CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set @@ -376,6 +363,7 @@ CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -421,25 +409,18 @@ CONFIG_IRDA_FAST_RR=y # # Dongle support # -# CONFIG_KINGSUN_DONGLE is not set -# CONFIG_KSDAZZLE_DONGLE is not set -# CONFIG_KS959_DONGLE is not set # # FIR device drivers # -# CONFIG_USB_IRDA is not set -# CONFIG_SIGMATEL_FIR is not set CONFIG_PXA_FICP=y -# CONFIG_MCS_FIR is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y CONFIG_CFG80211=m CONFIG_NL80211=y +CONFIG_WIRELESS_OLD_REGULATORY=y CONFIG_WIRELESS_EXT=y CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_MAC80211=m @@ -448,7 +429,9 @@ CONFIG_MAC80211=m # Rate control algorithm selection # CONFIG_MAC80211_RC_PID=y +# CONFIG_MAC80211_RC_MINSTREL is not set CONFIG_MAC80211_RC_DEFAULT_PID=y +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set CONFIG_MAC80211_RC_DEFAULT="pid" # CONFIG_MAC80211_MESH is not set # CONFIG_MAC80211_LEDS is not set @@ -539,11 +522,12 @@ CONFIG_MTD_NAND=m # CONFIG_MTD_NAND_VERIFY_WRITE is not set # CONFIG_MTD_NAND_ECC_SMC is not set # CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set CONFIG_MTD_NAND_IDS=m # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_SHARPSL is not set +CONFIG_MTD_NAND_TMIO=m # CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set # CONFIG_MTD_ONENAND is not set # @@ -556,13 +540,13 @@ CONFIG_BLK_DEV=y CONFIG_BLK_DEV_LOOP=m # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -632,37 +616,25 @@ CONFIG_NETDEVICES=y CONFIG_WLAN_80211=y # CONFIG_PCMCIA_RAYCS is not set # CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set CONFIG_HERMES=m CONFIG_PCMCIA_HERMES=m # CONFIG_PCMCIA_SPECTRUM is not set # CONFIG_ATMEL is not set # CONFIG_AIRO_CS is not set # CONFIG_PCMCIA_WL3501 is not set -# CONFIG_USB_ZD1201 is not set -# CONFIG_USB_NET_RNDIS_WLAN is not set -# CONFIG_RTL8187 is not set # CONFIG_MAC80211_HWSIM is not set # CONFIG_P54_COMMON is not set # CONFIG_IWLWIFI_LEDS is not set # CONFIG_HOSTAP is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set -# CONFIG_ZD1211RW is not set # CONFIG_RT2X00 is not set - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set CONFIG_NET_PCMCIA=y # CONFIG_PCMCIA_3C589 is not set # CONFIG_PCMCIA_3C574 is not set # CONFIG_PCMCIA_FMVJ18X is not set -CONFIG_PCMCIA_PCNET=m +# CONFIG_PCMCIA_PCNET is not set # CONFIG_PCMCIA_NMCLAN is not set # CONFIG_PCMCIA_SMC91C92 is not set # CONFIG_PCMCIA_XIRC2PS is not set @@ -714,13 +686,11 @@ CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_PENMOUNT is not set # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set # CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_UCB1400 is not set CONFIG_TOUCHSCREEN_WM97XX=m CONFIG_TOUCHSCREEN_WM9705=y CONFIG_TOUCHSCREEN_WM9712=y CONFIG_TOUCHSCREEN_WM9713=y # CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set # CONFIG_INPUT_MISC is not set @@ -749,11 +719,13 @@ CONFIG_DEVKMEM=y # # Non-8250 serial port support # -# CONFIG_SERIAL_PXA is not set +CONFIG_SERIAL_PXA=y +# CONFIG_SERIAL_PXA_CONSOLE is not set +CONFIG_SERIAL_CORE=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM is not set # CONFIG_NVRAM is not set # CONFIG_R3964 is not set @@ -773,6 +745,10 @@ CONFIG_GPIOLIB=y # CONFIG_GPIO_SYSFS is not set # +# Memory mapped GPIO expanders: +# + +# # I2C GPIO expanders: # @@ -786,12 +762,14 @@ CONFIG_GPIOLIB=y # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -799,8 +777,13 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE=y # CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_UCB1400_CORE is not set +CONFIG_MFD_TMIO=y +CONFIG_MFD_T7L66XB=y +CONFIG_MFD_TC6387XB=y CONFIG_MFD_TC6393XB=y # @@ -827,6 +810,7 @@ CONFIG_MFD_TC6393XB=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -851,8 +835,10 @@ CONFIG_FB_PXA=y # CONFIG_FB_PXA_PARAMETERS is not set # CONFIG_FB_MBX is not set CONFIG_FB_W100=y -# CONFIG_FB_AM200EPD is not set +# CONFIG_FB_TMIO is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y # CONFIG_LCD_ILI9320 is not set @@ -886,6 +872,7 @@ CONFIG_FONT_MINI_4x6=y # CONFIG_FONT_10x18 is not set # CONFIG_LOGO is not set CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m @@ -899,14 +886,18 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y CONFIG_SND_VERBOSE_PRINTK=y # CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=m CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set # CONFIG_SND_MTPAV is not set # CONFIG_SND_SERIAL_U16550 is not set # CONFIG_SND_MPU401 is not set +# CONFIG_SND_AC97_POWER_SAVE is not set CONFIG_SND_ARM=y +CONFIG_SND_PXA2XX_LIB=m +CONFIG_SND_PXA2XX_LIB_AC97=y # CONFIG_SND_PXA2XX_AC97 is not set -# CONFIG_SND_USB is not set # CONFIG_SND_PCMCIA is not set CONFIG_SND_SOC=m CONFIG_SND_SOC_AC97_BUS=y @@ -920,133 +911,19 @@ CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set # -# USB Input Devices +# Special HID drivers # -CONFIG_USB_HID=m -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set -# CONFIG_USB_HIDDEV is not set - -# -# USB HID Boot Protocol drivers -# -# CONFIG_USB_KBD is not set -# CONFIG_USB_MOUSE is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=m -# CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -# CONFIG_USB_DEVICEFS is not set -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_SUSPEND is not set -# CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# may also be needed; see USB_STORAGE Help for more information -# -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set -CONFIG_USB_MON=y - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGET is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_ISIGHTFW is not set -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_NET2280 is not set -CONFIG_USB_GADGET_PXA25X=y -CONFIG_USB_PXA25X=y -CONFIG_USB_PXA25X_SMALL=y -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -# CONFIG_USB_GADGET_DUALSPEED is not set -# CONFIG_USB_ZERO is not set -CONFIG_USB_ETH=m -# CONFIG_USB_ETH_RNDIS is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set +CONFIG_HID_COMPAT=y +# CONFIG_USB_SUPPORT is not set CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set CONFIG_MMC_UNSAFE_RESUME=y # -# MMC/SD Card Drivers +# MMC/SD/SDIO Card Drivers # CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_BOUNCE=y @@ -1054,14 +931,18 @@ CONFIG_MMC_BLOCK_BOUNCE=y # CONFIG_MMC_TEST is not set # -# MMC/SD Host Controller Drivers +# MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_PXA is not set # CONFIG_MMC_SDHCI is not set +CONFIG_MMC_TMIO=y +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set # CONFIG_NEW_LEDS is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set # CONFIG_UIO is not set # @@ -1070,11 +951,17 @@ CONFIG_RTC_LIB=y CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT3_FS=m +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=m +CONFIG_FS_MBCACHE=m # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -1106,6 +993,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_PROC_FS=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1142,6 +1030,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1228,13 +1117,15 @@ CONFIG_FRAME_WARN=1024 # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MEMORY_INIT is not set CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_LATENCYTOP is not set -CONFIG_HAVE_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -# CONFIG_FTRACE is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_USER is not set @@ -1244,15 +1135,23 @@ CONFIG_HAVE_ARCH_KGDB=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_ALGAPI2=m +CONFIG_CRYPTO_AEAD2=m CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=m +CONFIG_CRYPTO_HASH2=m +CONFIG_CRYPTO_RNG2=m CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_MANAGER2=m # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_CRYPTD is not set @@ -1324,14 +1223,17 @@ CONFIG_CRYPTO_ARC4=m # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=y # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set diff --git a/arch/arm/configs/h5000_defconfig b/arch/arm/configs/h5000_defconfig new file mode 100644 index 0000000..649baa3 --- /dev/null +++ b/arch/arm/configs/h5000_defconfig @@ -0,0 +1,996 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.27-rc6 +# Tue Sep 16 16:13:48 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_ZONE_DMA=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_CGROUPS is not set +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_UID16 is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_HAVE_IOREMAP_PROT is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_ARCH_TRACEHOOK is not set +# CONFIG_HAVE_DMA_ATTRS is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +CONFIG_HAVE_CLK=y +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM7X00A is not set + +# +# Intel PXA2xx/PXA3xx Implementations +# +# CONFIG_ARCH_GUMSTIX is not set +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_LOGICPD_PXA270 is not set +# CONFIG_MACH_MAINSTONE is not set +# CONFIG_ARCH_PXA_IDP is not set +# CONFIG_PXA_SHARPSL is not set +# CONFIG_ARCH_PXA_ESERIES is not set +CONFIG_MACH_H5000=y +# CONFIG_MACH_TRIZEPS4 is not set +# CONFIG_MACH_EM_X270 is not set +# CONFIG_MACH_COLIBRI is not set +# CONFIG_MACH_ZYLONITE is not set +# CONFIG_MACH_LITTLETON is not set +# CONFIG_MACH_TAVOREVB is not set +# CONFIG_MACH_SAAR is not set +# CONFIG_MACH_ARMCORE is not set +# CONFIG_MACH_MAGICIAN is not set +# CONFIG_MACH_PCM027 is not set +# CONFIG_ARCH_PXA_PALM is not set +# CONFIG_PXA_EZX is not set +CONFIG_PXA25x=y +# CONFIG_PXA_PWM is not set + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSCALE=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_OUTER_CACHE is not set +# CONFIG_IWMMXT is not set +CONFIG_XSCALE_PMU=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="keepinitrd" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_XIP is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x8000000 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_PXA2XX is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_SHARP_SL is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_APMPOWER is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=32 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +CONFIG_USB_GADGET_PXA25X=y +CONFIG_USB_PXA25X=y +CONFIG_USB_PXA25X_SMALL=y +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +# CONFIG_USB_GADGET_DUALSPEED is not set +# CONFIG_USB_ZERO is not set +CONFIG_USB_ETH=y +# CONFIG_USB_ETH_RNDIS is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_MMC is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_SA1100=y +# CONFIG_DMADEVICES is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +# CONFIG_FTRACE is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index e3357ba..ab8b1e0 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -1,11 +1,11 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26-rc5 -# Sun Jun 22 15:51:25 2008 +# Linux kernel version: 2.6.28-rc7 +# Thu Dec 4 15:27:39 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_GPIO is not set CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_MMU=y @@ -22,8 +22,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_SUPPORTS_AOUT=y -CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -49,14 +48,17 @@ CONFIG_LOG_BUF_SHIFT=14 # CONFIG_GROUP_SCHED is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set # CONFIG_BLK_DEV_INITRD is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y +# CONFIG_EMBEDDED is not set CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -73,9 +75,12 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set +CONFIG_PCI_QUIRKS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y # CONFIG_SLOB is not set CONFIG_PROFILING=y # CONFIG_MARKERS is not set @@ -85,8 +90,7 @@ CONFIG_KPROBES=y CONFIG_KRETPROBES=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set @@ -97,12 +101,13 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_KMOD is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -117,6 +122,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # System Type @@ -128,7 +134,6 @@ CONFIG_CLASSIC_RCU=y # CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set @@ -158,7 +163,7 @@ CONFIG_ARCH_KIRKWOOD=y # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_MSM7X00A is not set +# CONFIG_ARCH_MSM is not set # # Marvell Kirkwood Implementations @@ -199,6 +204,7 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_DCACHE_DISABLE is not set CONFIG_OUTER_CACHE=y CONFIG_CACHE_FEROCEON_L2=y +# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set # # Bus support @@ -217,25 +223,30 @@ CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 CONFIG_PREEMPT=y CONFIG_HZ=100 CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4096 # CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_ALIGNMENT_TRAP=y # @@ -248,6 +259,11 @@ CONFIG_CMDLINE="" # CONFIG_KEXEC is not set # +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# # Floating point emulation # @@ -260,6 +276,8 @@ CONFIG_CMDLINE="" # Userspace binary formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y # CONFIG_BINFMT_AOUT is not set # CONFIG_BINFMT_MISC is not set @@ -268,10 +286,6 @@ CONFIG_BINFMT_ELF=y # # CONFIG_PM is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y - -# -# Networking -# CONFIG_NET=y # @@ -322,6 +336,15 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +CONFIG_NET_DSA=y +# CONFIG_NET_DSA_TAG_DSA is not set +CONFIG_NET_DSA_TAG_EDSA=y +# CONFIG_NET_DSA_TAG_TRAILER is not set +CONFIG_NET_DSA_MV88E6XXX=y +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_MV88E6131 is not set +CONFIG_NET_DSA_MV88E6123_61_65=y # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -343,12 +366,12 @@ CONFIG_NET_PKTGEN=m # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set @@ -365,6 +388,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set @@ -453,7 +478,7 @@ CONFIG_M25PXX_USE_FAST_READ=y # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set # CONFIG_MTD_NAND_ECC_SMC is not set # CONFIG_MTD_NAND_MUSEUM_IDS is not set CONFIG_MTD_NAND_IDS=y @@ -561,6 +586,7 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_DH is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set CONFIG_SATA_PMP=y @@ -619,7 +645,6 @@ CONFIG_SATA_MV=y # CONFIG_PATA_SIS is not set # CONFIG_PATA_VIA is not set # CONFIG_PATA_WINBOND is not set -# CONFIG_PATA_PLATFORM is not set # CONFIG_PATA_SCH is not set # CONFIG_MD is not set # CONFIG_FUSION is not set @@ -627,11 +652,14 @@ CONFIG_SATA_MV=y # # IEEE 1394 (FireWire) support # + +# +# Enable only one of the two stacks, unless you know what you are doing +# # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -639,7 +667,23 @@ CONFIG_NETDEVICES=y # CONFIG_TUN is not set # CONFIG_VETH is not set # CONFIG_ARCNET is not set -# CONFIG_PHYLIB is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=y +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_AX88796 is not set @@ -650,12 +694,16 @@ CONFIG_MII=y # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set # CONFIG_ENC28J60 is not set +# CONFIG_SMC911X is not set # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -676,14 +724,12 @@ CONFIG_NET_PCI=y # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set -CONFIG_E1000=y -CONFIG_E1000_NAPI=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_E1000 is not set # CONFIG_E1000E is not set -# CONFIG_E1000E_ENABLED is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set # CONFIG_NS83820 is not set @@ -699,6 +745,8 @@ CONFIG_E1000_NAPI=y CONFIG_MV643XX_ETH=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_JME is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -765,7 +813,11 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # # Character devices # -# CONFIG_VT is not set +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set # CONFIG_DEVKMEM is not set # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_NOZOMI is not set @@ -775,7 +827,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_PCI=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 # CONFIG_SERIAL_8250_EXTENDED is not set @@ -800,44 +852,64 @@ CONFIG_DEVPORT=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y # # I2C Hardware Bus support # + +# +# PC SMBus host controller drivers +# # CONFIG_I2C_ALI1535 is not set # CONFIG_I2C_ALI1563 is not set # CONFIG_I2C_ALI15X3 is not set # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_GPIO is not set # CONFIG_I2C_I801 is not set -# CONFIG_I2C_I810 is not set +# CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PROSAVAGE is not set -# CONFIG_I2C_SAVAGE4 is not set -# CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_TINY_USB is not set # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_MV64XXX=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Graphics adapter I2C/DDC channel drivers +# # CONFIG_I2C_VOODOO3 is not set + +# +# Other I2C/SMBus bus drivers +# # CONFIG_I2C_PCA_PLATFORM is not set -CONFIG_I2C_MV64XXX=y +# CONFIG_I2C_STUB is not set # # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set +# CONFIG_AT24 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set @@ -864,20 +936,26 @@ CONFIG_SPI_ORION=y # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set # # Multimedia devices @@ -910,8 +988,10 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_DISPLAY_SUPPORT is not set # -# Sound +# Console display driver support # +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y @@ -922,9 +1002,36 @@ CONFIG_HID=y # USB Input Devices # CONFIG_USB_HID=y -# CONFIG_USB_HIDINPUT_POWERBOOK is not set -# CONFIG_HID_FF is not set +# CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -940,8 +1047,9 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -956,20 +1064,23 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers # # CONFIG_USB_ACM is not set -CONFIG_USB_PRINTER=y +CONFIG_USB_PRINTER=m # CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; # # -# may also be needed; see USB_STORAGE Help for more information +# see USB_STORAGE Help for more information # CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set @@ -992,7 +1103,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MON is not set # # USB port drivers @@ -1005,7 +1115,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1023,8 +1133,12 @@ CONFIG_USB_STORAGE_JUMPSHOT=y # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set # CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set CONFIG_NEW_LEDS=y # CONFIG_LEDS_CLASS is not set @@ -1038,6 +1152,8 @@ CONFIG_NEW_LEDS=y # CONFIG_LEDS_TRIGGERS is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" # CONFIG_RTC_DEBUG is not set # @@ -1056,7 +1172,6 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_DS1374 is not set # CONFIG_RTC_DRV_DS1672 is not set # CONFIG_RTC_DRV_MAX6900 is not set -CONFIG_RTC_DRV_MV=y # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_X1205 is not set @@ -1064,29 +1179,39 @@ CONFIG_RTC_DRV_MV=y # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set # CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set # # SPI RTC drivers # +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set # # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # # on-CPU RTC drivers # +CONFIG_RTC_DRV_MV=y CONFIG_DMADEVICES=y # @@ -1099,6 +1224,8 @@ CONFIG_DMA_ENGINE=y # DMA Clients # # CONFIG_NET_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_REGULATOR is not set # CONFIG_UIO is not set # @@ -1109,11 +1236,12 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y CONFIG_XFS_FS=y # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set @@ -1131,7 +1259,7 @@ CONFIG_INOTIFY_USER=y # # CD-ROM/DVD Filesystems # -CONFIG_ISO9660_FS=y +CONFIG_ISO9660_FS=m CONFIG_JOLIET=y # CONFIG_ZISOFS is not set CONFIG_UDF_FS=m @@ -1140,9 +1268,9 @@ CONFIG_UDF_NLS=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_NTFS_FS is not set @@ -1152,6 +1280,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_PROC_FS=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set @@ -1182,6 +1311,7 @@ CONFIG_JFFS2_RTIME=y CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set @@ -1192,13 +1322,13 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y -# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1210,24 +1340,8 @@ CONFIG_SUNRPC=y # # Partition Types # -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set +# CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y @@ -1284,11 +1398,14 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 # CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set # CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_PREEMPT is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set @@ -1300,21 +1417,40 @@ CONFIG_DETECT_SOFTLOCKUP=y # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_KPROBES_SANITY_TEST is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_LKDTM is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set @@ -1326,6 +1462,7 @@ CONFIG_DEBUG_LL=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_ASYNC_CORE=y CONFIG_CRYPTO=y @@ -1333,8 +1470,12 @@ CONFIG_CRYPTO=y # # Crypto core or helper # +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_AEAD=m CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_RNG=m CONFIG_CRYPTO_MANAGER=m # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -1373,6 +1514,10 @@ CONFIG_CRYPTO_PCBC=m # CONFIG_CRYPTO_MD4 is not set # CONFIG_CRYPTO_MD5 is not set # CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set @@ -1403,6 +1548,11 @@ CONFIG_CRYPTO_PCBC=m # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set @@ -1410,10 +1560,9 @@ CONFIG_CRYPTO_HW=y # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_CRC_CCITT=y CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set CONFIG_CRC_ITU_T=m CONFIG_CRC32=y # CONFIG_CRC7 is not set diff --git a/arch/arm/configs/ks8695_defconfig b/arch/arm/configs/ks8695_defconfig index 6077f2c..d25c41b 100644 --- a/arch/arm/configs/ks8695_defconfig +++ b/arch/arm/configs/ks8695_defconfig @@ -1,39 +1,67 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.17-rc4 -# Thu May 25 15:42:51 2006 +# Linux kernel version: 2.6.27-simtec-micrel1 +# Fri Dec 5 10:30:27 2008 # CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y +# CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -CONFIG_UID16=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y # CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -41,30 +69,50 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y +CONFIG_ANON_INODES=y CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_HAVE_IOREMAP_PROT is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_ARCH_TRACEHOOK is not set +# CONFIG_HAVE_DMA_ATTRS is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +# CONFIG_HAVE_CLK is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set -CONFIG_OBSOLETE_INTERMODULE=y - -# -# Loadable module support -# CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_KMOD=y - -# -# Block layer -# +CONFIG_BLOCK=y +# CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -78,60 +126,77 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y # # System Type # +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP3XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set # CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +CONFIG_ARCH_KS8695=y +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_AT91 is not set -CONFIG_ARCH_KS8695=y +# CONFIG_ARCH_MSM7X00A is not set + +# +# Boot options +# + +# +# Power management +# # # Kendin/Micrel KS8695 Implementations # CONFIG_MACH_KS8695=y -# CONFIG_MACH_DSM320 is not set -# CONFIG_MACH_CM4002 is not set -# CONFIG_MACH_CM4008 is not set -# CONFIG_MACH_CM40xx is not set -# CONFIG_MACH_LITE300 is not set -# CONFIG_MACH_SE4200 is not set -# CONFIG_MACH_MANGA_KS8695 is not set +CONFIG_MACH_DSM320=y # # Processor Type # CONFIG_CPU_32=y CONFIG_CPU_ARM922T=y -CONFIG_CPU_32v4=y +CONFIG_CPU_32v4T=y CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_PABRT_NOIFAR=y CONFIG_CPU_CACHE_V4WT=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_COPY_V4WB=y CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y # # Processor Features @@ -140,16 +205,16 @@ CONFIG_CPU_TLB_V4WBI=y # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_OUTER_CACHE is not set # # Bus support # CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y CONFIG_PCI_DEBUG=y - -# -# PCCARD (PCMCIA/CardBus) support -# CONFIG_PCCARD=y # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=y @@ -173,9 +238,12 @@ CONFIG_PCCARD_NONSTATIC=y # # Kernel Features # +# CONFIG_TICK_ONESHOT is not set # CONFIG_PREEMPT is not set CONFIG_HZ=100 -# CONFIG_AEABI is not set +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_ARCH_FLATMEM_HAS_HOLES=y # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y @@ -184,7 +252,14 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_LEDS is not set CONFIG_ALIGNMENT_TRAP=y # @@ -194,6 +269,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw" # CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set # # Floating point emulation @@ -202,8 +278,7 @@ CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev # # At least one emulation must be selected # -CONFIG_FPE_NWFPE=y -# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_NWFPE is not set # CONFIG_FPE_FASTFPE is not set # @@ -212,34 +287,33 @@ CONFIG_FPE_NWFPE=y CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_AOUT is not set # CONFIG_BINFMT_MISC is not set -# CONFIG_ARTHUR is not set # # Power management options # # CONFIG_PM is not set -# CONFIG_APM is not set - -# -# Networking -# +CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y # # Networking options # -# CONFIG_NETDEBUG is not set CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_FIB_HASH=y CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set @@ -250,28 +324,21 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# # CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# # CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set @@ -282,13 +349,8 @@ CONFIG_TCP_CONG_BIC=y # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set # @@ -296,9 +358,21 @@ CONFIG_TCP_CONG_BIC=y # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -307,36 +381,40 @@ CONFIG_TCP_CONG_BIC=y # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set - -# -# Connector - unified userspace <-> kernelspace linker -# +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers # CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -355,22 +433,25 @@ CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x8000000 +CONFIG_MTD_PHYSMAP_LEN=0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=4 # CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # @@ -388,29 +469,15 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# # CONFIG_MTD_NAND is not set - -# -# OneNAND Flash Device Drivers -# # CONFIG_MTD_ONENAND is not set # -# Parallel port support +# UBI - Unsorted block images # +# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -422,13 +489,17 @@ CONFIG_MTD_CFI_UTIL=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_INITRD=y +# CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set - -# -# ATA/ATAPI/MFM/RLL support -# +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # @@ -436,127 +507,85 @@ CONFIG_BLK_DEV_INITRD=y # # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set # CONFIG_MD is not set - -# -# Fusion MPT device support -# # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # -# CONFIG_IEEE1394 is not set # -# I2O device support +# Enable only one of the two stacks, unless you know what you are doing # +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set # CONFIG_I2O is not set - -# -# Network device support -# CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# ARCnet devices -# +# CONFIG_VETH is not set # CONFIG_ARCNET is not set - -# -# PHY device support -# # CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -CONFIG_ARM_KS8695_ETHER=y +CONFIG_MII=y +# CONFIG_AX88796 is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set - -# -# Tulip family network device support -# # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set # CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set - -# -# Ethernet (10000 Mbit) -# -# CONFIG_CHELSIO_T1 is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set - -# -# Token Ring devices -# +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set # -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# PCMCIA network device support -# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +# CONFIG_PCMCIA_RAYCS is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_LIBERTAS is not set +# CONFIG_HERMES is not set +# CONFIG_ATMEL is not set +# CONFIG_AIRO_CS is not set +# CONFIG_PCMCIA_WL3501 is not set +CONFIG_PRISM54=m +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_HOSTAP is not set # CONFIG_NET_PCMCIA is not set - -# -# Wan interfaces -# # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set # # Input device support # CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces @@ -566,7 +595,6 @@ CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set @@ -576,6 +604,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set @@ -589,9 +618,13 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set # # Serial drivers @@ -609,132 +642,113 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m # CONFIG_NVRAM is not set -# CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set - -# # PCMCIA character devices # # CONFIG_SYNCLINK_CS is not set # CONFIG_CARDMAN_4000 is not set # CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# # CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# +CONFIG_DEVPORT=y # CONFIG_I2C is not set - -# -# SPI support -# # CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# # CONFIG_W1 is not set - -# -# Hardware Monitoring support -# +# CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# +# CONFIG_WATCHDOG is not set # -# LED devices +# Sonics Silicon Backplane # -# CONFIG_NEW_LEDS is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set # -# LED drivers +# Multifunction device drivers # +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set # -# LED Triggers +# Multimedia devices # # -# Multimedia devices +# Multimedia core support # # CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set # -# Digital Video Broadcasting Devices +# Multimedia drivers # -# CONFIG_DVB is not set +# CONFIG_DAB is not set # # Graphics support # +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set # CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # -# Console display driver support +# Display device support # -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y +# CONFIG_DISPLAY_SUPPORT is not set # -# Sound +# Console display driver support # +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y # CONFIG_SOUND is not set - -# -# USB support -# +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set +CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# Enable Host or Gadget support to see Inventra options # # -# USB Gadget Support +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# # CONFIG_MMC is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set # -# Real Time Clock +# Voltage and Current regulators # -CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_UIO is not set # # File systems @@ -743,16 +757,16 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set @@ -774,10 +788,11 @@ CONFIG_DNOTIFY=y # Pseudo filesystems # CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y CONFIG_SYSFS=y CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set # @@ -790,67 +805,113 @@ CONFIG_RAMFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# -# CONFIG_NFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y # CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# # CONFIG_NLS is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set +# CONFIG_DLM is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_KERNEL=y -CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set # CONFIG_DEBUG_SLAB is not set -CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_FS is not set # CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set CONFIG_FRAME_POINTER=y -# CONFIG_UNWIND_INFO is not set -CONFIG_FORCED_INLINING=y +# CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +# CONFIG_FTRACE is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set CONFIG_DEBUG_USER=y # CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y # CONFIG_DEBUG_ICEDCC is not set @@ -859,21 +920,103 @@ CONFIG_DEBUG_LL=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set # -# Cryptographic options +# Ciphers # -# CONFIG_CRYPTO is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set # -# Hardware crypto devices +# Compression # +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set # # Library routines # +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mx31moboard_defconfig b/arch/arm/configs/mx31moboard_defconfig new file mode 100644 index 0000000..e90f86d --- /dev/null +++ b/arch/arm/configs/mx31moboard_defconfig @@ -0,0 +1,790 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.27-rc5 +# Fri Oct 24 11:41:22 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_ZONE_DMA=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_HAVE_IOREMAP_PROT is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_ARCH_TRACEHOOK is not set +# CONFIG_HAVE_DMA_ATTRS is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +# CONFIG_HAVE_CLK is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM7X00A is not set + +# +# Boot options +# + +# +# Power management +# + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX2 is not set +CONFIG_ARCH_MX3=y + +# +# MX3 Options +# +# CONFIG_MACH_MX31ADS is not set +# CONFIG_MACH_PCM037 is not set +# CONFIG_MACH_MX31LITE is not set +CONFIG_MACH_MX31MOBOARD=y +# CONFIG_MXC_IRQ_PRIOR is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_V6=y +# CONFIG_CPU_32v6K is not set +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=m +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +CONFIG_MTD_REDBOOT_PARTS_READONLY=y +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +# CONFIG_MTD_CFI_I2 is not set +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_XIP is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_SMC91X=y +# CONFIG_DM9000 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_SOUND is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_UIO is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_FRAME_POINTER=y +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +# CONFIG_FTRACE is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mx31pdk_defconfig b/arch/arm/configs/mx31pdk_defconfig new file mode 100644 index 0000000..95ffc0d --- /dev/null +++ b/arch/arm/configs/mx31pdk_defconfig @@ -0,0 +1,773 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28-rc2 +# Sun Oct 26 15:55:29 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_COMPAT_BRK is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set + +# +# Boot options +# + +# +# Power management +# + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX2 is not set +CONFIG_ARCH_MX3=y + +# +# MX3 Options +# +# CONFIG_MACH_MX31ADS is not set +# CONFIG_MACH_PCM037 is not set +# CONFIG_MACH_MX31LITE is not set +CONFIG_MACH_MX31_3DS=y +# CONFIG_MXC_IRQ_PRIOR is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_V6=y +# CONFIG_CPU_32v6K is not set +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_UNEVICTABLE_LRU is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_SMC911X is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_WM8400 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_UIO is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_HFSPLUS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_PCBC is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/neocore926_defconfig b/arch/arm/configs/neocore926_defconfig new file mode 100644 index 0000000..325f1e1 --- /dev/null +++ b/arch/arm/configs/neocore926_defconfig @@ -0,0 +1,1302 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.27-rc1 +# Tue Jul 29 10:46:54 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_COMPAT_BRK is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_HAVE_IOREMAP_PROT is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_ARCH_TRACEHOOK is not set +# CONFIG_HAVE_DMA_ATTRS is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +CONFIG_HAVE_CLK=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +CONFIG_ARCH_AT91=y +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM7X00A is not set + +# +# Boot options +# + +# +# Power management +# + +# +# Atmel AT91 System-on-Chip +# +# CONFIG_ARCH_AT91RM9200 is not set +# CONFIG_ARCH_AT91SAM9260 is not set +# CONFIG_ARCH_AT91SAM9261 is not set +CONFIG_ARCH_AT91SAM9263=y +# CONFIG_ARCH_AT91SAM9RL is not set +# CONFIG_ARCH_AT91SAM9G20 is not set +# CONFIG_ARCH_AT91CAP9 is not set +# CONFIG_ARCH_AT91X40 is not set +CONFIG_AT91_PMC_UNIT=y + +# +# AT91SAM9263 Board Type +# +# CONFIG_MACH_AT91SAM9263EK is not set +# CONFIG_MACH_USB_A9263 is not set +CONFIG_MACH_NEOCORE926=y + +# +# AT91 Board Options +# +CONFIG_MTD_AT91_DATAFLASH_CARD=y + +# +# AT91 Feature Selections +# +# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set +CONFIG_AT91_TIMER_HZ=100 +CONFIG_AT91_EARLY_DBGU=y +# CONFIG_AT91_EARLY_USART0 is not set +# CONFIG_AT91_EARLY_USART1 is not set +# CONFIG_AT91_EARLY_USART2 is not set +# CONFIG_AT91_EARLY_USART3 is not set +# CONFIG_AT91_EARLY_USART4 is not set +# CONFIG_AT91_EARLY_USART5 is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +CONFIG_MTD_BLOCK2MTD=y + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +CONFIG_MTD_NAND_ECC_SMC=y +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +CONFIG_MTD_NAND_ATMEL=y +CONFIG_MTD_NAND_ATMEL_ECC_HW=y +# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set +# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=y +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +CONFIG_ATMEL_PWM=y +CONFIG_ATMEL_TCLIB=y +CONFIG_ATMEL_TCB_CLKSRC=y +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0 +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ATMEL_SSC is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +# CONFIG_BLK_DEV_SD is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +CONFIG_SMSC_PHY=y +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +CONFIG_MACB=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_UCB1400 is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +# CONFIG_SERIAL_ATMEL_PDC is not set +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_AT24 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_ATMEL=y +# CONFIG_SPI_BITBANG is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_ATMEL=y +# CONFIG_FB_VIRTUAL is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_ATMEL_LCDC=y +# CONFIG_BACKLIGHT_ATMEL_PWM is not set +# CONFIG_BACKLIGHT_CORGI is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_SDIO_UART=y +# CONFIG_MMC_TEST is not set + +# +# MMC/SD Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_AT91=y +# CONFIG_MMC_SPI is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_FS_WBUF_VERIFY=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +# CONFIG_FTRACE is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/netx_defconfig b/arch/arm/configs/netx_defconfig index 0884f23..61d0fc5 100644 --- a/arch/arm/configs/netx_defconfig +++ b/arch/arm/configs/netx_defconfig @@ -728,9 +728,9 @@ CONFIG_RTC_CLASS=m # # RTC interfaces # -CONFIG_RTC_INTF_SYSFS=m -CONFIG_RTC_INTF_PROC=m -CONFIG_RTC_INTF_DEV=m +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y # # RTC drivers diff --git a/arch/arm/configs/omap3_pandora_defconfig b/arch/arm/configs/omap3_pandora_defconfig new file mode 100644 index 0000000..09543f4 --- /dev/null +++ b/arch/arm/configs/omap3_pandora_defconfig @@ -0,0 +1,1409 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28-rc7 +# Fri Dec 5 11:54:09 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +CONFIG_ARCH_OMAP=y +# CONFIG_ARCH_MSM is not set + +# +# TI OMAP Implementations +# +CONFIG_ARCH_OMAP_OTG=y +# CONFIG_ARCH_OMAP1 is not set +# CONFIG_ARCH_OMAP2 is not set +CONFIG_ARCH_OMAP3=y + +# +# OMAP Feature Selections +# +# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set +# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set +# CONFIG_OMAP_RESET_CLOCKS is not set +# CONFIG_OMAP_MUX is not set +CONFIG_OMAP_MCBSP=y +# CONFIG_OMAP_MPU_TIMER is not set +CONFIG_OMAP_32K_TIMER=y +CONFIG_OMAP_32K_TIMER_HZ=128 +CONFIG_OMAP_DM_TIMER=y +# CONFIG_OMAP_LL_DEBUG_UART1 is not set +# CONFIG_OMAP_LL_DEBUG_UART2 is not set +CONFIG_OMAP_LL_DEBUG_UART3=y +CONFIG_ARCH_OMAP34XX=y +CONFIG_ARCH_OMAP3430=y + +# +# OMAP Board Type +# +# CONFIG_MACH_OMAP3_BEAGLE is not set +# CONFIG_MACH_OMAP_LDP is not set +# CONFIG_MACH_OVERO is not set +CONFIG_MACH_OMAP3_PANDORA=y + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_IFAR=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=128 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE=" debug " +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=800 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +# CONFIG_MOUSE_PS2 is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_OMAP=y +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_AT24 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_ISP1301_OMAP is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +CONFIG_SPI_OMAP24XX=y + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +CONFIG_GPIO_TWL4030=y + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +CONFIG_TWL4030_CORE=y +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_COMPAT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BRIGHT is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DELL is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_SOC=y + +# +# OMAP 343x high speed USB support +# +CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_PERIPHERAL is not set +# CONFIG_USB_MUSB_OTG is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set +CONFIG_USB_MUSB_HDRC_HCD=y +# CONFIG_MUSB_PIO_ONLY is not set +CONFIG_USB_INVENTRA_DMA=y +# CONFIG_USB_TI_CPPI_DMA is not set +# CONFIG_USB_MUSB_DEBUG is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +CONFIG_USB_GADGET_OMAP=y +CONFIG_USB_OMAP=y +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +# CONFIG_USB_GADGET_DUALSPEED is not set +# CONFIG_USB_ZERO is not set +CONFIG_USB_ETH=y +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_OMAP is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +CONFIG_RTC_DRV_TWL4030=y +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/omap_ldp_defconfig b/arch/arm/configs/omap_ldp_defconfig index 948a212..b77d054 100644 --- a/arch/arm/configs/omap_ldp_defconfig +++ b/arch/arm/configs/omap_ldp_defconfig @@ -316,7 +316,82 @@ CONFIG_BINFMT_MISC=y # # CONFIG_PM is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_NET is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -332,6 +407,8 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y # CONFIG_MTD is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y @@ -390,6 +467,54 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_DH is not set # CONFIG_ATA is not set # CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +CONFIG_SMC911X=y +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set # # Input device support @@ -816,6 +941,27 @@ CONFIG_TMPFS=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types diff --git a/arch/arm/configs/picotux200_defconfig b/arch/arm/configs/picotux200_defconfig index 14826f0..59e4463 100644 --- a/arch/arm/configs/picotux200_defconfig +++ b/arch/arm/configs/picotux200_defconfig @@ -1069,9 +1069,9 @@ CONFIG_RTC_CLASS=m # # RTC interfaces # -CONFIG_RTC_INTF_SYSFS=m -CONFIG_RTC_INTF_PROC=m -CONFIG_RTC_INTF_DEV=m +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set # diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig index 0c09b23..cd29824 100644 --- a/arch/arm/configs/realview-smp_defconfig +++ b/arch/arm/configs/realview-smp_defconfig @@ -1,84 +1,111 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.19-rc3 -# Wed Oct 25 14:12:00 2006 +# Linux kernel version: 2.6.28-rc2 +# Mon Nov 10 14:41:47 2008 # CONFIG_ARM=y -# CONFIG_GENERIC_TIME is not set +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set -# CONFIG_CPUSETS is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set -CONFIG_INITRAMFS_SOURCE="" +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_BLK_DEV_INITRD is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y # CONFIG_EMBEDDED is not set CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y +CONFIG_ANON_INODES=y CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_SLAB=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_KMOD is not set +CONFIG_KMOD=y CONFIG_STOP_MACHINE=y - -# -# Block layer -# CONFIG_BLOCK=y +# CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -92,6 +119,8 @@ CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # System Type @@ -103,19 +132,26 @@ CONFIG_ARCH_REALVIEW=y # CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set # CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set @@ -123,13 +159,29 @@ CONFIG_ARCH_REALVIEW=y # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set + +# +# Boot options +# + +# +# Power management +# # # RealView platform type # CONFIG_MACH_REALVIEW_EB=y -CONFIG_REALVIEW_MPCORE=y +# CONFIG_REALVIEW_EB_A9MP is not set +CONFIG_REALVIEW_EB_ARM11MP=y +# CONFIG_REALVIEW_EB_ARM11MP_REVB is not set +CONFIG_MACH_REALVIEW_PB11MP=y +# CONFIG_MACH_REALVIEW_PB1176 is not set +# CONFIG_MACH_REALVIEW_PBA8 is not set +CONFIG_REALVIEW_HIGH_PHYS_OFFSET=y # # Processor Type @@ -138,12 +190,15 @@ CONFIG_CPU_32=y # CONFIG_CPU_ARM926T is not set CONFIG_CPU_V6=y CONFIG_CPU_32v6K=y +# CONFIG_CPU_V7 is not set CONFIG_CPU_32v6=y CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_NOIFAR=y CONFIG_CPU_CACHE_V6=y CONFIG_CPU_CACHE_VIPT=y CONFIG_CPU_COPY_V6=y CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y CONFIG_CPU_CP15=y CONFIG_CPU_CP15_MMU=y @@ -153,9 +208,10 @@ CONFIG_CPU_CP15_MMU=y CONFIG_ARM_THUMB=y # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_HAS_TLS_REG=y +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_L2X0=y CONFIG_ARM_GIC=y CONFIG_ICST307=y @@ -163,32 +219,44 @@ CONFIG_ICST307=y # Bus support # CONFIG_ARM_AMBA=y - -# -# PCCARD (PCMCIA/CardBus) support -# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set # CONFIG_PCCARD is not set # # Kernel Features # +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_SMP=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 CONFIG_NR_CPUS=4 CONFIG_HOTPLUG_CPU=y CONFIG_LOCAL_TIMERS=y # CONFIG_PREEMPT is not set CONFIG_HZ=100 -# CONFIG_AEABI is not set -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_ALIGNMENT_TRAP=y # @@ -198,6 +266,12 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="root=/dev/nfs nfsroot=10.1.69.3:/work/nfsroot ip=dhcp console=ttyAMA0 mem=128M" # CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set # # Floating point emulation @@ -206,8 +280,7 @@ CONFIG_CMDLINE="root=/dev/nfs nfsroot=10.1.69.3:/work/nfsroot ip=dhcp console=tt # # At least one emulation must be selected # -CONFIG_FPE_NWFPE=y -# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_NWFPE is not set # CONFIG_FPE_FASTFPE is not set CONFIG_VFP=y @@ -215,28 +288,29 @@ CONFIG_VFP=y # Userspace binary formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y # CONFIG_BINFMT_AOUT is not set # CONFIG_BINFMT_MISC is not set -# CONFIG_ARTHUR is not set # # Power management options # # CONFIG_PM is not set -# CONFIG_APM is not set - -# -# Networking -# +CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y # # Networking options # -# CONFIG_NETDEBUG is not set CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -255,36 +329,25 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# # CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# # CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -294,10 +357,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set # @@ -305,9 +364,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set -# CONFIG_IEEE80211 is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -316,38 +380,37 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# # CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_CONCAT=y CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers # CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -373,7 +436,6 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set # # Mapping drivers for chip access @@ -397,115 +459,73 @@ CONFIG_MTD_ARM_INTEGRATOR=y # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# # CONFIG_MTD_NAND is not set - -# -# OneNAND Flash Device Drivers -# # CONFIG_MTD_ONENAND is not set # -# Parallel port support +# UBI - Unsorted block images # +# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set -CONFIG_BLK_DEV_INITRD=y # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set - -# -# Multi-device support (RAID and LVM) -# +# CONFIG_ATA is not set # CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# PHY device support -# +# CONFIG_VETH is not set # CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y CONFIG_MII=y +# CONFIG_AX88796 is not set CONFIG_SMC91X=y # CONFIG_DM9000 is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# +CONFIG_SMC911X=y +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set # @@ -513,6 +533,7 @@ CONFIG_SMC91X=y # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces @@ -522,7 +543,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set @@ -538,9 +558,16 @@ CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_STOWAWAY is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set @@ -558,9 +585,11 @@ CONFIG_SERIO_LIBPS2=y # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # @@ -579,97 +608,91 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=16 - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set # CONFIG_NVRAM is not set -# CONFIG_DTLK is not set # CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# # CONFIG_TCG_TPM is not set - -# -# I2C support -# # CONFIG_I2C is not set - -# -# SPI support -# # CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# # CONFIG_W1 is not set - -# -# Hardware Monitoring support -# +# CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set - -# -# Misc devices -# -# CONFIG_SGI_IOC4 is not set -# CONFIG_TIFM_CORE is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set # -# LED devices +# Sonics Silicon Backplane # -# CONFIG_NEW_LEDS is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set # -# LED drivers +# Multifunction device drivers # +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_WM8400 is not set # -# LED Triggers +# Multimedia devices # # -# Multimedia devices +# Multimedia core support # # CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set # -# Digital Video Broadcasting Devices +# Multimedia drivers # -# CONFIG_DVB is not set +# CONFIG_DAB is not set # # Graphics support # -# CONFIG_FIRMWARE_EDID is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set # CONFIG_FB_BACKLIGHT is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# CONFIG_FB_ARMCLCD=y # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set # # Console display driver support @@ -677,28 +700,17 @@ CONFIG_FB_ARMCLCD=y # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y - -# -# Logo configuration -# CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# CONFIG_SOUND=y - -# -# Advanced Linux Sound Architecture -# +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y @@ -712,100 +724,65 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set - -# -# Generic devices -# -CONFIG_SND_AC97_CODEC=m -CONFIG_SND_AC97_BUS=m -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set - -# -# ALSA ARM devices -# -CONFIG_SND_ARMAACI=m - -# -# Open Sound System -# +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +# CONFIG_SND_DRIVERS is not set +CONFIG_SND_ARM=y +CONFIG_SND_ARMAACI=y +# CONFIG_SND_SOC is not set # CONFIG_SOUND_PRIME is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -# CONFIG_USB is not set - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -# - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# +CONFIG_AC97_BUS=y +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set -CONFIG_MMC_BLOCK=y -CONFIG_MMC_ARMMMCI=y -# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_UNSAFE_RESUME is not set # -# Real Time Clock +# MMC/SD/SDIO Card Drivers # -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set # -# RTC interfaces +# MMC/SD/SDIO Host Controller Drivers # -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_MMC_ARMMMCI=y +# CONFIG_MMC_SDHCI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set # -# RTC drivers +# Voltage and Current regulators # -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_M48T86 is not set -CONFIG_RTC_DRV_PL031=y -# CONFIG_RTC_DRV_TEST is not set -# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_UIO is not set # # File systems # -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y -# CONFIG_INOTIFY_USER is not set +CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set @@ -831,11 +808,11 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_PROC_FS=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set # @@ -848,29 +825,28 @@ CONFIG_RAMFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set # CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -878,17 +854,12 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y @@ -929,64 +900,177 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set +# CONFIG_DLM is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set -# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y # CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_KERNEL=y -CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set # CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_RWSEMS=y +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_FS is not set # CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set CONFIG_FRAME_POINTER=y -# CONFIG_UNWIND_INFO is not set -CONFIG_FORCED_INLINING=y -# CONFIG_HEADERS_CHECK is not set +# CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +# CONFIG_FTRACE is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y -CONFIG_DEBUG_LL=y -# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set # # Security options # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set # -# Cryptographic options +# Random Number Generation # -# CONFIG_CRYPTO is not set +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set # # Library routines # +CONFIG_BITREVERSE=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig index 907e543..7e253f5 100644 --- a/arch/arm/configs/realview_defconfig +++ b/arch/arm/configs/realview_defconfig @@ -1,105 +1,204 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.14-rc2 -# Thu Sep 29 14:50:10 2005 +# Linux kernel version: 2.6.28-rc2 +# Mon Nov 10 14:39:48 2008 # CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_MMU=y -CONFIG_UID16=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # -# CONFIG_EXPERIMENTAL is not set -CONFIG_CLEAN_COMPILE=y +CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y +# CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set -CONFIG_HOTPLUG=y -CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set -CONFIG_INITRAMFS_SOURCE="" +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y # CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y +CONFIG_ANON_INODES=y CONFIG_EPOLL=y -CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 - -# -# Loadable module support -# CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y -CONFIG_OBSOLETE_MODPARM=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_KMOD is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +CONFIG_IOSCHED_DEADLINE=y +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +CONFIG_DEFAULT_DEADLINE=y +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # System Type # +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_REALVIEW=y +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP3XX is not set -# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set # CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_VERSATILE is not set -CONFIG_ARCH_REALVIEW=y -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_MSM is not set + +# +# Boot options +# + +# +# Power management +# # # RealView platform type # CONFIG_MACH_REALVIEW_EB=y +# CONFIG_REALVIEW_EB_A9MP is not set +CONFIG_REALVIEW_EB_ARM11MP=y +# CONFIG_REALVIEW_EB_ARM11MP_REVB is not set +CONFIG_MACH_REALVIEW_PB11MP=y +CONFIG_MACH_REALVIEW_PB1176=y +# CONFIG_MACH_REALVIEW_PBA8 is not set # # Processor Type # CONFIG_CPU_32=y -CONFIG_CPU_ARM926T=y -# CONFIG_CPU_V6 is not set -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5TJ=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_TLB_V4WBI=y +# CONFIG_CPU_ARM926T is not set +CONFIG_CPU_V6=y +# CONFIG_CPU_32v6K is not set +# CONFIG_CPU_V7 is not set +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y # # Processor Features @@ -107,8 +206,9 @@ CONFIG_CPU_TLB_V4WBI=y CONFIG_ARM_THUMB=y # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_L2X0=y CONFIG_ARM_GIC=y CONFIG_ICST307=y @@ -116,20 +216,41 @@ CONFIG_ICST307=y # Bus support # CONFIG_ARM_AMBA=y -CONFIG_ISA_DMA_API=y - -# -# PCCARD (PCMCIA/CardBus) support -# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set # CONFIG_PCCARD is not set # # Kernel Features # -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_SMP is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_ALIGNMENT_TRAP=y # @@ -139,6 +260,12 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="root=/dev/nfs nfsroot=10.1.69.3:/work/nfsroot ip=dhcp console=ttyAMA0 mem=128M" # CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set # # Floating point emulation @@ -147,26 +274,24 @@ CONFIG_CMDLINE="root=/dev/nfs nfsroot=10.1.69.3:/work/nfsroot ip=dhcp console=tt # # At least one emulation must be selected # -CONFIG_FPE_NWFPE=y -# CONFIG_FPE_NWFPE_XP is not set -# CONFIG_VFP is not set +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y # # Userspace binary formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y # CONFIG_BINFMT_AOUT is not set # CONFIG_BINFMT_MISC is not set -# CONFIG_ARTHUR is not set # # Power management options # # CONFIG_PM is not set - -# -# Networking -# +CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y # @@ -175,6 +300,11 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -186,34 +316,56 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set # CONFIG_SYN_COOKIES is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set # CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set -# CONFIG_IEEE80211 is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -222,30 +374,37 @@ CONFIG_TCP_CONG_BIC=y # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set - -# -# Memory Technology Devices (MTD) -# +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_CONCAT=y CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers # CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -266,7 +425,6 @@ CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I8 is not set CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_AMDSTD_RETRY=0 # CONFIG_MTD_CFI_STAA is not set CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set @@ -279,7 +437,6 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set CONFIG_MTD_ARM_INTEGRATOR=y -# CONFIG_MTD_EDB7312 is not set # CONFIG_MTD_PLATRAM is not set # @@ -288,7 +445,7 @@ CONFIG_MTD_ARM_INTEGRATOR=y # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_BLOCK2MTD is not set # # Disk-On-Chip Device Drivers @@ -296,121 +453,81 @@ CONFIG_MTD_ARM_INTEGRATOR=y # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# # CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set # -# Parallel port support +# UBI - Unsorted block images # +# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set -CONFIG_BLK_DEV_RAM_COUNT=16 # CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -CONFIG_IOSCHED_DEADLINE=y -# CONFIG_IOSCHED_CFQ is not set # CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set # CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# PHY device support -# +# CONFIG_VETH is not set # CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y CONFIG_MII=y +# CONFIG_AX88796 is not set CONFIG_SMC91X=y # CONFIG_DM9000 is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# +CONFIG_SMC911X=y +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set # # Input device support # CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces @@ -420,7 +537,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set @@ -433,11 +549,19 @@ CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_XTKBD is not set # CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set @@ -455,8 +579,11 @@ CONFIG_SERIO_LIBPS2=y # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # @@ -475,73 +602,91 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=16 - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set +# CONFIG_HW_RANDOM is not set # CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_DTLK is not set # CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# - -# -# I2C support -# +# CONFIG_TCG_TPM is not set # CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set # -# Hardware Monitoring support +# Sonics Silicon Backplane # -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set # -# Misc devices +# Multifunction device drivers # +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_WM8400 is not set # -# Multimedia Capabilities Port drivers +# Multimedia devices # # -# Multimedia devices +# Multimedia core support # # CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set # -# Digital Video Broadcasting Devices +# Multimedia drivers # -# CONFIG_DVB is not set +# CONFIG_DAB is not set # # Graphics support # +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_SOFT_CURSOR=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# CONFIG_FB_ARMCLCD=y # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set # # Console display driver support @@ -549,27 +694,17 @@ CONFIG_FB_ARMCLCD=y # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y - -# -# Logo configuration -# CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# CONFIG_SOUND=y - -# -# Advanced Linux Sound Architecture -# +CONFIG_SOUND_OSS_CORE=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y @@ -577,59 +712,71 @@ CONFIG_SND_PCM=y CONFIG_SND_OSSEMUL=y CONFIG_SND_MIXER_OSS=y CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set - -# -# Generic devices -# -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set - -# -# ALSA ARM devices -# -# CONFIG_SND_ARMAACI is not set - -# -# Open Sound System -# +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +# CONFIG_SND_DRIVERS is not set +CONFIG_SND_ARM=y +CONFIG_SND_ARMAACI=y +# CONFIG_SND_SOC is not set # CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set # -# USB support +# MMC/SD/SDIO Card Drivers # -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set # -# USB Gadget Support +# MMC/SD/SDIO Host Controller Drivers # -# CONFIG_USB_GADGET is not set +CONFIG_MMC_ARMMMCI=y +# CONFIG_MMC_SDHCI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set # -# MMC/SD Card support +# Voltage and Current regulators # -# CONFIG_MMC is not set +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_UIO is not set # # File systems # # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set @@ -654,51 +801,59 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # Pseudo filesystems # CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_RELAYFS_FS is not set +# CONFIG_CONFIGFS_FS is not set # # Miscellaneous filesystems # +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set -# CONFIG_JFFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set # CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set -# CONFIG_NFSD is not set +# CONFIG_NFS_V4 is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y @@ -739,26 +894,71 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set -CONFIG_DEBUG_KERNEL=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y -CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set # CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +# CONFIG_FTRACE is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_DEBUG_LL is not set # @@ -766,21 +966,106 @@ CONFIG_DEBUG_ERRORS=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set # -# Cryptographic options +# Compression # -# CONFIG_CRYPTO is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set # -# Hardware crypto devices +# Random Number Generation # +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set # # Library routines # +CONFIG_BITREVERSE=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig new file mode 100644 index 0000000..cf3c1b5 --- /dev/null +++ b/arch/arm/configs/s3c6400_defconfig @@ -0,0 +1,845 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28-rc3 +# Mon Nov 3 10:10:30 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +CONFIG_NO_IOPORT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +CONFIG_LBD=y +# CONFIG_BLK_DEV_IO_TRACE is not set +CONFIG_LSF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +CONFIG_ARCH_S3C64XX=y +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +CONFIG_PLAT_S3C64XX=y +CONFIG_CPU_S3C6400_INIT=y +CONFIG_CPU_S3C6400_CLOCK=y +CONFIG_S3C64XX_SETUP_I2C0=y +CONFIG_S3C64XX_SETUP_I2C1=y +CONFIG_PLAT_S3C=y + +# +# Boot options +# +CONFIG_S3C_BOOT_ERROR_RESET=y + +# +# Power management +# +CONFIG_S3C_LOWLEVEL_UART_PORT=0 +CONFIG_S3C_GPIO_SPACE=0 +CONFIG_S3C_GPIO_TRACK=y +CONFIG_S3C_GPIO_PULL_UPDOWN=y +CONFIG_S3C_GPIO_CFG_S3C24XX=y +CONFIG_S3C_GPIO_CFG_S3C64XX=y +CONFIG_S3C_DEV_HSMMC=y +CONFIG_S3C_DEV_HSMMC1=y +CONFIG_S3C_DEV_I2C1=y +CONFIG_CPU_S3C6410=y +CONFIG_S3C6410_SETUP_SDHCI=y +CONFIG_MACH_SMDK6410=y +CONFIG_SMDK6410_SD_CH0=y +# CONFIG_SMDK6410_SD_CH1 is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_V6=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_ARM_VIC=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/bin/bash initrd=0x51000000,4M" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_CONSOLE is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_UARTS=4 +# CONFIG_SERIAL_SAMSUNG_DEBUG is not set +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_S3C6400=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_S3C2410=y +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +CONFIG_AT24=y +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +# CONFIG_HID_COMPAT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set + +# +# Enable Host or Gadget support to see Inventra options +# + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y +CONFIG_MMC_DEBUG=y +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_SDIO_UART=y +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set +CONFIG_DEBUG_S3C_PORT=y +CONFIG_DEBUG_S3C_UART=0 + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/w90p910_defconfig b/arch/arm/configs/w90p910_defconfig new file mode 100644 index 0000000..56bda7c --- /dev/null +++ b/arch/arm/configs/w90p910_defconfig @@ -0,0 +1,626 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.27-rc8-git8 +# Sat Nov 15 10:05:00 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +CONFIG_USER_NS=y +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_HAVE_IOREMAP_PROT is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_ARCH_TRACEHOOK is not set +# CONFIG_HAVE_DMA_ATTRS is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +# CONFIG_HAVE_CLK is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBD=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_LSF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM7X00A is not set +CONFIG_ARCH_W90X900=y + +# +# Boot options +# + +# +# Power management +# +CONFIG_CPU_W90P910=y + +# +# W90P910 Machines +# +CONFIG_MACH_W90P910EVB=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 initrd=0xa00000,4000000 mem=64M" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_W90X900=y +# CONFIG_SERIAL_W90X900_PORT1 is not set +# CONFIG_SERIAL_W90X900_PORT2 is not set +# CONFIG_SERIAL_W90X900_PORT3 is not set +# CONFIG_SERIAL_W90X900_PORT4 is not set +CONFIG_SERIAL_W90X900_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set + +# +# Voltage and Current regulators +# +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_UIO is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +# CONFIG_FTRACE is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index de6c59f..6cbd8fd 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -10,11 +10,11 @@ #ifndef _ASMARM_CACHEFLUSH_H #define _ASMARM_CACHEFLUSH_H -#include <linux/sched.h> #include <linux/mm.h> #include <asm/glue.h> #include <asm/shmparam.h> +#include <asm/cachetype.h> #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) @@ -296,16 +296,6 @@ static inline void outer_flush_range(unsigned long start, unsigned long end) #endif /* - * flush_cache_vmap() is used when creating mappings (eg, via vmap, - * vmalloc, ioremap etc) in kernel space for pages. Since the - * direct-mappings of these pages may contain cached data, we need - * to do a full cache flush to ensure that writebacks don't corrupt - * data placed into these pages via the new mappings. - */ -#define flush_cache_vmap(start, end) flush_cache_all() -#define flush_cache_vunmap(start, end) flush_cache_all() - -/* * Copy user data from/to a page which is mapped into a different * processes address space. Really, we want to allow our "user * space" model to handle this. @@ -444,4 +434,29 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, dmac_inv_range(start, start + size); } +/* + * flush_cache_vmap() is used when creating mappings (eg, via vmap, + * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT + * caches, since the direct-mappings of these pages may contain cached + * data, we need to do a full cache flush to ensure that writebacks + * don't corrupt data placed into these pages via the new mappings. + */ +static inline void flush_cache_vmap(unsigned long start, unsigned long end) +{ + if (!cache_is_vipt_nonaliasing()) + flush_cache_all(); + else + /* + * set_pte_at() called from vmap_pte_range() does not + * have a DSB after cleaning the cache line. + */ + dsb(); +} + +static inline void flush_cache_vunmap(unsigned long start, unsigned long end) +{ + if (!cache_is_vipt_nonaliasing()) + flush_cache_all(); +} + #endif diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h new file mode 100644 index 0000000..b6ec7c6 --- /dev/null +++ b/arch/arm/include/asm/clkdev.h @@ -0,0 +1,30 @@ +/* + * arch/arm/include/asm/clkdev.h + * + * Copyright (C) 2008 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Helper for the clk API to assist looking up a struct clk. + */ +#ifndef __ASM_CLKDEV_H +#define __ASM_CLKDEV_H + +struct clk; + +struct clk_lookup { + struct list_head node; + const char *dev_id; + const char *con_id; + struct clk *clk; +}; + +struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id, + const char *dev_fmt, ...); + +void clkdev_add(struct clk_lookup *cl); +void clkdev_drop(struct clk_lookup *cl); + +#endif diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 4ed149c..22cb14e 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -69,7 +69,9 @@ extern void dma_cache_maint(const void *kaddr, size_t size, int rw); */ static inline int dma_supported(struct device *dev, u64 mask) { - return dev->dma_mask && *dev->dma_mask != 0; + if (mask < ISA_DMA_THRESHOLD) + return 0; + return 1; } static inline int dma_set_mask(struct device *dev, u64 dma_mask) diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h index 75154b1..df5638f 100644 --- a/arch/arm/include/asm/dma.h +++ b/arch/arm/include/asm/dma.h @@ -1,12 +1,7 @@ #ifndef __ASM_ARM_DMA_H #define __ASM_ARM_DMA_H -typedef unsigned int dmach_t; - -#include <linux/spinlock.h> -#include <asm/system.h> -#include <asm/scatterlist.h> -#include <mach/dma.h> +#include <asm/memory.h> /* * This is the maximum virtual address which can be DMA'd from. @@ -15,6 +10,19 @@ typedef unsigned int dmach_t; #define MAX_DMA_ADDRESS 0xffffffff #endif +#ifdef CONFIG_ISA_DMA_API +/* + * This is used to support drivers written for the x86 ISA DMA API. + * It should not be re-used except for that purpose. + */ +#include <linux/spinlock.h> +#include <asm/system.h> +#include <asm/scatterlist.h> + +typedef unsigned int dmach_t; + +#include <mach/isa-dma.h> + /* * DMA modes */ @@ -140,4 +148,6 @@ extern int isa_dma_bridge_buggy; #define isa_dma_bridge_buggy (0) #endif -#endif /* _ARM_DMA_H */ +#endif /* CONFIG_ISA_DMA_API */ + +#endif /* __ASM_ARM_DMA_H */ diff --git a/arch/arm/include/asm/hardware/iomd.h b/arch/arm/include/asm/hardware/iomd.h index 9c5afbd..f9ee69e 100644 --- a/arch/arm/include/asm/hardware/iomd.h +++ b/arch/arm/include/asm/hardware/iomd.h @@ -32,19 +32,11 @@ #define IOMD_KARTRX (0x004) #define IOMD_KCTRL (0x008) -#ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_IOLINES (0x00C) -#endif - #define IOMD_IRQSTATA (0x010) #define IOMD_IRQREQA (0x014) #define IOMD_IRQCLRA (0x014) #define IOMD_IRQMASKA (0x018) -#ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_SUSMODE (0x01C) -#endif - #define IOMD_IRQSTATB (0x020) #define IOMD_IRQREQB (0x024) #define IOMD_IRQMASKB (0x028) @@ -53,10 +45,6 @@ #define IOMD_FIQREQ (0x034) #define IOMD_FIQMASK (0x038) -#ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_CLKCTL (0x03C) -#endif - #define IOMD_T0CNTL (0x040) #define IOMD_T0LTCHL (0x040) #define IOMD_T0CNTH (0x044) @@ -71,18 +59,6 @@ #define IOMD_T1GO (0x058) #define IOMD_T1LATCH (0x05c) -#ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_IRQSTATC (0x060) -#define IOMD_IRQREQC (0x064) -#define IOMD_IRQMASKC (0x068) - -#define IOMD_VIDMUX (0x06c) - -#define IOMD_IRQSTATD (0x070) -#define IOMD_IRQREQD (0x074) -#define IOMD_IRQMASKD (0x078) -#endif - #define IOMD_ROMCR0 (0x080) #define IOMD_ROMCR1 (0x084) #ifdef CONFIG_ARCH_RPC @@ -100,11 +76,6 @@ #define IOMD_MOUSEY (0x0A4) #endif -#ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_MSEDAT (0x0A8) -#define IOMD_MSECTL (0x0Ac) -#endif - #ifdef CONFIG_ARCH_RPC #define IOMD_DMATCR (0x0C0) #endif @@ -113,18 +84,6 @@ #ifdef CONFIG_ARCH_RPC #define IOMD_DMAEXT (0x0CC) #endif -#ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_ASTCR (0x0CC) -#define IOMD_DRAMCR (0x0D0) -#define IOMD_SELFREF (0x0D4) -#define IOMD_ATODICR (0x0E0) -#define IOMD_ATODSR (0x0E4) -#define IOMD_ATODCC (0x0E8) -#define IOMD_ATODCNT1 (0x0EC) -#define IOMD_ATODCNT2 (0x0F0) -#define IOMD_ATODCNT3 (0x0F4) -#define IOMD_ATODCNT4 (0x0F8) -#endif #ifdef CONFIG_ARCH_RPC #define DMA_EXT_IO0 1 diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h index 263f2c3..f87328d 100644 --- a/arch/arm/include/asm/hardware/vic.h +++ b/arch/arm/include/asm/hardware/vic.h @@ -29,15 +29,17 @@ #define VIC_INT_SOFT 0x18 #define VIC_INT_SOFT_CLEAR 0x1c #define VIC_PROTECT 0x20 -#define VIC_VECT_ADDR 0x30 -#define VIC_DEF_VECT_ADDR 0x34 +#define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */ +#define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */ -#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */ -#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */ +#define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */ +#define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */ #define VIC_ITCR 0x300 /* VIC test control register */ #define VIC_VECT_CNTL_ENABLE (1 << 5) +#define VIC_PL192_VECT_ADDR 0xF00 + #ifndef __ASSEMBLY__ void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources); #endif diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h index 81f4c89..bda489f 100644 --- a/arch/arm/include/asm/hwcap.h +++ b/arch/arm/include/asm/hwcap.h @@ -16,6 +16,7 @@ #define HWCAP_IWMMXT 512 #define HWCAP_CRUNCH 1024 #define HWCAP_THUMBEE 2048 +#define HWCAP_NEON 4096 #if defined(__KERNEL__) && !defined(__ASSEMBLY__) /* diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index a809445..d2a59cf 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -80,6 +80,14 @@ extern void __iounmap(volatile void __iomem *addr); extern void __readwrite_bug(const char *fn); /* + * A typesafe __io() helper + */ +static inline void __iomem *__typesafe_io(unsigned long addr) +{ + return (void __iomem *)addr; +} + +/* * Now, pick up the machine-defined IO definitions */ #include <mach/io.h> diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index a0009aa..328f14a 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h @@ -7,10 +7,6 @@ #define irq_canonicalize(i) (i) #endif -#ifndef NR_IRQS -#define NR_IRQS 128 -#endif - /* * Use this value to indicate lack of interrupt * capability diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 7776430..0202a7c 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -112,10 +112,8 @@ * private definitions which should NOT be used outside memory.h * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. */ -#ifndef __virt_to_phys #define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) #define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) -#endif /* * Convert a physical address to a Page Frame Number and back @@ -180,6 +178,11 @@ static inline void *phys_to_virt(unsigned long x) * memory. Use of these is *deprecated* (and that doesn't mean * use the __ prefixed forms instead.) See dma-mapping.h. */ +#ifndef __virt_to_bus +#define __virt_to_bus __virt_to_phys +#define __bus_to_virt __phys_to_virt +#endif + static inline __deprecated unsigned long virt_to_bus(void *x) { return __virt_to_bus((unsigned long)x); diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h index 0559f37..263fed0 100644 --- a/arch/arm/include/asm/mmu_context.h +++ b/arch/arm/include/asm/mmu_context.h @@ -14,6 +14,7 @@ #define __ASM_ARM_MMU_CONTEXT_H #include <linux/compiler.h> +#include <linux/sched.h> #include <asm/cacheflush.h> #include <asm/cachetype.h> #include <asm/proc-fns.h> diff --git a/arch/arm/include/asm/mtd-xip.h b/arch/arm/include/asm/mtd-xip.h index d8fbe2d..d79d66d 100644 --- a/arch/arm/include/asm/mtd-xip.h +++ b/arch/arm/include/asm/mtd-xip.h @@ -15,7 +15,6 @@ #ifndef __ARM_MTD_XIP_H__ #define __ARM_MTD_XIP_H__ -#include <mach/hardware.h> #include <mach/mtd-xip.h> /* fill instruction prefetch */ diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index bed1c0a..f341c9d 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h @@ -108,32 +108,38 @@ #error Unknown user operations model #endif +struct page; + struct cpu_user_fns { - void (*cpu_clear_user_page)(void *p, unsigned long user); - void (*cpu_copy_user_page)(void *to, const void *from, - unsigned long user); + void (*cpu_clear_user_highpage)(struct page *page, unsigned long vaddr); + void (*cpu_copy_user_highpage)(struct page *to, struct page *from, + unsigned long vaddr); }; #ifdef MULTI_USER extern struct cpu_user_fns cpu_user; -#define __cpu_clear_user_page cpu_user.cpu_clear_user_page -#define __cpu_copy_user_page cpu_user.cpu_copy_user_page +#define __cpu_clear_user_highpage cpu_user.cpu_clear_user_highpage +#define __cpu_copy_user_highpage cpu_user.cpu_copy_user_highpage #else -#define __cpu_clear_user_page __glue(_USER,_clear_user_page) -#define __cpu_copy_user_page __glue(_USER,_copy_user_page) +#define __cpu_clear_user_highpage __glue(_USER,_clear_user_highpage) +#define __cpu_copy_user_highpage __glue(_USER,_copy_user_highpage) -extern void __cpu_clear_user_page(void *p, unsigned long user); -extern void __cpu_copy_user_page(void *to, const void *from, - unsigned long user); +extern void __cpu_clear_user_highpage(struct page *page, unsigned long vaddr); +extern void __cpu_copy_user_highpage(struct page *to, struct page *from, + unsigned long vaddr); #endif -#define clear_user_page(addr,vaddr,pg) __cpu_clear_user_page(addr, vaddr) -#define copy_user_page(to,from,vaddr,pg) __cpu_copy_user_page(to, from, vaddr) +#define clear_user_highpage(page,vaddr) \ + __cpu_clear_user_highpage(page, vaddr) + +#define __HAVE_ARCH_COPY_USER_HIGHPAGE +#define copy_user_highpage(to,from,vaddr,vma) \ + __cpu_copy_user_highpage(to, from, vaddr) -#define clear_page(page) memzero((void *)(page), PAGE_SIZE) +#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) extern void copy_page(void *to, const void *from); #undef STRICT_MM_TYPECHECKS diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 6ff3379..1845892 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -64,7 +64,7 @@ struct thread_struct { ({ \ unsigned long *stack = (unsigned long *)sp; \ set_fs(USER_DS); \ - memzero(regs->uregs, sizeof(regs->uregs)); \ + memset(regs->uregs, 0, sizeof(regs->uregs)); \ if (current->personality & ADDR_LIMIT_32BIT) \ regs->ARM_cpsr = USR_MODE; \ else \ diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index a65413b..f2cd18a 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -209,9 +209,11 @@ struct meminfo { struct membank bank[NR_BANKS]; }; +extern struct meminfo meminfo; + #define for_each_nodebank(iter,mi,no) \ - for (iter = 0; iter < mi->nr_banks; iter++) \ - if (mi->bank[iter].node == no) + for (iter = 0; iter < (mi)->nr_banks; iter++) \ + if ((mi)->bank[iter].node == no) #define bank_pfn_start(bank) __phys_to_pfn((bank)->start) #define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size) diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 727b5c0..fad70da 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -114,7 +114,7 @@ extern void local_timer_interrupt(void); /* * Stop a local timer interrupt. */ -extern void local_timer_stop(unsigned int cpu); +extern void local_timer_stop(void); /* * Platform provides this to acknowledge a local timer IRQ @@ -123,7 +123,7 @@ extern int local_timer_ack(void); #else -static inline void local_timer_stop(unsigned int cpu) +static inline void local_timer_stop(void) { } @@ -132,7 +132,7 @@ static inline void local_timer_stop(unsigned int cpu) /* * Setup a local timer interrupt for a CPU. */ -extern void local_timer_setup(unsigned int cpu); +extern void local_timer_setup(void); /* * show local interrupt info diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h index e50c4a3..cf4f3aa 100644 --- a/arch/arm/include/asm/string.h +++ b/arch/arm/include/asm/string.h @@ -21,7 +21,6 @@ extern void * memmove(void *, const void *, __kernel_size_t); #define __HAVE_ARCH_MEMCHR extern void * memchr(const void *, int, __kernel_size_t); -#define __HAVE_ARCH_MEMZERO #define __HAVE_ARCH_MEMSET extern void * memset(void *, int, __kernel_size_t); @@ -39,12 +38,4 @@ extern void __memzero(void *ptr, __kernel_size_t n); (__p); \ }) -#define memzero(p,n) \ - ({ \ - void *__p = (p); size_t __n = n; \ - if ((__n) != 0) \ - __memzero((__p),(__n)); \ - (__p); \ - }) - #endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 568020b..811be55 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -3,8 +3,6 @@ #ifdef __KERNEL__ -#include <asm/memory.h> - #define CPU_ARCH_UNKNOWN 0 #define CPU_ARCH_ARMv3 1 #define CPU_ARCH_ARMv4 2 diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index e98ec60..7897464 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -11,7 +11,8 @@ /* * User space memory access functions */ -#include <linux/sched.h> +#include <linux/string.h> +#include <linux/thread_info.h> #include <asm/errno.h> #include <asm/memory.h> #include <asm/domain.h> @@ -400,7 +401,7 @@ static inline unsigned long __must_check copy_from_user(void *to, const void __u if (access_ok(VERIFY_READ, from, n)) n = __copy_from_user(to, from, n); else /* security hole - plug it */ - memzero(to, n); + memset(to, 0, n); return n; } diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index 23af3c9..531e186 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c @@ -8,6 +8,7 @@ * published by the Free Software Foundation. */ #include <linux/module.h> +#include <linux/sched.h> #include <linux/string.h> #include <linux/cryptohash.h> #include <linux/delay.h> diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c index 6c90479..c638427 100644 --- a/arch/arm/kernel/ftrace.c +++ b/arch/arm/kernel/ftrace.c @@ -95,7 +95,7 @@ int ftrace_update_ftrace_func(ftrace_func_t func) return ret; } -/* run from kstop_machine */ +/* run from ftrace_init with irqs disabled */ int __init ftrace_dyn_arch_init(void *data) { ftrace_mcount_set(data); diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index bde52df..991952c 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -18,7 +18,7 @@ __switch_data: .long __mmap_switched .long __data_loc @ r4 - .long __data_start @ r5 + .long _data @ r5 .long __bss_start @ r6 .long _end @ r7 .long processor_id @ r4 diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index b8d965d..dab48f2 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -21,6 +21,7 @@ #include <linux/string.h> #include <asm/pgtable.h> +#include <asm/sections.h> #ifdef CONFIG_XIP_KERNEL /* @@ -29,9 +30,8 @@ * MODULES_VADDR is redefined here and not in asm/memory.h to avoid * recompiling the whole kernel when CONFIG_XIP_KERNEL is turned on/off. */ -extern void _etext; #undef MODULES_VADDR -#define MODULES_VADDR (((unsigned long)&_etext + ~PGDIR_MASK) & PGDIR_MASK) +#define MODULES_VADDR (((unsigned long)_etext + ~PGDIR_MASK) & PGDIR_MASK) #endif #ifdef CONFIG_MMU diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 1f1eecc..7049815 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -29,6 +29,7 @@ #include <asm/cputype.h> #include <asm/elf.h> #include <asm/procinfo.h> +#include <asm/sections.h> #include <asm/setup.h> #include <asm/mach-types.h> #include <asm/cacheflush.h> @@ -59,9 +60,8 @@ static int __init fpe_setup(char *line) __setup("fpe=", fpe_setup); #endif -extern void paging_init(struct meminfo *, struct machine_desc *desc); +extern void paging_init(struct machine_desc *desc); extern void reboot_setup(char *str); -extern void _text, _etext, __data_start, _edata, _end; unsigned int processor_id; EXPORT_SYMBOL(processor_id); @@ -112,7 +112,6 @@ static struct stack stacks[NR_CPUS]; char elf_platform[ELF_PLATFORM_SIZE]; EXPORT_SYMBOL(elf_platform); -static struct meminfo meminfo __initdata = { 0, }; static const char *cpu_name; static const char *machine_name; static char __initdata command_line[COMMAND_LINE_SIZE]; @@ -367,21 +366,34 @@ static struct machine_desc * __init setup_machine(unsigned int nr) return list; } -static void __init arm_add_memory(unsigned long start, unsigned long size) +static int __init arm_add_memory(unsigned long start, unsigned long size) { - struct membank *bank; + struct membank *bank = &meminfo.bank[meminfo.nr_banks]; + + if (meminfo.nr_banks >= NR_BANKS) { + printk(KERN_CRIT "NR_BANKS too low, " + "ignoring memory at %#lx\n", start); + return -EINVAL; + } /* * Ensure that start/size are aligned to a page boundary. * Size is appropriately rounded down, start is rounded up. */ size -= start & ~PAGE_MASK; - - bank = &meminfo.bank[meminfo.nr_banks++]; - bank->start = PAGE_ALIGN(start); bank->size = size & PAGE_MASK; bank->node = PHYS_TO_NID(start); + + /* + * Check whether this memory region has non-zero size or + * invalid node number. + */ + if (bank->size == 0 || bank->node >= MAX_NUMNODES) + return -EINVAL; + + meminfo.nr_banks++; + return 0; } /* @@ -472,10 +484,10 @@ request_standard_resources(struct meminfo *mi, struct machine_desc *mdesc) struct resource *res; int i; - kernel_code.start = virt_to_phys(&_text); - kernel_code.end = virt_to_phys(&_etext - 1); - kernel_data.start = virt_to_phys(&__data_start); - kernel_data.end = virt_to_phys(&_end - 1); + kernel_code.start = virt_to_phys(_text); + kernel_code.end = virt_to_phys(_etext - 1); + kernel_data.start = virt_to_phys(_data); + kernel_data.end = virt_to_phys(_end - 1); for (i = 0; i < mi->nr_banks; i++) { if (mi->bank[i].size == 0) @@ -539,14 +551,7 @@ __tagtable(ATAG_CORE, parse_tag_core); static int __init parse_tag_mem32(const struct tag *tag) { - if (meminfo.nr_banks >= NR_BANKS) { - printk(KERN_WARNING - "Ignoring memory bank 0x%08x size %dKB\n", - tag->u.mem.start, tag->u.mem.size / 1024); - return -EINVAL; - } - arm_add_memory(tag->u.mem.start, tag->u.mem.size); - return 0; + return arm_add_memory(tag->u.mem.start, tag->u.mem.size); } __tagtable(ATAG_MEM, parse_tag_mem32); @@ -710,15 +715,15 @@ void __init setup_arch(char **cmdline_p) parse_tags(tags); } - init_mm.start_code = (unsigned long) &_text; - init_mm.end_code = (unsigned long) &_etext; - init_mm.end_data = (unsigned long) &_edata; - init_mm.brk = (unsigned long) &_end; + init_mm.start_code = (unsigned long) _text; + init_mm.end_code = (unsigned long) _etext; + init_mm.end_data = (unsigned long) _edata; + init_mm.brk = (unsigned long) _end; memcpy(boot_command_line, from, COMMAND_LINE_SIZE); boot_command_line[COMMAND_LINE_SIZE-1] = '\0'; parse_cmdline(cmdline_p, from); - paging_init(&meminfo, mdesc); + paging_init(mdesc); request_standard_resources(&meminfo, mdesc); #ifdef CONFIG_SMP @@ -772,6 +777,8 @@ static const char *hwcap_str[] = { "java", "iwmmxt", "crunch", + "thumbee", + "neon", NULL }; diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index e42a749..019237d 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -181,7 +181,7 @@ int __cpuexit __cpu_disable(void) /* * Stop the local timer for this CPU. */ - local_timer_stop(cpu); + local_timer_stop(); /* * Flush user cache and TLB mappings, and then remove this CPU @@ -284,7 +284,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void) /* * Setup local timer for this CPU. */ - local_timer_setup(cpu); + local_timer_setup(); calibrate_delay(); diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c index df3f6b7..9cb7aac 100644 --- a/arch/arm/kernel/thumbee.c +++ b/arch/arm/kernel/thumbee.c @@ -25,7 +25,7 @@ /* * Access to the ThumbEE Handler Base register */ -static inline unsigned long teehbr_read() +static inline unsigned long teehbr_read(void) { unsigned long v; asm("mrc p14, 6, %0, c1, c0, 0\n" : "=r" (v)); diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 4898bdc..0021607 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -119,7 +119,7 @@ SECTIONS #endif .data : AT(__data_loc) { - __data_start = .; /* address in memory */ + _data = .; /* address in memory */ /* * first, the init task union, aligned diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 30351cd4..866f84a 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -38,7 +38,6 @@ else endif lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o -lib-$(CONFIG_ARCH_CLPS7500) += io-acorn.o lib-$(CONFIG_ARCH_L7200) += io-acorn.o lib-$(CONFIG_ARCH_SHARK) += io-shark.o diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 761eefa..650d592 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -25,7 +25,7 @@ add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) /* * The pointer is now aligned and the length is adjusted. Try doing the - * memzero again. + * memset again. */ ENTRY(memset) diff --git a/arch/arm/mach-aaec2000/Makefile b/arch/arm/mach-aaec2000/Makefile index a8e462f..20ec838 100644 --- a/arch/arm/mach-aaec2000/Makefile +++ b/arch/arm/mach-aaec2000/Makefile @@ -3,7 +3,7 @@ # # Common support (must be linked before board specific support) -obj-y += core.o clock.o +obj-y += core.o # Specific board support obj-$(CONFIG_MACH_AAED2000) += aaed2000.o diff --git a/arch/arm/mach-aaec2000/clock.c b/arch/arm/mach-aaec2000/clock.c deleted file mode 100644 index e10ee15..0000000 --- a/arch/arm/mach-aaec2000/clock.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * linux/arch/arm/mach-aaec2000/clock.c - * - * Copyright (C) 2005 Nicolas Bellido Y Ortega - * - * Based on linux/arch/arm/mach-integrator/clock.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/string.h> -#include <linux/clk.h> -#include <linux/mutex.h> - -#include "clock.h" - -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); - -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p, *clk = ERR_PTR(-ENOENT); - - mutex_lock(&clocks_mutex); - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { - clk = p; - break; - } - } - mutex_unlock(&clocks_mutex); - - return clk; -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ - module_put(clk->owner); -} -EXPORT_SYMBOL(clk_put); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return clk->rate; -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - return rate; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - return 0; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_register(struct clk *clk) -{ - mutex_lock(&clocks_mutex); - list_add(&clk->node, &clocks); - mutex_unlock(&clocks_mutex); - return 0; -} -EXPORT_SYMBOL(clk_register); - -void clk_unregister(struct clk *clk) -{ - mutex_lock(&clocks_mutex); - list_del(&clk->node); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL(clk_unregister); - -static int __init clk_init(void) -{ - return 0; -} -arch_initcall(clk_init); diff --git a/arch/arm/mach-aaec2000/clock.h b/arch/arm/mach-aaec2000/clock.h deleted file mode 100644 index d4bb74f..0000000 --- a/arch/arm/mach-aaec2000/clock.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/arch/arm/mach-aaec2000/clock.h - * - * Copyright (C) 2005 Nicolas Bellido Y Ortega - * - * Based on linux/arch/arm/mach-integrator/clock.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -struct module; - -struct clk { - struct list_head node; - unsigned long rate; - struct module *owner; - const char *name; - void *data; -}; - -int clk_register(struct clk *clk); -void clk_unregister(struct clk *clk); diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c index dfb26bc..50e1396 100644 --- a/arch/arm/mach-aaec2000/core.c +++ b/arch/arm/mach-aaec2000/core.c @@ -19,6 +19,7 @@ #include <linux/interrupt.h> #include <linux/timex.h> #include <linux/signal.h> +#include <linux/clk.h> #include <mach/hardware.h> #include <asm/irq.h> @@ -30,7 +31,6 @@ #include <asm/mach/map.h> #include "core.h" -#include "clock.h" /* * Common I/O mapping: @@ -229,9 +229,28 @@ static struct amba_device *amba_devs[] __initdata = { &clcd_device, }; -static struct clk aaec2000_clcd_clk = { - .name = "CLCDCLK", -}; +void clk_disable(struct clk *clk) +{ +} + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + return 0; +} + +int clk_enable(struct clk *clk) +{ + return 0; +} + +struct clk *clk_get(struct device *dev, const char *id) +{ + return dev && strcmp(dev_name(dev), "mb:16") == 0 ? NULL : ERR_PTR(-ENOENT); +} + +void clk_put(struct clk *clk) +{ +} void __init aaec2000_set_clcd_plat_data(struct aaec2000_clcd_info *clcd) { @@ -265,8 +284,6 @@ static int __init aaec2000_init(void) { int i; - clk_register(&aaec2000_clcd_clk); - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; amba_device_register(d, &iomem_resource); diff --git a/arch/arm/mach-aaec2000/include/mach/dma.h b/arch/arm/mach-aaec2000/include/mach/dma.h deleted file mode 100644 index 2da846c..0000000 --- a/arch/arm/mach-aaec2000/include/mach/dma.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * arch/arm/mach-aaec2000/include/mach/dma.h - * - * Copyright (c) 2005 Nicolas Bellido Y Ortega - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ diff --git a/arch/arm/mach-aaec2000/include/mach/io.h b/arch/arm/mach-aaec2000/include/mach/io.h index c87c24de..ab4fe5d 100644 --- a/arch/arm/mach-aaec2000/include/mach/io.h +++ b/arch/arm/mach-aaec2000/include/mach/io.h @@ -6,15 +6,13 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#include <mach/hardware.h> - #define IO_SPACE_LIMIT 0xffffffff /* * We don't actually have real ISA nor PCI buses, but there is so many * drivers out there that might just work if we fake them... */ -#define __io(a) ((void __iomem *)(a)) -#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-aaec2000/include/mach/memory.h b/arch/arm/mach-aaec2000/include/mach/memory.h index 56ae900..c008225 100644 --- a/arch/arm/mach-aaec2000/include/mach/memory.h +++ b/arch/arm/mach-aaec2000/include/mach/memory.h @@ -14,9 +14,6 @@ #define PHYS_OFFSET UL(0xf0000000) -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - /* * The nodes are the followings: * diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 5aafb2e..323b47f 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -7,36 +7,43 @@ choice config ARCH_AT91RM9200 bool "AT91RM9200" + select CPU_ARM920T select GENERIC_TIME select GENERIC_CLOCKEVENTS config ARCH_AT91SAM9260 bool "AT91SAM9260 or AT91SAM9XE" + select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS config ARCH_AT91SAM9261 bool "AT91SAM9261" + select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS config ARCH_AT91SAM9263 bool "AT91SAM9263" + select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS config ARCH_AT91SAM9RL bool "AT91SAM9RL" + select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS config ARCH_AT91SAM9G20 bool "AT91SAM9G20" + select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS config ARCH_AT91CAP9 bool "AT91CAP9" + select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS @@ -235,6 +242,12 @@ config MACH_USB_A9263 Select this if you are using a Calao Systems USB-A9263. <http://www.calao-systems.com> +config MACH_NEOCORE926 + bool "Adeneo NEOCORE926" + depends on ARCH_AT91SAM9263 + help + Select this if you are using the Adeneo Neocore 926 board. + endif # ---------------------------------------------------------- @@ -302,7 +315,7 @@ comment "AT91 Board Options" config MTD_AT91_DATAFLASH_CARD bool "Enable DataFlash Card support" - depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK) + depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK || MACH_NEOCORE926) help Enable support for the DataFlash card. diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index cca612d..c69ff23 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -11,12 +11,12 @@ obj-$(CONFIG_AT91_PMC_UNIT) += clock.o # CPU-specific support obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o -obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o -obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o -obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o -obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o -obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o -obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o +obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o # AT91RM9200 board-specific support @@ -47,6 +47,7 @@ obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o # AT91SAM9263 board-specific support obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o obj-$(CONFIG_MACH_USB_A9263) += board-usb-a9263.o +obj-$(CONFIG_MACH_NEOCORE926) += board-neocore926.o # AT91SAM9RL board-specific support obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c index 0fc0ada..0a38c69 100644 --- a/arch/arm/mach-at91/at91cap9.c +++ b/arch/arm/mach-at91/at91cap9.c @@ -17,6 +17,8 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> + +#include <mach/cpu.h> #include <mach/at91cap9.h> #include <mach/at91_pmc.h> #include <mach/at91_rstc.h> @@ -317,6 +319,12 @@ void __init at91cap9_initialize(unsigned long main_clock) /* Register GPIO subsystem */ at91_gpio_init(at91cap9_gpio, 4); + + /* Remember the silicon revision */ + if (cpu_is_at91cap9_revB()) + system_rev = 0xB; + else if (cpu_is_at91cap9_revC()) + system_rev = 0xC; } /* -------------------------------------------------------------------- diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c index 5ebd427..9eca220 100644 --- a/arch/arm/mach-at91/at91cap9_devices.c +++ b/arch/arm/mach-at91/at91cap9_devices.c @@ -13,6 +13,7 @@ */ #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include <asm/mach/irq.h> #include <linux/dma-mapping.h> #include <linux/platform_device.h> @@ -21,6 +22,7 @@ #include <video/atmel_lcdc.h> #include <mach/board.h> +#include <mach/cpu.h> #include <mach/gpio.h> #include <mach/at91cap9.h> #include <mach/at91cap9_matrix.h> @@ -69,6 +71,9 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) if (!data) return; + if (cpu_is_at91cap9_revB()) + set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); + /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { if (data->vbus_pin[i]) @@ -151,8 +156,13 @@ static struct platform_device at91_usba_udc_device = { void __init at91_add_device_usba(struct usba_platform_data *data) { - at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS | - AT91_MATRIX_UDPHS_BYPASS_LOCK); + if (cpu_is_at91cap9_revB()) { + set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); + at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS | + AT91_MATRIX_UDPHS_BYPASS_LOCK); + } + else + at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS); /* * Invalid pins are 0 on AT91, but the usba driver is shared @@ -406,28 +416,13 @@ static struct platform_device at91cap9_nand_device = { void __init at91_add_device_nand(struct atmel_nand_data *data) { - unsigned long csa, mode; + unsigned long csa; if (!data) return; csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_EBI_VDDIOMSEL_3_3V); - - /* set the bus interface characteristics */ - at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) - | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1)); - - at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) - | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6)); - - at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8)); - - if (data->bus_width_16) - mode = AT91_SMC_DBW_16; - else - mode = AT91_SMC_DBW_8; - at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1)); + at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); /* enable pin */ if (data->enable_pin) @@ -865,6 +860,9 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) if (!data) return; + if (cpu_is_at91cap9_revB()) + set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index a72e798..d140eae 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -141,6 +141,15 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) /* Use "raw" primitives so we behave correctly on RT kernels. */ raw_local_irq_save(flags); + /* + * According to Thomas Gleixner irqs are already disabled here. Simply + * removing raw_local_irq_save above (and the matching + * raw_local_irq_restore) was not accepted. See + * http://thread.gmane.org/gmane.linux.ports.arm.kernel/41174 + * So for now (2008-11-20) just warn once if irqs were not disabled ... + */ + WARN_ON_ONCE(!raw_irqs_disabled_flags(flags)); + /* The alarm IRQ uses absolute time (now+delta), not the relative * time (delta) in our calling convention. Like all clockevents * using such "match" hardware, we have a race to defend against. diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 7774d17..fdde1ea 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -313,7 +313,7 @@ static struct platform_device at91sam9260_nand_device = { void __init at91_add_device_nand(struct atmel_nand_data *data) { - unsigned long csa, mode; + unsigned long csa; if (!data) return; @@ -321,42 +321,6 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) csa = at91_sys_read(AT91_MATRIX_EBICSA); at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); - if (cpu_is_at91sam9260()) { - /* Timing for sam9260 */ - /* set the bus interface characteristics */ - at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) - | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - - at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) - | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - - at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - - if (data->bus_width_16) - mode = AT91_SMC_DBW_16; - else - mode = AT91_SMC_DBW_8; - at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2)); - } - - if (cpu_is_at91sam9g20()) { - /* Timing for sam9g20 */ - /* set the bus interface characteristics */ - at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) - | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); - - at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4) - | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4)); - - at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); - - if (data->bus_width_16) - mode = AT91_SMC_DBW_16; - else - mode = AT91_SMC_DBW_8; - at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(3)); - } - /* enable pin */ if (data->enable_pin) at91_set_gpio_output(data->enable_pin, 1); diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 6b89172..1728975 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -223,7 +223,7 @@ static struct platform_device atmel_nand_device = { void __init at91_add_device_nand(struct atmel_nand_data *data) { - unsigned long csa, mode; + unsigned long csa; if (!data) return; @@ -231,21 +231,6 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) csa = at91_sys_read(AT91_MATRIX_EBICSA); at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); - /* set the bus interface characteristics */ - at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) - | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - - at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) - | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - - at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - - if (data->bus_width_16) - mode = AT91_SMC_DBW_16; - else - mode = AT91_SMC_DBW_8; - at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2)); - /* enable pin */ if (data->enable_pin) at91_set_gpio_output(data->enable_pin, 1); diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 8b88408..b753cb8 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -382,7 +382,7 @@ static struct platform_device at91sam9263_nand_device = { void __init at91_add_device_nand(struct atmel_nand_data *data) { - unsigned long csa, mode; + unsigned long csa; if (!data) return; @@ -390,21 +390,6 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) csa = at91_sys_read(AT91_MATRIX_EBI0CSA); at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); - /* set the bus interface characteristics */ - at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) - | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - - at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) - | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - - at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - - if (data->bus_width_16) - mode = AT91_SMC_DBW_16; - else - mode = AT91_SMC_DBW_8; - at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2)); - /* enable pin */ if (data->enable_pin) at91_set_gpio_output(data->enable_pin, 1); diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index 87deb1e..145324f 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c @@ -232,17 +232,6 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) csa = at91_sys_read(AT91_MATRIX_EBICSA); at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); - /* set the bus interface characteristics */ - at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) - | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - - at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) - | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - - at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - - at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2)); - /* enable pin */ if (data->enable_pin) at91_set_gpio_output(data->enable_pin, 1); diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c index cdddca5..d3ba29c 100644 --- a/arch/arm/mach-at91/board-cam60.c +++ b/arch/arm/mach-at91/board-cam60.c @@ -39,7 +39,9 @@ #include <mach/board.h> #include <mach/gpio.h> +#include <mach/at91sam9_smc.h> +#include "sam9_smc.h" #include "generic.h" @@ -151,6 +153,32 @@ static struct atmel_nand_data __initdata cam60_nand_data = { .partition_info = nand_partitions, }; +static struct sam9_smc_config __initdata cam60_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 2, +}; + +static void __init cam60_add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &cam60_nand_smc_config); + + at91_add_device_nand(&cam60_nand_data); +} + static void __init cam60_board_init(void) { @@ -165,7 +193,7 @@ static void __init cam60_board_init(void) at91_set_gpio_output(AT91_PIN_PB18, 1); at91_add_device_usbh(&cam60_usbh_data); /* NAND */ - at91_add_device_nand(&cam60_nand_data); + cam60_add_device_nand(); } MACHINE_START(CAM60, "KwikByte CAM60") diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c index 201b893..83a1a0f 100644 --- a/arch/arm/mach-at91/board-cap9adk.c +++ b/arch/arm/mach-at91/board-cap9adk.c @@ -36,17 +36,16 @@ #include <mach/hardware.h> #include <asm/setup.h> #include <asm/mach-types.h> -#include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/mach/irq.h> #include <mach/board.h> #include <mach/gpio.h> #include <mach/at91cap9_matrix.h> #include <mach/at91sam9_smc.h> +#include "sam9_smc.h" #include "generic.h" @@ -195,6 +194,43 @@ static struct atmel_nand_data __initdata cap9adk_nand_data = { #endif }; +static struct sam9_smc_config __initdata cap9adk_nand_smc_config = { + .ncs_read_setup = 1, + .nrd_setup = 2, + .ncs_write_setup = 1, + .nwe_setup = 2, + + .ncs_read_pulse = 6, + .nrd_pulse = 4, + .ncs_write_pulse = 6, + .nwe_pulse = 4, + + .read_cycle = 8, + .write_cycle = 8, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 1, +}; + +static void __init cap9adk_add_device_nand(void) +{ + unsigned long csa; + + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V); + + /* setup bus-width (8 or 16) */ + if (cap9adk_nand_data.bus_width_16) + cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &cap9adk_nand_smc_config); + + at91_add_device_nand(&cap9adk_nand_data); +} + /* * NOR flash @@ -234,6 +270,24 @@ static struct platform_device cap9adk_nor_flash = { .num_resources = ARRAY_SIZE(nor_flash_resources), }; +static struct sam9_smc_config __initdata cap9adk_nor_smc_config = { + .ncs_read_setup = 2, + .nrd_setup = 4, + .ncs_write_setup = 2, + .nwe_setup = 4, + + .ncs_read_pulse = 10, + .nrd_pulse = 8, + .ncs_write_pulse = 10, + .nwe_pulse = 8, + + .read_cycle = 16, + .write_cycle = 16, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16, + .tdf_cycles = 1, +}; + static __init void cap9adk_add_device_nor(void) { unsigned long csa; @@ -241,18 +295,8 @@ static __init void cap9adk_add_device_nor(void) csa = at91_sys_read(AT91_MATRIX_EBICSA); at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V); - /* set the bus interface characteristics */ - at91_sys_write(AT91_SMC_SETUP(0), AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) - | AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2)); - - at91_sys_write(AT91_SMC_PULSE(0), AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) - | AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10)); - - at91_sys_write(AT91_SMC_CYCLE(0), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); - - at91_sys_write(AT91_SMC_MODE(0), AT91_SMC_READMODE | AT91_SMC_WRITEMODE - | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE - | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1)); + /* configure chip-select 0 (NOR) */ + sam9_smc_configure(0, &cap9adk_nor_smc_config); platform_device_register(&cap9adk_nor_flash); } @@ -330,10 +374,8 @@ static void __init cap9adk_board_init(void) /* Serial */ at91_add_device_serial(); /* USB Host */ - set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); at91_add_device_usbh(&cap9adk_usbh_data); /* USB HS */ - set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); at91_add_device_usba(&cap9adk_usba_udc_data); /* SPI */ at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices)); @@ -344,13 +386,12 @@ static void __init cap9adk_board_init(void) /* Ethernet */ at91_add_device_eth(&cap9adk_macb_data); /* NAND */ - at91_add_device_nand(&cap9adk_nand_data); + cap9adk_add_device_nand(); /* NOR Flash */ cap9adk_add_device_nor(); /* I2C */ at91_add_device_i2c(NULL, 0); /* LCD Controller */ - set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); at91_add_device_lcdc(&cap9adk_lcdc_data); /* AC97 */ at91_add_device_ac97(&cap9adk_ac97_data); diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c new file mode 100644 index 0000000..9ba7ba2 --- /dev/null +++ b/arch/arm/mach-at91/board-neocore926.c @@ -0,0 +1,397 @@ +/* + * linux/arch/arm/mach-at91/board-neocore926.c + * + * Copyright (C) 2005 SAN People + * Copyright (C) 2007 Atmel Corporation + * Copyright (C) 2008 ADENEO. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/types.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/spi/spi.h> +#include <linux/spi/ads7846.h> +#include <linux/fb.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> + +#include <video/atmel_lcdc.h> + +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/irq.h> +#include <asm/sizes.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <mach/hardware.h> +#include <mach/board.h> +#include <mach/gpio.h> +#include <mach/at91sam9_smc.h> + +#include "sam9_smc.h" +#include "generic.h" + + +static void __init neocore926_map_io(void) +{ + /* Initialize processor: 20 MHz crystal */ + at91sam9263_initialize(20000000); + + /* DGBU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); + + /* set serial console to ttyS0 (ie, DBGU) */ + at91_set_serial_console(0); +} + +static void __init neocore926_init_irq(void) +{ + at91sam9263_init_interrupts(NULL); +} + + +/* + * USB Host port + */ +static struct at91_usbh_data __initdata neocore926_usbh_data = { + .ports = 2, + .vbus_pin = { AT91_PIN_PA24, AT91_PIN_PA21 }, +}; + +/* + * USB Device port + */ +static struct at91_udc_data __initdata neocore926_udc_data = { + .vbus_pin = AT91_PIN_PA25, + .pullup_pin = 0, /* pull-up driven by UDC */ +}; + + +/* + * ADS7846 Touchscreen + */ +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) +static int ads7843_pendown_state(void) +{ + return !at91_get_gpio_value(AT91_PIN_PA15); /* Touchscreen PENIRQ */ +} + +static struct ads7846_platform_data ads_info = { + .model = 7843, + .x_min = 150, + .x_max = 3830, + .y_min = 190, + .y_max = 3830, + .vref_delay_usecs = 100, + .x_plate_ohms = 450, + .y_plate_ohms = 250, + .pressure_max = 15000, + .debounce_max = 1, + .debounce_rep = 0, + .debounce_tol = (~0), + .get_pendown_state = ads7843_pendown_state, +}; + +static void __init neocore926_add_device_ts(void) +{ + at91_set_B_periph(AT91_PIN_PA15, 1); /* External IRQ1, with pullup */ + at91_set_gpio_input(AT91_PIN_PC13, 1); /* Touchscreen BUSY signal */ +} +#else +static void __init neocore926_add_device_ts(void) {} +#endif + +/* + * SPI devices. + */ +static struct spi_board_info neocore926_spi_devices[] = { +#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) + { /* DataFlash card */ + .modalias = "mtd_dataflash", + .chip_select = 0, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#endif +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) + { + .modalias = "ads7846", + .chip_select = 1, + .max_speed_hz = 125000 * 16, + .bus_num = 0, + .platform_data = &ads_info, + .irq = AT91SAM9263_ID_IRQ1, + }, +#endif +}; + + +/* + * MCI (SD/MMC) + */ +static struct at91_mmc_data __initdata neocore926_mmc_data = { + .wire4 = 1, + .det_pin = AT91_PIN_PE18, + .wp_pin = AT91_PIN_PE19, +}; + + +/* + * MACB Ethernet device + */ +static struct at91_eth_data __initdata neocore926_macb_data = { + .phy_irq_pin = AT91_PIN_PE31, + .is_rmii = 1, +}; + + +/* + * NAND flash + */ +static struct mtd_partition __initdata neocore926_nand_partition[] = { + { + .name = "Linux Kernel", /* "Partition 1", */ + .offset = 0, + .size = SZ_8M, + }, + { + .name = "Filesystem", /* "Partition 2", */ + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_32M, + }, + { + .name = "Free", /* "Partition 3", */ + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) +{ + *num_partitions = ARRAY_SIZE(neocore926_nand_partition); + return neocore926_nand_partition; +} + +static struct atmel_nand_data __initdata neocore926_nand_data = { + .ale = 21, + .cle = 22, + .rdy_pin = AT91_PIN_PB19, + .rdy_pin_active_low = 1, + .enable_pin = AT91_PIN_PD15, + .partition_info = nand_partitions, +}; + +static struct sam9_smc_config __initdata neocore926_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 4, + .nrd_pulse = 4, + .ncs_write_pulse = 4, + .nwe_pulse = 4, + + .read_cycle = 6, + .write_cycle = 6, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 2, +}; + +static void __init neocore926_add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &neocore926_nand_smc_config); + + at91_add_device_nand(&neocore926_nand_data); +} + + +/* + * LCD Controller + */ +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "TX09D50VM1CCA @ 60", + .refresh = 60, + .xres = 240, .yres = 320, + .pixclock = KHZ2PICOS(5000), + + .left_margin = 1, .right_margin = 33, + .upper_margin = 1, .lower_margin = 0, + .hsync_len = 5, .vsync_len = 1, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +static struct fb_monspecs at91fb_default_monspecs = { + .manufacturer = "HIT", + .monitor = "TX09D70VM1CCA", + + .modedb = at91_tft_vga_modes, + .modedb_len = ARRAY_SIZE(at91_tft_vga_modes), + .hfmin = 15000, + .hfmax = 64000, + .vfmin = 50, + .vfmax = 150, +}; + +#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ + | ATMEL_LCDC_DISTYPE_TFT \ + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) + +static void at91_lcdc_power_control(int on) +{ + at91_set_gpio_value(AT91_PIN_PA30, on); +} + +/* Driver datas */ +static struct atmel_lcdfb_info __initdata neocore926_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2, + .default_monspecs = &at91fb_default_monspecs, + .atmel_lcdfb_power_control = at91_lcdc_power_control, + .guard_time = 1, + .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB555, +}; + +#else +static struct atmel_lcdfb_info __initdata neocore926_lcdc_data; +#endif + + +/* + * GPIO Buttons + */ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +static struct gpio_keys_button neocore926_buttons[] = { + { /* BP1, "leftclic" */ + .code = BTN_LEFT, + .gpio = AT91_PIN_PC5, + .active_low = 1, + .desc = "left_click", + .wakeup = 1, + }, + { /* BP2, "rightclic" */ + .code = BTN_RIGHT, + .gpio = AT91_PIN_PC4, + .active_low = 1, + .desc = "right_click", + .wakeup = 1, + }, +}; + +static struct gpio_keys_platform_data neocore926_button_data = { + .buttons = neocore926_buttons, + .nbuttons = ARRAY_SIZE(neocore926_buttons), +}; + +static struct platform_device neocore926_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &neocore926_button_data, + } +}; + +static void __init neocore926_add_device_buttons(void) +{ + at91_set_GPIO_periph(AT91_PIN_PC5, 0); /* left button */ + at91_set_deglitch(AT91_PIN_PC5, 1); + at91_set_GPIO_periph(AT91_PIN_PC4, 0); /* right button */ + at91_set_deglitch(AT91_PIN_PC4, 1); + + platform_device_register(&neocore926_button_device); +} +#else +static void __init neocore926_add_device_buttons(void) {} +#endif + + +/* + * AC97 + */ +static struct atmel_ac97_data neocore926_ac97_data = { + .reset_pin = AT91_PIN_PA13, +}; + + +static void __init neocore926_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + + /* USB Host */ + at91_add_device_usbh(&neocore926_usbh_data); + + /* USB Device */ + at91_add_device_udc(&neocore926_udc_data); + + /* SPI */ + at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */ + at91_add_device_spi(neocore926_spi_devices, ARRAY_SIZE(neocore926_spi_devices)); + + /* Touchscreen */ + neocore926_add_device_ts(); + + /* MMC */ + at91_add_device_mmc(1, &neocore926_mmc_data); + + /* Ethernet */ + at91_add_device_eth(&neocore926_macb_data); + + /* NAND */ + neocore926_add_device_nand(); + + /* I2C */ + at91_add_device_i2c(NULL, 0); + + /* LCD Controller */ + at91_add_device_lcdc(&neocore926_lcdc_data); + + /* Push Buttons */ + neocore926_add_device_buttons(); + + /* AC97 */ + at91_add_device_ac97(&neocore926_ac97_data); +} + +MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926") + /* Maintainer: ADENEO */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = neocore926_map_io, + .init_irq = neocore926_init_irq, + .init_machine = neocore926_board_init, +MACHINE_END diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c index cfb4571..4cff9a7 100644 --- a/arch/arm/mach-at91/board-qil-a9260.c +++ b/arch/arm/mach-at91/board-qil-a9260.c @@ -41,8 +41,10 @@ #include <mach/hardware.h> #include <mach/board.h> #include <mach/gpio.h> +#include <mach/at91sam9_smc.h> #include <mach/at91_shdwc.h> +#include "sam9_smc.h" #include "generic.h" @@ -147,13 +149,34 @@ static struct atmel_nand_data __initdata ek_nand_data = { .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, .partition_info = nand_partitions, -#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) - .bus_width_16 = 1, -#else - .bus_width_16 = 0, -#endif }; +static struct sam9_smc_config __initdata ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 2, +}; + +static void __init ek_add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&ek_nand_data); +} + /* * MCI (SD/MMC) */ @@ -227,7 +250,7 @@ static void __init ek_board_init(void) /* SPI */ at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); /* NAND */ - at91_add_device_nand(&ek_nand_data); + ek_add_device_nand(); /* I2C */ at91_add_device_i2c(NULL, 0); /* Ethernet */ diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c index 99bb4cc..b483469 100644 --- a/arch/arm/mach-at91/board-sam9-l9260.c +++ b/arch/arm/mach-at91/board-sam9-l9260.c @@ -38,7 +38,9 @@ #include <mach/board.h> #include <mach/gpio.h> +#include <mach/at91sam9_smc.h> +#include "sam9_smc.h" #include "generic.h" @@ -148,13 +150,34 @@ static struct atmel_nand_data __initdata ek_nand_data = { .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, .partition_info = nand_partitions, -#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) - .bus_width_16 = 1, -#else - .bus_width_16 = 0, -#endif }; +static struct sam9_smc_config __initdata ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 2, +}; + +static void __init ek_add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&ek_nand_data); +} + /* * MCI (SD/MMC) @@ -178,7 +201,7 @@ static void __init ek_board_init(void) /* SPI */ at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); /* NAND */ - at91_add_device_nand(&ek_nand_data); + ek_add_device_nand(); /* Ethernet */ at91_add_device_eth(&ek_macb_data); /* MMC */ diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c index b49eb6e..93a0f8b 100644 --- a/arch/arm/mach-at91/board-sam9260ek.c +++ b/arch/arm/mach-at91/board-sam9260ek.c @@ -42,7 +42,10 @@ #include <mach/hardware.h> #include <mach/board.h> #include <mach/gpio.h> +#include <mach/at91sam9_smc.h> +#include <mach/at91_shdwc.h> +#include "sam9_smc.h" #include "generic.h" @@ -195,6 +198,38 @@ static struct atmel_nand_data __initdata ek_nand_data = { #endif }; +static struct sam9_smc_config __initdata ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 2, +}; + +static void __init ek_add_device_nand(void) +{ + /* setup bus-width (8 or 16) */ + if (ek_nand_data.bus_width_16) + ek_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + ek_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&ek_nand_data); +} + /* * MCI (SD/MMC) @@ -303,7 +338,7 @@ static void __init ek_board_init(void) /* SPI */ at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); /* NAND */ - at91_add_device_nand(&ek_nand_data); + ek_add_device_nand(); /* Ethernet */ at91_add_device_eth(&ek_macb_data); /* MMC */ diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index 4977409..d5266da 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -47,7 +47,9 @@ #include <mach/board.h> #include <mach/gpio.h> #include <mach/at91sam9_smc.h> +#include <mach/at91_shdwc.h> +#include "sam9_smc.h" #include "generic.h" @@ -76,7 +78,7 @@ static void __init ek_init_irq(void) * DM9000 ethernet device */ #if defined(CONFIG_DM9000) -static struct resource at91sam9261_dm9000_resource[] = { +static struct resource dm9000_resource[] = { [0] = { .start = AT91_CHIPSELECT_2, .end = AT91_CHIPSELECT_2 + 3, @@ -98,27 +100,42 @@ static struct dm9000_plat_data dm9000_platdata = { .flags = DM9000_PLATF_16BITONLY, }; -static struct platform_device at91sam9261_dm9000_device = { +static struct platform_device dm9000_device = { .name = "dm9000", .id = 0, - .num_resources = ARRAY_SIZE(at91sam9261_dm9000_resource), - .resource = at91sam9261_dm9000_resource, + .num_resources = ARRAY_SIZE(dm9000_resource), + .resource = dm9000_resource, .dev = { .platform_data = &dm9000_platdata, } }; +/* + * SMC timings for the DM9000. + * Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings. + */ +static struct sam9_smc_config __initdata dm9000_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 2, + .ncs_write_setup = 0, + .nwe_setup = 2, + + .ncs_read_pulse = 8, + .nrd_pulse = 4, + .ncs_write_pulse = 8, + .nwe_pulse = 4, + + .read_cycle = 16, + .write_cycle = 16, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16, + .tdf_cycles = 1, +}; + static void __init ek_add_device_dm9000(void) { - /* - * Configure Chip-Select 2 on SMC for the DM9000. - * Note: These timings were calculated for MASTER_CLOCK = 100000000 - * according to the DM9000 timings. - */ - at91_sys_write(AT91_SMC_SETUP(2), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(2), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); - at91_sys_write(AT91_SMC_CYCLE(2), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); - at91_sys_write(AT91_SMC_MODE(2), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1)); + /* Configure chip-select 2 (DM9000) */ + sam9_smc_configure(2, &dm9000_smc_config); /* Configure Reset signal as output */ at91_set_gpio_output(AT91_PIN_PC10, 0); @@ -126,7 +143,7 @@ static void __init ek_add_device_dm9000(void) /* Configure Interrupt pin as input, no pull-up */ at91_set_gpio_input(AT91_PIN_PC11, 0); - platform_device_register(&at91sam9261_dm9000_device); + platform_device_register(&dm9000_device); } #else static void __init ek_add_device_dm9000(void) {} @@ -197,6 +214,39 @@ static struct atmel_nand_data __initdata ek_nand_data = { #endif }; +static struct sam9_smc_config __initdata ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 2, +}; + +static void __init ek_add_device_nand(void) +{ + /* setup bus-width (8 or 16) */ + if (ek_nand_data.bus_width_16) + ek_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + ek_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&ek_nand_data); +} + + /* * ADS7846 Touchscreen */ @@ -525,7 +575,7 @@ static void __init ek_board_init(void) /* I2C */ at91_add_device_i2c(NULL, 0); /* NAND */ - at91_add_device_nand(&ek_nand_data); + ek_add_device_nand(); /* DM9000 ethernet */ ek_add_device_dm9000(); diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 8354015..57d5252 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c @@ -46,7 +46,9 @@ #include <mach/board.h> #include <mach/gpio.h> #include <mach/at91sam9_smc.h> +#include <mach/at91_shdwc.h> +#include "sam9_smc.h" #include "generic.h" @@ -203,6 +205,38 @@ static struct atmel_nand_data __initdata ek_nand_data = { #endif }; +static struct sam9_smc_config __initdata ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 2, +}; + +static void __init ek_add_device_nand(void) +{ + /* setup bus-width (8 or 16) */ + if (ek_nand_data.bus_width_16) + ek_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + ek_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&ek_nand_data); +} + /* * I2C devices @@ -385,7 +419,7 @@ static void __init ek_board_init(void) /* Ethernet */ at91_add_device_eth(&ek_macb_data); /* NAND */ - at91_add_device_nand(&ek_nand_data); + ek_add_device_nand(); /* I2C */ at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); /* LCD Controller */ diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index b588ead..81439fe 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c @@ -37,7 +37,9 @@ #include <mach/board.h> #include <mach/gpio.h> +#include <mach/at91sam9_smc.h> +#include "sam9_smc.h" #include "generic.h" @@ -156,6 +158,38 @@ static struct atmel_nand_data __initdata ek_nand_data = { #endif }; +static struct sam9_smc_config __initdata ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 2, + .ncs_write_setup = 0, + .nwe_setup = 2, + + .ncs_read_pulse = 4, + .nrd_pulse = 4, + .ncs_write_pulse = 4, + .nwe_pulse = 4, + + .read_cycle = 7, + .write_cycle = 7, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 3, +}; + +static void __init ek_add_device_nand(void) +{ + /* setup bus-width (8 or 16) */ + if (ek_nand_data.bus_width_16) + ek_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + ek_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&ek_nand_data); +} + /* * MCI (SD/MMC) @@ -195,7 +229,7 @@ static void __init ek_board_init(void) /* SPI */ at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); /* NAND */ - at91_add_device_nand(&ek_nand_data); + ek_add_device_nand(); /* Ethernet */ at91_add_device_eth(&ek_macb_data); /* MMC */ diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index 2708518..9b937ee 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c @@ -29,8 +29,9 @@ #include <mach/hardware.h> #include <mach/board.h> #include <mach/gpio.h> -#include <mach/at91sam9_smc.h> +#include <mach/at91_shdwc.h> +#include "sam9_smc.h" #include "generic.h" @@ -103,9 +104,34 @@ static struct atmel_nand_data __initdata ek_nand_data = { .rdy_pin = AT91_PIN_PD17, .enable_pin = AT91_PIN_PB6, .partition_info = nand_partitions, - .bus_width_16 = 0, }; +static struct sam9_smc_config __initdata ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 2, +}; + +static void __init ek_add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&ek_nand_data); +} + /* * SPI devices @@ -188,7 +214,7 @@ static void __init ek_board_init(void) /* I2C */ at91_add_device_i2c(NULL, 0); /* NAND */ - at91_add_device_nand(&ek_nand_data); + ek_add_device_nand(); /* SPI */ at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); /* MMC */ diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c index 7c35035..d13304c 100644 --- a/arch/arm/mach-at91/board-usb-a9260.c +++ b/arch/arm/mach-at91/board-usb-a9260.c @@ -41,8 +41,10 @@ #include <mach/hardware.h> #include <mach/board.h> #include <mach/gpio.h> +#include <mach/at91sam9_smc.h> #include <mach/at91_shdwc.h> +#include "sam9_smc.h" #include "generic.h" @@ -121,13 +123,34 @@ static struct atmel_nand_data __initdata ek_nand_data = { .rdy_pin = AT91_PIN_PC13, .enable_pin = AT91_PIN_PC14, .partition_info = nand_partitions, -#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) - .bus_width_16 = 1, -#else - .bus_width_16 = 0, -#endif }; +static struct sam9_smc_config __initdata ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 2, +}; + +static void __init ek_add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&ek_nand_data); +} + /* * GPIO Buttons */ @@ -189,7 +212,7 @@ static void __init ek_board_init(void) /* USB Device */ at91_add_device_udc(&ek_udc_data); /* NAND */ - at91_add_device_nand(&ek_nand_data); + ek_add_device_nand(); /* I2C */ at91_add_device_i2c(NULL, 0); /* Ethernet */ diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a9263.c index 391b566..d96405b 100644 --- a/arch/arm/mach-at91/board-usb-a9263.c +++ b/arch/arm/mach-at91/board-usb-a9263.c @@ -40,8 +40,10 @@ #include <mach/hardware.h> #include <mach/board.h> #include <mach/gpio.h> +#include <mach/at91sam9_smc.h> #include <mach/at91_shdwc.h> +#include "sam9_smc.h" #include "generic.h" @@ -134,13 +136,35 @@ static struct atmel_nand_data __initdata ek_nand_data = { .rdy_pin = AT91_PIN_PA22, .enable_pin = AT91_PIN_PD15, .partition_info = nand_partitions, -#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) - .bus_width_16 = 1, -#else - .bus_width_16 = 0, -#endif }; +static struct sam9_smc_config __initdata ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 2, +}; + +static void __init ek_add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&ek_nand_data); +} + + /* * GPIO Buttons */ @@ -206,7 +230,7 @@ static void __init ek_board_init(void) /* Ethernet */ at91_add_device_eth(&ek_macb_data); /* NAND */ - at91_add_device_nand(&ek_nand_data); + ek_add_device_nand(); /* I2C */ at91_add_device_i2c(NULL, 0); /* Push Buttons */ diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 2e3f289..9561e33 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -23,6 +23,7 @@ #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ +#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */ #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ #define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ @@ -102,10 +103,16 @@ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ +#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ +#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ +#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ + +#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ + #endif diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h index 4a4b641..d8c1ede 100644 --- a/arch/arm/mach-at91/include/mach/at91cap9.h +++ b/arch/arm/mach-at91/include/mach/at91cap9.h @@ -101,7 +101,9 @@ #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR (cpu_is_at91cap9_revB() ? \ + (0xfffffd50 - AT91_BASE_SYS) : \ + (0xfffffd60 - AT91_BASE_SYS)) #define AT91_USART0 AT91CAP9_BASE_US0 #define AT91_USART1 AT91CAP9_BASE_US1 diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index dbfd9f7..c554c3e 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -49,6 +49,17 @@ static inline unsigned long at91_arch_identify(void) return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH); } +#ifdef CONFIG_ARCH_AT91CAP9 +#include <mach/at91_pmc.h> + +#define ARCH_REVISION_CAP9_B 0x399 +#define ARCH_REVISION_CAP9_C 0x601 + +static inline unsigned long at91cap9_rev_identify(void) +{ + return (at91_sys_read(AT91_PMC_VER)); +} +#endif #ifdef CONFIG_ARCH_AT91RM9200 #define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200) @@ -90,8 +101,12 @@ static inline unsigned long at91_arch_identify(void) #ifdef CONFIG_ARCH_AT91CAP9 #define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) +#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B) +#define cpu_is_at91cap9_revC() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_C) #else #define cpu_is_at91cap9() (0) +#define cpu_is_at91cap9_revB() (0) +#define cpu_is_at91cap9_revC() (0) #endif /* diff --git a/arch/arm/mach-at91/include/mach/dma.h b/arch/arm/mach-at91/include/mach/dma.h deleted file mode 100644 index e4f90c1..0000000 --- a/arch/arm/mach-at91/include/mach/dma.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/dma.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h index 1611bd0..0b0cccc 100644 --- a/arch/arm/mach-at91/include/mach/io.h +++ b/arch/arm/mach-at91/include/mach/io.h @@ -23,8 +23,8 @@ #define IO_SPACE_LIMIT 0xFFFFFFFF -#define __io(a) ((void __iomem *)(a)) -#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-at91/include/mach/memory.h b/arch/arm/mach-at91/include/mach/memory.h index 9dd1b8c..14f4ef4 100644 --- a/arch/arm/mach-at91/include/mach/memory.h +++ b/arch/arm/mach-at91/include/mach/memory.h @@ -25,15 +25,4 @@ #define PHYS_OFFSET (AT91_SDRAM_BASE) - -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - #endif diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c new file mode 100644 index 0000000..5eab6aa6 --- /dev/null +++ b/arch/arm/mach-at91/sam9_smc.c @@ -0,0 +1,47 @@ +/* + * linux/arch/arm/mach-at91/sam9_smc.c + * + * Copyright (C) 2008 Andrew Victor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/io.h> + +#include <mach/at91sam9_smc.h> + +#include "sam9_smc.h" + +void __init sam9_smc_configure(int cs, struct sam9_smc_config* config) +{ + /* Setup register */ + at91_sys_write(AT91_SMC_SETUP(cs), + AT91_SMC_NWESETUP_(config->nwe_setup) + | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup) + | AT91_SMC_NRDSETUP_(config->nrd_setup) + | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup) + ); + + /* Pulse register */ + at91_sys_write(AT91_SMC_PULSE(cs), + AT91_SMC_NWEPULSE_(config->nwe_pulse) + | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse) + | AT91_SMC_NRDPULSE_(config->nrd_pulse) + | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse) + ); + + /* Cycle register */ + at91_sys_write(AT91_SMC_CYCLE(cs), + AT91_SMC_NWECYCLE_(config->write_cycle) + | AT91_SMC_NRDCYCLE_(config->read_cycle) + ); + + /* Mode register */ + at91_sys_write(AT91_SMC_MODE(cs), + config->mode + | AT91_SMC_TDF_(config->tdf_cycles) + ); +} diff --git a/arch/arm/mach-at91/sam9_smc.h b/arch/arm/mach-at91/sam9_smc.h new file mode 100644 index 0000000..bf72cfb --- /dev/null +++ b/arch/arm/mach-at91/sam9_smc.h @@ -0,0 +1,33 @@ +/* + * linux/arch/arm/mach-at91/sam9_smc. + * + * Copyright (C) 2008 Andrew Victor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +struct sam9_smc_config { + /* Setup register */ + u8 ncs_read_setup; + u8 nrd_setup; + u8 ncs_write_setup; + u8 nwe_setup; + + /* Pulse register */ + u8 ncs_read_pulse; + u8 nrd_pulse; + u8 ncs_write_pulse; + u8 nwe_pulse; + + /* Cycle register */ + u16 read_cycle; + u16 write_cycle; + + /* Mode register */ + u32 mode; + u8 tdf_cycles:4; +}; + +extern void __init sam9_smc_configure(int cs, struct sam9_smc_config* config); diff --git a/arch/arm/mach-clps711x/include/mach/dma.h b/arch/arm/mach-clps711x/include/mach/dma.h deleted file mode 100644 index 0d620e8..0000000 --- a/arch/arm/mach-clps711x/include/mach/dma.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/dma.h - * - * Copyright (C) 1997,1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ diff --git a/arch/arm/mach-clps711x/include/mach/io.h b/arch/arm/mach-clps711x/include/mach/io.h index 4c84400..2e0b3ce 100644 --- a/arch/arm/mach-clps711x/include/mach/io.h +++ b/arch/arm/mach-clps711x/include/mach/io.h @@ -20,12 +20,10 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#include <mach/hardware.h> - #define IO_SPACE_LIMIT 0xffffffff -#define __io(a) ((void __iomem *)(a)) -#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) /* * We don't support ins[lb]/outs[lb]. Make them fault. diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h index 98ec30c..e522b20 100644 --- a/arch/arm/mach-clps711x/include/mach/memory.h +++ b/arch/arm/mach-clps711x/include/mach/memory.h @@ -26,25 +26,7 @@ */ #define PHYS_OFFSET UL(0xc0000000) -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ - -#if defined(CONFIG_ARCH_CDB89712) - -#define __virt_to_bus(x) (x) -#define __bus_to_virt(x) (x) - -#elif defined (CONFIG_ARCH_AUTCPU12) - -#define __virt_to_bus(x) (x) -#define __bus_to_virt(x) (x) - -#else +#if !defined(CONFIG_ARCH_CDB89712) && !defined (CONFIG_ARCH_AUTCPU12) #define __virt_to_bus(x) ((x) - PAGE_OFFSET) #define __bus_to_virt(x) ((x) + PAGE_OFFSET) diff --git a/arch/arm/mach-clps7500/Makefile b/arch/arm/mach-clps7500/Makefile deleted file mode 100644 index 4bd8ebd..0000000 --- a/arch/arm/mach-clps7500/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y := core.o -obj-m := -obj-n := -obj- := - diff --git a/arch/arm/mach-clps7500/Makefile.boot b/arch/arm/mach-clps7500/Makefile.boot deleted file mode 100644 index fe16506..0000000 --- a/arch/arm/mach-clps7500/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ - zreladdr-y := 0x10008000 - diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c deleted file mode 100644 index 7e247c0..0000000 --- a/arch/arm/mach-clps7500/core.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * linux/arch/arm/mach-clps7500/core.c - * - * Copyright (C) 1998 Russell King - * Copyright (C) 1999 Nexus Electronics Ltd - * - * Extra MM routines for CL7500 architecture - */ -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/list.h> -#include <linux/sched.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/serial_8250.h> -#include <linux/io.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> - -#include <mach/hardware.h> -#include <asm/hardware/iomd.h> -#include <asm/irq.h> -#include <asm/mach-types.h> - -unsigned int vram_size; - -static void cl7500_ack_irq_a(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << irq; - val = iomd_readb(IOMD_IRQMASKA); - iomd_writeb(val & ~mask, IOMD_IRQMASKA); - iomd_writeb(mask, IOMD_IRQCLRA); -} - -static void cl7500_mask_irq_a(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << irq; - val = iomd_readb(IOMD_IRQMASKA); - iomd_writeb(val & ~mask, IOMD_IRQMASKA); -} - -static void cl7500_unmask_irq_a(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << irq; - val = iomd_readb(IOMD_IRQMASKA); - iomd_writeb(val | mask, IOMD_IRQMASKA); -} - -static struct irq_chip clps7500_a_chip = { - .ack = cl7500_ack_irq_a, - .mask = cl7500_mask_irq_a, - .unmask = cl7500_unmask_irq_a, -}; - -static void cl7500_mask_irq_b(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKB); - iomd_writeb(val & ~mask, IOMD_IRQMASKB); -} - -static void cl7500_unmask_irq_b(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKB); - iomd_writeb(val | mask, IOMD_IRQMASKB); -} - -static struct irq_chip clps7500_b_chip = { - .ack = cl7500_mask_irq_b, - .mask = cl7500_mask_irq_b, - .unmask = cl7500_unmask_irq_b, -}; - -static void cl7500_mask_irq_c(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKC); - iomd_writeb(val & ~mask, IOMD_IRQMASKC); -} - -static void cl7500_unmask_irq_c(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKC); - iomd_writeb(val | mask, IOMD_IRQMASKC); -} - -static struct irq_chip clps7500_c_chip = { - .ack = cl7500_mask_irq_c, - .mask = cl7500_mask_irq_c, - .unmask = cl7500_unmask_irq_c, -}; - -static void cl7500_mask_irq_d(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKD); - iomd_writeb(val & ~mask, IOMD_IRQMASKD); -} - -static void cl7500_unmask_irq_d(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKD); - iomd_writeb(val | mask, IOMD_IRQMASKD); -} - -static struct irq_chip clps7500_d_chip = { - .ack = cl7500_mask_irq_d, - .mask = cl7500_mask_irq_d, - .unmask = cl7500_unmask_irq_d, -}; - -static void cl7500_mask_irq_dma(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_DMAMASK); - iomd_writeb(val & ~mask, IOMD_DMAMASK); -} - -static void cl7500_unmask_irq_dma(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_DMAMASK); - iomd_writeb(val | mask, IOMD_DMAMASK); -} - -static struct irq_chip clps7500_dma_chip = { - .ack = cl7500_mask_irq_dma, - .mask = cl7500_mask_irq_dma, - .unmask = cl7500_unmask_irq_dma, -}; - -static void cl7500_mask_irq_fiq(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_FIQMASK); - iomd_writeb(val & ~mask, IOMD_FIQMASK); -} - -static void cl7500_unmask_irq_fiq(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_FIQMASK); - iomd_writeb(val | mask, IOMD_FIQMASK); -} - -static struct irq_chip clps7500_fiq_chip = { - .ack = cl7500_mask_irq_fiq, - .mask = cl7500_mask_irq_fiq, - .unmask = cl7500_unmask_irq_fiq, -}; - -static void cl7500_no_action(unsigned int irq) -{ -} - -static struct irq_chip clps7500_no_chip = { - .ack = cl7500_no_action, - .mask = cl7500_no_action, - .unmask = cl7500_no_action, -}; - -static struct irqaction irq_isa = { - .handler = no_action, - .mask = CPU_MASK_NONE, - .name = "isa", -}; - -static void __init clps7500_init_irq(void) -{ - unsigned int irq, flags; - - iomd_writeb(0, IOMD_IRQMASKA); - iomd_writeb(0, IOMD_IRQMASKB); - iomd_writeb(0, IOMD_FIQMASK); - iomd_writeb(0, IOMD_DMAMASK); - - for (irq = 0; irq < NR_IRQS; irq++) { - flags = IRQF_VALID; - - if (irq <= 6 || (irq >= 9 && irq <= 15) || - (irq >= 48 && irq <= 55)) - flags |= IRQF_PROBE; - - switch (irq) { - case 0 ... 7: - set_irq_chip(irq, &clps7500_a_chip); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, flags); - break; - - case 8 ... 15: - set_irq_chip(irq, &clps7500_b_chip); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, flags); - break; - - case 16 ... 22: - set_irq_chip(irq, &clps7500_dma_chip); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, flags); - break; - - case 24 ... 31: - set_irq_chip(irq, &clps7500_c_chip); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, flags); - break; - - case 40 ... 47: - set_irq_chip(irq, &clps7500_d_chip); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, flags); - break; - - case 48 ... 55: - set_irq_chip(irq, &clps7500_no_chip); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, flags); - break; - - case 64 ... 72: - set_irq_chip(irq, &clps7500_fiq_chip); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, flags); - break; - } - } - - setup_irq(IRQ_ISA, &irq_isa); -} - -static struct map_desc cl7500_io_desc[] __initdata = { - { /* IO space */ - .virtual = (unsigned long)IO_BASE, - .pfn = __phys_to_pfn(IO_START), - .length = IO_SIZE, - .type = MT_DEVICE - }, { /* ISA space */ - .virtual = ISA_BASE, - .pfn = __phys_to_pfn(ISA_START), - .length = ISA_SIZE, - .type = MT_DEVICE - }, { /* Flash */ - .virtual = CLPS7500_FLASH_BASE, - .pfn = __phys_to_pfn(CLPS7500_FLASH_START), - .length = CLPS7500_FLASH_SIZE, - .type = MT_DEVICE - }, { /* LED */ - .virtual = LED_BASE, - .pfn = __phys_to_pfn(LED_START), - .length = LED_SIZE, - .type = MT_DEVICE - } -}; - -static void __init clps7500_map_io(void) -{ - iotable_init(cl7500_io_desc, ARRAY_SIZE(cl7500_io_desc)); -} - -extern void ioctime_init(void); -extern unsigned long ioc_timer_gettimeoffset(void); - -static irqreturn_t -clps7500_timer_interrupt(int irq, void *dev_id) -{ - timer_tick(); - - /* Why not using do_leds interface?? */ - { - /* Twinkle the lights. */ - static int count, state = 0xff00; - if (count-- == 0) { - state ^= 0x100; - count = 25; - *((volatile unsigned int *)LED_ADDRESS) = state; - } - } - - return IRQ_HANDLED; -} - -static struct irqaction clps7500_timer_irq = { - .name = "CLPS7500 Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = clps7500_timer_interrupt, -}; - -/* - * Set up timer interrupt. - */ -static void __init clps7500_timer_init(void) -{ - ioctime_init(); - setup_irq(IRQ_TIMER, &clps7500_timer_irq); -} - -static struct sys_timer clps7500_timer = { - .init = clps7500_timer_init, - .offset = ioc_timer_gettimeoffset, -}; - -static struct plat_serial8250_port serial_platform_data[] = { - { - .mapbase = 0x03010fe0, - .irq = 10, - .uartclk = 1843200, - .regshift = 2, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST, - }, - { - .mapbase = 0x03010be0, - .irq = 0, - .uartclk = 1843200, - .regshift = 2, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST, - }, - { - .iobase = ISASLOT_IO + 0x2e8, - .irq = 41, - .uartclk = 1843200, - .regshift = 0, - .iotype = UPIO_PORT, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - { - .iobase = ISASLOT_IO + 0x3e8, - .irq = 40, - .uartclk = 1843200, - .regshift = 0, - .iotype = UPIO_PORT, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - { }, -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data, - }, -}; - -static void __init clps7500_init(void) -{ - platform_device_register(&serial_device); -} - -MACHINE_START(CLPS7500, "CL-PS7500") - /* Maintainer: Philip Blundell */ - .phys_io = 0x03000000, - .io_pg_offst = ((0xe0000000) >> 18) & 0xfffc, - .map_io = clps7500_map_io, - .init_irq = clps7500_init_irq, - .init_machine = clps7500_init, - .timer = &clps7500_timer, -MACHINE_END - diff --git a/arch/arm/mach-clps7500/include/mach/acornfb.h b/arch/arm/mach-clps7500/include/mach/acornfb.h deleted file mode 100644 index aea6330..0000000 --- a/arch/arm/mach-clps7500/include/mach/acornfb.h +++ /dev/null @@ -1,33 +0,0 @@ -#define acornfb_valid_pixrate(var) (var->pixclock >= 39325 && var->pixclock <= 40119) - -static inline void -acornfb_vidc20_find_rates(struct vidc_timing *vidc, - struct fb_var_screeninfo *var) -{ - u_int bandwidth; - - vidc->control |= VIDC20_CTRL_PIX_CK; - - /* Calculate bandwidth */ - bandwidth = var->pixclock * 8 / var->bits_per_pixel; - - /* Encode bandwidth as VIDC20 setting */ - if (bandwidth > 16667*2) - vidc->control |= VIDC20_CTRL_FIFO_16; - else if (bandwidth > 13333*2) - vidc->control |= VIDC20_CTRL_FIFO_20; - else if (bandwidth > 11111*2) - vidc->control |= VIDC20_CTRL_FIFO_24; - else - vidc->control |= VIDC20_CTRL_FIFO_28; - - vidc->pll_ctl = 0x2020; -} - -#ifdef CONFIG_CHRONTEL_7003 -#define acornfb_default_control() VIDC20_CTRL_PIX_HCLK -#else -#define acornfb_default_control() VIDC20_CTRL_PIX_VCLK -#endif - -#define acornfb_default_econtrol() VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3) | VIDC20_ECTL_ECK diff --git a/arch/arm/mach-clps7500/include/mach/debug-macro.S b/arch/arm/mach-clps7500/include/mach/debug-macro.S deleted file mode 100644 index af4104e..0000000 --- a/arch/arm/mach-clps7500/include/mach/debug-macro.S +++ /dev/null @@ -1,21 +0,0 @@ -/* arch/arm/mach-clps7500/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart,rx - mov \rx, #0xe0000000 - orr \rx, \rx, #0x00010000 - orr \rx, \rx, #0x00000be0 - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-clps7500/include/mach/dma.h b/arch/arm/mach-clps7500/include/mach/dma.h deleted file mode 100644 index 63fcde5..0000000 --- a/arch/arm/mach-clps7500/include/mach/dma.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-clps7500/include/mach/dma.h - * - * Copyright (C) 1999 Nexus Electronics Ltd. - */ - -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H - -/* DMA is not yet implemented! It should be the same as acorn, copy over.. */ - -/* - * This is the maximum DMA address that can be DMAd to. - * There should not be more than (0xd0000000 - 0xc0000000) - * bytes of RAM. - */ -#define MAX_DMA_ADDRESS 0xd0000000 - -#define DMA_S0 0 - -#endif /* _ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-clps7500/include/mach/entry-macro.S b/arch/arm/mach-clps7500/include/mach/entry-macro.S deleted file mode 100644 index 4e7e541..0000000 --- a/arch/arm/mach-clps7500/include/mach/entry-macro.S +++ /dev/null @@ -1,16 +0,0 @@ -#include <mach/hardware.h> -#include <asm/hardware/entry-macro-iomd.S> - - .equ ioc_base_high, IOC_BASE & 0xff000000 - .equ ioc_base_low, IOC_BASE & 0x00ff0000 - - .macro get_irqnr_preamble, base, tmp - mov \base, #ioc_base_high @ point at IOC - .if ioc_base_low - orr \base, \base, #ioc_base_low - .endif - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - diff --git a/arch/arm/mach-clps7500/include/mach/hardware.h b/arch/arm/mach-clps7500/include/mach/hardware.h deleted file mode 100644 index a6ad1d4..0000000 --- a/arch/arm/mach-clps7500/include/mach/hardware.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * arch/arm/mach-clps7500/include/mach/hardware.h - * - * Copyright (C) 1996-1999 Russell King. - * Copyright (C) 1999 Nexus Electronics Ltd. - * - * This file contains the hardware definitions of the - * CL7500 evaluation board. - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <mach/memory.h> -#include <asm/hardware/iomd.h> - -#ifdef __ASSEMBLY__ -#define IOMEM(x) x -#else -#define IOMEM(x) ((void __iomem *)(x)) -#endif - -/* - * What hardware must be present - */ -#define HAS_IOMD -#define HAS_VIDC20 - -/* Hardware addresses of major areas. - * *_START is the physical address - * *_SIZE is the size of the region - * *_BASE is the virtual address - */ - -#define IO_START 0x03000000 /* I/O */ -#define IO_SIZE 0x01000000 -#define IO_BASE IOMEM(0xe0000000) - -#define ISA_START 0x0c000000 /* ISA */ -#define ISA_SIZE 0x00010000 -#define ISA_BASE 0xe1000000 - -#define CLPS7500_FLASH_START 0x01000000 /* XXX */ -#define CLPS7500_FLASH_SIZE 0x01000000 -#define CLPS7500_FLASH_BASE 0xe2000000 - -#define LED_START 0x0302B000 -#define LED_SIZE 0x00001000 -#define LED_BASE 0xe3000000 -#define LED_ADDRESS (LED_BASE + 0xa00) - -/* Let's define SCREEN_START for CL7500, even though it's a lie. */ -#define SCREEN_START 0x02000000 /* VRAM */ -#define SCREEN_END 0xdfc00000 -#define SCREEN_BASE 0xdf800000 - -#define VIDC_BASE (void __iomem *)0xe0400000 -#define IOMD_BASE IOMEM(0xe0200000) -#define IOC_BASE IOMEM(0xe0200000) -#define FLOPPYDMA_BASE IOMEM(0xe002a000) -#define PCIO_BASE IOMEM(0xe0010000) - -#define vidc_writel(val) __raw_writel(val, VIDC_BASE) - -/* in/out bias for the ISA slot region */ -#define ISASLOT_IO 0x80400000 - -#endif diff --git a/arch/arm/mach-clps7500/include/mach/io.h b/arch/arm/mach-clps7500/include/mach/io.h deleted file mode 100644 index 2ff2860..0000000 --- a/arch/arm/mach-clps7500/include/mach/io.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * arch/arm/mach-clps7500/include/mach/io.h - * from arch/arm/mach-rpc/include/mach/io.h - * - * Copyright (C) 1997 Russell King - * - * Modifications: - * 06-Dec-1997 RMK Created. - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include <mach/hardware.h> - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * GCC is totally crap at loading/storing data. We try to persuade it - * to do the right thing by using these whereever possible instead of - * the above. - */ -#define __arch_base_getb(b,o) \ - ({ \ - unsigned int v, r = (b); \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2]" \ - : "=r" (v) \ - : "r" (r), "Ir" (o)); \ - v; \ - }) - -#define __arch_base_getl(b,o) \ - ({ \ - unsigned int v, r = (b); \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2]" \ - : "=r" (v) \ - : "r" (r), "Ir" (o)); \ - v; \ - }) - -#define __arch_base_putb(v,b,o) \ - ({ \ - unsigned int r = (b); \ - __asm__ __volatile__( \ - "strb %0, [%1, %2]" \ - : \ - : "r" (v), "r" (r), "Ir" (o)); \ - }) - -#define __arch_base_putl(v,b,o) \ - ({ \ - unsigned int r = (b); \ - __asm__ __volatile__( \ - "str %0, [%1, %2]" \ - : \ - : "r" (v), "r" (r), "Ir" (o)); \ - }) - -/* - * We use two different types of addressing - PC style addresses, and ARM - * addresses. PC style accesses the PC hardware with the normal PC IO - * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+ - * and are translated to the start of IO. Note that all addresses are - * shifted left! - */ -#define __PORT_PCIO(x) (!((x) & 0x80000000)) - -/* - * Dynamic IO functions - let the compiler - * optimize the expressions - */ -static inline void __outb (unsigned int value, unsigned int port) -{ - unsigned long temp; - __asm__ __volatile__( - "tst %2, #0x80000000\n\t" - "mov %0, %4\n\t" - "addeq %0, %0, %3\n\t" - "strb %1, [%0, %2, lsl #2] @ outb" - : "=&r" (temp) - : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) - : "cc"); -} - -static inline void __outw (unsigned int value, unsigned int port) -{ - unsigned long temp; - __asm__ __volatile__( - "tst %2, #0x80000000\n\t" - "mov %0, %4\n\t" - "addeq %0, %0, %3\n\t" - "str %1, [%0, %2, lsl #2] @ outw" - : "=&r" (temp) - : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) - : "cc"); -} - -static inline void __outl (unsigned int value, unsigned int port) -{ - unsigned long temp; - __asm__ __volatile__( - "tst %2, #0x80000000\n\t" - "mov %0, %4\n\t" - "addeq %0, %0, %3\n\t" - "str %1, [%0, %2, lsl #2] @ outl" - : "=&r" (temp) - : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) - : "cc"); -} - -#define DECLARE_DYN_IN(sz,fnsuffix,instr) \ -static inline unsigned sz __in##fnsuffix (unsigned int port) \ -{ \ - unsigned long temp, value; \ - __asm__ __volatile__( \ - "tst %2, #0x80000000\n\t" \ - "mov %0, %4\n\t" \ - "addeq %0, %0, %3\n\t" \ - "ldr" instr " %1, [%0, %2, lsl #2] @ in" #fnsuffix \ - : "=&r" (temp), "=r" (value) \ - : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \ - : "cc"); \ - return (unsigned sz)value; \ -} - -static inline unsigned int __ioaddr (unsigned int port) \ -{ \ - if (__PORT_PCIO(port)) \ - return (unsigned int)(PCIO_BASE + (port << 2)); \ - else \ - return (unsigned int)(IO_BASE + (port << 2)); \ -} - -#define DECLARE_IO(sz,fnsuffix,instr) \ - DECLARE_DYN_IN(sz,fnsuffix,instr) - -DECLARE_IO(char,b,"b") -DECLARE_IO(short,w,"") -DECLARE_IO(int,l,"") - -#undef DECLARE_IO -#undef DECLARE_DYN_IN - -/* - * Constant address IO functions - * - * These have to be macros for the 'J' constraint to work - - * +/-4096 immediate operand. - */ -#define __outbc(value,port) \ -({ \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "strb %0, [%1, %2] @ outbc" \ - : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "strb %0, [%1, %2] @ outbc" \ - : : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \ -}) - -#define __inbc(port) \ -({ \ - unsigned char result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2] @ inbc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2] @ inbc" \ - : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ - result; \ -}) - -#define __outwc(value,port) \ -({ \ - unsigned long v = value; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outwc" \ - : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outwc" \ - : : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2)); \ -}) - -#define __inwc(port) \ -({ \ - unsigned short result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inwc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inwc" \ - : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ - result & 0xffff; \ -}) - -#define __outlc(value,port) \ -({ \ - unsigned long v = value; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outlc" \ - : : "r" (v), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outlc" \ - : : "r" (v), "r" (IO_BASE), "r" ((port) << 2)); \ -}) - -#define __inlc(port) \ -({ \ - unsigned long result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inlc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ - else \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inlc" \ - : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ - result; \ -}) - -#define __ioaddrc(port) \ - (__PORT_PCIO((port)) ? PCIO_BASE + ((port) << 2) : IO_BASE + ((port) << 2)) - -#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) -#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) -#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) -#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) -#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) -#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) -#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) -/* the following macro is deprecated */ -#define ioaddr(port) __ioaddr((port)) - -#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) -#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) - -#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l) -#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l) - -/* - * 1:1 mapping for ioremapped regions. - */ -#define __mem_pci(x) (x) - -#endif diff --git a/arch/arm/mach-clps7500/include/mach/irq.h b/arch/arm/mach-clps7500/include/mach/irq.h deleted file mode 100644 index d02fcf2..0000000 --- a/arch/arm/mach-clps7500/include/mach/irq.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-clps7500/include/mach/irq.h - * - * Copyright (C) 1996 Russell King - * Copyright (C) 1999, 2001 Nexus Electronics Ltd. - * - * Changelog: - * 10-10-1996 RMK Brought up to date with arch-sa110eval - * 22-08-1998 RMK Restructured IRQ routines - * 11-08-1999 PJB Created ARM7500 version, derived from RiscPC code - */ - -#include <linux/io.h> -#include <asm/hardware/iomd.h> - -static inline int fixup_irq(unsigned int irq) -{ - if (irq == IRQ_ISA) { - int isabits = *((volatile unsigned int *)0xe002b700); - if (isabits == 0) { - printk("Spurious ISA IRQ!\n"); - return irq; - } - irq = IRQ_ISA_BASE; - while (!(isabits & 1)) { - irq++; - isabits >>= 1; - } - } - - return irq; -} diff --git a/arch/arm/mach-clps7500/include/mach/irqs.h b/arch/arm/mach-clps7500/include/mach/irqs.h deleted file mode 100644 index bee66b4..0000000 --- a/arch/arm/mach-clps7500/include/mach/irqs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * arch/arm/mach-clps7500/include/mach/irqs.h - * - * Copyright (C) 1999 Nexus Electronics Ltd - */ - -#define IRQ_INT2 0 -#define IRQ_INT1 2 -#define IRQ_VSYNCPULSE 3 -#define IRQ_POWERON 4 -#define IRQ_TIMER0 5 -#define IRQ_TIMER1 6 -#define IRQ_FORCE 7 -#define IRQ_INT8 8 -#define IRQ_ISA 9 -#define IRQ_INT6 10 -#define IRQ_INT5 11 -#define IRQ_INT4 12 -#define IRQ_INT3 13 -#define IRQ_KEYBOARDTX 14 -#define IRQ_KEYBOARDRX 15 - -#define IRQ_DMA0 16 -#define IRQ_DMA1 17 -#define IRQ_DMA2 18 -#define IRQ_DMA3 19 -#define IRQ_DMAS0 20 -#define IRQ_DMAS1 21 - -#define IRQ_IOP0 24 -#define IRQ_IOP1 25 -#define IRQ_IOP2 26 -#define IRQ_IOP3 27 -#define IRQ_IOP4 28 -#define IRQ_IOP5 29 -#define IRQ_IOP6 30 -#define IRQ_IOP7 31 - -#define IRQ_MOUSERX 40 -#define IRQ_MOUSETX 41 -#define IRQ_ADC 42 -#define IRQ_EVENT1 43 -#define IRQ_EVENT2 44 - -#define IRQ_ISA_BASE 48 -#define IRQ_ISA_3 48 -#define IRQ_ISA_4 49 -#define IRQ_ISA_5 50 -#define IRQ_ISA_7 51 -#define IRQ_ISA_9 52 -#define IRQ_ISA_10 53 -#define IRQ_ISA_11 54 -#define IRQ_ISA_14 55 - -#define FIQ_INT9 0 -#define FIQ_INT5 1 -#define FIQ_INT6 4 -#define FIQ_INT8 6 -#define FIQ_FORCE 7 - -/* - * This is the offset of the FIQ "IRQ" numbers - */ -#define FIQ_START 64 - -#define IRQ_TIMER IRQ_TIMER0 diff --git a/arch/arm/mach-clps7500/include/mach/memory.h b/arch/arm/mach-clps7500/include/mach/memory.h deleted file mode 100644 index 87b32db..0000000 --- a/arch/arm/mach-clps7500/include/mach/memory.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * arch/arm/mach-clps7500/include/mach/memory.h - * - * Copyright (c) 1996,1997,1998 Russell King. - * - * Changelog: - * 20-Oct-1996 RMK Created - * 31-Dec-1997 RMK Fixed definitions to reduce warnings - * 11-Jan-1998 RMK Uninlined to reduce hits on cache - * 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt - * 21-Mar-1999 RMK Renamed to memory.h - * RMK Added TASK_SIZE and PAGE_OFFSET - */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#define PHYS_OFFSET UL(0x10000000) - -/* - * These are exactly the same on the RiscPC as the - * physical memory view. - */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - -/* - * Cache flushing area - ROM - */ -#define FLUSH_BASE_PHYS 0x00000000 -#define FLUSH_BASE 0xdf000000 - -/* - * Sparsemem support. Each section is a maximum of 64MB. The sections - * are offset by 128MB and can cover 128MB, so that gives us a maximum - * of 29 physmem bits. - */ -#define MAX_PHYSMEM_BITS 29 -#define SECTION_SIZE_BITS 26 - -#endif diff --git a/arch/arm/mach-clps7500/include/mach/system.h b/arch/arm/mach-clps7500/include/mach/system.h deleted file mode 100644 index 6d325fb..0000000 --- a/arch/arm/mach-clps7500/include/mach/system.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * arch/arm/mach-clps7500/include/mach/system.h - * - * Copyright (c) 1999 Nexus Electronics Ltd. - */ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include <linux/io.h> -#include <asm/hardware/iomd.h> - -static inline void arch_idle(void) -{ - iomd_writeb(0, IOMD_SUSMODE); -} - -#define arch_reset(mode) \ - do { \ - iomd_writeb(0, IOMD_ROMCR0); \ - cpu_reset(0); \ - } while (0) - -#endif diff --git a/arch/arm/mach-clps7500/include/mach/timex.h b/arch/arm/mach-clps7500/include/mach/timex.h deleted file mode 100644 index dfaa9b4..0000000 --- a/arch/arm/mach-clps7500/include/mach/timex.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * arch/arm/mach-clps7500/include/mach/timex.h - * - * CL7500 architecture timex specifications - * - * Copyright (C) 1999 Nexus Electronics Ltd - */ - -/* - * On the ARM7500, the clock ticks at 2MHz. - */ -#define CLOCK_TICK_RATE 2000000 - diff --git a/arch/arm/mach-clps7500/include/mach/uncompress.h b/arch/arm/mach-clps7500/include/mach/uncompress.h deleted file mode 100644 index d7d0af4..0000000 --- a/arch/arm/mach-clps7500/include/mach/uncompress.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/mach-clps7500/include/mach/uncompress.h - * - * Copyright (C) 1999, 2000 Nexus Electronics Ltd. - */ -#define BASE 0x03010000 -#define SERBASE (BASE + (0x2f8 << 2)) - -static inline void putc(char c) -{ - while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20)) - barrier(); - - *((volatile unsigned int *)(SERBASE)) = c; -} - -static inline void flush(void) -{ -} - -static __inline__ void arch_decomp_setup(void) -{ - int baud = 3686400 / (9600 * 32); - - *((volatile unsigned int *)(SERBASE + 0xC)) = 0x80; - *((volatile unsigned int *)(SERBASE + 0x0)) = baud & 0xff; - *((volatile unsigned int *)(SERBASE + 0x4)) = (baud & 0xff00) >> 8; - *((volatile unsigned int *)(SERBASE + 0xC)) = 3; /* 8 bits */ - *((volatile unsigned int *)(SERBASE + 0x10)) = 3; /* DTR, RTS */ -} - -/* - * nothing to do - */ -#define arch_decomp_wdog() diff --git a/arch/arm/mach-clps7500/include/mach/vmalloc.h b/arch/arm/mach-clps7500/include/mach/vmalloc.h deleted file mode 100644 index 8fc5406..0000000 --- a/arch/arm/mach-clps7500/include/mach/vmalloc.h +++ /dev/null @@ -1,4 +0,0 @@ -/* - * arch/arm/mach-clps7500/include/mach/vmalloc.h - */ -#define VMALLOC_END (PAGE_OFFSET + 0x1c000000) diff --git a/arch/arm/mach-davinci/include/mach/dma.h b/arch/arm/mach-davinci/include/mach/dma.h deleted file mode 100644 index 8e2f2d0..0000000 --- a/arch/arm/mach-davinci/include/mach/dma.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * DaVinci DMA definitions - * - * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H - -#define MAX_DMA_ADDRESS 0xffffffff - -#endif /* __ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h index b78ee91..a48795f 100644 --- a/arch/arm/mach-davinci/include/mach/io.h +++ b/arch/arm/mach-davinci/include/mach/io.h @@ -29,8 +29,7 @@ * We don't actually have real ISA nor PCI buses, but there is so many * drivers out there that might just work if we fake them... */ -#define PCIO_BASE 0 -#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) +#define __io(a) __typesafe_io(a) #define __mem_pci(a) (a) #define __mem_isa(a) (a) diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index dd1625c..86c25c7 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -52,13 +52,8 @@ __arch_adjust_zones(int node, unsigned long *size, unsigned long *holes) if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes) #define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) +#define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20)) #endif -/* - * Bus address is physical address - */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h index b98bd9e..ad51625 100644 --- a/arch/arm/mach-davinci/include/mach/vmalloc.h +++ b/arch/arm/mach-davinci/include/mach/vmalloc.h @@ -8,7 +8,6 @@ * is licensed "as is" without any warranty of any kind, whether express * or implied. */ -#include <asm/memory.h> #include <mach/io.h> /* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ diff --git a/arch/arm/mach-ebsa110/include/mach/dma.h b/arch/arm/mach-ebsa110/include/mach/dma.h deleted file mode 100644 index 780a04c..0000000 --- a/arch/arm/mach-ebsa110/include/mach/dma.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * arch/arm/mach-ebsa110/include/mach/dma.h - * - * Copyright (C) 1997,1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * EBSA110 DMA definitions - */ diff --git a/arch/arm/mach-ebsa110/include/mach/memory.h b/arch/arm/mach-ebsa110/include/mach/memory.h index eea4b75..0ca66d0 100644 --- a/arch/arm/mach-ebsa110/include/mach/memory.h +++ b/arch/arm/mach-ebsa110/include/mach/memory.h @@ -22,13 +22,6 @@ #define PHYS_OFFSET UL(0x00000000) /* - * We keep this 1:1 so that we don't interfere - * with the PCMCIA memory regions - */ -#define __virt_to_bus(x) (x) -#define __bus_to_virt(x) (x) - -/* * Cache flushing area - SRAM */ #define FLUSH_BASE_PHYS 0x40000000 diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 5a1b8c0..56bddce 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -33,6 +33,12 @@ config MACH_EDB9307 Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9307 Evaluation Board. +config MACH_EDB9307A + bool "Support Cirrus Logic EDB9307A" + help + Say 'Y' here if you want your kernel to support the Cirrus + Logic EDB9307A Evaluation Board. + config MACH_EDB9312 bool "Support Cirrus Logic EDB9312" help diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile index c1252ca..944e42d 100644 --- a/arch/arm/mach-ep93xx/Makefile +++ b/arch/arm/mach-ep93xx/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o obj-$(CONFIG_MACH_EDB9302) += edb9302.o obj-$(CONFIG_MACH_EDB9302A) += edb9302a.o obj-$(CONFIG_MACH_EDB9307) += edb9307.o +obj-$(CONFIG_MACH_EDB9307A) += edb9307a.o obj-$(CONFIG_MACH_EDB9312) += edb9312.o obj-$(CONFIG_MACH_EDB9315) += edb9315.o obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c index 561db73..3fbd9b0 100644 --- a/arch/arm/mach-ep93xx/adssphere.c +++ b/arch/arm/mach-ep93xx/adssphere.c @@ -19,6 +19,7 @@ #include <linux/mtd/physmap.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/i2c.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -28,8 +29,8 @@ static struct physmap_flash_data adssphere_flash_data = { }; static struct resource adssphere_flash_resource = { - .start = 0x60000000, - .end = 0x61ffffff, + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_32M - 1, .flags = IORESOURCE_MEM, }; @@ -59,7 +60,7 @@ MACHINE_START(ADSSPHERE, "ADS Sphere board") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ .phys_io = EP93XX_APB_PHYS_BASE, .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .timer = &ep93xx_timer, diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index 8c9f249..9604928 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c @@ -16,11 +16,12 @@ #include <linux/module.h> #include <linux/string.h> #include <linux/io.h> + +#include <asm/clkdev.h> #include <asm/div64.h> #include <mach/hardware.h> struct clk { - char *name; unsigned long rate; int users; u32 enable_reg; @@ -28,53 +29,33 @@ struct clk { }; static struct clk clk_uart = { - .name = "UARTCLK", .rate = 14745600, }; -static struct clk clk_pll1 = { - .name = "pll1", -}; -static struct clk clk_f = { - .name = "fclk", -}; -static struct clk clk_h = { - .name = "hclk", -}; -static struct clk clk_p = { - .name = "pclk", -}; -static struct clk clk_pll2 = { - .name = "pll2", -}; +static struct clk clk_pll1; +static struct clk clk_f; +static struct clk clk_h; +static struct clk clk_p; +static struct clk clk_pll2; static struct clk clk_usb_host = { - .name = "usb_host", .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, .enable_mask = EP93XX_SYSCON_CLOCK_USH_EN, }; - -static struct clk *clocks[] = { - &clk_uart, - &clk_pll1, - &clk_f, - &clk_h, - &clk_p, - &clk_pll2, - &clk_usb_host, +#define INIT_CK(dev,con,ck) \ + { .dev_id = dev, .con_id = con, .clk = ck } + +static struct clk_lookup clocks[] = { + INIT_CK("apb:uart1", NULL, &clk_uart), + INIT_CK("apb:uart2", NULL, &clk_uart), + INIT_CK("apb:uart3", NULL, &clk_uart), + INIT_CK(NULL, "pll1", &clk_pll1), + INIT_CK(NULL, "fclk", &clk_f), + INIT_CK(NULL, "hclk", &clk_h), + INIT_CK(NULL, "pclk", &clk_p), + INIT_CK(NULL, "pll2", &clk_pll2), + INIT_CK(NULL, "usb_host", &clk_usb_host), }; -struct clk *clk_get(struct device *dev, const char *id) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(clocks); i++) { - if (!strcmp(clocks[i]->name, id)) - return clocks[i]; - } - - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); int clk_enable(struct clk *clk) { @@ -106,12 +87,6 @@ unsigned long clk_get_rate(struct clk *clk) } EXPORT_SYMBOL(clk_get_rate); -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - - static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; @@ -138,6 +113,7 @@ static unsigned long calc_pll_rate(u32 config_word) static int __init ep93xx_clock_init(void) { u32 value; + int i; value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1); if (!(value & 0x00800000)) { /* PLL1 bypassed? */ @@ -165,6 +141,8 @@ static int __init ep93xx_clock_init(void) clk_f.rate / 1000000, clk_h.rate / 1000000, clk_p.rate / 1000000); + for (i = 0; i < ARRAY_SIZE(clocks); i++) + clkdev_add(&clocks[i]); return 0; } arch_initcall(ep93xx_clock_init); diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 48345fb..4781f32 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -34,6 +34,8 @@ #include <linux/amba/bus.h> #include <linux/amba/serial.h> #include <linux/io.h> +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> #include <asm/types.h> #include <asm/setup.h> @@ -153,12 +155,14 @@ static unsigned char gpio_int_unmasked[3]; static unsigned char gpio_int_enabled[3]; static unsigned char gpio_int_type1[3]; static unsigned char gpio_int_type2[3]; +static unsigned char gpio_int_debouce[3]; /* Port ordering is: A B F */ static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c }; static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 }; static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 }; +static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 }; void ep93xx_gpio_update_int_params(unsigned port) { @@ -181,6 +185,22 @@ void ep93xx_gpio_int_mask(unsigned line) gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7)); } +void ep93xx_gpio_int_debounce(unsigned int irq, int enable) +{ + int line = irq_to_gpio(irq); + int port = line >> 3; + int port_mask = 1 << (line & 7); + + if (enable) + gpio_int_debouce[port] |= port_mask; + else + gpio_int_debouce[port] &= ~port_mask; + + __raw_writeb(gpio_int_debouce[port], + EP93XX_GPIO_REG(int_debounce_register_offset[port])); +} +EXPORT_SYMBOL(ep93xx_gpio_int_debounce); + /************************************************************************* * EP93xx IRQ handling *************************************************************************/ @@ -497,6 +517,26 @@ void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr) platform_device_register(&ep93xx_eth_device); } +static struct i2c_gpio_platform_data ep93xx_i2c_data = { + .sda_pin = EP93XX_GPIO_LINE_EEDAT, + .sda_is_open_drain = 0, + .scl_pin = EP93XX_GPIO_LINE_EECLK, + .scl_is_open_drain = 0, + .udelay = 2, +}; + +static struct platform_device ep93xx_i2c_device = { + .name = "i2c-gpio", + .id = 0, + .dev.platform_data = &ep93xx_i2c_data, +}; + +void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num) +{ + i2c_register_board_info(0, devices, num); + platform_device_register(&ep93xx_i2c_device); +} + extern void ep93xx_gpio_init(void); void __init ep93xx_init_devices(void) diff --git a/arch/arm/mach-ep93xx/edb9302.c b/arch/arm/mach-ep93xx/edb9302.c index e4add5b..8bf8d7c 100644 --- a/arch/arm/mach-ep93xx/edb9302.c +++ b/arch/arm/mach-ep93xx/edb9302.c @@ -19,6 +19,7 @@ #include <linux/mtd/physmap.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/i2c.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -28,8 +29,8 @@ static struct physmap_flash_data edb9302_flash_data = { }; static struct resource edb9302_flash_resource = { - .start = 0x60000000, - .end = 0x60ffffff, + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1, .flags = IORESOURCE_MEM, }; @@ -59,7 +60,7 @@ MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board") /* Maintainer: George Kashperko <george@chas.com.ua> */ .phys_io = EP93XX_APB_PHYS_BASE, .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .timer = &ep93xx_timer, diff --git a/arch/arm/mach-ep93xx/edb9302a.c b/arch/arm/mach-ep93xx/edb9302a.c index 02c4405..a352c57 100644 --- a/arch/arm/mach-ep93xx/edb9302a.c +++ b/arch/arm/mach-ep93xx/edb9302a.c @@ -19,6 +19,7 @@ #include <linux/mtd/physmap.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/i2c.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -28,8 +29,8 @@ static struct physmap_flash_data edb9302a_flash_data = { }; static struct resource edb9302a_flash_resource = { - .start = 0x60000000, - .end = 0x60ffffff, + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1, .flags = IORESOURCE_MEM, }; @@ -44,7 +45,7 @@ static struct platform_device edb9302a_flash = { }; static struct ep93xx_eth_data edb9302a_eth_data = { - .phy_id = 1, + .phy_id = 1, }; static void __init edb9302a_init_machine(void) @@ -59,7 +60,7 @@ MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ .phys_io = EP93XX_APB_PHYS_BASE, .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0xc0000100, + .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .timer = &ep93xx_timer, diff --git a/arch/arm/mach-ep93xx/edb9307.c b/arch/arm/mach-ep93xx/edb9307.c index 040edbd..5ab22f6 100644 --- a/arch/arm/mach-ep93xx/edb9307.c +++ b/arch/arm/mach-ep93xx/edb9307.c @@ -19,6 +19,7 @@ #include <linux/mtd/physmap.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/i2c.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -28,8 +29,8 @@ static struct physmap_flash_data edb9307_flash_data = { }; static struct resource edb9307_flash_resource = { - .start = 0x60000000, - .end = 0x61ffffff, + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_32M - 1, .flags = IORESOURCE_MEM, }; @@ -44,7 +45,7 @@ static struct platform_device edb9307_flash = { }; static struct ep93xx_eth_data edb9307_eth_data = { - .phy_id = 1, + .phy_id = 1, }; static void __init edb9307_init_machine(void) @@ -59,7 +60,7 @@ MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ .phys_io = EP93XX_APB_PHYS_BASE, .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .timer = &ep93xx_timer, diff --git a/arch/arm/mach-ep93xx/edb9307a.c b/arch/arm/mach-ep93xx/edb9307a.c new file mode 100644 index 0000000..5b5c22b --- /dev/null +++ b/arch/arm/mach-ep93xx/edb9307a.c @@ -0,0 +1,68 @@ +/* + * arch/arm/mach-ep93xx/edb9307a.c + * Cirrus Logic EDB9307A support. + * + * Copyright (C) 2008 H Hartley Sweeten <hsweeten@visionengravers.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/mtd/physmap.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/i2c.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +static struct physmap_flash_data edb9307a_flash_data = { + .width = 2, +}; + +static struct resource edb9307a_flash_resource = { + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device edb9307a_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &edb9307a_flash_data, + }, + .num_resources = 1, + .resource = &edb9307a_flash_resource, +}; + +static struct ep93xx_eth_data edb9307a_eth_data = { + .phy_id = 1, +}; + +static void __init edb9307a_init_machine(void) +{ + ep93xx_init_devices(); + platform_device_register(&edb9307a_flash); + + ep93xx_register_eth(&edb9307a_eth_data, 1); +} + +MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") + /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = edb9307a_init_machine, +MACHINE_END diff --git a/arch/arm/mach-ep93xx/edb9312.c b/arch/arm/mach-ep93xx/edb9312.c index 6853e30..d7179f6 100644 --- a/arch/arm/mach-ep93xx/edb9312.c +++ b/arch/arm/mach-ep93xx/edb9312.c @@ -20,6 +20,7 @@ #include <linux/mtd/physmap.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/i2c.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -29,8 +30,8 @@ static struct physmap_flash_data edb9312_flash_data = { }; static struct resource edb9312_flash_resource = { - .start = 0x60000000, - .end = 0x61ffffff, + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_32M - 1, .flags = IORESOURCE_MEM, }; @@ -45,7 +46,7 @@ static struct platform_device edb9312_flash = { }; static struct ep93xx_eth_data edb9312_eth_data = { - .phy_id = 1, + .phy_id = 1, }; static void __init edb9312_init_machine(void) @@ -60,7 +61,7 @@ MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board") /* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */ .phys_io = EP93XX_APB_PHYS_BASE, .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .timer = &ep93xx_timer, diff --git a/arch/arm/mach-ep93xx/edb9315.c b/arch/arm/mach-ep93xx/edb9315.c index 9469b35..025af6e 100644 --- a/arch/arm/mach-ep93xx/edb9315.c +++ b/arch/arm/mach-ep93xx/edb9315.c @@ -19,6 +19,7 @@ #include <linux/mtd/physmap.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/i2c.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -28,8 +29,8 @@ static struct physmap_flash_data edb9315_flash_data = { }; static struct resource edb9315_flash_resource = { - .start = 0x60000000, - .end = 0x61ffffff, + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_32M - 1, .flags = IORESOURCE_MEM, }; @@ -44,7 +45,7 @@ static struct platform_device edb9315_flash = { }; static struct ep93xx_eth_data edb9315_eth_data = { - .phy_id = 1, + .phy_id = 1, }; static void __init edb9315_init_machine(void) @@ -59,7 +60,7 @@ MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ .phys_io = EP93XX_APB_PHYS_BASE, .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .timer = &ep93xx_timer, diff --git a/arch/arm/mach-ep93xx/edb9315a.c b/arch/arm/mach-ep93xx/edb9315a.c index 584457c..4c9cc8a 100644 --- a/arch/arm/mach-ep93xx/edb9315a.c +++ b/arch/arm/mach-ep93xx/edb9315a.c @@ -19,6 +19,7 @@ #include <linux/mtd/physmap.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/i2c.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -28,8 +29,8 @@ static struct physmap_flash_data edb9315a_flash_data = { }; static struct resource edb9315a_flash_resource = { - .start = 0x60000000, - .end = 0x60ffffff, + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_16M - 1, .flags = IORESOURCE_MEM, }; @@ -44,7 +45,7 @@ static struct platform_device edb9315a_flash = { }; static struct ep93xx_eth_data edb9315a_eth_data = { - .phy_id = 1, + .phy_id = 1, }; static void __init edb9315a_init_machine(void) @@ -59,7 +60,7 @@ MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ .phys_io = EP93XX_APB_PHYS_BASE, .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0xc0000100, + .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .timer = &ep93xx_timer, diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c index 035b24e..3bad500 100644 --- a/arch/arm/mach-ep93xx/gesbc9312.c +++ b/arch/arm/mach-ep93xx/gesbc9312.c @@ -19,6 +19,7 @@ #include <linux/mtd/physmap.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/i2c.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -28,8 +29,8 @@ static struct physmap_flash_data gesbc9312_flash_data = { }; static struct resource gesbc9312_flash_resource = { - .start = 0x60000000, - .end = 0x607fffff, + .start = EP93XX_CS6_PHYS_BASE, + .end = EP93XX_CS6_PHYS_BASE + SZ_8M - 1, .flags = IORESOURCE_MEM, }; @@ -59,7 +60,7 @@ MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ .phys_io = EP93XX_APB_PHYS_BASE, .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, .map_io = ep93xx_map_io, .init_irq = ep93xx_init_irq, .timer = &ep93xx_timer, diff --git a/arch/arm/mach-ep93xx/include/mach/clkdev.h b/arch/arm/mach-ep93xx/include/mach/clkdev.h new file mode 100644 index 0000000..04b37a8 --- /dev/null +++ b/arch/arm/mach-ep93xx/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h deleted file mode 100644 index d0fa965..0000000 --- a/arch/arm/mach-ep93xx/include/mach/dma.h +++ /dev/null @@ -1,3 +0,0 @@ -/* - * arch/arm/mach-ep93xx/include/mach/dma.h - */ diff --git a/arch/arm/mach-ep93xx/include/mach/gpio.h b/arch/arm/mach-ep93xx/include/mach/gpio.h index f702041..0a1498a 100644 --- a/arch/arm/mach-ep93xx/include/mach/gpio.h +++ b/arch/arm/mach-ep93xx/include/mach/gpio.h @@ -99,6 +99,8 @@ /* maximum value for irq capable line identifiers */ #define EP93XX_GPIO_LINE_MAX_IRQ EP93XX_GPIO_LINE_F(7) +extern void ep93xx_gpio_int_debounce(unsigned int irq, int enable); + /* new generic GPIO API - see Documentation/gpio.txt */ #include <asm-generic/gpio.h> diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h index 1ab9a90..fd5f081 100644 --- a/arch/arm/mach-ep93xx/include/mach/io.h +++ b/arch/arm/mach-ep93xx/include/mach/io.h @@ -4,5 +4,5 @@ #define IO_SPACE_LIMIT 0xffffffff -#define __io(p) ((void __iomem *)(p)) -#define __mem_pci(p) (p) +#define __io(p) __typesafe_io(p) +#define __mem_pci(p) (p) diff --git a/arch/arm/mach-ep93xx/include/mach/memory.h b/arch/arm/mach-ep93xx/include/mach/memory.h index f1b6335..5c80c3c 100644 --- a/arch/arm/mach-ep93xx/include/mach/memory.h +++ b/arch/arm/mach-ep93xx/include/mach/memory.h @@ -7,8 +7,4 @@ #define PHYS_OFFSET UL(0x00000000) -#define __bus_to_virt(x) __phys_to_virt(x) -#define __virt_to_bus(x) __virt_to_phys(x) - - #endif diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h index db2489d..88f7e88 100644 --- a/arch/arm/mach-ep93xx/include/mach/platform.h +++ b/arch/arm/mach-ep93xx/include/mach/platform.h @@ -14,6 +14,7 @@ void ep93xx_map_io(void); void ep93xx_init_irq(void); void ep93xx_init_time(unsigned long); void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr); +void ep93xx_register_i2c(struct i2c_board_info *devices, int num); void ep93xx_init_devices(void); extern struct sys_timer ep93xx_timer; diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c index c219723..15d6815 100644 --- a/arch/arm/mach-ep93xx/micro9.c +++ b/arch/arm/mach-ep93xx/micro9.c @@ -17,6 +17,7 @@ #include <linux/platform_device.h> #include <linux/sched.h> #include <linux/io.h> +#include <linux/i2c.h> #include <linux/mtd/physmap.h> #include <mach/hardware.h> @@ -25,7 +26,7 @@ #include <asm/mach-types.h> static struct ep93xx_eth_data micro9_eth_data = { - .phy_id = 0x1f, + .phy_id = 0x1f, }; static void __init micro9_init(void) @@ -38,46 +39,46 @@ static void __init micro9_init(void) */ #ifdef CONFIG_MACH_MICRO9H static struct physmap_flash_data micro9h_flash_data = { - .width = 4, + .width = 4, }; static struct resource micro9h_flash_resource = { - .start = 0x10000000, - .end = 0x13ffffff, - .flags = IORESOURCE_MEM, + .start = EP93XX_CS1_PHYS_BASE, + .end = EP93XX_CS1_PHYS_BASE + SZ_64M - 1, + .flags = IORESOURCE_MEM, }; static struct platform_device micro9h_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = µ9h_flash_data, - }, - .num_resources = 1, - .resource = µ9h_flash_resource, + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = µ9h_flash_data, + }, + .num_resources = 1, + .resource = µ9h_flash_resource, }; static void __init micro9h_init(void) { - platform_device_register(µ9h_flash); + platform_device_register(µ9h_flash); } static void __init micro9h_init_machine(void) { - ep93xx_init_devices(); - micro9_init(); - micro9h_init(); + ep93xx_init_devices(); + micro9_init(); + micro9h_init(); } MACHINE_START(MICRO9, "Contec Hypercontrol Micro9-H") - /* Maintainer: Manfred Gruber <manfred.gruber@contec.at> */ - .phys_io = EP93XX_APB_PHYS_BASE, - .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .timer = &ep93xx_timer, - .init_machine = micro9h_init_machine, + /* Maintainer: Manfred Gruber <manfred.gruber@contec.at> */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = micro9h_init_machine, MACHINE_END #endif @@ -87,19 +88,19 @@ MACHINE_END #ifdef CONFIG_MACH_MICRO9M static void __init micro9m_init_machine(void) { - ep93xx_init_devices(); - micro9_init(); + ep93xx_init_devices(); + micro9_init(); } MACHINE_START(MICRO9M, "Contec Hypercontrol Micro9-M") - /* Maintainer: Manfred Gruber <manfred.gruber@contec.at> */ - .phys_io = EP93XX_APB_PHYS_BASE, - .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .timer = &ep93xx_timer, - .init_machine = micro9m_init_machine, + /* Maintainer: Manfred Gruber <manfred.gruber@contec.at> */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = micro9m_init_machine, MACHINE_END #endif @@ -109,19 +110,19 @@ MACHINE_END #ifdef CONFIG_MACH_MICRO9L static void __init micro9l_init_machine(void) { - ep93xx_init_devices(); - micro9_init(); + ep93xx_init_devices(); + micro9_init(); } MACHINE_START(MICRO9L, "Contec Hypercontrol Micro9-L") - /* Maintainer: Manfred Gruber <manfred.gruber@contec.at> */ - .phys_io = EP93XX_APB_PHYS_BASE, - .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .timer = &ep93xx_timer, - .init_machine = micro9l_init_machine, + /* Maintainer: Manfred Gruber <manfred.gruber@contec.at> */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = micro9l_init_machine, MACHINE_END #endif diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index b4aa4c0..7ee024d 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -20,6 +20,7 @@ #include <linux/platform_device.h> #include <linux/m48t86.h> #include <linux/io.h> +#include <linux/i2c.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -117,7 +118,7 @@ static struct physmap_flash_data ts72xx_flash_data = { static struct resource ts72xx_flash_resource = { .start = TS72XX_NOR_PHYS_BASE, - .end = TS72XX_NOR_PHYS_BASE + 0x00ffffff, + .end = TS72XX_NOR_PHYS_BASE + SZ_16M - 1, .flags = IORESOURCE_MEM, }; @@ -144,21 +145,21 @@ static void ts72xx_rtc_writebyte(unsigned char value, unsigned long addr) } static struct m48t86_ops ts72xx_rtc_ops = { - .readbyte = ts72xx_rtc_readbyte, - .writebyte = ts72xx_rtc_writebyte, + .readbyte = ts72xx_rtc_readbyte, + .writebyte = ts72xx_rtc_writebyte, }; static struct platform_device ts72xx_rtc_device = { - .name = "rtc-m48t86", - .id = -1, - .dev = { - .platform_data = &ts72xx_rtc_ops, + .name = "rtc-m48t86", + .id = -1, + .dev = { + .platform_data = &ts72xx_rtc_ops, }, - .num_resources = 0, + .num_resources = 0, }; static struct ep93xx_eth_data ts72xx_eth_data = { - .phy_id = 1, + .phy_id = 1, }; static void __init ts72xx_init_machine(void) @@ -175,7 +176,7 @@ MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ .phys_io = EP93XX_APB_PHYS_BASE, .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, + .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, .map_io = ts72xx_map_io, .init_irq = ep93xx_init_irq, .timer = &ep93xx_timer, diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c index 6a5b437..1b996b2 100644 --- a/arch/arm/mach-footbridge/cats-hw.c +++ b/arch/arm/mach-footbridge/cats-hw.c @@ -10,6 +10,7 @@ #include <linux/init.h> #include <linux/screen_info.h> #include <linux/io.h> +#include <linux/spinlock.h> #include <asm/hardware/dec21285.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 818014e..36ff06d 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -14,6 +14,7 @@ #include <linux/list.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/spinlock.h> #include <asm/pgtable.h> #include <asm/page.h> diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index b2a2118..da35bc5 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c @@ -7,6 +7,7 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/spinlock.h> #include <asm/irq.h> diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c index d4c1e52..1330860 100644 --- a/arch/arm/mach-footbridge/dc21285.c +++ b/arch/arm/mach-footbridge/dc21285.c @@ -17,6 +17,7 @@ #include <linux/ioport.h> #include <linux/irq.h> #include <linux/io.h> +#include <linux/spinlock.h> #include <asm/irq.h> #include <asm/system.h> diff --git a/arch/arm/mach-footbridge/dma.c b/arch/arm/mach-footbridge/dma.c index b653e9c..4f35063 100644 --- a/arch/arm/mach-footbridge/dma.c +++ b/arch/arm/mach-footbridge/dma.c @@ -12,6 +12,7 @@ */ #include <linux/init.h> #include <linux/io.h> +#include <linux/spinlock.h> #include <asm/dma.h> #include <asm/scatterlist.h> diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c index b1d3bf2..30040fd 100644 --- a/arch/arm/mach-footbridge/ebsa285.c +++ b/arch/arm/mach-footbridge/ebsa285.c @@ -4,6 +4,7 @@ * EBSA285 machine fixup */ #include <linux/init.h> +#include <linux/spinlock.h> #include <asm/hardware/dec21285.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h index ffaea90..51dd902 100644 --- a/arch/arm/mach-footbridge/include/mach/hardware.h +++ b/arch/arm/mach-footbridge/include/mach/hardware.h @@ -12,8 +12,6 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H -#include <mach/memory.h> - /* Virtual Physical Size * 0xff800000 0x40000000 1MB X-Bus * 0xff000000 0x7c000000 1MB PCI I/O space @@ -28,9 +26,6 @@ #define XBUS_SIZE 0x00100000 #define XBUS_BASE 0xff800000 -#define PCIO_SIZE 0x00100000 -#define PCIO_BASE 0xff000000 - #define ARMCSR_SIZE 0x00100000 #define ARMCSR_BASE 0xfe000000 @@ -91,10 +86,11 @@ #define CPLD_FLASH_WR_ENABLE 1 #ifndef __ASSEMBLY__ -extern void gpio_modify_op(int mask, int set); -extern void gpio_modify_io(int mask, int in); -extern int gpio_read(void); -extern void cpld_modify(int mask, int set); +extern spinlock_t nw_gpio_lock; +extern void nw_gpio_modify_op(unsigned int mask, unsigned int set); +extern void nw_gpio_modify_io(unsigned int mask, unsigned int in); +extern unsigned int nw_gpio_read(void); +extern void nw_cpld_modify(unsigned int mask, unsigned int set); #endif #define pcibios_assign_all_busses() 1 diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h index a7b0662..101a4fe 100644 --- a/arch/arm/mach-footbridge/include/mach/io.h +++ b/arch/arm/mach-footbridge/include/mach/io.h @@ -14,7 +14,8 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#include <mach/hardware.h> +#define PCIO_SIZE 0x00100000 +#define PCIO_BASE 0xff000000 #define IO_SPACE_LIMIT 0xffff diff --git a/arch/arm/mach-footbridge/include/mach/dma.h b/arch/arm/mach-footbridge/include/mach/isa-dma.h index 62afd21..5bd4a0d 100644 --- a/arch/arm/mach-footbridge/include/mach/dma.h +++ b/arch/arm/mach-footbridge/include/mach/isa-dma.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-footbridge/include/mach/dma.h + * arch/arm/mach-footbridge/include/mach/isa-dma.h * * Architecture DMA routines * diff --git a/arch/arm/mach-footbridge/include/mach/memory.h b/arch/arm/mach-footbridge/include/mach/memory.h index 6ae2f1a..cb16e59 100644 --- a/arch/arm/mach-footbridge/include/mach/memory.h +++ b/arch/arm/mach-footbridge/include/mach/memory.h @@ -30,9 +30,18 @@ extern unsigned long __virt_to_bus(unsigned long); extern unsigned long __bus_to_virt(unsigned long); #endif +#define __virt_to_bus __virt_to_bus +#define __bus_to_virt __bus_to_virt #elif defined(CONFIG_FOOTBRIDGE_HOST) +/* + * The footbridge is programmed to expose the system RAM at the corresponding + * address. So, if PAGE_OFFSET is 0xc0000000, RAM appears at 0xe0000000. + * If 0x80000000, then its exposed at 0xa0000000 on the bus. etc. + * The only requirement is that the RAM isn't placed at bus address 0 which + * would clash with VGA cards. + */ #define __virt_to_bus(x) ((x) - 0xe0000000) #define __bus_to_virt(x) ((x) + 0xe0000000) diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c index 54fec9a..9ee80a2 100644 --- a/arch/arm/mach-footbridge/isa-irq.c +++ b/arch/arm/mach-footbridge/isa-irq.c @@ -19,6 +19,7 @@ #include <linux/list.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/spinlock.h> #include <asm/mach/irq.h> diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c index 00b0ddc..ac7ffa6 100644 --- a/arch/arm/mach-footbridge/netwinder-hw.c +++ b/arch/arm/mach-footbridge/netwinder-hw.c @@ -11,6 +11,7 @@ #include <linux/delay.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/spinlock.h> #include <asm/hardware/dec21285.h> #include <asm/leds.h> @@ -67,13 +68,14 @@ static inline void wb977_ww(int reg, int val) /* * This is a lock for accessing ports GP1_IO_BASE and GP2_IO_BASE */ -DEFINE_SPINLOCK(gpio_lock); +DEFINE_SPINLOCK(nw_gpio_lock); +EXPORT_SYMBOL(nw_gpio_lock); static unsigned int current_gpio_op; static unsigned int current_gpio_io; static unsigned int current_cpld; -void gpio_modify_op(int mask, int set) +void nw_gpio_modify_op(unsigned int mask, unsigned int set) { unsigned int new_gpio, changed; @@ -86,6 +88,7 @@ void gpio_modify_op(int mask, int set) if (changed & 0xff00) outb(new_gpio >> 8, GP2_IO_BASE); } +EXPORT_SYMBOL(nw_gpio_modify_op); static inline void __gpio_modify_io(int mask, int in) { @@ -118,7 +121,7 @@ static inline void __gpio_modify_io(int mask, int in) } } -void gpio_modify_io(int mask, int in) +void nw_gpio_modify_io(unsigned int mask, unsigned int in) { /* Open up the SuperIO chip */ wb977_open(); @@ -128,11 +131,13 @@ void gpio_modify_io(int mask, int in) /* Close up the EFER gate */ wb977_close(); } +EXPORT_SYMBOL(nw_gpio_modify_io); -int gpio_read(void) +unsigned int nw_gpio_read(void) { return inb(GP1_IO_BASE) | inb(GP2_IO_BASE) << 8; } +EXPORT_SYMBOL(nw_gpio_read); /* * Initialise the Winbond W83977F global registers @@ -322,9 +327,9 @@ static inline void wb977_init_gpio(void) /* * Set Group1/Group2 outputs */ - spin_lock_irqsave(&gpio_lock, flags); - gpio_modify_op(-1, GPIO_RED_LED | GPIO_FAN); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_gpio_modify_op(-1, GPIO_RED_LED | GPIO_FAN); + spin_unlock_irqrestore(&nw_gpio_lock, flags); } /* @@ -359,34 +364,35 @@ static void __init wb977_init(void) wb977_close(); } -void cpld_modify(int mask, int set) +void nw_cpld_modify(unsigned int mask, unsigned int set) { int msk; current_cpld = (current_cpld & ~mask) | set; - gpio_modify_io(GPIO_DATA | GPIO_IOCLK | GPIO_IOLOAD, 0); - gpio_modify_op(GPIO_IOLOAD, 0); + nw_gpio_modify_io(GPIO_DATA | GPIO_IOCLK | GPIO_IOLOAD, 0); + nw_gpio_modify_op(GPIO_IOLOAD, 0); for (msk = 8; msk; msk >>= 1) { int bit = current_cpld & msk; - gpio_modify_op(GPIO_DATA | GPIO_IOCLK, bit ? GPIO_DATA : 0); - gpio_modify_op(GPIO_IOCLK, GPIO_IOCLK); + nw_gpio_modify_op(GPIO_DATA | GPIO_IOCLK, bit ? GPIO_DATA : 0); + nw_gpio_modify_op(GPIO_IOCLK, GPIO_IOCLK); } - gpio_modify_op(GPIO_IOCLK|GPIO_DATA, 0); - gpio_modify_op(GPIO_IOLOAD|GPIO_DSCLK, GPIO_IOLOAD|GPIO_DSCLK); - gpio_modify_op(GPIO_IOLOAD, 0); + nw_gpio_modify_op(GPIO_IOCLK|GPIO_DATA, 0); + nw_gpio_modify_op(GPIO_IOLOAD|GPIO_DSCLK, GPIO_IOLOAD|GPIO_DSCLK); + nw_gpio_modify_op(GPIO_IOLOAD, 0); } +EXPORT_SYMBOL(nw_cpld_modify); static void __init cpld_init(void) { unsigned long flags; - spin_lock_irqsave(&gpio_lock, flags); - cpld_modify(-1, CPLD_UNMUTE | CPLD_7111_DISABLE); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_cpld_modify(-1, CPLD_UNMUTE | CPLD_7111_DISABLE); + spin_unlock_irqrestore(&nw_gpio_lock, flags); } static unsigned char rwa_unlock[] __initdata = @@ -596,12 +602,6 @@ static void __init rwa010_init(void) rwa010_soundblaster_reset(); } -EXPORT_SYMBOL(gpio_lock); -EXPORT_SYMBOL(gpio_modify_op); -EXPORT_SYMBOL(gpio_modify_io); -EXPORT_SYMBOL(cpld_modify); -EXPORT_SYMBOL(gpio_read); - /* * Initialise any other hardware after we've got the PCI bus * initialised. We may need the PCI bus to talk to this other @@ -616,9 +616,9 @@ static int __init nw_hw_init(void) cpld_init(); rwa010_init(); - spin_lock_irqsave(&gpio_lock, flags); - gpio_modify_op(GPIO_RED_LED|GPIO_GREEN_LED, DEFAULT_LEDS); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_gpio_modify_op(GPIO_RED_LED|GPIO_GREEN_LED, DEFAULT_LEDS); + spin_unlock_irqrestore(&nw_gpio_lock, flags); } return 0; } diff --git a/arch/arm/mach-footbridge/netwinder-leds.c b/arch/arm/mach-footbridge/netwinder-leds.c index d91a4f4..00269fe 100644 --- a/arch/arm/mach-footbridge/netwinder-leds.c +++ b/arch/arm/mach-footbridge/netwinder-leds.c @@ -32,7 +32,6 @@ static char led_state; static char hw_led_state; static DEFINE_SPINLOCK(leds_lock); -extern spinlock_t gpio_lock; static void netwinder_leds_event(led_event_t evt) { @@ -121,9 +120,9 @@ static void netwinder_leds_event(led_event_t evt) spin_unlock_irqrestore(&leds_lock, flags); if (led_state & LED_STATE_ENABLED) { - spin_lock_irqsave(&gpio_lock, flags); - gpio_modify_op(GPIO_RED_LED | GPIO_GREEN_LED, hw_led_state); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_gpio_modify_op(GPIO_RED_LED | GPIO_GREEN_LED, hw_led_state); + spin_unlock_irqrestore(&nw_gpio_lock, flags); } } diff --git a/arch/arm/mach-footbridge/personal.c b/arch/arm/mach-footbridge/personal.c index c4f843f..e2c9f06 100644 --- a/arch/arm/mach-footbridge/personal.c +++ b/arch/arm/mach-footbridge/personal.c @@ -4,6 +4,7 @@ * Personal server (Skiff) machine fixup */ #include <linux/init.h> +#include <linux/spinlock.h> #include <asm/hardware/dec21285.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-h720x/include/mach/io.h b/arch/arm/mach-h720x/include/mach/io.h index 1dab74c..2c8659c 100644 --- a/arch/arm/mach-h720x/include/mach/io.h +++ b/arch/arm/mach-h720x/include/mach/io.h @@ -14,11 +14,9 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#include <mach/hardware.h> - #define IO_SPACE_LIMIT 0xffffffff -#define __io(a) ((void __iomem *)(a)) +#define __io(a) __typesafe_io(a) #define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-h720x/include/mach/dma.h b/arch/arm/mach-h720x/include/mach/isa-dma.h index 0a9d86e..3eafb3f 100644 --- a/arch/arm/mach-h720x/include/mach/dma.h +++ b/arch/arm/mach-h720x/include/mach/isa-dma.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-h720x/include/mach/dma.h + * arch/arm/mach-h720x/include/mach/isa-dma.h * * Architecture DMA routes * @@ -8,13 +8,6 @@ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H -/* - * This is the maximum DMA address that can be DMAd to. - * There should not be more than (0xd0000000 - 0xc0000000) - * bytes of RAM. - */ -#define MAX_DMA_ADDRESS 0xd0000000 - #if defined (CONFIG_CPU_H7201) #define MAX_DMA_CHANNELS 3 #elif defined (CONFIG_CPU_H7202) diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h index cb26f49..ef4c1e2 100644 --- a/arch/arm/mach-h720x/include/mach/memory.h +++ b/arch/arm/mach-h720x/include/mach/memory.h @@ -7,23 +7,13 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -/* - * Page offset: - * ( 0xc0000000UL ) - */ #define PHYS_OFFSET UL(0x40000000) - /* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - * - * There is something to do here later !, Mar 2000, Jungjun Kim + * This is the maximum DMA address that can be DMAd to. + * There should not be more than (0xd0000000 - 0xc0000000) + * bytes of RAM. */ - -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) +#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) #endif diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c index c10810c..1536583 100644 --- a/arch/arm/mach-imx/dma.c +++ b/arch/arm/mach-imx/dma.c @@ -28,10 +28,11 @@ #include <linux/interrupt.h> #include <linux/errno.h> +#include <asm/scatterlist.h> #include <asm/system.h> #include <asm/irq.h> #include <mach/hardware.h> -#include <asm/dma.h> +#include <mach/dma.h> #include <mach/imx-dma.h> struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; @@ -138,7 +139,7 @@ imx_dma_setup_sg_base(imx_dmach_t dma_ch, int imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, unsigned int dma_length, unsigned int dev_addr, - dmamode_t dmamode) + unsigned int dmamode) { struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; @@ -223,7 +224,7 @@ imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, int imx_dma_setup_sg(imx_dmach_t dma_ch, struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, - unsigned int dev_addr, dmamode_t dmamode) + unsigned int dev_addr, unsigned int dmamode) { int res; struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; diff --git a/arch/arm/mach-imx/include/mach/imx-dma.h b/arch/arm/mach-imx/include/mach/imx-dma.h index 44d89c3..bbe54df 100644 --- a/arch/arm/mach-imx/include/mach/imx-dma.h +++ b/arch/arm/mach-imx/include/mach/imx-dma.h @@ -18,7 +18,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include <asm/dma.h> +#include <mach/dma.h> #ifndef __ASM_ARCH_IMX_DMA_H #define __ASM_ARCH_IMX_DMA_H @@ -48,7 +48,7 @@ struct imx_dma_channel { void (*irq_handler) (int, void *); void (*err_handler) (int, void *, int errcode); void *data; - dmamode_t dma_mode; + unsigned int dma_mode; struct scatterlist *sg; unsigned int sgbc; unsigned int sgcount; @@ -66,14 +66,18 @@ extern struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; /* The type to distinguish channel numbers parameter from ordinal int type */ typedef int imx_dmach_t; +#define DMA_MODE_READ 0 +#define DMA_MODE_WRITE 1 +#define DMA_MODE_MASK 1 + int imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, - unsigned int dma_length, unsigned int dev_addr, dmamode_t dmamode); + unsigned int dma_length, unsigned int dev_addr, unsigned int dmamode); int imx_dma_setup_sg(imx_dmach_t dma_ch, struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, - unsigned int dev_addr, dmamode_t dmamode); + unsigned int dev_addr, unsigned int dmamode); int imx_dma_setup_handlers(imx_dmach_t dma_ch, diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/mach-imx/include/mach/imxfb.h index 3ed9ec8..870d0d9 100644 --- a/arch/arm/mach-imx/include/mach/imxfb.h +++ b/arch/arm/mach-imx/include/mach/imxfb.h @@ -1,7 +1,52 @@ /* * This structure describes the machine which we are running on. */ -struct imxfb_mach_info { + +#define PCR_TFT (1 << 31) +#define PCR_COLOR (1 << 30) +#define PCR_PBSIZ_1 (0 << 28) +#define PCR_PBSIZ_2 (1 << 28) +#define PCR_PBSIZ_4 (2 << 28) +#define PCR_PBSIZ_8 (3 << 28) +#define PCR_BPIX_1 (0 << 25) +#define PCR_BPIX_2 (1 << 25) +#define PCR_BPIX_4 (2 << 25) +#define PCR_BPIX_8 (3 << 25) +#define PCR_BPIX_12 (4 << 25) +#define PCR_BPIX_16 (4 << 25) +#define PCR_PIXPOL (1 << 24) +#define PCR_FLMPOL (1 << 23) +#define PCR_LPPOL (1 << 22) +#define PCR_CLKPOL (1 << 21) +#define PCR_OEPOL (1 << 20) +#define PCR_SCLKIDLE (1 << 19) +#define PCR_END_SEL (1 << 18) +#define PCR_END_BYTE_SWAP (1 << 17) +#define PCR_REV_VS (1 << 16) +#define PCR_ACD_SEL (1 << 15) +#define PCR_ACD(x) (((x) & 0x7f) << 8) +#define PCR_SCLK_SEL (1 << 7) +#define PCR_SHARP (1 << 6) +#define PCR_PCD(x) ((x) & 0x3f) + +#define PWMR_CLS(x) (((x) & 0x1ff) << 16) +#define PWMR_LDMSK (1 << 15) +#define PWMR_SCR1 (1 << 10) +#define PWMR_SCR0 (1 << 9) +#define PWMR_CC_EN (1 << 8) +#define PWMR_PW(x) ((x) & 0xff) + +#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) +#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) +#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) +#define LSCR1_GRAY2(x) (((x) & 0xf) << 4) +#define LSCR1_GRAY1(x) (((x) & 0xf)) + +#define DMACR_BURST (1 << 31) +#define DMACR_HM(x) (((x) & 0xf) << 16) +#define DMACR_TM(x) ((x) & 0xf) + +struct imx_fb_platform_data { u_long pixclock; u_short xres; @@ -34,4 +79,5 @@ struct imxfb_mach_info { void (*lcd_power)(int); void (*backlight_power)(int); }; -void set_imx_fb_info(struct imxfb_mach_info *hard_imx_fb_info); + +void set_imx_fb_info(struct imx_fb_platform_data *); diff --git a/arch/arm/mach-imx/include/mach/io.h b/arch/arm/mach-imx/include/mach/io.h index c50c5fa..9e197ae 100644 --- a/arch/arm/mach-imx/include/mach/io.h +++ b/arch/arm/mach-imx/include/mach/io.h @@ -20,11 +20,9 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#include <mach/hardware.h> - #define IO_SPACE_LIMIT 0xffffffff -#define __io(a) ((void __iomem *)(a)) +#define __io(a) __typesafe_io(a) #define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-imx/include/mach/memory.h b/arch/arm/mach-imx/include/mach/memory.h index 5c45306..a93df7c 100644 --- a/arch/arm/mach-imx/include/mach/memory.h +++ b/arch/arm/mach-imx/include/mach/memory.h @@ -23,14 +23,4 @@ #define PHYS_OFFSET UL(0x08000000) -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#define __virt_to_bus(x) (x - PAGE_OFFSET + PHYS_OFFSET) -#define __bus_to_virt(x) (x - PHYS_OFFSET + PAGE_OFFSET) - #endif diff --git a/arch/arm/mach-integrator/clock.c b/arch/arm/mach-integrator/clock.c index 8d761fd..989ecf5 100644 --- a/arch/arm/mach-integrator/clock.c +++ b/arch/arm/mach-integrator/clock.c @@ -10,42 +10,12 @@ */ #include <linux/module.h> #include <linux/kernel.h> -#include <linux/list.h> #include <linux/errno.h> -#include <linux/err.h> -#include <linux/string.h> #include <linux/clk.h> #include <linux/mutex.h> -#include <asm/hardware/icst525.h> - -#include "clock.h" - -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); - -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p, *clk = ERR_PTR(-ENOENT); - - mutex_lock(&clocks_mutex); - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { - clk = p; - break; - } - } - mutex_unlock(&clocks_mutex); - - return clk; -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ - module_put(clk->owner); -} -EXPORT_SYMBOL(clk_put); +#include <asm/clkdev.h> +#include <mach/clkdev.h> int clk_enable(struct clk *clk) { @@ -67,7 +37,6 @@ EXPORT_SYMBOL(clk_get_rate); long clk_round_rate(struct clk *clk, unsigned long rate) { struct icst525_vco vco; - vco = icst525_khz_to_vco(clk->params, rate / 1000); return icst525_khz(clk->params, vco) * 1000; } @@ -76,56 +45,15 @@ EXPORT_SYMBOL(clk_round_rate); int clk_set_rate(struct clk *clk, unsigned long rate) { int ret = -EIO; + if (clk->setvco) { struct icst525_vco vco; vco = icst525_khz_to_vco(clk->params, rate / 1000); clk->rate = icst525_khz(clk->params, vco) * 1000; - - printk("Clock %s: setting VCO reg params: S=%d R=%d V=%d\n", - clk->name, vco.s, vco.r, vco.v); - clk->setvco(clk, vco); ret = 0; } - return 0; + return ret; } EXPORT_SYMBOL(clk_set_rate); - -/* - * These are fixed clocks. - */ -static struct clk kmi_clk = { - .name = "KMIREFCLK", - .rate = 24000000, -}; - -static struct clk uart_clk = { - .name = "UARTCLK", - .rate = 14745600, -}; - -int clk_register(struct clk *clk) -{ - mutex_lock(&clocks_mutex); - list_add(&clk->node, &clocks); - mutex_unlock(&clocks_mutex); - return 0; -} -EXPORT_SYMBOL(clk_register); - -void clk_unregister(struct clk *clk) -{ - mutex_lock(&clocks_mutex); - list_del(&clk->node); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL(clk_unregister); - -static int __init clk_init(void) -{ - clk_register(&kmi_clk); - clk_register(&uart_clk); - return 0; -} -arch_initcall(clk_init); diff --git a/arch/arm/mach-integrator/clock.h b/arch/arm/mach-integrator/clock.h index 09e6328..e69de29 100644 --- a/arch/arm/mach-integrator/clock.h +++ b/arch/arm/mach-integrator/clock.h @@ -1,25 +0,0 @@ -/* - * linux/arch/arm/mach-integrator/clock.h - * - * Copyright (C) 2004 ARM Limited. - * Written by Deep Blue Solutions Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -struct module; -struct icst525_params; - -struct clk { - struct list_head node; - unsigned long rate; - struct module *owner; - const char *name; - const struct icst525_params *params; - void *data; - void (*setvco)(struct clk *, struct icst525_vco vco); -}; - -int clk_register(struct clk *clk); -void clk_unregister(struct clk *clk); diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index 595b739..c89c949 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c @@ -21,6 +21,8 @@ #include <linux/amba/serial.h> #include <linux/io.h> +#include <asm/clkdev.h> +#include <mach/clkdev.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/hardware/arm_timer.h> @@ -108,10 +110,43 @@ static struct amba_device *amba_devs[] __initdata = { &kmi1_device, }; +/* + * These are fixed clocks. + */ +static struct clk clk24mhz = { + .rate = 24000000, +}; + +static struct clk uartclk = { + .rate = 14745600, +}; + +static struct clk_lookup lookups[] __initdata = { + { /* UART0 */ + .dev_id = "mb:16", + .clk = &uartclk, + }, { /* UART1 */ + .dev_id = "mb:17", + .clk = &uartclk, + }, { /* KMI0 */ + .dev_id = "mb:18", + .clk = &clk24mhz, + }, { /* KMI1 */ + .dev_id = "mb:19", + .clk = &clk24mhz, + }, { /* MMCI - IntegratorCP */ + .dev_id = "mb:1c", + .clk = &uartclk, + } +}; + static int __init integrator_init(void) { int i; + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; amba_device_register(d, &iomem_resource); diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c index 172299a..0058c93 100644 --- a/arch/arm/mach-integrator/impd1.c +++ b/arch/arm/mach-integrator/impd1.c @@ -22,13 +22,13 @@ #include <linux/amba/clcd.h> #include <linux/io.h> +#include <asm/clkdev.h> +#include <mach/clkdev.h> #include <asm/hardware/icst525.h> #include <mach/lm.h> #include <mach/impd1.h> #include <asm/sizes.h> -#include "clock.h" - static int module_id; module_param_named(lmid, module_id, int, 0444); @@ -37,6 +37,7 @@ MODULE_PARM_DESC(lmid, "logic module stack position"); struct impd1_module { void __iomem *base; struct clk vcos[2]; + struct clk_lookup *clks[3]; }; static const struct icst525_params impd1_vco_params = { @@ -339,9 +340,8 @@ static struct impd1_device impd1_devs[] = { } }; -static const char *impd1_vconames[2] = { - "CLCDCLK", - "AUXVCO2", +static struct clk fixed_14745600 = { + .rate = 14745600, }; static int impd1_probe(struct lm_device *dev) @@ -374,14 +374,20 @@ static int impd1_probe(struct lm_device *dev) for (i = 0; i < ARRAY_SIZE(impd1->vcos); i++) { impd1->vcos[i].owner = THIS_MODULE, - impd1->vcos[i].name = impd1_vconames[i], impd1->vcos[i].params = &impd1_vco_params, impd1->vcos[i].data = impd1, impd1->vcos[i].setvco = impd1_setvco; - - clk_register(&impd1->vcos[i]); } + impd1->clks[0] = clkdev_alloc(&impd1->vcos[0], NULL, "lm%x:01000", + dev->id); + impd1->clks[1] = clkdev_alloc(&fixed_14745600, NULL, "lm%x:00100", + dev->id); + impd1->clks[2] = clkdev_alloc(&fixed_14745600, NULL, "lm%x:00200", + dev->id); + for (i = 0; i < ARRAY_SIZE(impd1->clks); i++) + clkdev_add(impd1->clks[i]); + for (i = 0; i < ARRAY_SIZE(impd1_devs); i++) { struct impd1_device *idev = impd1_devs + i; struct amba_device *d; @@ -434,8 +440,8 @@ static void impd1_remove(struct lm_device *dev) device_for_each_child(&dev->dev, NULL, impd1_remove_one); - for (i = 0; i < ARRAY_SIZE(impd1->vcos); i++) - clk_unregister(&impd1->vcos[i]); + for (i = 0; i < ARRAY_SIZE(impd1->clks); i++) + clkdev_drop(impd1->clks[i]); lm_set_drvdata(dev, NULL); diff --git a/arch/arm/mach-integrator/include/mach/clkdev.h b/arch/arm/mach-integrator/include/mach/clkdev.h new file mode 100644 index 0000000..9293e41 --- /dev/null +++ b/arch/arm/mach-integrator/include/mach/clkdev.h @@ -0,0 +1,25 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#include <linux/module.h> +#include <asm/hardware/icst525.h> + +struct clk { + unsigned long rate; + struct module *owner; + const struct icst525_params *params; + void *data; + void (*setvco)(struct clk *, struct icst525_vco vco); +}; + +static inline int __clk_get(struct clk *clk) +{ + return try_module_get(clk->owner); +} + +static inline void __clk_put(struct clk *clk) +{ + module_put(clk->owner); +} + +#endif diff --git a/arch/arm/mach-integrator/include/mach/memory.h b/arch/arm/mach-integrator/include/mach/memory.h index be7e63c..2b2e7a1 100644 --- a/arch/arm/mach-integrator/include/mach/memory.h +++ b/arch/arm/mach-integrator/include/mach/memory.h @@ -24,16 +24,9 @@ * Physical DRAM offset. */ #define PHYS_OFFSET UL(0x00000000) -#define BUS_OFFSET UL(0x80000000) -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#define __virt_to_bus(x) (x - PAGE_OFFSET + BUS_OFFSET) -#define __bus_to_virt(x) (x - BUS_OFFSET + PAGE_OFFSET) +#define BUS_OFFSET UL(0x80000000) +#define __virt_to_bus(x) ((x) - PAGE_OFFSET + BUS_OFFSET) +#define __bus_to_virt(x) ((x) - BUS_OFFSET + PAGE_OFFSET) #endif diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 88026cc..427c2d8 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -21,6 +21,8 @@ #include <linux/amba/clcd.h> #include <linux/io.h> +#include <asm/clkdev.h> +#include <mach/clkdev.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/setup.h> @@ -38,7 +40,6 @@ #include <asm/mach/time.h> #include "common.h" -#include "clock.h" #define INTCP_PA_MMC_BASE 0x1c000000 #define INTCP_PA_AACI_BASE 0x1d000000 @@ -289,15 +290,16 @@ static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco) writel(0, CM_LOCK); } -static struct clk cp_clcd_clk = { - .name = "CLCDCLK", +static struct clk cp_auxclk = { .params = &cp_auxvco_params, .setvco = cp_auxvco_set, }; -static struct clk cp_mmci_clk = { - .name = "MCLK", - .rate = 14745600, +static struct clk_lookup cp_lookups[] = { + { /* CLCD */ + .dev_id = "mb:c0", + .clk = &cp_auxclk, + }, }; /* @@ -554,8 +556,8 @@ static void __init intcp_init(void) { int i; - clk_register(&cp_clcd_clk); - clk_register(&cp_mmci_clk); + for (i = 0; i < ARRAY_SIZE(cp_lookups); i++) + clkdev_add(&cp_lookups[i]); platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs)); diff --git a/arch/arm/mach-iop13xx/include/mach/dma.h b/arch/arm/mach-iop13xx/include/mach/dma.h deleted file mode 100644 index d79846f..0000000 --- a/arch/arm/mach-iop13xx/include/mach/dma.h +++ /dev/null @@ -1,3 +0,0 @@ -#ifndef _IOP13XX_DMA_H -#define _IOP13XX_DMA_H -#endif diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h index b82602d..e012bf1 100644 --- a/arch/arm/mach-iop13xx/include/mach/memory.h +++ b/arch/arm/mach-iop13xx/include/mach/memory.h @@ -16,18 +16,6 @@ #define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) #define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) -/* - * Virtual view <-> PCI DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ - -/* RAM has 1:1 mapping on the PCIe/x Busses */ -#define __virt_to_bus(x) (__virt_to_phys(x)) -#define __bus_to_virt(x) (__phys_to_virt(x)) - static inline dma_addr_t __virt_to_lbus(unsigned long x) { return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE; @@ -55,7 +43,7 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x) if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \ __virt = __lbus_to_virt(__dma); \ else \ - __virt = __bus_to_virt(__dma); \ + __virt = __phys_to_virt(__dma); \ (void *)__virt; \ }) @@ -66,7 +54,7 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x) if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \ __dma = __virt_to_lbus(__virt); \ else \ - __dma = __virt_to_bus(__virt); \ + __dma = __virt_to_phys(__virt); \ __dma; \ }) diff --git a/arch/arm/mach-iop13xx/include/mach/timex.h b/arch/arm/mach-iop13xx/include/mach/timex.h index 5b1f1c8..45fb274 100644 --- a/arch/arm/mach-iop13xx/include/mach/timex.h +++ b/arch/arm/mach-iop13xx/include/mach/timex.h @@ -1,3 +1 @@ -#include <mach/hardware.h> - #define CLOCK_TICK_RATE (100 * HZ) diff --git a/arch/arm/mach-iop32x/include/mach/dma.h b/arch/arm/mach-iop32x/include/mach/dma.h deleted file mode 100644 index f8bd817..0000000 --- a/arch/arm/mach-iop32x/include/mach/dma.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * arch/arm/mach-iop32x/include/mach/dma.h - * - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h index ce54705..339e585 100644 --- a/arch/arm/mach-iop32x/include/mach/io.h +++ b/arch/arm/mach-iop32x/include/mach/io.h @@ -11,7 +11,7 @@ #ifndef __IO_H #define __IO_H -#include <mach/hardware.h> +#include <asm/hardware/iop3xx.h> extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, unsigned int mtype); diff --git a/arch/arm/mach-iop32x/include/mach/memory.h b/arch/arm/mach-iop32x/include/mach/memory.h index 42cd4bf..c30f645 100644 --- a/arch/arm/mach-iop32x/include/mach/memory.h +++ b/arch/arm/mach-iop32x/include/mach/memory.h @@ -5,22 +5,9 @@ #ifndef __MEMORY_H #define __MEMORY_H -#include <mach/hardware.h> - /* * Physical DRAM offset. */ #define PHYS_OFFSET UL(0xa0000000) -/* - * Virtual view <-> PCI DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#define __virt_to_bus(x) (__virt_to_phys(x)) -#define __bus_to_virt(x) (__phys_to_virt(x)) - - #endif diff --git a/arch/arm/mach-iop32x/include/mach/system.h b/arch/arm/mach-iop32x/include/mach/system.h index 20f923e..32d9e5b 100644 --- a/arch/arm/mach-iop32x/include/mach/system.h +++ b/arch/arm/mach-iop32x/include/mach/system.h @@ -7,8 +7,9 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ - #include <asm/mach-types.h> +#include <asm/hardware/iop3xx.h> +#include <mach/n2100.h> static inline void arch_idle(void) { diff --git a/arch/arm/mach-iop32x/include/mach/timex.h b/arch/arm/mach-iop32x/include/mach/timex.h index a541afc..7262ab8 100644 --- a/arch/arm/mach-iop32x/include/mach/timex.h +++ b/arch/arm/mach-iop32x/include/mach/timex.h @@ -3,7 +3,4 @@ * * IOP32x architecture timex specifications */ - -#include <mach/hardware.h> - #define CLOCK_TICK_RATE (100 * HZ) diff --git a/arch/arm/mach-iop33x/include/mach/dma.h b/arch/arm/mach-iop33x/include/mach/dma.h deleted file mode 100644 index d8b4223..0000000 --- a/arch/arm/mach-iop33x/include/mach/dma.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * arch/arm/mach-iop33x/include/mach/dma.h - * - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h index 1588746..e99a7ed 100644 --- a/arch/arm/mach-iop33x/include/mach/io.h +++ b/arch/arm/mach-iop33x/include/mach/io.h @@ -11,7 +11,7 @@ #ifndef __IO_H #define __IO_H -#include <mach/hardware.h> +#include <asm/hardware/iop3xx.h> extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, unsigned int mtype); diff --git a/arch/arm/mach-iop33x/include/mach/memory.h b/arch/arm/mach-iop33x/include/mach/memory.h index 2cef0bb..a30a96a 100644 --- a/arch/arm/mach-iop33x/include/mach/memory.h +++ b/arch/arm/mach-iop33x/include/mach/memory.h @@ -5,22 +5,9 @@ #ifndef __MEMORY_H #define __MEMORY_H -#include <mach/hardware.h> - /* * Physical DRAM offset. */ #define PHYS_OFFSET UL(0x00000000) -/* - * Virtual view <-> PCI DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#define __virt_to_bus(x) (__virt_to_phys(x)) -#define __bus_to_virt(x) (__phys_to_virt(x)) - - #endif diff --git a/arch/arm/mach-iop33x/include/mach/system.h b/arch/arm/mach-iop33x/include/mach/system.h index 7bf3bfb..0cb3ad8 100644 --- a/arch/arm/mach-iop33x/include/mach/system.h +++ b/arch/arm/mach-iop33x/include/mach/system.h @@ -7,6 +7,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include <asm/hardware/iop3xx.h> static inline void arch_idle(void) { diff --git a/arch/arm/mach-iop33x/include/mach/timex.h b/arch/arm/mach-iop33x/include/mach/timex.h index c757608..54c5890 100644 --- a/arch/arm/mach-iop33x/include/mach/timex.h +++ b/arch/arm/mach-iop33x/include/mach/timex.h @@ -3,7 +3,4 @@ * * IOP3xx architecture timex specifications */ - -#include <mach/hardware.h> - #define CLOCK_TICK_RATE (100 * HZ) diff --git a/arch/arm/mach-ixp2000/include/mach/dma.h b/arch/arm/mach-ixp2000/include/mach/dma.h deleted file mode 100644 index 26063d6..0000000 --- a/arch/arm/mach-ixp2000/include/mach/dma.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/dma.h - * - * Copyright (C) 2002 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h index 241529a..aee7eb8 100644 --- a/arch/arm/mach-ixp2000/include/mach/memory.h +++ b/arch/arm/mach-ixp2000/include/mach/memory.h @@ -15,13 +15,6 @@ #define PHYS_OFFSET UL(0x00000000) -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ #include <mach/ixp2000-regs.h> #define __virt_to_bus(v) \ diff --git a/arch/arm/mach-ixp23xx/include/mach/dma.h b/arch/arm/mach-ixp23xx/include/mach/dma.h deleted file mode 100644 index 8886544..0000000 --- a/arch/arm/mach-ixp23xx/include/mach/dma.h +++ /dev/null @@ -1,3 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/dma.h - */ diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h index 305ea18..fd9ef8e 100644 --- a/arch/arm/mach-ixp23xx/include/mach/io.h +++ b/arch/arm/mach-ixp23xx/include/mach/io.h @@ -20,8 +20,6 @@ #define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT)) #define __mem_pci(a) (a) -#include <linux/kernel.h> /* For BUG */ - static inline void __iomem * ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned int mtype) { diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h index 9d40115..fdd1387 100644 --- a/arch/arm/mach-ixp23xx/include/mach/memory.h +++ b/arch/arm/mach-ixp23xx/include/mach/memory.h @@ -19,16 +19,6 @@ */ #define PHYS_OFFSET (0x00000000) - -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#ifndef __ASSEMBLY__ - #define __virt_to_bus(v) \ ({ unsigned int ret; \ ret = ((__virt_to_phys(v) - 0x00000000) + \ @@ -43,6 +33,3 @@ #define arch_is_coherent() 1 #endif - - -#endif diff --git a/arch/arm/mach-ixp4xx/include/mach/dma.h b/arch/arm/mach-ixp4xx/include/mach/dma.h deleted file mode 100644 index 00c5070..0000000 --- a/arch/arm/mach-ixp4xx/include/mach/dma.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/include/mach/dma.h - * - * Copyright (C) 2001-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H - -#include <linux/device.h> -#include <asm/page.h> -#include <asm/sizes.h> -#include <mach/hardware.h> - -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) - -#endif /* _ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index 319948e..ce63048 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h @@ -49,8 +49,6 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); #else -#include <linux/mm.h> - /* * In the case of using indirect PCI, we simply return the actual PCI * address and our read/write implementation use that to drive the @@ -241,7 +239,7 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) #ifndef CONFIG_PCI -#define __io(v) v +#define __io(v) __typesafe_io(v) #else diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h index c4d2830..98f5e5e 100644 --- a/arch/arm/mach-ixp4xx/include/mach/memory.h +++ b/arch/arm/mach-ixp4xx/include/mach/memory.h @@ -22,19 +22,8 @@ void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes); ixp4xx_adjust_zones(node, size, holes) #define ISA_DMA_THRESHOLD (SZ_64M - 1) +#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) #endif -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - * - * These are dummies for now. - */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - #endif diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 0bb1fbd..7b8ef97 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -57,6 +57,7 @@ void __init kirkwood_map_io(void) ****************************************************************************/ static struct orion_ehci_data kirkwood_ehci_data = { .dram = &kirkwood_mbus_dram_info, + .phy_version = EHCI_PHY_NA, }; static u64 ehci_dmamask = 0xffffffffUL; @@ -153,6 +154,64 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) /***************************************************************************** + * GE01 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = { + .dram = &kirkwood_mbus_dram_info, + .shared_smi = &kirkwood_ge00_shared, +}; + +static struct resource kirkwood_ge01_shared_resources[] = { + { + .name = "ge01 base", + .start = GE01_PHYS_BASE + 0x2000, + .end = GE01_PHYS_BASE + 0x3fff, + .flags = IORESOURCE_MEM, + }, { + .name = "ge01 err irq", + .start = IRQ_KIRKWOOD_GE01_ERR, + .end = IRQ_KIRKWOOD_GE01_ERR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kirkwood_ge01_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &kirkwood_ge01_shared_data, + }, + .num_resources = ARRAY_SIZE(kirkwood_ge01_shared_resources), + .resource = kirkwood_ge01_shared_resources, +}; + +static struct resource kirkwood_ge01_resources[] = { + { + .name = "ge01 irq", + .start = IRQ_KIRKWOOD_GE01_SUM, + .end = IRQ_KIRKWOOD_GE01_SUM, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kirkwood_ge01 = { + .name = MV643XX_ETH_NAME, + .id = 1, + .num_resources = 1, + .resource = kirkwood_ge01_resources, +}; + +void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) +{ + eth_data->shared = &kirkwood_ge01_shared; + kirkwood_ge01.dev.platform_data = eth_data; + + platform_device_register(&kirkwood_ge01_shared); + platform_device_register(&kirkwood_ge01); +} + + +/***************************************************************************** * Ethernet switch ****************************************************************************/ static struct resource kirkwood_switch_resources[] = { diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 5774632..fe367c1 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -30,6 +30,7 @@ void kirkwood_pcie_id(u32 *dev, u32 *rev); void kirkwood_ehci_init(void); void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data); +void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data); void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq); void kirkwood_pcie_init(void); void kirkwood_rtc_init(void); diff --git a/arch/arm/mach-kirkwood/include/mach/dma.h b/arch/arm/mach-kirkwood/include/mach/dma.h deleted file mode 100644 index 40a8c17..0000000 --- a/arch/arm/mach-kirkwood/include/mach/dma.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/mach-kirkwood/include/mach/gpio.h b/arch/arm/mach-kirkwood/include/mach/gpio.h new file mode 100644 index 0000000..81b335e --- /dev/null +++ b/arch/arm/mach-kirkwood/include/mach/gpio.h @@ -0,0 +1,38 @@ +/* + * arch/asm-arm/mach-kirkwood/include/mach/gpio.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#include <mach/irqs.h> +#include <plat/gpio.h> +#include <asm-generic/gpio.h> /* cansleep wrappers */ + +#define GPIO_MAX 50 +#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0140 : 0x0100) +#define GPIO_OUT(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x00) +#define GPIO_IO_CONF(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x04) +#define GPIO_BLINK_EN(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x08) +#define GPIO_IN_POL(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x0c) +#define GPIO_DATA_IN(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x10) +#define GPIO_EDGE_CAUSE(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x14) +#define GPIO_EDGE_MASK(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x18) +#define GPIO_LEVEL_MASK(pin) (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x1c) + +static inline int gpio_to_irq(int pin) +{ + return pin + IRQ_KIRKWOOD_GPIO_START; +} + +static inline int irq_to_gpio(int irq) +{ + return irq - IRQ_KIRKWOOD_GPIO_START; +} + + +#endif diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h index ffab89f..f00a0a4 100644 --- a/arch/arm/mach-kirkwood/include/mach/irqs.h +++ b/arch/arm/mach-kirkwood/include/mach/irqs.h @@ -11,8 +11,6 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H -#include "kirkwood.h" /* need GPIO_MAX */ - /* * Low Interrupt Controller */ @@ -51,12 +49,13 @@ #define IRQ_KIRKWOOD_GPIO_HIGH_8_15 40 #define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41 #define IRQ_KIRKWOOD_GE00_ERR 46 +#define IRQ_KIRKWOOD_GE01_ERR 47 /* * KIRKWOOD General Purpose Pins */ #define IRQ_KIRKWOOD_GPIO_START 64 -#define NR_GPIO_IRQS GPIO_MAX +#define NR_GPIO_IRQS 50 #define NR_IRQS (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS) diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index eae4240..ada480c 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -117,7 +117,4 @@ #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) -#define GPIO_MAX 50 - - #endif diff --git a/arch/arm/mach-kirkwood/include/mach/memory.h b/arch/arm/mach-kirkwood/include/mach/memory.h index b5fb34b..45431e1 100644 --- a/arch/arm/mach-kirkwood/include/mach/memory.h +++ b/arch/arm/mach-kirkwood/include/mach/memory.h @@ -7,8 +7,4 @@ #define PHYS_OFFSET UL(0x00000000) -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - - #endif diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c index 5790643..efb86b7 100644 --- a/arch/arm/mach-kirkwood/irq.c +++ b/arch/arm/mach-kirkwood/irq.c @@ -13,10 +13,45 @@ #include <linux/irq.h> #include <linux/io.h> #include <plat/irq.h> +#include <asm/gpio.h> #include "common.h" +static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + BUG_ON(irq < IRQ_KIRKWOOD_GPIO_LOW_0_7); + BUG_ON(irq > IRQ_KIRKWOOD_GPIO_HIGH_16_23); + + orion_gpio_irq_handler((irq - IRQ_KIRKWOOD_GPIO_LOW_0_7) << 3); +} + void __init kirkwood_init_irq(void) { + int i; + orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); + + /* + * Mask and clear GPIO IRQ interrupts. + */ + writel(0, GPIO_LEVEL_MASK(0)); + writel(0, GPIO_EDGE_MASK(0)); + writel(0, GPIO_EDGE_CAUSE(0)); + writel(0, GPIO_LEVEL_MASK(32)); + writel(0, GPIO_EDGE_MASK(32)); + writel(0, GPIO_EDGE_CAUSE(32)); + + for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) { + set_irq_chip(i, &orion_gpio_irq_level_chip); + set_irq_handler(i, handle_level_irq); + irq_desc[i].status |= IRQ_LEVEL; + set_irq_flags(i, IRQF_VALID); + } + set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); + set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); + set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); + set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); + set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); + set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); + set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler); } diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c index 175054a..9a0e905 100644 --- a/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -80,24 +80,38 @@ static struct dsa_platform_data rd88f6281_switch_data = { .port_names[1] = "lan2", .port_names[2] = "lan3", .port_names[3] = "lan4", - .port_names[4] = "wan", .port_names[5] = "cpu", }; +static struct mv643xx_eth_platform_data rd88f6281_ge01_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(11), +}; + static struct mv_sata_platform_data rd88f6281_sata_data = { .n_ports = 2, }; static void __init rd88f6281_init(void) { + u32 dev, rev; + /* * Basic setup. Needs to be called early. */ kirkwood_init(); kirkwood_ehci_init(); + kirkwood_ge00_init(&rd88f6281_ge00_data); + kirkwood_pcie_id(&dev, &rev); + if (rev == MV88F6281_REV_A0) { + rd88f6281_switch_data.sw_addr = 10; + kirkwood_ge01_init(&rd88f6281_ge01_data); + } else { + rd88f6281_switch_data.port_names[4] = "wan"; + } kirkwood_ge00_switch_init(&rd88f6281_switch_data, NO_IRQ); + kirkwood_rtc_init(); kirkwood_sata_init(&rd88f6281_sata_data); kirkwood_uart0_init(); diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig index ce1cf8d..2754daa 100644 --- a/arch/arm/mach-ks8695/Kconfig +++ b/arch/arm/mach-ks8695/Kconfig @@ -8,6 +8,12 @@ config MACH_KS8695 Say 'Y' here if you want your kernel to run on the original Kendin-Micrel KS8695 development board. +config MACH_DSM320 + bool "DSM-320 Wireless Media Player" + help + Say 'Y' here if you want your kernel to run on the D-Link + DSM-320 Wireless Media Player. + endmenu endif diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile index ade42b7..f735d2c 100644 --- a/arch/arm/mach-ks8695/Makefile +++ b/arch/arm/mach-ks8695/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_LEDS) += leds.o # Board-specific support obj-$(CONFIG_MACH_KS8695) += board-micrel.o +obj-$(CONFIG_MACH_DSM320) += board-dsm320.o diff --git a/arch/arm/mach-ks8695/board-dsm320.c b/arch/arm/mach-ks8695/board-dsm320.c new file mode 100644 index 0000000..521ff07 --- /dev/null +++ b/arch/arm/mach-ks8695/board-dsm320.c @@ -0,0 +1,131 @@ +/* + * arch/arm/mach-ks8695/board-dsm320.c + * + * DSM-320 D-Link Wireless Media Player, board support. + * + * Copyright 2008 Simtec Electronics + * Daniel Silverstone <dsilvers@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <linux/platform_device.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/map.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/partitions.h> + +#include <asm/mach-types.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <mach/devices.h> +#include <mach/gpio.h> + +#include "generic.h" + +#ifdef CONFIG_PCI +static int dsm320_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + switch (slot) { + case 0: + /* PCI-AHB bridge? */ + return KS8695_IRQ_EXTERN0; + case 18: + /* Mini PCI slot */ + return KS8695_IRQ_EXTERN2; + case 20: + /* RealMAGIC chip */ + return KS8695_IRQ_EXTERN0; + } + BUG(); +} + +static struct ks8695_pci_cfg __initdata dsm320_pci = { + .mode = KS8695_MODE_MINIPCI, + .map_irq = dsm320_pci_map_irq, +}; + +static void __init dsm320_register_pci(void) +{ + /* Initialise the GPIO lines for interrupt mode */ + /* RealMAGIC */ + ks8695_gpio_interrupt(KS8695_GPIO_0, IRQ_TYPE_LEVEL_LOW); + /* MiniPCI Slot */ + ks8695_gpio_interrupt(KS8695_GPIO_2, IRQ_TYPE_LEVEL_LOW); + + ks8695_init_pci(&dsm320_pci); +} + +#else +static inline void __init dsm320_register_pci(void) { } +#endif + +static struct physmap_flash_data dsm320_nor_pdata = { + .width = 4, + .nr_parts = 0, +}; + +static struct resource dsm320_nor_resource[] = { + [0] = { + .start = SZ_32M, /* We expect the bootloader to map + * the flash here. + */ + .end = SZ_32M + SZ_4M - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device dsm320_device_nor = { + .name = "physmap-flash", + .id = -1, + .num_resources = ARRAY_SIZE(dsm320_nor_resource), + .resource = dsm320_nor_resource, + .dev = { + .platform_data = &dsm320_nor_pdata, + }, +}; + +void __init dsm320_register_nor(void) +{ + int ret; + + ret = platform_device_register(&dsm320_device_nor); + if (ret < 0) + printk(KERN_ERR "failed to register physmap-flash device\n"); +} + +static void __init dsm320_init(void) +{ + /* GPIO registration */ + ks8695_register_gpios(); + + /* PCI registration */ + dsm320_register_pci(); + + /* Network device */ + ks8695_add_device_lan(); /* eth0 = LAN */ + + /* NOR devices */ + dsm320_register_nor(); +} + +MACHINE_START(DSM320, "D-Link DSM-320 Wireless Media Player") + /* Maintainer: Simtec Electronics. */ + .phys_io = KS8695_IO_PA, + .io_pg_offst = (KS8695_IO_VA >> 18) & 0xfffc, + .boot_params = KS8695_SDRAM_PA + 0x100, + .map_io = ks8695_map_io, + .init_irq = ks8695_init_irq, + .init_machine = dsm320_init, + .timer = &ks8695_timer, +MACHINE_END diff --git a/arch/arm/mach-ks8695/board-micrel.c b/arch/arm/mach-ks8695/board-micrel.c index 0468e93..8ceaf5a 100644 --- a/arch/arm/mach-ks8695/board-micrel.c +++ b/arch/arm/mach-ks8695/board-micrel.c @@ -18,6 +18,7 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> +#include <mach/gpio.h> #include <mach/devices.h> #include "generic.h" @@ -39,6 +40,8 @@ static void __init micrel_init(void) { printk(KERN_INFO "Micrel KS8695 Development Board initializing\n"); + ks8695_register_gpios(); + #ifdef CONFIG_PCI ks8695_init_pci(&micrel_pci); #endif diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c index 4bd2514..36ab0fd 100644 --- a/arch/arm/mach-ks8695/devices.c +++ b/arch/arm/mach-ks8695/devices.c @@ -25,19 +25,20 @@ #include <mach/regs-wan.h> #include <mach/regs-lan.h> #include <mach/regs-hpna.h> +#include <mach/regs-switch.h> +#include <mach/regs-misc.h> /* -------------------------------------------------------------------- * Ethernet * -------------------------------------------------------------------- */ -#if defined(CONFIG_ARM_KS8695_ETHER) || defined(CONFIG_ARM_KS8695_ETHER_MODULE) static u64 eth_dmamask = 0xffffffffUL; static struct resource ks8695_wan_resources[] = { [0] = { - .start = KS8695_WAN_VA, - .end = KS8695_WAN_VA + 0x00ff, + .start = KS8695_WAN_PA, + .end = KS8695_WAN_PA + 0x00ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -58,6 +59,12 @@ static struct resource ks8695_wan_resources[] = { .end = KS8695_IRQ_WAN_LINK, .flags = IORESOURCE_IRQ, }, + [4] = { + .name = "WAN PHY", + .start = KS8695_MISC_PA, + .end = KS8695_MISC_PA + 0x1f, + .flags = IORESOURCE_MEM, + }, }; static struct platform_device ks8695_wan_device = { @@ -74,8 +81,8 @@ static struct platform_device ks8695_wan_device = { static struct resource ks8695_lan_resources[] = { [0] = { - .start = KS8695_LAN_VA, - .end = KS8695_LAN_VA + 0x00ff, + .start = KS8695_LAN_PA, + .end = KS8695_LAN_PA + 0x00ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -90,6 +97,12 @@ static struct resource ks8695_lan_resources[] = { .end = KS8695_IRQ_LAN_TX_STATUS, .flags = IORESOURCE_IRQ, }, + [3] = { + .name = "LAN SWITCH", + .start = KS8695_SWITCH_PA, + .end = KS8695_SWITCH_PA + 0x4f, + .flags = IORESOURCE_MEM, + }, }; static struct platform_device ks8695_lan_device = { @@ -106,8 +119,8 @@ static struct platform_device ks8695_lan_device = { static struct resource ks8695_hpna_resources[] = { [0] = { - .start = KS8695_HPNA_VA, - .end = KS8695_HPNA_VA + 0x00ff, + .start = KS8695_HPNA_PA, + .end = KS8695_HPNA_PA + 0x00ff, .flags = IORESOURCE_MEM, }, [1] = { @@ -149,18 +162,12 @@ void __init ks8696_add_device_hpna(void) { platform_device_register(&ks8695_hpna_device); } -#else -void __init ks8695_add_device_wan(void) {} -void __init ks8695_add_device_lan(void) {} -void __init ks8696_add_device_hpna(void) {} -#endif /* -------------------------------------------------------------------- * Watchdog * -------------------------------------------------------------------- */ -#if defined(CONFIG_KS8695_WATCHDOG) || defined(CONFIG_KS8695_WATCHDOG_MODULE) static struct platform_device ks8695_wdt_device = { .name = "ks8695_wdt", .id = -1, @@ -171,9 +178,6 @@ static void __init ks8695_add_device_watchdog(void) { platform_device_register(&ks8695_wdt_device); } -#else -static void __init ks8695_add_device_watchdog(void) {} -#endif /* -------------------------------------------------------------------- @@ -190,7 +194,7 @@ void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) gpio_direction_output(cpu_led, 1); gpio_direction_output(timer_led, 1); - ks8695_leds_cpu = cpu_led; + ks8695_leds_cpu = cpu_led; ks8695_leds_timer = timer_led; } #else diff --git a/arch/arm/mach-ks8695/gpio.c b/arch/arm/mach-ks8695/gpio.c index 9aecf0c..55fbf71 100644 --- a/arch/arm/mach-ks8695/gpio.c +++ b/arch/arm/mach-ks8695/gpio.c @@ -2,6 +2,8 @@ * arch/arm/mach-ks8695/gpio.c * * Copyright (C) 2006 Andrew Victor + * Updated to GPIOLIB, Copyright 2008 Simtec Electronics + * Daniel Silverstone <dsilvers@simtec.co.uk> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -35,7 +37,7 @@ * Configure a GPIO line for either GPIO function, or its internal * function (Interrupt, Timer, etc). */ -static void __init_or_module ks8695_gpio_mode(unsigned int pin, short gpio) +static void ks8695_gpio_mode(unsigned int pin, short gpio) { unsigned int enable[] = { IOPC_IOEINT0EN, IOPC_IOEINT1EN, IOPC_IOEINT2EN, IOPC_IOEINT3EN, IOPC_IOTIM0EN, IOPC_IOTIM1EN }; unsigned long x, flags; @@ -61,7 +63,7 @@ static unsigned short gpio_irq[] = { KS8695_IRQ_EXTERN0, KS8695_IRQ_EXTERN1, KS8 /* * Configure GPIO pin as external interrupt source. */ -int __init_or_module ks8695_gpio_interrupt(unsigned int pin, unsigned int type) +int ks8695_gpio_interrupt(unsigned int pin, unsigned int type) { unsigned long x, flags; @@ -94,7 +96,7 @@ EXPORT_SYMBOL(ks8695_gpio_interrupt); /* * Configure the GPIO line as an input. */ -int __init_or_module gpio_direction_input(unsigned int pin) +static int ks8695_gpio_direction_input(struct gpio_chip *gc, unsigned int pin) { unsigned long x, flags; @@ -115,13 +117,13 @@ int __init_or_module gpio_direction_input(unsigned int pin) return 0; } -EXPORT_SYMBOL(gpio_direction_input); /* * Configure the GPIO line as an output, with default state. */ -int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state) +static int ks8695_gpio_direction_output(struct gpio_chip *gc, + unsigned int pin, int state) { unsigned long x, flags; @@ -150,13 +152,13 @@ int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state) return 0; } -EXPORT_SYMBOL(gpio_direction_output); /* * Set the state of an output GPIO line. */ -void gpio_set_value(unsigned int pin, unsigned int state) +static void ks8695_gpio_set_value(struct gpio_chip *gc, + unsigned int pin, int state) { unsigned long x, flags; @@ -175,13 +177,12 @@ void gpio_set_value(unsigned int pin, unsigned int state) local_irq_restore(flags); } -EXPORT_SYMBOL(gpio_set_value); /* * Read the state of a GPIO line. */ -int gpio_get_value(unsigned int pin) +static int ks8695_gpio_get_value(struct gpio_chip *gc, unsigned int pin) { unsigned long x; @@ -191,21 +192,18 @@ int gpio_get_value(unsigned int pin) x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD); return (x & IOPD(pin)) != 0; } -EXPORT_SYMBOL(gpio_get_value); /* * Map GPIO line to IRQ number. */ -int gpio_to_irq(unsigned int pin) +static int ks8695_gpio_to_irq(struct gpio_chip *gc, unsigned int pin) { if (pin > KS8695_GPIO_3) /* only GPIO 0..3 can generate IRQ */ return -EINVAL; return gpio_irq[pin]; } -EXPORT_SYMBOL(gpio_to_irq); - /* * Map IRQ number to GPIO line. @@ -219,6 +217,26 @@ int irq_to_gpio(unsigned int irq) } EXPORT_SYMBOL(irq_to_gpio); +/* GPIOLIB interface */ + +static struct gpio_chip ks8695_gpio_chip = { + .label = "KS8695", + .direction_input = ks8695_gpio_direction_input, + .direction_output = ks8695_gpio_direction_output, + .get = ks8695_gpio_get_value, + .set = ks8695_gpio_set_value, + .to_irq = ks8695_gpio_to_irq, + .base = 0, + .ngpio = 16, + .can_sleep = 0, +}; + +/* Register the GPIOs */ +void ks8695_register_gpios(void) +{ + if (gpiochip_add(&ks8695_gpio_chip)) + printk(KERN_ERR "Unable to register core GPIOs\n"); +} /* .... Debug interface ..................................................... */ diff --git a/arch/arm/mach-ks8695/include/mach/dma.h b/arch/arm/mach-ks8695/include/mach/dma.h deleted file mode 100644 index 5612062..0000000 --- a/arch/arm/mach-ks8695/include/mach/dma.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * arch/arm/mach-ks8695/include/mach/dma.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ diff --git a/arch/arm/mach-ks8695/include/mach/gpio.h b/arch/arm/mach-ks8695/include/mach/gpio.h index d4af5c3..86312d4 100644 --- a/arch/arm/mach-ks8695/include/mach/gpio.h +++ b/arch/arm/mach-ks8695/include/mach/gpio.h @@ -30,53 +30,28 @@ #define KS8695_GPIO_14 14 #define KS8695_GPIO_15 15 - /* * Configure GPIO pin as external interrupt source. */ -int __init_or_module ks8695_gpio_interrupt(unsigned int pin, unsigned int type); - -/* - * Configure the GPIO line as an input. - */ -int __init_or_module gpio_direction_input(unsigned int pin); - -/* - * Configure the GPIO line as an output, with default state. - */ -int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state); - -/* - * Set the state of an output GPIO line. - */ -void gpio_set_value(unsigned int pin, unsigned int state); - -/* - * Read the state of a GPIO line. - */ -int gpio_get_value(unsigned int pin); - -/* - * Map GPIO line to IRQ number. - */ -int gpio_to_irq(unsigned int pin); +extern int ks8695_gpio_interrupt(unsigned int pin, unsigned int type); /* * Map IRQ number to GPIO line. */ -int irq_to_gpio(unsigned int irq); - +extern int irq_to_gpio(unsigned int irq); #include <asm-generic/gpio.h> -static inline int gpio_request(unsigned int pin, const char *label) -{ - return 0; -} +/* If it turns out that we need to optimise GPIO access for the + * Micrel's GPIOs, then these can be changed to check their argument + * directly as static inlines. However for now it's probably not + * worthwhile. + */ +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_to_irq __gpio_to_irq -static inline void gpio_free(unsigned int pin) -{ - might_sleep(); -} +/* Register the GPIOs */ +extern void ks8695_register_gpios(void); #endif diff --git a/arch/arm/mach-ks8695/include/mach/io.h b/arch/arm/mach-ks8695/include/mach/io.h index f364f24..a7a63ac 100644 --- a/arch/arm/mach-ks8695/include/mach/io.h +++ b/arch/arm/mach-ks8695/include/mach/io.h @@ -13,7 +13,7 @@ #define IO_SPACE_LIMIT 0xffffffff -#define __io(a) ((void __iomem *)(a)) -#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h index 8fbc4c7..6d5887c 100644 --- a/arch/arm/mach-ks8695/include/mach/memory.h +++ b/arch/arm/mach-ks8695/include/mach/memory.h @@ -37,11 +37,6 @@ extern struct bus_type platform_bus_type; (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) #define __arch_page_to_dma(dev, x) __arch_virt_to_dma(dev, page_address(x)) -#else - -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - #endif #endif diff --git a/arch/arm/mach-l7200/include/mach/dma.h b/arch/arm/mach-l7200/include/mach/dma.h deleted file mode 100644 index c7e48bd..0000000 --- a/arch/arm/mach-l7200/include/mach/dma.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * arch/arm/mach-l7200/include/mach/dma.h - * - * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) - * - * Changelog: - * 08-29-2000 SJH Created - */ -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H - -/* DMA is not yet implemented! It should be the same as acorn, copy over.. */ - -/* - * This is the maximum DMA address that can be DMAd to. - * There should not be more than (0xd0000000 - 0xc0000000) - * bytes of RAM. - */ -#define MAX_DMA_ADDRESS 0xd0000000 - -#define DMA_S0 0 - -#endif /* _ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-l7200/include/mach/io.h b/arch/arm/mach-l7200/include/mach/io.h index d432ba9..a770a89 100644 --- a/arch/arm/mach-l7200/include/mach/io.h +++ b/arch/arm/mach-l7200/include/mach/io.h @@ -10,18 +10,12 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#include <mach/hardware.h> - #define IO_SPACE_LIMIT 0xffffffff /* * There are not real ISA nor PCI buses, so we fake it. */ -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)addr; -} -#define __io(a) __io(a) -#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-l7200/include/mach/memory.h b/arch/arm/mach-l7200/include/mach/memory.h index f338cf3..9fb40ed 100644 --- a/arch/arm/mach-l7200/include/mach/memory.h +++ b/arch/arm/mach-l7200/include/mach/memory.h @@ -17,9 +17,6 @@ */ #define PHYS_OFFSET UL(0xf0000000) -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - /* * Cache flushing area - ROM */ diff --git a/arch/arm/mach-lh7a40x/clocks.c b/arch/arm/mach-lh7a40x/clocks.c index 4fb23ac..6182f54 100644 --- a/arch/arm/mach-lh7a40x/clocks.c +++ b/arch/arm/mach-lh7a40x/clocks.c @@ -14,21 +14,14 @@ #include <linux/err.h> struct module; -struct icst525_params; struct clk { struct list_head node; unsigned long rate; struct module *owner; const char *name; -// void *data; -// const struct icst525_params *params; -// void (*setvco)(struct clk *, struct icst525_vco vco); }; -int clk_register(struct clk *clk); -void clk_unregister(struct clk *clk); - /* ----- */ #define MAINDIV1(c) (((c) >> 7) & 0x0f) @@ -79,31 +72,15 @@ unsigned int pclkfreq_get (void) /* ----- */ -static LIST_HEAD(clocks); -static DECLARE_MUTEX(clocks_sem); - struct clk *clk_get (struct device *dev, const char *id) { - struct clk *p; - struct clk *clk = ERR_PTR(-ENOENT); - - down (&clocks_sem); - list_for_each_entry (p, &clocks, node) { - if (strcmp (id, p->name) == 0 - && try_module_get(p->owner)) { - clk = p; - break; - } - } - up (&clocks_sem); - - return clk; + return dev && strcmp(dev_name(dev), "cldc-lh7a40x") == 0 + ? NULL : ERR_PTR(-ENOENT); } EXPORT_SYMBOL(clk_get); void clk_put (struct clk *clk) { - module_put(clk->owner); } EXPORT_SYMBOL(clk_put); @@ -118,20 +95,9 @@ void clk_disable (struct clk *clk) } EXPORT_SYMBOL(clk_disable); -int clk_use (struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_use); - -void clk_unuse (struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_unuse); - unsigned long clk_get_rate (struct clk *clk) { - return clk->rate; + return 0; } EXPORT_SYMBOL(clk_get_rate); @@ -143,56 +109,6 @@ EXPORT_SYMBOL(clk_round_rate); int clk_set_rate (struct clk *clk, unsigned long rate) { - int ret = -EIO; - return ret; + return -EIO; } EXPORT_SYMBOL(clk_set_rate); - -#if 0 -/* - * These are fixed clocks. - */ -static struct clk kmi_clk = { - .name = "KMIREFCLK", - .rate = 24000000, -}; - -static struct clk uart_clk = { - .name = "UARTCLK", - .rate = 24000000, -}; - -static struct clk mmci_clk = { - .name = "MCLK", - .rate = 33000000, -}; -#endif - -static struct clk clcd_clk = { - .name = "CLCDCLK", - .rate = 0, -}; - -int clk_register (struct clk *clk) -{ - down (&clocks_sem); - list_add (&clk->node, &clocks); - up (&clocks_sem); - return 0; -} -EXPORT_SYMBOL(clk_register); - -void clk_unregister (struct clk *clk) -{ - down (&clocks_sem); - list_del (&clk->node); - up (&clocks_sem); -} -EXPORT_SYMBOL(clk_unregister); - -static int __init clk_init (void) -{ - clk_register(&clcd_clk); - return 0; -} -arch_initcall(clk_init); diff --git a/arch/arm/mach-lh7a40x/include/mach/io.h b/arch/arm/mach-lh7a40x/include/mach/io.h index 031d26f..6ece459 100644 --- a/arch/arm/mach-lh7a40x/include/mach/io.h +++ b/arch/arm/mach-lh7a40x/include/mach/io.h @@ -11,12 +11,10 @@ #ifndef __ASM_ARCH_IO_H #define __ASM_ARCH_IO_H -#include <mach/hardware.h> - #define IO_SPACE_LIMIT 0xffffffff /* No ISA or PCI bus on this machine. */ -#define __io(a) ((void __iomem *)(a)) -#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) #endif /* __ASM_ARCH_IO_H */ diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h index 1da14ff..189d20e 100644 --- a/arch/arm/mach-lh7a40x/include/mach/memory.h +++ b/arch/arm/mach-lh7a40x/include/mach/memory.h @@ -19,16 +19,6 @@ */ #define PHYS_OFFSET UL(0xc0000000) -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - #ifdef CONFIG_DISCONTIGMEM /* diff --git a/arch/arm/mach-loki/include/mach/dma.h b/arch/arm/mach-loki/include/mach/dma.h deleted file mode 100644 index 40a8c17..0000000 --- a/arch/arm/mach-loki/include/mach/dma.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/mach-loki/include/mach/memory.h b/arch/arm/mach-loki/include/mach/memory.h index a39533a..2ed7e6e7 100644 --- a/arch/arm/mach-loki/include/mach/memory.h +++ b/arch/arm/mach-loki/include/mach/memory.h @@ -7,8 +7,4 @@ #define PHYS_OFFSET UL(0x00000000) -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - - #endif diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h index c6a2feb..aab9645 100644 --- a/arch/arm/mach-msm/include/mach/io.h +++ b/arch/arm/mach-msm/include/mach/io.h @@ -23,11 +23,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype); -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)addr; -} -#define __io(a) __io(a) +#define __io(a) __typesafe_io(a) #define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h index 63fd47f..f4698ba 100644 --- a/arch/arm/mach-msm/include/mach/memory.h +++ b/arch/arm/mach-msm/include/mach/memory.h @@ -19,9 +19,5 @@ /* physical offset of RAM */ #define PHYS_OFFSET UL(0x10000000) -/* bus address and physical addresses are identical */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - #endif diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 238a2f8..b0e4e0d 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -167,6 +167,7 @@ void __init mv78xx0_map_io(void) ****************************************************************************/ static struct orion_ehci_data mv78xx0_ehci_data = { .dram = &mv78xx0_mbus_dram_info, + .phy_version = EHCI_PHY_NA, }; static u64 ehci_dmamask = 0xffffffffUL; diff --git a/arch/arm/mach-mv78xx0/include/mach/dma.h b/arch/arm/mach-mv78xx0/include/mach/dma.h deleted file mode 100644 index 40a8c17..0000000 --- a/arch/arm/mach-mv78xx0/include/mach/dma.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/mach-mv78xx0/include/mach/gpio.h b/arch/arm/mach-mv78xx0/include/mach/gpio.h new file mode 100644 index 0000000..d9d1535 --- /dev/null +++ b/arch/arm/mach-mv78xx0/include/mach/gpio.h @@ -0,0 +1,40 @@ +/* + * arch/asm-arm/mach-mv78xx0/include/mach/gpio.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#include <mach/irqs.h> +#include <plat/gpio.h> +#include <asm-generic/gpio.h> /* cansleep wrappers */ + +extern int mv78xx0_core_index(void); + +#define GPIO_MAX 32 +#define GPIO_OUT(pin) (DEV_BUS_VIRT_BASE + 0x0100) +#define GPIO_IO_CONF(pin) (DEV_BUS_VIRT_BASE + 0x0104) +#define GPIO_BLINK_EN(pin) (DEV_BUS_VIRT_BASE + 0x0108) +#define GPIO_IN_POL(pin) (DEV_BUS_VIRT_BASE + 0x010c) +#define GPIO_DATA_IN(pin) (DEV_BUS_VIRT_BASE + 0x0110) +#define GPIO_EDGE_CAUSE(pin) (DEV_BUS_VIRT_BASE + 0x0114) +#define GPIO_MASK_OFF (mv78xx0_core_index() ? 0x18 : 0) +#define GPIO_EDGE_MASK(pin) (DEV_BUS_VIRT_BASE + 0x0118 + GPIO_MASK_OFF) +#define GPIO_LEVEL_MASK(pin) (DEV_BUS_VIRT_BASE + 0x011c + GPIO_MASK_OFF) + +static inline int gpio_to_irq(int pin) +{ + return pin + IRQ_MV78XX0_GPIO_START; +} + +static inline int irq_to_gpio(int irq) +{ + return irq - IRQ_MV78XX0_GPIO_START; +} + + +#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/irqs.h b/arch/arm/mach-mv78xx0/include/mach/irqs.h index bebc330..fa1d422 100644 --- a/arch/arm/mach-mv78xx0/include/mach/irqs.h +++ b/arch/arm/mach-mv78xx0/include/mach/irqs.h @@ -11,8 +11,6 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H -#include "mv78xx0.h" /* need GPIO_MAX */ - /* * MV78xx0 Low Interrupt Controller */ @@ -88,7 +86,7 @@ * MV78XX0 General Purpose Pins */ #define IRQ_MV78XX0_GPIO_START 96 -#define NR_GPIO_IRQS GPIO_MAX +#define NR_GPIO_IRQS 32 #define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) diff --git a/arch/arm/mach-mv78xx0/include/mach/memory.h b/arch/arm/mach-mv78xx0/include/mach/memory.h index 9e47a140..e663042 100644 --- a/arch/arm/mach-mv78xx0/include/mach/memory.h +++ b/arch/arm/mach-mv78xx0/include/mach/memory.h @@ -7,8 +7,4 @@ #define PHYS_OFFSET UL(0x00000000) -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - - #endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index ee9c559..e930ea5 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -122,7 +122,4 @@ #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) -#define GPIO_MAX 32 - - #endif diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 503e5d1..e273418 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -11,13 +11,42 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/pci.h> +#include <linux/irq.h> +#include <asm/gpio.h> #include <mach/mv78xx0.h> #include <plat/irq.h> #include "common.h" +static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + BUG_ON(irq < IRQ_MV78XX0_GPIO_0_7 || irq > IRQ_MV78XX0_GPIO_24_31); + + orion_gpio_irq_handler((irq - IRQ_MV78XX0_GPIO_0_7) << 3); +} + void __init mv78xx0_init_irq(void) { + int i; + orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); + + /* + * Mask and clear GPIO IRQ interrupts. + */ + writel(0, GPIO_LEVEL_MASK(0)); + writel(0, GPIO_EDGE_MASK(0)); + writel(0, GPIO_EDGE_CAUSE(0)); + + for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) { + set_irq_chip(i, &orion_gpio_irq_level_chip); + set_irq_handler(i, handle_level_irq); + irq_desc[i].status |= IRQ_LEVEL; + set_irq_flags(i, IRQF_VALID); + } + set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); + set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); + set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); + set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); } diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig new file mode 100644 index 0000000..2b59fc7 --- /dev/null +++ b/arch/arm/mach-mx1/Kconfig @@ -0,0 +1,14 @@ +if ARCH_MX1 + +comment "MX1 Platforms" + +config MACH_MXLADS + bool + +config ARCH_MX1ADS + bool "MX1ADS platform" + select MACH_MXLADS + help + Say Y here if you are using Motorola MX1ADS/MXLADS boards + +endif diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile new file mode 100644 index 0000000..b969719 --- /dev/null +++ b/arch/arm/mach-mx1/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-y += generic.o clock.o devices.o + +# Specific board support +obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o diff --git a/arch/arm/mach-mx1/Makefile.boot b/arch/arm/mach-mx1/Makefile.boot new file mode 100644 index 0000000..8ed1492 --- /dev/null +++ b/arch/arm/mach-mx1/Makefile.boot @@ -0,0 +1,4 @@ + zreladdr-y := 0x08008000 +params_phys-y := 0x08000100 +initrd_phys-y := 0x08800000 + diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c new file mode 100644 index 0000000..4bcd1ec --- /dev/null +++ b/arch/arm/mach-mx1/clock.c @@ -0,0 +1,656 @@ +/* + * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/math64.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <mach/clock.h> +#include <mach/hardware.h> +#include "crm_regs.h" + +static int _clk_enable(struct clk *clk) +{ + unsigned int reg; + + reg = __raw_readl(clk->enable_reg); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void _clk_disable(struct clk *clk) +{ + unsigned int reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(1 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static int _clk_can_use_parent(const struct clk *clk_arr[], unsigned int size, + struct clk *parent) +{ + int i; + + for (i = 0; i < size; i++) + if (parent == clk_arr[i]) + return i; + + return -EINVAL; +} + +static unsigned long +_clk_simple_round_rate(struct clk *clk, unsigned long rate, unsigned int limit) +{ + int div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (parent_rate % rate) + div++; + + if (div > limit) + div = limit; + + return parent_rate / div; +} + +static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate) +{ + return clk->parent->round_rate(clk->parent, rate); +} + +static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) +{ + return clk->parent->set_rate(clk->parent, rate); +} + +/* + * get the system pll clock in Hz + * + * mfi + mfn / (mfd +1) + * f = 2 * f_ref * -------------------- + * pd + 1 + */ +static unsigned long mx1_decode_pll(unsigned int pll, u32 f_ref) +{ + unsigned long long ll; + unsigned long quot; + + u32 mfi = (pll >> 10) & 0xf; + u32 mfn = pll & 0x3ff; + u32 mfd = (pll >> 16) & 0x3ff; + u32 pd = (pll >> 26) & 0xf; + + mfi = mfi <= 5 ? 5 : mfi; + + ll = 2 * (unsigned long long)f_ref * + ((mfi << 16) + (mfn << 16) / (mfd + 1)); + quot = (pd + 1) * (1 << 16); + ll += quot / 2; + do_div(ll, quot); + return (unsigned long)ll; +} + +static unsigned long clk16m_get_rate(struct clk *clk) +{ + return 16000000; +} + +static struct clk clk16m = { + .name = "CLK16M", + .get_rate = clk16m_get_rate, + .enable = _clk_enable, + .enable_reg = CCM_CSCR, + .enable_shift = CCM_CSCR_OSC_EN_SHIFT, + .disable = _clk_disable, +}; + +/* in Hz */ +static unsigned long clk32_rate; + +static unsigned long clk32_get_rate(struct clk *clk) +{ + return clk32_rate; +} + +static struct clk clk32 = { + .name = "CLK32", + .get_rate = clk32_get_rate, +}; + +static unsigned long clk32_premult_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) * 512; +} + +static struct clk clk32_premult = { + .name = "CLK32_premultiplier", + .parent = &clk32, + .get_rate = clk32_premult_get_rate, +}; + +static const struct clk *prem_clk_clocks[] = { + &clk32_premult, + &clk16m, +}; + +static int prem_clk_set_parent(struct clk *clk, struct clk *parent) +{ + int i; + unsigned int reg = __raw_readl(CCM_CSCR); + + i = _clk_can_use_parent(prem_clk_clocks, ARRAY_SIZE(prem_clk_clocks), + parent); + + switch (i) { + case 0: + reg &= ~CCM_CSCR_SYSTEM_SEL; + break; + case 1: + reg |= CCM_CSCR_SYSTEM_SEL; + break; + default: + return i; + } + + __raw_writel(reg, CCM_CSCR); + + return 0; +} + +static struct clk prem_clk = { + .name = "prem_clk", + .set_parent = prem_clk_set_parent, +}; + +static unsigned long system_clk_get_rate(struct clk *clk) +{ + return mx1_decode_pll(__raw_readl(CCM_SPCTL0), + clk_get_rate(clk->parent)); +} + +static struct clk system_clk = { + .name = "system_clk", + .parent = &prem_clk, + .get_rate = system_clk_get_rate, +}; + +static unsigned long mcu_clk_get_rate(struct clk *clk) +{ + return mx1_decode_pll(__raw_readl(CCM_MPCTL0), + clk_get_rate(clk->parent)); +} + +static struct clk mcu_clk = { + .name = "mcu_clk", + .parent = &clk32_premult, + .get_rate = mcu_clk_get_rate, +}; + +static unsigned long fclk_get_rate(struct clk *clk) +{ + unsigned long fclk = clk_get_rate(clk->parent); + + if (__raw_readl(CCM_CSCR) & CCM_CSCR_PRESC) + fclk /= 2; + + return fclk; +} + +static struct clk fclk = { + .name = "fclk", + .parent = &mcu_clk, + .get_rate = fclk_get_rate, +}; + +/* + * get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA ) + */ +static unsigned long hclk_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) & + CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET) + 1); +} + +static unsigned long hclk_round_rate(struct clk *clk, unsigned long rate) +{ + return _clk_simple_round_rate(clk, rate, 16); +} + +static int hclk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int div; + unsigned int reg; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if (div > 16 || div < 1 || ((parent_rate / div) != rate)) + return -EINVAL; + + div--; + + reg = __raw_readl(CCM_CSCR); + reg &= ~CCM_CSCR_BCLK_MASK; + reg |= div << CCM_CSCR_BCLK_OFFSET; + __raw_writel(reg, CCM_CSCR); + + return 0; +} + +static struct clk hclk = { + .name = "hclk", + .parent = &system_clk, + .get_rate = hclk_get_rate, + .round_rate = hclk_round_rate, + .set_rate = hclk_set_rate, +}; + +static unsigned long clk48m_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) & + CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET) + 1); +} + +static unsigned long clk48m_round_rate(struct clk *clk, unsigned long rate) +{ + return _clk_simple_round_rate(clk, rate, 8); +} + +static int clk48m_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int div; + unsigned int reg; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if (div > 8 || div < 1 || ((parent_rate / div) != rate)) + return -EINVAL; + + div--; + + reg = __raw_readl(CCM_CSCR); + reg &= ~CCM_CSCR_USB_MASK; + reg |= div << CCM_CSCR_USB_OFFSET; + __raw_writel(reg, CCM_CSCR); + + return 0; +} + +static struct clk clk48m = { + .name = "CLK48M", + .parent = &system_clk, + .get_rate = clk48m_get_rate, + .round_rate = clk48m_round_rate, + .set_rate = clk48m_set_rate, +}; + +/* + * get peripheral clock 1 ( UART[12], Timer[12], PWM ) + */ +static unsigned long perclk1_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) & + CCM_PCDR_PCLK1_MASK) >> CCM_PCDR_PCLK1_OFFSET) + 1); +} + +static unsigned long perclk1_round_rate(struct clk *clk, unsigned long rate) +{ + return _clk_simple_round_rate(clk, rate, 16); +} + +static int perclk1_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int div; + unsigned int reg; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if (div > 16 || div < 1 || ((parent_rate / div) != rate)) + return -EINVAL; + + div--; + + reg = __raw_readl(CCM_PCDR); + reg &= ~CCM_PCDR_PCLK1_MASK; + reg |= div << CCM_PCDR_PCLK1_OFFSET; + __raw_writel(reg, CCM_PCDR); + + return 0; +} + +/* + * get peripheral clock 2 ( LCD, SD, SPI[12] ) + */ +static unsigned long perclk2_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) & + CCM_PCDR_PCLK2_MASK) >> CCM_PCDR_PCLK2_OFFSET) + 1); +} + +static unsigned long perclk2_round_rate(struct clk *clk, unsigned long rate) +{ + return _clk_simple_round_rate(clk, rate, 16); +} + +static int perclk2_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int div; + unsigned int reg; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if (div > 16 || div < 1 || ((parent_rate / div) != rate)) + return -EINVAL; + + div--; + + reg = __raw_readl(CCM_PCDR); + reg &= ~CCM_PCDR_PCLK2_MASK; + reg |= div << CCM_PCDR_PCLK2_OFFSET; + __raw_writel(reg, CCM_PCDR); + + return 0; +} + +/* + * get peripheral clock 3 ( SSI ) + */ +static unsigned long perclk3_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) & + CCM_PCDR_PCLK3_MASK) >> CCM_PCDR_PCLK3_OFFSET) + 1); +} + +static unsigned long perclk3_round_rate(struct clk *clk, unsigned long rate) +{ + return _clk_simple_round_rate(clk, rate, 128); +} + +static int perclk3_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int div; + unsigned int reg; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if (div > 128 || div < 1 || ((parent_rate / div) != rate)) + return -EINVAL; + + div--; + + reg = __raw_readl(CCM_PCDR); + reg &= ~CCM_PCDR_PCLK3_MASK; + reg |= div << CCM_PCDR_PCLK3_OFFSET; + __raw_writel(reg, CCM_PCDR); + + return 0; +} + +static struct clk perclk[] = { + { + .name = "perclk", + .id = 0, + .parent = &system_clk, + .get_rate = perclk1_get_rate, + .round_rate = perclk1_round_rate, + .set_rate = perclk1_set_rate, + }, { + .name = "perclk", + .id = 1, + .parent = &system_clk, + .get_rate = perclk2_get_rate, + .round_rate = perclk2_round_rate, + .set_rate = perclk2_set_rate, + }, { + .name = "perclk", + .id = 2, + .parent = &system_clk, + .get_rate = perclk3_get_rate, + .round_rate = perclk3_round_rate, + .set_rate = perclk3_set_rate, + } +}; + +static const struct clk *clko_clocks[] = { + &perclk[0], + &hclk, + &clk48m, + &clk16m, + &prem_clk, + &fclk, +}; + +static int clko_set_parent(struct clk *clk, struct clk *parent) +{ + int i; + unsigned int reg; + + i = _clk_can_use_parent(clko_clocks, ARRAY_SIZE(clko_clocks), parent); + if (i < 0) + return i; + + reg = __raw_readl(CCM_CSCR) & ~CCM_CSCR_CLKO_MASK; + reg |= i << CCM_CSCR_CLKO_OFFSET; + __raw_writel(reg, CCM_CSCR); + + if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) { + clk->set_rate = _clk_parent_set_rate; + clk->round_rate = _clk_parent_round_rate; + } else { + clk->set_rate = NULL; + clk->round_rate = NULL; + } + + return 0; +} + +static struct clk clko_clk = { + .name = "clko_clk", + .set_parent = clko_set_parent, +}; + +static struct clk dma_clk = { + .name = "dma_clk", + .parent = &hclk, + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, + .enable = _clk_enable, + .enable_reg = SCM_GCCR, + .enable_shift = SCM_GCCR_DMA_CLK_EN_OFFSET, + .disable = _clk_disable, +}; + +static struct clk csi_clk = { + .name = "csi_clk", + .parent = &hclk, + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, + .enable = _clk_enable, + .enable_reg = SCM_GCCR, + .enable_shift = SCM_GCCR_CSI_CLK_EN_OFFSET, + .disable = _clk_disable, +}; + +static struct clk mma_clk = { + .name = "mma_clk", + .parent = &hclk, + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, + .enable = _clk_enable, + .enable_reg = SCM_GCCR, + .enable_shift = SCM_GCCR_MMA_CLK_EN_OFFSET, + .disable = _clk_disable, +}; + +static struct clk usbd_clk = { + .name = "usbd_clk", + .parent = &clk48m, + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, + .enable = _clk_enable, + .enable_reg = SCM_GCCR, + .enable_shift = SCM_GCCR_USBD_CLK_EN_OFFSET, + .disable = _clk_disable, +}; + +static struct clk gpt_clk = { + .name = "gpt_clk", + .parent = &perclk[0], + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, +}; + +static struct clk uart_clk = { + .name = "uart_clk", + .parent = &perclk[0], + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, +}; + +static struct clk i2c_clk = { + .name = "i2c_clk", + .parent = &hclk, + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, +}; + +static struct clk spi_clk = { + .name = "spi_clk", + .parent = &perclk[1], + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, +}; + +static struct clk sdhc_clk = { + .name = "sdhc_clk", + .parent = &perclk[1], + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, +}; + +static struct clk lcdc_clk = { + .name = "lcdc_clk", + .parent = &perclk[1], + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, +}; + +static struct clk mshc_clk = { + .name = "mshc_clk", + .parent = &hclk, + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, +}; + +static struct clk ssi_clk = { + .name = "ssi_clk", + .parent = &perclk[2], + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate, +}; + +static struct clk rtc_clk = { + .name = "rtc_clk", + .parent = &clk32, +}; + +static struct clk *mxc_clks[] = { + &clk16m, + &clk32, + &clk32_premult, + &prem_clk, + &system_clk, + &mcu_clk, + &fclk, + &hclk, + &clk48m, + &perclk[0], + &perclk[1], + &perclk[2], + &clko_clk, + &dma_clk, + &csi_clk, + &mma_clk, + &usbd_clk, + &gpt_clk, + &uart_clk, + &i2c_clk, + &spi_clk, + &sdhc_clk, + &lcdc_clk, + &mshc_clk, + &ssi_clk, + &rtc_clk, +}; + +int __init mxc_clocks_init(unsigned long fref) +{ + struct clk **clkp; + unsigned int reg; + + /* disable clocks we are able to */ + __raw_writel(0, SCM_GCCR); + + clk32_rate = fref; + reg = __raw_readl(CCM_CSCR); + + /* detect clock reference for system PLL */ + if (reg & CCM_CSCR_SYSTEM_SEL) { + prem_clk.parent = &clk16m; + } else { + /* ensure that oscillator is disabled */ + reg &= ~(1 << CCM_CSCR_OSC_EN_SHIFT); + __raw_writel(reg, CCM_CSCR); + prem_clk.parent = &clk32_premult; + } + + /* detect reference for CLKO */ + reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET; + clko_clk.parent = (struct clk *)clko_clocks[reg]; + + for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) + clk_register(*clkp); + + clk_enable(&hclk); + clk_enable(&fclk); + + return 0; +} diff --git a/arch/arm/mach-mx1/crm_regs.h b/arch/arm/mach-mx1/crm_regs.h new file mode 100644 index 0000000..22e866f --- /dev/null +++ b/arch/arm/mach-mx1/crm_regs.h @@ -0,0 +1,55 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> + * + * This file may be distributed under the terms of the GNU General + * Public License, version 2. + */ + +#ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX1_CRM_REGS_H__ + +#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) +#define SCM_BASE IO_ADDRESS(SCM_BASE_ADDR) + +/* CCM register addresses */ +#define CCM_CSCR (CCM_BASE + 0x0) +#define CCM_MPCTL0 (CCM_BASE + 0x4) +#define CCM_MPCTL1 (CCM_BASE + 0x8) +#define CCM_SPCTL0 (CCM_BASE + 0xC) +#define CCM_SPCTL1 (CCM_BASE + 0x10) +#define CCM_PCDR (CCM_BASE + 0x20) + +#define CCM_CSCR_CLKO_OFFSET 29 +#define CCM_CSCR_CLKO_MASK (0x7 << 29) +#define CCM_CSCR_USB_OFFSET 26 +#define CCM_CSCR_USB_MASK (0x7 << 26) +#define CCM_CSCR_SPLL_RESTART (1 << 22) +#define CCM_CSCR_MPLL_RESTART (1 << 21) +#define CCM_CSCR_OSC_EN_SHIFT 17 +#define CCM_CSCR_SYSTEM_SEL (1 << 16) +#define CCM_CSCR_BCLK_OFFSET 10 +#define CCM_CSCR_BCLK_MASK (0xF << 10) +#define CCM_CSCR_PRESC (1 << 15) +#define CCM_CSCR_SPEN (1 << 1) +#define CCM_CSCR_MPEN (1 << 0) + +#define CCM_PCDR_PCLK3_OFFSET 16 +#define CCM_PCDR_PCLK3_MASK (0x7F << 16) +#define CCM_PCDR_PCLK2_OFFSET 4 +#define CCM_PCDR_PCLK2_MASK (0xF << 4) +#define CCM_PCDR_PCLK1_OFFSET 0 +#define CCM_PCDR_PCLK1_MASK 0xF + +/* SCM register addresses */ +#define SCM_SIDR (SCM_BASE + 0x0) +#define SCM_FMCR (SCM_BASE + 0x4) +#define SCM_GPCR (SCM_BASE + 0x8) +#define SCM_GCCR (SCM_BASE + 0xC) + +#define SCM_GCCR_DMA_CLK_EN_OFFSET 3 +#define SCM_GCCR_CSI_CLK_EN_OFFSET 2 +#define SCM_GCCR_MMA_CLK_EN_OFFSET 1 +#define SCM_GCCR_USBD_CLK_EN_OFFSET 0 + +#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */ diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c new file mode 100644 index 0000000..686d8d2 --- /dev/null +++ b/arch/arm/mach-mx1/devices.c @@ -0,0 +1,260 @@ +/* + * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Sascha Hauer, kernel@pengutronix.de + * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> + * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <mach/hardware.h> + +static struct resource imx_csi_resources[] = { + [0] = { + .start = 0x00224000, + .end = 0x00224010, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CSI_INT, + .end = CSI_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 imx_csi_dmamask = 0xffffffffUL; + +struct platform_device imx_csi_device = { + .name = "imx-csi", + .id = 0, /* This is used to put cameras on this interface */ + .dev = { + .dma_mask = &imx_csi_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = imx_csi_resources, + .num_resources = ARRAY_SIZE(imx_csi_resources), +}; + +static struct resource imx_i2c_resources[] = { + [0] = { + .start = 0x00217000, + .end = 0x00217010, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = I2C_INT, + .end = I2C_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_i2c_device = { + .name = "imx-i2c", + .id = 0, + .resource = imx_i2c_resources, + .num_resources = ARRAY_SIZE(imx_i2c_resources), +}; + +static struct resource imx_uart1_resources[] = { + [0] = { + .start = UART1_BASE_ADDR, + .end = UART1_BASE_ADDR + 0xD0, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = UART1_MINT_RX, + .end = UART1_MINT_RX, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = UART1_MINT_TX, + .end = UART1_MINT_TX, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = UART1_MINT_RTS, + .end = UART1_MINT_RTS, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_uart1_device = { + .name = "imx-uart", + .id = 0, + .num_resources = ARRAY_SIZE(imx_uart1_resources), + .resource = imx_uart1_resources, +}; + +static struct resource imx_uart2_resources[] = { + [0] = { + .start = UART2_BASE_ADDR, + .end = UART2_BASE_ADDR + 0xD0, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = UART2_MINT_RX, + .end = UART2_MINT_RX, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = UART2_MINT_TX, + .end = UART2_MINT_TX, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = UART2_MINT_RTS, + .end = UART2_MINT_RTS, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_uart2_device = { + .name = "imx-uart", + .id = 1, + .num_resources = ARRAY_SIZE(imx_uart2_resources), + .resource = imx_uart2_resources, +}; + +static struct resource imx_rtc_resources[] = { + [0] = { + .start = 0x00204000, + .end = 0x00204024, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = RTC_INT, + .end = RTC_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = RTC_SAMINT, + .end = RTC_SAMINT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_rtc_device = { + .name = "rtc-imx", + .id = 0, + .resource = imx_rtc_resources, + .num_resources = ARRAY_SIZE(imx_rtc_resources), +}; + +static struct resource imx_wdt_resources[] = { + [0] = { + .start = 0x00201000, + .end = 0x00201008, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = WDT_INT, + .end = WDT_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_wdt_device = { + .name = "imx-wdt", + .id = 0, + .resource = imx_wdt_resources, + .num_resources = ARRAY_SIZE(imx_wdt_resources), +}; + +static struct resource imx_usb_resources[] = { + [0] = { + .start = 0x00212000, + .end = 0x00212148, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = USBD_INT0, + .end = USBD_INT0, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = USBD_INT1, + .end = USBD_INT1, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = USBD_INT2, + .end = USBD_INT2, + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = USBD_INT3, + .end = USBD_INT3, + .flags = IORESOURCE_IRQ, + }, + [5] = { + .start = USBD_INT4, + .end = USBD_INT4, + .flags = IORESOURCE_IRQ, + }, + [6] = { + .start = USBD_INT5, + .end = USBD_INT5, + .flags = IORESOURCE_IRQ, + }, + [7] = { + .start = USBD_INT6, + .end = USBD_INT6, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_usb_device = { + .name = "imx_udc", + .id = 0, + .num_resources = ARRAY_SIZE(imx_usb_resources), + .resource = imx_usb_resources, +}; + +/* GPIO port description */ +static struct mxc_gpio_port imx_gpio_ports[] = { + [0] = { + .chip.label = "gpio-0", + .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR), + .irq = GPIO_INT_PORTA, + .virtual_irq_start = MXC_GPIO_IRQ_START + }, + [1] = { + .chip.label = "gpio-1", + .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100), + .irq = GPIO_INT_PORTB, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 + }, + [2] = { + .chip.label = "gpio-2", + .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200), + .irq = GPIO_INT_PORTC, + .virtual_irq_start = MXC_GPIO_IRQ_START + 64 + }, + [3] = { + .chip.label = "gpio-3", + .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300), + .irq = GPIO_INT_PORTD, + .virtual_irq_start = MXC_GPIO_IRQ_START + 96 + } +}; + +int __init mxc_register_gpios(void) +{ + return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); +} diff --git a/arch/arm/mach-mx1/devices.h b/arch/arm/mach-mx1/devices.h new file mode 100644 index 0000000..0da5d7c --- /dev/null +++ b/arch/arm/mach-mx1/devices.h @@ -0,0 +1,7 @@ +extern struct platform_device imx_csi_device; +extern struct platform_device imx_i2c_device; +extern struct platform_device imx_uart1_device; +extern struct platform_device imx_uart2_device; +extern struct platform_device imx_rtc_device; +extern struct platform_device imx_wdt_device; +extern struct platform_device imx_usb_device; diff --git a/arch/arm/mach-integrator/include/mach/dma.h b/arch/arm/mach-mx1/generic.c index fbebe85..0dec6f3 100644 --- a/arch/arm/mach-integrator/include/mach/dma.h +++ b/arch/arm/mach-mx1/generic.c @@ -1,7 +1,9 @@ /* - * arch/arm/mach-integrator/include/mach/dma.h + * author: Sascha Hauer + * Created: april 20th, 2004 + * Copyright: Synertronixx GmbH * - * Copyright (C) 1997,1998 Russell King + * Common code for i.MX machines * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,4 +18,26 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> + +#include <asm/mach/map.h> + +#include <mach/hardware.h> + +static struct map_desc imx_io_desc[] __initdata = { + { + .virtual = IMX_IO_BASE, + .pfn = __phys_to_pfn(IMX_IO_PHYS), + .length = IMX_IO_SIZE, + .type = MT_DEVICE + } +}; + +void __init mxc_map_io(void) +{ + iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); +} diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mx1ads.c new file mode 100644 index 0000000..2e4b185 --- /dev/null +++ b/arch/arm/mach-mx1/mx1ads.c @@ -0,0 +1,148 @@ +/* + * arch/arm/mach-imx/mx1ads.c + * + * Initially based on: + * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c + * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de> + * + * 2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx1-mx2.h> +#include "devices.h" + +/* + * UARTs platform data + */ +static int mxc_uart1_pins[] = { + PC9_PF_UART1_CTS, + PC10_PF_UART1_RTS, + PC11_PF_UART1_TXD, + PC12_PF_UART1_RXD, +}; + +static int uart1_mxc_init(struct platform_device *pdev) +{ + return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, + ARRAY_SIZE(mxc_uart1_pins), "UART1"); +} + +static int uart1_mxc_exit(struct platform_device *pdev) +{ + mxc_gpio_release_multiple_pins(mxc_uart1_pins, + ARRAY_SIZE(mxc_uart1_pins)); + return 0; +} + +static int mxc_uart2_pins[] = { + PB28_PF_UART2_CTS, + PB29_PF_UART2_RTS, + PB30_PF_UART2_TXD, + PB31_PF_UART2_RXD, +}; + +static int uart2_mxc_init(struct platform_device *pdev) +{ + return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, + ARRAY_SIZE(mxc_uart2_pins), "UART2"); +} + +static int uart2_mxc_exit(struct platform_device *pdev) +{ + mxc_gpio_release_multiple_pins(mxc_uart2_pins, + ARRAY_SIZE(mxc_uart2_pins)); + return 0; +} + +static struct imxuart_platform_data uart_pdata[] = { + { + .init = uart1_mxc_init, + .exit = uart1_mxc_exit, + .flags = IMXUART_HAVE_RTSCTS, + }, { + .init = uart2_mxc_init, + .exit = uart2_mxc_exit, + .flags = IMXUART_HAVE_RTSCTS, + }, +}; + +/* + * Physmap flash + */ + +static struct physmap_flash_data mx1ads_flash_data = { + .width = 4, /* bankwidth in bytes */ +}; + +static struct resource flash_resource = { + .start = IMX_CS0_PHYS, + .end = IMX_CS0_PHYS + SZ_32M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device flash_device = { + .name = "physmap-flash", + .id = 0, + .resource = &flash_resource, + .num_resources = 1, +}; + +/* + * Board init + */ +static void __init mx1ads_init(void) +{ + /* UART */ + mxc_register_device(&imx_uart1_device, &uart_pdata[0]); + mxc_register_device(&imx_uart2_device, &uart_pdata[1]); + + /* Physmap flash */ + mxc_register_device(&flash_device, &mx1ads_flash_data); +} + +static void __init mx1ads_timer_init(void) +{ + mxc_clocks_init(32000); + mxc_timer_init("gpt_clk"); +} + +struct sys_timer mx1ads_timer = { + .init = mx1ads_timer_init, +}; + +MACHINE_START(MX1ADS, "Freescale MX1ADS") + /* Maintainer: Sascha Hauer, Pengutronix */ + .phys_io = IMX_IO_PHYS, + .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mxc_map_io, + .init_irq = mxc_init_irq, + .timer = &mx1ads_timer, + .init_machine = mx1ads_init, +MACHINE_END + +MACHINE_START(MXLADS, "Freescale MXLADS") + .phys_io = IMX_IO_PHYS, + .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mxc_map_io, + .init_irq = mxc_init_irq, + .timer = &mx1ads_timer, + .init_machine = mx1ads_init, +MACHINE_END diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index bd0559d..af121f5 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -190,38 +190,72 @@ struct platform_device mxc_wdt = { .resource = mxc_wdt_resources, }; +static struct resource mxc_w1_master_resources[] = { + { + .start = OWIRE_BASE_ADDR, + .end = OWIRE_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxc_w1_master_device = { + .name = "mxc_w1", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_w1_master_resources), + .resource = mxc_w1_master_resources, +}; + +static struct resource mxc_nand_resources[] = { + { + .start = NFC_BASE_ADDR, + .end = NFC_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM + }, { + .start = MXC_INT_NANDFC, + .end = MXC_INT_NANDFC, + .flags = IORESOURCE_IRQ + }, +}; + +struct platform_device mxc_nand_device = { + .name = "mxc_nand", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_nand_resources), + .resource = mxc_nand_resources, +}; + /* GPIO port description */ static struct mxc_gpio_port imx_gpio_ports[] = { [0] = { .chip.label = "gpio-0", .irq = MXC_INT_GPIO, .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0), - .virtual_irq_start = MXC_MAX_INT_LINES, + .virtual_irq_start = MXC_GPIO_IRQ_START, }, [1] = { .chip.label = "gpio-1", .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1), - .virtual_irq_start = MXC_MAX_INT_LINES + 32, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32, }, [2] = { .chip.label = "gpio-2", .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2), - .virtual_irq_start = MXC_MAX_INT_LINES + 64, + .virtual_irq_start = MXC_GPIO_IRQ_START + 64, }, [3] = { .chip.label = "gpio-3", .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3), - .virtual_irq_start = MXC_MAX_INT_LINES + 96, + .virtual_irq_start = MXC_GPIO_IRQ_START + 96, }, [4] = { .chip.label = "gpio-4", .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4), - .virtual_irq_start = MXC_MAX_INT_LINES + 128, + .virtual_irq_start = MXC_GPIO_IRQ_START + 128, }, [5] = { .chip.label = "gpio-5", .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5), - .virtual_irq_start = MXC_MAX_INT_LINES + 160, + .virtual_irq_start = MXC_GPIO_IRQ_START + 160, } }; diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h index c77a4b8..1e8cb57 100644 --- a/arch/arm/mach-mx2/devices.h +++ b/arch/arm/mach-mx2/devices.h @@ -12,4 +12,5 @@ extern struct platform_device mxc_uart_device2; extern struct platform_device mxc_uart_device3; extern struct platform_device mxc_uart_device4; extern struct platform_device mxc_uart_device5; - +extern struct platform_device mxc_w1_master_device; +extern struct platform_device mxc_nand_device; diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c index 56e22d3..2b5c67f 100644 --- a/arch/arm/mach-mx2/mx27ads.c +++ b/arch/arm/mach-mx2/mx27ads.c @@ -68,15 +68,14 @@ static int mxc_uart0_pins[] = { static int uart_mxc_port0_init(struct platform_device *pdev) { return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, - ARRAY_SIZE(mxc_uart0_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "UART0"); + ARRAY_SIZE(mxc_uart0_pins), "UART0"); } static int uart_mxc_port0_exit(struct platform_device *pdev) { - return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, - ARRAY_SIZE(mxc_uart0_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "UART0"); + mxc_gpio_release_multiple_pins(mxc_uart0_pins, + ARRAY_SIZE(mxc_uart0_pins)); + return 0; } static int mxc_uart1_pins[] = { @@ -89,15 +88,14 @@ static int mxc_uart1_pins[] = { static int uart_mxc_port1_init(struct platform_device *pdev) { return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "UART1"); + ARRAY_SIZE(mxc_uart1_pins), "UART1"); } static int uart_mxc_port1_exit(struct platform_device *pdev) { - return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "UART1"); + mxc_gpio_release_multiple_pins(mxc_uart1_pins, + ARRAY_SIZE(mxc_uart1_pins)); + return 0; } static int mxc_uart2_pins[] = { @@ -110,15 +108,14 @@ static int mxc_uart2_pins[] = { static int uart_mxc_port2_init(struct platform_device *pdev) { return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, - ARRAY_SIZE(mxc_uart2_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "UART2"); + ARRAY_SIZE(mxc_uart2_pins), "UART2"); } static int uart_mxc_port2_exit(struct platform_device *pdev) { - return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, - ARRAY_SIZE(mxc_uart2_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "UART2"); + mxc_gpio_release_multiple_pins(mxc_uart2_pins, + ARRAY_SIZE(mxc_uart2_pins)); + return 0; } static int mxc_uart3_pins[] = { @@ -131,15 +128,13 @@ static int mxc_uart3_pins[] = { static int uart_mxc_port3_init(struct platform_device *pdev) { return mxc_gpio_setup_multiple_pins(mxc_uart3_pins, - ARRAY_SIZE(mxc_uart3_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "UART3"); + ARRAY_SIZE(mxc_uart3_pins), "UART3"); } static int uart_mxc_port3_exit(struct platform_device *pdev) { - return mxc_gpio_setup_multiple_pins(mxc_uart3_pins, - ARRAY_SIZE(mxc_uart3_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "UART3"); + mxc_gpio_release_multiple_pins(mxc_uart3_pins, + ARRAY_SIZE(mxc_uart3_pins)); } static int mxc_uart4_pins[] = { @@ -152,15 +147,14 @@ static int mxc_uart4_pins[] = { static int uart_mxc_port4_init(struct platform_device *pdev) { return mxc_gpio_setup_multiple_pins(mxc_uart4_pins, - ARRAY_SIZE(mxc_uart4_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "UART4"); + ARRAY_SIZE(mxc_uart4_pins), "UART4"); } static int uart_mxc_port4_exit(struct platform_device *pdev) { - return mxc_gpio_setup_multiple_pins(mxc_uart4_pins, - ARRAY_SIZE(mxc_uart4_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "UART4"); + mxc_gpio_release_multiple_pins(mxc_uart4_pins, + ARRAY_SIZE(mxc_uart4_pins)); + return 0; } static int mxc_uart5_pins[] = { @@ -173,15 +167,14 @@ static int mxc_uart5_pins[] = { static int uart_mxc_port5_init(struct platform_device *pdev) { return mxc_gpio_setup_multiple_pins(mxc_uart5_pins, - ARRAY_SIZE(mxc_uart5_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "UART5"); + ARRAY_SIZE(mxc_uart5_pins), "UART5"); } static int uart_mxc_port5_exit(struct platform_device *pdev) { - return mxc_gpio_setup_multiple_pins(mxc_uart5_pins, - ARRAY_SIZE(mxc_uart5_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "UART5"); + mxc_gpio_release_multiple_pins(mxc_uart5_pins, + ARRAY_SIZE(mxc_uart5_pins)); + return 0; } static struct platform_device *platform_devices[] __initdata = { @@ -212,15 +205,13 @@ static int mxc_fec_pins[] = { static void gpio_fec_active(void) { mxc_gpio_setup_multiple_pins(mxc_fec_pins, - ARRAY_SIZE(mxc_fec_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "FEC"); + ARRAY_SIZE(mxc_fec_pins), "FEC"); } static void gpio_fec_inactive(void) { - mxc_gpio_setup_multiple_pins(mxc_fec_pins, - ARRAY_SIZE(mxc_fec_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "FEC"); + mxc_gpio_release_multiple_pins(mxc_fec_pins, + ARRAY_SIZE(mxc_fec_pins)); } static struct imxuart_platform_data uart_pdata[] = { diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c index 7f55746..dfd4156 100644 --- a/arch/arm/mach-mx2/pcm038.c +++ b/arch/arm/mach-mx2/pcm038.c @@ -19,6 +19,7 @@ #include <linux/platform_device.h> #include <linux/mtd/physmap.h> +#include <linux/mtd/plat-ram.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <mach/common.h> @@ -27,10 +28,36 @@ #include <asm/mach/time.h> #include <mach/imx-uart.h> #include <mach/board-pcm038.h> +#include <mach/mxc_nand.h> #include "devices.h" /* + * Phytec's PCM038 comes with 2MiB battery buffered SRAM, + * 16 bit width + */ + +static struct platdata_mtd_ram pcm038_sram_data = { + .bankwidth = 2, +}; + +static struct resource pcm038_sram_resource = { + .start = CS1_BASE_ADDR, + .end = CS1_BASE_ADDR + 512 * 1024 - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device pcm038_sram_mtd_device = { + .name = "mtd-ram", + .id = 0, + .dev = { + .platform_data = &pcm038_sram_data, + }, + .num_resources = 1, + .resource = &pcm038_sram_resource, +}; + +/* * Phytec's phyCORE-i.MX27 comes with 32MiB flash, * 16 bit width */ @@ -64,15 +91,14 @@ static int mxc_uart0_pins[] = { static int uart_mxc_port0_init(struct platform_device *pdev) { return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, - ARRAY_SIZE(mxc_uart0_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "UART0"); + ARRAY_SIZE(mxc_uart0_pins), "UART0"); } static int uart_mxc_port0_exit(struct platform_device *pdev) { - return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, - ARRAY_SIZE(mxc_uart0_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "UART0"); + mxc_gpio_release_multiple_pins(mxc_uart0_pins, + ARRAY_SIZE(mxc_uart0_pins)); + return 0; } static int mxc_uart1_pins[] = { @@ -85,15 +111,14 @@ static int mxc_uart1_pins[] = { static int uart_mxc_port1_init(struct platform_device *pdev) { return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "UART1"); + ARRAY_SIZE(mxc_uart1_pins), "UART1"); } static int uart_mxc_port1_exit(struct platform_device *pdev) { - return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "UART1"); + mxc_gpio_release_multiple_pins(mxc_uart1_pins, + ARRAY_SIZE(mxc_uart1_pins)); + return 0; } static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS, @@ -104,15 +129,14 @@ static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS, static int uart_mxc_port2_init(struct platform_device *pdev) { return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, - ARRAY_SIZE(mxc_uart2_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "UART2"); + ARRAY_SIZE(mxc_uart2_pins), "UART2"); } static int uart_mxc_port2_exit(struct platform_device *pdev) { - return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, - ARRAY_SIZE(mxc_uart2_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "UART2"); + mxc_gpio_release_multiple_pins(mxc_uart2_pins, + ARRAY_SIZE(mxc_uart2_pins)); + return 0; } static struct imxuart_platform_data uart_pdata[] = { @@ -155,29 +179,47 @@ static int mxc_fec_pins[] = { static void gpio_fec_active(void) { mxc_gpio_setup_multiple_pins(mxc_fec_pins, - ARRAY_SIZE(mxc_fec_pins), - MXC_GPIO_ALLOC_MODE_NORMAL, "FEC"); + ARRAY_SIZE(mxc_fec_pins), "FEC"); } static void gpio_fec_inactive(void) { - mxc_gpio_setup_multiple_pins(mxc_fec_pins, - ARRAY_SIZE(mxc_fec_pins), - MXC_GPIO_ALLOC_MODE_RELEASE, "FEC"); + mxc_gpio_release_multiple_pins(mxc_fec_pins, + ARRAY_SIZE(mxc_fec_pins)); } +static struct mxc_nand_platform_data pcm038_nand_board_info = { + .width = 1, + .hw_ecc = 1, +}; + static struct platform_device *platform_devices[] __initdata = { &pcm038_nor_mtd_device, + &mxc_w1_master_device, + &pcm038_sram_mtd_device, }; +/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and + * setup other stuffs to access the sram. */ +static void __init pcm038_init_sram(void) +{ + __raw_writel(0x0000d843, CSCR_U(1)); + __raw_writel(0x22252521, CSCR_L(1)); + __raw_writel(0x22220a00, CSCR_A(1)); +} + static void __init pcm038_init(void) { gpio_fec_active(); + pcm038_init_sram(); mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); + mxc_gpio_mode(PE16_AF_RTCK); /* OWIRE */ + mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); #ifdef CONFIG_MACH_PCM970_BASEBOARD diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index db9431d..e79659e 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -21,5 +21,19 @@ config MACH_MX31LITE Include support for MX31 LITEKIT platform. This includes specific configurations for the board and its peripherals. +config MACH_MX31_3DS + bool "Support MX31PDK (3DS)" + default n + help + Include support for MX31PDK (3DS) platform. This includes specific + configurations for the board and its peripherals. + +config MACH_MX31MOBOARD + bool "Support mx31moboard platforms (EPFL Mobots group)" + default n + help + Include support for mx31moboard platform. This includes specific + configurations for the board and its peripherals. + endmenu diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 8b21abb..5a151540 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -8,3 +8,5 @@ obj-y := mm.o clock.o devices.o iomux.o obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o obj-$(CONFIG_MACH_PCM037) += pcm037.o +obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o +obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c index 9f14a87..b1746aa 100644 --- a/arch/arm/mach-mx3/clock.c +++ b/arch/arm/mach-mx3/clock.c @@ -24,6 +24,7 @@ #include <linux/err.h> #include <linux/io.h> #include <mach/clock.h> +#include <mach/hardware.h> #include <asm/div64.h> #include "crm_regs.h" diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index a6bdcc0..1d46cb4 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -125,19 +125,19 @@ static struct mxc_gpio_port imx_gpio_ports[] = { .chip.label = "gpio-0", .base = IO_ADDRESS(GPIO1_BASE_ADDR), .irq = MXC_INT_GPIO1, - .virtual_irq_start = MXC_GPIO_INT_BASE + .virtual_irq_start = MXC_GPIO_IRQ_START, }, [1] = { .chip.label = "gpio-1", .base = IO_ADDRESS(GPIO2_BASE_ADDR), .irq = MXC_INT_GPIO2, - .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN + .virtual_irq_start = MXC_GPIO_IRQ_START + 32, }, [2] = { .chip.label = "gpio-2", .base = IO_ADDRESS(GPIO3_BASE_ADDR), .irq = MXC_INT_GPIO3, - .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 2 + .virtual_irq_start = MXC_GPIO_IRQ_START + 64, } }; @@ -145,3 +145,37 @@ int __init mxc_register_gpios(void) { return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); } + +static struct resource mxc_w1_master_resources[] = { + { + .start = OWIRE_BASE_ADDR, + .end = OWIRE_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxc_w1_master_device = { + .name = "mxc_w1", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_w1_master_resources), + .resource = mxc_w1_master_resources, +}; + +static struct resource mxc_nand_resources[] = { + { + .start = NFC_BASE_ADDR, + .end = NFC_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM + }, { + .start = MXC_INT_NANDFC, + .end = MXC_INT_NANDFC, + .flags = IORESOURCE_IRQ + }, +}; + +struct platform_device mxc_nand_device = { + .name = "mxc_nand", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_nand_resources), + .resource = mxc_nand_resources, +}; diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index 4dc03f9..9949ef4 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h @@ -4,3 +4,5 @@ extern struct platform_device mxc_uart_device1; extern struct platform_device mxc_uart_device2; extern struct platform_device mxc_uart_device3; extern struct platform_device mxc_uart_device4; +extern struct platform_device mxc_w1_master_device; +extern struct platform_device mxc_nand_device; diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c index 6e664be..7a5088b 100644 --- a/arch/arm/mach-mx3/iomux.c +++ b/arch/arm/mach-mx3/iomux.c @@ -74,17 +74,18 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) u32 field, l; void __iomem *reg; - reg = IOMUXSW_PAD_CTL + (pin + 2) / 3; + pin &= IOMUX_PADNUM_MASK; + reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4; field = (pin + 2) % 3; - pr_debug("%s: reg offset = 0x%x field = %d\n", + pr_debug("%s: reg offset = 0x%x, field = %d\n", __func__, (pin + 2) / 3, field); spin_lock(&gpio_mux_lock); l = __raw_readl(reg); - l &= ~(0x1ff << (field * 9)); - l |= config << (field * 9); + l &= ~(0x1ff << (field * 10)); + l |= config << (field * 10); __raw_writel(l, reg); spin_unlock(&gpio_mux_lock); diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c new file mode 100644 index 0000000..c29098a --- /dev/null +++ b/arch/arm/mach-mx3/mx31moboard.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2008 Valentin Longchamp, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/types.h> +#include <linux/init.h> + +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/partitions.h> +#include <linux/memory.h> + +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/mach/map.h> +#include <mach/common.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx3.h> + +#include "devices.h" + +static struct physmap_flash_data mx31moboard_flash_data = { + .width = 2, +}; + +static struct resource mx31moboard_flash_resource = { + .start = 0xa0000000, + .end = 0xa1ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device mx31moboard_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &mx31moboard_flash_data, + }, + .resource = &mx31moboard_flash_resource, + .num_resources = 1, +}; + +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct platform_device *devices[] __initdata = { + &mx31moboard_flash, +}; + +/* + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + platform_add_devices(devices, ARRAY_SIZE(devices)); + + mxc_iomux_mode(MX31_PIN_CTS1__CTS1); + mxc_iomux_mode(MX31_PIN_RTS1__RTS1); + mxc_iomux_mode(MX31_PIN_TXD1__TXD1); + mxc_iomux_mode(MX31_PIN_RXD1__RXD1); + + mxc_register_device(&mxc_uart_device0, &uart_pdata); + + mxc_iomux_mode(MX31_PIN_CTS2__CTS2); + mxc_iomux_mode(MX31_PIN_RTS2__RTS2); + mxc_iomux_mode(MX31_PIN_TXD2__TXD2); + mxc_iomux_mode(MX31_PIN_RXD2__RXD2); + + mxc_register_device(&mxc_uart_device1, &uart_pdata); + + mxc_iomux_mode(MX31_PIN_PC_RST__CTS5); + mxc_iomux_mode(MX31_PIN_PC_VS2__RTS5); + mxc_iomux_mode(MX31_PIN_PC_BVD2__TXD5); + mxc_iomux_mode(MX31_PIN_PC_BVD1__RXD5); + + mxc_register_device(&mxc_uart_device4, &uart_pdata); +} + +/* + * This structure defines static mappings for the mx31moboard. + */ +static struct map_desc mx31moboard_io_desc[] __initdata = { + { + .virtual = AIPS1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), + .length = AIPS1_SIZE, + .type = MT_DEVICE_NONSHARED + }, { + .virtual = AIPS2_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), + .length = AIPS2_SIZE, + .type = MT_DEVICE_NONSHARED + }, +}; + +/* + * Set up static virtual mappings. + */ +void __init mx31moboard_map_io(void) +{ + mxc_map_io(); + iotable_init(mx31moboard_io_desc, ARRAY_SIZE(mx31moboard_io_desc)); +} + +static void __init mx31moboard_timer_init(void) +{ + mxc_clocks_init(26000000); + mxc_timer_init("ipg_clk.0"); +} + +struct sys_timer mx31moboard_timer = { + .init = mx31moboard_timer_init, +}; + +MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") + /* Maintainer: Valentin Longchamp, EPFL Mobots group */ + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mx31moboard_map_io, + .init_irq = mxc_init_irq, + .init_machine = mxc_board_init, + .timer = &mx31moboard_timer, +MACHINE_END + diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c new file mode 100644 index 0000000..d464d06 --- /dev/null +++ b/arch/arm/mach-mx3/mx31pdk.c @@ -0,0 +1,115 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/types.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/irq.h> + +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/memory.h> +#include <asm/mach/map.h> +#include <mach/common.h> +#include <mach/board-mx31pdk.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx3.h> +#include "devices.h" + +/*! + * @file mx31pdk.c + * + * @brief This file contains the board-specific initialization routines. + * + * @ingroup System + */ + +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static inline void mxc_init_imx_uart(void) +{ + mxc_iomux_mode(MX31_PIN_CTS1__CTS1); + mxc_iomux_mode(MX31_PIN_RTS1__RTS1); + mxc_iomux_mode(MX31_PIN_TXD1__TXD1); + mxc_iomux_mode(MX31_PIN_RXD1__RXD1); + + mxc_register_device(&mxc_uart_device0, &uart_pdata); +} + +/*! + * This structure defines static mappings for the i.MX31PDK board. + */ +static struct map_desc mx31pdk_io_desc[] __initdata = { + { + .virtual = AIPS1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), + .length = AIPS1_SIZE, + .type = MT_DEVICE_NONSHARED + }, { + .virtual = AIPS2_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), + .length = AIPS2_SIZE, + .type = MT_DEVICE_NONSHARED + }, +}; + +/*! + * Set up static virtual mappings. + */ +static void __init mx31pdk_map_io(void) +{ + mxc_map_io(); + iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc)); +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_init_imx_uart(); +} + +static void __init mx31pdk_timer_init(void) +{ + mxc_clocks_init(26000000); + mxc_timer_init("ipg_clk.0"); +} + +static struct sys_timer mx31pdk_timer = { + .init = mx31pdk_timer_init, +}; + +/* + * The following uses standard kernel macros defined in arch.h in order to + * initialize __mach_desc_MX31PDK data structure. + */ +MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") + /* Maintainer: Freescale Semiconductor, Inc. */ + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mx31pdk_map_io, + .init_irq = mxc_init_irq, + .init_machine = mxc_board_init, + .timer = &mx31pdk_timer, +MACHINE_END diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c index 843f68c..8cea825 100644 --- a/arch/arm/mach-mx3/pcm037.c +++ b/arch/arm/mach-mx3/pcm037.c @@ -21,7 +21,11 @@ #include <linux/platform_device.h> #include <linux/mtd/physmap.h> +#include <linux/mtd/plat-ram.h> #include <linux/memory.h> +#include <linux/gpio.h> +#include <linux/smc911x.h> +#include <linux/interrupt.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -32,6 +36,7 @@ #include <mach/imx-uart.h> #include <mach/iomux-mx3.h> #include <mach/board-pcm037.h> +#include <mach/mxc_nand.h> #include "devices.h" @@ -59,8 +64,63 @@ static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; +static struct resource smc911x_resources[] = { + [0] = { + .start = CS1_BASE_ADDR + 0x300, + .end = CS1_BASE_ADDR + 0x300 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), + .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smc911x_platdata smc911x_info = { + .flags = SMC911X_USE_32BIT, + .irq_flags = IRQF_SHARED | IRQF_TRIGGER_LOW, +}; + +static struct platform_device pcm037_eth = { + .name = "smc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smc911x_resources), + .resource = smc911x_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static struct platdata_mtd_ram pcm038_sram_data = { + .bankwidth = 2, +}; + +static struct resource pcm038_sram_resource = { + .start = CS4_BASE_ADDR, + .end = CS4_BASE_ADDR + 512 * 1024 - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device pcm037_sram_device = { + .name = "mtd-ram", + .id = 0, + .dev = { + .platform_data = &pcm038_sram_data, + }, + .num_resources = 1, + .resource = &pcm038_sram_resource, +}; + +static struct mxc_nand_platform_data pcm037_nand_board_info = { + .width = 1, + .hw_ecc = 1, +}; + static struct platform_device *devices[] __initdata = { &pcm037_flash, + &pcm037_eth, + &pcm037_sram_device, }; /* @@ -81,6 +141,16 @@ static void __init mxc_board_init(void) mxc_iomux_mode(MX31_PIN_CSPI3_MISO__TXD3); mxc_register_device(&mxc_uart_device2, &uart_pdata); + + mxc_iomux_mode(MX31_PIN_BATT_LINE__OWIRE); + mxc_register_device(&mxc_w1_master_device, NULL); + + /* SMSC9215 IRQ pin */ + mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)); + if (!gpio_request(MX31_PIN_GPIO3_1, "pcm037-eth")) + gpio_direction_input(MX31_PIN_GPIO3_1); + + mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); } /* diff --git a/arch/arm/mach-netx/fb.c b/arch/arm/mach-netx/fb.c index 24c7965..8f1f992 100644 --- a/arch/arm/mach-netx/fb.c +++ b/arch/arm/mach-netx/fb.c @@ -22,14 +22,11 @@ #include <linux/dma-mapping.h> #include <linux/amba/bus.h> #include <linux/amba/clcd.h> +#include <linux/err.h> #include <mach/netx-regs.h> #include <mach/hardware.h> -struct clk {}; - -static struct clk fb_clk; - static struct clcd_panel *netx_panel; void netx_clcd_enable(struct clcd_fb *fb) @@ -85,7 +82,7 @@ int clk_enable(struct clk *clk) struct clk *clk_get(struct device *dev, const char *id) { - return &fb_clk; + return dev && strcmp(dev_name(dev), "fb") == 0 ? NULL : ERR_PTR(-ENOENT); } void clk_put(struct clk *clk) diff --git a/arch/arm/mach-netx/include/mach/dma.h b/arch/arm/mach-netx/include/mach/dma.h deleted file mode 100644 index 690b3eb..0000000 --- a/arch/arm/mach-netx/include/mach/dma.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-netx/include/mach/dma.h - * - * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#define MAX_DMA_CHANNELS 0 -#define MAX_DMA_ADDRESS ~0 diff --git a/arch/arm/mach-netx/include/mach/io.h b/arch/arm/mach-netx/include/mach/io.h index 468b92a..c3921cb 100644 --- a/arch/arm/mach-netx/include/mach/io.h +++ b/arch/arm/mach-netx/include/mach/io.h @@ -22,7 +22,7 @@ #define IO_SPACE_LIMIT 0xffffffff -#define __io(a) ((void __iomem *)(a)) +#define __io(a) __typesafe_io(a) #define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-netx/include/mach/memory.h b/arch/arm/mach-netx/include/mach/memory.h index 53745a1..9a363f2 100644 --- a/arch/arm/mach-netx/include/mach/memory.h +++ b/arch/arm/mach-netx/include/mach/memory.h @@ -22,15 +22,5 @@ #define PHYS_OFFSET UL(0x80000000) -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - #endif diff --git a/arch/arm/mach-netx/include/mach/netx-regs.h b/arch/arm/mach-netx/include/mach/netx-regs.h index 5104a00..08c60ff 100644 --- a/arch/arm/mach-netx/include/mach/netx-regs.h +++ b/arch/arm/mach-netx/include/mach/netx-regs.h @@ -328,6 +328,28 @@ #define NETX_PFIFO_FILL_LEVEL(pfifo) NETX_PFIFO_REG(0x180 + ((pfifo)<<2)) #define NETX_PFIFO_XPEC_ISR(xpec) NETX_PFIFO_REG(0x400 + ((xpec) << 2)) + +/******************************* + * Memory Controller * + *******************************/ + +/* Registers */ +#define NETX_MEMCR_REG(ofs) __io(NETX_VA_MEMCR + (ofs)) +#define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */ +#define NETX_MEMCR_SDRAM_CFG_CTRL NETX_MEMCR_REG(0x40) +#define NETX_MEMCR_SDRAM_TIMING_CTRL NETX_MEMCR_REG(0x44) +#define NETX_MEMCR_SDRAM_MODE NETX_MEMCR_REG(0x48) +#define NETX_MEMCR_SDRAM_EXT_MODE NETX_MEMCR_REG(0x4c) +#define NETX_MEMCR_PRIO_TIMESLOT_CTRL NETX_MEMCR_REG(0x80) +#define NETX_MEMCR_PRIO_ACCESS_CTRL NETX_MEMCR_REG(0x84) + +/* Bits */ +#define NETX_MEMCR_SRAM_CTRL_WIDTHEXTMEM(x) (((x) & 0x3) << 24) +#define NETX_MEMCR_SRAM_CTRL_WSPOSTPAUSEEXTMEM(x) (((x) & 0x3) << 16) +#define NETX_MEMCR_SRAM_CTRL_WSPREPASEEXTMEM(x) (((x) & 0x3) << 8) +#define NETX_MEMCR_SRAM_CTRL_WSEXTMEM(x) (((x) & 0x1f) << 0) + + /******************************* * Dual Port Memory * *******************************/ diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c index 7c540c1..d51d627 100644 --- a/arch/arm/mach-netx/time.c +++ b/arch/arm/mach-netx/time.c @@ -21,43 +21,100 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/clocksource.h> +#include <linux/clockchips.h> #include <linux/io.h> #include <mach/hardware.h> #include <asm/mach/time.h> #include <mach/netx-regs.h> +#define TIMER_CLOCKEVENT 0 +#define TIMER_CLOCKSOURCE 1 + +static void netx_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + u32 tmode; + + /* disable timer */ + writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + writel(LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); + tmode = NETX_GPIO_COUNTER_CTRL_RST_EN | + NETX_GPIO_COUNTER_CTRL_IRQ_EN | + NETX_GPIO_COUNTER_CTRL_RUN; + break; + + case CLOCK_EVT_MODE_ONESHOT: + writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); + tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN | + NETX_GPIO_COUNTER_CTRL_RUN; + break; + + default: + WARN(1, "%s: unhandled mode %d\n", __func__, mode); + /* fall through */ + + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + tmode = 0; + break; + } + + writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); +} + +static int netx_set_next_event(unsigned long evt, + struct clock_event_device *clk) +{ + writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT)); + return 0; +} + +static struct clock_event_device netx_clockevent = { + .name = "netx-timer" __stringify(TIMER_CLOCKEVENT), + .shift = 32, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = netx_set_next_event, + .set_mode = netx_set_mode, +}; + /* * IRQ handler for the timer */ static irqreturn_t netx_timer_interrupt(int irq, void *dev_id) { - timer_tick(); + struct clock_event_device *evt = &netx_clockevent; /* acknowledge interrupt */ writel(COUNTER_BIT(0), NETX_GPIO_IRQ); + evt->event_handler(evt); + return IRQ_HANDLED; } static struct irqaction netx_timer_irq = { - .name = "NetX Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = netx_timer_interrupt, + .name = "NetX Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = netx_timer_interrupt, }; cycle_t netx_get_cycles(void) { - return readl(NETX_GPIO_COUNTER_CURRENT(1)); + return readl(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE)); } static struct clocksource clocksource_netx = { - .name = "netx_timer", + .name = "netx_timer", .rating = 200, .read = netx_get_cycles, .mask = CLOCKSOURCE_MASK(32), - .shift = 20, + .shift = 20, .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; @@ -77,24 +134,37 @@ static void __init netx_timer_init(void) /* acknowledge interrupt */ writel(COUNTER_BIT(0), NETX_GPIO_IRQ); - /* Enable the interrupt in the specific timer register and start timer */ + /* Enable the interrupt in the specific timer + * register and start timer + */ writel(COUNTER_BIT(0), NETX_GPIO_IRQ_ENABLE); writel(NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN, - NETX_GPIO_COUNTER_CTRL(0)); + NETX_GPIO_COUNTER_CTRL(0)); setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq); /* Setup timer one for clocksource */ - writel(0, NETX_GPIO_COUNTER_CTRL(1)); - writel(0, NETX_GPIO_COUNTER_CURRENT(1)); - writel(0xFFFFFFFF, NETX_GPIO_COUNTER_MAX(1)); + writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); + writel(0, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE)); + writel(0xffffffff, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKSOURCE)); - writel(NETX_GPIO_COUNTER_CTRL_RUN, - NETX_GPIO_COUNTER_CTRL(1)); + writel(NETX_GPIO_COUNTER_CTRL_RUN, + NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); clocksource_netx.mult = clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_netx.shift); clocksource_register(&clocksource_netx); + + netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, + netx_clockevent.shift); + netx_clockevent.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &netx_clockevent); + /* with max_delta_ns >= delta2ns(0x800) the system currently runs fine. + * Adding some safety ... */ + netx_clockevent.min_delta_ns = + clockevent_delta2ns(0xa00, &netx_clockevent); + netx_clockevent.cpumask = cpumask_of_cpu(0); + clockevents_register_device(&netx_clockevent); } struct sys_timer netx_timer = { diff --git a/arch/arm/mach-netx/xc.c b/arch/arm/mach-netx/xc.c index 32eabf5..8fc6205 100644 --- a/arch/arm/mach-netx/xc.c +++ b/arch/arm/mach-netx/xc.c @@ -92,10 +92,10 @@ static int xc_check_ptr(struct xc *x, unsigned long adr, unsigned int size) return -1; } -static int xc_patch(struct xc *x, void *patch, int count) +static int xc_patch(struct xc *x, const void *patch, int count) { unsigned int val, adr; - unsigned int *data = patch; + const unsigned int *data = patch; int i; for (i = 0; i < count; i++) { @@ -117,7 +117,7 @@ int xc_request_firmware(struct xc *x) struct fw_header *head; unsigned int size; int i; - void *src; + const void *src; unsigned long dst; sprintf(name, "xc%d.bin", x->no); diff --git a/arch/arm/mach-ns9xxx/include/mach/dma.h b/arch/arm/mach-ns9xxx/include/mach/dma.h deleted file mode 100644 index 3f50d8c..0000000 --- a/arch/arm/mach-ns9xxx/include/mach/dma.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/dma.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H - -#endif /* ifndef __ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/hardware.h b/arch/arm/mach-ns9xxx/include/mach/hardware.h index 6dbb203..7663112 100644 --- a/arch/arm/mach-ns9xxx/include/mach/hardware.h +++ b/arch/arm/mach-ns9xxx/include/mach/hardware.h @@ -11,8 +11,6 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H -#include <asm/memory.h> - /* * NetSilicon NS9xxx internal mapping: * diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h index 027bf64..f08451d 100644 --- a/arch/arm/mach-ns9xxx/include/mach/io.h +++ b/arch/arm/mach-ns9xxx/include/mach/io.h @@ -13,7 +13,7 @@ #define IO_SPACE_LIMIT 0xffffffff /* XXX */ -#define __io(a) ((void __iomem *)(a)) +#define __io(a) __typesafe_io(a) #define __mem_pci(a) (a) #define __mem_isa(a) (IO_BASE + (a)) diff --git a/arch/arm/mach-ns9xxx/include/mach/memory.h b/arch/arm/mach-ns9xxx/include/mach/memory.h index 649ee62..6107193 100644 --- a/arch/arm/mach-ns9xxx/include/mach/memory.h +++ b/arch/arm/mach-ns9xxx/include/mach/memory.h @@ -21,7 +21,4 @@ #define PHYS_OFFSET UL(0x00000000) -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - #endif diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 79f0b1f..10a301e 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -4,16 +4,19 @@ comment "OMAP Core Type" config ARCH_OMAP730 depends on ARCH_OMAP1 bool "OMAP730 Based System" + select CPU_ARM926T select ARCH_OMAP_OTG config ARCH_OMAP15XX depends on ARCH_OMAP1 default y bool "OMAP15xx Based System" + select CPU_ARM925T config ARCH_OMAP16XX depends on ARCH_OMAP1 bool "OMAP16xx Based System" + select CPU_ARM926T select ARCH_OMAP_OTG comment "OMAP Board Type" diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index db78946..3030829 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -205,7 +205,7 @@ static struct platform_device *devices[] __initdata = { static int nand_dev_ready(struct omap_nand_platform_data *data) { - return omap_get_gpio_datain(P2_NAND_RB_GPIO_PIN); + return gpio_get_value(P2_NAND_RB_GPIO_PIN); } static struct omap_uart_config fsample_uart_config __initdata = { @@ -223,8 +223,9 @@ static struct omap_board_config_kernel fsample_config[] = { static void __init omap_fsample_init(void) { - if (!(omap_request_gpio(P2_NAND_RB_GPIO_PIN))) - nand_data.dev_ready = nand_dev_ready; + if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0) + BUG(); + nand_data.dev_ready = nand_dev_ready; omap_cfg_reg(L3_1610_FLASH_CS2B_OE); omap_cfg_reg(M8_1610_FLASH_CS2B_WE); diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c index ab9ee58..409fa56 100644 --- a/arch/arm/mach-omap1/board-h2-mmc.c +++ b/arch/arm/mach-omap1/board-h2-mmc.c @@ -12,90 +12,68 @@ * published by the Free Software Foundation. */ +#include <linux/platform_device.h> + +#include <linux/i2c/tps65010.h> + #include <mach/mmc.h> #include <mach/gpio.h> -#ifdef CONFIG_MMC_OMAP -static int slot_cover_open; -static struct device *mmc_device; +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) -static int h2_mmc_set_power(struct device *dev, int slot, int power_on, +static int mmc_set_power(struct device *dev, int slot, int power_on, int vdd) { -#ifdef CONFIG_MMC_DEBUG - dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1, - power_on ? "on" : "off", vdd); -#endif - if (slot != 0) { - dev_err(dev, "No such slot %d\n", slot + 1); - return -ENODEV; - } + if (power_on) + gpio_direction_output(H2_TPS_GPIO_MMC_PWR_EN, 1); + else + gpio_direction_output(H2_TPS_GPIO_MMC_PWR_EN, 0); return 0; } -static int h2_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode) +static int mmc_late_init(struct device *dev) { -#ifdef CONFIG_MMC_DEBUG - dev_dbg(dev, "Set slot %d bus_mode %s\n", slot + 1, - bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull"); -#endif - if (slot != 0) { - dev_err(dev, "No such slot %d\n", slot + 1); - return -ENODEV; - } + int ret; - return 0; -} + ret = gpio_request(H2_TPS_GPIO_MMC_PWR_EN, "MMC power"); + if (ret < 0) + return ret; -static int h2_mmc_get_cover_state(struct device *dev, int slot) -{ - BUG_ON(slot != 0); - - return slot_cover_open; -} - -void h2_mmc_slot_cover_handler(void *arg, int state) -{ - if (mmc_device == NULL) - return; - - slot_cover_open = state; - omap_mmc_notify_cover_event(mmc_device, 0, state); -} - -static int h2_mmc_late_init(struct device *dev) -{ - int ret = 0; - - mmc_device = dev; + gpio_direction_output(H2_TPS_GPIO_MMC_PWR_EN, 0); return ret; } -static void h2_mmc_cleanup(struct device *dev) +static void mmc_shutdown(struct device *dev) { + gpio_free(H2_TPS_GPIO_MMC_PWR_EN); } -static struct omap_mmc_platform_data h2_mmc_data = { +/* + * H2 could use the following functions tested: + * - mmc_get_cover_state that uses OMAP_MPUIO(1) + * - mmc_get_wp that uses OMAP_MPUIO(3) + */ +static struct omap_mmc_platform_data mmc1_data = { .nr_slots = 1, - .switch_slot = NULL, - .init = h2_mmc_late_init, - .cleanup = h2_mmc_cleanup, + .init = mmc_late_init, + .shutdown = mmc_shutdown, + .dma_mask = 0xffffffff, .slots[0] = { - .set_power = h2_mmc_set_power, - .set_bus_mode = h2_mmc_set_bus_mode, - .get_ro = NULL, - .get_cover_state = h2_mmc_get_cover_state, + .set_power = mmc_set_power, .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | MMC_VDD_32_33 | MMC_VDD_33_34, .name = "mmcblk", }, }; +static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC]; + void __init h2_mmc_init(void) { - omap_set_mmc_info(1, &h2_mmc_data); + mmc_data[0] = &mmc1_data; + omap1_init_mmc(mmc_data, OMAP16XX_NR_MMC); } #else @@ -104,7 +82,4 @@ void __init h2_mmc_init(void) { } -void h2_mmc_slot_cover_handler(void *arg, int state) -{ -} #endif diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 3b65914..b240c5f 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -250,11 +250,8 @@ static struct platform_device h2_kp_device = { #if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE) static int h2_transceiver_mode(struct device *dev, int state) { - if (state & IR_SIRMODE) - omap_set_gpio_dataout(H2_IRDA_FIRSEL_GPIO_PIN, 0); - else /* MIR/FIR */ - omap_set_gpio_dataout(H2_IRDA_FIRSEL_GPIO_PIN, 1); - + /* SIR when low, else MIR/FIR when HIGH */ + gpio_set_value(H2_IRDA_FIRSEL_GPIO_PIN, !(state & IR_SIRMODE)); return 0; } #endif @@ -342,16 +339,31 @@ static struct platform_device *h2_devices[] __initdata = { static void __init h2_init_smc91x(void) { - if ((omap_request_gpio(0)) < 0) { + if (gpio_request(0, "SMC91x irq") < 0) { printk("Error requesting gpio 0 for smc91x irq\n"); return; } } +static int tps_setup(struct i2c_client *client, void *context) +{ + tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V | + TPS_LDO1_ENABLE | TPS_VLDO1_3_0V); + + return 0; +} + +static struct tps65010_board tps_board = { + .base = H2_TPS_GPIO_BASE, + .outmask = 0x0f, + .setup = tps_setup, +}; + static struct i2c_board_info __initdata h2_i2c_board_info[] = { { I2C_BOARD_INFO("tps65010", 0x48), .irq = OMAP_GPIO_IRQ(58), + .platform_data = &tps_board, }, { I2C_BOARD_INFO("isp1301_omap", 0x2d), .irq = OMAP_GPIO_IRQ(2), @@ -381,15 +393,6 @@ static struct omap_usb_config h2_usb_config __initdata = { .pins[1] = 3, }; -static struct omap_mmc_config h2_mmc_config __initdata = { - .mmc[0] = { - .enabled = 1, - .wire4 = 1, - }, -}; - -extern struct omap_mmc_platform_data h2_mmc_data; - static struct omap_uart_config h2_uart_config __initdata = { .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), }; @@ -400,7 +403,6 @@ static struct omap_lcd_config h2_lcd_config __initdata = { static struct omap_board_config_kernel h2_config[] __initdata = { { OMAP_TAG_USB, &h2_usb_config }, - { OMAP_TAG_MMC, &h2_mmc_config }, { OMAP_TAG_UART, &h2_uart_config }, { OMAP_TAG_LCD, &h2_lcd_config }, }; @@ -409,7 +411,7 @@ static struct omap_board_config_kernel h2_config[] __initdata = { static int h2_nand_dev_ready(struct omap_nand_platform_data *data) { - return omap_get_gpio_datain(H2_NAND_RB_GPIO_PIN); + return gpio_get_value(H2_NAND_RB_GPIO_PIN); } static void __init h2_init(void) @@ -428,8 +430,9 @@ static void __init h2_init(void) h2_nand_resource.end = h2_nand_resource.start = OMAP_CS2B_PHYS; h2_nand_resource.end += SZ_4K - 1; - if (!(omap_request_gpio(H2_NAND_RB_GPIO_PIN))) - h2_nand_data.dev_ready = h2_nand_dev_ready; + if (gpio_request(H2_NAND_RB_GPIO_PIN, "NAND ready") < 0) + BUG(); + gpio_direction_input(H2_NAND_RB_GPIO_PIN); omap_cfg_reg(L3_1610_FLASH_CS2B_OE); omap_cfg_reg(M8_1610_FLASH_CS2B_WE); @@ -441,10 +444,10 @@ static void __init h2_init(void) /* Irda */ #if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE) omap_writel(omap_readl(FUNC_MUX_CTRL_A) | 7, FUNC_MUX_CTRL_A); - if (!(omap_request_gpio(H2_IRDA_FIRSEL_GPIO_PIN))) { - omap_set_gpio_direction(H2_IRDA_FIRSEL_GPIO_PIN, 0); - h2_irda_data.transceiver_mode = h2_transceiver_mode; - } + if (gpio_request(H2_IRDA_FIRSEL_GPIO_PIN, "IRDA mode") < 0) + BUG(); + gpio_direction_output(H2_IRDA_FIRSEL_GPIO_PIN, 0); + h2_irda_data.transceiver_mode = h2_transceiver_mode; #endif platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices)); diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c index 3608581..fdfe793 100644 --- a/arch/arm/mach-omap1/board-h3-mmc.c +++ b/arch/arm/mach-omap1/board-h3-mmc.c @@ -12,94 +12,55 @@ * published by the Free Software Foundation. */ +#include <linux/platform_device.h> + +#include <linux/i2c/tps65010.h> + #include <mach/mmc.h> #include <mach/gpio.h> -#ifdef CONFIG_MMC_OMAP -static int slot_cover_open; -static struct device *mmc_device; +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) -static int h3_mmc_set_power(struct device *dev, int slot, int power_on, +static int mmc_set_power(struct device *dev, int slot, int power_on, int vdd) { -#ifdef CONFIG_MMC_DEBUG - dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1, - power_on ? "on" : "off", vdd); -#endif - if (slot != 0) { - dev_err(dev, "No such slot %d\n", slot + 1); - return -ENODEV; - } + if (power_on) + gpio_direction_output(H3_TPS_GPIO_MMC_PWR_EN, 1); + else + gpio_direction_output(H3_TPS_GPIO_MMC_PWR_EN, 0); return 0; } -static int h3_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode) -{ - int ret = 0; - -#ifdef CONFIG_MMC_DEBUG - dev_dbg(dev, "Set slot %d bus_mode %s\n", slot + 1, - bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull"); -#endif - if (slot != 0) { - dev_err(dev, "No such slot %d\n", slot + 1); - return -ENODEV; - } - - /* Treated on upper level */ - - return bus_mode; -} - -static int h3_mmc_get_cover_state(struct device *dev, int slot) -{ - BUG_ON(slot != 0); - - return slot_cover_open; -} - -void h3_mmc_slot_cover_handler(void *arg, int state) -{ - if (mmc_device == NULL) - return; - - slot_cover_open = state; - omap_mmc_notify_cover_event(mmc_device, 0, state); -} - -static int h3_mmc_late_init(struct device *dev) -{ - int ret = 0; - - mmc_device = dev; - - return ret; -} - -static void h3_mmc_cleanup(struct device *dev) -{ -} - -static struct omap_mmc_platform_data h3_mmc_data = { +/* + * H3 could use the following functions tested: + * - mmc_get_cover_state that uses OMAP_MPUIO(1) + * - mmc_get_wp that maybe uses OMAP_MPUIO(3) + */ +static struct omap_mmc_platform_data mmc1_data = { .nr_slots = 1, - .switch_slot = NULL, - .init = h3_mmc_late_init, - .cleanup = h3_mmc_cleanup, + .dma_mask = 0xffffffff, .slots[0] = { - .set_power = h3_mmc_set_power, - .set_bus_mode = h3_mmc_set_bus_mode, - .get_ro = NULL, - .get_cover_state = h3_mmc_get_cover_state, + .set_power = mmc_set_power, .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | MMC_VDD_32_33 | MMC_VDD_33_34, .name = "mmcblk", }, }; +static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC]; + void __init h3_mmc_init(void) { - omap_set_mmc_info(1, &h3_mmc_data); + int ret; + + ret = gpio_request(H3_TPS_GPIO_MMC_PWR_EN, "MMC power"); + if (ret < 0) + return; + gpio_direction_output(H3_TPS_GPIO_MMC_PWR_EN, 0); + + mmc_data[0] = &mmc1_data; + omap1_init_mmc(mmc_data, OMAP16XX_NR_MMC); } #else @@ -108,7 +69,4 @@ void __init h3_mmc_init(void) { } -void h3_mmc_slot_cover_handler(void *arg, int state) -{ -} #endif diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index adfcd7b..5157eea 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -447,15 +447,6 @@ static struct omap_usb_config h3_usb_config __initdata = { .pins[1] = 3, }; -static struct omap_mmc_config h3_mmc_config __initdata = { - .mmc[0] = { - .enabled = 1, - .wire4 = 1, - }, -}; - -extern struct omap_mmc_platform_data h3_mmc_data; - static struct omap_uart_config h3_uart_config __initdata = { .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), }; @@ -466,7 +457,6 @@ static struct omap_lcd_config h3_lcd_config __initdata = { static struct omap_board_config_kernel h3_config[] __initdata = { { OMAP_TAG_USB, &h3_usb_config }, - { OMAP_TAG_MMC, &h3_mmc_config }, { OMAP_TAG_UART, &h3_uart_config }, { OMAP_TAG_LCD, &h3_lcd_config }, }; @@ -498,7 +488,7 @@ static struct omap_gpio_switch h3_gpio_switches[] __initdata = { static int nand_dev_ready(struct omap_nand_platform_data *data) { - return omap_get_gpio_datain(H3_NAND_RB_GPIO_PIN); + return gpio_get_value(H3_NAND_RB_GPIO_PIN); } static void __init h3_init(void) @@ -516,8 +506,9 @@ static void __init h3_init(void) nand_resource.end = nand_resource.start = OMAP_CS2B_PHYS; nand_resource.end += SZ_4K - 1; - if (!(omap_request_gpio(H3_NAND_RB_GPIO_PIN))) - nand_data.dev_ready = nand_dev_ready; + if (gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0) + BUG(); + nand_data.dev_ready = nand_dev_ready; /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */ /* GPIO10 pullup/down register, Enable pullup on GPIO10 */ @@ -537,7 +528,7 @@ static void __init h3_init(void) static void __init h3_init_smc91x(void) { omap_cfg_reg(W15_1710_GPIO40); - if (omap_request_gpio(40) < 0) { + if (gpio_request(40, "SMC91x irq") < 0) { printk("Error requesting gpio 40 for smc91x irq\n"); return; } diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index cbc11be..af2fb90 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -39,6 +39,7 @@ #include <mach/common.h> #include <mach/mcbsp.h> #include <mach/omap-alsa.h> +#include <mach/mmc.h> static int innovator_keymap[] = { KEY(0, 0, KEY_F1), @@ -301,7 +302,7 @@ static void __init innovator_init_smc91x(void) OMAP1510_FPGA_RST); udelay(750); } else { - if ((omap_request_gpio(0)) < 0) { + if (gpio_request(0, "SMC91x irq") < 0) { printk("Error requesting gpio 0 for smc91x irq\n"); return; } @@ -360,16 +361,49 @@ static struct omap_lcd_config innovator1610_lcd_config __initdata = { }; #endif -static struct omap_mmc_config innovator_mmc_config __initdata = { - .mmc [0] = { - .enabled = 1, - .wire4 = 1, - .wp_pin = OMAP_MPUIO(3), - .power_pin = -1, /* FPGA F3 UIO42 */ - .switch_pin = -1, /* FPGA F4 UIO43 */ +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) + +static int mmc_set_power(struct device *dev, int slot, int power_on, + int vdd) +{ + if (power_on) + fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3), + OMAP1510_FPGA_POWER); + else + fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3), + OMAP1510_FPGA_POWER); + + return 0; +} + +/* + * Innovator could use the following functions tested: + * - mmc_get_wp that uses OMAP_MPUIO(3) + * - mmc_get_cover_state that uses FPGA F4 UIO43 + */ +static struct omap_mmc_platform_data mmc1_data = { + .nr_slots = 1, + .slots[0] = { + .set_power = mmc_set_power, + .wires = 4, + .name = "mmcblk", }, }; +static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC]; + +void __init innovator_mmc_init(void) +{ + mmc_data[0] = &mmc1_data; + omap1_init_mmc(mmc_data, OMAP15XX_NR_MMC); +} + +#else +static inline void innovator_mmc_init(void) +{ +} +#endif + static struct omap_uart_config innovator_uart_config __initdata = { .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), }; @@ -377,7 +411,6 @@ static struct omap_uart_config innovator_uart_config __initdata = { static struct omap_board_config_kernel innovator_config[] = { { OMAP_TAG_USB, NULL }, { OMAP_TAG_LCD, NULL }, - { OMAP_TAG_MMC, &innovator_mmc_config }, { OMAP_TAG_UART, &innovator_uart_config }, }; @@ -412,6 +445,7 @@ static void __init innovator_init(void) omap_board_config_size = ARRAY_SIZE(innovator_config); omap_serial_init(); omap_register_i2c_bus(1, 100, NULL, 0); + innovator_mmc_init(); } static void __init innovator_map_io(void) diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 38d9783..4970c40 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -35,6 +35,7 @@ #include <mach/aic23.h> #include <mach/omapfb.h> #include <mach/lcd_mipid.h> +#include <mach/mmc.h> #define ADS7846_PENDOWN_GPIO 15 @@ -102,7 +103,7 @@ static void mipid_shutdown(struct mipid_platform_data *pdata) { if (pdata->nreset_gpio != -1) { printk(KERN_INFO "shutdown LCD\n"); - omap_set_gpio_dataout(pdata->nreset_gpio, 0); + gpio_set_value(pdata->nreset_gpio, 0); msleep(120); } } @@ -124,13 +125,13 @@ static void mipid_dev_init(void) static void ads7846_dev_init(void) { - if (omap_request_gpio(ADS7846_PENDOWN_GPIO) < 0) + if (gpio_request(ADS7846_PENDOWN_GPIO, "ADS7846 pendown") < 0) printk(KERN_ERR "can't get ads7846 pen down GPIO\n"); } static int ads7846_get_pendown_state(void) { - return !omap_get_gpio_datain(ADS7846_PENDOWN_GPIO); + return !gpio_get_value(ADS7846_PENDOWN_GPIO); } static struct ads7846_platform_data nokia770_ads7846_platform_data __initdata = { @@ -173,26 +174,68 @@ static struct omap_usb_config nokia770_usb_config __initdata = { .pins[0] = 6, }; -static struct omap_mmc_config nokia770_mmc_config __initdata = { - .mmc[0] = { - .enabled = 0, - .wire4 = 0, - .wp_pin = -1, - .power_pin = -1, - .switch_pin = -1, - }, - .mmc[1] = { - .enabled = 0, - .wire4 = 0, - .wp_pin = -1, - .power_pin = -1, - .switch_pin = -1, +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) + +#define NOKIA770_GPIO_MMC_POWER 41 +#define NOKIA770_GPIO_MMC_SWITCH 23 + +static int nokia770_mmc_set_power(struct device *dev, int slot, int power_on, + int vdd) +{ + if (power_on) + gpio_set_value(NOKIA770_GPIO_MMC_POWER, 1); + else + gpio_set_value(NOKIA770_GPIO_MMC_POWER, 0); + + return 0; +} + +static int nokia770_mmc_get_cover_state(struct device *dev, int slot) +{ + return gpio_get_value(NOKIA770_GPIO_MMC_SWITCH); +} + +static struct omap_mmc_platform_data nokia770_mmc2_data = { + .nr_slots = 1, + .dma_mask = 0xffffffff, + .slots[0] = { + .set_power = nokia770_mmc_set_power, + .get_cover_state = nokia770_mmc_get_cover_state, + .name = "mmcblk", }, }; +static struct omap_mmc_platform_data *nokia770_mmc_data[OMAP16XX_NR_MMC]; + +static void __init nokia770_mmc_init(void) +{ + int ret; + + ret = gpio_request(NOKIA770_GPIO_MMC_POWER, "MMC power"); + if (ret < 0) + return; + gpio_direction_output(NOKIA770_GPIO_MMC_POWER, 0); + + ret = gpio_request(NOKIA770_GPIO_MMC_SWITCH, "MMC cover"); + if (ret < 0) { + gpio_free(NOKIA770_GPIO_MMC_POWER); + return; + } + gpio_direction_input(NOKIA770_GPIO_MMC_SWITCH); + + /* Only the second MMC controller is used */ + nokia770_mmc_data[1] = &nokia770_mmc2_data; + omap1_init_mmc(nokia770_mmc_data, OMAP16XX_NR_MMC); +} + +#else +static inline void nokia770_mmc_init(void) +{ +} +#endif + static struct omap_board_config_kernel nokia770_config[] __initdata = { { OMAP_TAG_USB, NULL }, - { OMAP_TAG_MMC, &nokia770_mmc_config }, }; #if defined(CONFIG_OMAP_DSP) @@ -228,9 +271,9 @@ static void nokia770_audio_pwr_up(void) /* Turn on codec */ aic23_power_up(); - if (omap_get_gpio_datain(HEADPHONE_GPIO)) + if (gpio_get_value(HEADPHONE_GPIO)) /* HP not connected, turn on amplifier */ - omap_set_gpio_dataout(AMPLIFIER_CTRL_GPIO, 1); + gpio_set_value(AMPLIFIER_CTRL_GPIO, 1); else /* HP connected, do not turn on amplifier */ printk("HP connected\n"); @@ -250,7 +293,7 @@ static DECLARE_DELAYED_WORK(codec_power_down_work, codec_delayed_power_down); static void nokia770_audio_pwr_down(void) { /* Turn off amplifier */ - omap_set_gpio_dataout(AMPLIFIER_CTRL_GPIO, 0); + gpio_set_value(AMPLIFIER_CTRL_GPIO, 0); /* Turn off codec: schedule delayed work */ schedule_delayed_work(&codec_power_down_work, HZ / 20); /* 50ms */ @@ -335,6 +378,7 @@ static void __init omap_nokia770_init(void) omap_dsp_init(); ads7846_dev_init(); mipid_dev_init(); + nokia770_mmc_init(); } static void __init omap_nokia770_map_io(void) diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 3e766e4..ff9e67b 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -188,7 +188,8 @@ static struct gpio_led tps_leds[] = { /* NOTE: D9 and D2 have hardware blink support. * Also, D9 requires non-battery power. */ - { .gpio = OSK_TPS_GPIO_LED_D9, .name = "d9", }, + { .gpio = OSK_TPS_GPIO_LED_D9, .name = "d9", + .default_trigger = "ide-disk", }, { .gpio = OSK_TPS_GPIO_LED_D2, .name = "d2", }, { .gpio = OSK_TPS_GPIO_LED_D3, .name = "d3", .active_low = 1, .default_trigger = "heartbeat", }, @@ -260,7 +261,6 @@ static struct i2c_board_info __initdata osk_i2c_board_info[] = { }, /* TODO when driver support is ready: * - aic23 audio chip at 0x1a - * - on Mistral, 24c04 eeprom at 0x50 * - optionally on Mistral, ov9640 camera sensor at 0x30 */ }; @@ -288,7 +288,7 @@ static void __init osk_init_cf(void) return; } /* the CF I/O IRQ is really active-low */ - set_irq_type(OMAP_GPIO_IRQ(62), IRQ_TYPE_EDGE_FALLING); + set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); } static void __init osk_init_irq(void) @@ -337,11 +337,28 @@ static struct omap_board_config_kernel osk_config[] __initdata = { #ifdef CONFIG_OMAP_OSK_MISTRAL #include <linux/input.h> +#include <linux/i2c/at24.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> #include <mach/keypad.h> +static struct at24_platform_data at24c04 = { + .byte_len = SZ_4K / 8, + .page_size = 16, +}; + +static struct i2c_board_info __initdata mistral_i2c_board_info[] = { + { + /* NOTE: powered from LCD supply */ + I2C_BOARD_INFO("24c04", 0x50), + .platform_data = &at24c04, + }, + /* TODO when driver support is ready: + * - optionally ov9640 camera sensor at 0x30 + */ +}; + static const int osk_keymap[] = { /* KEY(col, row, code) */ KEY(0, 0, KEY_F1), /* SW4 */ @@ -483,23 +500,30 @@ static void __init osk_mistral_init(void) omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ gpio_request(4, "ts_int"); gpio_direction_input(4); - set_irq_type(OMAP_GPIO_IRQ(4), IRQ_TYPE_EDGE_FALLING); + set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); spi_register_board_info(mistral_boardinfo, ARRAY_SIZE(mistral_boardinfo)); - /* the sideways button (SW1) is for use as a "wakeup" button */ + /* the sideways button (SW1) is for use as a "wakeup" button + * + * NOTE: The Mistral board has the wakeup button (SW1) wired + * to the LCD 3.3V rail, which is powered down during suspend. + * To allow this button to wake up the omap, work around this + * HW bug by rewiring SW1 to use the main 3.3V rail. + */ omap_cfg_reg(N15_1610_MPUIO2); if (gpio_request(OMAP_MPUIO(2), "wakeup") == 0) { int ret = 0; + int irq = gpio_to_irq(OMAP_MPUIO(2)); gpio_direction_input(OMAP_MPUIO(2)); - set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQ_TYPE_EDGE_RISING); + set_irq_type(irq, IRQ_TYPE_EDGE_RISING); #ifdef CONFIG_PM /* share the IRQ in case someone wants to use the * button for more than wakeup from system sleep. */ - ret = request_irq(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), + ret = request_irq(irq, &osk_mistral_wake_interrupt, IRQF_SHARED, "mistral_wakeup", &osk_mistral_wake_interrupt); @@ -508,7 +532,7 @@ static void __init osk_mistral_init(void) printk(KERN_ERR "OSK+Mistral: no wakeup irq, %d?\n", ret); } else - enable_irq_wake(OMAP_GPIO_IRQ(OMAP_MPUIO(2))); + enable_irq_wake(irq); #endif } else printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n"); @@ -520,6 +544,9 @@ static void __init osk_mistral_init(void) if (gpio_request(2, "lcd_pwr") == 0) gpio_direction_output(2, 1); + i2c_register_board_info(1, mistral_i2c_board_info, + ARRAY_SIZE(mistral_i2c_board_info)); + platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices)); } #else diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index b580436..75e32d3 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -255,7 +255,7 @@ static void palmte_get_power_status(struct apm_power_info *info, int *battery) { int charging, batt, hi, lo, mid; - charging = !omap_get_gpio_datain(PALMTE_DC_GPIO); + charging = !gpio_get_value(PALMTE_DC_GPIO); batt = battery[0]; if (charging) batt -= 60; @@ -316,7 +316,6 @@ static void palmte_get_power_status(struct apm_power_info *info, int *battery) static struct omap_board_config_kernel palmte_config[] __initdata = { { OMAP_TAG_USB, &palmte_usb_config }, - { OMAP_TAG_MMC, &palmte_mmc_config }, { OMAP_TAG_LCD, &palmte_lcd_config }, { OMAP_TAG_UART, &palmte_uart_config }, }; @@ -335,11 +334,11 @@ static void palmte_headphones_detect(void *data, int state) { if (state) { /* Headphones connected, disable speaker */ - omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 0); + gpio_set_value(PALMTE_SPEAKER_GPIO, 0); printk(KERN_INFO "PM: speaker off\n"); } else { /* Headphones unplugged, re-enable speaker */ - omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 1); + gpio_set_value(PALMTE_SPEAKER_GPIO, 1); printk(KERN_INFO "PM: speaker on\n"); } } @@ -347,18 +346,18 @@ static void palmte_headphones_detect(void *data, int state) static void __init palmte_misc_gpio_setup(void) { /* Set TSC2102 PINTDAV pin as input (used by TSC2102 driver) */ - if (omap_request_gpio(PALMTE_PINTDAV_GPIO)) { + if (gpio_request(PALMTE_PINTDAV_GPIO, "TSC2102 PINTDAV") < 0) { printk(KERN_ERR "Could not reserve PINTDAV GPIO!\n"); return; } - omap_set_gpio_direction(PALMTE_PINTDAV_GPIO, 1); + gpio_direction_input(PALMTE_PINTDAV_GPIO); /* Set USB-or-DC-IN pin as input (unused) */ - if (omap_request_gpio(PALMTE_USB_OR_DC_GPIO)) { + if (gpio_request(PALMTE_USB_OR_DC_GPIO, "USB/DC-IN") < 0) { printk(KERN_ERR "Could not reserve cable signal GPIO!\n"); return; } - omap_set_gpio_direction(PALMTE_USB_OR_DC_GPIO, 1); + gpio_direction_input(PALMTE_USB_OR_DC_GPIO); } static void __init omap_palmte_init(void) diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 40f9860..5c001af 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -268,7 +268,7 @@ static struct platform_device *palmtt_devices[] __initdata = { static int palmtt_get_pendown_state(void) { - return !omap_get_gpio_datain(6); + return !gpio_get_value(6); } static const struct ads7846_platform_data palmtt_ts_info = { diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index e719294..cc05257 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -239,7 +239,7 @@ static struct platform_device *devices[] __initdata = { static int palmz71_get_pendown_state(void) { - return !omap_get_gpio_datain(PALMZ71_PENIRQ_GPIO); + return !gpio_get_value(PALMZ71_PENIRQ_GPIO); } static const struct ads7846_platform_data palmz71_ts_info = { @@ -267,16 +267,6 @@ static struct omap_usb_config palmz71_usb_config __initdata = { .pins[0] = 2, }; -static struct omap_mmc_config palmz71_mmc_config __initdata = { - .mmc[0] = { - .enabled = 1, - .wire4 = 0, - .wp_pin = PALMZ71_MMC_WP_GPIO, - .power_pin = -1, - .switch_pin = PALMZ71_MMC_IN_GPIO, - }, -}; - static struct omap_lcd_config palmz71_lcd_config __initdata = { .ctrl_name = "internal", }; @@ -287,7 +277,6 @@ static struct omap_uart_config palmz71_uart_config __initdata = { static struct omap_board_config_kernel palmz71_config[] __initdata = { {OMAP_TAG_USB, &palmz71_usb_config}, - {OMAP_TAG_MMC, &palmz71_mmc_config}, {OMAP_TAG_LCD, &palmz71_lcd_config}, {OMAP_TAG_UART, &palmz71_uart_config}, }; @@ -295,13 +284,13 @@ static struct omap_board_config_kernel palmz71_config[] __initdata = { static irqreturn_t palmz71_powercable(int irq, void *dev_id) { - if (omap_get_gpio_datain(PALMZ71_USBDETECT_GPIO)) { + if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) { printk(KERN_INFO "PM: Power cable connected\n"); - set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), + set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), IRQ_TYPE_EDGE_FALLING); } else { printk(KERN_INFO "PM: Power cable disconnected\n"); - set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), + set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), IRQ_TYPE_EDGE_RISING); } return IRQ_HANDLED; @@ -323,29 +312,28 @@ palmz71_gpio_setup(int early) { if (early) { /* Only set GPIO1 so we have a working serial */ - omap_set_gpio_dataout(1, 1); - omap_set_gpio_direction(1, 0); + gpio_direction_output(1, 1); } else { /* Set MMC/SD host WP pin as input */ - if (omap_request_gpio(PALMZ71_MMC_WP_GPIO)) { + if (gpio_request(PALMZ71_MMC_WP_GPIO, "MMC WP") < 0) { printk(KERN_ERR "Could not reserve WP GPIO!\n"); return; } - omap_set_gpio_direction(PALMZ71_MMC_WP_GPIO, 1); + gpio_direction_input(PALMZ71_MMC_WP_GPIO); /* Monitor the Power-cable-connected signal */ - if (omap_request_gpio(PALMZ71_USBDETECT_GPIO)) { + if (gpio_request(PALMZ71_USBDETECT_GPIO, "USB detect") < 0) { printk(KERN_ERR "Could not reserve cable signal GPIO!\n"); return; } - omap_set_gpio_direction(PALMZ71_USBDETECT_GPIO, 1); - if (request_irq(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), + gpio_direction_input(PALMZ71_USBDETECT_GPIO); + if (request_irq(gpio_to_irq(PALMZ71_USBDETECT_GPIO), palmz71_powercable, IRQF_SAMPLE_RANDOM, "palmz71-cable", 0)) printk(KERN_ERR "IRQ request for power cable failed!\n"); - palmz71_powercable(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), 0); + palmz71_powercable(gpio_to_irq(PALMZ71_USBDETECT_GPIO), 0); } } diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index b715917..3b9f907 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -205,7 +205,7 @@ static struct platform_device *devices[] __initdata = { static int nand_dev_ready(struct omap_nand_platform_data *data) { - return omap_get_gpio_datain(P2_NAND_RB_GPIO_PIN); + return gpio_get_value(P2_NAND_RB_GPIO_PIN); } static struct omap_uart_config perseus2_uart_config __initdata = { @@ -223,8 +223,9 @@ static struct omap_board_config_kernel perseus2_config[] __initdata = { static void __init omap_perseus2_init(void) { - if (!(omap_request_gpio(P2_NAND_RB_GPIO_PIN))) - nand_data.dev_ready = nand_dev_ready; + if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0) + BUG(); + nand_data.dev_ready = nand_dev_ready; omap_cfg_reg(L3_1610_FLASH_CS2B_OE); omap_cfg_reg(M8_1610_FLASH_CS2B_WE); diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c index 0be4eba..66a4d7d 100644 --- a/arch/arm/mach-omap1/board-sx1-mmc.c +++ b/arch/arm/mach-omap1/board-sx1-mmc.c @@ -12,30 +12,20 @@ * published by the Free Software Foundation. */ +#include <linux/platform_device.h> + #include <mach/hardware.h> #include <mach/mmc.h> #include <mach/gpio.h> -#ifdef CONFIG_MMC_OMAP -static int slot_cover_open; -static struct device *mmc_device; +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) -static int sx1_mmc_set_power(struct device *dev, int slot, int power_on, +static int mmc_set_power(struct device *dev, int slot, int power_on, int vdd) { int err; u8 dat = 0; -#ifdef CONFIG_MMC_DEBUG - dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1, - power_on ? "on" : "off", vdd); -#endif - - if (slot != 0) { - dev_err(dev, "No such slot %d\n", slot + 1); - return -ENODEV; - } - err = sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); if (err < 0) return err; @@ -48,68 +38,23 @@ static int sx1_mmc_set_power(struct device *dev, int slot, int power_on, return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); } -static int sx1_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode) -{ -#ifdef CONFIG_MMC_DEBUG - dev_dbg(dev, "Set slot %d bus_mode %s\n", slot + 1, - bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull"); -#endif - if (slot != 0) { - dev_err(dev, "No such slot %d\n", slot + 1); - return -ENODEV; - } - - return 0; -} - -static int sx1_mmc_get_cover_state(struct device *dev, int slot) -{ - BUG_ON(slot != 0); - - return slot_cover_open; -} - -void sx1_mmc_slot_cover_handler(void *arg, int state) -{ - if (mmc_device == NULL) - return; - - slot_cover_open = state; - omap_mmc_notify_cover_event(mmc_device, 0, state); -} - -static int sx1_mmc_late_init(struct device *dev) -{ - int ret = 0; - - mmc_device = dev; - - return ret; -} - -static void sx1_mmc_cleanup(struct device *dev) -{ -} - -static struct omap_mmc_platform_data sx1_mmc_data = { +/* Cover switch is at OMAP_MPUIO(3) */ +static struct omap_mmc_platform_data mmc1_data = { .nr_slots = 1, - .switch_slot = NULL, - .init = sx1_mmc_late_init, - .cleanup = sx1_mmc_cleanup, .slots[0] = { - .set_power = sx1_mmc_set_power, - .set_bus_mode = sx1_mmc_set_bus_mode, - .get_ro = NULL, - .get_cover_state = sx1_mmc_get_cover_state, + .set_power = mmc_set_power, .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | MMC_VDD_32_33 | MMC_VDD_33_34, .name = "mmcblk", }, }; +static struct omap_mmc_platform_data *mmc_data[OMAP15XX_NR_MMC]; + void __init sx1_mmc_init(void) { - omap_set_mmc_info(1, &sx1_mmc_data); + mmc_data[0] = &mmc1_data; + omap1_init_mmc(mmc_data, OMAP15XX_NR_MMC); } #else @@ -118,7 +63,4 @@ void __init sx1_mmc_init(void) { } -void sx1_mmc_slot_cover_handler(void *arg, int state) -{ -} #endif diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 130bcc6..8171fe0 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -378,15 +378,6 @@ static struct omap_usb_config sx1_usb_config __initdata = { .pins[2] = 0, }; -/*----------- MMC -------------------------*/ - -static struct omap_mmc_config sx1_mmc_config __initdata = { - .mmc [0] = { - .enabled = 1, - .wire4 = 0, - }, -}; - /*----------- LCD -------------------------*/ static struct platform_device sx1_lcd_device = { @@ -414,7 +405,6 @@ static struct omap_uart_config sx1_uart_config __initdata = { static struct omap_board_config_kernel sx1_config[] __initdata = { { OMAP_TAG_USB, &sx1_usb_config }, - { OMAP_TAG_MMC, &sx1_mmc_config }, { OMAP_TAG_LCD, &sx1_lcd_config }, { OMAP_TAG_UART, &sx1_uart_config }, }; @@ -436,14 +426,9 @@ static void __init omap_sx1_init(void) omap_request_gpio(1); /* A_IRDA_OFF */ omap_request_gpio(11); /* A_SWITCH */ omap_request_gpio(15); /* A_USB_ON */ - omap_set_gpio_direction(1, 0);/* gpio1 -> output */ - omap_set_gpio_direction(11, 0);/* gpio11 -> output */ - omap_set_gpio_direction(15, 0);/* gpio15 -> output */ - /* set GPIO data */ - omap_set_gpio_dataout(1, 1);/*A_IRDA_OFF = 1 */ - omap_set_gpio_dataout(11, 0);/*A_SWITCH = 0 */ - omap_set_gpio_dataout(15, 0);/*A_USB_ON = 0 */ - + gpio_direction_output(1, 1); /*A_IRDA_OFF = 1 */ + gpio_direction_output(11, 0); /*A_SWITCH = 0 */ + gpio_direction_output(15, 0); /*A_USB_ON = 0 */ } /*----------------------------------------*/ static void __init omap_sx1_init_irq(void) diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 45a0131..c224f3c 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -15,6 +15,7 @@ #include <linux/delay.h> #include <linux/platform_device.h> #include <linux/interrupt.h> +#include <linux/irq.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/notifier.h> @@ -140,21 +141,12 @@ static struct omap_usb_config voiceblue_usb_config __initdata = { .pins[2] = 6, }; -static struct omap_mmc_config voiceblue_mmc_config __initdata = { - .mmc[0] = { - .enabled = 1, - .power_pin = 2, - .switch_pin = -1, - }, -}; - static struct omap_uart_config voiceblue_uart_config __initdata = { .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), }; static struct omap_board_config_kernel voiceblue_config[] = { { OMAP_TAG_USB, &voiceblue_usb_config }, - { OMAP_TAG_MMC, &voiceblue_mmc_config }, { OMAP_TAG_UART, &voiceblue_uart_config }, }; @@ -168,29 +160,27 @@ static void __init voiceblue_init_irq(void) static void __init voiceblue_init(void) { /* Watchdog */ - omap_request_gpio(0); + gpio_request(0, "Watchdog"); /* smc91x reset */ - omap_request_gpio(7); - omap_set_gpio_direction(7, 0); - omap_set_gpio_dataout(7, 1); + gpio_request(7, "SMC91x reset"); + gpio_direction_output(7, 1); udelay(2); /* wait at least 100ns */ - omap_set_gpio_dataout(7, 0); + gpio_set_value(7, 0); mdelay(50); /* 50ms until PHY ready */ /* smc91x interrupt pin */ - omap_request_gpio(8); + gpio_request(8, "SMC91x irq"); /* 16C554 reset*/ - omap_request_gpio(6); - omap_set_gpio_direction(6, 0); - omap_set_gpio_dataout(6, 0); + gpio_request(6, "16C554 reset"); + gpio_direction_output(6, 0); /* 16C554 interrupt pins */ - omap_request_gpio(12); - omap_request_gpio(13); - omap_request_gpio(14); - omap_request_gpio(15); - set_irq_type(OMAP_GPIO_IRQ(12), IRQ_TYPE_EDGE_RISING); - set_irq_type(OMAP_GPIO_IRQ(13), IRQ_TYPE_EDGE_RISING); - set_irq_type(OMAP_GPIO_IRQ(14), IRQ_TYPE_EDGE_RISING); - set_irq_type(OMAP_GPIO_IRQ(15), IRQ_TYPE_EDGE_RISING); + gpio_request(12, "16C554 irq"); + gpio_request(13, "16C554 irq"); + gpio_request(14, "16C554 irq"); + gpio_request(15, "16C554 irq"); + set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); + set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); + set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); + set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); omap_board_config = voiceblue_config; @@ -244,19 +234,18 @@ static int wdt_gpio_state; void voiceblue_wdt_enable(void) { - omap_set_gpio_direction(0, 0); - omap_set_gpio_dataout(0, 0); - omap_set_gpio_dataout(0, 1); - omap_set_gpio_dataout(0, 0); + gpio_direction_output(0, 0); + gpio_set_value(0, 1); + gpio_set_value(0, 0); wdt_gpio_state = 0; } void voiceblue_wdt_disable(void) { - omap_set_gpio_dataout(0, 0); - omap_set_gpio_dataout(0, 1); - omap_set_gpio_dataout(0, 0); - omap_set_gpio_direction(0, 1); + gpio_set_value(0, 0); + gpio_set_value(0, 1); + gpio_set_value(0, 0); + gpio_direction_input(0); } void voiceblue_wdt_ping(void) @@ -265,7 +254,7 @@ void voiceblue_wdt_ping(void) return; wdt_gpio_state = !wdt_gpio_state; - omap_set_gpio_dataout(0, wdt_gpio_state); + gpio_set_value(0, wdt_gpio_state); } void voiceblue_reset(void) diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 5635b51..c1dcdf1 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -705,7 +705,6 @@ static struct clk bclk_16xx = { static struct clk mmc1_ck = { .name = "mmc_ck", - .id = 1, /* Functional clock is direct from ULPD, interface clock is ARMPER */ .parent = &armper_ck.clk, .rate = 48000000, @@ -720,7 +719,7 @@ static struct clk mmc1_ck = { static struct clk mmc2_ck = { .name = "mmc_ck", - .id = 2, + .id = 1, /* Functional clock is direct from ULPD, interface clock is ARMPER */ .parent = &armper_ck.clk, .rate = 48000000, diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index e382b43..77382d8 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -22,6 +22,7 @@ #include <mach/board.h> #include <mach/mux.h> #include <mach/gpio.h> +#include <mach/mmc.h> /*-------------------------------------------------------------------------*/ @@ -99,6 +100,95 @@ static inline void omap_init_mbox(void) static inline void omap_init_mbox(void) { } #endif +/*-------------------------------------------------------------------------*/ + +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) + +static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller, + int controller_nr) +{ + if (controller_nr == 0) { + omap_cfg_reg(MMC_CMD); + omap_cfg_reg(MMC_CLK); + omap_cfg_reg(MMC_DAT0); + if (cpu_is_omap1710()) { + omap_cfg_reg(M15_1710_MMC_CLKI); + omap_cfg_reg(P19_1710_MMC_CMDDIR); + omap_cfg_reg(P20_1710_MMC_DATDIR0); + } + if (mmc_controller->slots[0].wires == 4) { + omap_cfg_reg(MMC_DAT1); + /* NOTE: DAT2 can be on W10 (here) or M15 */ + if (!mmc_controller->slots[0].nomux) + omap_cfg_reg(MMC_DAT2); + omap_cfg_reg(MMC_DAT3); + } + } + + /* Block 2 is on newer chips, and has many pinout options */ + if (cpu_is_omap16xx() && controller_nr == 1) { + if (!mmc_controller->slots[1].nomux) { + omap_cfg_reg(Y8_1610_MMC2_CMD); + omap_cfg_reg(Y10_1610_MMC2_CLK); + omap_cfg_reg(R18_1610_MMC2_CLKIN); + omap_cfg_reg(W8_1610_MMC2_DAT0); + if (mmc_controller->slots[1].wires == 4) { + omap_cfg_reg(V8_1610_MMC2_DAT1); + omap_cfg_reg(W15_1610_MMC2_DAT2); + omap_cfg_reg(R10_1610_MMC2_DAT3); + } + + /* These are needed for the level shifter */ + omap_cfg_reg(V9_1610_MMC2_CMDDIR); + omap_cfg_reg(V5_1610_MMC2_DATDIR0); + omap_cfg_reg(W19_1610_MMC2_DATDIR1); + } + + /* Feedback clock must be set on OMAP-1710 MMC2 */ + if (cpu_is_omap1710()) + omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24), + MOD_CONF_CTRL_1); + } +} + +void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, + int nr_controllers) +{ + int i; + + for (i = 0; i < nr_controllers; i++) { + unsigned long base, size; + unsigned int irq = 0; + + if (!mmc_data[i]) + continue; + + omap1_mmc_mux(mmc_data[i], i); + + switch (i) { + case 0: + base = OMAP1_MMC1_BASE; + irq = INT_MMC; + break; + case 1: + if (!cpu_is_omap16xx()) + return; + base = OMAP1_MMC2_BASE; + irq = INT_1610_MMC2; + break; + default: + continue; + } + size = OMAP1_MMC_SIZE; + + omap_mmc_add(i, base, size, irq, mmc_data[i]); + }; +} + +#endif + +/*-------------------------------------------------------------------------*/ + #if defined(CONFIG_OMAP_STI) #define OMAP1_STI_BASE 0xfffea000 diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 0499538..4f2b8a7 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c @@ -177,9 +177,9 @@ void omap1510_fpga_init_irq(void) * NOTE: For general GPIO/MPUIO access and interrupts, please see * gpio.[ch] */ - omap_request_gpio(13); - omap_set_gpio_direction(13, 1); - set_irq_type(OMAP_GPIO_IRQ(13), IRQ_TYPE_EDGE_RISING); + gpio_request(13, "FPGA irq"); + gpio_direction_input(13); + set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); } diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c index 13083d7..89bb875 100644 --- a/arch/arm/mach-omap1/id.c +++ b/arch/arm/mach-omap1/id.c @@ -15,6 +15,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> +#include <mach/cpu.h> #define OMAP_DIE_ID_0 0xfffe1800 #define OMAP_DIE_ID_1 0xfffe1804 @@ -30,6 +31,8 @@ struct omap_id { u32 type; /* Cpu id bits [31:08], cpu class bits [07:00] */ }; +static unsigned int omap_revision; + /* Register values to detect the OMAP version */ static struct omap_id omap_ids[] __initdata = { { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000}, @@ -53,6 +56,12 @@ static struct omap_id omap_ids[] __initdata = { { .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 0x17100000}, }; +unsigned int omap_rev(void) +{ + return omap_revision; +} +EXPORT_SYMBOL(omap_rev); + /* * Get OMAP type from PROD_ID. * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM. @@ -121,17 +130,18 @@ void __init omap_check_revision(void) omap_id = omap_readl(OMAP32_ID_0); #ifdef DEBUG - printk("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0)); - printk("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n", + printk(KERN_DEBUG "OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0)); + printk(KERN_DEBUG "OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n", omap_readl(OMAP_DIE_ID_1), (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf); - printk("OMAP_PRODUCTION_ID_0: 0x%08x\n", omap_readl(OMAP_PRODUCTION_ID_0)); - printk("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n", + printk(KERN_DEBUG "OMAP_PRODUCTION_ID_0: 0x%08x\n", + omap_readl(OMAP_PRODUCTION_ID_0)); + printk(KERN_DEBUG "OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n", omap_readl(OMAP_PRODUCTION_ID_1), omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff); - printk("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0)); - printk("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1)); - printk("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev); + printk(KERN_DEBUG "OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0)); + printk(KERN_DEBUG "OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1)); + printk(KERN_DEBUG "JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev); #endif system_serial_high = omap_readl(OMAP_DIE_ID_0); @@ -140,7 +150,7 @@ void __init omap_check_revision(void) /* First check only the major version in a safe way */ for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { if (jtag_id == (omap_ids[i].jtag_id)) { - system_rev = omap_ids[i].type; + omap_revision = omap_ids[i].type; break; } } @@ -148,7 +158,7 @@ void __init omap_check_revision(void) /* Check if we can find the die revision */ for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev) { - system_rev = omap_ids[i].type; + omap_revision = omap_ids[i].type; break; } } @@ -158,38 +168,35 @@ void __init omap_check_revision(void) if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev && omap_id == omap_ids[i].omap_id) { - system_rev = omap_ids[i].type; + omap_revision = omap_ids[i].type; break; } } /* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */ - cpu_type = system_rev >> 24; + cpu_type = omap_revision >> 24; switch (cpu_type) { case 0x07: - system_rev |= 0x07; + omap_revision |= 0x07; break; case 0x03: case 0x15: - system_rev |= 0x15; + omap_revision |= 0x15; break; case 0x16: case 0x17: - system_rev |= 0x16; - break; - case 0x24: - system_rev |= 0x24; + omap_revision |= 0x16; break; default: - printk("Unknown OMAP cpu type: 0x%02x\n", cpu_type); + printk(KERN_INFO "Unknown OMAP cpu type: 0x%02x\n", cpu_type); } - printk("OMAP%04x", system_rev >> 16); - if ((system_rev >> 8) & 0xff) - printk("%x", (system_rev >> 8) & 0xff); - printk(" revision %i handled as %02xxx id: %08x%08x\n", - die_rev, system_rev & 0xff, system_serial_low, + printk(KERN_INFO "OMAP%04x", omap_revision >> 16); + if ((omap_revision >> 8) & 0xff) + printk(KERN_INFO "%x", (omap_revision >> 8) & 0xff); + printk(KERN_INFO " revision %i handled as %02xxx id: %08x%08x\n", + die_rev, omap_revision & 0xff, system_serial_low, system_serial_high); } diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c index 71fe2cc..17c9d0e 100644 --- a/arch/arm/mach-omap1/leds-h2p2-debug.c +++ b/arch/arm/mach-omap1/leds-h2p2-debug.c @@ -65,8 +65,8 @@ void h2p2_dbg_leds_event(led_event_t evt) /* all leds off during suspend or shutdown */ if (! machine_is_omap_perseus2()) { - omap_set_gpio_dataout(GPIO_TIMER, 0); - omap_set_gpio_dataout(GPIO_IDLE, 0); + gpio_set_value(GPIO_TIMER, 0); + gpio_set_value(GPIO_IDLE, 0); } __raw_writew(~0, &fpga->leds); @@ -94,7 +94,7 @@ void h2p2_dbg_leds_event(led_event_t evt) if (machine_is_omap_perseus2()) hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER; else { - omap_set_gpio_dataout(GPIO_TIMER, led_state & LED_TIMER_ON); + gpio_set_value(GPIO_TIMER, led_state & LED_TIMER_ON); goto done; } @@ -106,7 +106,7 @@ void h2p2_dbg_leds_event(led_event_t evt) if (machine_is_omap_perseus2()) hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE; else { - omap_set_gpio_dataout(GPIO_IDLE, 1); + gpio_set_value(GPIO_IDLE, 1); goto done; } @@ -116,7 +116,7 @@ void h2p2_dbg_leds_event(led_event_t evt) if (machine_is_omap_perseus2()) hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE; else { - omap_set_gpio_dataout(GPIO_IDLE, 0); + gpio_set_value(GPIO_IDLE, 0); goto done; } diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c index 98e7896..499d7ad 100644 --- a/arch/arm/mach-omap1/leds-osk.c +++ b/arch/arm/mach-omap1/leds-osk.c @@ -44,8 +44,8 @@ static void mistral_setled(void) green = 1; /* else both sides are disabled */ - omap_set_gpio_dataout(GPIO_LED_GREEN, green); - omap_set_gpio_dataout(GPIO_LED_RED, red); + gpio_set_value(GPIO_LED_GREEN, green); + gpio_set_value(GPIO_LED_RED, red); } #endif diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c index 6cdad93..8cbf256 100644 --- a/arch/arm/mach-omap1/leds.c +++ b/arch/arm/mach-omap1/leds.c @@ -47,14 +47,14 @@ omap_leds_init(void) * that's a different kind of LED (just one color at a time). */ omap_cfg_reg(P18_1610_GPIO3); - if (omap_request_gpio(3) == 0) - omap_set_gpio_direction(3, 0); + if (gpio_request(3, "LED red") == 0) + gpio_direction_output(3, 1); else printk(KERN_WARNING "LED: can't get GPIO3/red?\n"); omap_cfg_reg(MPUIO4); - if (omap_request_gpio(OMAP_MPUIO(4)) == 0) - omap_set_gpio_direction(OMAP_MPUIO(4), 0); + if (gpio_request(OMAP_MPUIO(4), "LED green") == 0) + gpio_direction_output(OMAP_MPUIO(4), 1); else printk(KERN_WARNING "LED: can't get MPUIO4/green?\n"); } diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index 770d256..9774c1f 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -226,7 +226,8 @@ void omap_pm_suspend(void) { unsigned long arg0 = 0, arg1 = 0; - printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev); + printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n", + omap_rev()); omap_serial_wake_trigger(1); @@ -421,7 +422,8 @@ void omap_pm_suspend(void) omap_serial_wake_trigger(0); - printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev); + printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n", + omap_rev()); } #if defined(DEBUG) && defined(CONFIG_PROC_FS) diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 528691d5c..0002084 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -244,22 +244,22 @@ static void __init omap_serial_set_port_wakeup(int gpio_nr) { int ret; - ret = omap_request_gpio(gpio_nr); + ret = gpio_request(gpio_nr, "UART wake"); if (ret < 0) { printk(KERN_ERR "Could not request UART wake GPIO: %i\n", gpio_nr); return; } - omap_set_gpio_direction(gpio_nr, 1); - ret = request_irq(OMAP_GPIO_IRQ(gpio_nr), &omap_serial_wake_interrupt, + gpio_direction_input(gpio_nr); + ret = request_irq(gpio_to_irq(gpio_nr), &omap_serial_wake_interrupt, IRQF_TRIGGER_RISING, "serial wakeup", NULL); if (ret) { - omap_free_gpio(gpio_nr); + gpio_free(gpio_nr); printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n", gpio_nr); return; } - enable_irq_wake(OMAP_GPIO_IRQ(gpio_nr)); + enable_irq_wake(gpio_to_irq(gpio_nr)); } static int __init omap_serial_wakeup_init(void) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 4832fcc..3754b79 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -55,3 +55,7 @@ config MACH_OMAP_LDP config MACH_OVERO bool "Gumstix Overo board" depends on ARCH_OMAP3 && ARCH_OMAP34XX + +config MACH_OMAP3_PANDORA + bool "OMAP3 Pandora" + depends on ARCH_OMAP3 && ARCH_OMAP34XX
\ No newline at end of file diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index c693923..bbd12bc 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -27,9 +27,15 @@ obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o -obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o +obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o \ + mmc-twl4030.o obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o -obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o -obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o -obj-$(CONFIG_MACH_OVERO) += board-overo.o +obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \ + mmc-twl4030.o +obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ + mmc-twl4030.o +obj-$(CONFIG_MACH_OVERO) += board-overo.o \ + mmc-twl4030.o +obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ + mmc-twl4030.o diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 24688ef..83fa372 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -19,6 +19,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/delay.h> +#include <linux/i2c/twl4030.h> #include <linux/err.h> #include <linux/clk.h> #include <linux/io.h> @@ -35,6 +36,7 @@ #include <mach/common.h> #include <mach/gpmc.h> +#include "mmc-twl4030.h" #define SDP2430_FLASH_CS 0 #define SDP2430_SMC91X_CS 5 @@ -168,13 +170,13 @@ static inline void __init sdp2430_init_smc91x(void) sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f; udelay(100); - if (omap_request_gpio(OMAP24XX_ETHR_GPIO_IRQ) < 0) { + if (gpio_request(OMAP24XX_ETHR_GPIO_IRQ, "SMC91x irq") < 0) { printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", OMAP24XX_ETHR_GPIO_IRQ); gpmc_cs_free(eth_cs); goto out; } - omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1); + gpio_direction_input(OMAP24XX_ETHR_GPIO_IRQ); out: clk_disable(gpmc_fck); @@ -197,12 +199,58 @@ static struct omap_board_config_kernel sdp2430_config[] = { {OMAP_TAG_UART, &sdp2430_uart_config}, }; + +static struct twl4030_gpio_platform_data sdp2430_gpio_data = { + .gpio_base = OMAP_MAX_GPIO_LINES, + .irq_base = TWL4030_GPIO_IRQ_BASE, + .irq_end = TWL4030_GPIO_IRQ_END, +}; + +static struct twl4030_platform_data sdp2430_twldata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, + + /* platform_data for children goes here */ + .gpio = &sdp2430_gpio_data, +}; + +static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl4030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = INT_24XX_SYS_NIRQ, + .platform_data = &sdp2430_twldata, + }, +}; + +static int __init omap2430_i2c_init(void) +{ + omap_register_i2c_bus(1, 400, NULL, 0); + omap_register_i2c_bus(2, 2600, sdp2430_i2c_boardinfo, + ARRAY_SIZE(sdp2430_i2c_boardinfo)); + return 0; +} + +static struct twl4030_hsmmc_info mmc[] __initdata = { + { + .mmc = 1, + .wires = 4, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + .ext_clock = 1, + }, + {} /* Terminator */ +}; + static void __init omap_2430sdp_init(void) { + omap2430_i2c_init(); + platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); omap_board_config = sdp2430_config; omap_board_config_size = ARRAY_SIZE(sdp2430_config); omap_serial_init(); + twl4030_mmc_init(mmc); } static void __init omap_2430sdp_map_io(void) diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 989ad15..bf1e5d3 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -236,13 +236,13 @@ static inline void __init apollon_init_smc91x(void) udelay(100); omap_cfg_reg(W4__24XX_GPIO74); - if (omap_request_gpio(APOLLON_ETHR_GPIO_IRQ) < 0) { + if (gpio_request(APOLLON_ETHR_GPIO_IRQ, "SMC91x irq") < 0) { printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", APOLLON_ETHR_GPIO_IRQ); gpmc_cs_free(APOLLON_ETH_CS); goto out; } - omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1); + gpio_direction_input(APOLLON_ETHR_GPIO_IRQ); out: clk_disable(gpmc_fck); @@ -261,16 +261,6 @@ static struct omap_uart_config apollon_uart_config __initdata = { .enabled_uarts = (1 << 0) | (0 << 1) | (0 << 2), }; -static struct omap_mmc_config apollon_mmc_config __initdata = { - .mmc [0] = { - .enabled = 1, - .wire4 = 1, - .wp_pin = -1, - .power_pin = -1, - .switch_pin = -1, - }, -}; - static struct omap_usb_config apollon_usb_config __initdata = { .register_dev = 1, .hmc_mode = 0x14, /* 0:dev 1:host1 2:disable */ @@ -284,7 +274,6 @@ static struct omap_lcd_config apollon_lcd_config __initdata = { static struct omap_board_config_kernel apollon_config[] = { { OMAP_TAG_UART, &apollon_uart_config }, - { OMAP_TAG_MMC, &apollon_mmc_config }, { OMAP_TAG_USB, &apollon_usb_config }, { OMAP_TAG_LCD, &apollon_lcd_config }, }; @@ -327,15 +316,15 @@ static void __init apollon_sw_init(void) /* Enter SW - Y11 */ omap_cfg_reg(Y11_242X_GPIO16); omap_request_gpio(SW_ENTER_GPIO16); - omap_set_gpio_direction(SW_ENTER_GPIO16, 1); + gpio_direction_input(SW_ENTER_GPIO16); /* Up SW - AA12 */ omap_cfg_reg(AA12_242X_GPIO17); omap_request_gpio(SW_UP_GPIO17); - omap_set_gpio_direction(SW_UP_GPIO17, 1); + gpio_direction_input(SW_UP_GPIO17); /* Down SW - AA8 */ omap_cfg_reg(AA8_242X_GPIO58); omap_request_gpio(SW_DOWN_GPIO58); - omap_set_gpio_direction(SW_DOWN_GPIO58, 1); + gpio_direction_input(SW_DOWN_GPIO58); set_irq_type(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), IRQ_TYPE_EDGE_RISING); if (request_irq(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), &apollon_sw_interrupt, @@ -359,9 +348,8 @@ static void __init apollon_usb_init(void) /* USB device */ /* DEVICE_SUSPEND */ omap_cfg_reg(P21_242X_GPIO12); - omap_request_gpio(12); - omap_set_gpio_direction(12, 0); /* OUT */ - omap_set_gpio_dataout(12, 0); + gpio_request(12, "USB suspend"); + gpio_direction_output(12, 0); } static void __init omap_apollon_init(void) diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 9ba0978..3b34c20 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -41,19 +41,8 @@ static struct omap_uart_config generic_uart_config __initdata = { .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), }; -static struct omap_mmc_config generic_mmc_config __initdata = { - .mmc [0] = { - .enabled = 0, - .wire4 = 0, - .wp_pin = -1, - .power_pin = -1, - .switch_pin = -1, - }, -}; - static struct omap_board_config_kernel generic_config[] = { { OMAP_TAG_UART, &generic_uart_config }, - { OMAP_TAG_MMC, &generic_mmc_config }, }; static void __init omap_generic_init(void) diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 2fef2c8..5e9b146 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -19,6 +19,7 @@ #include <linux/delay.h> #include <linux/workqueue.h> #include <linux/i2c.h> +#include <linux/i2c/at24.h> #include <linux/input.h> #include <linux/err.h> #include <linux/clk.h> @@ -372,31 +373,33 @@ static struct omap_uart_config h4_uart_config __initdata = { .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), }; -static struct omap_mmc_config h4_mmc_config __initdata = { - .mmc [0] = { - .enabled = 1, - .wire4 = 1, - .wp_pin = -1, - .power_pin = -1, - .switch_pin = -1, - }, -}; - static struct omap_lcd_config h4_lcd_config __initdata = { .ctrl_name = "internal", }; static struct omap_board_config_kernel h4_config[] = { { OMAP_TAG_UART, &h4_uart_config }, - { OMAP_TAG_MMC, &h4_mmc_config }, { OMAP_TAG_LCD, &h4_lcd_config }, }; +static struct at24_platform_data m24c01 = { + .byte_len = SZ_1K / 8, + .page_size = 16, +}; + static struct i2c_board_info __initdata h4_i2c_board_info[] = { { I2C_BOARD_INFO("isp1301_omap", 0x2d), .irq = OMAP_GPIO_IRQ(125), }, + { /* EEPROM on mainboard */ + I2C_BOARD_INFO("24c01", 0x52), + .platform_data = &m24c01, + }, + { /* EEPROM on cpu card */ + I2C_BOARD_INFO("24c01", 0x57), + .platform_data = &m24c01, + }, }; static void __init omap_h4_init(void) diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 1ea59986..aa69727 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -21,6 +21,7 @@ #include <linux/clk.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> +#include <linux/i2c/twl4030.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -38,11 +39,69 @@ #include <asm/delay.h> #include <mach/control.h> +#include "mmc-twl4030.h" + +#define SDP3430_SMC91X_CS 3 + +static struct resource ldp_smc911x_resources[] = { + [0] = { + .start = OMAP34XX_ETHR_START, + .end = OMAP34XX_ETHR_START + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, + }, +}; + +static struct platform_device ldp_smc911x_device = { + .name = "smc911x", + .id = -1, + .num_resources = ARRAY_SIZE(ldp_smc911x_resources), + .resource = ldp_smc911x_resources, +}; + +static struct platform_device *ldp_devices[] __initdata = { + &ldp_smc911x_device, +}; + +static inline void __init ldp_init_smc911x(void) +{ + int eth_cs; + unsigned long cs_mem_base; + int eth_gpio = 0; + + eth_cs = LDP_SMC911X_CS; + + if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { + printk(KERN_ERR "Failed to request GPMC mem for smc911x\n"); + return; + } + + ldp_smc911x_resources[0].start = cs_mem_base + 0x0; + ldp_smc911x_resources[0].end = cs_mem_base + 0xf; + udelay(100); + + eth_gpio = LDP_SMC911X_GPIO; + + ldp_smc911x_resources[1].start = OMAP_GPIO_IRQ(eth_gpio); + + if (omap_request_gpio(eth_gpio) < 0) { + printk(KERN_ERR "Failed to request GPIO%d for smc911x IRQ\n", + eth_gpio); + return; + } + gpio_direction_input(eth_gpio); +} + static void __init omap_ldp_init_irq(void) { omap2_init_common_hw(); omap_init_irq(); omap_gpio_init(); + ldp_init_smc911x(); } static struct omap_uart_config ldp_uart_config __initdata = { @@ -53,20 +112,56 @@ static struct omap_board_config_kernel ldp_config[] __initdata = { { OMAP_TAG_UART, &ldp_uart_config }, }; +static struct twl4030_gpio_platform_data ldp_gpio_data = { + .gpio_base = OMAP_MAX_GPIO_LINES, + .irq_base = TWL4030_GPIO_IRQ_BASE, + .irq_end = TWL4030_GPIO_IRQ_END, +}; + +static struct twl4030_platform_data ldp_twldata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, + + /* platform_data for children goes here */ + .gpio = &ldp_gpio_data, +}; + +static struct i2c_board_info __initdata ldp_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl4030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = INT_34XX_SYS_NIRQ, + .platform_data = &ldp_twldata, + }, +}; + static int __init omap_i2c_init(void) { - omap_register_i2c_bus(1, 2600, NULL, 0); + omap_register_i2c_bus(1, 2600, ldp_i2c_boardinfo, + ARRAY_SIZE(ldp_i2c_boardinfo)); omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, NULL, 0); return 0; } +static struct twl4030_hsmmc_info mmc[] __initdata = { + { + .mmc = 1, + .wires = 4, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, + {} /* Terminator */ +}; + static void __init omap_ldp_init(void) { omap_i2c_init(); + platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); omap_board_config = ldp_config; omap_board_config_size = ARRAY_SIZE(ldp_config); omap_serial_init(); + twl4030_mmc_init(mmc); } static void __init omap_ldp_map_io(void) diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index baa7967..9e5ada0 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -38,7 +38,9 @@ #include <mach/common.h> #include <mach/gpmc.h> #include <mach/nand.h> +#include <mach/mux.h> +#include "mmc-twl4030.h" #define GPMC_CS0_BASE 0x60 #define GPMC_CS_SIZE 0x30 @@ -103,6 +105,78 @@ static struct omap_uart_config omap3_beagle_uart_config __initdata = { .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), }; +static struct twl4030_hsmmc_info mmc[] = { + { + .mmc = 1, + .wires = 8, + .gpio_wp = 29, + }, + {} /* Terminator */ +}; + +static struct gpio_led gpio_leds[]; + +static int beagle_twl_gpio_setup(struct device *dev, + unsigned gpio, unsigned ngpio) +{ + /* gpio + 0 is "mmc0_cd" (input/IRQ) */ + + /* REVISIT: need ehci-omap hooks for external VBUS + * power switch and overcurrent detect + */ + + gpio_request(gpio + 1, "EHCI_nOC"); + gpio_direction_input(gpio + 1); + + /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */ + gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); + gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1); + + /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ + gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; + + return 0; +} + +static struct twl4030_gpio_platform_data beagle_gpio_data = { + .gpio_base = OMAP_MAX_GPIO_LINES, + .irq_base = TWL4030_GPIO_IRQ_BASE, + .irq_end = TWL4030_GPIO_IRQ_END, + .use_leds = true, + .pullups = BIT(1), + .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13) + | BIT(15) | BIT(16) | BIT(17), + .setup = beagle_twl_gpio_setup, +}; + +static struct twl4030_platform_data beagle_twldata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, + + /* platform_data for children goes here */ + .gpio = &beagle_gpio_data, +}; + +static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl4030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = INT_34XX_SYS_NIRQ, + .platform_data = &beagle_twldata, + }, +}; + +static int __init omap3_beagle_i2c_init(void) +{ + omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo, + ARRAY_SIZE(beagle_i2c_boardinfo)); +#ifdef CONFIG_I2C2_OMAP_BEAGLE + omap_register_i2c_bus(2, 400, NULL, 0); +#endif + omap_register_i2c_bus(3, 400, NULL, 0); + return 0; +} + static void __init omap3_beagle_init_irq(void) { omap2_init_common_hw(); @@ -130,6 +204,11 @@ static struct gpio_led gpio_leds[] = { .default_trigger = "mmc0", .gpio = 149, }, + { + .name = "beagleboard::pmu_stat", + .gpio = -EINVAL, /* gets replaced */ + .active_low = true, + }, }; static struct gpio_led_platform_data gpio_led_info = { @@ -218,11 +297,22 @@ static void __init omap3beagle_flash_init(void) static void __init omap3_beagle_init(void) { + omap3_beagle_i2c_init(); platform_add_devices(omap3_beagle_devices, ARRAY_SIZE(omap3_beagle_devices)); omap_board_config = omap3_beagle_config; omap_board_config_size = ARRAY_SIZE(omap3_beagle_config); omap_serial_init(); + + omap_cfg_reg(AH8_34XX_GPIO29); + mmc[0].gpio_cd = gpio + 0; + twl4030_mmc_init(mmc); + + omap_cfg_reg(J25_34XX_GPIO170); + gpio_request(170, "DVI_nPD"); + /* REVISIT leave DVI powered down until it's needed ... */ + gpio_direction_output(170, true); + omap3beagle_flash_init(); } diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c new file mode 100644 index 0000000..b319610 --- /dev/null +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -0,0 +1,212 @@ +/* + * board-omap3pandora.c (Pandora Handheld Console) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <linux/spi/spi.h> +#include <linux/spi/ads7846.h> +#include <linux/i2c/twl4030.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <mach/board.h> +#include <mach/common.h> +#include <mach/gpio.h> +#include <mach/hardware.h> +#include <mach/mcspi.h> + +#include "mmc-twl4030.h" + +#define OMAP3_PANDORA_TS_GPIO 94 + +static struct twl4030_hsmmc_info omap3pandora_mmc[] = { + { + .mmc = 1, + .wires = 4, + .gpio_cd = -EINVAL, + .gpio_wp = 126, + .ext_clock = 0, + }, + { + .mmc = 2, + .wires = 4, + .gpio_cd = -EINVAL, + .gpio_wp = 127, + .ext_clock = 1, + }, + {} /* Terminator */ +}; + +static struct omap_uart_config omap3pandora_uart_config __initdata = { + .enabled_uarts = (1 << 2), /* UART3 */ +}; + +static int omap3pandora_twl_gpio_setup(struct device *dev, + unsigned gpio, unsigned ngpio) +{ + /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */ + omap3pandora_mmc[0].gpio_cd = gpio + 0; + omap3pandora_mmc[1].gpio_cd = gpio + 1; + twl4030_mmc_init(omap3pandora_mmc); + + return 0; +} + +static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { + .gpio_base = OMAP_MAX_GPIO_LINES, + .irq_base = TWL4030_GPIO_IRQ_BASE, + .irq_end = TWL4030_GPIO_IRQ_END, + .setup = omap3pandora_twl_gpio_setup, +}; + +static struct twl4030_usb_data omap3pandora_usb_data = { + .usb_mode = T2_USB_MODE_ULPI, +}; + +static struct twl4030_platform_data omap3pandora_twldata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, + .gpio = &omap3pandora_gpio_data, + .usb = &omap3pandora_usb_data, +}; + +static struct i2c_board_info __initdata omap3pandora_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("tps65950", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = INT_34XX_SYS_NIRQ, + .platform_data = &omap3pandora_twldata, + }, +}; + +static int __init omap3pandora_i2c_init(void) +{ + omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo, + ARRAY_SIZE(omap3pandora_i2c_boardinfo)); + /* i2c2 pins are not connected */ + omap_register_i2c_bus(3, 400, NULL, 0); + return 0; +} + +static void __init omap3pandora_init_irq(void) +{ + omap2_init_common_hw(); + omap_init_irq(); + omap_gpio_init(); +} + +static void __init omap3pandora_ads7846_init(void) +{ + int gpio = OMAP3_PANDORA_TS_GPIO; + int ret; + + ret = gpio_request(gpio, "ads7846_pen_down"); + if (ret < 0) { + printk(KERN_ERR "Failed to request GPIO %d for " + "ads7846 pen down IRQ\n", gpio); + return; + } + + gpio_direction_input(gpio); +} + +static int ads7846_get_pendown_state(void) +{ + return !gpio_get_value(OMAP3_PANDORA_TS_GPIO); +} + +static struct ads7846_platform_data ads7846_config = { + .x_max = 0x0fff, + .y_max = 0x0fff, + .x_plate_ohms = 180, + .pressure_max = 255, + .debounce_max = 10, + .debounce_tol = 3, + .debounce_rep = 1, + .get_pendown_state = ads7846_get_pendown_state, + .keep_vref_on = 1, +}; + +static struct omap2_mcspi_device_config ads7846_mcspi_config = { + .turbo_mode = 0, + .single_channel = 1, /* 0: slave, 1: master */ +}; + +static struct spi_board_info omap3pandora_spi_board_info[] __initdata = { + { + .modalias = "ads7846", + .bus_num = 1, + .chip_select = 0, + .max_speed_hz = 1500000, + .controller_data = &ads7846_mcspi_config, + .irq = OMAP_GPIO_IRQ(OMAP3_PANDORA_TS_GPIO), + .platform_data = &ads7846_config, + } +}; + +static struct platform_device omap3pandora_lcd_device = { + .name = "pandora_lcd", + .id = -1, +}; + +static struct omap_lcd_config omap3pandora_lcd_config __initdata = { + .ctrl_name = "internal", +}; + +static struct omap_board_config_kernel omap3pandora_config[] __initdata = { + { OMAP_TAG_UART, &omap3pandora_uart_config }, + { OMAP_TAG_LCD, &omap3pandora_lcd_config }, +}; + +static struct platform_device *omap3pandora_devices[] __initdata = { + &omap3pandora_lcd_device, +}; + +static void __init omap3pandora_init(void) +{ + omap3pandora_i2c_init(); + platform_add_devices(omap3pandora_devices, + ARRAY_SIZE(omap3pandora_devices)); + omap_board_config = omap3pandora_config; + omap_board_config_size = ARRAY_SIZE(omap3pandora_config); + omap_serial_init(); + spi_register_board_info(omap3pandora_spi_board_info, + ARRAY_SIZE(omap3pandora_spi_board_info)); + omap3pandora_ads7846_init(); +} + +static void __init omap3pandora_map_io(void) +{ + omap2_set_globals_343x(); + omap2_map_common_io(); +} + +MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") + .phys_io = 0x48000000, + .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = omap3pandora_map_io, + .init_irq = omap3pandora_init_irq, + .init_machine = omap3pandora_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index e09aa59..82b3dc5 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -26,6 +26,7 @@ #include <linux/io.h> #include <linux/kernel.h> #include <linux/platform_device.h> +#include <linux/i2c/twl4030.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> @@ -44,6 +45,8 @@ #include <mach/hardware.h> #include <mach/nand.h> +#include "mmc-twl4030.h" + #define NAND_BLOCK_SIZE SZ_128K #define GPMC_CS0_BASE 0x60 #define GPMC_CS_SIZE 0x30 @@ -139,8 +142,31 @@ static struct omap_uart_config overo_uart_config __initdata = { .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), }; +static struct twl4030_gpio_platform_data overo_gpio_data = { + .gpio_base = OMAP_MAX_GPIO_LINES, + .irq_base = TWL4030_GPIO_IRQ_BASE, + .irq_end = TWL4030_GPIO_IRQ_END, +}; + +static struct twl4030_platform_data overo_twldata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, + .gpio = &overo_gpio_data, +}; + +static struct i2c_board_info __initdata overo_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl4030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = INT_34XX_SYS_NIRQ, + .platform_data = &overo_twldata, + }, +}; + static int __init overo_i2c_init(void) { + omap_register_i2c_bus(1, 2600, overo_i2c_boardinfo, + ARRAY_SIZE(overo_i2c_boardinfo)); /* i2c2 pins are used for gpio */ omap_register_i2c_bus(3, 400, NULL, 0); return 0; @@ -171,6 +197,22 @@ static struct platform_device *overo_devices[] __initdata = { &overo_lcd_device, }; +static struct twl4030_hsmmc_info mmc[] __initdata = { + { + .mmc = 1, + .wires = 4, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, + { + .mmc = 2, + .wires = 4, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, + {} /* Terminator */ +}; + static void __init overo_init(void) { overo_i2c_init(); @@ -178,6 +220,7 @@ static void __init overo_init(void) omap_board_config = overo_config; omap_board_config_size = ARRAY_SIZE(overo_config); omap_serial_init(); + twl4030_mmc_init(mmc); overo_flash_init(); if ((gpio_request(OVERO_GPIO_W2W_NRESET, diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 242a19d..ff6cd14 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -2522,7 +2522,6 @@ static struct clk usbhs_ick = { static struct clk mmchs1_ick = { .name = "mmchs_ick", - .id = 1, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2533,7 +2532,6 @@ static struct clk mmchs1_ick = { static struct clk mmchs1_fck = { .name = "mmchs_fck", - .id = 1, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l3_clkdm", @@ -2544,7 +2542,7 @@ static struct clk mmchs1_fck = { static struct clk mmchs2_ick = { .name = "mmchs_ick", - .id = 2, + .id = 1, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2555,7 +2553,7 @@ static struct clk mmchs2_ick = { static struct clk mmchs2_fck = { .name = "mmchs_fck", - .id = 2, + .id = 1, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), @@ -2595,7 +2593,6 @@ static struct clk mdm_intc_ick = { static struct clk mmchsdb1_fck = { .name = "mmchsdb_fck", - .id = 1, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2606,7 +2603,7 @@ static struct clk mmchsdb1_fck = { static struct clk mmchsdb2_fck = { .name = "mmchsdb_fck", - .id = 2, + .id = 1, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 084e110..31bb701 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -475,7 +475,7 @@ int __init omap2_clk_init(void) * Update this if there are further clock changes between ES2 * and production parts */ - if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) { + if (omap_rev() == OMAP3430_REV_ES1_0) { /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ cpu_clkflg |= CLOCK_IN_OMAP3430ES1; } else { diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index c38a8a0..a826094 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -1374,7 +1374,7 @@ static struct clk core_96m_fck = { static struct clk mmchs3_fck = { .name = "mmchs_fck", - .id = 3, + .id = 2, .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, @@ -1385,7 +1385,7 @@ static struct clk mmchs3_fck = { static struct clk mmchs2_fck = { .name = "mmchs_fck", - .id = 2, + .id = 1, .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MMC2_SHIFT, @@ -1406,7 +1406,6 @@ static struct clk mspro_fck = { static struct clk mmchs1_fck = { .name = "mmchs_fck", - .id = 1, .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, @@ -1722,7 +1721,7 @@ static struct clk usbtll_ick = { static struct clk mmchs3_ick = { .name = "mmchs_ick", - .id = 3, + .id = 2, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, @@ -1774,7 +1773,7 @@ static struct clk des2_ick = { static struct clk mmchs2_ick = { .name = "mmchs_ick", - .id = 2, + .id = 1, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC2_SHIFT, @@ -1785,7 +1784,6 @@ static struct clk mmchs2_ick = { static struct clk mmchs1_ick = { .name = "mmchs_ick", - .id = 1, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, @@ -2280,8 +2278,8 @@ static struct clk wkup_32k_fck = { .recalc = &followparent_recalc, }; -static struct clk gpio1_fck = { - .name = "gpio1_fck", +static struct clk gpio1_dbck = { + .name = "gpio1_dbck", .parent = &wkup_32k_fck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, @@ -2527,8 +2525,8 @@ static struct clk per_32k_alwon_fck = { .recalc = &followparent_recalc, }; -static struct clk gpio6_fck = { - .name = "gpio6_fck", +static struct clk gpio6_dbck = { + .name = "gpio6_dbck", .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, @@ -2537,8 +2535,8 @@ static struct clk gpio6_fck = { .recalc = &followparent_recalc, }; -static struct clk gpio5_fck = { - .name = "gpio5_fck", +static struct clk gpio5_dbck = { + .name = "gpio5_dbck", .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, @@ -2547,8 +2545,8 @@ static struct clk gpio5_fck = { .recalc = &followparent_recalc, }; -static struct clk gpio4_fck = { - .name = "gpio4_fck", +static struct clk gpio4_dbck = { + .name = "gpio4_dbck", .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, @@ -2557,8 +2555,8 @@ static struct clk gpio4_fck = { .recalc = &followparent_recalc, }; -static struct clk gpio3_fck = { - .name = "gpio3_fck", +static struct clk gpio3_dbck = { + .name = "gpio3_dbck", .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, @@ -2567,8 +2565,8 @@ static struct clk gpio3_fck = { .recalc = &followparent_recalc, }; -static struct clk gpio2_fck = { - .name = "gpio2_fck", +static struct clk gpio2_dbck = { + .name = "gpio2_dbck", .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, @@ -3170,7 +3168,7 @@ static struct clk *onchip_34xx_clks[] __initdata = { &usim_fck, &gpt1_fck, &wkup_32k_fck, - &gpio1_fck, + &gpio1_dbck, &wdt2_fck, &wkup_l4_ick, &usim_ick, @@ -3192,11 +3190,11 @@ static struct clk *onchip_34xx_clks[] __initdata = { &gpt8_fck, &gpt9_fck, &per_32k_alwon_fck, - &gpio6_fck, - &gpio5_fck, - &gpio4_fck, - &gpio3_fck, - &gpio2_fck, + &gpio6_dbck, + &gpio5_dbck, + &gpio4_dbck, + &gpio3_dbck, + &gpio2_dbck, &wdt3_fck, &per_l4_ick, &gpio6_ick, diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 90af2ac..9d7216f 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -14,16 +14,19 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/clk.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/map.h> +#include <mach/control.h> #include <mach/tc.h> #include <mach/board.h> #include <mach/mux.h> #include <mach/gpio.h> #include <mach/eac.h> +#include <mach/mmc.h> #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) #define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE) @@ -295,6 +298,171 @@ static void omap_init_sha1_md5(void) static inline void omap_init_sha1_md5(void) { } #endif +/*-------------------------------------------------------------------------*/ + +#ifdef CONFIG_ARCH_OMAP3 + +#define MMCHS_SYSCONFIG 0x0010 +#define MMCHS_SYSCONFIG_SWRESET (1 << 1) +#define MMCHS_SYSSTATUS 0x0014 +#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) + +static struct platform_device dummy_pdev = { + .dev = { + .bus = &platform_bus_type, + }, +}; + +/** + * omap_hsmmc_reset() - Full reset of each HS-MMC controller + * + * Ensure that each MMC controller is fully reset. Controllers + * left in an unknown state (by bootloader) may prevent retention + * or OFF-mode. This is especially important in cases where the + * MMC driver is not enabled, _or_ built as a module. + * + * In order for reset to work, interface, functional and debounce + * clocks must be enabled. The debounce clock comes from func_32k_clk + * and is not under SW control, so we only enable i- and f-clocks. + **/ +static void __init omap_hsmmc_reset(void) +{ + u32 i, nr_controllers = cpu_is_omap34xx() ? OMAP34XX_NR_MMC : + OMAP24XX_NR_MMC; + + for (i = 0; i < nr_controllers; i++) { + u32 v, base = 0; + struct clk *iclk, *fclk; + struct device *dev = &dummy_pdev.dev; + + switch (i) { + case 0: + base = OMAP2_MMC1_BASE; + break; + case 1: + base = OMAP2_MMC2_BASE; + break; + case 2: + base = OMAP3_MMC3_BASE; + break; + } + + dummy_pdev.id = i; + iclk = clk_get(dev, "mmchs_ick"); + if (iclk && clk_enable(iclk)) + iclk = NULL; + + fclk = clk_get(dev, "mmchs_fck"); + if (fclk && clk_enable(fclk)) + fclk = NULL; + + if (!iclk || !fclk) { + printk(KERN_WARNING + "%s: Unable to enable clocks for MMC%d, " + "cannot reset.\n", __func__, i); + break; + } + + omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); + v = omap_readl(base + MMCHS_SYSSTATUS); + while (!(omap_readl(base + MMCHS_SYSSTATUS) & + MMCHS_SYSSTATUS_RESETDONE)) + cpu_relax(); + + if (fclk) { + clk_disable(fclk); + clk_put(fclk); + } + if (iclk) { + clk_disable(iclk); + clk_put(iclk); + } + } +} +#else +static inline void omap_hsmmc_reset(void) {} +#endif + +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ + defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) + +static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, + int controller_nr) +{ + if (cpu_is_omap2420() && controller_nr == 0) { + omap_cfg_reg(H18_24XX_MMC_CMD); + omap_cfg_reg(H15_24XX_MMC_CLKI); + omap_cfg_reg(G19_24XX_MMC_CLKO); + omap_cfg_reg(F20_24XX_MMC_DAT0); + omap_cfg_reg(F19_24XX_MMC_DAT_DIR0); + omap_cfg_reg(G18_24XX_MMC_CMD_DIR); + if (mmc_controller->slots[0].wires == 4) { + omap_cfg_reg(H14_24XX_MMC_DAT1); + omap_cfg_reg(E19_24XX_MMC_DAT2); + omap_cfg_reg(D19_24XX_MMC_DAT3); + omap_cfg_reg(E20_24XX_MMC_DAT_DIR1); + omap_cfg_reg(F18_24XX_MMC_DAT_DIR2); + omap_cfg_reg(E18_24XX_MMC_DAT_DIR3); + } + + /* + * Use internal loop-back in MMC/SDIO Module Input Clock + * selection + */ + if (mmc_controller->slots[0].internal_clock) { + u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + v |= (1 << 24); + omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); + } + } +} + +void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, + int nr_controllers) +{ + int i; + + for (i = 0; i < nr_controllers; i++) { + unsigned long base, size; + unsigned int irq = 0; + + if (!mmc_data[i]) + continue; + + omap2_mmc_mux(mmc_data[i], i); + + switch (i) { + case 0: + base = OMAP2_MMC1_BASE; + irq = INT_24XX_MMC_IRQ; + break; + case 1: + base = OMAP2_MMC2_BASE; + irq = INT_24XX_MMC2_IRQ; + break; + case 2: + if (!cpu_is_omap34xx()) + return; + base = OMAP3_MMC3_BASE; + irq = INT_34XX_MMC3_IRQ; + break; + default: + continue; + } + + if (cpu_is_omap2420()) + size = OMAP2420_MMC_SIZE; + else + size = HSMMC_SIZE; + + omap_mmc_add(i, base, size, irq, mmc_data[i]); + }; +} + +#endif + +/*-------------------------------------------------------------------------*/ + #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) #define OMAP_HDQ_BASE 0x480B2000 @@ -334,6 +502,7 @@ static int __init omap2_init_devices(void) /* please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ + omap_hsmmc_reset(); omap_init_mbox(); omap_init_mcspi(); omap_hdq_init(); diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index bf45ff3..b0f8e7d 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -22,40 +22,15 @@ #include <mach/control.h> #include <mach/cpu.h> -static u32 class; -static void __iomem *tap_base; -static u16 tap_prod_id; - -#define OMAP_TAP_IDCODE 0x0204 -#define OMAP_TAP_DIE_ID_0 0x0218 -#define OMAP_TAP_DIE_ID_1 0x021C -#define OMAP_TAP_DIE_ID_2 0x0220 -#define OMAP_TAP_DIE_ID_3 0x0224 - -/* system_rev fields for OMAP2 processors: - * CPU id bits [31:16], - * CPU device type [15:12], (unprg,normal,POP) - * CPU revision [11:08] - * CPU class bits [07:00] - */ - -struct omap_id { - u16 hawkeye; /* Silicon type (Hawkeye id) */ - u8 dev; /* Device type from production_id reg */ - u32 type; /* combined type id copied to system_rev */ -}; +static struct omap_chip_id omap_chip; +static unsigned int omap_revision; -/* Register values to detect the OMAP version */ -static struct omap_id omap_ids[] __initdata = { - { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 }, - { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 }, - { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 }, - { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 }, - { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 }, - { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 }, -}; -static struct omap_chip_id omap_chip; +unsigned int omap_rev(void) +{ + return omap_revision; +} +EXPORT_SYMBOL(omap_rev); /** * omap_chip_is - test whether currently running OMAP matches a chip type @@ -70,135 +45,41 @@ int omap_chip_is(struct omap_chip_id oci) } EXPORT_SYMBOL(omap_chip_is); -static u32 __init read_tap_reg(int reg) -{ - unsigned int regval = 0; - u32 cpuid; - - /* Reading the IDCODE register on 3430 ES1 results in a - * data abort as the register is not exposed on the OCP - * Hence reading the Cortex Rev - */ - cpuid = read_cpuid(CPUID_ID); - - /* If the processor type is Cortex-A8 and the revision is 0x0 - * it means its Cortex r0p0 which is 3430 ES1 - */ - if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) { - - if (reg == tap_prod_id) { - regval = 0x000F00F0; - goto out; - } - - switch (reg) { - case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break; - /* Making DevType as 0xF in ES1 to differ from ES2 */ - case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break; - case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break; - case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break; - case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break; - } - } else - regval = __raw_readl(tap_base + reg); - -out: - return regval; - -} +/*----------------------------------------------------------------------------*/ -/* - * _set_system_rev - set the system_rev global based on current OMAP chip type - * - * Set the system_rev global. This is primarily used by the cpu_is_omapxxxx() - * macros. - */ -static void __init _set_system_rev(u32 type, u8 rev) -{ - u32 i, ctrl_status; - - /* - * system_rev encoding is as follows - * system_rev & 0xff000000 -> Omap Class (24xx/34xx) - * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x) - * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430) - * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 ) - * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD ) - * system_rev & 0x000000c0 -> IDCODE revision[6:7] - * system_rev & 0x0000003f -> sys_boot[0:5] - */ - /* Embedding the ES revision info in type field */ - system_rev = type; - /* Also add IDCODE revision info only two lower bits */ - system_rev |= ((rev & 0x3) << 6); - - /* Add in the device type and sys_boot fields (see above) */ - if (cpu_is_omap24xx()) { - i = OMAP24XX_CONTROL_STATUS; - } else if (cpu_is_omap343x()) { - i = OMAP343X_CONTROL_STATUS; - } else { - printk(KERN_ERR "id: unknown CPU type\n"); - BUG(); - } - ctrl_status = omap_ctrl_readl(i); - system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK | - OMAP2_SYSBOOT_4_MASK | - OMAP2_SYSBOOT_3_MASK | - OMAP2_SYSBOOT_2_MASK | - OMAP2_SYSBOOT_1_MASK | - OMAP2_SYSBOOT_0_MASK)); - system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK); -} - - -/* - * _set_omap_chip - set the omap_chip global based on OMAP chip type - * - * Build the omap_chip bits. This variable is used by powerdomain and - * clockdomain code to indicate whether structures are applicable for - * the current OMAP chip type by ANDing it against a 'platform' bitfield - * in the structure. - */ -static void __init _set_omap_chip(void) -{ - if (cpu_is_omap343x()) { - - omap_chip.oc = CHIP_IS_OMAP3430; - if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) - omap_chip.oc |= CHIP_IS_OMAP3430ES1; - else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) - omap_chip.oc |= CHIP_IS_OMAP3430ES2; - - } else if (cpu_is_omap243x()) { - - /* Currently only supports 2430ES2.1 and 2430-all */ - omap_chip.oc |= CHIP_IS_OMAP2430; - - } else if (cpu_is_omap242x()) { - - /* Currently only supports 2420ES2.1.1 and 2420-all */ - omap_chip.oc |= CHIP_IS_OMAP2420; +#define OMAP_TAP_IDCODE 0x0204 +#define OMAP_TAP_DIE_ID_0 0x0218 +#define OMAP_TAP_DIE_ID_1 0x021C +#define OMAP_TAP_DIE_ID_2 0x0220 +#define OMAP_TAP_DIE_ID_3 0x0224 - } else { +#define read_tap_reg(reg) __raw_readl(tap_base + (reg)) - /* Current CPU not supported by this code. */ - printk(KERN_WARNING "OMAP chip type code does not yet support " - "this CPU type.\n"); - WARN_ON(1); +struct omap_id { + u16 hawkeye; /* Silicon type (Hawkeye id) */ + u8 dev; /* Device type from production_id reg */ + u32 type; /* Combined type id copied to omap_revision */ +}; - } +/* Register values to detect the OMAP version */ +static struct omap_id omap_ids[] __initdata = { + { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, + { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, + { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, + { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, + { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, + { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, +}; -} +static void __iomem *tap_base; +static u16 tap_prod_id; -void __init omap2_check_revision(void) +void __init omap24xx_check_revision(void) { int i, j; - u32 idcode; - u32 prod_id; + u32 idcode, prod_id; u16 hawkeye; - u8 dev_type; - u8 rev; + u8 dev_type, rev; idcode = read_tap_reg(OMAP_TAP_IDCODE); prod_id = read_tap_reg(tap_prod_id); @@ -220,18 +101,6 @@ void __init omap2_check_revision(void) pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", prod_id, dev_type); - /* - * Detection for 34xx ES2.0 and above can be done with just - * hawkeye and rev. See TRM 1.5.2 Device Identification. - * Note that rev cannot be used directly as ES1.0 uses value 0. - */ - if (hawkeye == 0xb7ae) { - system_rev = 0x34300000 | ((1 + rev) << 12); - pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev); - _set_omap_chip(); - return; - } - /* Check hawkeye ids */ for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { if (hawkeye == omap_ids[i].hawkeye) @@ -255,23 +124,115 @@ void __init omap2_check_revision(void) j = i; } - _set_system_rev(omap_ids[j].type, rev); + pr_info("OMAP%04x", omap_rev() >> 16); + if ((omap_rev() >> 8) & 0x0f) + pr_info("ES%x", (omap_rev() >> 12) & 0xf); + pr_info("\n"); +} - _set_omap_chip(); +void __init omap34xx_check_revision(void) +{ + u32 cpuid, idcode; + u16 hawkeye; + u8 rev; + char *rev_name = "ES1.0"; - pr_info("OMAP%04x", system_rev >> 16); - if ((system_rev >> 8) & 0x0f) - pr_info("ES%x", (system_rev >> 12) & 0xf); - pr_info("\n"); + /* + * We cannot access revision registers on ES1.0. + * If the processor type is Cortex-A8 and the revision is 0x0 + * it means its Cortex r0p0 which is 3430 ES1.0. + */ + cpuid = read_cpuid(CPUID_ID); + if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { + omap_revision = OMAP3430_REV_ES1_0; + goto out; + } + /* + * Detection for 34xx ES2.0 and above can be done with just + * hawkeye and rev. See TRM 1.5.2 Device Identification. + * Note that rev does not map directly to our defined processor + * revision numbers as ES1.0 uses value 0. + */ + idcode = read_tap_reg(OMAP_TAP_IDCODE); + hawkeye = (idcode >> 12) & 0xffff; + rev = (idcode >> 28) & 0xff; + + if (hawkeye == 0xb7ae) { + switch (rev) { + case 0: + omap_revision = OMAP3430_REV_ES2_0; + rev_name = "ES2.0"; + break; + case 2: + omap_revision = OMAP3430_REV_ES2_1; + rev_name = "ES2.1"; + break; + case 3: + omap_revision = OMAP3430_REV_ES3_0; + rev_name = "ES3.0"; + break; + default: + /* Use the latest known revision as default */ + omap_revision = OMAP3430_REV_ES3_0; + rev_name = "Unknown revision\n"; + } + } + +out: + pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); } +/* + * Try to detect the exact revision of the omap we're running on + */ +void __init omap2_check_revision(void) +{ + /* + * At this point we have an idea about the processor revision set + * earlier with omap2_set_globals_tap(). + */ + if (cpu_is_omap24xx()) + omap24xx_check_revision(); + else if (cpu_is_omap34xx()) + omap34xx_check_revision(); + else + pr_err("OMAP revision unknown, please fix!\n"); + + /* + * OK, now we know the exact revision. Initialize omap_chip bits + * for powerdowmain and clockdomain code. + */ + if (cpu_is_omap243x()) { + /* Currently only supports 2430ES2.1 and 2430-all */ + omap_chip.oc |= CHIP_IS_OMAP2430; + } else if (cpu_is_omap242x()) { + /* Currently only supports 2420ES2.1.1 and 2420-all */ + omap_chip.oc |= CHIP_IS_OMAP2420; + } else if (cpu_is_omap343x()) { + omap_chip.oc = CHIP_IS_OMAP3430; + if (omap_rev() == OMAP3430_REV_ES1_0) + omap_chip.oc |= CHIP_IS_OMAP3430ES1; + else if (omap_rev() > OMAP3430_REV_ES1_0) + omap_chip.oc |= CHIP_IS_OMAP3430ES2; + } else { + pr_err("Uninitialized omap_chip, please fix!\n"); + } +} + +/* + * Set up things for map_io and processor detection later on. Gets called + * pretty much first thing from board init. For multi-omap, this gets + * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to + * detect the exact revision later on in omap2_detect_revision() once map_io + * is done. + */ void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) { - class = omap2_globals->class; + omap_revision = omap2_globals->class; tap_base = omap2_globals->tap; - if (class == 0x3430) + if (cpu_is_omap34xx()) tap_prod_id = 0x0210; else tap_prod_id = 0x0208; diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index c40fc37..636e282 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -23,6 +23,7 @@ #define INTC_REVISION 0x0000 #define INTC_SYSCONFIG 0x0010 #define INTC_SYSSTATUS 0x0014 +#define INTC_SIR 0x0040 #define INTC_CONTROL 0x0048 #define INTC_MIR_CLEAR0 0x0088 #define INTC_MIR_SET0 0x008c @@ -60,6 +61,30 @@ static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg) return __raw_readl(bank->base_reg + reg); } +static int previous_irq; + +/* + * On 34xx we can get occasional spurious interrupts if the ack from + * an interrupt handler does not get posted before we unmask. Warn about + * the interrupt handlers that need to flush posted writes. + */ +static int omap_check_spurious(unsigned int irq) +{ + u32 sir, spurious; + + sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR); + spurious = sir >> 6; + + if (spurious > 1) { + printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush " + "posted write for irq %i\n", + irq, sir, previous_irq); + return spurious; + } + + return 0; +} + /* XXX: FIQ and additional INTC support (only MPU at the moment) */ static void omap_ack_irq(unsigned int irq) { @@ -70,6 +95,20 @@ static void omap_mask_irq(unsigned int irq) { int offset = irq & (~(IRQ_BITS_PER_REG - 1)); + if (cpu_is_omap34xx()) { + int spurious = 0; + + /* + * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because + * it is the highest irq number? + */ + if (irq == INT_34XX_GPT12_IRQ) + spurious = omap_check_spurious(irq); + + if (!spurious) + previous_irq = irq; + } + irq &= (IRQ_BITS_PER_REG - 1); intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset); diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c new file mode 100644 index 0000000..437f520 --- /dev/null +++ b/arch/arm/mach-omap2/mmc-twl4030.c @@ -0,0 +1,408 @@ +/* + * linux/arch/arm/mach-omap2/mmc-twl4030.c + * + * Copyright (C) 2007-2008 Texas Instruments + * Copyright (C) 2008 Nokia Corporation + * Author: Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/i2c/twl4030.h> + +#include <mach/hardware.h> +#include <mach/control.h> +#include <mach/mmc.h> +#include <mach/board.h> + +#include "mmc-twl4030.h" + +#if defined(CONFIG_TWL4030_CORE) && \ + (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)) + +#define LDO_CLR 0x00 +#define VSEL_S2_CLR 0x40 + +#define VMMC1_DEV_GRP 0x27 +#define VMMC1_CLR 0x00 +#define VMMC1_315V 0x03 +#define VMMC1_300V 0x02 +#define VMMC1_285V 0x01 +#define VMMC1_185V 0x00 +#define VMMC1_DEDICATED 0x2A + +#define VMMC2_DEV_GRP 0x2B +#define VMMC2_CLR 0x40 +#define VMMC2_315V 0x0c +#define VMMC2_300V 0x0b +#define VMMC2_285V 0x0a +#define VMMC2_260V 0x08 +#define VMMC2_185V 0x06 +#define VMMC2_DEDICATED 0x2E + +#define VMMC_DEV_GRP_P1 0x20 + +static u16 control_pbias_offset; +static u16 control_devconf1_offset; + +#define HSMMC_NAME_LEN 9 + +static struct twl_mmc_controller { + struct omap_mmc_platform_data *mmc; + u8 twl_vmmc_dev_grp; + u8 twl_mmc_dedicated; + char name[HSMMC_NAME_LEN]; +} hsmmc[] = { + { + .twl_vmmc_dev_grp = VMMC1_DEV_GRP, + .twl_mmc_dedicated = VMMC1_DEDICATED, + }, + { + .twl_vmmc_dev_grp = VMMC2_DEV_GRP, + .twl_mmc_dedicated = VMMC2_DEDICATED, + }, +}; + +static int twl_mmc_card_detect(int irq) +{ + unsigned i; + + for (i = 0; i < ARRAY_SIZE(hsmmc); i++) { + struct omap_mmc_platform_data *mmc; + + mmc = hsmmc[i].mmc; + if (!mmc) + continue; + if (irq != mmc->slots[0].card_detect_irq) + continue; + + /* NOTE: assumes card detect signal is active-low */ + return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); + } + return -ENOSYS; +} + +static int twl_mmc_get_ro(struct device *dev, int slot) +{ + struct omap_mmc_platform_data *mmc = dev->platform_data; + + /* NOTE: assumes write protect signal is active-high */ + return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); +} + +/* + * MMC Slot Initialization. + */ +static int twl_mmc_late_init(struct device *dev) +{ + struct omap_mmc_platform_data *mmc = dev->platform_data; + int ret = 0; + int i; + + ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd"); + if (ret) + goto done; + ret = gpio_direction_input(mmc->slots[0].switch_pin); + if (ret) + goto err; + + for (i = 0; i < ARRAY_SIZE(hsmmc); i++) { + if (hsmmc[i].name == mmc->slots[0].name) { + hsmmc[i].mmc = mmc; + break; + } + } + + return 0; + +err: + gpio_free(mmc->slots[0].switch_pin); +done: + mmc->slots[0].card_detect_irq = 0; + mmc->slots[0].card_detect = NULL; + + dev_err(dev, "err %d configuring card detect\n", ret); + return ret; +} + +static void twl_mmc_cleanup(struct device *dev) +{ + struct omap_mmc_platform_data *mmc = dev->platform_data; + + gpio_free(mmc->slots[0].switch_pin); +} + +#ifdef CONFIG_PM + +static int twl_mmc_suspend(struct device *dev, int slot) +{ + struct omap_mmc_platform_data *mmc = dev->platform_data; + + disable_irq(mmc->slots[0].card_detect_irq); + return 0; +} + +static int twl_mmc_resume(struct device *dev, int slot) +{ + struct omap_mmc_platform_data *mmc = dev->platform_data; + + enable_irq(mmc->slots[0].card_detect_irq); + return 0; +} + +#else +#define twl_mmc_suspend NULL +#define twl_mmc_resume NULL +#endif + +/* + * Sets the MMC voltage in twl4030 + */ +static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd) +{ + int ret; + u8 vmmc, dev_grp_val; + + switch (1 << vdd) { + case MMC_VDD_35_36: + case MMC_VDD_34_35: + case MMC_VDD_33_34: + case MMC_VDD_32_33: + case MMC_VDD_31_32: + case MMC_VDD_30_31: + if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) + vmmc = VMMC1_315V; + else + vmmc = VMMC2_315V; + break; + case MMC_VDD_29_30: + if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) + vmmc = VMMC1_315V; + else + vmmc = VMMC2_300V; + break; + case MMC_VDD_27_28: + case MMC_VDD_26_27: + if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) + vmmc = VMMC1_285V; + else + vmmc = VMMC2_285V; + break; + case MMC_VDD_25_26: + case MMC_VDD_24_25: + case MMC_VDD_23_24: + case MMC_VDD_22_23: + case MMC_VDD_21_22: + case MMC_VDD_20_21: + if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) + vmmc = VMMC1_285V; + else + vmmc = VMMC2_260V; + break; + case MMC_VDD_165_195: + if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) + vmmc = VMMC1_185V; + else + vmmc = VMMC2_185V; + break; + default: + vmmc = 0; + break; + } + + if (vmmc) + dev_grp_val = VMMC_DEV_GRP_P1; /* Power up */ + else + dev_grp_val = LDO_CLR; /* Power down */ + + ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, + dev_grp_val, c->twl_vmmc_dev_grp); + if (ret) + return ret; + + ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, + vmmc, c->twl_mmc_dedicated); + + return ret; +} + +static int twl_mmc1_set_power(struct device *dev, int slot, int power_on, + int vdd) +{ + u32 reg; + int ret = 0; + struct twl_mmc_controller *c = &hsmmc[0]; + struct omap_mmc_platform_data *mmc = dev->platform_data; + + if (power_on) { + if (cpu_is_omap2430()) { + reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); + if ((1 << vdd) >= MMC_VDD_30_31) + reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE; + else + reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE; + omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1); + } + + if (mmc->slots[0].internal_clock) { + reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + reg |= OMAP2_MMCSDIO1ADPCLKISEL; + omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0); + } + + reg = omap_ctrl_readl(control_pbias_offset); + reg |= OMAP2_PBIASSPEEDCTRL0; + reg &= ~OMAP2_PBIASLITEPWRDNZ0; + omap_ctrl_writel(reg, control_pbias_offset); + + ret = twl_mmc_set_voltage(c, vdd); + + /* 100ms delay required for PBIAS configuration */ + msleep(100); + reg = omap_ctrl_readl(control_pbias_offset); + reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0); + if ((1 << vdd) <= MMC_VDD_165_195) + reg &= ~OMAP2_PBIASLITEVMODE0; + else + reg |= OMAP2_PBIASLITEVMODE0; + omap_ctrl_writel(reg, control_pbias_offset); + } else { + reg = omap_ctrl_readl(control_pbias_offset); + reg &= ~OMAP2_PBIASLITEPWRDNZ0; + omap_ctrl_writel(reg, control_pbias_offset); + + ret = twl_mmc_set_voltage(c, 0); + + /* 100ms delay required for PBIAS configuration */ + msleep(100); + reg = omap_ctrl_readl(control_pbias_offset); + reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 | + OMAP2_PBIASLITEVMODE0); + omap_ctrl_writel(reg, control_pbias_offset); + } + + return ret; +} + +static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vdd) +{ + int ret; + struct twl_mmc_controller *c = &hsmmc[1]; + struct omap_mmc_platform_data *mmc = dev->platform_data; + + if (power_on) { + if (mmc->slots[0].internal_clock) { + u32 reg; + + reg = omap_ctrl_readl(control_devconf1_offset); + reg |= OMAP2_MMCSDIO2ADPCLKISEL; + omap_ctrl_writel(reg, control_devconf1_offset); + } + ret = twl_mmc_set_voltage(c, vdd); + } else { + ret = twl_mmc_set_voltage(c, 0); + } + + return ret; +} + +static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; + +void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) +{ + struct twl4030_hsmmc_info *c; + int nr_hsmmc = ARRAY_SIZE(hsmmc_data); + + if (cpu_is_omap2430()) { + control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; + control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; + nr_hsmmc = 2; + } else { + control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; + control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; + } + + for (c = controllers; c->mmc; c++) { + struct twl_mmc_controller *twl = hsmmc + c->mmc - 1; + struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; + + if (!c->mmc || c->mmc > nr_hsmmc) { + pr_debug("MMC%d: no such controller\n", c->mmc); + continue; + } + if (mmc) { + pr_debug("MMC%d: already configured\n", c->mmc); + continue; + } + + mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); + if (!mmc) { + pr_err("Cannot allocate memory for mmc device!\n"); + return; + } + + sprintf(twl->name, "mmc%islot%i", c->mmc, 1); + mmc->slots[0].name = twl->name; + mmc->nr_slots = 1; + mmc->slots[0].ocr_mask = MMC_VDD_165_195 | + MMC_VDD_26_27 | MMC_VDD_27_28 | + MMC_VDD_29_30 | + MMC_VDD_30_31 | MMC_VDD_31_32; + mmc->slots[0].wires = c->wires; + mmc->slots[0].internal_clock = !c->ext_clock; + mmc->dma_mask = 0xffffffff; + + /* note: twl4030 card detect GPIOs normally switch VMMCx ... */ + if (gpio_is_valid(c->gpio_cd)) { + mmc->init = twl_mmc_late_init; + mmc->cleanup = twl_mmc_cleanup; + mmc->suspend = twl_mmc_suspend; + mmc->resume = twl_mmc_resume; + + mmc->slots[0].switch_pin = c->gpio_cd; + mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd); + mmc->slots[0].card_detect = twl_mmc_card_detect; + } else + mmc->slots[0].switch_pin = -EINVAL; + + /* write protect normally uses an OMAP gpio */ + if (gpio_is_valid(c->gpio_wp)) { + gpio_request(c->gpio_wp, "mmc_wp"); + gpio_direction_input(c->gpio_wp); + + mmc->slots[0].gpio_wp = c->gpio_wp; + mmc->slots[0].get_ro = twl_mmc_get_ro; + } else + mmc->slots[0].gpio_wp = -EINVAL; + + /* NOTE: we assume OMAP's MMC1 and MMC2 use + * the TWL4030's VMMC1 and VMMC2, respectively; + * and that OMAP's MMC3 isn't used. + */ + + switch (c->mmc) { + case 1: + mmc->slots[0].set_power = twl_mmc1_set_power; + break; + case 2: + mmc->slots[0].set_power = twl_mmc2_set_power; + break; + default: + pr_err("MMC%d configuration not supported!\n", c->mmc); + continue; + } + hsmmc_data[c->mmc - 1] = mmc; + } + + omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); +} + +#endif diff --git a/arch/arm/mach-omap2/mmc-twl4030.h b/arch/arm/mach-omap2/mmc-twl4030.h new file mode 100644 index 0000000..e1c8076 --- /dev/null +++ b/arch/arm/mach-omap2/mmc-twl4030.h @@ -0,0 +1,29 @@ +/* + * MMC definitions for OMAP2 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +struct twl4030_hsmmc_info { + u8 mmc; /* controller 1/2/3 */ + u8 wires; /* 1/4/8 wires */ + int gpio_cd; /* or -EINVAL */ + int gpio_wp; /* or -EINVAL */ + int ext_clock:1; /* use external pin for input clock */ +}; + +#if defined(CONFIG_TWL4030_CORE) && \ + (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ + defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)) + +void twl4030_mmc_init(struct twl4030_hsmmc_info *); + +#else + +static inline void twl4030_mmc_init(struct twl4030_hsmmc_info *info) +{ +} + +#endif diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index b139367..dacb41f 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -203,6 +203,15 @@ MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1) MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1) /* 2430 McBSP */ +MUX_CFG_24XX("AD6_2430_MCBSP_CLKS", 0x011E, 0, 0, 0, 1) + +MUX_CFG_24XX("AB2_2430_MCBSP1_CLKR", 0x011A, 0, 0, 0, 1) +MUX_CFG_24XX("AD5_2430_MCBSP1_FSR", 0x011B, 0, 0, 0, 1) +MUX_CFG_24XX("AA1_2430_MCBSP1_DX", 0x011C, 0, 0, 0, 1) +MUX_CFG_24XX("AF3_2430_MCBSP1_DR", 0x011D, 0, 0, 0, 1) +MUX_CFG_24XX("AB3_2430_MCBSP1_FSX", 0x011F, 0, 0, 0, 1) +MUX_CFG_24XX("Y9_2430_MCBSP1_CLKX", 0x0120, 0, 0, 0, 1) + MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1) MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1) MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1) @@ -211,6 +220,31 @@ MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1) MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1) MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1) MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1) + +MUX_CFG_24XX("AC9_2430_MCBSP3_CLKX", 0x0103, 0, 0, 0, 1) +MUX_CFG_24XX("AE4_2430_MCBSP3_FSX", 0x0104, 0, 0, 0, 1) +MUX_CFG_24XX("AE2_2430_MCBSP3_DR", 0x0105, 0, 0, 0, 1) +MUX_CFG_24XX("AF4_2430_MCBSP3_DX", 0x0106, 0, 0, 0, 1) + +MUX_CFG_24XX("N3_2430_MCBSP4_CLKX", 0x010B, 1, 0, 0, 1) +MUX_CFG_24XX("AD23_2430_MCBSP4_DR", 0x010C, 1, 0, 0, 1) +MUX_CFG_24XX("AB25_2430_MCBSP4_DX", 0x010D, 1, 0, 0, 1) +MUX_CFG_24XX("AC25_2430_MCBSP4_FSX", 0x010E, 1, 0, 0, 1) + +MUX_CFG_24XX("AE16_2430_MCBSP5_CLKX", 0x00ED, 1, 0, 0, 1) +MUX_CFG_24XX("AF12_2430_MCBSP5_FSX", 0x00ED, 1, 0, 0, 1) +MUX_CFG_24XX("K7_2430_MCBSP5_DX", 0x00EF, 1, 0, 0, 1) +MUX_CFG_24XX("M1_2430_MCBSP5_DR", 0x00F0, 1, 0, 0, 1) + +/* 2430 MCSPI1 */ +MUX_CFG_24XX("Y18_2430_MCSPI1_CLK", 0x010F, 0, 0, 0, 1) +MUX_CFG_24XX("AD15_2430_MCSPI1_SIMO", 0x0110, 0, 0, 0, 1) +MUX_CFG_24XX("AE17_2430_MCSPI1_SOMI", 0x0111, 0, 0, 0, 1) +MUX_CFG_24XX("U1_2430_MCSPI1_CS0", 0x0112, 0, 0, 0, 1) + +/* Touchscreen GPIO */ +MUX_CFG_24XX("AF19_2430_GPIO_85", 0x0113, 3, 0, 0, 1) + }; #define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins) @@ -417,6 +451,14 @@ MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188, MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a, OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) + +/* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix. + * No internal pullup/pulldown without "_UP" or "_DOWN" suffix. + */ +MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) +MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6, + OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) }; #define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins) @@ -452,7 +494,7 @@ static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 r #endif #ifdef CONFIG_ARCH_OMAP24XX -int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) +static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) { static DEFINE_SPINLOCK(mux_spin_lock); unsigned long flags; diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 10ef464..15e5090 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c @@ -12,11 +12,11 @@ #include <linux/errno.h> #include <linux/delay.h> #include <linux/platform_device.h> +#include <linux/gpio.h> #include <linux/usb/musb.h> #include <mach/gpmc.h> -#include <mach/gpio.h> #include <mach/mux.h> @@ -292,12 +292,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data, ); /* IRQ */ - status = omap_request_gpio(irq); + status = gpio_request(irq, "TUSB6010 irq"); if (status < 0) { printk(error, 3, status); return status; } - omap_set_gpio_direction(irq, 1); + gpio_direction_input(irq); tusb_resources[2].start = irq + IH_GPIO_BASE; /* set up memory timings ... can speed them up later */ diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 3d4a1bc..edc38e2 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -1,4 +1,4 @@ -obj-y += common.o addr-map.o pci.o gpio.o irq.o mpp.o +obj-y += common.o addr-map.o pci.o irq.o mpp.o obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 437065c..0a62337 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -72,6 +72,7 @@ void __init orion5x_map_io(void) ****************************************************************************/ static struct orion_ehci_data orion5x_ehci_data = { .dram = &orion5x_mbus_dram_info, + .phy_version = EHCI_PHY_ORION, }; static u64 ehci_dmamask = 0xffffffffUL; diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index a000c7c..798b9a5 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -51,13 +51,6 @@ int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); -/* - * Valid GPIO pins according to MPP setup, used by machine-setup. - * (/mach-orion/gpio.c). - */ -void orion5x_gpio_set_valid(unsigned pin, int valid); -void gpio_display(void); /* debug */ - struct machine_desc; struct meminfo; struct tag; diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 3e66098..0722d65 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -21,6 +21,7 @@ #include <linux/gpio_keys.h> #include <linux/input.h> #include <linux/i2c.h> +#include <linux/ata_platform.h> #include <asm/mach-types.h> #include <asm/gpio.h> #include <asm/mach/arch.h> @@ -64,9 +65,21 @@ static struct hw_pci dns323_pci __initdata = { .map_irq = dns323_pci_map_irq, }; +static int __init dns323_dev_id(void) +{ + u32 dev, rev; + + orion5x_pcie_id(&dev, &rev); + + return dev; +} + static int __init dns323_pci_init(void) { - if (machine_is_dns323()) + /* The 5182 doesn't really use it's PCI bus, and initialising PCI + * gets in the way of initialising the SATA controller. + */ + if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID) pci_common_init(&dns323_pci); return 0; @@ -75,14 +88,6 @@ static int __init dns323_pci_init(void) subsys_initcall(dns323_pci_init); /**************************************************************************** - * Ethernet - */ - -static struct mv643xx_eth_platform_data dns323_eth_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/**************************************************************************** * 8MiB NOR flash (Spansion S29GL064M90TFIR4) * * Layout as used by D-Link: @@ -143,6 +148,90 @@ static struct platform_device dns323_nor_flash = { }; /**************************************************************************** + * Ethernet + */ + +static struct mv643xx_eth_platform_data dns323_eth_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + +/* dns323_parse_hex_*() taken from tsx09-common.c; should a common copy of these + * functions be kept somewhere? + */ +static int __init dns323_parse_hex_nibble(char n) +{ + if (n >= '0' && n <= '9') + return n - '0'; + + if (n >= 'A' && n <= 'F') + return n - 'A' + 10; + + if (n >= 'a' && n <= 'f') + return n - 'a' + 10; + + return -1; +} + +static int __init dns323_parse_hex_byte(const char *b) +{ + int hi; + int lo; + + hi = dns323_parse_hex_nibble(b[0]); + lo = dns323_parse_hex_nibble(b[1]); + + if (hi < 0 || lo < 0) + return -1; + + return (hi << 4) | lo; +} + +static int __init dns323_read_mac_addr(void) +{ + u_int8_t addr[6]; + int i; + char *mac_page; + + /* MAC address is stored as a regular ol' string in /dev/mtdblock4 + * (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80). + */ + mac_page = ioremap(DNS323_NOR_BOOT_BASE + 0x7d0000 + 196480, 1024); + if (!mac_page) + return -ENOMEM; + + /* Sanity check the string we're looking at */ + for (i = 0; i < 5; i++) { + if (*(mac_page + (i * 3) + 2) != ':') { + goto error_fail; + } + } + + for (i = 0; i < 6; i++) { + int byte; + + byte = dns323_parse_hex_byte(mac_page + (i * 3)); + if (byte < 0) { + goto error_fail; + } + + addr[i] = byte; + } + + iounmap(mac_page); + printk("DNS323: Found ethernet MAC address: "); + for (i = 0; i < 6; i++) + printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); + + memcpy(dns323_eth_data.mac_addr, addr, 6); + + return 0; + +error_fail: + iounmap(mac_page); + return -EINVAL; +} + +/**************************************************************************** * GPIO LEDs (simple - doesn't use hardware blinking support) */ @@ -207,10 +296,17 @@ static struct platform_device dns323_button_device = { }, }; +/***************************************************************************** + * SATA + */ +static struct mv_sata_platform_data dns323_sata_data = { + .n_ports = 2, +}; + /**************************************************************************** * General Setup */ -static struct orion5x_mpp_mode dns323_mpp_modes[] __initdata = { +static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = { { 0, MPP_PCIE_RST_OUTn }, { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ @@ -234,6 +330,30 @@ static struct orion5x_mpp_mode dns323_mpp_modes[] __initdata = { { -1 }, }; +static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = { + { 0, MPP_UNUSED }, + { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ + { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ + { 3, MPP_UNUSED }, + { 4, MPP_GPIO }, /* power button LED */ + { 5, MPP_GPIO }, /* power button LED */ + { 6, MPP_GPIO }, /* GMT G751-2f overtemp */ + { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */ + { 8, MPP_GPIO }, /* triggers power off */ + { 9, MPP_GPIO }, /* power button switch */ + { 10, MPP_GPIO }, /* reset button switch */ + { 11, MPP_UNUSED }, + { 12, MPP_SATA_LED }, + { 13, MPP_SATA_LED }, + { 14, MPP_SATA_LED }, + { 15, MPP_SATA_LED }, + { 16, MPP_UNUSED }, + { 17, MPP_UNUSED }, + { 18, MPP_UNUSED }, + { 19, MPP_UNUSED }, + { -1 }, +}; + /* * On the DNS-323 the following devices are attached via I2C: * @@ -264,16 +384,15 @@ static void __init dns323_init(void) /* Setup basic Orion functions. Need to be called early. */ orion5x_init(); - orion5x_mpp_conf(dns323_mpp_modes); - writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ - - /* - * Configure peripherals. + /* Just to be tricky, the 5182 has a completely different + * set of MPP modes to the 5181. */ - orion5x_ehci0_init(); - orion5x_eth_init(&dns323_eth_data); - orion5x_i2c_init(); - orion5x_uart0_init(); + if (dns323_dev_id() == MV88F5182_DEV_ID) + orion5x_mpp_conf(dns323_mv88f5182_mpp_modes); + else { + orion5x_mpp_conf(dns323_mv88f5181_mpp_modes); + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ + } /* setup flash mapping * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 @@ -288,6 +407,23 @@ static void __init dns323_init(void) i2c_register_board_info(0, dns323_i2c_devices, ARRAY_SIZE(dns323_i2c_devices)); + /* + * Configure peripherals. + */ + if (dns323_read_mac_addr() < 0) + printk("DNS323: Failed to read MAC address\n"); + + orion5x_ehci0_init(); + orion5x_eth_init(&dns323_eth_data); + orion5x_i2c_init(); + orion5x_uart0_init(); + + /* The 5182 has it's SATA controller on-chip, and needs it's own little + * init routine. + */ + if (dns323_dev_id() == MV88F5182_DEV_ID) + orion5x_sata_init(&dns323_sata_data); + /* register dns323 specific power-off method */ if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) diff --git a/arch/arm/mach-orion5x/gpio.c b/arch/arm/mach-orion5x/gpio.c deleted file mode 100644 index f99d088..0000000 --- a/arch/arm/mach-orion5x/gpio.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * arch/arm/mach-orion5x/gpio.c - * - * GPIO functions for Marvell Orion System On Chip - * - * Maintainer: Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/spinlock.h> -#include <linux/bitops.h> -#include <linux/io.h> -#include <asm/gpio.h> -#include <mach/orion5x.h> -#include "common.h" - -static DEFINE_SPINLOCK(gpio_lock); -static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; -static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ - -void __init orion5x_gpio_set_valid(unsigned pin, int valid) -{ - if (valid) - __set_bit(pin, gpio_valid); - else - __clear_bit(pin, gpio_valid); -} - -/* - * GENERIC_GPIO primitives - */ -int gpio_direction_input(unsigned pin) -{ - unsigned long flags; - - if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { - pr_debug("%s: invalid GPIO %d\n", __func__, pin); - return -EINVAL; - } - - spin_lock_irqsave(&gpio_lock, flags); - - /* - * Some callers might have not used the gpio_request(), - * so flag this pin as requested now. - */ - if (!gpio_label[pin]) - gpio_label[pin] = "?"; - - orion5x_setbits(GPIO_IO_CONF, 1 << pin); - - spin_unlock_irqrestore(&gpio_lock, flags); - return 0; -} -EXPORT_SYMBOL(gpio_direction_input); - -int gpio_direction_output(unsigned pin, int value) -{ - unsigned long flags; - int mask; - - if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { - pr_debug("%s: invalid GPIO %d\n", __func__, pin); - return -EINVAL; - } - - spin_lock_irqsave(&gpio_lock, flags); - - /* - * Some callers might have not used the gpio_request(), - * so flag this pin as requested now. - */ - if (!gpio_label[pin]) - gpio_label[pin] = "?"; - - mask = 1 << pin; - orion5x_clrbits(GPIO_BLINK_EN, mask); - if (value) - orion5x_setbits(GPIO_OUT, mask); - else - orion5x_clrbits(GPIO_OUT, mask); - orion5x_clrbits(GPIO_IO_CONF, mask); - - spin_unlock_irqrestore(&gpio_lock, flags); - return 0; -} -EXPORT_SYMBOL(gpio_direction_output); - -int gpio_get_value(unsigned pin) -{ - int val, mask = 1 << pin; - - if (readl(GPIO_IO_CONF) & mask) - val = readl(GPIO_DATA_IN) ^ readl(GPIO_IN_POL); - else - val = readl(GPIO_OUT); - - return val & mask; -} -EXPORT_SYMBOL(gpio_get_value); - -void gpio_set_value(unsigned pin, int value) -{ - unsigned long flags; - int mask = 1 << pin; - - spin_lock_irqsave(&gpio_lock, flags); - - orion5x_clrbits(GPIO_BLINK_EN, mask); - if (value) - orion5x_setbits(GPIO_OUT, mask); - else - orion5x_clrbits(GPIO_OUT, mask); - - spin_unlock_irqrestore(&gpio_lock, flags); -} -EXPORT_SYMBOL(gpio_set_value); - -void orion5x_gpio_set_blink(unsigned pin, int blink) -{ - unsigned long flags; - int mask = 1 << pin; - - spin_lock_irqsave(&gpio_lock, flags); - - orion5x_clrbits(GPIO_OUT, mask); - if (blink) - orion5x_setbits(GPIO_BLINK_EN, mask); - else - orion5x_clrbits(GPIO_BLINK_EN, mask); - - spin_unlock_irqrestore(&gpio_lock, flags); -} -EXPORT_SYMBOL(orion5x_gpio_set_blink); - -int gpio_request(unsigned pin, const char *label) -{ - int ret = 0; - unsigned long flags; - - if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { - pr_debug("%s: invalid GPIO %d\n", __func__, pin); - return -EINVAL; - } - - spin_lock_irqsave(&gpio_lock, flags); - - if (gpio_label[pin]) { - pr_debug("%s: GPIO %d already used as %s\n", - __func__, pin, gpio_label[pin]); - ret = -EBUSY; - } else - gpio_label[pin] = label ? label : "?"; - - spin_unlock_irqrestore(&gpio_lock, flags); - return ret; -} -EXPORT_SYMBOL(gpio_request); - -void gpio_free(unsigned pin) -{ - might_sleep(); - - if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { - pr_debug("%s: invalid GPIO %d\n", __func__, pin); - return; - } - - if (!gpio_label[pin]) - pr_warning("%s: GPIO %d already freed\n", __func__, pin); - else - gpio_label[pin] = NULL; -} -EXPORT_SYMBOL(gpio_free); - -/* Debug helper */ -void gpio_display(void) -{ - int i; - - for (i = 0; i < GPIO_MAX; i++) { - printk(KERN_DEBUG "Pin-%d: ", i); - - if (!test_bit(i, gpio_valid)) { - printk("non-GPIO\n"); - } else if (!gpio_label[i]) { - printk("GPIO, free\n"); - } else { - printk("GPIO, used by %s, ", gpio_label[i]); - if (readl(GPIO_IO_CONF) & (1 << i)) { - printk("input, active %s, level %s, edge %s\n", - ((readl(GPIO_IN_POL) >> i) & 1) ? "low" : "high", - ((readl(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", - ((readl(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); - } else { - printk("output, val=%d\n", (readl(GPIO_OUT) >> i) & 1); - } - } - } - - printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", - MPP_0_7_CTRL, readl(MPP_0_7_CTRL)); - printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", - MPP_8_15_CTRL, readl(MPP_8_15_CTRL)); - printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", - MPP_16_19_CTRL, readl(MPP_16_19_CTRL)); - printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", - MPP_DEV_CTRL, readl(MPP_DEV_CTRL)); - printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", - GPIO_OUT, readl(GPIO_OUT)); - printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", - GPIO_IO_CONF, readl(GPIO_IO_CONF)); - printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", - GPIO_BLINK_EN, readl(GPIO_BLINK_EN)); - printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", - GPIO_IN_POL, readl(GPIO_IN_POL)); - printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", - GPIO_DATA_IN, readl(GPIO_DATA_IN)); - printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", - GPIO_LEVEL_MASK, readl(GPIO_LEVEL_MASK)); - printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", - GPIO_EDGE_CAUSE, readl(GPIO_EDGE_CAUSE)); - printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", - GPIO_EDGE_MASK, readl(GPIO_EDGE_MASK)); -} diff --git a/arch/arm/mach-orion5x/include/mach/dma.h b/arch/arm/mach-orion5x/include/mach/dma.h deleted file mode 100644 index 40a8c17..0000000 --- a/arch/arm/mach-orion5x/include/mach/dma.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h index 65dc136..d8182e8 100644 --- a/arch/arm/mach-orion5x/include/mach/gpio.h +++ b/arch/arm/mach-orion5x/include/mach/gpio.h @@ -2,18 +2,26 @@ * arch/arm/mach-orion5x/include/mach/gpio.h * * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -extern int gpio_request(unsigned pin, const char *label); -extern void gpio_free(unsigned pin); -extern int gpio_direction_input(unsigned pin); -extern int gpio_direction_output(unsigned pin, int value); -extern int gpio_get_value(unsigned pin); -extern void gpio_set_value(unsigned pin, int value); -extern void orion5x_gpio_set_blink(unsigned pin, int blink); -extern void gpio_display(void); /* debug */ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#include <mach/irqs.h> +#include <plat/gpio.h> +#include <asm-generic/gpio.h> /* cansleep wrappers */ + +#define GPIO_MAX 32 +#define GPIO_OUT(pin) ORION5X_DEV_BUS_REG(0x100) +#define GPIO_IO_CONF(pin) ORION5X_DEV_BUS_REG(0x104) +#define GPIO_BLINK_EN(pin) ORION5X_DEV_BUS_REG(0x108) +#define GPIO_IN_POL(pin) ORION5X_DEV_BUS_REG(0x10c) +#define GPIO_DATA_IN(pin) ORION5X_DEV_BUS_REG(0x110) +#define GPIO_EDGE_CAUSE(pin) ORION5X_DEV_BUS_REG(0x114) +#define GPIO_EDGE_MASK(pin) ORION5X_DEV_BUS_REG(0x118) +#define GPIO_LEVEL_MASK(pin) ORION5X_DEV_BUS_REG(0x11c) static inline int gpio_to_irq(int pin) { @@ -25,4 +33,5 @@ static inline int irq_to_gpio(int irq) return irq - IRQ_ORION5X_GPIO_START; } -#include <asm-generic/gpio.h> /* cansleep wrappers */ + +#endif diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h index f24b251..c47b033 100644 --- a/arch/arm/mach-orion5x/include/mach/io.h +++ b/arch/arm/mach-orion5x/include/mach/io.h @@ -38,14 +38,9 @@ __arch_iounmap(void __iomem *addr) __iounmap(addr); } -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)addr; -} - #define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m) #define __arch_iounmap(a) __arch_iounmap(a) -#define __io(a) __io(a) +#define __io(a) __typesafe_io(a) #define __mem_pci(a) (a) diff --git a/arch/arm/mach-orion5x/include/mach/irqs.h b/arch/arm/mach-orion5x/include/mach/irqs.h index d5b0fbf..a6fa9d8 100644 --- a/arch/arm/mach-orion5x/include/mach/irqs.h +++ b/arch/arm/mach-orion5x/include/mach/irqs.h @@ -13,8 +13,6 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H -#include "orion5x.h" /* need GPIO_MAX */ - /* * Orion Main Interrupt Controller */ @@ -54,7 +52,7 @@ * Orion General Purpose Pins */ #define IRQ_ORION5X_GPIO_START 32 -#define NR_GPIO_IRQS GPIO_MAX +#define NR_GPIO_IRQS 32 #define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) diff --git a/arch/arm/mach-orion5x/include/mach/memory.h b/arch/arm/mach-orion5x/include/mach/memory.h index 54dd76b..52a2955 100644 --- a/arch/arm/mach-orion5x/include/mach/memory.h +++ b/arch/arm/mach-orion5x/include/mach/memory.h @@ -9,8 +9,4 @@ #define PHYS_OFFSET UL(0x00000000) -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - - #endif diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 9f5ce1c..67bda31 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -134,14 +134,6 @@ #define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) #define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) #define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) -#define GPIO_OUT ORION5X_DEV_BUS_REG(0x100) -#define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104) -#define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108) -#define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c) -#define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110) -#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114) -#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118) -#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c) #define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) #define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) #define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) @@ -149,7 +141,6 @@ #define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) #define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) #define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) -#define GPIO_MAX 32 /*************************************************************************** * Orion CPU Bridge Registers diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index 632a36f..0caae43 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -19,193 +19,38 @@ #include <plat/irq.h> #include "common.h" -/***************************************************************************** - * Orion GPIO IRQ - * - * GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same - * value of the line or the opposite value. - * - * Level IRQ handlers: DATA_IN is used directly as cause register. - * Interrupt are masked by LEVEL_MASK registers. - * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. - * Interrupt are masked by EDGE_MASK registers. - * Both-edge handlers: Similar to regular Edge handlers, but also swaps - * the polarity to catch the next line transaction. - * This is a race condition that might not perfectly - * work on some use cases. - * - * Every eight GPIO lines are grouped (OR'ed) before going up to main - * cause register. - * - * EDGE cause mask - * data-in /--------| |-----| |----\ - * -----| |----- ---- to main cause reg - * X \----------------| |----/ - * polarity LEVEL mask - * - ****************************************************************************/ -static void orion5x_gpio_irq_ack(u32 irq) -{ - int pin = irq_to_gpio(irq); - if (irq_desc[irq].status & IRQ_LEVEL) - /* - * Mask bit for level interrupt - */ - orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); - else - /* - * Clear casue bit for egde interrupt - */ - orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin); -} - -static void orion5x_gpio_irq_mask(u32 irq) -{ - int pin = irq_to_gpio(irq); - if (irq_desc[irq].status & IRQ_LEVEL) - orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); - else - orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin); -} - -static void orion5x_gpio_irq_unmask(u32 irq) +static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { - int pin = irq_to_gpio(irq); - if (irq_desc[irq].status & IRQ_LEVEL) - orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin); - else - orion5x_setbits(GPIO_EDGE_MASK, 1 << pin); -} - -static int orion5x_gpio_set_irq_type(u32 irq, u32 type) -{ - int pin = irq_to_gpio(irq); - struct irq_desc *desc; - - if ((readl(GPIO_IO_CONF) & (1 << pin)) == 0) { - printk(KERN_ERR "orion5x_gpio_set_irq_type failed " - "(irq %d, pin %d).\n", irq, pin); - return -EINVAL; - } - - desc = irq_desc + irq; - - switch (type) { - case IRQ_TYPE_LEVEL_HIGH: - desc->handle_irq = handle_level_irq; - desc->status |= IRQ_LEVEL; - orion5x_clrbits(GPIO_IN_POL, (1 << pin)); - break; - case IRQ_TYPE_LEVEL_LOW: - desc->handle_irq = handle_level_irq; - desc->status |= IRQ_LEVEL; - orion5x_setbits(GPIO_IN_POL, (1 << pin)); - break; - case IRQ_TYPE_EDGE_RISING: - desc->handle_irq = handle_edge_irq; - desc->status &= ~IRQ_LEVEL; - orion5x_clrbits(GPIO_IN_POL, (1 << pin)); - break; - case IRQ_TYPE_EDGE_FALLING: - desc->handle_irq = handle_edge_irq; - desc->status &= ~IRQ_LEVEL; - orion5x_setbits(GPIO_IN_POL, (1 << pin)); - break; - case IRQ_TYPE_EDGE_BOTH: - desc->handle_irq = handle_edge_irq; - desc->status &= ~IRQ_LEVEL; - /* - * set initial polarity based on current input level - */ - if ((readl(GPIO_IN_POL) ^ readl(GPIO_DATA_IN)) - & (1 << pin)) - orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ - else - orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ - - break; - default: - printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type); - return -EINVAL; - } - - desc->status &= ~IRQ_TYPE_SENSE_MASK; - desc->status |= type & IRQ_TYPE_SENSE_MASK; - - return 0; -} - -static struct irq_chip orion5x_gpio_irq_chip = { - .name = "Orion-IRQ-GPIO", - .ack = orion5x_gpio_irq_ack, - .mask = orion5x_gpio_irq_mask, - .unmask = orion5x_gpio_irq_unmask, - .set_type = orion5x_gpio_set_irq_type, -}; - -static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - u32 cause, offs, pin; - BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); - offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8; - cause = (readl(GPIO_DATA_IN) & readl(GPIO_LEVEL_MASK)) | - (readl(GPIO_EDGE_CAUSE) & readl(GPIO_EDGE_MASK)); - for (pin = offs; pin < offs + 8; pin++) { - if (cause & (1 << pin)) { - irq = gpio_to_irq(pin); - desc = irq_desc + irq; - if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { - /* Swap polarity (race with GPIO line) */ - u32 polarity = readl(GPIO_IN_POL); - polarity ^= 1 << pin; - writel(polarity, GPIO_IN_POL); - } - generic_handle_irq(irq); - } - } + orion_gpio_irq_handler((irq - IRQ_ORION5X_GPIO_0_7) << 3); } -static void __init orion5x_init_gpio_irq(void) +void __init orion5x_init_irq(void) { int i; - struct irq_desc *desc; + + orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); /* * Mask and clear GPIO IRQ interrupts */ - writel(0x0, GPIO_LEVEL_MASK); - writel(0x0, GPIO_EDGE_MASK); - writel(0x0, GPIO_EDGE_CAUSE); + writel(0x0, GPIO_LEVEL_MASK(0)); + writel(0x0, GPIO_EDGE_MASK(0)); + writel(0x0, GPIO_EDGE_CAUSE(0)); /* * Register chained level handlers for GPIO IRQs by default. * User can use set_type() if he wants to use edge types handlers. */ for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { - set_irq_chip(i, &orion5x_gpio_irq_chip); + set_irq_chip(i, &orion_gpio_irq_level_chip); set_irq_handler(i, handle_level_irq); - desc = irq_desc + i; - desc->status |= IRQ_LEVEL; + irq_desc[i].status |= IRQ_LEVEL; set_irq_flags(i, IRQF_VALID); } - set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler); -} - -/***************************************************************************** - * Orion Main IRQ - ****************************************************************************/ -static void __init orion5x_init_main_irq(void) -{ - orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); -} - -void __init orion5x_init_irq(void) -{ - orion5x_init_main_irq(); - orion5x_init_gpio_irq(); + set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); } diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index 640ea2a..e23a3f9 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -12,6 +12,7 @@ #include <linux/init.h> #include <linux/mbus.h> #include <linux/io.h> +#include <asm/gpio.h> #include <mach/hardware.h> #include "common.h" #include "mpp.h" @@ -152,7 +153,10 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode) *reg &= ~(0xf << shift); *reg |= (num_type & 0xf) << shift; - orion5x_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO)); + if (mode->type == MPP_UNUSED && (mode->mpp < 16 || is_5182())) + orion_gpio_set_unused(mode->mpp); + + orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO)); mode++; } diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c index ac2f70e..425f718 100644 --- a/arch/arm/mach-pnx4008/dma.c +++ b/arch/arm/mach-pnx4008/dma.c @@ -25,9 +25,8 @@ #include <asm/system.h> #include <mach/hardware.h> -#include <asm/dma.h> +#include <mach/dma.h> #include <asm/dma-mapping.h> -#include <asm/mach/dma.h> #include <mach/clock.h> static struct dma_channel { diff --git a/arch/arm/mach-pnx4008/include/mach/dma.h b/arch/arm/mach-pnx4008/include/mach/dma.h index 5442d04..f094bf8 100644 --- a/arch/arm/mach-pnx4008/include/mach/dma.h +++ b/arch/arm/mach-pnx4008/include/mach/dma.h @@ -16,8 +16,6 @@ #include "platform.h" -#define MAX_DMA_ADDRESS 0xffffffff - #define MAX_DMA_CHANNELS 8 #define DMAC_BASE IO_ADDRESS(PNX4008_DMA_CONFIG_BASE) diff --git a/arch/arm/mach-pnx4008/include/mach/io.h b/arch/arm/mach-pnx4008/include/mach/io.h index c6206f2..cbf0904 100644 --- a/arch/arm/mach-pnx4008/include/mach/io.h +++ b/arch/arm/mach-pnx4008/include/mach/io.h @@ -15,7 +15,7 @@ #define IO_SPACE_LIMIT 0xffffffff -#define __io(a) ((void __iomem *)(a)) -#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-pnx4008/include/mach/memory.h b/arch/arm/mach-pnx4008/include/mach/memory.h index 5789a2d..0e87700 100644 --- a/arch/arm/mach-pnx4008/include/mach/memory.h +++ b/arch/arm/mach-pnx4008/include/mach/memory.h @@ -16,9 +16,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET (0x80000000) - -#define __virt_to_bus(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) -#define __bus_to_virt(x) ((x) + PAGE_OFFSET - PHYS_OFFSET) +#define PHYS_OFFSET UL(0x80000000) #endif diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index a062235..8eea730 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -19,20 +19,34 @@ config CPU_PXA320 config CPU_PXA930 bool "PXA930 (codename Tavor-P)" +config CPU_PXA935 + bool "PXA935 (codename Tavor-P65)" + endmenu endif config ARCH_GUMSTIX - bool "Gumstix XScale boards" + bool "Gumstix XScale 255 boards" + select PXA25x help - Say Y here if you intend to run this kernel on a - Gumstix Full Function Minature Computer. + Say Y here if you intend to run this kernel on + Basix, Connex, ws-200ax, ws-400ax systems -config MACH_GUMSTIX_F - bool "Basix, Connex, ws-200ax, ws-400ax systems" +choice + prompt "Gumstix Carrier/Expansion Board" depends on ARCH_GUMSTIX - select PXA25x + +config GUMSTIX_AM200EPD + bool "Enable AM200EPD board support" + +endchoice + +config MACH_INTELMOTE2 + bool "Intel Mote 2 Platform" + select PXA27x + select IWMMXT + select PXA_HAVE_BOARD_IRQS config ARCH_LUBBOCK bool "Intel DBPXA250 Development Platform" @@ -199,6 +213,10 @@ config MACH_E800 config TRIZEPS_PXA bool "PXA based Keith und Koep Trizeps DIMM-Modules" +config MACH_H5000 + bool "HP iPAQ h5000" + select PXA25x + config MACH_TRIZEPS4 bool "Keith und Koep Trizeps4 DIMM-Module" depends on TRIZEPS_PXA @@ -283,7 +301,6 @@ config MACH_MIOA701 bool "Mitac Mio A701 Support" select PXA27x select IWMMXT - select LEDS_GPIO select HAVE_PWM select GPIO_SYSFS help @@ -342,10 +359,6 @@ config PCM990_DISPLAY_NONE endchoice -config MACH_AM200EPD - depends on MACH_GUMSTIX_F - bool "Enable AM200EPD board support" - config PXA_EZX bool "Motorola EZX Platform" select PXA27x @@ -386,16 +399,25 @@ endmenu config PXA25x bool + select CPU_XSCALE help Select code specific to PXA21x/25x/26x variants config PXA27x bool + select CPU_XSCALE help Select code specific to PXA27x variants +config CPU_PXA26x + bool + select PXA25x + help + Select code specific to PXA26x (codename Dalhart) + config PXA3xx bool + select CPU_XSC3 help Select code specific to PXA3xx variants diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index d64c68b..7b28bb5 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -27,7 +27,7 @@ obj-$(CONFIG_CPU_PXA930) += pxa930.o # Specific board support obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o -obj-$(CONFIG_MACH_AM200EPD) += am200epd.o +obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o @@ -35,6 +35,7 @@ obj-$(CONFIG_MACH_MP900C) += mp900.o obj-$(CONFIG_ARCH_PXA_IDP) += idp.o obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o obj-$(CONFIG_MACH_COLIBRI) += colibri.o +obj-$(CONFIG_MACH_H5000) += h5000.o obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o @@ -69,6 +70,8 @@ obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx.o cm-x255.o cm-x270.o obj-$(CONFIG_MACH_CM_X300) += cm-x300.o obj-$(CONFIG_PXA_EZX) += ezx.o +obj-$(CONFIG_MACH_INTELMOTE2) += imote2.o + # Support for blinky lights led-y := leds.o led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c index b965085..77ee80e 100644 --- a/arch/arm/mach-pxa/am200epd.c +++ b/arch/arm/mach-pxa/am200epd.c @@ -30,8 +30,12 @@ #include <linux/irq.h> #include <linux/gpio.h> +#include <mach/gumstix.h> +#include <mach/mfp-pxa25x.h> #include <mach/pxafb.h> +#include "generic.h" + #include <video/metronomefb.h> static unsigned int panel_type = 6; @@ -331,7 +335,16 @@ static struct metronome_board am200_board = { .cleanup = am200_cleanup, }; -static int __init am200_init(void) +static unsigned long am200_pin_config[] __initdata = { + GPIO51_GPIO, + GPIO49_GPIO, + GPIO48_GPIO, + GPIO32_GPIO, + GPIO17_GPIO, + GPIO16_GPIO, +}; + +int __init am200_init(void) { int ret; @@ -339,6 +352,8 @@ static int __init am200_init(void) * creation events */ fb_register_client(&am200_fb_notif); + pxa2xx_mfp_config(ARRAY_AND_SIZE(am200_pin_config)); + /* request our platform independent driver */ request_module("metronomefb"); @@ -367,8 +382,6 @@ static int __init am200_init(void) module_param(panel_type, uint, 0); MODULE_PARM_DESC(panel_type, "Select the panel type: 6, 8, 97"); -module_init(am200_init); - MODULE_DESCRIPTION("board driver for am200 metronome epd kit"); MODULE_AUTHOR("Jaya Kumar"); MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index ca8e205..40b7740 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c @@ -12,53 +12,16 @@ #include <linux/platform_device.h> #include <linux/delay.h> +#include <asm/clkdev.h> #include <mach/pxa2xx-regs.h> -#include <mach/pxa2xx-gpio.h> #include <mach/hardware.h> #include "devices.h" #include "generic.h" #include "clock.h" -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); static DEFINE_SPINLOCK(clocks_lock); -static struct clk *clk_lookup(struct device *dev, const char *id) -{ - struct clk *p; - - list_for_each_entry(p, &clocks, node) - if (strcmp(id, p->name) == 0 && p->dev == dev) - return p; - - return NULL; -} - -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p, *clk = ERR_PTR(-ENOENT); - - mutex_lock(&clocks_mutex); - p = clk_lookup(dev, id); - if (!p) - p = clk_lookup(NULL, id); - if (p) - clk = p; - mutex_unlock(&clocks_mutex); - - if (!IS_ERR(clk) && clk->ops == NULL) - clk = clk->other; - - return clk; -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - int clk_enable(struct clk *clk) { unsigned long flags; @@ -116,37 +79,27 @@ const struct clkops clk_cken_ops = { .disable = clk_cken_disable, }; -void clks_register(struct clk *clks, size_t num) +void clks_register(struct clk_lookup *clks, size_t num) { int i; - mutex_lock(&clocks_mutex); for (i = 0; i < num; i++) - list_add(&clks[i].node, &clocks); - mutex_unlock(&clocks_mutex); + clkdev_add(&clks[i]); } int clk_add_alias(char *alias, struct device *alias_dev, char *id, struct device *dev) { - struct clk *r = clk_lookup(dev, id); - struct clk *new; + struct clk *r = clk_get(dev, id); + struct clk_lookup *l; if (!r) return -ENODEV; - new = kzalloc(sizeof(struct clk), GFP_KERNEL); - - if (!new) - return -ENOMEM; - - new->name = alias; - new->dev = alias_dev; - new->other = r; - - mutex_lock(&clocks_mutex); - list_add(&new->node, &clocks); - mutex_unlock(&clocks_mutex); - + l = clkdev_alloc(r, alias, alias_dev ? dev_name(alias_dev) : NULL); + clk_put(r); + if (!l) + return -ENODEV; + clkdev_add(l); return 0; } diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h index 73be795..4e9c613 100644 --- a/arch/arm/mach-pxa/clock.h +++ b/arch/arm/mach-pxa/clock.h @@ -1,6 +1,4 @@ -#include <linux/list.h> - -struct clk; +#include <asm/clkdev.h> struct clkops { void (*enable)(struct clk *); @@ -9,9 +7,6 @@ struct clkops { }; struct clk { - struct list_head node; - const char *name; - struct device *dev; const struct clkops *ops; unsigned long rate; unsigned int cken; @@ -20,41 +15,31 @@ struct clk { struct clk *other; }; -#define INIT_CKEN(_name, _cken, _rate, _delay, _dev) \ +#define INIT_CLKREG(_clk,_devname,_conname) \ { \ - .name = _name, \ - .dev = _dev, \ + .clk = _clk, \ + .dev_id = _devname, \ + .con_id = _conname, \ + } + +#define DEFINE_CKEN(_name, _cken, _rate, _delay) \ +struct clk clk_##_name = { \ .ops = &clk_cken_ops, \ .rate = _rate, \ .cken = CKEN_##_cken, \ .delay = _delay, \ } -#define INIT_CK(_name, _cken, _ops, _dev) \ - { \ - .name = _name, \ - .dev = _dev, \ +#define DEFINE_CK(_name, _cken, _ops) \ +struct clk clk_##_name = { \ .ops = _ops, \ .cken = CKEN_##_cken, \ } -/* - * This is a placeholder to alias one clock device+name pair - * to another struct clk. - */ -#define INIT_CKOTHER(_name, _other, _dev) \ - { \ - .name = _name, \ - .dev = _dev, \ - .other = _other, \ - } - -#define INIT_CLK(_name, _ops, _rate, _delay, _dev) \ - { \ - .name = _name, \ - .dev = _dev, \ - .ops = _ops, \ - .rate = _rate, \ +#define DEFINE_CLK(_name, _ops, _rate, _delay) \ +struct clk clk_##_name = { \ + .ops = _ops, \ + .rate = _rate, \ .delay = _delay, \ } @@ -64,20 +49,16 @@ void clk_cken_enable(struct clk *clk); void clk_cken_disable(struct clk *clk); #ifdef CONFIG_PXA3xx -#define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ - { \ - .name = _name, \ - .dev = _dev, \ +#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \ +struct clk clk_##_name = { \ .ops = &clk_pxa3xx_cken_ops, \ .rate = _rate, \ .cken = CKEN_##_cken, \ .delay = _delay, \ } -#define PXA3xx_CK(_name, _cken, _ops, _dev) \ - { \ - .name = _name, \ - .dev = _dev, \ +#define DEFINE_PXA3_CK(_name, _cken, _ops) \ +struct clk clk_##_name = { \ .ops = _ops, \ .cken = CKEN_##_cken, \ } @@ -87,7 +68,7 @@ extern void clk_pxa3xx_cken_enable(struct clk *); extern void clk_pxa3xx_cken_disable(struct clk *); #endif -void clks_register(struct clk *clks, size_t num); +void clks_register(struct clk_lookup *clks, size_t num); int clk_add_alias(char *alias, struct device *alias_dev, char *id, struct device *dev); diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index 0b3ce3b..d99fd9e 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c @@ -210,10 +210,8 @@ static struct pxafb_mode_info generic_stn_320x240_mode = { static struct pxafb_mach_info generic_stn_320x240 = { .modes = &generic_stn_320x240_mode, .num_modes = 1, - .lccr0 = 0, - .lccr3 = (LCCR3_PixClkDiv(0x03) | - LCCR3_Acb(0xff) | - LCCR3_PCP), + .lcd_conn = LCD_COLOR_STN_8BPP | LCD_PCLK_EDGE_FALL |\ + LCD_AC_BIAS_FREQ(0xff), .cmap_inverse = 0, .cmap_static = 0, }; @@ -236,10 +234,8 @@ static struct pxafb_mode_info generic_tft_640x480_mode = { static struct pxafb_mach_info generic_tft_640x480 = { .modes = &generic_tft_640x480_mode, .num_modes = 1, - .lccr0 = (LCCR0_PAS), - .lccr3 = (LCCR3_PixClkDiv(0x01) | - LCCR3_Acb(0xff) | - LCCR3_PCP), + .lcd_conn = LCD_COLOR_TFT_8BPP | LCD_PCLK_EDGE_FALL |\ + LCD_AC_BIAS_FREQ(0xff), .cmap_inverse = 0, .cmap_static = 0, }; @@ -263,9 +259,7 @@ static struct pxafb_mode_info generic_crt_640x480_mode = { static struct pxafb_mach_info generic_crt_640x480 = { .modes = &generic_crt_640x480_mode, .num_modes = 1, - .lccr0 = (LCCR0_PAS), - .lccr3 = (LCCR3_PixClkDiv(0x01) | - LCCR3_Acb(0xff)), + .lcd_conn = LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff), .cmap_inverse = 0, .cmap_static = 0, }; @@ -289,9 +283,7 @@ static struct pxafb_mode_info generic_crt_800x600_mode = { static struct pxafb_mach_info generic_crt_800x600 = { .modes = &generic_crt_800x600_mode, .num_modes = 1, - .lccr0 = (LCCR0_PAS), - .lccr3 = (LCCR3_PixClkDiv(0x02) | - LCCR3_Acb(0xff)), + .lcd_conn = LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff), .cmap_inverse = 0, .cmap_static = 0, }; @@ -314,10 +306,7 @@ static struct pxafb_mode_info generic_tft_320x240_mode = { static struct pxafb_mach_info generic_tft_320x240 = { .modes = &generic_tft_320x240_mode, .num_modes = 1, - .lccr0 = (LCCR0_PAS), - .lccr3 = (LCCR3_PixClkDiv(0x06) | - LCCR3_Acb(0xff) | - LCCR3_PCP), + .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_AC_BIAS_FREQ(0xff), .cmap_inverse = 0, .cmap_static = 0, }; @@ -341,9 +330,7 @@ static struct pxafb_mode_info generic_stn_640x480_mode = { static struct pxafb_mach_info generic_stn_640x480 = { .modes = &generic_stn_640x480_mode, .num_modes = 1, - .lccr0 = 0, - .lccr3 = (LCCR3_PixClkDiv(0x02) | - LCCR3_Acb(0xff)), + .lcd_conn = LCD_COLOR_STN_8BPP | LCD_AC_BIAS_FREQ(0xff), .cmap_inverse = 0, .cmap_static = 0, }; diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index deb46cd..ff0c577 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -31,7 +31,6 @@ #include <mach/mfp-pxa300.h> #include <mach/hardware.h> -#include <mach/gpio.h> #include <mach/pxafb.h> #include <mach/mmc.h> #include <mach/ohci.h> @@ -137,6 +136,10 @@ static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = { GPIO82_GPIO | MFP_PULL_HIGH, /* MMC CD */ GPIO85_GPIO, /* MMC WP */ GPIO99_GPIO, /* Ethernet IRQ */ + + /* Standard I2C */ + GPIO21_I2C_SCL, + GPIO22_I2C_SDA, }; #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 65558d6..c5e28a4 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -19,6 +19,7 @@ #include <linux/fs.h> #include <linux/interrupt.h> #include <linux/mmc/host.h> +#include <linux/mtd/physmap.h> #include <linux/pm.h> #include <linux/gpio.h> #include <linux/backlight.h> @@ -541,11 +542,42 @@ err_free_1: static inline void corgi_init_spi(void) {} #endif +static struct mtd_partition sharpsl_rom_parts[] = { + { + .name ="Boot PROM Filesystem", + .offset = 0x00120000, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data sharpsl_rom_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(sharpsl_rom_parts), + .parts = sharpsl_rom_parts, +}; + +static struct resource sharpsl_rom_resources[] = { + { + .start = 0x00000000, + .end = 0x007fffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sharpsl_rom_device = { + .name = "physmap-flash", + .id = -1, + .resource = sharpsl_rom_resources, + .num_resources = ARRAY_SIZE(sharpsl_rom_resources), + .dev.platform_data = &sharpsl_rom_data, +}; + static struct platform_device *devices[] __initdata = { &corgiscoop_device, &corgifb_device, &corgikbd_device, &corgiled_device, + &sharpsl_rom_device, }; static void corgi_poweroff(void) diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c index 1f272ea..771dd4e 100644 --- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c +++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c @@ -64,7 +64,7 @@ typedef struct { /* Define the refresh period in mSec for the SDRAM and the number of rows */ #define SDRAM_TREF 64 /* standard 64ms SDRAM */ -#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */ +static unsigned int sdram_rows; #define CCLKCFG_TURBO 0x1 #define CCLKCFG_FCS 0x2 @@ -73,6 +73,9 @@ typedef struct { #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2) #define MDREFR_DRI_MASK 0xFFF +#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3) +#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3) + /* * PXA255 definitions */ @@ -109,6 +112,10 @@ static struct cpufreq_frequency_table static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1]; +static unsigned int pxa255_turbo_table; +module_param(pxa255_turbo_table, uint, 0); +MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)"); + /* * PXA270 definitions * @@ -158,22 +165,16 @@ static struct cpufreq_frequency_table extern unsigned get_clk_frequency_khz(int info); -static void find_freq_tables(struct cpufreq_policy *policy, - struct cpufreq_frequency_table **freq_table, +static void find_freq_tables(struct cpufreq_frequency_table **freq_table, pxa_freqs_t **pxa_freqs) { if (cpu_is_pxa25x()) { - if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { + if (!pxa255_turbo_table) { *pxa_freqs = pxa255_run_freqs; *freq_table = pxa255_run_freq_table; - } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) { + } else { *pxa_freqs = pxa255_turbo_freqs; *freq_table = pxa255_turbo_freq_table; - } else { - printk("CPU PXA: Unknown policy found. " - "Using CPUFREQ_POLICY_PERFORMANCE\n"); - *pxa_freqs = pxa255_run_freqs; - *freq_table = pxa255_run_freq_table; } } if (cpu_is_pxa27x()) { @@ -194,14 +195,28 @@ static void pxa27x_guess_max_freq(void) } } +static void init_sdram_rows(void) +{ + uint32_t mdcnfg = MDCNFG; + unsigned int drac2 = 0, drac0 = 0; + + if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3)) + drac2 = MDCNFG_DRAC2(mdcnfg); + + if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1)) + drac0 = MDCNFG_DRAC0(mdcnfg); + + sdram_rows = 1 << (11 + max(drac0, drac2)); +} + static u32 mdrefr_dri(unsigned int freq) { u32 dri = 0; if (cpu_is_pxa25x()) - dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS * 32)); + dri = ((freq * SDRAM_TREF) / (sdram_rows * 32)); if (cpu_is_pxa27x()) - dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS - 31)) / 32; + dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32; return dri; } @@ -212,7 +227,7 @@ static int pxa_verify_policy(struct cpufreq_policy *policy) pxa_freqs_t *pxa_freqs; int ret; - find_freq_tables(policy, &pxa_freqs_table, &pxa_freqs); + find_freq_tables(&pxa_freqs_table, &pxa_freqs); ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table); if (freq_debug) @@ -240,7 +255,7 @@ static int pxa_set_target(struct cpufreq_policy *policy, unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg; /* Get the current policy */ - find_freq_tables(policy, &pxa_freqs_table, &pxa_freq_settings); + find_freq_tables(&pxa_freqs_table, &pxa_freq_settings); /* Lookup the next frequency */ if (cpufreq_frequency_table_target(policy, pxa_freqs_table, @@ -329,11 +344,15 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy) { int i; unsigned int freq; + struct cpufreq_frequency_table *pxa255_freq_table; + pxa_freqs_t *pxa255_freqs; /* try to guess pxa27x cpu */ if (cpu_is_pxa27x()) pxa27x_guess_max_freq(); + init_sdram_rows(); + /* set default policy and cpuinfo */ policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ policy->cur = get_clk_frequency_khz(0); /* current freq */ @@ -354,6 +373,8 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy) } pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; + pxa255_turbo_table = !!pxa255_turbo_table; + /* Generate the pxa27x cpufreq_frequency_table struct */ for (i = 0; i < NUM_PXA27x_FREQS; i++) { freq = pxa27x_freqs[i].khz; @@ -368,8 +389,12 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy) * Set the policy's minimum and maximum frequencies from the tables * just constructed. This sets cpuinfo.mxx_freq, min and max. */ - if (cpu_is_pxa25x()) - cpufreq_frequency_table_cpuinfo(policy, pxa255_run_freq_table); + if (cpu_is_pxa25x()) { + find_freq_tables(&pxa255_freq_table, &pxa255_freqs); + pr_info("PXA255 cpufreq using %s frequency table\n", + pxa255_turbo_table ? "turbo" : "run"); + cpufreq_frequency_table_cpuinfo(policy, pxa255_freq_table); + } else if (cpu_is_pxa27x()) cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table); diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 35736fc..e16f8e3 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -4,13 +4,12 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> -#include <mach/gpio.h> +#include <mach/pxa-regs.h> #include <mach/udc.h> #include <mach/pxafb.h> #include <mach/mmc.h> #include <mach/irda.h> #include <mach/i2c.h> -#include <mach/mfp-pxa27x.h> #include <mach/ohci.h> #include <mach/pxa27x_keypad.h> #include <mach/pxa2xx_spi.h> @@ -156,8 +155,8 @@ void __init set_pxa_fb_parent(struct device *parent_dev) static struct resource pxa_resource_ffuart[] = { { - .start = __PREG(FFUART), - .end = __PREG(FFUART) + 35, + .start = 0x40100000, + .end = 0x40100023, .flags = IORESOURCE_MEM, }, { .start = IRQ_FFUART, @@ -175,8 +174,8 @@ struct platform_device pxa_device_ffuart= { static struct resource pxa_resource_btuart[] = { { - .start = __PREG(BTUART), - .end = __PREG(BTUART) + 35, + .start = 0x40200000, + .end = 0x40200023, .flags = IORESOURCE_MEM, }, { .start = IRQ_BTUART, @@ -194,8 +193,8 @@ struct platform_device pxa_device_btuart = { static struct resource pxa_resource_stuart[] = { { - .start = __PREG(STUART), - .end = __PREG(STUART) + 35, + .start = 0x40700000, + .end = 0x40700023, .flags = IORESOURCE_MEM, }, { .start = IRQ_STUART, @@ -213,8 +212,8 @@ struct platform_device pxa_device_stuart = { static struct resource pxa_resource_hwuart[] = { { - .start = __PREG(HWUART), - .end = __PREG(HWUART) + 47, + .start = 0x41600000, + .end = 0x4160002F, .flags = IORESOURCE_MEM, }, { .start = IRQ_HWUART, @@ -249,18 +248,53 @@ struct platform_device pxa_device_i2c = { .num_resources = ARRAY_SIZE(pxai2c_resources), }; -static unsigned long pxa27x_i2c_mfp_cfg[] = { - GPIO117_I2C_SCL, - GPIO118_I2C_SDA, -}; - void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info) { - if (cpu_is_pxa27x()) - pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg)); pxa_register_device(&pxa_device_i2c, info); } +#ifdef CONFIG_PXA27x +static struct resource pxa27x_resources_i2c_power[] = { + { + .start = 0x40f00180, + .end = 0x40f001a3, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_PWRI2C, + .end = IRQ_PWRI2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa27x_device_i2c_power = { + .name = "pxa2xx-i2c", + .id = 1, + .resource = pxa27x_resources_i2c_power, + .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power), +}; +#endif + +#ifdef CONFIG_PXA3xx +static struct resource pxa3xx_resources_i2c_power[] = { + { + .start = 0x40f500c0, + .end = 0x40f500d3, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_PWRI2C, + .end = IRQ_PWRI2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa3xx_device_i2c_power = { + .name = "pxa2xx-i2c", + .id = 1, + .resource = pxa3xx_resources_i2c_power, + .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power), +}; +#endif + static struct resource pxai2s_resources[] = { { .start = 0x40400000, @@ -296,11 +330,36 @@ void __init pxa_set_ficp_info(struct pxaficp_platform_data *info) pxa_register_device(&pxa_device_ficp, info); } -struct platform_device pxa_device_rtc = { +static struct resource pxa_rtc_resources[] = { + [0] = { + .start = 0x40900000, + .end = 0x40900000 + 0x3b, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_RTC1Hz, + .end = IRQ_RTC1Hz, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_RTCAlrm, + .end = IRQ_RTCAlrm, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device sa1100_device_rtc = { .name = "sa1100-rtc", .id = -1, }; +struct platform_device pxa_device_rtc = { + .name = "pxa-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(pxa_rtc_resources), + .resource = pxa_rtc_resources, +}; + static struct resource pxa_ac97_resources[] = { [0] = { .start = 0x40500000, diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index bb04af4..ecc24a4 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h @@ -11,6 +11,7 @@ extern struct platform_device pxa_device_hwuart; extern struct platform_device pxa_device_i2c; extern struct platform_device pxa_device_i2s; extern struct platform_device pxa_device_ficp; +extern struct platform_device sa1100_device_rtc; extern struct platform_device pxa_device_rtc; extern struct platform_device pxa_device_ac97; diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/mach-pxa/dma.c index c0be17e..b1514fb 100644 --- a/arch/arm/mach-pxa/dma.c +++ b/arch/arm/mach-pxa/dma.c @@ -21,7 +21,7 @@ #include <asm/system.h> #include <asm/irq.h> #include <mach/hardware.h> -#include <asm/dma.h> +#include <mach/dma.h> #include <mach/pxa-regs.h> diff --git a/arch/arm/mach-pxa/e330.c b/arch/arm/mach-pxa/e330.c index d488ede..1bd7f74 100644 --- a/arch/arm/mach-pxa/e330.c +++ b/arch/arm/mach-pxa/e330.c @@ -1,5 +1,5 @@ /* - * Hardware definitions for the Toshiba eseries PDAs + * Hardware definitions for the Toshiba e330 PDAs * * Copyright (c) 2003 Ian Molton <spyro@f2s.com> * @@ -12,6 +12,9 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <linux/mfd/tc6387xb.h> #include <asm/setup.h> #include <asm/mach/arch.h> @@ -19,13 +22,44 @@ #include <mach/mfp-pxa25x.h> #include <mach/hardware.h> +#include <mach/pxa-regs.h> +#include <mach/eseries-gpio.h> #include <mach/udc.h> #include "generic.h" #include "eseries.h" +#include "clock.h" + +/* -------------------- e330 tc6387xb parameters -------------------- */ + +static struct tc6387xb_platform_data e330_tc6387xb_info = { + .enable = &eseries_tmio_enable, + .disable = &eseries_tmio_disable, + .suspend = &eseries_tmio_suspend, + .resume = &eseries_tmio_resume, +}; + +static struct platform_device e330_tc6387xb_device = { + .name = "tc6387xb", + .id = -1, + .dev = { + .platform_data = &e330_tc6387xb_info, + }, + .num_resources = 2, + .resource = eseries_tmio_resources, +}; + +/* --------------------------------------------------------------- */ + +static struct platform_device *devices[] __initdata = { + &e330_tc6387xb_device, +}; static void __init e330_init(void) { + eseries_register_clks(); + eseries_get_tmio_gpios(); + platform_add_devices(devices, ARRAY_SIZE(devices)); pxa_set_udc_info(&e7xx_udc_mach_info); } diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c index 8ecbc54..2511293 100644 --- a/arch/arm/mach-pxa/e350.c +++ b/arch/arm/mach-pxa/e350.c @@ -1,5 +1,5 @@ /* - * Hardware definitions for the Toshiba eseries PDAs + * Hardware definitions for the Toshiba e350 PDAs * * Copyright (c) 2003 Ian Molton <spyro@f2s.com> * @@ -12,20 +12,54 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <linux/mfd/t7l66xb.h> #include <asm/setup.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <mach/mfp-pxa25x.h> +#include <mach/pxa-regs.h> #include <mach/hardware.h> +#include <mach/eseries-gpio.h> #include <mach/udc.h> #include "generic.h" #include "eseries.h" +#include "clock.h" + +/* -------------------- e350 t7l66xb parameters -------------------- */ + +static struct t7l66xb_platform_data e350_t7l66xb_info = { + .irq_base = IRQ_BOARD_START, + .enable = &eseries_tmio_enable, + .suspend = &eseries_tmio_suspend, + .resume = &eseries_tmio_resume, +}; + +static struct platform_device e350_t7l66xb_device = { + .name = "t7l66xb", + .id = -1, + .dev = { + .platform_data = &e350_t7l66xb_info, + }, + .num_resources = 2, + .resource = eseries_tmio_resources, +}; + +/* ---------------------------------------------------------- */ + +static struct platform_device *devices[] __initdata = { + &e350_t7l66xb_device, +}; static void __init e350_init(void) { + eseries_register_clks(); + eseries_get_tmio_gpios(); + platform_add_devices(devices, ARRAY_SIZE(devices)); pxa_set_udc_info(&e7xx_udc_mach_info); } diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c index 544bbaa..bed0336 100644 --- a/arch/arm/mach-pxa/e400.c +++ b/arch/arm/mach-pxa/e400.c @@ -12,20 +12,26 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <linux/mfd/t7l66xb.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> #include <asm/setup.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> -#include <mach/pxa-regs.h> #include <mach/mfp-pxa25x.h> +#include <mach/pxa-regs.h> #include <mach/hardware.h> - +#include <mach/eseries-gpio.h> #include <mach/pxafb.h> #include <mach/udc.h> #include "generic.h" #include "eseries.h" +#include "clock.h" /* ------------------------ E400 LCD definitions ------------------------ */ @@ -46,7 +52,7 @@ static struct pxafb_mode_info e400_pxafb_mode_info = { static struct pxafb_mach_info e400_pxafb_mach_info = { .modes = &e400_pxafb_mode_info, .num_modes = 1, - .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, + .lcd_conn = LCD_COLOR_TFT_16BPP, .lccr3 = 0, .pxafb_backlight_power = NULL, }; @@ -65,7 +71,10 @@ static unsigned long e400_pin_config[] __initdata = { GPIO42_BTUART_RXD, GPIO43_BTUART_TXD, GPIO44_BTUART_CTS, - GPIO45_GPIO, /* Used by TMIO for #SUSPEND */ + + /* TMIO controller */ + GPIO19_GPIO, /* t7l66xb #PCLR */ + GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */ /* wakeup */ GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, @@ -73,10 +82,60 @@ static unsigned long e400_pin_config[] __initdata = { /* ---------------------------------------------------------------------- */ +static struct mtd_partition partition_a = { + .name = "Internal NAND flash", + .offset = 0, + .size = MTDPART_SIZ_FULL, +}; + +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr e400_t7l66xb_nand_bbt = { + .options = 0, + .offs = 4, + .len = 2, + .pattern = scan_ff_pattern +}; + +static struct tmio_nand_data e400_t7l66xb_nand_config = { + .num_partitions = 1, + .partition = &partition_a, + .badblock_pattern = &e400_t7l66xb_nand_bbt, +}; + +static struct t7l66xb_platform_data e400_t7l66xb_info = { + .irq_base = IRQ_BOARD_START, + .enable = &eseries_tmio_enable, + .suspend = &eseries_tmio_suspend, + .resume = &eseries_tmio_resume, + + .nand_data = &e400_t7l66xb_nand_config, +}; + +static struct platform_device e400_t7l66xb_device = { + .name = "t7l66xb", + .id = -1, + .dev = { + .platform_data = &e400_t7l66xb_info, + }, + .num_resources = 2, + .resource = eseries_tmio_resources, +}; + +/* ---------------------------------------------------------- */ + +static struct platform_device *devices[] __initdata = { + &e400_t7l66xb_device, +}; + static void __init e400_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config)); + /* Fixme - e400 may have a switched clock */ + eseries_register_clks(); + eseries_get_tmio_gpios(); set_pxa_fb_info(&e400_pxafb_mach_info); + platform_add_devices(devices, ARRAY_SIZE(devices)); pxa_set_udc_info(&e7xx_udc_mach_info); } diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c index c57a15b..b00d670 100644 --- a/arch/arm/mach-pxa/e740.c +++ b/arch/arm/mach-pxa/e740.c @@ -15,6 +15,8 @@ #include <linux/device.h> #include <linux/platform_device.h> #include <linux/fb.h> +#include <linux/clk.h> +#include <linux/mfd/t7l66xb.h> #include <video/w100fb.h> @@ -23,12 +25,16 @@ #include <asm/mach-types.h> #include <mach/mfp-pxa25x.h> +#include <mach/pxa-regs.h> #include <mach/hardware.h> +#include <mach/eseries-gpio.h> #include <mach/udc.h> +#include <mach/irda.h> #include "generic.h" #include "eseries.h" - +#include "clock.h" +#include "devices.h" /* ------------------------ e740 video support --------------------------- */ @@ -116,7 +122,17 @@ static unsigned long e740_pin_config[] __initdata = { GPIO42_BTUART_RXD, GPIO43_BTUART_TXD, GPIO44_BTUART_CTS, - GPIO45_GPIO, /* Used by TMIO for #SUSPEND */ + + /* TMIO controller */ + GPIO19_GPIO, /* t7l66xb #PCLR */ + GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */ + + /* UDC */ + GPIO13_GPIO, + GPIO3_GPIO, + + /* IrDA */ + GPIO38_GPIO | MFP_LPM_DRIVE_HIGH, /* PC Card */ GPIO8_GPIO, /* CD0 */ @@ -142,17 +158,43 @@ static unsigned long e740_pin_config[] __initdata = { GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, }; +/* -------------------- e740 t7l66xb parameters -------------------- */ + +static struct t7l66xb_platform_data e740_t7l66xb_info = { + .irq_base = IRQ_BOARD_START, + .enable = &eseries_tmio_enable, + .suspend = &eseries_tmio_suspend, + .resume = &eseries_tmio_resume, +}; + +static struct platform_device e740_t7l66xb_device = { + .name = "t7l66xb", + .id = -1, + .dev = { + .platform_data = &e740_t7l66xb_info, + }, + .num_resources = 2, + .resource = eseries_tmio_resources, +}; + /* ----------------------------------------------------------------------- */ static struct platform_device *devices[] __initdata = { &e740_fb_device, + &e740_t7l66xb_device, }; static void __init e740_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config)); + eseries_register_clks(); + clk_add_alias("CLK_CK48M", &e740_t7l66xb_device.dev, + "UDCCLK", &pxa25x_device_udc.dev), + eseries_get_tmio_gpios(); platform_add_devices(devices, ARRAY_SIZE(devices)); pxa_set_udc_info(&e7xx_udc_mach_info); + e7xx_irda_init(); + pxa_set_ficp_info(&e7xx_ficp_platform_data); } MACHINE_START(E740, "Toshiba e740") diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c index 640e738..84d7c1a 100644 --- a/arch/arm/mach-pxa/e750.c +++ b/arch/arm/mach-pxa/e750.c @@ -15,6 +15,7 @@ #include <linux/device.h> #include <linux/platform_device.h> #include <linux/fb.h> +#include <linux/mfd/tc6393xb.h> #include <video/w100fb.h> @@ -23,11 +24,15 @@ #include <asm/mach-types.h> #include <mach/mfp-pxa25x.h> +#include <mach/pxa-regs.h> #include <mach/hardware.h> +#include <mach/eseries-gpio.h> #include <mach/udc.h> +#include <mach/irda.h> #include "generic.h" #include "eseries.h" +#include "clock.h" /* ---------------------- E750 LCD definitions -------------------- */ @@ -100,16 +105,45 @@ static struct platform_device e750_fb_device = { .resource = e750_fb_resources, }; -/* ----------------------------------------------------------------------- */ +/* ----------------- e750 tc6393xb parameters ------------------ */ + +static struct tc6393xb_platform_data e750_tc6393xb_info = { + .irq_base = IRQ_BOARD_START, + .scr_pll2cr = 0x0cc1, + .scr_gper = 0, + .gpio_base = -1, + .suspend = &eseries_tmio_suspend, + .resume = &eseries_tmio_resume, + .enable = &eseries_tmio_enable, + .disable = &eseries_tmio_disable, +}; + +static struct platform_device e750_tc6393xb_device = { + .name = "tc6393xb", + .id = -1, + .dev = { + .platform_data = &e750_tc6393xb_info, + }, + .num_resources = 2, + .resource = eseries_tmio_resources, +}; + +/* ------------------------------------------------------------- */ static struct platform_device *devices[] __initdata = { &e750_fb_device, + &e750_tc6393xb_device, }; static void __init e750_init(void) { + clk_add_alias("CLK_CK3P6MI", &e750_tc6393xb_device.dev, + "GPIO11_CLK", NULL), + eseries_get_tmio_gpios(); platform_add_devices(devices, ARRAY_SIZE(devices)); pxa_set_udc_info(&e7xx_udc_mach_info); + e7xx_irda_init(); + pxa_set_ficp_info(&e7xx_ficp_platform_data); } MACHINE_START(E750, "Toshiba e750") diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c index a293e09..9a86a42 100644 --- a/arch/arm/mach-pxa/e800.c +++ b/arch/arm/mach-pxa/e800.c @@ -15,6 +15,7 @@ #include <linux/device.h> #include <linux/platform_device.h> #include <linux/fb.h> +#include <linux/mfd/tc6393xb.h> #include <video/w100fb.h> @@ -23,12 +24,14 @@ #include <asm/mach-types.h> #include <mach/mfp-pxa25x.h> +#include <mach/pxa-regs.h> #include <mach/hardware.h> #include <mach/eseries-gpio.h> #include <mach/udc.h> #include "generic.h" #include "eseries.h" +#include "clock.h" /* ------------------------ e800 LCD definitions ------------------------- */ @@ -160,14 +163,41 @@ static struct pxa2xx_udc_mach_info e800_udc_mach_info = { .gpio_pullup_inverted = 1 }; +/* ----------------- e800 tc6393xb parameters ------------------ */ + +static struct tc6393xb_platform_data e800_tc6393xb_info = { + .irq_base = IRQ_BOARD_START, + .scr_pll2cr = 0x0cc1, + .scr_gper = 0, + .gpio_base = -1, + .suspend = &eseries_tmio_suspend, + .resume = &eseries_tmio_resume, + .enable = &eseries_tmio_enable, + .disable = &eseries_tmio_disable, +}; + +static struct platform_device e800_tc6393xb_device = { + .name = "tc6393xb", + .id = -1, + .dev = { + .platform_data = &e800_tc6393xb_info, + }, + .num_resources = 2, + .resource = eseries_tmio_resources, +}; + /* ----------------------------------------------------------------------- */ static struct platform_device *devices[] __initdata = { &e800_fb_device, + &e800_tc6393xb_device, }; static void __init e800_init(void) { + clk_add_alias("CLK_CK3P6MI", &e800_tc6393xb_device.dev, + "GPIO11_CLK", NULL), + eseries_get_tmio_gpios(); platform_add_devices(devices, ARRAY_SIZE(devices)); pxa_set_udc_info(&e800_udc_mach_info); } diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index d28849b..dfce7d5 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -12,6 +12,9 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/platform_device.h> #include <asm/setup.h> #include <asm/mach/arch.h> @@ -21,8 +24,10 @@ #include <mach/hardware.h> #include <mach/eseries-gpio.h> #include <mach/udc.h> +#include <mach/irda.h> #include "generic.h" +#include "clock.h" /* Only e800 has 128MB RAM */ void __init eseries_fixup(struct machine_desc *desc, @@ -43,3 +48,122 @@ struct pxa2xx_udc_mach_info e7xx_udc_mach_info = { .gpio_pullup_inverted = 1 }; +static void e7xx_irda_transceiver_mode(struct device *dev, int mode) +{ + if (mode & IR_OFF) { + gpio_set_value(GPIO_E7XX_IR_OFF, 1); + pxa2xx_transceiver_mode(dev, mode); + } else { + pxa2xx_transceiver_mode(dev, mode); + gpio_set_value(GPIO_E7XX_IR_OFF, 0); + } +} + +int e7xx_irda_init(void) +{ + int ret; + + ret = gpio_request(GPIO_E7XX_IR_OFF, "IrDA power"); + if (ret) + goto out; + + ret = gpio_direction_output(GPIO_E7XX_IR_OFF, 0); + if (ret) + goto out; + + e7xx_irda_transceiver_mode(NULL, IR_SIRMODE | IR_OFF); +out: + return ret; +} + +static void e7xx_irda_shutdown(struct device *dev) +{ + e7xx_irda_transceiver_mode(dev, IR_SIRMODE | IR_OFF); + gpio_free(GPIO_E7XX_IR_OFF); +} + +struct pxaficp_platform_data e7xx_ficp_platform_data = { + .transceiver_cap = IR_SIRMODE | IR_OFF, + .transceiver_mode = e7xx_irda_transceiver_mode, + .shutdown = e7xx_irda_shutdown, +}; + +int eseries_tmio_enable(struct platform_device *dev) +{ + /* Reset - bring SUSPEND high before PCLR */ + gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0); + gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 0); + msleep(1); + gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 1); + msleep(1); + gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 1); + msleep(1); + return 0; +} + +int eseries_tmio_disable(struct platform_device *dev) +{ + gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0); + gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 0); + return 0; +} + +int eseries_tmio_suspend(struct platform_device *dev) +{ + gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0); + return 0; +} + +int eseries_tmio_resume(struct platform_device *dev) +{ + gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 1); + msleep(1); + return 0; +} + +void eseries_get_tmio_gpios(void) +{ + gpio_request(GPIO_ESERIES_TMIO_SUSPEND, NULL); + gpio_request(GPIO_ESERIES_TMIO_PCLR, NULL); + gpio_direction_output(GPIO_ESERIES_TMIO_SUSPEND, 0); + gpio_direction_output(GPIO_ESERIES_TMIO_PCLR, 0); +} + +/* TMIO controller uses the same resources on all e-series machines. */ +struct resource eseries_tmio_resources[] = { + [0] = { + .start = PXA_CS4_PHYS, + .end = PXA_CS4_PHYS + 0x1fffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ), + .end = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ), + .flags = IORESOURCE_IRQ, + }, +}; + +/* Some e-series hardware cannot control the 32K clock */ +static void clk_32k_dummy(struct clk *clk) +{ +} + +static const struct clkops clk_32k_dummy_ops = { + .enable = clk_32k_dummy, + .disable = clk_32k_dummy, +}; + +static struct clk tmio_dummy_clk = { + .ops = &clk_32k_dummy_ops, + .rate = 32768, +}; + +static struct clk_lookup eseries_clkregs[] = { + INIT_CLKREG(&tmio_dummy_clk, NULL, "CLK_CK32K"), +}; + +void eseries_register_clks(void) +{ + clks_register(eseries_clkregs, ARRAY_SIZE(eseries_clkregs)); +} + diff --git a/arch/arm/mach-pxa/eseries.h b/arch/arm/mach-pxa/eseries.h index a83f88d..5930f5e 100644 --- a/arch/arm/mach-pxa/eseries.h +++ b/arch/arm/mach-pxa/eseries.h @@ -2,3 +2,15 @@ void __init eseries_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi); extern struct pxa2xx_udc_mach_info e7xx_udc_mach_info; +extern struct pxaficp_platform_data e7xx_ficp_platform_data; +extern int e7xx_irda_init(void); + +extern int eseries_tmio_enable(struct platform_device *dev); +extern int eseries_tmio_disable(struct platform_device *dev); +extern int eseries_tmio_suspend(struct platform_device *dev); +extern int eseries_tmio_resume(struct platform_device *dev); +extern void eseries_get_tmio_gpios(void); +extern struct resource eseries_tmio_resources[]; +extern struct platform_device e300_tc6387xb_device; +extern void eseries_register_clks(void); + diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index cc3d850..df5f822 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -16,11 +16,14 @@ #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/pwm_backlight.h> +#include <linux/input.h> #include <asm/setup.h> #include <mach/pxafb.h> #include <mach/ohci.h> #include <mach/i2c.h> +#include <mach/hardware.h> +#include <mach/pxa27x_keypad.h> #include <mach/mfp-pxa27x.h> #include <mach/pxa-regs.h> @@ -101,120 +104,732 @@ static unsigned long ezx_pin_config[] __initdata = { GPIO44_BTUART_CTS, GPIO45_BTUART_RTS, - /* STUART */ - GPIO46_STUART_RXD, - GPIO47_STUART_TXD, + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, - /* For A780 support (connected with Neptune GSM chip) */ - GPIO30_USB_P3_2, /* ICL_TXENB */ - GPIO31_USB_P3_6, /* ICL_VPOUT */ - GPIO90_USB_P3_5, /* ICL_VPIN */ - GPIO91_USB_P3_1, /* ICL_XRXD */ - GPIO56_USB_P3_4, /* ICL_VMOUT */ - GPIO113_USB_P3_3, /* /ICL_VMIN */ + /* PCAP SSP */ + GPIO29_SSP1_SCLK, + GPIO25_SSP1_TXD, + GPIO26_SSP1_RXD, + GPIO24_GPIO, /* pcap chip select */ + GPIO1_GPIO, /* pcap interrupt */ + GPIO4_GPIO, /* WDI_AP */ + GPIO55_GPIO, /* SYS_RESTART */ + + /* MMC */ + GPIO32_MMC_CLK, + GPIO92_MMC_DAT_0, + GPIO109_MMC_DAT_1, + GPIO110_MMC_DAT_2, + GPIO111_MMC_DAT_3, + GPIO112_MMC_CMD, + GPIO11_GPIO, /* mmc detect */ + + /* usb to external transceiver */ + GPIO34_USB_P2_2, + GPIO35_USB_P2_1, + GPIO36_USB_P2_4, + GPIO39_USB_P2_6, + GPIO40_USB_P2_5, + GPIO53_USB_P2_3, + + /* usb to Neptune GSM chip */ + GPIO30_USB_P3_2, + GPIO31_USB_P3_6, + GPIO90_USB_P3_5, + GPIO91_USB_P3_1, + GPIO56_USB_P3_4, + GPIO113_USB_P3_3, +}; + +#if defined(CONFIG_MACH_EZX_A780) || defined(CONFIG_MACH_EZX_E680) +static unsigned long gen1_pin_config[] __initdata = { + /* flip / lockswitch */ + GPIO12_GPIO, + + /* bluetooth (bcm2035) */ + GPIO14_GPIO | WAKEUP_ON_LEVEL_HIGH, /* HOSTWAKE */ + GPIO48_GPIO, /* RESET */ + GPIO28_GPIO, /* WAKEUP */ + + /* Neptune handshake */ + GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* BP_RDY */ + GPIO57_GPIO, /* AP_RDY */ + GPIO13_GPIO | WAKEUP_ON_LEVEL_HIGH, /* WDI */ + GPIO3_GPIO | WAKEUP_ON_LEVEL_HIGH, /* WDI2 */ + GPIO82_GPIO, /* RESET */ + GPIO99_GPIO, /* TC_MM_EN */ + + /* sound */ + GPIO52_SSP3_SCLK, + GPIO83_SSP3_SFRM, + GPIO81_SSP3_TXD, + GPIO89_SSP3_RXD, + + /* ssp2 pins to in */ + GPIO22_GPIO, /* SSP2_SCLK */ + GPIO37_GPIO, /* SSP2_SFRM */ + GPIO38_GPIO, /* SSP2_TXD */ + GPIO88_GPIO, /* SSP2_RXD */ + + /* camera */ + GPIO23_CIF_MCLK, + GPIO54_CIF_PCLK, + GPIO85_CIF_LV, + GPIO84_CIF_FV, + GPIO27_CIF_DD_0, + GPIO114_CIF_DD_1, + GPIO51_CIF_DD_2, + GPIO115_CIF_DD_3, + GPIO95_CIF_DD_4, + GPIO94_CIF_DD_5, + GPIO17_CIF_DD_6, + GPIO108_CIF_DD_7, + GPIO50_GPIO, /* CAM_EN */ + GPIO19_GPIO, /* CAM_RST */ + + /* EMU */ + GPIO120_GPIO, /* EMU_MUX1 */ + GPIO119_GPIO, /* EMU_MUX2 */ + GPIO86_GPIO, /* SNP_INT_CTL */ + GPIO87_GPIO, /* SNP_INT_IN */ +}; +#endif + +#if defined(CONFIG_MACH_EZX_A1200) || defined(CONFIG_MACH_EZX_A910) || \ + defined(CONFIG_MACH_EZX_E2) || defined(CONFIG_MACH_EZX_E6) +static unsigned long gen2_pin_config[] __initdata = { + /* flip / lockswitch */ + GPIO15_GPIO, + + /* EOC */ + GPIO10_GPIO, + + /* bluetooth (bcm2045) */ + GPIO13_GPIO | WAKEUP_ON_LEVEL_HIGH, /* HOSTWAKE */ + GPIO37_GPIO, /* RESET */ + GPIO57_GPIO, /* WAKEUP */ + + /* Neptune handshake */ + GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* BP_RDY */ + GPIO96_GPIO, /* AP_RDY */ + GPIO3_GPIO | WAKEUP_ON_LEVEL_HIGH, /* WDI */ + GPIO116_GPIO, /* RESET */ + GPIO41_GPIO, /* BP_FLASH */ + + /* sound */ + GPIO52_SSP3_SCLK, + GPIO83_SSP3_SFRM, + GPIO81_SSP3_TXD, + GPIO82_SSP3_RXD, + + /* ssp2 pins to in */ + GPIO22_GPIO, /* SSP2_SCLK */ + GPIO14_GPIO, /* SSP2_SFRM */ + GPIO38_GPIO, /* SSP2_TXD */ + GPIO88_GPIO, /* SSP2_RXD */ + + /* camera */ + GPIO23_CIF_MCLK, + GPIO54_CIF_PCLK, + GPIO85_CIF_LV, + GPIO84_CIF_FV, + GPIO27_CIF_DD_0, + GPIO114_CIF_DD_1, + GPIO51_CIF_DD_2, + GPIO115_CIF_DD_3, + GPIO95_CIF_DD_4, + GPIO48_CIF_DD_5, + GPIO93_CIF_DD_6, + GPIO12_CIF_DD_7, + GPIO50_GPIO, /* CAM_EN */ + GPIO28_GPIO, /* CAM_RST */ + GPIO17_GPIO, /* CAM_FLASH */ +}; +#endif + +#ifdef CONFIG_MACH_EZX_A780 +static unsigned long a780_pin_config[] __initdata = { + /* keypad */ + GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, + GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, + GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, + GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, + GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, + GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, + GPIO103_KP_MKOUT_0, + GPIO104_KP_MKOUT_1, + GPIO105_KP_MKOUT_2, + GPIO106_KP_MKOUT_3, + GPIO107_KP_MKOUT_4, + + /* attenuate sound */ + GPIO96_GPIO, +}; +#endif + +#ifdef CONFIG_MACH_EZX_E680 +static unsigned long e680_pin_config[] __initdata = { + /* keypad */ + GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, + GPIO96_KP_DKIN_3 | WAKEUP_ON_LEVEL_HIGH, + GPIO97_KP_DKIN_4 | WAKEUP_ON_LEVEL_HIGH, + GPIO98_KP_DKIN_5 | WAKEUP_ON_LEVEL_HIGH, + GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, + GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, + GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, + GPIO103_KP_MKOUT_0, + GPIO104_KP_MKOUT_1, + GPIO105_KP_MKOUT_2, + GPIO106_KP_MKOUT_3, + + /* MIDI */ + GPIO79_GPIO, /* VA_SEL_BUL */ + GPIO80_GPIO, /* FLT_SEL_BUL */ + GPIO78_GPIO, /* MIDI_RESET */ + GPIO33_GPIO, /* MIDI_CS */ + GPIO15_GPIO, /* MIDI_IRQ */ + GPIO49_GPIO, /* MIDI_NPWE */ + GPIO18_GPIO, /* MIDI_RDY */ + + /* leds */ + GPIO46_GPIO, + GPIO47_GPIO, +}; +#endif + +#ifdef CONFIG_MACH_EZX_A1200 +static unsigned long a1200_pin_config[] __initdata = { + /* keypad */ + GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, + GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, + GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, + GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, + GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, + GPIO103_KP_MKOUT_0, + GPIO104_KP_MKOUT_1, + GPIO105_KP_MKOUT_2, + GPIO106_KP_MKOUT_3, + GPIO107_KP_MKOUT_4, + GPIO108_KP_MKOUT_5, +}; +#endif + +#ifdef CONFIG_MACH_EZX_A910 +static unsigned long a910_pin_config[] __initdata = { + /* keypad */ + GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, + GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, + GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, + GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, + GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, + GPIO103_KP_MKOUT_0, + GPIO104_KP_MKOUT_1, + GPIO105_KP_MKOUT_2, + GPIO106_KP_MKOUT_3, + GPIO107_KP_MKOUT_4, + GPIO108_KP_MKOUT_5, + + /* WLAN */ + GPIO89_GPIO, /* RESET */ + GPIO33_GPIO, /* WAKEUP */ + GPIO94_GPIO | WAKEUP_ON_LEVEL_HIGH, /* HOSTWAKE */ + + /* MMC CS */ + GPIO20_GPIO, +}; +#endif + +#ifdef CONFIG_MACH_EZX_E2 +static unsigned long e2_pin_config[] __initdata = { + /* keypad */ + GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, + GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, + GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, + GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, + GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, + GPIO103_KP_MKOUT_0, + GPIO104_KP_MKOUT_1, + GPIO105_KP_MKOUT_2, + GPIO106_KP_MKOUT_3, + GPIO107_KP_MKOUT_4, + GPIO108_KP_MKOUT_5, }; +#endif + +#ifdef CONFIG_MACH_EZX_E6 +static unsigned long e6_pin_config[] __initdata = { + /* keypad */ + GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, + GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, + GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, + GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, + GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, + GPIO103_KP_MKOUT_0, + GPIO104_KP_MKOUT_1, + GPIO105_KP_MKOUT_2, + GPIO106_KP_MKOUT_3, + GPIO107_KP_MKOUT_4, + GPIO108_KP_MKOUT_5, +}; +#endif + +/* KEYPAD */ +#ifdef CONFIG_MACH_EZX_A780 +static unsigned int a780_key_map[] = { + KEY(0, 0, KEY_SEND), + KEY(0, 1, KEY_BACK), + KEY(0, 2, KEY_END), + KEY(0, 3, KEY_PAGEUP), + KEY(0, 4, KEY_UP), + + KEY(1, 0, KEY_NUMERIC_1), + KEY(1, 1, KEY_NUMERIC_2), + KEY(1, 2, KEY_NUMERIC_3), + KEY(1, 3, KEY_SELECT), + KEY(1, 4, KEY_KPENTER), + + KEY(2, 0, KEY_NUMERIC_4), + KEY(2, 1, KEY_NUMERIC_5), + KEY(2, 2, KEY_NUMERIC_6), + KEY(2, 3, KEY_RECORD), + KEY(2, 4, KEY_LEFT), + + KEY(3, 0, KEY_NUMERIC_7), + KEY(3, 1, KEY_NUMERIC_8), + KEY(3, 2, KEY_NUMERIC_9), + KEY(3, 3, KEY_HOME), + KEY(3, 4, KEY_RIGHT), + + KEY(4, 0, KEY_NUMERIC_STAR), + KEY(4, 1, KEY_NUMERIC_0), + KEY(4, 2, KEY_NUMERIC_POUND), + KEY(4, 3, KEY_PAGEDOWN), + KEY(4, 4, KEY_DOWN), +}; + +static struct pxa27x_keypad_platform_data a780_keypad_platform_data = { + .matrix_key_rows = 5, + .matrix_key_cols = 5, + .matrix_key_map = a780_key_map, + .matrix_key_map_size = ARRAY_SIZE(a780_key_map), + + .direct_key_map = { KEY_CAMERA }, + .direct_key_num = 1, + + .debounce_interval = 30, +}; +#endif /* CONFIG_MACH_EZX_A780 */ + +#ifdef CONFIG_MACH_EZX_E680 +static unsigned int e680_key_map[] = { + KEY(0, 0, KEY_UP), + KEY(0, 1, KEY_RIGHT), + KEY(0, 2, KEY_RESERVED), + KEY(0, 3, KEY_SEND), + + KEY(1, 0, KEY_DOWN), + KEY(1, 1, KEY_LEFT), + KEY(1, 2, KEY_PAGEUP), + KEY(1, 3, KEY_PAGEDOWN), + + KEY(2, 0, KEY_RESERVED), + KEY(2, 1, KEY_RESERVED), + KEY(2, 2, KEY_RESERVED), + KEY(2, 3, KEY_KPENTER), +}; + +static struct pxa27x_keypad_platform_data e680_keypad_platform_data = { + .matrix_key_rows = 3, + .matrix_key_cols = 4, + .matrix_key_map = e680_key_map, + .matrix_key_map_size = ARRAY_SIZE(e680_key_map), + + .direct_key_map = { + KEY_CAMERA, + KEY_RESERVED, + KEY_RESERVED, + KEY_F1, + KEY_CANCEL, + KEY_F2, + }, + .direct_key_num = 6, + + .debounce_interval = 30, +}; +#endif /* CONFIG_MACH_EZX_E680 */ + +#ifdef CONFIG_MACH_EZX_A1200 +static unsigned int a1200_key_map[] = { + KEY(0, 0, KEY_RESERVED), + KEY(0, 1, KEY_RIGHT), + KEY(0, 2, KEY_PAGEDOWN), + KEY(0, 3, KEY_RESERVED), + KEY(0, 4, KEY_RESERVED), + KEY(0, 5, KEY_RESERVED), + + KEY(1, 0, KEY_RESERVED), + KEY(1, 1, KEY_DOWN), + KEY(1, 2, KEY_CAMERA), + KEY(1, 3, KEY_RESERVED), + KEY(1, 4, KEY_RESERVED), + KEY(1, 5, KEY_RESERVED), + + KEY(2, 0, KEY_RESERVED), + KEY(2, 1, KEY_KPENTER), + KEY(2, 2, KEY_RECORD), + KEY(2, 3, KEY_RESERVED), + KEY(2, 4, KEY_RESERVED), + KEY(2, 5, KEY_SELECT), + + KEY(3, 0, KEY_RESERVED), + KEY(3, 1, KEY_UP), + KEY(3, 2, KEY_SEND), + KEY(3, 3, KEY_RESERVED), + KEY(3, 4, KEY_RESERVED), + KEY(3, 5, KEY_RESERVED), + + KEY(4, 0, KEY_RESERVED), + KEY(4, 1, KEY_LEFT), + KEY(4, 2, KEY_PAGEUP), + KEY(4, 3, KEY_RESERVED), + KEY(4, 4, KEY_RESERVED), + KEY(4, 5, KEY_RESERVED), +}; + +static struct pxa27x_keypad_platform_data a1200_keypad_platform_data = { + .matrix_key_rows = 5, + .matrix_key_cols = 6, + .matrix_key_map = a1200_key_map, + .matrix_key_map_size = ARRAY_SIZE(a1200_key_map), + + .debounce_interval = 30, +}; +#endif /* CONFIG_MACH_EZX_A1200 */ + +#ifdef CONFIG_MACH_EZX_E6 +static unsigned int e6_key_map[] = { + KEY(0, 0, KEY_RESERVED), + KEY(0, 1, KEY_RIGHT), + KEY(0, 2, KEY_PAGEDOWN), + KEY(0, 3, KEY_RESERVED), + KEY(0, 4, KEY_RESERVED), + KEY(0, 5, KEY_NEXTSONG), + + KEY(1, 0, KEY_RESERVED), + KEY(1, 1, KEY_DOWN), + KEY(1, 2, KEY_PROG1), + KEY(1, 3, KEY_RESERVED), + KEY(1, 4, KEY_RESERVED), + KEY(1, 5, KEY_RESERVED), + + KEY(2, 0, KEY_RESERVED), + KEY(2, 1, KEY_ENTER), + KEY(2, 2, KEY_CAMERA), + KEY(2, 3, KEY_RESERVED), + KEY(2, 4, KEY_RESERVED), + KEY(2, 5, KEY_WWW), + + KEY(3, 0, KEY_RESERVED), + KEY(3, 1, KEY_UP), + KEY(3, 2, KEY_SEND), + KEY(3, 3, KEY_RESERVED), + KEY(3, 4, KEY_RESERVED), + KEY(3, 5, KEY_PLAYPAUSE), + + KEY(4, 0, KEY_RESERVED), + KEY(4, 1, KEY_LEFT), + KEY(4, 2, KEY_PAGEUP), + KEY(4, 3, KEY_RESERVED), + KEY(4, 4, KEY_RESERVED), + KEY(4, 5, KEY_PREVIOUSSONG), +}; + +static struct pxa27x_keypad_platform_data e6_keypad_platform_data = { + .matrix_key_rows = 5, + .matrix_key_cols = 6, + .matrix_key_map = e6_key_map, + .matrix_key_map_size = ARRAY_SIZE(e6_key_map), -static void __init ezx_init(void) + .debounce_interval = 30, +}; +#endif /* CONFIG_MACH_EZX_E6 */ + +#ifdef CONFIG_MACH_EZX_A910 +static unsigned int a910_key_map[] = { + KEY(0, 0, KEY_NUMERIC_6), + KEY(0, 1, KEY_RIGHT), + KEY(0, 2, KEY_PAGEDOWN), + KEY(0, 3, KEY_KPENTER), + KEY(0, 4, KEY_NUMERIC_5), + KEY(0, 5, KEY_CAMERA), + + KEY(1, 0, KEY_NUMERIC_8), + KEY(1, 1, KEY_DOWN), + KEY(1, 2, KEY_RESERVED), + KEY(1, 3, KEY_F1), /* Left SoftKey */ + KEY(1, 4, KEY_NUMERIC_STAR), + KEY(1, 5, KEY_RESERVED), + + KEY(2, 0, KEY_NUMERIC_7), + KEY(2, 1, KEY_NUMERIC_9), + KEY(2, 2, KEY_RECORD), + KEY(2, 3, KEY_F2), /* Right SoftKey */ + KEY(2, 4, KEY_BACK), + KEY(2, 5, KEY_SELECT), + + KEY(3, 0, KEY_NUMERIC_2), + KEY(3, 1, KEY_UP), + KEY(3, 2, KEY_SEND), + KEY(3, 3, KEY_NUMERIC_0), + KEY(3, 4, KEY_NUMERIC_1), + KEY(3, 5, KEY_RECORD), + + KEY(4, 0, KEY_NUMERIC_4), + KEY(4, 1, KEY_LEFT), + KEY(4, 2, KEY_PAGEUP), + KEY(4, 3, KEY_NUMERIC_POUND), + KEY(4, 4, KEY_NUMERIC_3), + KEY(4, 5, KEY_RESERVED), +}; + +static struct pxa27x_keypad_platform_data a910_keypad_platform_data = { + .matrix_key_rows = 5, + .matrix_key_cols = 6, + .matrix_key_map = a910_key_map, + .matrix_key_map_size = ARRAY_SIZE(a910_key_map), + + .debounce_interval = 30, +}; +#endif /* CONFIG_MACH_EZX_A910 */ + +#ifdef CONFIG_MACH_EZX_E2 +static unsigned int e2_key_map[] = { + KEY(0, 0, KEY_NUMERIC_6), + KEY(0, 1, KEY_RIGHT), + KEY(0, 2, KEY_NUMERIC_9), + KEY(0, 3, KEY_NEXTSONG), + KEY(0, 4, KEY_NUMERIC_5), + KEY(0, 5, KEY_F1), /* Left SoftKey */ + + KEY(1, 0, KEY_NUMERIC_8), + KEY(1, 1, KEY_DOWN), + KEY(1, 2, KEY_RESERVED), + KEY(1, 3, KEY_PAGEUP), + KEY(1, 4, KEY_NUMERIC_STAR), + KEY(1, 5, KEY_F2), /* Right SoftKey */ + + KEY(2, 0, KEY_NUMERIC_7), + KEY(2, 1, KEY_KPENTER), + KEY(2, 2, KEY_RECORD), + KEY(2, 3, KEY_PAGEDOWN), + KEY(2, 4, KEY_BACK), + KEY(2, 5, KEY_NUMERIC_0), + + KEY(3, 0, KEY_NUMERIC_2), + KEY(3, 1, KEY_UP), + KEY(3, 2, KEY_SEND), + KEY(3, 3, KEY_PLAYPAUSE), + KEY(3, 4, KEY_NUMERIC_1), + KEY(3, 5, KEY_SOUND), /* Music SoftKey */ + + KEY(4, 0, KEY_NUMERIC_4), + KEY(4, 1, KEY_LEFT), + KEY(4, 2, KEY_NUMERIC_POUND), + KEY(4, 3, KEY_PREVIOUSSONG), + KEY(4, 4, KEY_NUMERIC_3), + KEY(4, 5, KEY_RESERVED), +}; + +static struct pxa27x_keypad_platform_data e2_keypad_platform_data = { + .matrix_key_rows = 5, + .matrix_key_cols = 6, + .matrix_key_map = e2_key_map, + .matrix_key_map_size = ARRAY_SIZE(e2_key_map), + + .debounce_interval = 30, +}; +#endif /* CONFIG_MACH_EZX_E2 */ + +#ifdef CONFIG_MACH_EZX_A780 +static void __init a780_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config)); + pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config)); + pxa2xx_mfp_config(ARRAY_AND_SIZE(a780_pin_config)); + pxa_set_i2c_info(NULL); - if (machine_is_ezx_a780() || machine_is_ezx_e680()) - set_pxa_fb_info(&ezx_fb_info_1); - else - set_pxa_fb_info(&ezx_fb_info_2); - platform_add_devices(devices, ARRAY_SIZE(devices)); -} + set_pxa_fb_info(&ezx_fb_info_1); -static void __init ezx_fixup(struct machine_desc *desc, struct tag *tags, - char **cmdline, struct meminfo *mi) -{ - /* We have two ram chips. First one with 32MB at 0xA0000000 and a second - * 16MB one at 0xAC000000 - */ - mi->nr_banks = 2; - mi->bank[0].start = 0xa0000000; - mi->bank[0].node = 0; - mi->bank[0].size = (32*1024*1024); - mi->bank[1].start = 0xac000000; - mi->bank[1].node = 1; - mi->bank[1].size = (16*1024*1024); + pxa_set_keypad_info(&a780_keypad_platform_data); + + platform_add_devices(devices, ARRAY_SIZE(devices)); } -#ifdef CONFIG_MACH_EZX_A780 MACHINE_START(EZX_A780, "Motorola EZX A780") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .fixup = ezx_fixup, .boot_params = 0xa0000100, .map_io = pxa_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, - .init_machine = &ezx_init, + .init_machine = a780_init, MACHINE_END #endif #ifdef CONFIG_MACH_EZX_E680 +static struct i2c_board_info __initdata e680_i2c_board_info[] = { + { I2C_BOARD_INFO("tea5767", 0x81) }, +}; + +static void __init e680_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config)); + pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config)); + pxa2xx_mfp_config(ARRAY_AND_SIZE(e680_pin_config)); + + pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info)); + + set_pxa_fb_info(&ezx_fb_info_1); + + pxa_set_keypad_info(&e680_keypad_platform_data); + + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + MACHINE_START(EZX_E680, "Motorola EZX E680") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .fixup = ezx_fixup, .boot_params = 0xa0000100, .map_io = pxa_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, - .init_machine = &ezx_init, + .init_machine = e680_init, MACHINE_END #endif #ifdef CONFIG_MACH_EZX_A1200 +static struct i2c_board_info __initdata a1200_i2c_board_info[] = { + { I2C_BOARD_INFO("tea5767", 0x81) }, +}; + +static void __init a1200_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config)); + pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); + pxa2xx_mfp_config(ARRAY_AND_SIZE(a1200_pin_config)); + + pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info)); + + set_pxa_fb_info(&ezx_fb_info_2); + + pxa_set_keypad_info(&a1200_keypad_platform_data); + + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + MACHINE_START(EZX_A1200, "Motorola EZX A1200") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .fixup = ezx_fixup, .boot_params = 0xa0000100, .map_io = pxa_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, - .init_machine = &ezx_init, + .init_machine = a1200_init, MACHINE_END #endif #ifdef CONFIG_MACH_EZX_A910 +static void __init a910_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config)); + pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); + pxa2xx_mfp_config(ARRAY_AND_SIZE(a910_pin_config)); + + pxa_set_i2c_info(NULL); + + set_pxa_fb_info(&ezx_fb_info_2); + + pxa_set_keypad_info(&a910_keypad_platform_data); + + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + MACHINE_START(EZX_A910, "Motorola EZX A910") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .fixup = ezx_fixup, .boot_params = 0xa0000100, .map_io = pxa_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, - .init_machine = &ezx_init, + .init_machine = a910_init, MACHINE_END #endif #ifdef CONFIG_MACH_EZX_E6 +static struct i2c_board_info __initdata e6_i2c_board_info[] = { + { I2C_BOARD_INFO("tea5767", 0x81) }, +}; + +static void __init e6_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config)); + pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); + pxa2xx_mfp_config(ARRAY_AND_SIZE(e6_pin_config)); + + pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info)); + + set_pxa_fb_info(&ezx_fb_info_2); + + pxa_set_keypad_info(&e6_keypad_platform_data); + + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + MACHINE_START(EZX_E6, "Motorola EZX E6") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .fixup = ezx_fixup, .boot_params = 0xa0000100, .map_io = pxa_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, - .init_machine = &ezx_init, + .init_machine = e6_init, MACHINE_END #endif #ifdef CONFIG_MACH_EZX_E2 +static struct i2c_board_info __initdata e2_i2c_board_info[] = { + { I2C_BOARD_INFO("tea5767", 0x81) }, +}; + +static void __init e2_init(void) +{ + pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config)); + pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); + pxa2xx_mfp_config(ARRAY_AND_SIZE(e2_pin_config)); + + pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info)); + + set_pxa_fb_info(&ezx_fb_info_2); + + pxa_set_keypad_info(&e2_keypad_platform_data); + + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + MACHINE_START(EZX_E2, "Motorola EZX E2") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, - .fixup = ezx_fixup, .boot_params = 0xa0000100, .map_io = pxa_map_io, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, - .init_machine = &ezx_init, + .init_machine = e2_init, MACHINE_END #endif diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 85ed0b3..0ccc91c 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -24,6 +24,7 @@ #include <asm/system.h> #include <asm/pgtable.h> #include <asm/mach/map.h> +#include <asm/mach-types.h> #include <mach/pxa-regs.h> #include <mach/reset.h> @@ -39,6 +40,21 @@ void clear_reset_status(unsigned int mask) pxa3xx_clear_reset_status(mask); } +unsigned long get_clock_tick_rate(void) +{ + unsigned long clock_tick_rate; + + if (cpu_is_pxa25x()) + clock_tick_rate = 3686400; + else if (machine_is_mainstone()) + clock_tick_rate = 3249600; + else + clock_tick_rate = 3250000; + + return clock_tick_rate; +} +EXPORT_SYMBOL(get_clock_tick_rate); + /* * Get the clock frequency as reflected by CCCR and the turbo flag. * We assume these values have been applied via a fcs. diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c index 14930cf..5fec1e4 100644 --- a/arch/arm/mach-pxa/gpio.c +++ b/arch/arm/mach-pxa/gpio.c @@ -25,6 +25,18 @@ #include "generic.h" +#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) +#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) +#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) +#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) + +#define GPLR_OFFSET 0x00 +#define GPDR_OFFSET 0x0C +#define GPSR_OFFSET 0x18 +#define GPCR_OFFSET 0x24 +#define GRER_OFFSET 0x30 +#define GFER_OFFSET 0x3C +#define GEDR_OFFSET 0x48 struct pxa_gpio_chip { struct gpio_chip chip; @@ -33,6 +45,18 @@ struct pxa_gpio_chip { int pxa_last_gpio; +#ifdef CONFIG_CPU_PXA26x +/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, + * as well as their Alternate Function value being '1' for GPIO in GAFRx. + */ +static int __gpio_is_inverted(unsigned gpio) +{ + return cpu_is_pxa25x() && gpio > 85; +} +#else +#define __gpio_is_inverted(gpio) (0) +#endif + /* * Configure pins for GPIO or other functions */ @@ -75,7 +99,10 @@ static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) gpdr = pxa->regbase + GPDR_OFFSET; local_irq_save(flags); value = __raw_readl(gpdr); - value &= ~mask; + if (__gpio_is_inverted(chip->base + offset)) + value |= mask; + else + value &= ~mask; __raw_writel(value, gpdr); local_irq_restore(flags); @@ -97,7 +124,10 @@ static int pxa_gpio_direction_output(struct gpio_chip *chip, gpdr = pxa->regbase + GPDR_OFFSET; local_irq_save(flags); tmp = __raw_readl(gpdr); - tmp |= mask; + if (__gpio_is_inverted(chip->base + offset)) + tmp &= ~mask; + else + tmp |= mask; __raw_writel(tmp, gpdr); local_irq_restore(flags); @@ -173,10 +203,17 @@ static unsigned long GPIO_IRQ_mask[4]; */ static int __gpio_is_occupied(unsigned gpio) { - if (cpu_is_pxa25x() || cpu_is_pxa27x()) - return GAFR(gpio) & (0x3 << (((gpio) & 0xf) * 2)); - else - return 0; + if (cpu_is_pxa27x() || cpu_is_pxa25x()) { + int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; + int dir = GPDR(gpio) & GPIO_bit(gpio); + + if (__gpio_is_inverted(gpio)) + return af != 1 || dir == 0; + else + return af != 0 || dir != 0; + } + + return 0; } static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) @@ -190,9 +227,8 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) /* Don't mess with enabled GPIOs using preconfigured edges or * GPIOs set to alternate function or to output during probe */ - if ((GPIO_IRQ_rising_edge[idx] | - GPIO_IRQ_falling_edge[idx] | - GPDR(gpio)) & GPIO_bit(gpio)) + if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) || + (GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio))) return 0; if (__gpio_is_occupied(gpio)) @@ -201,7 +237,10 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; } - GPDR(gpio) &= ~GPIO_bit(gpio); + if (__gpio_is_inverted(gpio)) + GPDR(gpio) |= GPIO_bit(gpio); + else + GPDR(gpio) &= ~GPIO_bit(gpio); if (type & IRQ_TYPE_EDGE_RISING) __set_bit(gpio, GPIO_IRQ_rising_edge); diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index d8962a0..e296ce1 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c @@ -184,15 +184,22 @@ static unsigned long gumstix_pin_config[] __initdata = { GPIO6_MMC_CLK, GPIO53_MMC_CLK, GPIO8_MMC_CS0, - /* these are used by AM200EPD */ - GPIO51_GPIO, - GPIO49_GPIO, - GPIO48_GPIO, - GPIO32_GPIO, - GPIO17_GPIO, - GPIO16_GPIO, }; +int __attribute__((weak)) am200_init(void) +{ + return 0; +} + +static void __init carrier_board_init(void) +{ + /* + * put carrier/expansion board init here if + * they cannot be detected programatically + */ + am200_init(); +} + static void __init gumstix_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(gumstix_pin_config)); @@ -201,6 +208,7 @@ static void __init gumstix_init(void) gumstix_udc_init(); gumstix_mmc_init(); (void) platform_add_devices(devices, ARRAY_SIZE(devices)); + carrier_board_init(); } MACHINE_START(GUMSTIX, "Gumstix") diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c new file mode 100644 index 0000000..da6e442 --- /dev/null +++ b/arch/arm/mach-pxa/h5000.c @@ -0,0 +1,200 @@ +/* + * Hardware definitions for HP iPAQ h5xxx Handheld Computers + * + * Copyright 2000-2003 Hewlett-Packard Company. + * Copyright 2002 Jamey Hicks <jamey.hicks@hp.com> + * Copyright 2004-2005 Phil Blundell <pb@handhelds.org> + * Copyright 2007-2008 Anton Vorontsov <cbouatmailru@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, + * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS + * FITNESS FOR ANY PARTICULAR PURPOSE. + * + * Author: Jamey Hicks. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/h5000.h> +#include <mach/pxa-regs.h> +#include <mach/pxa2xx-regs.h> +#include <mach/mfp-pxa25x.h> +#include <mach/udc.h> +#include "generic.h" + +/* + * Flash + */ + +static struct mtd_partition h5000_flash0_partitions[] = { + { + .name = "bootldr", + .size = 0x00040000, + .offset = 0, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "root", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + }, +}; + +static struct mtd_partition h5000_flash1_partitions[] = { + { + .name = "second root", + .size = SZ_16M - 0x00040000, + .offset = 0, + }, + { + .name = "asset", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, +}; + +static struct physmap_flash_data h5000_flash0_data = { + .width = 4, + .parts = h5000_flash0_partitions, + .nr_parts = ARRAY_SIZE(h5000_flash0_partitions), +}; + +static struct physmap_flash_data h5000_flash1_data = { + .width = 4, + .parts = h5000_flash1_partitions, + .nr_parts = ARRAY_SIZE(h5000_flash1_partitions), +}; + +static struct resource h5000_flash0_resources = { + .start = PXA_CS0_PHYS, + .end = PXA_CS0_PHYS + SZ_32M - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, +}; + +static struct resource h5000_flash1_resources = { + .start = PXA_CS0_PHYS + SZ_32M, + .end = PXA_CS0_PHYS + SZ_32M + SZ_16M - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, +}; + +static struct platform_device h5000_flash[] = { + { + .name = "physmap-flash", + .id = 0, + .resource = &h5000_flash0_resources, + .num_resources = 1, + .dev = { + .platform_data = &h5000_flash0_data, + }, + }, + { + .name = "physmap-flash", + .id = 1, + .resource = &h5000_flash1_resources, + .num_resources = 1, + .dev = { + .platform_data = &h5000_flash1_data, + }, + }, +}; + +/* + * USB Device Controller + */ + +static struct pxa2xx_udc_mach_info h5000_udc_mach_info __initdata = { + .gpio_pullup = H5000_GPIO_USB_PULLUP, +}; + +/* + * GPIO setup + */ + +static unsigned long h5000_pin_config[] __initdata = { + /* Crystal and Clock Signals */ + GPIO12_32KHz, + + /* SDRAM and Static Memory I/O Signals */ + GPIO15_nCS_1, + GPIO78_nCS_2, + GPIO79_nCS_3, + GPIO80_nCS_4, + + /* FFUART */ + GPIO34_FFUART_RXD, + GPIO35_FFUART_CTS, + GPIO36_FFUART_DCD, + GPIO37_FFUART_DSR, + GPIO38_FFUART_RI, + GPIO39_FFUART_TXD, + GPIO40_FFUART_DTR, + GPIO41_FFUART_RTS, + + /* BTUART */ + GPIO42_BTUART_RXD, + GPIO43_BTUART_TXD, + GPIO44_BTUART_CTS, + GPIO45_BTUART_RTS, + + /* SSP1 */ + GPIO23_SSP1_SCLK, + GPIO25_SSP1_TXD, + GPIO26_SSP1_RXD, +}; + +/* + * Localbus setup: + * CS0: Flash; + * CS1: MediaQ chip, select 16-bit bus and vlio; + * CS5: SAMCOP. + */ + +static void fix_msc(void) +{ + MSC0 = 0x129c24f2; + MSC1 = 0x7ff424fa; + MSC2 = 0x7ff47ff4; + + MDREFR |= 0x02080000; +} + +/* + * Platform devices + */ + +static struct platform_device *devices[] __initdata = { + &h5000_flash[0], + &h5000_flash[1], +}; + +static void __init h5000_init(void) +{ + fix_msc(); + + pxa2xx_mfp_config(ARRAY_AND_SIZE(h5000_pin_config)); + pxa_set_udc_info(&h5000_udc_mach_info); + platform_add_devices(ARRAY_AND_SIZE(devices)); +} + +MACHINE_START(H5400, "HP iPAQ H5000") + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa25x_init_irq, + .timer = &pxa_timer, + .init_machine = h5000_init, +MACHINE_END diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c new file mode 100644 index 0000000..364c5e2 --- /dev/null +++ b/arch/arm/mach-pxa/imote2.c @@ -0,0 +1,575 @@ +/* + * linux/arch/arm/mach-pxa/imote2.c + * + * Author: Ed C. Epp + * Created: Nov 05, 2002 + * Copyright: Intel Corp. + * + * Modified 2008: Jonathan Cameron + * + * The Imote2 is a wireless sensor node platform sold + * by Crossbow (www.xbow.com). + */ + +#include <linux/init.h> +#include <linux/device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/platform_device.h> +#include <linux/regulator/machine.h> +#include <linux/gpio.h> +#include <linux/leds.h> +#include <linux/spi/spi.h> +#include <linux/i2c.h> +#include <linux/mfd/da903x.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/flash.h> + +#include <mach/i2c.h> +#include <mach/pxa-regs.h> +#include <mach/pxa2xx-regs.h> +#include <mach/mfp-pxa27x.h> +#include <mach/regs-ssp.h> +#include <mach/udc.h> +#include <mach/mmc.h> +#include <mach/pxa2xx_spi.h> +#include <mach/pxa27x-udc.h> + +#include "devices.h" +#include "generic.h" + +static unsigned long imote2_pin_config[] __initdata = { + + /* Device Identification for wakeup*/ + GPIO102_GPIO, + + /* Button */ + GPIO91_GPIO, + + /* DA9030 */ + GPIO1_GPIO, + + /* MMC */ + GPIO32_MMC_CLK, + GPIO112_MMC_CMD, + GPIO92_MMC_DAT_0, + GPIO109_MMC_DAT_1, + GPIO110_MMC_DAT_2, + GPIO111_MMC_DAT_3, + + /* 802.15.4 radio - driver out of mainline */ + GPIO22_GPIO, /* CC_RSTN */ + GPIO114_GPIO, /* CC_FIFO */ + GPIO116_GPIO, /* CC_CCA */ + GPIO0_GPIO, /* CC_FIFOP */ + GPIO16_GPIO, /* CCSFD */ + GPIO39_GPIO, /* CSn */ + GPIO115_GPIO, /* Power enable */ + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + + /* SSP 3 - 802.15.4 radio */ + GPIO39_GPIO, /* Chip Select */ + GPIO34_SSP3_SCLK, + GPIO35_SSP3_TXD, + GPIO41_SSP3_RXD, + + /* SSP 2 - to daughter boards */ + GPIO37_GPIO, /* Chip Select */ + GPIO36_SSP2_SCLK, + GPIO38_SSP2_TXD, + GPIO11_SSP2_RXD, + + /* SSP 1 - to daughter boards */ + GPIO24_GPIO, /* Chip Select */ + GPIO23_SSP1_SCLK, + GPIO25_SSP1_TXD, + GPIO26_SSP1_RXD, + + /* BTUART Basic Connector*/ + GPIO42_BTUART_RXD, + GPIO43_BTUART_TXD, + GPIO44_BTUART_CTS, + GPIO45_BTUART_RTS, + + /* STUART Serial console via debug board*/ + GPIO46_STUART_RXD, + GPIO47_STUART_TXD, + + /* Basic sensor board */ + GPIO96_GPIO, /* accelerometer interrupt */ + GPIO99_GPIO, /* ADC interrupt */ + + /* Connector pins specified as gpios */ + GPIO94_GPIO, /* large basic connector pin 14 */ + GPIO10_GPIO, /* large basic connector pin 23 */ + + /* LEDS */ + GPIO103_GPIO, /* red led */ + GPIO104_GPIO, /* green led */ + GPIO105_GPIO, /* blue led */ +}; + +static struct gpio_led imote2_led_pins[] = { + { + .name = "imote2:red", + .gpio = 103, + .active_low = 1, + }, { + .name = "imote2:green", + .gpio = 104, + .active_low = 1, + }, { + .name = "imote2:blue", + .gpio = 105, + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data imote2_led_data = { + .num_leds = ARRAY_SIZE(imote2_led_pins), + .leds = imote2_led_pins, +}; + +static struct platform_device imote2_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &imote2_led_data, + }, +}; + +/* Reverse engineered partly from Platformx drivers */ +enum imote2_ldos{ + vcc_vref, + vcc_cc2420, + vcc_mica, + vcc_bt, + /* The two voltages available to sensor boards */ + vcc_sensor_1_8, + vcc_sensor_3, + + vcc_sram_ext, /* directly connected to the pxa271 */ + vcc_pxa_pll, + vcc_pxa_usim, /* Reference voltage for certain gpios */ + vcc_pxa_mem, + vcc_pxa_flash, + vcc_pxa_core, /*Dc-Dc buck not yet supported */ + vcc_lcd, + vcc_bb, + vcc_bbio, + vcc_io, /* cc2420 802.15.4 radio and pxa vcc_io ?*/ +}; + +/* The values of the various regulator constraints are obviously dependent + * on exactly what is wired to each ldo. Unfortunately this information is + * not generally available. More information has been requested from Xbow + * but as of yet they haven't been forthcoming. + * + * Some of these are clearly Stargate 2 related (no way of plugging + * in an lcd on the IM2 for example!). + */ +static struct regulator_init_data imote2_ldo_init_data[] = { + [vcc_bbio] = { + .constraints = { /* board default 1.8V */ + .name = "vcc_bbio", + .min_uV = 1800000, + .max_uV = 1800000, + }, + }, + [vcc_bb] = { + .constraints = { /* board default 2.8V */ + .name = "vcc_bb", + .min_uV = 2700000, + .max_uV = 3000000, + }, + }, + [vcc_pxa_flash] = { + .constraints = {/* default is 1.8V */ + .name = "vcc_pxa_flash", + .min_uV = 1800000, + .max_uV = 1800000, + }, + }, + [vcc_cc2420] = { /* also vcc_io */ + .constraints = { + /* board default is 2.8V */ + .name = "vcc_cc2420", + .min_uV = 2700000, + .max_uV = 3300000, + }, + }, + [vcc_vref] = { /* Reference for what? */ + .constraints = { /* default 1.8V */ + .name = "vcc_vref", + .min_uV = 1800000, + .max_uV = 1800000, + }, + }, + [vcc_sram_ext] = { + .constraints = { /* default 2.8V */ + .name = "vcc_sram_ext", + .min_uV = 2800000, + .max_uV = 2800000, + }, + }, + [vcc_mica] = { + .constraints = { /* default 2.8V */ + .name = "vcc_mica", + .min_uV = 2800000, + .max_uV = 2800000, + }, + }, + [vcc_bt] = { + .constraints = { /* default 2.8V */ + .name = "vcc_bt", + .min_uV = 2800000, + .max_uV = 2800000, + }, + }, + [vcc_lcd] = { + .constraints = { /* default 2.8V */ + .name = "vcc_lcd", + .min_uV = 2700000, + .max_uV = 3300000, + }, + }, + [vcc_io] = { /* Same or higher than everything + * bar vccbat and vccusb */ + .constraints = { /* default 2.8V */ + .name = "vcc_io", + .min_uV = 2692000, + .max_uV = 3300000, + }, + }, + [vcc_sensor_1_8] = { + .constraints = { /* default 1.8V */ + .name = "vcc_sensor_1_8", + .min_uV = 1800000, + .max_uV = 1800000, + }, + }, + [vcc_sensor_3] = { /* curiously default 2.8V */ + .constraints = { + .name = "vcc_sensor_3", + .min_uV = 2800000, + .max_uV = 3000000, + }, + }, + [vcc_pxa_pll] = { /* 1.17V - 1.43V, default 1.3V*/ + .constraints = { + .name = "vcc_pxa_pll", + .min_uV = 1170000, + .max_uV = 1430000, + }, + }, + [vcc_pxa_usim] = { + .constraints = { /* default 1.8V */ + .name = "vcc_pxa_usim", + .min_uV = 1710000, + .max_uV = 2160000, + }, + }, + [vcc_pxa_mem] = { + .constraints = { /* default 1.8V */ + .name = "vcc_pxa_mem", + .min_uV = 1800000, + .max_uV = 1800000, + }, + }, +}; + +static struct da903x_subdev_info imote2_da9030_subdevs[] = { + { + .name = "da903x-regulator", + .id = DA9030_ID_LDO2, + .platform_data = &imote2_ldo_init_data[vcc_bbio], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO3, + .platform_data = &imote2_ldo_init_data[vcc_bb], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO4, + .platform_data = &imote2_ldo_init_data[vcc_pxa_flash], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO5, + .platform_data = &imote2_ldo_init_data[vcc_cc2420], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO6, + .platform_data = &imote2_ldo_init_data[vcc_vref], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO7, + .platform_data = &imote2_ldo_init_data[vcc_sram_ext], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO8, + .platform_data = &imote2_ldo_init_data[vcc_mica], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO9, + .platform_data = &imote2_ldo_init_data[vcc_bt], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO10, + .platform_data = &imote2_ldo_init_data[vcc_sensor_1_8], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO11, + .platform_data = &imote2_ldo_init_data[vcc_sensor_3], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO12, + .platform_data = &imote2_ldo_init_data[vcc_lcd], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO15, + .platform_data = &imote2_ldo_init_data[vcc_pxa_pll], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO17, + .platform_data = &imote2_ldo_init_data[vcc_pxa_usim], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO18, + .platform_data = &imote2_ldo_init_data[vcc_io], + }, { + .name = "da903x-regulator", + .id = DA9030_ID_LDO19, + .platform_data = &imote2_ldo_init_data[vcc_pxa_mem], + }, +}; + +static struct da903x_platform_data imote2_da9030_pdata = { + .num_subdevs = ARRAY_SIZE(imote2_da9030_subdevs), + .subdevs = imote2_da9030_subdevs, +}; + +/* As the the imote2 doesn't currently have a conventional SD slot + * there is no option to hotplug cards, making all this rather simple + */ +static int imote2_mci_get_ro(struct device *dev) +{ + return 0; +} + +/* Rather simple case as hotplugging not possible */ +static struct pxamci_platform_data imote2_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* default anyway */ + .get_ro = imote2_mci_get_ro, +}; + +static struct mtd_partition imote2flash_partitions[] = { + { + .name = "Bootloader", + .size = 0x00040000, + .offset = 0, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "Kernel", + .size = 0x00200000, + .offset = 0x00040000, + .mask_flags = 0, + }, { + .name = "Filesystem", + .size = 0x01DC0000, + .offset = 0x00240000, + .mask_flags = 0, + }, +}; + +static struct resource flash_resources = { + .start = PXA_CS0_PHYS, + .end = PXA_CS0_PHYS + SZ_32M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct flash_platform_data imote2_flash_data = { + .map_name = "cfi_probe", + .parts = imote2flash_partitions, + .nr_parts = ARRAY_SIZE(imote2flash_partitions), + .name = "PXA27xOnChipROM", + .width = 2, +}; + +static struct platform_device imote2_flash_device = { + .name = "pxa2xx-flash", + .id = 0, + .dev = { + .platform_data = &imote2_flash_data, + }, + .resource = &flash_resources, + .num_resources = 1, +}; + +/* Some of the drivers here are out of kernel at the moment (parts of IIO) + * and it may be a while before they are in the mainline. + */ +static struct i2c_board_info __initdata imote2_i2c_board_info[] = { + { /* UCAM sensor board */ + .type = "max1238", + .addr = 0x35, + }, { /* ITS400 Sensor board only */ + .type = "max1363", + .addr = 0x34, + /* Through a nand gate - Also beware, on V2 sensor board the + * pull up resistors are missing. + */ + .irq = IRQ_GPIO(99), + }, { /* ITS400 Sensor board only */ + .type = "tsl2561", + .addr = 0x49, + /* Through a nand gate - Also beware, on V2 sensor board the + * pull up resistors are missing. + */ + .irq = IRQ_GPIO(99), + }, { /* ITS400 Sensor board only */ + .type = "tmp175", + .addr = 0x4A, + .irq = IRQ_GPIO(96), + }, +}; + +static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = { + { + .type = "da9030", + .addr = 0x49, + .platform_data = &imote2_da9030_pdata, + .irq = gpio_to_irq(1), + }, +}; + +static struct pxa2xx_spi_master pxa_ssp_master_0_info = { + .num_chipselect = 1, +}; + +static struct pxa2xx_spi_master pxa_ssp_master_1_info = { + .num_chipselect = 1, +}; + +static struct pxa2xx_spi_master pxa_ssp_master_2_info = { + .num_chipselect = 1, +}; + +/* Patch posted by Eric Miao <eric.miao@marvell.com> will remove + * the need for these functions. + */ +static void spi1control(u32 command) +{ + gpio_set_value(24, command & PXA2XX_CS_ASSERT ? 0 : 1); +}; + +static void spi3control(u32 command) +{ + gpio_set_value(39, command & PXA2XX_CS_ASSERT ? 0 : 1); +}; + +static struct pxa2xx_spi_chip staccel_chip_info = { + .tx_threshold = 8, + .rx_threshold = 8, + .dma_burst_size = 8, + .timeout = 235, + .cs_control = spi1control, +}; + +static struct pxa2xx_spi_chip cc2420_info = { + .tx_threshold = 8, + .rx_threshold = 8, + .dma_burst_size = 8, + .timeout = 235, + .cs_control = spi3control, +}; + +static struct spi_board_info spi_board_info[] __initdata = { + { /* Driver in IIO */ + .modalias = "lis3l02dq", + .max_speed_hz = 8000000,/* 8MHz max spi frequency at 3V */ + .bus_num = 1, + .chip_select = 0, + .controller_data = &staccel_chip_info, + .irq = IRQ_GPIO(96), + }, { /* Driver out of kernel as it needs considerable rewriting */ + .modalias = "cc2420", + .max_speed_hz = 6500000, + .bus_num = 3, + .chip_select = 0, + .controller_data = &cc2420_info, + }, +}; + +static void im2_udc_command(int cmd) +{ + switch (cmd) { + case PXA2XX_UDC_CMD_CONNECT: + UP2OCR |= UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE; + break; + case PXA2XX_UDC_CMD_DISCONNECT: + UP2OCR &= ~(UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE); + break; + } +} + +static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = { + .udc_command = im2_udc_command, +}; + +static struct platform_device *imote2_devices[] = { + &imote2_flash_device, + &imote2_leds, +}; + +static struct i2c_pxa_platform_data i2c_pwr_pdata = { + .fast_mode = 1, +}; + +static struct i2c_pxa_platform_data i2c_pdata = { + .fast_mode = 1, +}; + +static void __init imote2_init(void) +{ + + pxa2xx_mfp_config(ARRAY_AND_SIZE(imote2_pin_config)); + /* SPI chip select directions - all other directions should + * be handled by drivers.*/ + gpio_direction_output(37, 0); + gpio_direction_output(24, 0); + gpio_direction_output(39, 0); + + platform_add_devices(imote2_devices, ARRAY_SIZE(imote2_devices)); + + pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info); + pxa2xx_set_spi_info(2, &pxa_ssp_master_1_info); + pxa2xx_set_spi_info(3, &pxa_ssp_master_2_info); + + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); + + i2c_register_board_info(0, imote2_i2c_board_info, + ARRAY_SIZE(imote2_i2c_board_info)); + i2c_register_board_info(1, imote2_pwr_i2c_board_info, + ARRAY_SIZE(imote2_pwr_i2c_board_info)); + + pxa27x_set_i2c_power_info(&i2c_pwr_pdata); + pxa_set_i2c_info(&i2c_pdata); + + pxa_set_mci_info(&imote2_mci_platform_data); + pxa_set_udc_info(&imote2_udc_info); +} + +MACHINE_START(INTELMOTE2, "IMOTE 2") + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = pxa27x_init_irq, + .timer = &pxa_timer, + .init_machine = imote2_init, + .boot_params = 0xA0000100, +MACHINE_END diff --git a/arch/arm/mach-pxa/include/mach/clkdev.h b/arch/arm/mach-pxa/include/mach/clkdev.h new file mode 100644 index 0000000..04b37a8 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h index 955bfe6..7804637 100644 --- a/arch/arm/mach-pxa/include/mach/dma.h +++ b/arch/arm/mach-pxa/include/mach/dma.h @@ -30,10 +30,6 @@ typedef enum { DMA_PRIO_LOW = 2 } pxa_dma_prio; -#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) -#define HAVE_ARCH_PCI_SET_DMA_MASK 1 -#endif - /* * DMA registration */ diff --git a/arch/arm/mach-pxa/include/mach/eseries-gpio.h b/arch/arm/mach-pxa/include/mach/eseries-gpio.h index 4c90b13..efbd2aa 100644 --- a/arch/arm/mach-pxa/include/mach/eseries-gpio.h +++ b/arch/arm/mach-pxa/include/mach/eseries-gpio.h @@ -43,8 +43,10 @@ #define GPIO_E800_PCMCIA_PWR1 73 /* e7xx IrDA power control */ -#define GPIO_E7XX_IR_ON 38 +#define GPIO_E7XX_IR_OFF 38 /* ASIC related GPIOs */ #define GPIO_ESERIES_TMIO_IRQ 5 +#define GPIO_ESERIES_TMIO_PCLR 19 +#define GPIO_ESERIES_TMIO_SUSPEND 45 #define GPIO_E800_ANGELX_IRQ 8 diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h index 42ee195..099f54a 100644 --- a/arch/arm/mach-pxa/include/mach/gumstix.h +++ b/arch/arm/mach-pxa/include/mach/gumstix.h @@ -94,3 +94,7 @@ has detected a cable insertion; driven low otherwise. */ #define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN) #define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN) #define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN) + +/* for expansion boards that can't be programatically detected */ +extern int am200_init(void); + diff --git a/arch/arm/mach-pxa/include/mach/h5000.h b/arch/arm/mach-pxa/include/mach/h5000.h new file mode 100644 index 0000000..2a5ae38 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/h5000.h @@ -0,0 +1,113 @@ +/* + * Hardware definitions for HP iPAQ h5xxx Handheld Computers + * + * Copyright(20)02 Hewlett-Packard Company. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, + * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS + * FITNESS FOR ANY PARTICULAR PURPOSE. + * + * Author: Jamey Hicks + */ + +#ifndef __ASM_ARCH_H5000_H +#define __ASM_ARCH_H5000_H + +#include <mach/mfp-pxa25x.h> + +/* + * CPU GPIOs + */ + +#define H5000_GPIO_POWER_BUTTON (0) +#define H5000_GPIO_RESET_BUTTON_N (1) +#define H5000_GPIO_OPT_INT (2) +#define H5000_GPIO_BACKUP_POWER (3) +#define H5000_GPIO_ACTION_BUTTON (4) +#define H5000_GPIO_COM_DCD_SOMETHING (5) /* what is this really ? */ +/* 6 not connected */ +#define H5000_GPIO_RESET_BUTTON_AGAIN_N (7) /* connected to gpio 1 as well */ +/* 8 not connected */ +#define H5000_GPIO_RSO_N (9) /* reset output from max1702 which regulates 3.3 and 2.5 */ +#define H5000_GPIO_ASIC_INT_N (10) /* from companion asic */ +#define H5000_GPIO_BT_ENV_0 (11) /* to LMX9814, set to 1 according to regdump */ +/*(12) not connected */ +#define H5000_GPIO_BT_ENV_1 (13) /* to LMX9814, set to 1 according to regdump */ +#define H5000_GPIO_BT_WU (14) /* from LMX9814, Defined as HOST_WAKEUP in the LMX9820 data sheet */ +/*(15) is CS1# */ +/*(16) not connected */ +/*(17) not connected */ +/*(18) is pcmcia ready */ +/*(19) is dreq1 */ +/*(20) is dreq0 */ +#define H5000_GPIO_OE_RD_NWR (21) /* output enable on rd/nwr signal to companion asic */ +/*(22) is not connected */ +#define H5000_GPIO_OPT_SPI_CLK (23) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_CS_N (24) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_DOUT (25) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_DIN (26) /* to extension pack */ +/*(27) not connected */ +#define H5000_GPIO_I2S_BITCLK (28) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_DATAOUT (29) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_DATAIN (30) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_LRCLK (31) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_SYSCLK (32) /* connected to AC97 codec */ +/*(33) is CS5# */ +#define H5000_GPIO_COM_RXD (34) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_CTS (35) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DCD (36) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DSR (37) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_RI (38) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_TXD (39) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DTR (40) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_RTS (41) /* connected to cradle/cable connector */ + +#define H5000_GPIO_BT_RXD (42) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_TXD (43) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_CTS (44) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_RTS (45) /* connected to BT (LMX9814) */ + +#define H5000_GPIO_IRDA_RXD (46) +#define H5000_GPIO_IRDA_TXD (47) + +#define H5000_GPIO_POE_N (48) /* used for pcmcia */ +#define H5000_GPIO_PWE_N (49) /* used for pcmcia */ +#define H5000_GPIO_PIOR_N (50) /* used for pcmcia */ +#define H5000_GPIO_PIOW_N (51) /* used for pcmcia */ +#define H5000_GPIO_PCE1_N (52) /* used for pcmcia */ +#define H5000_GPIO_PCE2_N (53) /* used for pcmcia */ +#define H5000_GPIO_PSKTSEL (54) /* used for pcmcia */ +#define H5000_GPIO_PREG_N (55) /* used for pcmcia */ +#define H5000_GPIO_PWAIT_N (56) /* used for pcmcia */ +#define H5000_GPIO_IOIS16_N (57) /* used for pcmcia */ + +#define H5000_GPIO_IRDA_SD (58) /* to hsdl3002 sd */ +/*(59) not connected */ +#define H5000_GPIO_POWER_SD_N (60) /* controls power to SD */ +#define H5000_GPIO_POWER_RS232_N (61) /* inverted FORCEON to rs232 transceiver */ +#define H5000_GPIO_POWER_ACCEL_N (62) /* controls power to accel */ +/*(63) is not connected */ +#define H5000_GPIO_OPT_NVRAM (64) /* controls power to expansion pack */ +#define H5000_GPIO_CHG_EN (65) /* to sc801 en */ +#define H5000_GPIO_USB_PULLUP (66) /* USB d+ pullup via 1.5K resistor */ +#define H5000_GPIO_BT_2V8_N (67) /* 2.8V used by bluetooth */ +#define H5000_GPIO_EXT_CHG_RATE (68) /* enables external charging rate */ +/*(69) is not connected */ +#define H5000_GPIO_CIR_RESET (70) /* consumer IR reset */ +#define H5000_GPIO_POWER_LIGHT_SENSOR_N (71) +#define H5000_GPIO_BT_M_RESET (72) +#define H5000_GPIO_STD_CHG_RATE (73) +#define H5000_GPIO_SD_WP_N (74) +#define H5000_GPIO_MOTOR_ON_N (75) /* external pullup on this */ +#define H5000_GPIO_HEADPHONE_DETECT (76) +#define H5000_GPIO_USB_CHG_RATE (77) /* select rate for charging via usb */ +/*(78) is CS2# */ +/*(79) is CS3# */ +/*(80) is CS4# */ + +#endif /* __ASM_ARCH_H5000_H */ diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index a582a6d..16ab795 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -102,6 +102,9 @@ * PXA930 B0 0x69056835 0x5E643013 * PXA930 B1 0x69056837 0x7E643013 * PXA930 B2 0x69056838 0x8E643013 + * + * PXA935 A0 0x56056931 0x1E653013 + * PXA935 B0 0x56056936 0x6E653013 */ #ifdef CONFIG_PXA25x #define __cpu_is_pxa210(id) \ @@ -178,12 +181,22 @@ #define __cpu_is_pxa930(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ - _id == 0x683; \ + _id == 0x683; \ }) #else #define __cpu_is_pxa930(id) (0) #endif +#ifdef CONFIG_CPU_PXA935 +#define __cpu_is_pxa935(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x693; \ + }) +#else +#define __cpu_is_pxa935(id) (0) +#endif + #define cpu_is_pxa210() \ ({ \ __cpu_is_pxa210(read_cpuid_id()); \ @@ -204,8 +217,6 @@ __cpu_is_pxa25x(read_cpuid_id()); \ }) -extern int cpu_is_pxa26x(void); - #define cpu_is_pxa27x() \ ({ \ __cpu_is_pxa27x(read_cpuid_id()); \ @@ -232,6 +243,12 @@ extern int cpu_is_pxa26x(void); __cpu_is_pxa930(id); \ }) +#define cpu_is_pxa935() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa935(id); \ + }) + /* * CPUID Core Generation Bit * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x @@ -249,6 +266,12 @@ extern int cpu_is_pxa26x(void); _id == 0x3; \ }) +#define __cpu_is_pxa9xx(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x683 || _id == 0x693; \ + }) + #define cpu_is_pxa2xx() \ ({ \ __cpu_is_pxa2xx(read_cpuid_id()); \ @@ -259,32 +282,25 @@ extern int cpu_is_pxa26x(void); __cpu_is_pxa3xx(read_cpuid_id()); \ }) -/* - * Handy routine to set GPIO alternate functions - */ -extern int pxa_gpio_mode( int gpio_mode ); - -/* - * Return GPIO level, nonzero means high, zero is low - */ -extern int pxa_gpio_get_value(unsigned gpio); - -/* - * Set output GPIO level - */ -extern void pxa_gpio_set_value(unsigned gpio, int value); - +#define cpu_is_pxa9xx() \ + ({ \ + __cpu_is_pxa9xx(read_cpuid_id()); \ + }) /* * return current memory and LCD clock frequency in units of 10kHz */ extern unsigned int get_memclk_frequency_10khz(void); +/* return the clock tick rate of the OS timer */ +extern unsigned long get_clock_tick_rate(void); #endif #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) #define PCIBIOS_MIN_IO 0 #define PCIBIOS_MIN_MEM 0 #define pcibios_assign_all_busses() 1 +#define HAVE_ARCH_PCI_SET_DMA_MASK 1 #endif + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h index 600fd4f..262691f 100644 --- a/arch/arm/mach-pxa/include/mach/io.h +++ b/arch/arm/mach-pxa/include/mach/io.h @@ -6,15 +6,13 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#include <mach/hardware.h> - #define IO_SPACE_LIMIT 0xffffffff /* * We don't actually have real ISA nor PCI buses, but there is so many * drivers out there that might just work if we fake them... */ -#define __io(a) ((void __iomem *)(a)) -#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h index 5c4e320..6c9b21c 100644 --- a/arch/arm/mach-pxa/include/mach/littleton.h +++ b/arch/arm/mach-pxa/include/mach/littleton.h @@ -1,8 +1,13 @@ -#ifndef __ASM_ARCH_ZYLONITE_H -#define __ASM_ARCH_ZYLONITE_H +#ifndef __ASM_ARCH_LITTLETON_H +#define __ASM_ARCH_LITTLETON_H + +#include <mach/gpio.h> #define LITTLETON_ETH_PHYS 0x30000000 #define LITTLETON_GPIO_LCD_CS (17) -#endif /* __ASM_ARCH_ZYLONITE_H */ +#define EXT0_GPIO_BASE (NR_BUILTIN_GPIO) +#define EXT0_GPIO(x) (EXT0_GPIO_BASE + (x)) + +#endif /* __ASM_ARCH_LITTLETON_H */ diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h index 59aef89..f626730 100644 --- a/arch/arm/mach-pxa/include/mach/memory.h +++ b/arch/arm/mach-pxa/include/mach/memory.h @@ -18,16 +18,6 @@ #define PHYS_OFFSET UL(0xa0000000) /* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - -/* * The nodes are matched with the physical SDRAM banks as follows: * * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff @@ -47,6 +37,7 @@ void cmx2xx_pci_adjust_zones(int node, unsigned long *size, cmx2xx_pci_adjust_zones(node, size, holes) #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) +#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) #endif #endif diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h index 617cab2..a72869b 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h @@ -158,4 +158,35 @@ #define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) #define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) +#ifdef CONFIG_CPU_PXA26x +/* GPIO */ +#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF1) +#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF1) +#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF1) +#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF1) + +/* SDRAM */ +#define GPIO86_nSDCS2 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH) +#define GPIO87_nSDCS3 MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH) +#define GPIO88_RDnWR MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH) +#define GPIO89_nACRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH) + +/* USB */ +#define GPIO9_USB_RCV MFP_CFG_IN(GPIO9, AF1) +#define GPIO32_USB_VP MFP_CFG_IN(GPIO32, AF2) +#define GPIO34_USB_VM MFP_CFG_IN(GPIO34, AF2) +#define GPIO39_USB_VPO MFP_CFG_OUT(GPIO39, AF3, DRIVE_LOW) +#define GPIO56_USB_VMO MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) +#define GPIO57_USB_nOE MFP_CFG_OUT(GPIO57, AF1, DRIVE_HIGH) + +/* ASSP */ +#define GPIO28_ASSP_BITCLK_IN MFP_CFG_IN(GPIO28, AF3) +#define GPIO28_ASSP_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF3, DRIVE_LOW) +#define GPIO29_ASSP_RXD MFP_CFG_IN(GPIO29, AF3) +#define GPIO30_ASSP_TXD MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) +#define GPIO31_ASSP_SFRM_IN MFP_CFG_IN(GPIO31, AF1) +#define GPIO31_ASSP_SFRM_OUT MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) +#endif + #endif /* __ASM_ARCH_MFP_PXA25X_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h index 122bdbd..da4f85a 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h @@ -11,6 +11,12 @@ #include <mach/mfp.h> #include <mach/mfp-pxa2xx.h> +/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN + * bit is set, regardless of the GPIO configuration + */ +#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) + /* GPIO */ #define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) #define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h index fabd9b4..fa73f56 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h @@ -421,6 +421,7 @@ #define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW) #define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW) #define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW) +#define GPIO32_PWM0 MFP_CFG_LPM(GPIO32, AF4, PULL_LOW) /* CIR */ #define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1) diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h index 8483cb5..0286844 100644 --- a/arch/arm/mach-pxa/include/mach/mioa701.h +++ b/arch/arm/mach-pxa/include/mach/mioa701.h @@ -10,12 +10,14 @@ (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) /* Global GPIOs */ -#define GPIO9_CHARGE_nEN 9 +#define GPIO9_CHARGE_EN 9 #define GPIO18_POWEROFF 18 #define GPIO87_LCD_POWER 87 +#define GPIO96_AC_DETECT 96 +#define GPIO80_MAYBE_CHARGE_VDROP 80 /* Drop of 88mV */ /* USB */ -#define GPIO13_USB_DETECT 13 +#define GPIO13_nUSB_DETECT 13 #define GPIO22_USB_ENABLE 22 /* SDIO bits */ @@ -24,7 +26,10 @@ #define GPIO91_SDIO_EN 91 /* Bluetooth */ +#define GPIO14_BT_nACTIVITY 14 #define GPIO83_BT_ON 83 +#define GPIO77_BT_UNKNOWN1 77 +#define GPIO86_BT_MAYBE_nRESET 86 /* GPS */ #define GPIO23_GPS_UNKNOWN1 23 diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h index 4d452fc..cfca815 100644 --- a/arch/arm/mach-pxa/include/mach/mtd-xip.h +++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h @@ -15,6 +15,7 @@ #ifndef __ARCH_PXA_MTD_XIP_H__ #define __ARCH_PXA_MTD_XIP_H__ +#include <mach/hardware.h> #include <mach/pxa-regs.h> #define xip_irqpending() (ICIP & ICMR) diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h index 15295d9..31d615a 100644 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h @@ -13,6 +13,7 @@ #ifndef __PXA_REGS_H #define __PXA_REGS_H +#include <mach/hardware.h> /* * PXA Chip selects @@ -123,298 +124,6 @@ #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ - -/* - * UARTs - */ - -/* Full Function UART (FFUART) */ -#define FFUART FFRBR -#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ -#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ -#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ -#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ -#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ -#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ -#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ -#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ -#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ -#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ -#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ -#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Bluetooth UART (BTUART) */ -#define BTUART BTRBR -#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ -#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ -#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ -#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ -#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ -#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ -#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ -#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ -#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ -#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ -#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ -#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Standard UART (STUART) */ -#define STUART STRBR -#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ -#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ -#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ -#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ -#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ -#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ -#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ -#define STLSR __REG(0x40700014) /* Line Status Register (read only) */ -#define STMSR __REG(0x40700018) /* Reserved */ -#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ -#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ -#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Hardware UART (HWUART) */ -#define HWUART HWRBR -#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ -#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ -#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ -#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ -#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ -#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ -#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ -#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ -#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ -#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ -#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ -#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ -#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ -#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ -#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -#define IER_DMAE (1 << 7) /* DMA Requests Enable */ -#define IER_UUE (1 << 6) /* UART Unit Enable */ -#define IER_NRZE (1 << 5) /* NRZ coding Enable */ -#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ -#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ -#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ -#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ -#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ - -#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ -#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ -#define IIR_TOD (1 << 3) /* Time Out Detected */ -#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ -#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ -#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ - -#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ -#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ -#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ -#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ -#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ -#define FCR_ITL_1 (0) -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ -#define LCR_SB (1 << 6) /* Set Break */ -#define LCR_STKYP (1 << 5) /* Sticky Parity */ -#define LCR_EPS (1 << 4) /* Even Parity Select */ -#define LCR_PEN (1 << 3) /* Parity Enable */ -#define LCR_STB (1 << 2) /* Stop Bit */ -#define LCR_WLS1 (1 << 1) /* Word Length Select */ -#define LCR_WLS0 (1 << 0) /* Word Length Select */ - -#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ -#define LSR_TEMT (1 << 6) /* Transmitter Empty */ -#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ -#define LSR_BI (1 << 4) /* Break Interrupt */ -#define LSR_FE (1 << 3) /* Framing Error */ -#define LSR_PE (1 << 2) /* Parity Error */ -#define LSR_OE (1 << 1) /* Overrun Error */ -#define LSR_DR (1 << 0) /* Data Ready */ - -#define MCR_LOOP (1 << 4) -#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ -#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ -#define MCR_RTS (1 << 1) /* Request to Send */ -#define MCR_DTR (1 << 0) /* Data Terminal Ready */ - -#define MSR_DCD (1 << 7) /* Data Carrier Detect */ -#define MSR_RI (1 << 6) /* Ring Indicator */ -#define MSR_DSR (1 << 5) /* Data Set Ready */ -#define MSR_CTS (1 << 4) /* Clear To Send */ -#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ -#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ -#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ -#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ - -/* - * IrSR (Infrared Selection Register) - */ -#define STISR_RXPL (1 << 4) /* Receive Data Polarity */ -#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ -#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ -#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ -#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ - - -/* - * I2C registers - moved into drivers/i2c/busses/i2c-pxa.c - */ - -/* - * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c - */ - -/* - * AC97 Controller registers - */ - -#define POCR __REG(0x40500000) /* PCM Out Control Register */ -#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define PICR __REG(0x40500004) /* PCM In Control Register */ -#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define MCCR __REG(0x40500008) /* Mic In Control Register */ -#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define GCR __REG(0x4050000C) /* Global Control Register */ -#ifdef CONFIG_PXA3xx -#define GCR_CLKBPB (1 << 31) /* Internal clock enable */ -#endif -#define GCR_nDMAEN (1 << 24) /* non DMA Enable */ -#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ -#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ -#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ -#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ -#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ -#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ -#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ -#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ -#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ -#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ - -#define POSR __REG(0x40500010) /* PCM Out Status Register */ -#define POSR_FIFOE (1 << 4) /* FIFO error */ -#define POSR_FSR (1 << 2) /* FIFO Service Request */ - -#define PISR __REG(0x40500014) /* PCM In Status Register */ -#define PISR_FIFOE (1 << 4) /* FIFO error */ -#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ -#define PISR_FSR (1 << 2) /* FIFO Service Request */ - -#define MCSR __REG(0x40500018) /* Mic In Status Register */ -#define MCSR_FIFOE (1 << 4) /* FIFO error */ -#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ -#define MCSR_FSR (1 << 2) /* FIFO Service Request */ - -#define GSR __REG(0x4050001C) /* Global Status Register */ -#define GSR_CDONE (1 << 19) /* Command Done */ -#define GSR_SDONE (1 << 18) /* Status Done */ -#define GSR_RDCS (1 << 15) /* Read Completion Status */ -#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ -#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ -#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ -#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ -#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ -#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ -#define GSR_PCR (1 << 8) /* Primary Codec Ready */ -#define GSR_MCINT (1 << 7) /* Mic In Interrupt */ -#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ -#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ -#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ -#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ -#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ -#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ - -#define CAR __REG(0x40500020) /* CODEC Access Register */ -#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ - -#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ -#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ - -#define MOCR __REG(0x40500100) /* Modem Out Control Register */ -#define MOCR_FEIE (1 << 3) /* FIFO Error */ -#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define MICR __REG(0x40500108) /* Modem In Control Register */ -#define MICR_FEIE (1 << 3) /* FIFO Error */ -#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define MOSR __REG(0x40500110) /* Modem Out Status Register */ -#define MOSR_FIFOE (1 << 4) /* FIFO error */ -#define MOSR_FSR (1 << 2) /* FIFO Service Request */ - -#define MISR __REG(0x40500118) /* Modem In Status Register */ -#define MISR_FIFOE (1 << 4) /* FIFO error */ -#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ -#define MISR_FSR (1 << 2) /* FIFO Service Request */ - -#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ - -#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ -#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ -#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ -#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ - - -/* - * Fast Infrared Communication Port - */ - -#define FICP __REG(0x40800000) /* Start of FICP area */ -#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ -#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ -#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ -#define ICDR __REG(0x4080000c) /* ICP Data Register */ -#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ -#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ - -#define ICCR0_AME (1 << 7) /* Address match enable */ -#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ -#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ -#define ICCR0_RXE (1 << 4) /* Receive enable */ -#define ICCR0_TXE (1 << 3) /* Transmit enable */ -#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ -#define ICCR0_LBM (1 << 1) /* Loopback mode */ -#define ICCR0_ITR (1 << 0) /* IrDA transmission */ - -#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ -#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ -#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ -#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ -#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ -#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ - -#ifdef CONFIG_PXA27x -#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ -#endif -#define ICSR0_FRE (1 << 5) /* Framing error */ -#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ -#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ -#define ICSR0_RAB (1 << 2) /* Receiver abort */ -#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ -#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ - -#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ -#define ICSR1_CRE (1 << 5) /* CRC error */ -#define ICSR1_EOF (1 << 4) /* End of frame */ -#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ -#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ -#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ -#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ - - /* * Real Time Clock */ @@ -463,19 +172,6 @@ /* - * Pulse Width Modulator - */ - -#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */ -#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */ -#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */ - -#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */ -#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */ -#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */ - - -/* * Interrupt Controller */ @@ -496,19 +192,6 @@ * General Purpose I/O */ -#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) -#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) -#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) -#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) - -#define GPLR_OFFSET 0x00 -#define GPDR_OFFSET 0x0C -#define GPSR_OFFSET 0x18 -#define GPCR_OFFSET 0x24 -#define GRER_OFFSET 0x30 -#define GFER_OFFSET 0x3C -#define GEDR_OFFSET 0x48 - #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ @@ -558,10 +241,6 @@ #define GPIO_bit(x) (1 << ((x) & 0x1f)) -#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) - -/* Interrupt Controller */ - #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) @@ -580,189 +259,5 @@ #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) -#else - -#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) -#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) -#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) -#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) -#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) -#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) -#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) -#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) - -#endif - -/* - * Power Manager - see pxa2xx-regs.h - */ - -/* - * SSP Serial Port Registers - see arch/arm/mach-pxa/include/mach/regs-ssp.h - */ - -/* - * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h - */ - -/* - * Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h - */ - -#ifdef CONFIG_PXA27x - -/* Camera Interface */ -#define CICR0 __REG(0x50000000) -#define CICR1 __REG(0x50000004) -#define CICR2 __REG(0x50000008) -#define CICR3 __REG(0x5000000C) -#define CICR4 __REG(0x50000010) -#define CISR __REG(0x50000014) -#define CIFR __REG(0x50000018) -#define CITOR __REG(0x5000001C) -#define CIBR0 __REG(0x50000028) -#define CIBR1 __REG(0x50000030) -#define CIBR2 __REG(0x50000038) - -#define CICR0_DMAEN (1 << 31) /* DMA request enable */ -#define CICR0_PAR_EN (1 << 30) /* Parity enable */ -#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ -#define CICR0_ENB (1 << 28) /* Camera interface enable */ -#define CICR0_DIS (1 << 27) /* Camera interface disable */ -#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ -#define CICR0_TOM (1 << 9) /* Time-out mask */ -#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ -#define CICR0_FEM (1 << 7) /* FIFO-empty mask */ -#define CICR0_EOLM (1 << 6) /* End-of-line mask */ -#define CICR0_PERRM (1 << 5) /* Parity-error mask */ -#define CICR0_QDM (1 << 4) /* Quick-disable mask */ -#define CICR0_CDM (1 << 3) /* Disable-done mask */ -#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ -#define CICR0_EOFM (1 << 1) /* End-of-frame mask */ -#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ - -#define CICR1_TBIT (1 << 31) /* Transparency bit */ -#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ -#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ -#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ -#define CICR1_RGB_F (1 << 11) /* RGB format */ -#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ -#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ -#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ -#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ -#define CICR1_DW (0x7 << 0) /* Data width mask */ - -#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock - wait count mask */ -#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock - wait count mask */ -#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ -#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock - wait count mask */ -#define CICR2_FSW (0x7 << 0) /* Frame stabilization - wait count mask */ - -#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock - wait count mask */ -#define CICR3_EFW (0xff << 16) /* End-of-frame line clock - wait count mask */ -#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ -#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock - wait count mask */ -#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ - -#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ -#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ -#define CICR4_PCP (1 << 22) /* Pixel clock polarity */ -#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ -#define CICR4_VSP (1 << 20) /* Vertical sync polarity */ -#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ -#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ -#define CICR4_DIV (0xff << 0) /* Clock divisor mask */ - -#define CISR_FTO (1 << 15) /* FIFO time-out */ -#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ -#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ -#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ -#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ -#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ -#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ -#define CISR_EOL (1 << 8) /* End of line */ -#define CISR_PAR_ERR (1 << 7) /* Parity error */ -#define CISR_CQD (1 << 6) /* Camera interface quick disable */ -#define CISR_CDD (1 << 5) /* Camera interface disable done */ -#define CISR_SOF (1 << 4) /* Start of frame */ -#define CISR_EOF (1 << 3) /* End of frame */ -#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ -#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ -#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ - -#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ -#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ -#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ -#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ -#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ -#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ -#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ -#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ - -#define SRAM_SIZE 0x40000 /* 4x64K */ - -#define SRAM_MEM_PHYS 0x5C000000 - -#define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */ -#define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */ - -#define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */ -#define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */ -#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */ -#define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */ - -#define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */ -#define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */ -#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */ -#define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */ - -#define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */ -#define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */ -#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */ -#define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */ - -#define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */ -#define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */ -#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */ -#define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */ - -#define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */ -#define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */ -#define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */ -#define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */ - -#define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */ - -#define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */ -#define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */ -#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */ - -#define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */ -#define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */ -#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */ - -#define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */ -#define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */ -#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */ - -#define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */ -#define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */ -#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */ - -#endif - -/* PWRMODE register M field values */ - -#define PWRMODE_IDLE 0x1 -#define PWRMODE_STANDBY 0x2 -#define PWRMODE_SLEEP 0x3 -#define PWRMODE_DEEPSLEEP 0x7 #endif diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h index 6ef1dd0..d83393e 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h @@ -365,4 +365,9 @@ #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) +/* + * Handy routine to set GPIO alternate functions + */ +extern int pxa_gpio_mode( int gpio_mode ); + #endif /* __ASM_ARCH_PXA2XX_GPIO_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index 806ecfe..77102d6 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h @@ -49,6 +49,11 @@ #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ +#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ +#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ +#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ +#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ + #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ @@ -243,4 +248,11 @@ #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ +/* PWRMODE register M field values */ + +#define PWRMODE_IDLE 0x1 +#define PWRMODE_STANDBY 0x2 +#define PWRMODE_SLEEP 0x3 +#define PWRMODE_DEEPSLEEP 0x7 + #endif diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h index cbda4d3..6932720 100644 --- a/arch/arm/mach-pxa/include/mach/pxafb.h +++ b/arch/arm/mach-pxa/include/mach/pxafb.h @@ -48,6 +48,7 @@ #define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN) #define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN) #define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN) +#define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT) #define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT) #define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT) #define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL) @@ -94,6 +95,10 @@ struct pxafb_mode_info { * in pxa27x and pxa3xx, initialize them to the same value or * the larger one will be used * 3. same to {rd,wr}_pulse_width + * + * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity + * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0 + * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD */ unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */ unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */ @@ -108,6 +113,7 @@ struct pxafb_mach_info { unsigned int num_modes; unsigned int lcd_conn; + unsigned long video_mem_size; u_int fixed_modes:1, cmap_inverse:1, diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/mach-pxa/include/mach/regs-ac97.h new file mode 100644 index 0000000..e41b9d2 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-ac97.h @@ -0,0 +1,99 @@ +#ifndef __ASM_ARCH_REGS_AC97_H +#define __ASM_ARCH_REGS_AC97_H + +/* + * AC97 Controller registers + */ + +#define POCR __REG(0x40500000) /* PCM Out Control Register */ +#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define PICR __REG(0x40500004) /* PCM In Control Register */ +#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MCCR __REG(0x40500008) /* Mic In Control Register */ +#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define GCR __REG(0x4050000C) /* Global Control Register */ +#ifdef CONFIG_PXA3xx +#define GCR_CLKBPB (1 << 31) /* Internal clock enable */ +#endif +#define GCR_nDMAEN (1 << 24) /* non DMA Enable */ +#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ +#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ +#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ +#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ +#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ +#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ +#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ +#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ +#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ +#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ + +#define POSR __REG(0x40500010) /* PCM Out Status Register */ +#define POSR_FIFOE (1 << 4) /* FIFO error */ +#define POSR_FSR (1 << 2) /* FIFO Service Request */ + +#define PISR __REG(0x40500014) /* PCM In Status Register */ +#define PISR_FIFOE (1 << 4) /* FIFO error */ +#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define PISR_FSR (1 << 2) /* FIFO Service Request */ + +#define MCSR __REG(0x40500018) /* Mic In Status Register */ +#define MCSR_FIFOE (1 << 4) /* FIFO error */ +#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define MCSR_FSR (1 << 2) /* FIFO Service Request */ + +#define GSR __REG(0x4050001C) /* Global Status Register */ +#define GSR_CDONE (1 << 19) /* Command Done */ +#define GSR_SDONE (1 << 18) /* Status Done */ +#define GSR_RDCS (1 << 15) /* Read Completion Status */ +#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ +#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ +#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ +#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ +#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ +#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ +#define GSR_PCR (1 << 8) /* Primary Codec Ready */ +#define GSR_MCINT (1 << 7) /* Mic In Interrupt */ +#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ +#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ +#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ +#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ +#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ +#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ + +#define CAR __REG(0x40500020) /* CODEC Access Register */ +#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ + +#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ +#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ + +#define MOCR __REG(0x40500100) /* Modem Out Control Register */ +#define MOCR_FEIE (1 << 3) /* FIFO Error */ +#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MICR __REG(0x40500108) /* Modem In Control Register */ +#define MICR_FEIE (1 << 3) /* FIFO Error */ +#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MOSR __REG(0x40500110) /* Modem Out Status Register */ +#define MOSR_FIFOE (1 << 4) /* FIFO error */ +#define MOSR_FSR (1 << 2) /* FIFO Service Request */ + +#define MISR __REG(0x40500118) /* Modem In Status Register */ +#define MISR_FIFOE (1 << 4) /* FIFO error */ +#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define MISR_FSR (1 << 2) /* FIFO Service Request */ + +#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ + +#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ +#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ +#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ +#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ + +#endif /* __ASM_ARCH_REGS_AC97_H */ diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h index c689c4e..f82dcea 100644 --- a/arch/arm/mach-pxa/include/mach/regs-lcd.h +++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h @@ -12,27 +12,29 @@ #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ #define LCCR4 (0x010) /* LCD Controller Control Register 4 */ #define LCCR5 (0x014) /* LCD Controller Control Register 5 */ -#define DFBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ -#define DFBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ -#define LCSR (0x038) /* LCD Controller Status Register */ +#define LCSR (0x038) /* LCD Controller Status Register 0 */ +#define LCSR1 (0x034) /* LCD Controller Status Register 1 */ #define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ #define TMEDRGBR (0x040) /* TMED RGB Seed Register */ #define TMEDCR (0x044) /* TMED Control Register */ +#define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ +#define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ +#define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */ +#define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */ +#define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */ +#define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ +#define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */ + +#define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */ +#define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */ +#define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */ +#define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */ + #define CMDCR (0x100) /* Command Control Register */ #define PRSR (0x104) /* Panel Read Status Register */ -#define LCCR3_1BPP (0 << 24) -#define LCCR3_2BPP (1 << 24) -#define LCCR3_4BPP (2 << 24) -#define LCCR3_8BPP (3 << 24) -#define LCCR3_16BPP (4 << 24) -#define LCCR3_18BPP (5 << 24) -#define LCCR3_18BPP_P (6 << 24) -#define LCCR3_19BPP (7 << 24) -#define LCCR3_19BPP_P (1 << 29) -#define LCCR3_24BPP ((1 << 29) | (1 << 24)) -#define LCCR3_25BPP ((1 << 29) | (2 << 24)) +#define LCCR3_BPP(x) ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0)) #define LCCR3_PDFOR_0 (0 << 30) #define LCCR3_PDFOR_1 (1 << 30) @@ -42,19 +44,16 @@ #define LCCR4_PAL_FOR_0 (0 << 15) #define LCCR4_PAL_FOR_1 (1 << 15) #define LCCR4_PAL_FOR_2 (2 << 15) +#define LCCR4_PAL_FOR_3 (3 << 15) #define LCCR4_PAL_FOR_MASK (3 << 15) #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ -#define FSADR0 (0x204) /* DMA Channel 0 Frame Source Address Register */ -#define FIDR0 (0x208) /* DMA Channel 0 Frame ID Register */ -#define LDCMD0 (0x20C) /* DMA Channel 0 Command Register */ #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ -#define FSADR1 (0x214) /* DMA Channel 1 Frame Source Address Register */ -#define FIDR1 (0x218) /* DMA Channel 1 Frame ID Register */ -#define LDCMD1 (0x21C) /* DMA Channel 1 Command Register */ +#define FDADR2 (0x220) /* DMA Channel 2 Frame Descriptor Address Register */ +#define FDADR3 (0x230) /* DMA Channel 3 Frame Descriptor Address Register */ +#define FDADR4 (0x240) /* DMA Channel 4 Frame Descriptor Address Register */ +#define FDADR5 (0x250) /* DMA Channel 5 Frame Descriptor Address Register */ #define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ -#define FSADR6 (0x264) /* DMA Channel 6 Frame Source Address Register */ -#define FIDR6 (0x268) /* DMA Channel 6 Frame ID Register */ #define LCCR0_ENB (1 << 0) /* LCD Controller enable */ #define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ @@ -126,9 +125,6 @@ #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ #define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD))) -#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ -#define LCCR3_Bpp(Bpp) (((Bpp) << FShft (LCCR3_BPP))) - #define LCCR3_ACB Fld (8, 8) /* AC Bias */ #define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB))) @@ -157,8 +153,22 @@ #define LCSR_RD_ST (1 << 11) /* read status */ #define LCSR_CMD_INT (1 << 12) /* command interrupt */ +#define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */ +#define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */ +#define LCSR1_EOF(x) (1 << ((x) + 7)) /* End of Frame Status */ +#define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */ + #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ +/* overlay control registers */ +#define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */ +#define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */ +#define OVLxC1_BPP(x) (((x) & 0xf) << 20) /* Bits Per Pixel */ +#define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */ +#define OVLxC2_XPOS(x) (((x) & 0x3ff) << 0) /* Horizontal Position */ +#define OVLxC2_YPOS(x) (((x) & 0x3ff) << 10) /* Vertical Position */ +#define OVL2C2_PFOR(x) (((x) & 0x7) << 20) /* Pixel Format */ + /* smartpanel related */ #define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ #define PRSR_A0 (1 << 8) /* Read Data Source */ @@ -177,4 +187,11 @@ #define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff)) #define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff)) + +/* SMART_DELAY() is introduced for software controlled delay primitive which + * can be inserted between command sequences, unused command 0x6 is used here + * and delay ranges from 0ms ~ 255ms + */ +#define SMART_CMD_DELAY (0x6 << 9) +#define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff)) #endif /* __ASM_ARCH_REGS_LCD_H */ diff --git a/arch/arm/mach-pxa/include/mach/regs-uart.h b/arch/arm/mach-pxa/include/mach/regs-uart.h new file mode 100644 index 0000000..55aeb7f --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-uart.h @@ -0,0 +1,143 @@ +#ifndef __ASM_ARCH_REGS_UART_H +#define __ASM_ARCH_REGS_UART_H + +/* + * UARTs + */ + +/* Full Function UART (FFUART) */ +#define FFUART FFRBR +#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ +#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ +#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ +#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ +#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ +#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ +#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ +#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ +#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ +#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ +#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ +#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Bluetooth UART (BTUART) */ +#define BTUART BTRBR +#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ +#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ +#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ +#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ +#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ +#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ +#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ +#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ +#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ +#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ +#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ +#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Standard UART (STUART) */ +#define STUART STRBR +#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ +#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ +#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ +#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ +#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ +#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ +#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ +#define STLSR __REG(0x40700014) /* Line Status Register (read only) */ +#define STMSR __REG(0x40700018) /* Reserved */ +#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ +#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ +#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +/* Hardware UART (HWUART) */ +#define HWUART HWRBR +#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ +#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ +#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ +#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ +#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ +#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ +#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ +#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ +#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ +#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ +#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ +#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ +#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ +#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ +#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ + +#define IER_DMAE (1 << 7) /* DMA Requests Enable */ +#define IER_UUE (1 << 6) /* UART Unit Enable */ +#define IER_NRZE (1 << 5) /* NRZ coding Enable */ +#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ +#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ +#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ +#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ +#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ + +#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ +#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ +#define IIR_TOD (1 << 3) /* Time Out Detected */ +#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ +#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ +#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ + +#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ +#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ +#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ +#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ +#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ +#define FCR_ITL_1 (0) +#define FCR_ITL_8 (FCR_ITL1) +#define FCR_ITL_16 (FCR_ITL2) +#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) + +#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ +#define LCR_SB (1 << 6) /* Set Break */ +#define LCR_STKYP (1 << 5) /* Sticky Parity */ +#define LCR_EPS (1 << 4) /* Even Parity Select */ +#define LCR_PEN (1 << 3) /* Parity Enable */ +#define LCR_STB (1 << 2) /* Stop Bit */ +#define LCR_WLS1 (1 << 1) /* Word Length Select */ +#define LCR_WLS0 (1 << 0) /* Word Length Select */ + +#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ +#define LSR_TEMT (1 << 6) /* Transmitter Empty */ +#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ +#define LSR_BI (1 << 4) /* Break Interrupt */ +#define LSR_FE (1 << 3) /* Framing Error */ +#define LSR_PE (1 << 2) /* Parity Error */ +#define LSR_OE (1 << 1) /* Overrun Error */ +#define LSR_DR (1 << 0) /* Data Ready */ + +#define MCR_LOOP (1 << 4) +#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ +#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ +#define MCR_RTS (1 << 1) /* Request to Send */ +#define MCR_DTR (1 << 0) /* Data Terminal Ready */ + +#define MSR_DCD (1 << 7) /* Data Carrier Detect */ +#define MSR_RI (1 << 6) /* Ring Indicator */ +#define MSR_DSR (1 << 5) /* Data Set Ready */ +#define MSR_CTS (1 << 4) /* Clear To Send */ +#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ +#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ +#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ +#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ + +/* + * IrSR (Infrared Selection Register) + */ +#define STISR_RXPL (1 << 4) /* Receive Data Polarity */ +#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ +#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ +#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ +#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ + +#endif /* __ASM_ARCH_REGS_UART_H */ diff --git a/arch/arm/mach-pxa/include/mach/timex.h b/arch/arm/mach-pxa/include/mach/timex.h index b05fc66..af6760a 100644 --- a/arch/arm/mach-pxa/include/mach/timex.h +++ b/arch/arm/mach-pxa/include/mach/timex.h @@ -10,6 +10,14 @@ * published by the Free Software Foundation. */ +/* Various drivers are still using the constant of CLOCK_TICK_RATE, for + * those drivers to at least work, the definition is provided here. + * + * NOTE: this is no longer accurate when multiple processors and boards + * are selected, newer drivers should not depend on this any more. Use + * either the clocksource/clockevent or get this at run-time by calling + * get_clock_tick_rate() (as defined in generic.c). + */ #if defined(CONFIG_PXA25x) /* PXA250/210 timer base */ diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h index 21e3e89..f4b029c 100644 --- a/arch/arm/mach-pxa/include/mach/uncompress.h +++ b/arch/arm/mach-pxa/include/mach/uncompress.h @@ -10,7 +10,7 @@ */ #include <linux/serial_reg.h> -#include <mach/pxa-regs.h> +#include <mach/regs-uart.h> #include <asm/mach-types.h> #define __REG(x) ((volatile unsigned long *)x) @@ -35,7 +35,7 @@ static inline void flush(void) static inline void arch_decomp_setup(void) { - if (machine_is_littleton()) + if (machine_is_littleton() || machine_is_intelmote2()) UART = STUART; } diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index b4d00ab..31da7f3 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -20,8 +20,13 @@ #include <linux/delay.h> #include <linux/platform_device.h> #include <linux/clk.h> +#include <linux/gpio.h> #include <linux/spi/spi.h> #include <linux/smc91x.h> +#include <linux/i2c.h> +#include <linux/leds.h> +#include <linux/mfd/da903x.h> +#include <linux/i2c/max732x.h> #include <asm/types.h> #include <asm/setup.h> @@ -36,10 +41,10 @@ #include <mach/pxa-regs.h> #include <mach/mfp-pxa300.h> -#include <mach/gpio.h> #include <mach/pxafb.h> #include <mach/ssp.h> #include <mach/pxa2xx_spi.h> +#include <mach/i2c.h> #include <mach/pxa27x_keypad.h> #include <mach/pxa3xx_nand.h> #include <mach/littleton.h> @@ -314,6 +319,73 @@ static void __init littleton_init_nand(void) static inline void littleton_init_nand(void) {} #endif /* CONFIG_MTD_NAND_PXA3xx || CONFIG_MTD_NAND_PXA3xx_MODULE */ +#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE) +static struct led_info littleton_da9034_leds[] = { + [0] = { + .name = "littleton:keypad1", + .flags = DA9034_LED_RAMP, + }, + [1] = { + .name = "littleton:keypad2", + .flags = DA9034_LED_RAMP, + }, + [2] = { + .name = "littleton:vibra", + .flags = 0, + }, +}; + +static struct da903x_subdev_info littleton_da9034_subdevs[] = { + { + .name = "da903x-led", + .id = DA9034_ID_LED_1, + .platform_data = &littleton_da9034_leds[0], + }, { + .name = "da903x-led", + .id = DA9034_ID_LED_2, + .platform_data = &littleton_da9034_leds[1], + }, { + .name = "da903x-led", + .id = DA9034_ID_VIBRA, + .platform_data = &littleton_da9034_leds[2], + }, { + .name = "da903x-backlight", + .id = DA9034_ID_WLED, + }, +}; + +static struct da903x_platform_data littleton_da9034_info = { + .num_subdevs = ARRAY_SIZE(littleton_da9034_subdevs), + .subdevs = littleton_da9034_subdevs, +}; + +static struct max732x_platform_data littleton_max7320_info = { + .gpio_base = EXT0_GPIO_BASE, +}; + +static struct i2c_board_info littleton_i2c_info[] = { + [0] = { + .type = "da9034", + .addr = 0x34, + .platform_data = &littleton_da9034_info, + .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO18)), + }, + [1] = { + .type = "max7320", + .addr = 0x50, + .platform_data = &littleton_max7320_info, + }, +}; + +static void __init littleton_init_i2c(void) +{ + pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(littleton_i2c_info)); +} +#else +static inline void littleton_init_i2c(void) {} +#endif /* CONFIG_I2C_PXA || CONFIG_I2C_PXA_MODULE */ + static void __init littleton_init(void) { /* initialize MFP configurations */ @@ -326,6 +398,7 @@ static void __init littleton_init(void) platform_device_register(&smc91x_device); littleton_init_spi(); + littleton_init_i2c(); littleton_init_lcd(); littleton_init_keypad(); littleton_init_nand(); diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 519138b..21b821e 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -123,6 +123,10 @@ static unsigned long magician_pin_config[] __initdata = { GPIO107_GPIO, /* DS1WM_IRQ */ GPIO108_GPIO, /* GSM_READY */ GPIO115_GPIO, /* nPEN_IRQ */ + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, }; /* @@ -332,8 +336,7 @@ static struct pxafb_mach_info toppoly_info = { .modes = toppoly_modes, .num_modes = 1, .fixed_modes = 1, - .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, - .lccr3 = LCCR3_PixRsEdg, + .lcd_conn = LCD_COLOR_TFT_16BPP, .pxafb_lcd_power = toppoly_lcd_power, }; @@ -341,8 +344,8 @@ static struct pxafb_mach_info samsung_info = { .modes = samsung_modes, .num_modes = 1, .fixed_modes = 1, - .lccr0 = LCCR0_LDDALT | LCCR0_Color | LCCR0_Sngl | LCCR0_Act, - .lccr3 = LCCR3_PixFlEdg, + .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |\ + LCD_ALTERNATE_MAPPING, .pxafb_lcd_power = samsung_lcd_power, }; diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index f2c7ad8..5f22496 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -128,6 +128,10 @@ static unsigned long mainstone_pin_config[] = { GPIO108_KP_MKOUT_5, GPIO96_KP_MKOUT_6, + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + /* GPIO */ GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, }; diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 2061c00..33626de 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -38,12 +38,13 @@ struct gpio_desc { unsigned valid : 1; unsigned can_wakeup : 1; unsigned keypad_gpio : 1; + unsigned dir_inverted : 1; unsigned int mask; /* bit mask in PWER or PKWR */ + unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */ unsigned long config; }; static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1]; -static int gpio_nr; static unsigned long gpdr_lpm[4]; @@ -54,7 +55,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */ int shft = (gpio & 0xf) << 1; int fn = MFP_AF(c); - int dir = c & MFP_DIR_OUT; + int is_out = (c & MFP_DIR_OUT) ? 1 : 0; if (fn > 3) return -EINVAL; @@ -68,7 +69,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) else GAFR_U(bank) = gafr; - if (dir == MFP_DIR_OUT) + if (is_out ^ gpio_desc[gpio].dir_inverted) GPDR(gpio) |= mask; else GPDR(gpio) &= ~mask; @@ -77,11 +78,11 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) switch (c & MFP_LPM_STATE_MASK) { case MFP_LPM_DRIVE_HIGH: PGSR(bank) |= mask; - dir = MFP_DIR_OUT; + is_out = 1; break; case MFP_LPM_DRIVE_LOW: PGSR(bank) &= ~mask; - dir = MFP_DIR_OUT; + is_out = 1; break; case MFP_LPM_DEFAULT: break; @@ -92,7 +93,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) break; } - if (dir == MFP_DIR_OUT) + if (is_out ^ gpio_desc[gpio].dir_inverted) gpdr_lpm[bank] |= mask; else gpdr_lpm[bank] &= ~mask; @@ -106,7 +107,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c) return -EINVAL; } - if ((c & MFP_LPM_CAN_WAKEUP) && (dir == MFP_DIR_OUT)) { + if ((c & MFP_LPM_CAN_WAKEUP) && is_out) { pr_warning("%s: output GPIO%d unable to wakeup\n", __func__, gpio); return -EINVAL; @@ -169,7 +170,7 @@ void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm) int gpio_set_wake(unsigned int gpio, unsigned int on) { struct gpio_desc *d; - unsigned long c; + unsigned long c, mux_taken; if (gpio > mfp_to_gpio(MFP_PIN_GPIO127)) return -EINVAL; @@ -183,9 +184,13 @@ int gpio_set_wake(unsigned int gpio, unsigned int on) if (d->keypad_gpio) return -EINVAL; + mux_taken = (PWER & d->mux_mask) & (~d->mask); + if (on && mux_taken) + return -EBUSY; + if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) { if (on) { - PWER |= d->mask; + PWER = (PWER & ~d->mux_mask) | d->mask; if (c & MFP_LPM_EDGE_RISE) PRER |= d->mask; @@ -210,7 +215,7 @@ static void __init pxa25x_mfp_init(void) { int i; - for (i = 0; i <= 84; i++) + for (i = 0; i <= pxa_last_gpio; i++) gpio_desc[i].valid = 1; for (i = 0; i <= 15; i++) { @@ -218,7 +223,11 @@ static void __init pxa25x_mfp_init(void) gpio_desc[i].mask = GPIO_bit(i); } - gpio_nr = 85; + /* PXA26x has additional 4 GPIOs (86/87/88/89) which has the + * direction bit inverted in GPDR2. See PXA26x DM 4.1.1. + */ + for (i = 86; i <= pxa_last_gpio; i++) + gpio_desc[i].dir_inverted = 1; } #else static inline void pxa25x_mfp_init(void) {} @@ -251,11 +260,27 @@ int keypad_set_wake(unsigned int on) return 0; } +#define PWER_WEMUX2_GPIO38 (1 << 16) +#define PWER_WEMUX2_GPIO53 (2 << 16) +#define PWER_WEMUX2_GPIO40 (3 << 16) +#define PWER_WEMUX2_GPIO36 (4 << 16) +#define PWER_WEMUX2_MASK (7 << 16) +#define PWER_WEMUX3_GPIO31 (1 << 19) +#define PWER_WEMUX3_GPIO113 (2 << 19) +#define PWER_WEMUX3_MASK (3 << 19) + +#define INIT_GPIO_DESC_MUXED(mux, gpio) \ +do { \ + gpio_desc[(gpio)].can_wakeup = 1; \ + gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio; \ + gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK; \ +} while (0) + static void __init pxa27x_mfp_init(void) { int i, gpio; - for (i = 0; i <= 120; i++) { + for (i = 0; i <= pxa_last_gpio; i++) { /* skip GPIO2, 5, 6, 7, 8, they are not * valid pins allow configuration */ @@ -286,7 +311,12 @@ static void __init pxa27x_mfp_init(void) gpio_desc[35].can_wakeup = 1; gpio_desc[35].mask = PWER_WE35; - gpio_nr = 121; + INIT_GPIO_DESC_MUXED(WEMUX3, 31); + INIT_GPIO_DESC_MUXED(WEMUX3, 113); + INIT_GPIO_DESC_MUXED(WEMUX2, 38); + INIT_GPIO_DESC_MUXED(WEMUX2, 53); + INIT_GPIO_DESC_MUXED(WEMUX2, 40); + INIT_GPIO_DESC_MUXED(WEMUX2, 36); } #else static inline void pxa27x_mfp_init(void) {} @@ -300,7 +330,7 @@ static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state) { int i; - for (i = 0; i <= gpio_to_bank(gpio_nr); i++) { + for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { saved_gafr[0][i] = GAFR_L(i); saved_gafr[1][i] = GAFR_U(i); @@ -315,7 +345,7 @@ static int pxa2xx_mfp_resume(struct sys_device *d) { int i; - for (i = 0; i <= gpio_to_bank(gpio_nr); i++) { + for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { GAFR_L(i) = saved_gafr[0][i]; GAFR_U(i) = saved_gafr[1][i]; GPDR(i * 32) = saved_gpdr[i]; @@ -348,7 +378,7 @@ static int __init pxa2xx_mfp_init(void) pxa27x_mfp_init(); /* initialize gafr_run[], pgsr_lpm[] from existing values */ - for (i = 0; i <= gpio_to_bank(gpio_nr); i++) + for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) gpdr_lpm[i] = GPDR(i * 32); return sysdev_class_register(&pxa2xx_mfp_sysclass); diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 782903f..2b427e0 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -34,7 +34,7 @@ #include <linux/irq.h> #include <linux/pda_power.h> #include <linux/power_supply.h> -#include <linux/wm97xx.h> +#include <linux/wm97xx_batt.h> #include <linux/mtd/physmap.h> #include <asm/mach-types.h> @@ -46,6 +46,9 @@ #include <mach/mmc.h> #include <mach/udc.h> #include <mach/pxa27x-udc.h> +#include <mach/i2c.h> +#include <mach/camera.h> +#include <media/soc_camera.h> #include <mach/mioa701.h> @@ -54,10 +57,11 @@ static unsigned long mioa701_pin_config[] = { /* Mio global */ - MIO_CFG_OUT(GPIO9_CHARGE_nEN, AF0, DRIVE_LOW), + MIO_CFG_OUT(GPIO9_CHARGE_EN, AF0, DRIVE_LOW), MIO_CFG_OUT(GPIO18_POWEROFF, AF0, DRIVE_LOW), MFP_CFG_OUT(GPIO3, AF0, DRIVE_HIGH), MFP_CFG_OUT(GPIO4, AF0, DRIVE_HIGH), + MIO_CFG_IN(GPIO80_MAYBE_CHARGE_VDROP, AF0), /* Backlight PWM 0 */ GPIO16_PWM0_OUT, @@ -74,7 +78,7 @@ static unsigned long mioa701_pin_config[] = { MIO_CFG_OUT(GPIO91_SDIO_EN, AF0, DRIVE_LOW), /* USB */ - MIO_CFG_IN(GPIO13_USB_DETECT, AF0), + MIO_CFG_IN(GPIO13_nUSB_DETECT, AF0), MIO_CFG_OUT(GPIO22_USB_ENABLE, AF0, DRIVE_LOW), /* LCD */ @@ -98,12 +102,29 @@ static unsigned long mioa701_pin_config[] = { GPIO75_LCD_LCLK, GPIO76_LCD_PCLK, + /* QCI */ + GPIO12_CIF_DD_7, + GPIO17_CIF_DD_6, + GPIO50_CIF_DD_3, + GPIO51_CIF_DD_2, + GPIO52_CIF_DD_4, + GPIO53_CIF_MCLK, + GPIO54_CIF_PCLK, + GPIO55_CIF_DD_1, + GPIO81_CIF_DD_0, + GPIO82_CIF_DD_5, + GPIO84_CIF_FV, + GPIO85_CIF_LV, + /* Bluetooth */ + MIO_CFG_IN(GPIO14_BT_nACTIVITY, AF0), GPIO44_BTUART_CTS, GPIO42_BTUART_RXD, GPIO45_BTUART_RTS, GPIO43_BTUART_TXD, MIO_CFG_OUT(GPIO83_BT_ON, AF0, DRIVE_LOW), + MIO_CFG_OUT(GPIO77_BT_UNKNOWN1, AF0, DRIVE_HIGH), + MIO_CFG_OUT(GPIO86_BT_MAYBE_nRESET, AF0, DRIVE_HIGH), /* GPS */ MIO_CFG_OUT(GPIO23_GPS_UNKNOWN1, AF0, DRIVE_LOW), @@ -151,16 +172,16 @@ static unsigned long mioa701_pin_config[] = { GPIO104_KP_MKOUT_1, GPIO105_KP_MKOUT_2, + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + /* Unknown */ - MFP_CFG_IN(GPIO14, AF0), MFP_CFG_IN(GPIO20, AF0), MFP_CFG_IN(GPIO21, AF0), MFP_CFG_IN(GPIO33, AF0), MFP_CFG_OUT(GPIO49, AF0, DRIVE_HIGH), MFP_CFG_OUT(GPIO57, AF0, DRIVE_HIGH), - MFP_CFG_OUT(GPIO77, AF0, DRIVE_HIGH), - MFP_CFG_IN(GPIO80, AF0), - MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH), MFP_CFG_IN(GPIO96, AF0), MFP_CFG_OUT(GPIO116, AF0, DRIVE_HIGH), }; @@ -407,7 +428,7 @@ static void udc_power_command(int cmd) static int is_usb_connected(void) { - return !!gpio_get_value(GPIO13_USB_DETECT); + return !gpio_get_value(GPIO13_nUSB_DETECT); } static struct pxa2xx_udc_mach_info mioa701_udc_info = { @@ -659,13 +680,19 @@ static char *supplicants[] = { "mioa701_battery" }; +static int is_ac_connected(void) +{ + return gpio_get_value(GPIO96_AC_DETECT); +} + static void mioa701_set_charge(int flags) { - gpio_set_value(GPIO9_CHARGE_nEN, !flags); + gpio_set_value(GPIO9_CHARGE_EN, (flags == PDA_POWER_CHARGE_USB)); } static struct pda_power_pdata power_pdata = { - .is_ac_online = is_usb_connected, + .is_ac_online = is_ac_connected, + .is_usb_online = is_usb_connected, .set_charge = mioa701_set_charge, .supplied_to = supplicants, .num_supplicants = ARRAY_SIZE(supplicants), @@ -674,8 +701,15 @@ static struct pda_power_pdata power_pdata = { static struct resource power_resources[] = { [0] = { .name = "ac", - .start = gpio_to_irq(GPIO13_USB_DETECT), - .end = gpio_to_irq(GPIO13_USB_DETECT), + .start = gpio_to_irq(GPIO96_AC_DETECT), + .end = gpio_to_irq(GPIO96_AC_DETECT), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | + IORESOURCE_IRQ_LOWEDGE, + }, + [1] = { + .name = "usb", + .start = gpio_to_irq(GPIO13_nUSB_DETECT), + .end = gpio_to_irq(GPIO13_nUSB_DETECT), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, }, @@ -691,120 +725,43 @@ static struct platform_device power_dev = { }, }; -#if defined(CONFIG_PDA_POWER) && defined(CONFIG_TOUCHSCREEN_WM97XX) -static struct wm97xx *battery_wm; - -static enum power_supply_property battery_props[] = { - POWER_SUPPLY_PROP_STATUS, - POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, - POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, - POWER_SUPPLY_PROP_VOLTAGE_NOW, - POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, /* Necessary for apm */ +static struct wm97xx_batt_info mioa701_battery_data = { + .batt_aux = WM97XX_AUX_ID1, + .temp_aux = -1, + .charge_gpio = -1, + .min_voltage = 0xc00, + .max_voltage = 0xfc0, + .batt_tech = POWER_SUPPLY_TECHNOLOGY_LION, + .batt_div = 1, + .batt_mult = 1, + .batt_name = "mioa701_battery", }; -static int get_battery_voltage(void) -{ - int adc = -1; - - if (battery_wm) - adc = wm97xx_read_aux_adc(battery_wm, WM97XX_AUX_ID1); - return adc; -} - -static int get_battery_status(struct power_supply *b) -{ - int status; - - if (is_usb_connected()) - status = POWER_SUPPLY_STATUS_CHARGING; - else - status = POWER_SUPPLY_STATUS_DISCHARGING; - - return status; -} - -static int get_property(struct power_supply *b, - enum power_supply_property psp, - union power_supply_propval *val) -{ - int rc = 0; - - switch (psp) { - case POWER_SUPPLY_PROP_STATUS: - val->intval = get_battery_status(b); - break; - case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: - val->intval = 0xfd0; - break; - case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: - val->intval = 0xc00; - break; - case POWER_SUPPLY_PROP_VOLTAGE_NOW: - val->intval = get_battery_voltage(); - break; - case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: - val->intval = 100; - break; - default: - val->intval = -1; - rc = -1; - } - - return rc; +/* + * Camera interface + */ +struct pxacamera_platform_data mioa701_pxacamera_platform_data = { + .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | + PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, + .mclk_10khz = 5000, }; -static struct power_supply battery_ps = { - .name = "mioa701_battery", - .type = POWER_SUPPLY_TYPE_BATTERY, - .get_property = get_property, - .properties = battery_props, - .num_properties = ARRAY_SIZE(battery_props), +static struct soc_camera_link iclink = { + .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */ }; -static int battery_probe(struct platform_device *pdev) -{ - struct wm97xx *wm = platform_get_drvdata(pdev); - int rc; - - battery_wm = wm; - - rc = power_supply_register(NULL, &battery_ps); - if (rc) - dev_err(&pdev->dev, - "Could not register mioa701 battery -> %d\n", rc); - return rc; -} - -static int battery_remove(struct platform_device *pdev) -{ - battery_wm = NULL; - return 0; -} - -static struct platform_driver mioa701_battery_driver = { - .driver = { - .name = "wm97xx-battery", +/* Board I2C devices. */ +static struct i2c_board_info __initdata mioa701_i2c_devices[] = { + { + /* Must initialize before the camera(s) */ + I2C_BOARD_INFO("mt9m111", 0x5d), + .platform_data = &iclink, }, - .probe = battery_probe, - .remove = battery_remove }; -static int __init mioa701_battery_init(void) -{ - int rc; - - rc = platform_driver_register(&mioa701_battery_driver); - if (rc) - printk(KERN_ERR "Could not register mioa701 battery driver\n"); - return rc; -} - -#else -static int __init mioa701_battery_init(void) -{ - return 0; -} -#endif +struct i2c_pxa_platform_data i2c_pdata = { + .fast_mode = 1, +}; /* * Mio global @@ -851,17 +808,17 @@ static void mioa701_machine_exit(void); static void mioa701_poweroff(void) { mioa701_machine_exit(); - gpio_set_value(GPIO18_POWEROFF, 1); + arm_machine_restart('s'); } static void mioa701_restart(char c) { mioa701_machine_exit(); - arm_machine_restart(c); + arm_machine_restart('s'); } struct gpio_ress global_gpios[] = { - MIO_GPIO_OUT(GPIO9_CHARGE_nEN, 1, "Charger enable"), + MIO_GPIO_OUT(GPIO9_CHARGE_EN, 1, "Charger enable"), MIO_GPIO_OUT(GPIO18_POWEROFF, 0, "Power Off"), MIO_GPIO_OUT(GPIO87_LCD_POWER, 0, "LCD Power") }; @@ -879,12 +836,16 @@ static void __init mioa701_machine_init(void) set_pxa_fb_info(&mioa701_pxafb_info); pxa_set_mci_info(&mioa701_mci_info); pxa_set_keypad_info(&mioa701_keypad_info); + wm97xx_bat_set_pdata(&mioa701_battery_data); udc_init(); pm_power_off = mioa701_poweroff; arm_pm_restart = mioa701_restart; platform_add_devices(devices, ARRAY_SIZE(devices)); gsm_init(); - mioa701_battery_init(); + + pxa_set_i2c_info(&i2c_pdata); + pxa_set_camera_info(&mioa701_pxacamera_platform_data); + i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices)); } static void mioa701_machine_exit(void) diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index b36cec5c..34841c7 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -55,6 +55,10 @@ static unsigned long pcm990_pin_config[] __initdata = { GPIO89_USBH1_PEN, /* PWM0 */ GPIO16_PWM0_OUT, + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, }; /* @@ -100,8 +104,7 @@ static struct pxafb_mode_info fb_info_sharp_lq084v1dg21 = { static struct pxafb_mach_info pcm990_fbinfo __initdata = { .modes = &fb_info_sharp_lq084v1dg21, .num_modes = 1, - .lccr0 = LCCR0_PAS, - .lccr3 = LCCR3_PCP, + .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, .pxafb_lcd_power = pcm990_lcd_power, }; #elif defined(CONFIG_PCM990_DISPLAY_NEC) @@ -123,8 +126,7 @@ struct pxafb_mode_info fb_info_nec_nl6448bc20_18d = { static struct pxafb_mach_info pcm990_fbinfo __initdata = { .modes = &fb_info_nec_nl6448bc20_18d, .num_modes = 1, - .lccr0 = LCCR0_Act, - .lccr3 = LCCR3_PixFlEdg, + .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, .pxafb_lcd_power = pcm990_lcd_power, }; #endif diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 2e3bd8b..ae88855 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -20,6 +20,7 @@ #include <linux/fb.h> #include <linux/pm.h> #include <linux/delay.h> +#include <linux/mtd/physmap.h> #include <linux/gpio.h> #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> @@ -413,9 +414,40 @@ static struct pxafb_mach_info poodle_fb_info = { .lcd_conn = LCD_COLOR_TFT_16BPP, }; +static struct mtd_partition sharpsl_rom_parts[] = { + { + .name ="Boot PROM Filesystem", + .offset = 0x00120000, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data sharpsl_rom_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(sharpsl_rom_parts), + .parts = sharpsl_rom_parts, +}; + +static struct resource sharpsl_rom_resources[] = { + { + .start = 0x00000000, + .end = 0x007fffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sharpsl_rom_device = { + .name = "physmap-flash", + .id = -1, + .resource = sharpsl_rom_resources, + .num_resources = ARRAY_SIZE(sharpsl_rom_resources), + .dev.platform_data = &sharpsl_rom_data, +}; + static struct platform_device *devices[] __initdata = { &poodle_locomo_device, &poodle_scoop_device, + &sharpsl_rom_device, }; static void poodle_poweroff(void) diff --git a/arch/arm/mach-pxa/pwm.c b/arch/arm/mach-pxa/pwm.c index 74e2ead..3ca7ffc6 100644 --- a/arch/arm/mach-pxa/pwm.c +++ b/arch/arm/mach-pxa/pwm.c @@ -173,7 +173,7 @@ static struct pwm_device *pwm_probe(struct platform_device *pdev, return ERR_PTR(-ENOMEM); } - pwm->clk = clk_get(&pdev->dev, "PWMCLK"); + pwm->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(pwm->clk)) { ret = PTR_ERR(pwm->clk); goto err_free; diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 25d17a1..6c57522 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -36,12 +36,6 @@ #include "devices.h" #include "clock.h" -int cpu_is_pxa26x(void) -{ - return cpu_is_pxa250() && ((BOOT_DEF & 0x8) == 0); -} -EXPORT_SYMBOL_GPL(cpu_is_pxa26x); - /* * Various clock factors driven by the CCCR register. */ @@ -167,36 +161,51 @@ static const struct clkops clk_pxa25x_gpio11_ops = { * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) */ -static struct clk pxa25x_hwuart_clk = - INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev) -; +static DEFINE_CKEN(pxa25x_hwuart, HWUART, 14745600, 1); + +static struct clk_lookup pxa25x_hwuart_clkreg = + INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL); /* * PXA 2xx clock declarations. */ -static struct clk pxa25x_clks[] = { - INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), - INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), - INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), - INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), - INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev), - INIT_CLK("GPIO11_CLK", &clk_pxa25x_gpio11_ops, 3686400, 0, NULL), - INIT_CLK("GPIO12_CLK", &clk_pxa25x_gpio12_ops, 32768, 0, NULL), - INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), - INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), - - INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev), - INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), - INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), - INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev), - INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev), - - INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), - - /* - INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), - */ - INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), +static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops); +static DEFINE_CKEN(pxa25x_ffuart, FFUART, 14745600, 1); +static DEFINE_CKEN(pxa25x_btuart, BTUART, 14745600, 1); +static DEFINE_CKEN(pxa25x_stuart, STUART, 14745600, 1); +static DEFINE_CKEN(pxa25x_usb, USB, 47923000, 5); +static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0); +static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0); +static DEFINE_CKEN(pxa25x_mmc, MMC, 19169000, 0); +static DEFINE_CKEN(pxa25x_i2c, I2C, 31949000, 0); +static DEFINE_CKEN(pxa25x_ssp, SSP, 3686400, 0); +static DEFINE_CKEN(pxa25x_nssp, NSSP, 3686400, 0); +static DEFINE_CKEN(pxa25x_assp, ASSP, 3686400, 0); +static DEFINE_CKEN(pxa25x_pwm0, PWM0, 3686400, 0); +static DEFINE_CKEN(pxa25x_pwm1, PWM1, 3686400, 0); +static DEFINE_CKEN(pxa25x_ac97, AC97, 24576000, 0); +static DEFINE_CKEN(pxa25x_i2s, I2S, 14745600, 0); +static DEFINE_CKEN(pxa25x_ficp, FICP, 47923000, 0); + +static struct clk_lookup pxa25x_clkregs[] = { + INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL), + INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL), + INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL), + INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL), + INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL), + INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL), + INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL), + INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL), + INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL), + INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"), + INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"), + INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"), + INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), + INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), }; #ifdef CONFIG_PM @@ -304,13 +313,21 @@ void __init pxa25x_init_irq(void) pxa_init_gpio(85, pxa25x_set_wake); } +#ifdef CONFIG_CPU_PXA26x +void __init pxa26x_init_irq(void) +{ + pxa_init_irq(32, pxa25x_set_wake); + pxa_init_gpio(90, pxa25x_set_wake); +} +#endif + static struct platform_device *pxa25x_devices[] __initdata = { &pxa25x_device_udc, &pxa_device_ffuart, &pxa_device_btuart, &pxa_device_stuart, &pxa_device_i2s, - &pxa_device_rtc, + &sa1100_device_rtc, &pxa25x_device_ssp, &pxa25x_device_nssp, &pxa25x_device_assp, @@ -336,7 +353,7 @@ static int __init pxa25x_init(void) reset_status = RCSR; - clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); + clks_register(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs)); if ((ret = pxa_init_dma(16))) return ret; @@ -356,8 +373,8 @@ static int __init pxa25x_init(void) } /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */ - if (cpu_is_pxa255() || cpu_is_pxa26x()) { - clks_register(&pxa25x_hwuart_clk, 1); + if (cpu_is_pxa255()) { + clks_register(&pxa25x_hwuart_clkreg, 1); ret = platform_device_register(&pxa_device_hwuart); } diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 3e4ab22..411bec5 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -144,40 +144,59 @@ static const struct clkops clk_pxa27x_lcd_ops = { .getrate = clk_pxa27x_lcd_getrate, }; -static struct clk pxa27x_clks[] = { - INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev), - INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL), - - INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), - INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), - INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL), - - INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev), - INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), - INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa27x_device_udc.dev), - INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev), - INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev), - - INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev), - INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), - INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), - - INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), - INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), - INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), - INIT_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev), - INIT_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev), - - INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), - INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL), - - /* - INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), - INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), - INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), - INIT_CKEN("IMCLK", IM, 0, 0, NULL), - INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL), - */ +static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops); +static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops); +static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1); +static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1); +static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1); +static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0); +static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0); +static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5); +static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0); +static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0); +static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0); +static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0); +static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0); +static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0); +static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0); +static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0); +static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0); +static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0); +static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0); +static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0); +static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0); +static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0); +static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0); +static DEFINE_CKEN(pxa27x_im, IM, 0, 0); +static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0); + +static struct clk_lookup pxa27x_clkregs[] = { + INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL), + INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL), + INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL), + INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL), + INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL), + INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"), + INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"), + INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL), + INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL), + INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL), + INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL), + INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL), + INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL), + INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL), + INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"), + INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"), + INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"), + INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"), + INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"), + INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), + INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), }; #ifdef CONFIG_PM @@ -313,38 +332,18 @@ static int pxa27x_set_wake(unsigned int irq, unsigned int on) void __init pxa27x_init_irq(void) { pxa_init_irq(34, pxa27x_set_wake); - pxa_init_gpio(128, pxa27x_set_wake); + pxa_init_gpio(121, pxa27x_set_wake); } /* * device registration specific to PXA27x. */ - -static struct resource i2c_power_resources[] = { - { - .start = 0x40f00180, - .end = 0x40f001a3, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PWRI2C, - .end = IRQ_PWRI2C, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa27x_device_i2c_power = { - .name = "pxa2xx-i2c", - .id = 1, - .resource = i2c_power_resources, - .num_resources = ARRAY_SIZE(i2c_power_resources), -}; - void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) { local_irq_disable(); PCFR |= PCFR_PI2CEN; local_irq_enable(); - pxa27x_device_i2c_power.dev.platform_data = info; + pxa_register_device(&pxa27x_device_i2c_power, info); } static struct platform_device *devices[] __initdata = { @@ -353,8 +352,8 @@ static struct platform_device *devices[] __initdata = { &pxa_device_btuart, &pxa_device_stuart, &pxa_device_i2s, + &sa1100_device_rtc, &pxa_device_rtc, - &pxa27x_device_i2c_power, &pxa27x_device_ssp1, &pxa27x_device_ssp2, &pxa27x_device_ssp3, @@ -380,7 +379,7 @@ static int __init pxa27x_init(void) reset_status = RCSR; - clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); + clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs)); if ((ret = pxa_init_dma(32))) return ret; diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c index 9adc7fc..f735e58 100644 --- a/arch/arm/mach-pxa/pxa300.c +++ b/arch/arm/mach-pxa/pxa300.c @@ -85,14 +85,16 @@ static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = { MFP_ADDR_END, }; -static struct clk common_clks[] = { - PXA3xx_CKEN("NANDCLK", NAND, 156000000, 0, &pxa3xx_device_nand.dev), +static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0); + +static struct clk_lookup common_clkregs[] = { + INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", "NANDCLK"), }; -static struct clk pxa310_clks[] = { -#ifdef CONFIG_CPU_PXA310 - PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev), -#endif +static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0); + +static struct clk_lookup pxa310_clkregs[] = { + INIT_CLKREG(&clk_pxa310_mmc3, "pxa2xx-mci.2", "MMCCLK"), }; static int __init pxa300_init(void) @@ -100,12 +102,12 @@ static int __init pxa300_init(void) if (cpu_is_pxa300() || cpu_is_pxa310()) { pxa3xx_init_mfp(); pxa3xx_mfp_init_addr(pxa300_mfp_addr_map); - clks_register(ARRAY_AND_SIZE(common_clks)); + clks_register(ARRAY_AND_SIZE(common_clkregs)); } if (cpu_is_pxa310()) { pxa3xx_mfp_init_addr(pxa310_mfp_addr_map); - clks_register(ARRAY_AND_SIZE(pxa310_clks)); + clks_register(ARRAY_AND_SIZE(pxa310_clkregs)); } return 0; diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c index 016eb18..effe408 100644 --- a/arch/arm/mach-pxa/pxa320.c +++ b/arch/arm/mach-pxa/pxa320.c @@ -80,8 +80,10 @@ static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = { MFP_ADDR_END, }; -static struct clk pxa320_clks[] = { - PXA3xx_CKEN("NANDCLK", NAND, 104000000, 0, &pxa3xx_device_nand.dev), +static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0); + +static struct clk_lookup pxa320_clkregs[] = { + INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", "NANDCLK"), }; static int __init pxa320_init(void) @@ -89,7 +91,7 @@ static int __init pxa320_init(void) if (cpu_is_pxa320()) { pxa3xx_init_mfp(); pxa3xx_mfp_init_addr(pxa320_mfp_addr_map); - clks_register(ARRAY_AND_SIZE(pxa320_clks)); + clks_register(ARRAY_AND_SIZE(pxa320_clkregs)); } return 0; diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index b3cd5d0..4908938 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -29,6 +29,7 @@ #include <mach/pm.h> #include <mach/dma.h> #include <mach/ssp.h> +#include <mach/i2c.h> #include "generic.h" #include "devices.h" @@ -216,43 +217,58 @@ static const struct clkops clk_dummy_ops = { .disable = clk_dummy_disable, }; -static struct clk pxa3xx_clks[] = { - { - .name = "CLK_POUT", - .ops = &clk_pout_ops, - .rate = 13000000, - .delay = 70, - }, - - /* Power I2C clock is always on */ - { - .name = "I2CCLK", - .ops = &clk_dummy_ops, - .dev = &pxa3xx_device_i2c_power.dev, - }, - - PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), - PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), - PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL), - - PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), - PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), - PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL), - - PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), - PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa27x_device_udc.dev), - PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), - PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), +static struct clk clk_pxa3xx_pout = { + .ops = &clk_pout_ops, + .rate = 13000000, + .delay = 70, +}; - PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), - PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), - PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), - PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), - PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev), - PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev), +static struct clk clk_dummy = { + .ops = &clk_dummy_ops, +}; - PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), - PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), +static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); +static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); +static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); +static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); +static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); +static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); +static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); +static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); +static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); +static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); +static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); +static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); +static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0); +static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0); +static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0); +static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); +static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); +static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); + +static struct clk_lookup pxa3xx_clkregs[] = { + INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), + /* Power I2C clock is always on */ + INIT_CLKREG(&clk_dummy, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL), + INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"), + INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"), + INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"), + INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), + INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), + INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), + INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), + INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), + INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL), + INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL), + INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL), + INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), + INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), + INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), }; #ifdef CONFIG_PM @@ -529,28 +545,9 @@ void __init pxa3xx_init_irq(void) * device registration specific to PXA3xx. */ -static struct resource i2c_power_resources[] = { - { - .start = 0x40f500c0, - .end = 0x40f500d3, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PWRI2C, - .end = IRQ_PWRI2C, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa3xx_device_i2c_power = { - .name = "pxa2xx-i2c", - .id = 1, - .resource = i2c_power_resources, - .num_resources = ARRAY_SIZE(i2c_power_resources), -}; - void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) { - pxa3xx_device_i2c_power.dev.platform_data = info; + pxa_register_device(&pxa3xx_device_i2c_power, info); } static struct platform_device *devices[] __initdata = { @@ -559,6 +556,7 @@ static struct platform_device *devices[] __initdata = { &pxa_device_btuart, &pxa_device_stuart, &pxa_device_i2s, + &sa1100_device_rtc, &pxa_device_rtc, &pxa27x_device_ssp1, &pxa27x_device_ssp2, @@ -566,7 +564,6 @@ static struct platform_device *devices[] __initdata = { &pxa3xx_device_ssp4, &pxa27x_device_pwm0, &pxa27x_device_pwm1, - &pxa3xx_device_i2c_power, }; static struct sys_device pxa3xx_sysdev[] = { @@ -595,7 +592,7 @@ static int __init pxa3xx_init(void) */ ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); - clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); + clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); if ((ret = pxa_init_dma(32))) return ret; diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index e7ea91c..5d02a73 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c @@ -17,19 +17,44 @@ #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/fb.h> +#include <linux/i2c.h> #include <linux/smc91x.h> +#include <linux/mfd/da903x.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/hardware.h> #include <mach/pxa3xx-regs.h> #include <mach/mfp-pxa930.h> +#include <mach/i2c.h> +#include <mach/regs-lcd.h> +#include <mach/pxafb.h> #include "devices.h" #include "generic.h" +#define GPIO_LCD_RESET (16) + /* SAAR MFP configurations */ static mfp_cfg_t saar_mfp_cfg[] __initdata = { + /* LCD */ + GPIO23_LCD_DD0, + GPIO24_LCD_DD1, + GPIO25_LCD_DD2, + GPIO26_LCD_DD3, + GPIO27_LCD_DD4, + GPIO28_LCD_DD5, + GPIO29_LCD_DD6, + GPIO44_LCD_DD7, + GPIO21_LCD_CS, + GPIO22_LCD_VSYNC, + GPIO17_LCD_FCLK_RD, + GPIO18_LCD_LCLK_A0, + GPIO19_LCD_PCLK_WR, + GPIO16_GPIO, /* LCD reset */ + /* Ethernet */ DF_nCS1_nCS3, GPIO97_GPIO, @@ -64,12 +89,408 @@ static struct platform_device smc91x_device = { }, }; +#if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULE) +static uint16_t lcd_power_on[] = { + /* single frame */ + SMART_CMD_NOOP, + SMART_CMD(0x00), + SMART_DELAY(0), + + SMART_CMD_NOOP, + SMART_CMD(0x00), + SMART_DELAY(0), + + SMART_CMD_NOOP, + SMART_CMD(0x00), + SMART_DELAY(0), + + SMART_CMD_NOOP, + SMART_CMD(0x00), + SMART_DELAY(10), + + /* calibration control */ + SMART_CMD(0x00), + SMART_CMD(0xA4), + SMART_DAT(0x80), + SMART_DAT(0x01), + SMART_DELAY(150), + + /*Power-On Init sequence*/ + SMART_CMD(0x00), /* output ctrl */ + SMART_CMD(0x01), + SMART_DAT(0x01), + SMART_DAT(0x00), + SMART_CMD(0x00), /* wave ctrl */ + SMART_CMD(0x02), + SMART_DAT(0x07), + SMART_DAT(0x00), + SMART_CMD(0x00), + SMART_CMD(0x03), /* entry mode */ + SMART_DAT(0xD0), + SMART_DAT(0x30), + SMART_CMD(0x00), + SMART_CMD(0x08), /* display ctrl 2 */ + SMART_DAT(0x08), + SMART_DAT(0x08), + SMART_CMD(0x00), + SMART_CMD(0x09), /* display ctrl 3 */ + SMART_DAT(0x04), + SMART_DAT(0x2F), + SMART_CMD(0x00), + SMART_CMD(0x0A), /* display ctrl 4 */ + SMART_DAT(0x00), + SMART_DAT(0x08), + SMART_CMD(0x00), + SMART_CMD(0x0D), /* Frame Marker position */ + SMART_DAT(0x00), + SMART_DAT(0x08), + SMART_CMD(0x00), + SMART_CMD(0x60), /* Driver output control */ + SMART_DAT(0x27), + SMART_DAT(0x00), + SMART_CMD(0x00), + SMART_CMD(0x61), /* Base image display control */ + SMART_DAT(0x00), + SMART_DAT(0x01), + SMART_CMD(0x00), + SMART_CMD(0x30), /* Y settings 30h-3Dh */ + SMART_DAT(0x07), + SMART_DAT(0x07), + SMART_CMD(0x00), + SMART_CMD(0x31), + SMART_DAT(0x00), + SMART_DAT(0x07), + SMART_CMD(0x00), + SMART_CMD(0x32), /* Timing(3), ASW HOLD=0.5CLK */ + SMART_DAT(0x04), + SMART_DAT(0x00), + SMART_CMD(0x00), + SMART_CMD(0x33), /* Timing(4), CKV ST=0CLK, CKV ED=1CLK */ + SMART_DAT(0x03), + SMART_DAT(0x03), + SMART_CMD(0x00), + SMART_CMD(0x34), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x00), + SMART_CMD(0x35), + SMART_DAT(0x02), + SMART_DAT(0x05), + SMART_CMD(0x00), + SMART_CMD(0x36), + SMART_DAT(0x1F), + SMART_DAT(0x1F), + SMART_CMD(0x00), + SMART_CMD(0x37), + SMART_DAT(0x07), + SMART_DAT(0x07), + SMART_CMD(0x00), + SMART_CMD(0x38), + SMART_DAT(0x00), + SMART_DAT(0x07), + SMART_CMD(0x00), + SMART_CMD(0x39), + SMART_DAT(0x04), + SMART_DAT(0x00), + SMART_CMD(0x00), + SMART_CMD(0x3A), + SMART_DAT(0x03), + SMART_DAT(0x03), + SMART_CMD(0x00), + SMART_CMD(0x3B), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x00), + SMART_CMD(0x3C), + SMART_DAT(0x02), + SMART_DAT(0x05), + SMART_CMD(0x00), + SMART_CMD(0x3D), + SMART_DAT(0x1F), + SMART_DAT(0x1F), + SMART_CMD(0x00), /* Display control 1 */ + SMART_CMD(0x07), + SMART_DAT(0x00), + SMART_DAT(0x01), + SMART_CMD(0x00), /* Power control 5 */ + SMART_CMD(0x17), + SMART_DAT(0x00), + SMART_DAT(0x01), + SMART_CMD(0x00), /* Power control 1 */ + SMART_CMD(0x10), + SMART_DAT(0x10), + SMART_DAT(0xB0), + SMART_CMD(0x00), /* Power control 2 */ + SMART_CMD(0x11), + SMART_DAT(0x01), + SMART_DAT(0x30), + SMART_CMD(0x00), /* Power control 3 */ + SMART_CMD(0x12), + SMART_DAT(0x01), + SMART_DAT(0x9E), + SMART_CMD(0x00), /* Power control 4 */ + SMART_CMD(0x13), + SMART_DAT(0x17), + SMART_DAT(0x00), + SMART_CMD(0x00), /* Power control 3 */ + SMART_CMD(0x12), + SMART_DAT(0x01), + SMART_DAT(0xBE), + SMART_DELAY(100), + + /* display mode : 240*320 */ + SMART_CMD(0x00), /* RAM address set(H) 0*/ + SMART_CMD(0x20), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x00), /* RAM address set(V) 4*/ + SMART_CMD(0x21), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x00), /* Start of Window RAM address set(H) 8*/ + SMART_CMD(0x50), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x00), /* End of Window RAM address set(H) 12*/ + SMART_CMD(0x51), + SMART_DAT(0x00), + SMART_DAT(0xEF), + SMART_CMD(0x00), /* Start of Window RAM address set(V) 16*/ + SMART_CMD(0x52), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x00), /* End of Window RAM address set(V) 20*/ + SMART_CMD(0x53), + SMART_DAT(0x01), + SMART_DAT(0x3F), + SMART_CMD(0x00), /* Panel interface control 1 */ + SMART_CMD(0x90), + SMART_DAT(0x00), + SMART_DAT(0x1A), + SMART_CMD(0x00), /* Panel interface control 2 */ + SMART_CMD(0x92), + SMART_DAT(0x04), + SMART_DAT(0x00), + SMART_CMD(0x00), /* Panel interface control 3 */ + SMART_CMD(0x93), + SMART_DAT(0x00), + SMART_DAT(0x05), + SMART_DELAY(20), +}; + +static uint16_t lcd_panel_on[] = { + SMART_CMD(0x00), + SMART_CMD(0x07), + SMART_DAT(0x00), + SMART_DAT(0x21), + SMART_DELAY(1), + + SMART_CMD(0x00), + SMART_CMD(0x07), + SMART_DAT(0x00), + SMART_DAT(0x61), + SMART_DELAY(100), + + SMART_CMD(0x00), + SMART_CMD(0x07), + SMART_DAT(0x01), + SMART_DAT(0x73), + SMART_DELAY(1), +}; + +static uint16_t lcd_panel_off[] = { + SMART_CMD(0x00), + SMART_CMD(0x07), + SMART_DAT(0x00), + SMART_DAT(0x72), + SMART_DELAY(40), + + SMART_CMD(0x00), + SMART_CMD(0x07), + SMART_DAT(0x00), + SMART_DAT(0x01), + SMART_DELAY(1), + + SMART_CMD(0x00), + SMART_CMD(0x07), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_DELAY(1), +}; + +static uint16_t lcd_power_off[] = { + SMART_CMD(0x00), + SMART_CMD(0x10), + SMART_DAT(0x00), + SMART_DAT(0x80), + + SMART_CMD(0x00), + SMART_CMD(0x11), + SMART_DAT(0x01), + SMART_DAT(0x60), + + SMART_CMD(0x00), + SMART_CMD(0x12), + SMART_DAT(0x01), + SMART_DAT(0xAE), + SMART_DELAY(40), + + SMART_CMD(0x00), + SMART_CMD(0x10), + SMART_DAT(0x00), + SMART_DAT(0x00), +}; + +static uint16_t update_framedata[] = { + /* set display ram: 240*320 */ + SMART_CMD(0x00), /* RAM address set(H) 0*/ + SMART_CMD(0x20), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x00), /* RAM address set(V) 4*/ + SMART_CMD(0x21), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x00), /* Start of Window RAM address set(H) 8 */ + SMART_CMD(0x50), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x00), /* End of Window RAM address set(H) 12 */ + SMART_CMD(0x51), + SMART_DAT(0x00), + SMART_DAT(0xEF), + SMART_CMD(0x00), /* Start of Window RAM address set(V) 16 */ + SMART_CMD(0x52), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x00), /* End of Window RAM address set(V) 20 */ + SMART_CMD(0x53), + SMART_DAT(0x01), + SMART_DAT(0x3F), + + /* wait for vsync cmd before transferring frame data */ + SMART_CMD_WAIT_FOR_VSYNC, + + /* write ram */ + SMART_CMD(0x00), + SMART_CMD(0x22), + + /* write frame data */ + SMART_CMD_WRITE_FRAME, +}; + +static void ltm022a97a_lcd_power(int on, struct fb_var_screeninfo *var) +{ + static int pin_requested = 0; + struct fb_info *info = container_of(var, struct fb_info, var); + int err; + + if (!pin_requested) { + err = gpio_request(GPIO_LCD_RESET, "lcd reset"); + if (err) { + pr_err("failed to request gpio for LCD reset\n"); + return; + } + + gpio_direction_output(GPIO_LCD_RESET, 0); + pin_requested = 1; + } + + if (on) { + gpio_set_value(GPIO_LCD_RESET, 0); msleep(100); + gpio_set_value(GPIO_LCD_RESET, 1); msleep(10); + + pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_on)); + pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_on)); + } else { + pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_off)); + pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_off)); + } + + err = pxafb_smart_flush(info); + if (err) + pr_err("%s: timed out\n", __func__); +} + +static void ltm022a97a_update(struct fb_info *info) +{ + pxafb_smart_queue(info, ARRAY_AND_SIZE(update_framedata)); + pxafb_smart_flush(info); +} + +static struct pxafb_mode_info toshiba_ltm022a97a_modes[] = { + [0] = { + .xres = 240, + .yres = 320, + .bpp = 16, + .a0csrd_set_hld = 30, + .a0cswr_set_hld = 30, + .wr_pulse_width = 30, + .rd_pulse_width = 30, + .op_hold_time = 30, + .cmd_inh_time = 60, + + /* L_LCLK_A0 and L_LCLK_RD active low */ + .sync = FB_SYNC_HOR_HIGH_ACT | + FB_SYNC_VERT_HIGH_ACT, + }, +}; + +static struct pxafb_mach_info saar_lcd_info = { + .modes = toshiba_ltm022a97a_modes, + .num_modes = 1, + .lcd_conn = LCD_SMART_PANEL_8BPP | LCD_PCLK_EDGE_FALL, + .pxafb_lcd_power = ltm022a97a_lcd_power, + .smart_update = ltm022a97a_update, +}; + +static void __init saar_init_lcd(void) +{ + set_pxa_fb_info(&saar_lcd_info); +} +#else +static inline void saar_init_lcd(void) {} +#endif + +#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE) +static struct da903x_subdev_info saar_da9034_subdevs[] = { + [0] = { + .name = "da903x-backlight", + .id = DA9034_ID_WLED, + }, +}; + +static struct da903x_platform_data saar_da9034_info = { + .num_subdevs = ARRAY_SIZE(saar_da9034_subdevs), + .subdevs = saar_da9034_subdevs, +}; + +static struct i2c_board_info saar_i2c_info[] = { + [0] = { + .type = "da9034", + .addr = 0x34, + .platform_data = &saar_da9034_info, + .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), + }, +}; + +static void __init saar_init_i2c(void) +{ + pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(saar_i2c_info)); +} +#else +static inline void saar_init_i2c(void) {} +#endif static void __init saar_init(void) { /* initialize MFP configurations */ pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg)); platform_device_register(&smc91x_device); + + saar_init_i2c(); + saar_init_lcd(); } MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)") diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c index ad346ad..d6f6904 100644 --- a/arch/arm/mach-pxa/smemc.c +++ b/arch/arm/mach-pxa/smemc.c @@ -8,6 +8,8 @@ #include <linux/io.h> #include <linux/sysdev.h> +#include <mach/hardware.h> + #define SMEMC_PHYS_BASE (0x4A000000) #define SMEMC_PHYS_SIZE (0x90) diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 3be76ee..7299d87 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -22,6 +22,7 @@ #include <linux/gpio.h> #include <linux/leds.h> #include <linux/mmc/host.h> +#include <linux/mtd/physmap.h> #include <linux/pm.h> #include <linux/backlight.h> #include <linux/io.h> @@ -122,6 +123,10 @@ static unsigned long spitz_pin_config[] __initdata = { GPIO105_GPIO, /* SPITZ_GPIO_CF_IRQ */ GPIO106_GPIO, /* SPITZ_GPIO_CF2_IRQ */ + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, }; @@ -609,10 +614,41 @@ static struct pxafb_mach_info spitz_pxafb_info = { }; +static struct mtd_partition sharpsl_rom_parts[] = { + { + .name ="Boot PROM Filesystem", + .offset = 0x00140000, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data sharpsl_rom_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(sharpsl_rom_parts), + .parts = sharpsl_rom_parts, +}; + +static struct resource sharpsl_rom_resources[] = { + { + .start = 0x00000000, + .end = 0x007fffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sharpsl_rom_device = { + .name = "physmap-flash", + .id = -1, + .resource = sharpsl_rom_resources, + .num_resources = ARRAY_SIZE(sharpsl_rom_resources), + .dev.platform_data = &sharpsl_rom_data, +}; + static struct platform_device *devices[] __initdata = { &spitzscoop_device, &spitzkbd_device, &spitzled_device, + &sharpsl_rom_device, }; static void spitz_poweroff(void) diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c index 2c31ec7..6f42004 100644 --- a/arch/arm/mach-pxa/ssp.c +++ b/arch/arm/mach-pxa/ssp.c @@ -356,7 +356,7 @@ static int __devinit ssp_probe(struct platform_device *pdev, int type) } ssp->pdev = pdev; - ssp->clk = clk_get(&pdev->dev, "SSPCLK"); + ssp->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(ssp->clk)) { ret = PTR_ERR(ssp->clk); goto err_free; diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index 589d32b..58ef08a 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c @@ -18,12 +18,15 @@ #include <linux/clk.h> #include <linux/gpio.h> #include <linux/smc91x.h> +#include <linux/pwm_backlight.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <mach/hardware.h> #include <mach/pxa3xx-regs.h> #include <mach/mfp-pxa930.h> +#include <mach/pxafb.h> +#include <mach/pxa27x_keypad.h> #include "devices.h" #include "generic.h" @@ -33,6 +36,45 @@ static mfp_cfg_t tavorevb_mfp_cfg[] __initdata = { /* Ethernet */ DF_nCS1_nCS3, GPIO47_GPIO, + + /* LCD */ + GPIO23_LCD_DD0, + GPIO24_LCD_DD1, + GPIO25_LCD_DD2, + GPIO26_LCD_DD3, + GPIO27_LCD_DD4, + GPIO28_LCD_DD5, + GPIO29_LCD_DD6, + GPIO44_LCD_DD7, + GPIO21_LCD_CS, + GPIO22_LCD_CS2, + + GPIO17_LCD_FCLK_RD, + GPIO18_LCD_LCLK_A0, + GPIO19_LCD_PCLK_WR, + + /* LCD Backlight */ + GPIO43_PWM3, /* primary backlight */ + GPIO32_PWM0, /* secondary backlight */ + + /* Keypad */ + GPIO0_KP_MKIN_0, + GPIO2_KP_MKIN_1, + GPIO4_KP_MKIN_2, + GPIO6_KP_MKIN_3, + GPIO8_KP_MKIN_4, + GPIO10_KP_MKIN_5, + GPIO12_KP_MKIN_6, + GPIO1_KP_MKOUT_0, + GPIO3_KP_MKOUT_1, + GPIO5_KP_MKOUT_2, + GPIO7_KP_MKOUT_3, + GPIO9_KP_MKOUT_4, + GPIO11_KP_MKOUT_5, + GPIO13_KP_MKOUT_6, + + GPIO14_KP_DKIN_2, + GPIO15_KP_DKIN_3, }; #define TAVOREVB_ETH_PHYS (0x14000000) @@ -64,12 +106,382 @@ static struct platform_device smc91x_device = { }, }; +#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE) +static unsigned int tavorevb_matrix_key_map[] = { + /* KEY(row, col, key_code) */ + KEY(0, 4, KEY_A), KEY(0, 5, KEY_B), KEY(0, 6, KEY_C), + KEY(1, 4, KEY_E), KEY(1, 5, KEY_F), KEY(1, 6, KEY_G), + KEY(2, 4, KEY_I), KEY(2, 5, KEY_J), KEY(2, 6, KEY_K), + KEY(3, 4, KEY_M), KEY(3, 5, KEY_N), KEY(3, 6, KEY_O), + KEY(4, 5, KEY_R), KEY(4, 6, KEY_S), + KEY(5, 4, KEY_U), KEY(5, 4, KEY_V), KEY(5, 6, KEY_W), + + KEY(6, 4, KEY_Y), KEY(6, 5, KEY_Z), + + KEY(0, 3, KEY_0), KEY(2, 0, KEY_1), KEY(2, 1, KEY_2), KEY(2, 2, KEY_3), + KEY(2, 3, KEY_4), KEY(1, 0, KEY_5), KEY(1, 1, KEY_6), KEY(1, 2, KEY_7), + KEY(1, 3, KEY_8), KEY(0, 2, KEY_9), + + KEY(6, 6, KEY_SPACE), + KEY(0, 0, KEY_KPASTERISK), /* * */ + KEY(0, 1, KEY_KPDOT), /* # */ + + KEY(4, 1, KEY_UP), + KEY(4, 3, KEY_DOWN), + KEY(4, 0, KEY_LEFT), + KEY(4, 2, KEY_RIGHT), + KEY(6, 0, KEY_HOME), + KEY(3, 2, KEY_END), + KEY(6, 1, KEY_DELETE), + KEY(5, 2, KEY_BACK), + KEY(6, 3, KEY_CAPSLOCK), /* KEY_LEFTSHIFT), */ + + KEY(4, 4, KEY_ENTER), /* scroll push */ + KEY(6, 2, KEY_ENTER), /* keypad action */ + + KEY(3, 1, KEY_SEND), + KEY(5, 3, KEY_RECORD), + KEY(5, 0, KEY_VOLUMEUP), + KEY(5, 1, KEY_VOLUMEDOWN), + + KEY(3, 0, KEY_F22), /* soft1 */ + KEY(3, 3, KEY_F23), /* soft2 */ +}; + +static struct pxa27x_keypad_platform_data tavorevb_keypad_info = { + .matrix_key_rows = 7, + .matrix_key_cols = 7, + .matrix_key_map = tavorevb_matrix_key_map, + .matrix_key_map_size = ARRAY_SIZE(tavorevb_matrix_key_map), + .debounce_interval = 30, +}; + +static void __init tavorevb_init_keypad(void) +{ + pxa_set_keypad_info(&tavorevb_keypad_info); +} +#else +static inline void tavorevb_init_keypad(void) {} +#endif /* CONFIG_KEYBOARD_PXA27x || CONFIG_KEYBOARD_PXA27x_MODULE */ + +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) +static struct platform_pwm_backlight_data tavorevb_backlight_data[] = { + [0] = { + /* primary backlight */ + .pwm_id = 2, + .max_brightness = 100, + .dft_brightness = 100, + .pwm_period_ns = 100000, + }, + [1] = { + /* secondary backlight */ + .pwm_id = 0, + .max_brightness = 100, + .dft_brightness = 100, + .pwm_period_ns = 100000, + }, +}; + +static struct platform_device tavorevb_backlight_devices[] = { + [0] = { + .name = "pwm-backlight", + .id = 0, + .dev = { + .platform_data = &tavorevb_backlight_data[0], + }, + }, + [1] = { + .name = "pwm-backlight", + .id = 1, + .dev = { + .platform_data = &tavorevb_backlight_data[1], + }, + }, +}; + +static uint16_t panel_init[] = { + /* DSTB OUT */ + SMART_CMD(0x00), + SMART_CMD_NOOP, + SMART_DELAY(1), + + SMART_CMD(0x00), + SMART_CMD_NOOP, + SMART_DELAY(1), + + SMART_CMD(0x00), + SMART_CMD_NOOP, + SMART_DELAY(1), + + /* STB OUT */ + SMART_CMD(0x00), + SMART_CMD(0x1D), + SMART_DAT(0x00), + SMART_DAT(0x05), + SMART_DELAY(1), + + /* P-ON Init sequence */ + SMART_CMD(0x00), /* OSC ON */ + SMART_CMD(0x00), + SMART_DAT(0x00), + SMART_DAT(0x01), + SMART_CMD(0x00), + SMART_CMD(0x01), /* SOURCE DRIVER SHIFT DIRECTION and display RAM setting */ + SMART_DAT(0x01), + SMART_DAT(0x27), + SMART_CMD(0x00), + SMART_CMD(0x02), /* LINE INV */ + SMART_DAT(0x02), + SMART_DAT(0x00), + SMART_CMD(0x00), + SMART_CMD(0x03), /* IF mode(1) */ + SMART_DAT(0x01), /* 8bit smart mode(8-8),high speed write mode */ + SMART_DAT(0x30), + SMART_CMD(0x07), + SMART_CMD(0x00), /* RAM Write Mode */ + SMART_DAT(0x00), + SMART_DAT(0x03), + SMART_CMD(0x00), + + /* DISPLAY Setting, 262K, fixed(NO scroll), no split screen */ + SMART_CMD(0x07), + SMART_DAT(0x40), /* 16/18/19 BPP */ + SMART_DAT(0x00), + SMART_CMD(0x00), + SMART_CMD(0x08), /* BP, FP Seting, BP=2H, FP=3H */ + SMART_DAT(0x03), + SMART_DAT(0x02), + SMART_CMD(0x00), + SMART_CMD(0x0C), /* IF mode(2), using internal clock & MPU */ + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x00), + SMART_CMD(0x0D), /* Frame setting, 1Min. Frequence, 16CLK */ + SMART_DAT(0x00), + SMART_DAT(0x10), + SMART_CMD(0x00), + SMART_CMD(0x12), /* Timing(1),ASW W=4CLK, ASW ST=1CLK */ + SMART_DAT(0x03), + SMART_DAT(0x02), + SMART_CMD(0x00), + SMART_CMD(0x13), /* Timing(2),OEV ST=0.5CLK, OEV ED=1CLK */ + SMART_DAT(0x01), + SMART_DAT(0x02), + SMART_CMD(0x00), + SMART_CMD(0x14), /* Timing(3), ASW HOLD=0.5CLK */ + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x00), + SMART_CMD(0x15), /* Timing(4), CKV ST=0CLK, CKV ED=1CLK */ + SMART_DAT(0x20), + SMART_DAT(0x00), + SMART_CMD(0x00), + SMART_CMD(0x1C), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x03), + SMART_CMD(0x00), + SMART_DAT(0x04), + SMART_DAT(0x03), + SMART_CMD(0x03), + SMART_CMD(0x01), + SMART_DAT(0x03), + SMART_DAT(0x04), + SMART_CMD(0x03), + SMART_CMD(0x02), + SMART_DAT(0x04), + SMART_DAT(0x03), + SMART_CMD(0x03), + SMART_CMD(0x03), + SMART_DAT(0x03), + SMART_DAT(0x03), + SMART_CMD(0x03), + SMART_CMD(0x04), + SMART_DAT(0x01), + SMART_DAT(0x01), + SMART_CMD(0x03), + SMART_CMD(0x05), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x04), + SMART_CMD(0x02), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x04), + SMART_CMD(0x03), + SMART_DAT(0x01), + SMART_DAT(0x3F), + SMART_DELAY(0), + + /* DISP RAM setting: 240*320 */ + SMART_CMD(0x04), /* HADDR, START 0 */ + SMART_CMD(0x06), + SMART_DAT(0x00), + SMART_DAT(0x00), /* x1,3 */ + SMART_CMD(0x04), /* HADDR, END 4 */ + SMART_CMD(0x07), + SMART_DAT(0x00), + SMART_DAT(0xEF), /* x2, 7 */ + SMART_CMD(0x04), /* VADDR, START 8 */ + SMART_CMD(0x08), + SMART_DAT(0x00), /* y1, 10 */ + SMART_DAT(0x00), /* y1, 11 */ + SMART_CMD(0x04), /* VADDR, END 12 */ + SMART_CMD(0x09), + SMART_DAT(0x01), /* y2, 14 */ + SMART_DAT(0x3F), /* y2, 15 */ + SMART_CMD(0x02), /* RAM ADDR SETTING 16 */ + SMART_CMD(0x00), + SMART_DAT(0x00), + SMART_DAT(0x00), /* x1, 19 */ + SMART_CMD(0x02), /* RAM ADDR SETTING 20 */ + SMART_CMD(0x01), + SMART_DAT(0x00), /* y1, 22 */ + SMART_DAT(0x00), /* y1, 23 */ +}; + +static uint16_t panel_on[] = { + /* Power-IC ON */ + SMART_CMD(0x01), + SMART_CMD(0x02), + SMART_DAT(0x07), + SMART_DAT(0x7D), + SMART_CMD(0x01), + SMART_CMD(0x03), + SMART_DAT(0x00), + SMART_DAT(0x05), + SMART_CMD(0x01), + SMART_CMD(0x04), + SMART_DAT(0x00), + SMART_DAT(0x00), + SMART_CMD(0x01), + SMART_CMD(0x05), + SMART_DAT(0x00), + SMART_DAT(0x15), + SMART_CMD(0x01), + SMART_CMD(0x00), + SMART_DAT(0xC0), + SMART_DAT(0x10), + SMART_DELAY(30), + + /* DISP ON */ + SMART_CMD(0x01), + SMART_CMD(0x01), + SMART_DAT(0x00), + SMART_DAT(0x01), + SMART_CMD(0x01), + SMART_CMD(0x00), + SMART_DAT(0xFF), + SMART_DAT(0xFE), + SMART_DELAY(150), +}; + +static uint16_t panel_off[] = { + SMART_CMD(0x00), + SMART_CMD(0x1E), + SMART_DAT(0x00), + SMART_DAT(0x0A), + SMART_CMD(0x01), + SMART_CMD(0x00), + SMART_DAT(0xFF), + SMART_DAT(0xEE), + SMART_CMD(0x01), + SMART_CMD(0x00), + SMART_DAT(0xF8), + SMART_DAT(0x12), + SMART_CMD(0x01), + SMART_CMD(0x00), + SMART_DAT(0xE8), + SMART_DAT(0x11), + SMART_CMD(0x01), + SMART_CMD(0x00), + SMART_DAT(0xC0), + SMART_DAT(0x11), + SMART_CMD(0x01), + SMART_CMD(0x00), + SMART_DAT(0x40), + SMART_DAT(0x11), + SMART_CMD(0x01), + SMART_CMD(0x00), + SMART_DAT(0x00), + SMART_DAT(0x10), +}; + +static uint16_t update_framedata[] = { + /* write ram */ + SMART_CMD(0x02), + SMART_CMD(0x02), + + /* write frame data */ + SMART_CMD_WRITE_FRAME, +}; + +static void ltm020d550_lcd_power(int on, struct fb_var_screeninfo *var) +{ + struct fb_info *info = container_of(var, struct fb_info, var); + + if (on) { + pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_init)); + pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_on)); + } else { + pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_off)); + } + + if (pxafb_smart_flush(info)) + pr_err("%s: timed out\n", __func__); +} + +static void ltm020d550_update(struct fb_info *info) +{ + pxafb_smart_queue(info, ARRAY_AND_SIZE(update_framedata)); + pxafb_smart_flush(info); +} + +static struct pxafb_mode_info toshiba_ltm020d550_modes[] = { + [0] = { + .xres = 240, + .yres = 320, + .bpp = 16, + .a0csrd_set_hld = 30, + .a0cswr_set_hld = 30, + .wr_pulse_width = 30, + .rd_pulse_width = 170, + .op_hold_time = 30, + .cmd_inh_time = 60, + + /* L_LCLK_A0 and L_LCLK_RD active low */ + .sync = FB_SYNC_HOR_HIGH_ACT | + FB_SYNC_VERT_HIGH_ACT, + }, +}; + +static struct pxafb_mach_info tavorevb_lcd_info = { + .modes = toshiba_ltm020d550_modes, + .num_modes = 1, + .lcd_conn = LCD_SMART_PANEL_8BPP | LCD_PCLK_EDGE_FALL, + .pxafb_lcd_power = ltm020d550_lcd_power, + .smart_update = ltm020d550_update, +}; + +static void __init tavorevb_init_lcd(void) +{ + platform_device_register(&tavorevb_backlight_devices[0]); + platform_device_register(&tavorevb_backlight_devices[1]); + set_pxa_fb_info(&tavorevb_lcd_info); +} +#else +static inline void tavorevb_init_lcd(void) {} +#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */ + static void __init tavorevb_init(void) { /* initialize MFP configurations */ pxa3xx_mfp_config(ARRAY_AND_SIZE(tavorevb_mfp_cfg)); platform_device_register(&smc91x_device); + + tavorevb_init_lcd(); + tavorevb_init_keypad(); } MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)") diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index f8a9a62..0016241 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -22,8 +22,8 @@ #include <asm/div64.h> #include <asm/mach/irq.h> #include <asm/mach/time.h> +#include <mach/hardware.h> #include <mach/pxa-regs.h> -#include <asm/mach-types.h> /* * This is PXA's sched_clock implementation. This has a resolution @@ -150,18 +150,11 @@ static struct irqaction pxa_ost0_irq = { static void __init pxa_timer_init(void) { - unsigned long clock_tick_rate; + unsigned long clock_tick_rate = get_clock_tick_rate(); OIER = 0; OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; - if (cpu_is_pxa25x()) - clock_tick_rate = 3686400; - else if (machine_is_mainstone()) - clock_tick_rate = 3249600; - else - clock_tick_rate = 3250000; - set_oscr2ns_scale(clock_tick_rate); ckevt_pxa_osmr0.mult = diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 224897a..3332e5d 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -25,6 +25,7 @@ #include <linux/mfd/tmio.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> #include <linux/pm.h> #include <linux/gpio_keys.h> #include <linux/input.h> @@ -733,6 +734,45 @@ static void tosa_tc6393xb_teardown(struct platform_device *dev) gpio_free(TOSA_GPIO_CARD_VCC_ON); } +#ifdef CONFIG_MFD_TC6393XB +static struct fb_videomode tosa_tc6393xb_lcd_mode[] = { + { + .xres = 480, + .yres = 640, + .pixclock = 0x002cdf00,/* PLL divisor */ + .left_margin = 0x004c, + .right_margin = 0x005b, + .upper_margin = 0x0001, + .lower_margin = 0x000d, + .hsync_len = 0x0002, + .vsync_len = 0x0001, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + },{ + .xres = 240, + .yres = 320, + .pixclock = 0x00e7f203,/* PLL divisor */ + .left_margin = 0x0024, + .right_margin = 0x002f, + .upper_margin = 0x0001, + .lower_margin = 0x000d, + .hsync_len = 0x0002, + .vsync_len = 0x0001, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + } +}; + +static struct tmio_fb_data tosa_tc6393xb_fb_config = { + .lcd_set_power = tc6393xb_lcd_set_power, + .lcd_mode = tc6393xb_lcd_mode, + .num_modes = ARRAY_SIZE(tosa_tc6393xb_lcd_mode), + .modes = &tosa_tc6393xb_lcd_mode[0], + .height = 82, + .width = 60, +}; +#endif + static struct tc6393xb_platform_data tosa_tc6393xb_data = { .scr_pll2cr = 0x0cc1, .scr_gper = 0x3300, @@ -748,6 +788,9 @@ static struct tc6393xb_platform_data tosa_tc6393xb_data = { .resume = tosa_tc6393xb_resume, .nand_data = &tosa_tc6393xb_nand_config, +#ifdef CONFIG_MFD_TC6393XB + .fb_data = &tosa_tc6393xb_fb_config, +#endif .resume_restore = 1, }; @@ -789,6 +832,36 @@ static struct spi_board_info spi_board_info[] __initdata = { }, }; +static struct mtd_partition sharpsl_rom_parts[] = { + { + .name ="Boot PROM Filesystem", + .offset = 0x00160000, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data sharpsl_rom_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(sharpsl_rom_parts), + .parts = sharpsl_rom_parts, +}; + +static struct resource sharpsl_rom_resources[] = { + { + .start = 0x00000000, + .end = 0x007fffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sharpsl_rom_device = { + .name = "physmap-flash", + .id = -1, + .resource = sharpsl_rom_resources, + .num_resources = ARRAY_SIZE(sharpsl_rom_resources), + .dev.platform_data = &sharpsl_rom_data, +}; + static struct platform_device *devices[] __initdata = { &tosascoop_device, &tosascoop_jc_device, @@ -798,6 +871,7 @@ static struct platform_device *devices[] __initdata = { &tosa_gpio_keys_device, &tosaled_device, &tosa_bt_device, + &sharpsl_rom_device, }; static void tosa_poweroff(void) diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 8138044..218d200 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -18,6 +18,7 @@ #include <linux/interrupt.h> #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/gpio.h> #include <linux/pwm_backlight.h> #include <linux/smc91x.h> @@ -25,7 +26,6 @@ #include <asm/mach/arch.h> #include <mach/hardware.h> #include <mach/audio.h> -#include <mach/gpio.h> #include <mach/pxafb.h> #include <mach/zylonite.h> #include <mach/mmc.h> diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c index 0f24474..28e4e62 100644 --- a/arch/arm/mach-pxa/zylonite_pxa320.c +++ b/arch/arm/mach-pxa/zylonite_pxa320.c @@ -16,8 +16,8 @@ #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> +#include <linux/gpio.h> -#include <mach/gpio.h> #include <mach/mfp-pxa320.h> #include <mach/zylonite.h> diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 5ccde7c..ad91185 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -7,9 +7,17 @@ config MACH_REALVIEW_EB help Include support for the ARM(R) RealView Emulation Baseboard platform. +config REALVIEW_EB_A9MP + bool "Support Multicore Cortex-A9" + depends on MACH_REALVIEW_EB + select CPU_V7 + help + Enable support for the Cortex-A9MPCore tile on the Realview platform. + config REALVIEW_EB_ARM11MP bool "Support ARM11MPCore tile" depends on MACH_REALVIEW_EB + select CPU_V6 help Enable support for the ARM11MPCore tile on the Realview platform. @@ -25,6 +33,7 @@ config REALVIEW_EB_ARM11MP_REVB config MACH_REALVIEW_PB11MP bool "Support RealView/PB11MPCore platform" + select CPU_V6 select ARM_GIC help Include support for the ARM(R) RealView MPCore Platform Baseboard. @@ -33,8 +42,29 @@ config MACH_REALVIEW_PB11MP config MACH_REALVIEW_PB1176 bool "Support RealView/PB1176 platform" + select CPU_V6 select ARM_GIC help Include support for the ARM(R) RealView ARM1176 Platform Baseboard. +config MACH_REALVIEW_PBA8 + bool "Support RealView/PB-A8 platform" + select CPU_V7 + select ARM_GIC + help + Include support for the ARM(R) RealView Cortex-A8 Platform Baseboard. + PB-A8 is a platform with an on-board Cortex-A8 and has support for + PCI-E and Compact Flash. + +config REALVIEW_HIGH_PHYS_OFFSET + bool "High physical base address for the RealView platform" + depends on !MACH_REALVIEW_PB1176 + default y + help + RealView boards other than PB1176 have the RAM available at + 0x70000000, 256MB of which being mirrored at 0x00000000. If + the board supports 512MB of RAM, this option allows the + memory to be accessed contiguously at the high physical + offset. + endmenu diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile index d2ae077..7bea8ff 100644 --- a/arch/arm/mach-realview/Makefile +++ b/arch/arm/mach-realview/Makefile @@ -6,5 +6,6 @@ obj-y := core.o clock.o obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o +obj-$(CONFIG_MACH_REALVIEW_PBA8) += realview_pba8.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-realview/Makefile.boot b/arch/arm/mach-realview/Makefile.boot index c7e75ac..d97e003 100644 --- a/arch/arm/mach-realview/Makefile.boot +++ b/arch/arm/mach-realview/Makefile.boot @@ -1,4 +1,9 @@ +ifeq ($(CONFIG_REALVIEW_HIGH_PHYS_OFFSET),y) + zreladdr-y := 0x70008000 +params_phys-y := 0x70000100 +initrd_phys-y := 0x70800000 +else zreladdr-y := 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 - +endif diff --git a/arch/arm/mach-realview/clock.c b/arch/arm/mach-realview/clock.c index 3347c42..a704311 100644 --- a/arch/arm/mach-realview/clock.c +++ b/arch/arm/mach-realview/clock.c @@ -10,9 +10,11 @@ */ #include <linux/module.h> #include <linux/kernel.h> +#include <linux/device.h> #include <linux/list.h> #include <linux/errno.h> #include <linux/err.h> +#include <linux/string.h> #include <linux/clk.h> #include <linux/mutex.h> @@ -20,32 +22,6 @@ #include "clock.h" -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); - -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p, *clk = ERR_PTR(-ENOENT); - - mutex_lock(&clocks_mutex); - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { - clk = p; - break; - } - } - mutex_unlock(&clocks_mutex); - - return clk; -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ - module_put(clk->owner); -} -EXPORT_SYMBOL(clk_put); - int clk_enable(struct clk *clk) { return 0; @@ -65,7 +41,9 @@ EXPORT_SYMBOL(clk_get_rate); long clk_round_rate(struct clk *clk, unsigned long rate) { - return rate; + struct icst307_vco vco; + vco = icst307_khz_to_vco(clk->params, rate / 1000); + return icst307_khz(clk->params, vco) * 1000; } EXPORT_SYMBOL(clk_round_rate); @@ -78,57 +56,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate) vco = icst307_khz_to_vco(clk->params, rate / 1000); clk->rate = icst307_khz(clk->params, vco) * 1000; - - printk("Clock %s: setting VCO reg params: S=%d R=%d V=%d\n", - clk->name, vco.s, vco.r, vco.v); - clk->setvco(clk, vco); ret = 0; } return ret; } EXPORT_SYMBOL(clk_set_rate); - -/* - * These are fixed clocks. - */ -static struct clk kmi_clk = { - .name = "KMIREFCLK", - .rate = 24000000, -}; - -static struct clk uart_clk = { - .name = "UARTCLK", - .rate = 24000000, -}; - -static struct clk mmci_clk = { - .name = "MCLK", - .rate = 24000000, -}; - -int clk_register(struct clk *clk) -{ - mutex_lock(&clocks_mutex); - list_add(&clk->node, &clocks); - mutex_unlock(&clocks_mutex); - return 0; -} -EXPORT_SYMBOL(clk_register); - -void clk_unregister(struct clk *clk) -{ - mutex_lock(&clocks_mutex); - list_del(&clk->node); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL(clk_unregister); - -static int __init clk_init(void) -{ - clk_register(&kmi_clk); - clk_register(&uart_clk); - clk_register(&mmci_clk); - return 0; -} -arch_initcall(clk_init); diff --git a/arch/arm/mach-realview/clock.h b/arch/arm/mach-realview/clock.h index dadba69..ebbb0f0 100644 --- a/arch/arm/mach-realview/clock.h +++ b/arch/arm/mach-realview/clock.h @@ -12,14 +12,8 @@ struct module; struct icst307_params; struct clk { - struct list_head node; unsigned long rate; - struct module *owner; - const char *name; const struct icst307_params *params; void *data; void (*setvco)(struct clk *, struct icst307_vco vco); }; - -int clk_register(struct clk *clk); -void clk_unregister(struct clk *clk); diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 2f04d54..5f1d559 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -28,11 +28,14 @@ #include <linux/clocksource.h> #include <linux/clockchips.h> #include <linux/io.h> +#include <linux/smc911x.h> +#include <asm/clkdev.h> #include <asm/system.h> #include <mach/hardware.h> #include <asm/irq.h> #include <asm/leds.h> +#include <asm/mach-types.h> #include <asm/hardware/arm_timer.h> #include <asm/hardware/icst307.h> @@ -49,7 +52,7 @@ #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET) -/* used by entry-macro.S */ +/* used by entry-macro.S and platsmp.c */ void __iomem *gic_cpu_base_addr; /* @@ -124,6 +127,29 @@ int realview_flash_register(struct resource *res, u32 num) return platform_device_register(&realview_flash_device); } +static struct smc911x_platdata realview_smc911x_platdata = { + .flags = SMC911X_USE_32BIT, + .irq_flags = IRQF_SHARED, + .irq_polarity = 1, +}; + +static struct platform_device realview_eth_device = { + .name = "smc911x", + .id = 0, + .num_resources = 2, +}; + +int realview_eth_register(const char *name, struct resource *res) +{ + if (name) + realview_eth_device.name = name; + realview_eth_device.resource = res; + if (strcmp(realview_eth_device.name, "smc911x") == 0) + realview_eth_device.dev.platform_data = &realview_smc911x_platdata; + + return platform_device_register(&realview_eth_device); +} + static struct resource realview_i2c_resource = { .start = REALVIEW_I2C_BASE, .end = REALVIEW_I2C_BASE + SZ_4K - 1, @@ -177,9 +203,14 @@ static const struct icst307_params realview_oscvco_params = { static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco) { void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET; - void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET; + void __iomem *sys_osc; u32 val; + if (machine_is_realview_pb1176()) + sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET; + else + sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET; + val = readl(sys_osc) & ~0x7ffff; val |= vco.v | (vco.r << 9) | (vco.s << 16); @@ -188,13 +219,60 @@ static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco) writel(0, sys_lock); } -struct clk realview_clcd_clk = { - .name = "CLCDCLK", +static struct clk oscvco_clk = { .params = &realview_oscvco_params, .setvco = realview_oscvco_set, }; /* + * These are fixed clocks. + */ +static struct clk ref24_clk = { + .rate = 24000000, +}; + +static struct clk_lookup lookups[] = { + { /* UART0 */ + .dev_id = "dev:f1", + .clk = &ref24_clk, + }, { /* UART1 */ + .dev_id = "dev:f2", + .clk = &ref24_clk, + }, { /* UART2 */ + .dev_id = "dev:f3", + .clk = &ref24_clk, + }, { /* UART3 */ + .dev_id = "fpga:09", + .clk = &ref24_clk, + }, { /* KMI0 */ + .dev_id = "fpga:06", + .clk = &ref24_clk, + }, { /* KMI1 */ + .dev_id = "fpga:07", + .clk = &ref24_clk, + }, { /* MMC0 */ + .dev_id = "fpga:05", + .clk = &ref24_clk, + }, { /* EB:CLCD */ + .dev_id = "dev:20", + .clk = &oscvco_clk, + }, { /* PB:CLCD */ + .dev_id = "issp:20", + .clk = &oscvco_clk, + } +}; + +static int __init clk_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); + return 0; +} +arch_initcall(clk_init); + +/* * CLCD support. */ #define SYS_CLCD_NLCDIOON (1 << 2) @@ -226,7 +304,30 @@ static struct clcd_panel vga = { .width = -1, .height = -1, .tim2 = TIM2_BCD | TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), + .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), + .bpp = 16, +}; + +static struct clcd_panel xvga = { + .mode = { + .name = "XVGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15748, + .left_margin = 152, + .right_margin = 48, + .upper_margin = 23, + .lower_margin = 3, + .hsync_len = 104, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, + .width = -1, + .height = -1, + .tim2 = TIM2_BCD | TIM2_IPC, + .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), .bpp = 16, }; @@ -249,7 +350,7 @@ static struct clcd_panel sanyo_3_8_in = { .width = -1, .height = -1, .tim2 = TIM2_BCD, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), + .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), .bpp = 16, }; @@ -272,7 +373,7 @@ static struct clcd_panel sanyo_2_5_in = { .width = -1, .height = -1, .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), + .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), .bpp = 16, }; @@ -295,7 +396,7 @@ static struct clcd_panel epson_2_2_in = { .width = -1, .height = -1, .tim2 = TIM2_BCD | TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), + .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), .bpp = 16, }; @@ -308,9 +409,15 @@ static struct clcd_panel epson_2_2_in = { static struct clcd_panel *realview_clcd_panel(void) { void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; - struct clcd_panel *panel = &vga; + struct clcd_panel *vga_panel; + struct clcd_panel *panel; u32 val; + if (machine_is_realview_eb()) + vga_panel = &vga; + else + vga_panel = &xvga; + val = readl(sys_clcd) & SYS_CLCD_ID_MASK; if (val == SYS_CLCD_ID_SANYO_3_8) panel = &sanyo_3_8_in; @@ -319,11 +426,11 @@ static struct clcd_panel *realview_clcd_panel(void) else if (val == SYS_CLCD_ID_EPSON_2_2) panel = &epson_2_2_in; else if (val == SYS_CLCD_ID_VGA) - panel = &vga; + panel = vga_panel; else { printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val); - panel = &vga; + panel = vga_panel; } return panel; @@ -358,12 +465,18 @@ static void realview_clcd_enable(struct clcd_fb *fb) writel(val, sys_clcd); } -static unsigned long framesize = SZ_1M; - static int realview_clcd_setup(struct clcd_fb *fb) { + unsigned long framesize; dma_addr_t dma; + if (machine_is_realview_eb()) + /* VGA, 16bpp */ + framesize = 640 * 480 * 2; + else + /* XVGA, 16bpp */ + framesize = 1024 * 768 * 2; + fb->panel = realview_clcd_panel(); fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, @@ -588,7 +701,7 @@ void __init realview_timer_init(unsigned int timer_irq) * The dummy clock device has to be registered before the main device * so that the latter will broadcast the clock events */ - local_timer_setup(smp_processor_id()); + local_timer_setup(); #endif /* diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 3cea92c..63be2ab 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h @@ -48,12 +48,10 @@ extern struct platform_device realview_flash_device; extern struct platform_device realview_i2c_device; extern struct mmc_platform_data realview_mmc0_plat_data; extern struct mmc_platform_data realview_mmc1_plat_data; -extern struct clk realview_clcd_clk; extern struct clcd_board clcd_plat_data; extern void __iomem *gic_cpu_base_addr; #ifdef CONFIG_LOCAL_TIMERS -extern void __iomem *twd_base_addr; -extern unsigned int twd_size; +extern void __iomem *twd_base; #endif extern void __iomem *timer0_va_base; extern void __iomem *timer1_va_base; @@ -63,5 +61,6 @@ extern void __iomem *timer3_va_base; extern void realview_leds_event(led_event_t ledevt); extern void realview_timer_init(unsigned int timer_irq); extern int realview_flash_register(struct resource *res, u32 num); +extern int realview_eth_register(const char *name, struct resource *res); #endif diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c index 09748cb..be048e3 100644 --- a/arch/arm/mach-realview/hotplug.c +++ b/arch/arm/mach-realview/hotplug.c @@ -13,6 +13,8 @@ #include <linux/smp.h> #include <linux/completion.h> +#include <asm/cacheflush.h> + extern volatile int pen_release; static DECLARE_COMPLETION(cpu_killed); @@ -21,7 +23,8 @@ static inline void cpu_enter_lowpower(void) { unsigned int v; - asm volatile( "mcr p15, 0, %1, c7, c14, 0\n" + flush_cache_all(); + asm volatile( " mcr p15, 0, %1, c7, c5, 0\n" " mcr p15, 0, %1, c7, c10, 4\n" /* diff --git a/arch/arm/mach-realview/include/mach/board-eb.h b/arch/arm/mach-realview/include/mach/board-eb.h index 8d699fd..268d770 100644 --- a/arch/arm/mach-realview/include/mach/board-eb.h +++ b/arch/arm/mach-realview/include/mach/board-eb.h @@ -49,16 +49,14 @@ #ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB #define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */ #define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ -#define REALVIEW_EB11MP_TWD_BASE 0x10100700 -#define REALVIEW_EB11MP_TWD_SIZE 0x00000100 +#define REALVIEW_EB11MP_TWD_BASE 0x10100600 #define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ #define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */ #define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ #else #define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */ #define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */ -#define REALVIEW_EB11MP_TWD_BASE 0x1F000700 -#define REALVIEW_EB11MP_TWD_SIZE 0x00000100 +#define REALVIEW_EB11MP_TWD_BASE 0x1F000600 #define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */ #define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */ #define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ @@ -163,7 +161,7 @@ #define NR_IRQS NR_IRQS_EB #endif -#if defined(CONFIG_REALVIEW_EB_ARM11MP) \ +#if defined(CONFIG_REALVIEW_EB_ARM11MP) || defined(CONFIG_REALVIEW_EB_A9MP) \ && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP)) #undef MAX_GIC_NR #define MAX_GIC_NR NR_GIC_EB11MP @@ -177,6 +175,7 @@ #define REALVIEW_EB_PROC_ARM9 0x02000000 #define REALVIEW_EB_PROC_ARM11 0x04000000 #define REALVIEW_EB_PROC_ARM11MP 0x06000000 +#define REALVIEW_EB_PROC_A9MP 0x0C000000 #define check_eb_proc(proc_type) \ ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \ @@ -188,4 +187,13 @@ #define core_tile_eb11mp() 0 #endif +#ifdef CONFIG_REALVIEW_EB_A9MP +#define core_tile_a9mp() check_eb_proc(REALVIEW_EB_PROC_A9MP) +#else +#define core_tile_a9mp() 0 +#endif + +#define machine_is_realview_eb_mp() \ + (machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp())) + #endif /* __ASM_ARCH_BOARD_EB_H */ diff --git a/arch/arm/mach-realview/include/mach/board-pb11mp.h b/arch/arm/mach-realview/include/mach/board-pb11mp.h index ecd80e5..53ea0e7 100644 --- a/arch/arm/mach-realview/include/mach/board-pb11mp.h +++ b/arch/arm/mach-realview/include/mach/board-pb11mp.h @@ -77,8 +77,7 @@ */ #define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */ #define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */ -#define REALVIEW_TC11MP_TWD_BASE 0x1F000700 -#define REALVIEW_TC11MP_TWD_SIZE 0x00000100 +#define REALVIEW_TC11MP_TWD_BASE 0x1F000600 #define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */ #define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */ diff --git a/arch/arm/mach-realview/include/mach/board-pba8.h b/arch/arm/mach-realview/include/mach/board-pba8.h new file mode 100644 index 0000000..c8bed8f --- /dev/null +++ b/arch/arm/mach-realview/include/mach/board-pba8.h @@ -0,0 +1,152 @@ +/* + * include/asm-arm/arch-realview/board-pba8.h + * + * Copyright (C) 2008 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_BOARD_PBA8_H +#define __ASM_ARCH_BOARD_PBA8_H + +#include <mach/platform.h> + +/* + * Peripheral addresses + */ +#define REALVIEW_PBA8_UART0_BASE 0x10009000 /* UART 0 */ +#define REALVIEW_PBA8_UART1_BASE 0x1000A000 /* UART 1 */ +#define REALVIEW_PBA8_UART2_BASE 0x1000B000 /* UART 2 */ +#define REALVIEW_PBA8_UART3_BASE 0x1000C000 /* UART 3 */ +#define REALVIEW_PBA8_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ +#define REALVIEW_PBA8_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */ +#define REALVIEW_PBA8_WATCHDOG_BASE 0x10010000 /* watchdog interface */ +#define REALVIEW_PBA8_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ +#define REALVIEW_PBA8_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ +#define REALVIEW_PBA8_GPIO0_BASE 0x10013000 /* GPIO port 0 */ +#define REALVIEW_PBA8_RTC_BASE 0x10017000 /* Real Time Clock */ +#define REALVIEW_PBA8_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */ +#define REALVIEW_PBA8_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */ +#define REALVIEW_PBA8_SCTL_BASE 0x1001A000 /* System Controller */ +#define REALVIEW_PBA8_CLCD_BASE 0x10020000 /* CLCD */ +#define REALVIEW_PBA8_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */ +#define REALVIEW_PBA8_DMC_BASE 0x100E0000 /* DMC configuration */ +#define REALVIEW_PBA8_SMC_BASE 0x100E1000 /* SMC configuration */ +#define REALVIEW_PBA8_CAN_BASE 0x100E2000 /* CAN bus */ +#define REALVIEW_PBA8_CF_BASE 0x18000000 /* Compact flash */ +#define REALVIEW_PBA8_CF_MEM_BASE 0x18003000 /* SMC for Compact flash */ +#define REALVIEW_PBA8_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */ +#define REALVIEW_PBA8_FLASH0_BASE 0x40000000 +#define REALVIEW_PBA8_FLASH0_SIZE SZ_64M +#define REALVIEW_PBA8_FLASH1_BASE 0x44000000 +#define REALVIEW_PBA8_FLASH1_SIZE SZ_64M +#define REALVIEW_PBA8_ETH_BASE 0x4E000000 /* Ethernet */ +#define REALVIEW_PBA8_USB_BASE 0x4F000000 /* USB */ +#define REALVIEW_PBA8_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */ +#define REALVIEW_PBA8_LT_BASE 0xC0000000 /* Logic Tile expansion */ +#define REALVIEW_PBA8_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */ +#define REALVIEW_PBA8_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */ + +#define REALVIEW_PBA8_SYS_PLD_CTRL1 0x74 + +/* + * PBA8 PCI regions + */ +#define REALVIEW_PBA8_PCI_BASE 0x90040000 /* PCI-X Unit base */ +#define REALVIEW_PBA8_PCI_IO_BASE 0x90050000 /* IO Region on AHB */ +#define REALVIEW_PBA8_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */ + +#define REALVIEW_PBA8_PCI_BASE_SIZE 0x10000 /* 16 Kb */ +#define REALVIEW_PBA8_PCI_IO_SIZE 0x1000 /* 4 Kb */ +#define REALVIEW_PBA8_PCI_MEM_SIZE 0x20000000 /* 512 MB */ + +/* + * Irqs + */ +#define IRQ_PBA8_GIC_START 32 + +/* L220 +#define IRQ_PBA8_L220_EVENT (IRQ_PBA8_GIC_START + 29) +#define IRQ_PBA8_L220_SLAVE (IRQ_PBA8_GIC_START + 30) +#define IRQ_PBA8_L220_DECODE (IRQ_PBA8_GIC_START + 31) +*/ + +/* + * PB-A8 on-board gic irq sources + */ +#define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */ +#define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */ +#define IRQ_PBA8_COMMRx (IRQ_PBA8_GIC_START + 2) /* Debug Comm Rx interrupt */ +#define IRQ_PBA8_COMMTx (IRQ_PBA8_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 4) /* Timer 0/1 (default timer) */ +#define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 5) /* Timer 2/3 */ +#define IRQ_PBA8_GPIO0 (IRQ_PBA8_GIC_START + 6) /* GPIO 0 */ +#define IRQ_PBA8_GPIO1 (IRQ_PBA8_GIC_START + 7) /* GPIO 1 */ +#define IRQ_PBA8_GPIO2 (IRQ_PBA8_GIC_START + 8) /* GPIO 2 */ + /* 9 reserved */ +#define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 10) /* Real Time Clock */ +#define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */ +#define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 12) /* UART 0 on development chip */ +#define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 13) /* UART 1 on development chip */ +#define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 14) /* UART 2 on development chip */ +#define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 15) /* UART 3 on development chip */ +#define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */ +#define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */ +#define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */ +#define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */ +#define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */ +#define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */ +#define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */ +#define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */ +#define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */ +#define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */ +#define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */ +#define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */ +#define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */ +#define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */ +#define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */ +#define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */ + +/* ... */ +#define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50) +#define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51) +#define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52) +#define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53) + +#define IRQ_PBA8_SMC -1 +#define IRQ_PBA8_SCTL -1 + +#define NR_GIC_PBA8 1 + +/* + * Only define NR_IRQS if less than NR_IRQS_PBA8 + */ +#define NR_IRQS_PBA8 (IRQ_PBA8_GIC_START + 64) + +#if defined(CONFIG_MACH_REALVIEW_PBA8) + +#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBA8) +#undef NR_IRQS +#define NR_IRQS NR_IRQS_PBA8 +#endif + +#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBA8) +#undef MAX_GIC_NR +#define MAX_GIC_NR NR_GIC_PBA8 +#endif + +#endif /* CONFIG_MACH_REALVIEW_PBA8 */ + +#endif /* __ASM_ARCH_BOARD_PBA8_H */ diff --git a/arch/arm/mach-realview/include/mach/clkdev.h b/arch/arm/mach-realview/include/mach/clkdev.h new file mode 100644 index 0000000..04b37a8 --- /dev/null +++ b/arch/arm/mach-realview/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S index 7196bca..92dbcb9 100644 --- a/arch/arm/mach-realview/include/mach/debug-macro.S +++ b/arch/arm/mach-realview/include/mach/debug-macro.S @@ -8,15 +8,36 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * -*/ + */ + +#if defined(CONFIG_MACH_REALVIEW_EB) || \ + defined(CONFIG_MACH_REALVIEW_PB11MP) || \ + defined(CONFIG_MACH_REALVIEW_PBA8) +#ifndef DEBUG_LL_UART_OFFSET +#define DEBUG_LL_UART_OFFSET 0x00009000 +#elif DEBUG_LL_UART_OFFSET != 0x00009000 +#warning "DEBUG_LL_UART_OFFSET already defined to a different value" +#endif +#endif + +#ifdef CONFIG_MACH_REALVIEW_PB1176 +#ifndef DEBUG_LL_UART_OFFSET +#define DEBUG_LL_UART_OFFSET 0x0010c000 +#elif DEBUG_LL_UART_OFFSET != 0x0010c000 +#warning "DEBUG_LL_UART_OFFSET already defined to a different value" +#endif +#endif + +#ifndef DEBUG_LL_UART_OFFSET +#error "Unknown RealView platform" +#endif .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? moveq \rx, #0x10000000 - movne \rx, #0xf0000000 @ virtual base - orr \rx, \rx, #0x00009000 + movne \rx, #0xfb000000 @ virtual base + orr \rx, \rx, #DEBUG_LL_UART_OFFSET .endm #include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-realview/include/mach/dma.h b/arch/arm/mach-realview/include/mach/dma.h deleted file mode 100644 index f1a5a1a..0000000 --- a/arch/arm/mach-realview/include/mach/dma.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * arch/arm/mach-realview/include/mach/dma.h - * - * Copyright (C) 2003 ARM Limited. - * Copyright (C) 1997,1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ diff --git a/arch/arm/mach-realview/include/mach/hardware.h b/arch/arm/mach-realview/include/mach/hardware.h index 79a93b3..b42c14f 100644 --- a/arch/arm/mach-realview/include/mach/hardware.h +++ b/arch/arm/mach-realview/include/mach/hardware.h @@ -25,7 +25,14 @@ #include <asm/sizes.h> /* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) (((x) & 0x0fffffff) + 0xf0000000) +/* + * Statically mapped addresses: + * + * 10xx xxxx -> fbxx xxxx + * 1exx xxxx -> fdxx xxxx + * 1fxx xxxx -> fexx xxxx + */ +#define IO_ADDRESS(x) (((x) & 0x03ffffff) + 0xfb000000) #define __io_address(n) __io(IO_ADDRESS(n)) #endif diff --git a/arch/arm/mach-realview/include/mach/io.h b/arch/arm/mach-realview/include/mach/io.h index aa06942..f05bcdf 100644 --- a/arch/arm/mach-realview/include/mach/io.h +++ b/arch/arm/mach-realview/include/mach/io.h @@ -22,12 +22,7 @@ #define IO_SPACE_LIMIT 0xffffffff -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)addr; -} - -#define __io(a) __io(a) -#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-realview/include/mach/irqs.h b/arch/arm/mach-realview/include/mach/irqs.h index 02a9185..fe5cb98 100644 --- a/arch/arm/mach-realview/include/mach/irqs.h +++ b/arch/arm/mach-realview/include/mach/irqs.h @@ -25,6 +25,7 @@ #include <mach/board-eb.h> #include <mach/board-pb11mp.h> #include <mach/board-pb1176.h> +#include <mach/board-pba8.h> #define IRQ_LOCALTIMER 29 #define IRQ_LOCALWDOG 30 diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h index 0e67348..293c300 100644 --- a/arch/arm/mach-realview/include/mach/memory.h +++ b/arch/arm/mach-realview/include/mach/memory.h @@ -23,16 +23,10 @@ /* * Physical DRAM offset. */ +#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET +#define PHYS_OFFSET UL(0x70000000) +#else #define PHYS_OFFSET UL(0x00000000) - -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#define __virt_to_bus(x) ((x) - PAGE_OFFSET) -#define __bus_to_virt(x) ((x) + PAGE_OFFSET) +#endif #endif diff --git a/arch/arm/mach-realview/include/mach/uncompress.h b/arch/arm/mach-realview/include/mach/uncompress.h index 79f50f2..415d634 100644 --- a/arch/arm/mach-realview/include/mach/uncompress.h +++ b/arch/arm/mach-realview/include/mach/uncompress.h @@ -23,6 +23,7 @@ #include <mach/board-eb.h> #include <mach/board-pb11mp.h> #include <mach/board-pb1176.h> +#include <mach/board-pba8.h> #define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) #define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) @@ -40,6 +41,8 @@ static inline unsigned long get_uart_base(void) return REALVIEW_PB11MP_UART0_BASE; else if (machine_is_realview_pb1176()) return REALVIEW_PB1176_UART0_BASE; + else if (machine_is_realview_pba8()) + return REALVIEW_PBA8_UART0_BASE; else return 0; } diff --git a/arch/arm/mach-realview/include/mach/vmalloc.h b/arch/arm/mach-realview/include/mach/vmalloc.h index 48cbcc87..fe0de1b 100644 --- a/arch/arm/mach-realview/include/mach/vmalloc.h +++ b/arch/arm/mach-realview/include/mach/vmalloc.h @@ -18,4 +18,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END (PAGE_OFFSET + 0x18000000) +#define VMALLOC_END 0xf8000000 diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c index 44d178c..9019ef2 100644 --- a/arch/arm/mach-realview/localtimer.c +++ b/arch/arm/mach-realview/localtimer.c @@ -38,18 +38,14 @@ void local_timer_interrupt(void) #ifdef CONFIG_LOCAL_TIMERS -#define TWD_BASE(cpu) (twd_base_addr + (cpu) * twd_size) - /* set up by the platform code */ -void __iomem *twd_base_addr; -unsigned int twd_size; +void __iomem *twd_base; static unsigned long mpcore_timer_rate; static void local_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *clk) { - void __iomem *base = TWD_BASE(smp_processor_id()); unsigned long ctrl; switch(mode) { @@ -68,17 +64,16 @@ static void local_timer_set_mode(enum clock_event_mode mode, ctrl = 0; } - __raw_writel(ctrl, base + TWD_TIMER_CONTROL); + __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL); } static int local_timer_set_next_event(unsigned long evt, struct clock_event_device *unused) { - void __iomem *base = TWD_BASE(smp_processor_id()); - unsigned long ctrl = __raw_readl(base + TWD_TIMER_CONTROL); + unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL); - __raw_writel(evt, base + TWD_TIMER_COUNTER); - __raw_writel(ctrl | TWD_TIMER_CONTROL_ENABLE, base + TWD_TIMER_CONTROL); + __raw_writel(evt, twd_base + TWD_TIMER_COUNTER); + __raw_writel(ctrl | TWD_TIMER_CONTROL_ENABLE, twd_base + TWD_TIMER_CONTROL); return 0; } @@ -91,19 +86,16 @@ static int local_timer_set_next_event(unsigned long evt, */ int local_timer_ack(void) { - void __iomem *base = TWD_BASE(smp_processor_id()); - - if (__raw_readl(base + TWD_TIMER_INTSTAT)) { - __raw_writel(1, base + TWD_TIMER_INTSTAT); + if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) { + __raw_writel(1, twd_base + TWD_TIMER_INTSTAT); return 1; } return 0; } -static void __cpuinit twd_calibrate_rate(unsigned int cpu) +static void __cpuinit twd_calibrate_rate(void) { - void __iomem *base = TWD_BASE(cpu); unsigned long load, count; u64 waitjiffies; @@ -124,15 +116,15 @@ static void __cpuinit twd_calibrate_rate(unsigned int cpu) waitjiffies += 5; /* enable, no interrupt or reload */ - __raw_writel(0x1, base + TWD_TIMER_CONTROL); + __raw_writel(0x1, twd_base + TWD_TIMER_CONTROL); /* maximum value */ - __raw_writel(0xFFFFFFFFU, base + TWD_TIMER_COUNTER); + __raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER); while (get_jiffies_64() < waitjiffies) udelay(10); - count = __raw_readl(base + TWD_TIMER_COUNTER); + count = __raw_readl(twd_base + TWD_TIMER_COUNTER); mpcore_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5); @@ -142,18 +134,19 @@ static void __cpuinit twd_calibrate_rate(unsigned int cpu) load = mpcore_timer_rate / HZ; - __raw_writel(load, base + TWD_TIMER_LOAD); + __raw_writel(load, twd_base + TWD_TIMER_LOAD); } /* * Setup the local clock events for a CPU. */ -void __cpuinit local_timer_setup(unsigned int cpu) +void __cpuinit local_timer_setup(void) { + unsigned int cpu = smp_processor_id(); struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); unsigned long flags; - twd_calibrate_rate(cpu); + twd_calibrate_rate(); clk->name = "local_timer"; clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; @@ -178,9 +171,9 @@ void __cpuinit local_timer_setup(unsigned int cpu) /* * take a local timer down */ -void __cpuexit local_timer_stop(unsigned int cpu) +void __cpuexit local_timer_stop(void) { - __raw_writel(0, TWD_BASE(cpu) + TWD_TIMER_CONTROL); + __raw_writel(0, twd_base + TWD_TIMER_CONTROL); } #else /* CONFIG_LOCAL_TIMERS */ @@ -190,8 +183,9 @@ static void dummy_timer_set_mode(enum clock_event_mode mode, { } -void __cpuinit local_timer_setup(unsigned int cpu) +void __cpuinit local_timer_setup(void) { + unsigned int cpu = smp_processor_id(); struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); clk->name = "dummy_timer"; diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index e102aeb..8fce85f 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -23,6 +23,8 @@ #include <mach/board-pb11mp.h> #include <mach/scu.h> +#include "core.h" + extern void realview_secondary_startup(void); /* @@ -31,15 +33,20 @@ extern void realview_secondary_startup(void); */ volatile int __cpuinitdata pen_release = -1; +static void __iomem *scu_base_addr(void) +{ + if (machine_is_realview_eb_mp()) + return __io_address(REALVIEW_EB11MP_SCU_BASE); + else if (machine_is_realview_pb11mp()) + return __io_address(REALVIEW_TC11MP_SCU_BASE); + else + return (void __iomem *)0; +} + static unsigned int __init get_core_count(void) { unsigned int ncores; - void __iomem *scu_base = 0; - - if (machine_is_realview_eb() && core_tile_eb11mp()) - scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); - else if (machine_is_realview_pb11mp()) - scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); + void __iomem *scu_base = scu_base_addr(); if (scu_base) { ncores = __raw_readl(scu_base + SCU_CONFIG); @@ -56,14 +63,7 @@ static unsigned int __init get_core_count(void) static void scu_enable(void) { u32 scu_ctrl; - void __iomem *scu_base; - - if (machine_is_realview_eb() && core_tile_eb11mp()) - scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); - else if (machine_is_realview_pb11mp()) - scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); - else - BUG(); + void __iomem *scu_base = scu_base_addr(); scu_ctrl = __raw_readl(scu_base + SCU_CTRL); scu_ctrl |= 1; @@ -88,10 +88,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) * core (e.g. timer irq), then they will not have been enabled * for us: do so */ - if (machine_is_realview_eb() && core_tile_eb11mp()) - gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); - else if (machine_is_realview_pb11mp()) - gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE)); + gic_cpu_init(0, gic_cpu_base_addr); /* * let the primary processor know we're out of the @@ -232,9 +229,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in * realview_timer_init */ - if ((machine_is_realview_eb() && core_tile_eb11mp()) || - machine_is_realview_pb11mp()) - local_timer_setup(cpu); + local_timer_setup(); #endif /* diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index eb829eb..bed39ed 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -108,7 +108,7 @@ static struct map_desc realview_eb11mp_io_desc[] __initdata = { static void __init realview_eb_map_io(void) { iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc)); - if (core_tile_eb11mp()) + if (core_tile_eb11mp() || core_tile_a9mp()) iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc)); } @@ -242,12 +242,6 @@ static struct resource realview_eb_eth_resources[] = { }, }; -static struct platform_device realview_eb_eth_device = { - .id = 0, - .num_resources = ARRAY_SIZE(realview_eb_eth_resources), - .resource = realview_eb_eth_resources, -}; - /* * Detect and register the correct Ethernet device. RealView/EB rev D * platforms use the newer SMSC LAN9118 Ethernet chip @@ -255,26 +249,24 @@ static struct platform_device realview_eb_eth_device = { static int eth_device_register(void) { void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K); + const char *name = NULL; u32 idrev; if (!eth_addr) return -ENOMEM; idrev = readl(eth_addr + 0x50); - if ((idrev & 0xFFFF0000) == 0x01180000) - /* SMSC LAN9118 chip present */ - realview_eb_eth_device.name = "smc911x"; - else - /* SMSC 91C111 chip present */ - realview_eb_eth_device.name = "smc91x"; + if ((idrev & 0xFFFF0000) != 0x01180000) + /* SMSC LAN9118 not present, use LAN91C111 instead */ + name = "smc91x"; iounmap(eth_addr); - return platform_device_register(&realview_eb_eth_device); + return realview_eth_register(name, realview_eb_eth_resources); } static void __init gic_init_irq(void) { - if (core_tile_eb11mp()) { + if (core_tile_eb11mp() || core_tile_a9mp()) { unsigned int pldctrl; /* new irq mode */ @@ -342,10 +334,9 @@ static void __init realview_eb_timer_init(void) timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE); timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20; - if (core_tile_eb11mp()) { + if (core_tile_eb11mp() || core_tile_a9mp()) { #ifdef CONFIG_LOCAL_TIMERS - twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE); - twd_size = REALVIEW_EB11MP_TWD_SIZE; + twd_base = __io_address(REALVIEW_EB11MP_TWD_BASE); #endif timer_irq = IRQ_EB11MP_TIMER0_1; } else @@ -362,7 +353,7 @@ static void __init realview_eb_init(void) { int i; - if (core_tile_eb11mp()) { + if (core_tile_eb11mp() || core_tile_a9mp()) { realview_eb11mp_fixup(); #ifdef CONFIG_CACHE_L2X0 @@ -372,8 +363,6 @@ static void __init realview_eb_init(void) #endif } - clk_register(&realview_clcd_clk); - realview_flash_register(&realview_eb_flash_resource, 1); platform_device_register(&realview_i2c_device); eth_device_register(); @@ -392,7 +381,7 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ .phys_io = REALVIEW_EB_UART0_BASE, .io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, + .boot_params = PHYS_OFFSET + 0x00000100, .map_io = realview_eb_map_io, .init_irq = gic_init_irq, .timer = &realview_eb_timer, diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index cccdb3e..8f0683c 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -222,13 +222,6 @@ static struct resource realview_pb1176_smsc911x_resources[] = { }, }; -static struct platform_device realview_pb1176_smsc911x_device = { - .name = "smc911x", - .id = 0, - .num_resources = ARRAY_SIZE(realview_pb1176_smsc911x_resources), - .resource = realview_pb1176_smsc911x_resources, -}; - static void __init gic_init_irq(void) { /* ARM1176 DevChip GIC, primary */ @@ -265,10 +258,8 @@ static void __init realview_pb1176_init(void) l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff); #endif - clk_register(&realview_clcd_clk); - realview_flash_register(&realview_pb1176_flash_resource, 1); - platform_device_register(&realview_pb1176_smsc911x_device); + realview_eth_register(NULL, realview_pb1176_smsc911x_resources); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; @@ -284,7 +275,7 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ .phys_io = REALVIEW_PB1176_UART0_BASE, .io_pg_offst = (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, + .boot_params = PHYS_OFFSET + 0x00000100, .map_io = realview_pb1176_map_io, .init_irq = gic_init_irq, .timer = &realview_pb1176_timer, diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 8b86314..3ebdb2d 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c @@ -230,13 +230,6 @@ static struct resource realview_pb11mp_smsc911x_resources[] = { }, }; -static struct platform_device realview_pb11mp_smsc911x_device = { - .name = "smc911x", - .id = 0, - .num_resources = ARRAY_SIZE(realview_pb11mp_smsc911x_resources), - .resource = realview_pb11mp_smsc911x_resources, -}; - struct resource realview_pb11mp_cf_resources[] = { [0] = { .start = REALVIEW_PB11MP_CF_BASE, @@ -292,8 +285,7 @@ static void __init realview_pb11mp_timer_init(void) timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20; #ifdef CONFIG_LOCAL_TIMERS - twd_base_addr = __io_address(REALVIEW_TC11MP_TWD_BASE); - twd_size = REALVIEW_TC11MP_TWD_SIZE; + twd_base = __io_address(REALVIEW_TC11MP_TWD_BASE); #endif realview_timer_init(IRQ_TC11MP_TIMER0_1); } @@ -312,11 +304,9 @@ static void __init realview_pb11mp_init(void) l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff); #endif - clk_register(&realview_clcd_clk); - realview_flash_register(realview_pb11mp_flash_resource, ARRAY_SIZE(realview_pb11mp_flash_resource)); - platform_device_register(&realview_pb11mp_smsc911x_device); + realview_eth_register(NULL, realview_pb11mp_smsc911x_resources); platform_device_register(&realview_i2c_device); platform_device_register(&realview_pb11mp_cf_device); @@ -334,7 +324,7 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ .phys_io = REALVIEW_PB11MP_UART0_BASE, .io_pg_offst = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, + .boot_params = PHYS_OFFSET + 0x00000100, .map_io = realview_pb11mp_map_io, .init_irq = gic_init_irq, .timer = &realview_pb11mp_timer, diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c new file mode 100644 index 0000000..34c9443 --- /dev/null +++ b/arch/arm/mach-realview/realview_pba8.c @@ -0,0 +1,300 @@ +/* + * linux/arch/arm/mach-realview/realview_pba8.c + * + * Copyright (C) 2008 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/sysdev.h> +#include <linux/amba/bus.h> +#include <linux/io.h> + +#include <asm/irq.h> +#include <asm/leds.h> +#include <asm/mach-types.h> +#include <asm/hardware/gic.h> +#include <asm/hardware/icst307.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/mmc.h> +#include <asm/mach/time.h> + +#include <mach/hardware.h> +#include <mach/board-pba8.h> +#include <mach/irqs.h> + +#include "core.h" +#include "clock.h" + +static struct map_desc realview_pba8_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(REALVIEW_SYS_BASE), + .pfn = __phys_to_pfn(REALVIEW_SYS_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PBA8_GIC_CPU_BASE), + .pfn = __phys_to_pfn(REALVIEW_PBA8_GIC_CPU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PBA8_GIC_DIST_BASE), + .pfn = __phys_to_pfn(REALVIEW_PBA8_GIC_DIST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), + .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PBA8_TIMER0_1_BASE), + .pfn = __phys_to_pfn(REALVIEW_PBA8_TIMER0_1_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_PBA8_TIMER2_3_BASE), + .pfn = __phys_to_pfn(REALVIEW_PBA8_TIMER2_3_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +#ifdef CONFIG_PCI + { + .virtual = PCIX_UNIT_BASE, + .pfn = __phys_to_pfn(REALVIEW_PBA8_PCI_BASE), + .length = REALVIEW_PBA8_PCI_BASE_SIZE, + .type = MT_DEVICE + }, +#endif +#ifdef CONFIG_DEBUG_LL + { + .virtual = IO_ADDRESS(REALVIEW_PBA8_UART0_BASE), + .pfn = __phys_to_pfn(REALVIEW_PBA8_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +#endif +}; + +static void __init realview_pba8_map_io(void) +{ + iotable_init(realview_pba8_io_desc, ARRAY_SIZE(realview_pba8_io_desc)); +} + +/* + * RealView PBA8Core AMBA devices + */ + +#define GPIO2_IRQ { IRQ_PBA8_GPIO2, NO_IRQ } +#define GPIO2_DMA { 0, 0 } +#define GPIO3_IRQ { IRQ_PBA8_GPIO3, NO_IRQ } +#define GPIO3_DMA { 0, 0 } +#define AACI_IRQ { IRQ_PBA8_AACI, NO_IRQ } +#define AACI_DMA { 0x80, 0x81 } +#define MMCI0_IRQ { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B } +#define MMCI0_DMA { 0x84, 0 } +#define KMI0_IRQ { IRQ_PBA8_KMI0, NO_IRQ } +#define KMI0_DMA { 0, 0 } +#define KMI1_IRQ { IRQ_PBA8_KMI1, NO_IRQ } +#define KMI1_DMA { 0, 0 } +#define PBA8_SMC_IRQ { NO_IRQ, NO_IRQ } +#define PBA8_SMC_DMA { 0, 0 } +#define MPMC_IRQ { NO_IRQ, NO_IRQ } +#define MPMC_DMA { 0, 0 } +#define PBA8_CLCD_IRQ { IRQ_PBA8_CLCD, NO_IRQ } +#define PBA8_CLCD_DMA { 0, 0 } +#define DMAC_IRQ { IRQ_PBA8_DMAC, NO_IRQ } +#define DMAC_DMA { 0, 0 } +#define SCTL_IRQ { NO_IRQ, NO_IRQ } +#define SCTL_DMA { 0, 0 } +#define PBA8_WATCHDOG_IRQ { IRQ_PBA8_WATCHDOG, NO_IRQ } +#define PBA8_WATCHDOG_DMA { 0, 0 } +#define PBA8_GPIO0_IRQ { IRQ_PBA8_GPIO0, NO_IRQ } +#define PBA8_GPIO0_DMA { 0, 0 } +#define GPIO1_IRQ { IRQ_PBA8_GPIO1, NO_IRQ } +#define GPIO1_DMA { 0, 0 } +#define PBA8_RTC_IRQ { IRQ_PBA8_RTC, NO_IRQ } +#define PBA8_RTC_DMA { 0, 0 } +#define SCI_IRQ { IRQ_PBA8_SCI, NO_IRQ } +#define SCI_DMA { 7, 6 } +#define PBA8_UART0_IRQ { IRQ_PBA8_UART0, NO_IRQ } +#define PBA8_UART0_DMA { 15, 14 } +#define PBA8_UART1_IRQ { IRQ_PBA8_UART1, NO_IRQ } +#define PBA8_UART1_DMA { 13, 12 } +#define PBA8_UART2_IRQ { IRQ_PBA8_UART2, NO_IRQ } +#define PBA8_UART2_DMA { 11, 10 } +#define PBA8_UART3_IRQ { IRQ_PBA8_UART3, NO_IRQ } +#define PBA8_UART3_DMA { 0x86, 0x87 } +#define PBA8_SSP_IRQ { IRQ_PBA8_SSP, NO_IRQ } +#define PBA8_SSP_DMA { 9, 8 } + +/* FPGA Primecells */ +AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); +AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); +AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL); +AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL); +AMBA_DEVICE(uart3, "fpga:09", PBA8_UART3, NULL); + +/* DevChip Primecells */ +AMBA_DEVICE(smc, "dev:00", PBA8_SMC, NULL); +AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); +AMBA_DEVICE(wdog, "dev:e1", PBA8_WATCHDOG, NULL); +AMBA_DEVICE(gpio0, "dev:e4", PBA8_GPIO0, NULL); +AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); +AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); +AMBA_DEVICE(rtc, "dev:e8", PBA8_RTC, NULL); +AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); +AMBA_DEVICE(uart0, "dev:f1", PBA8_UART0, NULL); +AMBA_DEVICE(uart1, "dev:f2", PBA8_UART1, NULL); +AMBA_DEVICE(uart2, "dev:f3", PBA8_UART2, NULL); +AMBA_DEVICE(ssp0, "dev:f4", PBA8_SSP, NULL); + +/* Primecells on the NEC ISSP chip */ +AMBA_DEVICE(clcd, "issp:20", PBA8_CLCD, &clcd_plat_data); +AMBA_DEVICE(dmac, "issp:30", DMAC, NULL); + +static struct amba_device *amba_devs[] __initdata = { + &dmac_device, + &uart0_device, + &uart1_device, + &uart2_device, + &uart3_device, + &smc_device, + &clcd_device, + &sctl_device, + &wdog_device, + &gpio0_device, + &gpio1_device, + &gpio2_device, + &rtc_device, + &sci0_device, + &ssp0_device, + &aaci_device, + &mmc0_device, + &kmi0_device, + &kmi1_device, +}; + +/* + * RealView PB-A8 platform devices + */ +static struct resource realview_pba8_flash_resource[] = { + [0] = { + .start = REALVIEW_PBA8_FLASH0_BASE, + .end = REALVIEW_PBA8_FLASH0_BASE + REALVIEW_PBA8_FLASH0_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = REALVIEW_PBA8_FLASH1_BASE, + .end = REALVIEW_PBA8_FLASH1_BASE + REALVIEW_PBA8_FLASH1_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource realview_pba8_smsc911x_resources[] = { + [0] = { + .start = REALVIEW_PBA8_ETH_BASE, + .end = REALVIEW_PBA8_ETH_BASE + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PBA8_ETH, + .end = IRQ_PBA8_ETH, + .flags = IORESOURCE_IRQ, + }, +}; + +struct resource realview_pba8_cf_resources[] = { + [0] = { + .start = REALVIEW_PBA8_CF_BASE, + .end = REALVIEW_PBA8_CF_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = REALVIEW_PBA8_CF_MEM_BASE, + .end = REALVIEW_PBA8_CF_MEM_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = -1, /* FIXME: Find correct irq */ + .end = -1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device realview_pba8_cf_device = { + .name = "compactflash", + .id = 0, + .num_resources = ARRAY_SIZE(realview_pba8_cf_resources), + .resource = realview_pba8_cf_resources, +}; + +static void __init gic_init_irq(void) +{ + /* ARM PB-A8 on-board GIC */ + gic_cpu_base_addr = __io_address(REALVIEW_PBA8_GIC_CPU_BASE); + gic_dist_init(0, __io_address(REALVIEW_PBA8_GIC_DIST_BASE), IRQ_PBA8_GIC_START); + gic_cpu_init(0, __io_address(REALVIEW_PBA8_GIC_CPU_BASE)); +} + +static void __init realview_pba8_timer_init(void) +{ + timer0_va_base = __io_address(REALVIEW_PBA8_TIMER0_1_BASE); + timer1_va_base = __io_address(REALVIEW_PBA8_TIMER0_1_BASE) + 0x20; + timer2_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE); + timer3_va_base = __io_address(REALVIEW_PBA8_TIMER2_3_BASE) + 0x20; + + realview_timer_init(IRQ_PBA8_TIMER0_1); +} + +static struct sys_timer realview_pba8_timer = { + .init = realview_pba8_timer_init, +}; + +static void __init realview_pba8_init(void) +{ + int i; + + realview_flash_register(realview_pba8_flash_resource, + ARRAY_SIZE(realview_pba8_flash_resource)); + realview_eth_register(NULL, realview_pba8_smsc911x_resources); + platform_device_register(&realview_i2c_device); + platform_device_register(&realview_pba8_cf_device); + + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; + amba_device_register(d, &iomem_resource); + } + +#ifdef CONFIG_LEDS + leds_event = realview_leds_event; +#endif +} + +MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8") + /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ + .phys_io = REALVIEW_PBA8_UART0_BASE, + .io_pg_offst = (IO_ADDRESS(REALVIEW_PBA8_UART0_BASE) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x00000100, + .map_io = realview_pba8_map_io, + .init_irq = gic_init_irq, + .timer = &realview_pba8_timer, + .init_machine = realview_pba8_init, +MACHINE_END diff --git a/arch/arm/mach-rpc/include/mach/io.h b/arch/arm/mach-rpc/include/mach/io.h index 9f0553b..20da7f4 100644 --- a/arch/arm/mach-rpc/include/mach/io.h +++ b/arch/arm/mach-rpc/include/mach/io.h @@ -18,49 +18,6 @@ #define IO_SPACE_LIMIT 0xffffffff /* - * GCC is totally crap at loading/storing data. We try to persuade it - * to do the right thing by using these whereever possible instead of - * the above. - */ -#define __arch_base_getb(b,o) \ - ({ \ - unsigned int __v, __r = (b); \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2]" \ - : "=r" (__v) \ - : "r" (__r), "Ir" (o)); \ - __v; \ - }) - -#define __arch_base_getl(b,o) \ - ({ \ - unsigned int __v, __r = (b); \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2]" \ - : "=r" (__v) \ - : "r" (__r), "Ir" (o)); \ - __v; \ - }) - -#define __arch_base_putb(v,b,o) \ - ({ \ - unsigned int __r = (b); \ - __asm__ __volatile__( \ - "strb %0, [%1, %2]" \ - : \ - : "r" (v), "r" (__r), "Ir" (o));\ - }) - -#define __arch_base_putl(v,b,o) \ - ({ \ - unsigned int __r = (b); \ - __asm__ __volatile__( \ - "str %0, [%1, %2]" \ - : \ - : "r" (v), "r" (__r), "Ir" (o));\ - }) - -/* * We use two different types of addressing - PC style addresses, and ARM * addresses. PC style accesses the PC hardware with the normal PC IO * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+ @@ -232,15 +189,13 @@ DECLARE_IO(int,l,"") result; \ }) -#define __ioaddrc(port) __ioaddr(port) - #define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) #define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) #define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) #define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) #define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) #define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) -#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) + /* the following macro is deprecated */ #define ioaddr(port) ((unsigned long)__ioaddr((port))) diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h index 4ce6ca9..3d20374 100644 --- a/arch/arm/mach-rpc/include/mach/irqs.h +++ b/arch/arm/mach-rpc/include/mach/irqs.h @@ -44,3 +44,4 @@ #define IRQ_TIMER IRQ_TIMER0 +#define NR_IRQS 128 diff --git a/arch/arm/mach-rpc/include/mach/dma.h b/arch/arm/mach-rpc/include/mach/isa-dma.h index 360b56f..bad7205 100644 --- a/arch/arm/mach-rpc/include/mach/dma.h +++ b/arch/arm/mach-rpc/include/mach/isa-dma.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-rpc/include/mach/dma.h + * arch/arm/mach-rpc/include/mach/isa-dma.h * * Copyright (C) 1997 Russell King * @@ -10,12 +10,6 @@ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H -/* - * This is the maximum DMA address that can be DMAd to. - * There should not be more than (0xd0000000 - 0xc0000000) - * bytes of RAM. - */ -#define MAX_DMA_ADDRESS 0xd0000000 #define MAX_DMA_CHANNELS 8 #define DMA_0 0 diff --git a/arch/arm/mach-rpc/include/mach/memory.h b/arch/arm/mach-rpc/include/mach/memory.h index 9bf7e43..78191bf 100644 --- a/arch/arm/mach-rpc/include/mach/memory.h +++ b/arch/arm/mach-rpc/include/mach/memory.h @@ -24,13 +24,6 @@ #define PHYS_OFFSET UL(0x10000000) /* - * These are exactly the same on the RiscPC as the - * physical memory view. - */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - -/* * Cache flushing area - ROM */ #define FLUSH_BASE_PHYS 0x00000000 diff --git a/arch/arm/mach-s3c2400/include/mach/memory.h b/arch/arm/mach-s3c2400/include/mach/memory.h index 8f4878e..cf5901f 100644 --- a/arch/arm/mach-s3c2400/include/mach/memory.h +++ b/arch/arm/mach-s3c2400/include/mach/memory.h @@ -17,7 +17,4 @@ #define PHYS_OFFSET UL(0x0C000000) -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - #endif diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 99fdc73..63a30d1 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig @@ -7,6 +7,7 @@ config CPU_S3C2410 bool depends on ARCH_S3C2410 + select CPU_ARM920T select S3C2410_CLOCK select S3C2410_GPIO select CPU_LLSERIAL_S3C2410 @@ -32,11 +33,6 @@ config S3C2410_GPIO help GPIO code for S3C2410 and similar processors -config S3C2410_CLOCK - bool - help - Clock code for the S3C2410, and similar processors - config SIMTEC_NOR bool help @@ -84,6 +80,7 @@ config ARCH_BAST select PM_SIMTEC if PM select SIMTEC_NOR select MACH_BAST_IDE + select S3C24XX_DCLK select ISA help Say Y here if you are using the Simtec Electronics EB2410ITX @@ -121,6 +118,7 @@ config MACH_TCT_HAMMER config MACH_VR1000 bool "Thorcom VR1000" select PM_SIMTEC if PM + select S3C24XX_DCLK select SIMTEC_NOR select MACH_BAST_IDE select CPU_S3C2410 diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 00f31f8..fca02f8 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o obj-$(CONFIG_S3C2410_GPIO) += gpio.o -obj-$(CONFIG_S3C2410_CLOCK) += clock.o # Machine support diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index 7d914a4..552b4c7 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c @@ -17,7 +17,6 @@ #include <linux/sysdev.h> #include <linux/serial_core.h> -#include <asm/dma.h> #include <mach/dma.h> #include <plat/cpu.h> @@ -25,12 +24,12 @@ #include <plat/regs-serial.h> #include <mach/regs-gpio.h> -#include <asm/plat-s3c/regs-ac97.h> +#include <plat/regs-ac97.h> #include <mach/regs-mem.h> #include <mach/regs-lcd.h> #include <mach/regs-sdi.h> #include <asm/plat-s3c24xx/regs-iis.h> -#include <asm/plat-s3c24xx/regs-spi.h> +#include <plat/regs-spi.h> static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = { [DMACH_XD0] = { diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h index 891b53c..13358ce 100644 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ b/arch/arm/mach-s3c2410/include/mach/dma.h @@ -16,11 +16,6 @@ #include <linux/sysdev.h> #include <mach/hardware.h> -/* - * This is the maximum DMA address(physical address) that can be DMAd to. - * - */ -#define MAX_DMA_ADDRESS 0x40000000 #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ /* We use `virtual` dma channels to hide the fact we have only a limited @@ -254,7 +249,7 @@ typedef unsigned long dma_device_t; * request a dma channel exclusivley */ -extern int s3c2410_dma_request(dmach_t channel, +extern int s3c2410_dma_request(unsigned int channel, struct s3c2410_dma_client *, void *dev); @@ -263,14 +258,14 @@ extern int s3c2410_dma_request(dmach_t channel, * change the state of the dma channel */ -extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op); +extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op); /* s3c2410_dma_setflags * * set the channel's flags to a given state */ -extern int s3c2410_dma_setflags(dmach_t channel, +extern int s3c2410_dma_setflags(unsigned int channel, unsigned int flags); /* s3c2410_dma_free @@ -278,7 +273,7 @@ extern int s3c2410_dma_setflags(dmach_t channel, * free the dma channel (will also abort any outstanding operations) */ -extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *); +extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *); /* s3c2410_dma_enqueue * @@ -287,7 +282,7 @@ extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *); * drained before the buffer is given to the DMA system. */ -extern int s3c2410_dma_enqueue(dmach_t channel, void *id, +extern int s3c2410_dma_enqueue(unsigned int channel, void *id, dma_addr_t data, int size); /* s3c2410_dma_config @@ -295,7 +290,7 @@ extern int s3c2410_dma_enqueue(dmach_t channel, void *id, * configure the dma channel */ -extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon); +extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon); /* s3c2410_dma_devconfig * @@ -310,11 +305,11 @@ extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, * get the position that the dma transfer is currently at */ -extern int s3c2410_dma_getposition(dmach_t channel, +extern int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dest); -extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn); -extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); +extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn); +extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn); /* DMA Register definitions */ diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-core.h new file mode 100644 index 0000000..6c9fbb9 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h @@ -0,0 +1,34 @@ +/* arch/arm/mach-s3c24100/include/mach/gpio-core.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C2410 - GPIO core support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_GPIO_CORE_H +#define __ASM_ARCH_GPIO_CORE_H __FILE__ + +#include <plat/gpio-core.h> +#include <mach/regs-gpio.h> + +extern struct s3c_gpio_chip s3c24xx_gpios[]; + +static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin) +{ + struct s3c_gpio_chip *chip; + + if (pin > S3C2410_GPG10) + return NULL; + + chip = &s3c24xx_gpios[pin/32]; + return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL; +} + +#endif /* __ASM_ARCH_GPIO_CORE_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h index 3b52b86..e0349af 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio.h @@ -15,4 +15,10 @@ #define gpio_set_value __gpio_set_value #define gpio_cansleep __gpio_cansleep +/* some boards require extra gpio capacity to support external + * devices that need GPIO. + */ + +#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) + #include <asm-generic/gpio.h> diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h index 950c71b..9565903 100644 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h @@ -134,6 +134,8 @@ #define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ #define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ +#define IRQ_HSMMC0 IRQ_S3C2443_HSMMC + #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) #define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) #define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) @@ -160,6 +162,12 @@ #define NR_IRQS (IRQ_S3C2440_AC97+1) #endif +/* compatibility define. */ +#define IRQ_UART3 IRQ_S3C2443_UART3 +#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3 +#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 +#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 + /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ #define FIQ_START IRQ_EINT0 diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index 23c470c..255fdfe 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -13,34 +13,20 @@ #ifndef __ASM_ARCH_MAP_H #define __ASM_ARCH_MAP_H +#include <plat/map-base.h> #include <plat/map.h> #define S3C2410_ADDR(x) S3C_ADDR(x) -/* interrupt controller is the first thing we put in, to make - * the assembly code for the irq detection easier - */ -#define S3C24XX_VA_IRQ S3C_VA_IRQ -#define S3C2410_PA_IRQ (0x4A000000) -#define S3C24XX_SZ_IRQ SZ_1M - -/* memory controller registers */ -#define S3C24XX_VA_MEMCTRL S3C_VA_MEM -#define S3C2410_PA_MEMCTRL (0x48000000) -#define S3C24XX_SZ_MEMCTRL SZ_1M - /* USB host controller */ #define S3C2410_PA_USBHOST (0x49000000) -#define S3C24XX_SZ_USBHOST SZ_1M /* DMA controller */ #define S3C2410_PA_DMA (0x4B000000) #define S3C24XX_SZ_DMA SZ_1M /* Clock and Power management */ -#define S3C24XX_VA_CLKPWR S3C_VA_SYS #define S3C2410_PA_CLKPWR (0x4C000000) -#define S3C24XX_SZ_CLKPWR SZ_1M /* LCD controller */ #define S3C2410_PA_LCD (0x4D000000) @@ -48,48 +34,12 @@ /* NAND flash controller */ #define S3C2410_PA_NAND (0x4E000000) -#define S3C24XX_SZ_NAND SZ_1M - -/* UARTs */ -#define S3C24XX_VA_UART S3C_VA_UART -#define S3C2410_PA_UART (0x50000000) -#define S3C24XX_SZ_UART SZ_1M - -/* Timers */ -#define S3C24XX_VA_TIMER S3C_VA_TIMER -#define S3C2410_PA_TIMER (0x51000000) -#define S3C24XX_SZ_TIMER SZ_1M - -/* USB Device port */ -#define S3C2410_PA_USBDEV (0x52000000) -#define S3C24XX_SZ_USBDEV SZ_1M - -/* Watchdog */ -#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG -#define S3C2410_PA_WATCHDOG (0x53000000) -#define S3C24XX_SZ_WATCHDOG SZ_1M /* IIC hardware controller */ #define S3C2410_PA_IIC (0x54000000) -#define S3C24XX_SZ_IIC SZ_1M /* IIS controller */ #define S3C2410_PA_IIS (0x55000000) -#define S3C24XX_SZ_IIS SZ_1M - -/* GPIO ports */ - -/* the calculation for the VA of this must ensure that - * it is the same distance apart from the UART in the - * phsyical address space, as the initial mapping for the IO - * is done as a 1:1 maping. This puts it (currently) at - * 0xFA800000, which is not in the way of any current mapping - * by the base system. -*/ - -#define S3C2410_PA_GPIO (0x56000000) -#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) -#define S3C24XX_SZ_GPIO SZ_1M /* RTC */ #define S3C2410_PA_RTC (0x57000000) @@ -97,15 +47,12 @@ /* ADC */ #define S3C2410_PA_ADC (0x58000000) -#define S3C24XX_SZ_ADC SZ_1M /* SPI */ #define S3C2410_PA_SPI (0x59000000) -#define S3C24XX_SZ_SPI SZ_1M /* SDI */ #define S3C2410_PA_SDI (0x5A000000) -#define S3C24XX_SZ_SDI SZ_1M /* CAMIF */ #define S3C2440_PA_CAMIF (0x4F000000) @@ -120,13 +67,6 @@ #define S3C2443_PA_HSMMC (0x4A800000) #define S3C2443_SZ_HSMMC (256) -/* ISA style IO, for each machine to sort out mappings for, if it - * implements it. We reserve two 16M regions for ISA. - */ - -#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) -#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) - /* physical addresses of all the chip-select areas */ #define S3C2410_CS0 (0x00000000) @@ -152,27 +92,16 @@ #define S3C24XX_PA_TIMER S3C2410_PA_TIMER #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG -#define S3C24XX_PA_IIC S3C2410_PA_IIC #define S3C24XX_PA_IIS S3C2410_PA_IIS #define S3C24XX_PA_GPIO S3C2410_PA_GPIO #define S3C24XX_PA_RTC S3C2410_PA_RTC #define S3C24XX_PA_ADC S3C2410_PA_ADC #define S3C24XX_PA_SPI S3C2410_PA_SPI +#define S3C24XX_PA_SDI S3C2410_PA_SDI +#define S3C24XX_PA_NAND S3C2410_PA_NAND -/* deal with the registers that move under the 2412/2413 */ - -#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) -#ifndef __ASSEMBLY__ -extern void __iomem *s3c24xx_va_gpio2; -#endif -#ifdef CONFIG_CPU_S3C2412_ONLY -#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) -#else -#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 -#endif -#else -#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO -#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO -#endif +#define S3C_PA_IIC S3C2410_PA_IIC +#define S3C_PA_UART S3C24XX_PA_UART +#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/memory.h b/arch/arm/mach-s3c2410/include/mach/memory.h index 9378262..6f1e587 100644 --- a/arch/arm/mach-s3c2410/include/mach/memory.h +++ b/arch/arm/mach-s3c2410/include/mach/memory.h @@ -13,7 +13,4 @@ #define PHYS_OFFSET UL(0x30000000) -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - #endif diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h index b3f90aa..2a5d90e 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h @@ -42,13 +42,6 @@ #define S3C2410_CLKCON_IIS (1<<17) #define S3C2410_CLKCON_SPI (1<<18) -#define S3C2410_PLLCON_MDIVSHIFT 12 -#define S3C2410_PLLCON_PDIVSHIFT 4 -#define S3C2410_PLLCON_SDIVSHIFT 0 -#define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) -#define S3C2410_PLLCON_PDIVMASK ((1<<5)-1) -#define S3C2410_PLLCON_SDIVMASK 3 - /* DCLKCON register addresses in gpio.h */ #define S3C2410_DCLKCON_DCLK0EN (1<<0) @@ -76,32 +69,6 @@ #define S3C2410_CLKSLOW_SLOWVAL(x) (x) #define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) -#ifndef __ASSEMBLY__ - -#include <asm/div64.h> - -static inline unsigned int -s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) -{ - unsigned int mdiv, pdiv, sdiv; - uint64_t fvco; - - mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT; - pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT; - sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT; - - mdiv &= S3C2410_PLLCON_MDIVMASK; - pdiv &= S3C2410_PLLCON_PDIVMASK; - sdiv &= S3C2410_PLLCON_SDIVMASK; - - fvco = (uint64_t)baseclk * (mdiv + 8); - do_div(fvco, (pdiv + 2) << sdiv); - - return (unsigned int)fvco; -} - -#endif /* __ASSEMBLY__ */ - #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) /* extra registers */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index 528080c..3210776 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h @@ -1053,13 +1053,6 @@ #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) -/* values for S3C2410_EXTINT0/1/2 */ -#define S3C2410_EXTINT_LOWLEV (0x00) -#define S3C2410_EXTINT_HILEV (0x01) -#define S3C2410_EXTINT_FALLEDGE (0x02) -#define S3C2410_EXTINT_RISEEDGE (0x04) -#define S3C2410_EXTINT_BOTHEDGE (0x06) - /* interrupt filtering conrrol for EINT16..EINT23 */ #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h index 46d46f5..774f3ad 100644 --- a/arch/arm/mach-s3c2410/include/mach/spi.h +++ b/arch/arm/mach-s3c2410/include/mach/spi.h @@ -22,5 +22,12 @@ struct s3c2410_spi_info { void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol); }; +/* Standard setup / suspend routines for SPI GPIO pins. */ + +extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, + int enable); + +extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, + int enable); #endif /* __ASM_ARCH_SPI_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h index 43535a0..7613d0a 100644 --- a/arch/arm/mach-s3c2410/include/mach/system-reset.h +++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h @@ -13,7 +13,7 @@ #include <mach/hardware.h> #include <linux/io.h> -#include <asm/plat-s3c/regs-watchdog.h> +#include <plat/regs-watchdog.h> #include <mach/regs-clock.h> #include <linux/clk.h> diff --git a/arch/arm/mach-s3c2410/include/mach/tick.h b/arch/arm/mach-s3c2410/include/mach/tick.h new file mode 100644 index 0000000..544da41 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/tick.h @@ -0,0 +1,15 @@ +/* linux/arch/arm/mach-s3c2410/include/mach/tick.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C2410 - timer tick support + */ + +#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0)) + +static inline int s3c24xx_ostimer_pending(void) +{ + return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4; +} diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h index ab39491..c943210 100644 --- a/arch/arm/mach-s3c2410/include/mach/uncompress.h +++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h @@ -1,3 +1,4 @@ + /* arch/arm/mach-s3c2410/include/mach/uncompress.h * * Copyright (c) 2003, 2007 Simtec Electronics diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c index d061fea..6d6995a 100644 --- a/arch/arm/mach-s3c2410/mach-amlm5900.c +++ b/arch/arm/mach-s3c2410/mach-amlm5900.c @@ -52,6 +52,7 @@ #include <mach/regs-lcd.h> #include <mach/regs-gpio.h> +#include <plat/iic.h> #include <plat/devs.h> #include <plat/cpu.h> @@ -150,7 +151,7 @@ static struct platform_device *amlm5900_devices[] __initdata = { #endif &s3c_device_adc, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_usb, &s3c_device_rtc, &s3c_device_usbgadget, @@ -233,6 +234,7 @@ static void __init amlm5900_init(void) #ifdef CONFIG_FB_S3C2410 s3c24xx_fb_set_platdata(&amlm5900_fb_info); #endif + s3c_i2c0_set_platdata(NULL); platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices)); } diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index 8db9c70..01bd767 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -44,8 +44,8 @@ #include <mach/regs-mem.h> #include <mach/regs-lcd.h> -#include <asm/plat-s3c/nand.h> -#include <asm/plat-s3c/iic.h> +#include <plat/nand.h> +#include <plat/iic.h> #include <mach/fb.h> #include <linux/mtd/mtd.h> @@ -406,7 +406,7 @@ static struct platform_device bast_sio = { * standard 100KHz i2c bus frequency */ -static struct s3c2410_platform_i2c bast_i2c_info = { +static struct s3c2410_platform_i2c __initdata bast_i2c_info = { .flags = 0, .slave_addr = 0x10, .bus_freq = 100*1000, @@ -553,7 +553,7 @@ static struct platform_device *bast_devices[] __initdata = { &s3c_device_usb, &s3c_device_lcd, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_rtc, &s3c_device_nand, &bast_device_dm9k, @@ -588,7 +588,8 @@ static void __init bast_map_io(void) s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); s3c_device_nand.dev.platform_data = &bast_nand_info; - s3c_device_i2c.dev.platform_data = &bast_i2c_info; + + s3c_i2c0_set_platdata(&bast_i2c_info); s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); s3c24xx_init_clocks(0); diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 98716d0..821a166 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -38,11 +38,13 @@ #include <mach/h1940.h> #include <mach/h1940-latch.h> #include <mach/fb.h> -#include <asm/plat-s3c24xx/udc.h> +#include <plat/udc.h> +#include <plat/iic.h> #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <plat/pll.h> #include <plat/pm.h> static struct map_desc h1940_iodesc[] __initdata = { @@ -183,7 +185,7 @@ static struct platform_device *h1940_devices[] __initdata = { &s3c_device_usb, &s3c_device_lcd, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_iis, &s3c_device_usbgadget, &s3c_device_leds, @@ -215,6 +217,7 @@ static void __init h1940_init(void) s3c24xx_fb_set_platdata(&h1940_fb_info); s3c24xx_udc_set_platdata(&h1940_udc_cfg); + s3c_i2c0_set_platdata(NULL); /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ @@ -223,10 +226,9 @@ static void __init h1940_init(void) S3C2410_MISCCR_USBSUSPND0 | S3C2410_MISCCR_USBSUSPND1, 0x0); - tmp = ( - 0x78 << S3C2410_PLLCON_MDIVSHIFT) - | (0x02 << S3C2410_PLLCON_PDIVSHIFT) - | (0x03 << S3C2410_PLLCON_SDIVSHIFT); + tmp = (0x78 << S3C24XX_PLLCON_MDIVSHIFT) + | (0x02 << S3C24XX_PLLCON_PDIVSHIFT) + | (0x03 << S3C24XX_PLLCON_SDIVSHIFT); writel(tmp, S3C2410_UPLLCON); platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices)); diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 8250551..05a5e87 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c @@ -17,7 +17,6 @@ #include <linux/kernel.h> #include <linux/types.h> -#include <linux/delay.h> #include <linux/gpio_keys.h> #include <linux/init.h> #include <linux/input.h> @@ -40,14 +39,14 @@ #include <asm/mach/irq.h> #include <asm/mach/map.h> -#include <asm/plat-s3c/iic.h> +#include <plat/iic.h> #include <plat/regs-serial.h> #include <plat/clock.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/s3c2410.h> -#include <asm/plat-s3c24xx/udc.h> +#include <plat/udc.h> static struct map_desc n30_iodesc[] __initdata = { /* nothing here yet */ @@ -320,7 +319,7 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = { static struct platform_device *n30_devices[] __initdata = { &s3c_device_lcd, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_iis, &s3c_device_usb, &s3c_device_usbgadget, @@ -332,7 +331,7 @@ static struct platform_device *n30_devices[] __initdata = { static struct platform_device *n35_devices[] __initdata = { &s3c_device_lcd, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_iis, &s3c_device_usbgadget, &n35_button_device, @@ -501,7 +500,7 @@ static void __init n30_init_irq(void) static void __init n30_init(void) { s3c24xx_fb_set_platdata(&n30_fb_info); - s3c_device_i2c.dev.platform_data = &n30_i2ccfg; + s3c_device_i2c0.dev.platform_data = &n30_i2ccfg; s3c24xx_udc_set_platdata(&n30_udc_cfg); /* Turn off suspend on both USB ports, and switch the diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c index d8255cf..f6c7261 100644 --- a/arch/arm/mach-s3c2410/mach-otom.c +++ b/arch/arm/mach-s3c2410/mach-otom.c @@ -35,6 +35,7 @@ #include <plat/s3c2410.h> #include <plat/clock.h> #include <plat/devs.h> +#include <plat/iic.h> #include <plat/cpu.h> static struct map_desc otom11_iodesc[] __initdata = { @@ -94,7 +95,7 @@ static struct platform_device *otom11_devices[] __initdata = { &s3c_device_usb, &s3c_device_lcd, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_iis, &s3c_device_rtc, &otom_device_nor, @@ -109,6 +110,7 @@ static void __init otom11_map_io(void) static void __init otom11_init(void) { + s3c_i2c0_set_platdata(NULL); platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices)); } diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index 661807e..9678a53 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c @@ -50,10 +50,11 @@ #include <mach/leds-gpio.h> #include <plat/regs-serial.h> #include <mach/fb.h> -#include <asm/plat-s3c/nand.h> -#include <asm/plat-s3c24xx/udc.h> +#include <plat/nand.h> +#include <plat/udc.h> #include <mach/spi.h> #include <mach/spi-gpio.h> +#include <plat/iic.h> #include <plat/common-smdk.h> #include <plat/devs.h> @@ -247,7 +248,7 @@ static struct platform_device *qt2410_devices[] __initdata = { &s3c_device_usb, &s3c_device_lcd, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_iis, &s3c_device_sdi, &s3c_device_usbgadget, @@ -349,6 +350,7 @@ static void __init qt2410_machine_init(void) s3c2410_gpio_setpin(S3C2410_GPB0, 1); s3c24xx_udc_set_platdata(&qt2410_udc_cfg); + s3c_i2c0_set_platdata(NULL); s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c index 152527b..c49126c 100644 --- a/arch/arm/mach-s3c2410/mach-smdk2410.c +++ b/arch/arm/mach-s3c2410/mach-smdk2410.c @@ -47,6 +47,7 @@ #include <asm/mach-types.h> #include <plat/regs-serial.h> +#include <plat/iic.h> #include <plat/devs.h> #include <plat/cpu.h> @@ -89,7 +90,7 @@ static struct platform_device *smdk2410_devices[] __initdata = { &s3c_device_usb, &s3c_device_lcd, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_iis, }; @@ -102,6 +103,7 @@ static void __init smdk2410_map_io(void) static void __init smdk2410_init(void) { + s3c_i2c0_set_platdata(NULL); platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices)); smdk_machine_init(); } diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c index 309dcf4..8fdb043 100644 --- a/arch/arm/mach-s3c2410/mach-tct_hammer.c +++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c @@ -45,6 +45,7 @@ #include <asm/mach-types.h> #include <plat/regs-serial.h> +#include <plat/iic.h> #include <plat/devs.h> #include <plat/cpu.h> @@ -127,7 +128,7 @@ static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = { static struct platform_device *tct_hammer_devices[] __initdata = { &s3c_device_adc, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_usb, &s3c_device_rtc, &s3c_device_usbgadget, @@ -146,6 +147,7 @@ static void __init tct_hammer_map_io(void) static void __init tct_hammer_init(void) { + s3c_i2c0_set_platdata(NULL); platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices)); } diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 941353a..61a1ea9 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c @@ -47,6 +47,7 @@ #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <plat/iic.h> #include "usb-simtec.h" #include "nor-simtec.h" @@ -334,7 +335,7 @@ static struct platform_device *vr1000_devices[] __initdata = { &s3c_device_usb, &s3c_device_lcd, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_adc, &serial_device, &vr1000_dm9k0, @@ -384,6 +385,7 @@ static void __init vr1000_map_io(void) static void __init vr1000_init(void) { + s3c_i2c0_set_platdata(NULL); platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices)); i2c_register_board_info(0, vr1000_i2c_devs, diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index ac79b53..feb141b1 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c @@ -16,6 +16,7 @@ #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> +#include <linux/clk.h> #include <linux/sysdev.h> #include <linux/serial_core.h> #include <linux/platform_device.h> @@ -28,6 +29,8 @@ #include <mach/hardware.h> #include <asm/irq.h> +#include <plat/cpu-freq.h> + #include <mach/regs-clock.h> #include <plat/regs-serial.h> @@ -35,6 +38,7 @@ #include <plat/cpu.h> #include <plat/devs.h> #include <plat/clock.h> +#include <plat/pll.h> /* Initial IO mappings */ @@ -59,25 +63,28 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no) * machine specific initialisation. */ -void __init s3c2410_map_io(struct map_desc *mach_desc, int mach_size) +void __init s3c2410_map_io(void) { - /* register our io-tables */ - iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); - iotable_init(mach_desc, mach_size); } -void __init s3c2410_init_clocks(int xtal) +void __init_or_cpufreq s3c2410_setup_clocks(void) { + struct clk *xtal_clk; unsigned long tmp; + unsigned long xtal; unsigned long fclk; unsigned long hclk; unsigned long pclk; + xtal_clk = clk_get(NULL, "xtal"); + xtal = clk_get_rate(xtal_clk); + clk_put(xtal_clk); + /* now we've got our machine bits initialised, work out what * clocks we've got */ - fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); + fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); tmp = __raw_readl(S3C2410_CLKDIVN); @@ -95,7 +102,13 @@ void __init s3c2410_init_clocks(int xtal) * console to use them */ - s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); + s3c24xx_setup_clocks(fclk, hclk, pclk); +} + +void __init s3c2410_init_clocks(int xtal) +{ + s3c24xx_register_baseclocks(xtal); + s3c2410_setup_clocks(); s3c2410_baseclk_add(); } diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig index c59a9d2..ca99564 100644 --- a/arch/arm/mach-s3c2412/Kconfig +++ b/arch/arm/mach-s3c2412/Kconfig @@ -7,6 +7,7 @@ config CPU_S3C2412 bool depends on ARCH_S3C2410 + select CPU_ARM926T select CPU_LLSERIAL_S3C2440 select S3C2412_PM if PM select S3C2412_DMA if S3C2410_DMA diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c index 96d9eb1..a037df5 100644 --- a/arch/arm/mach-s3c2412/clock.c +++ b/arch/arm/mach-s3c2412/clock.c @@ -93,12 +93,6 @@ static int s3c2412_upll_enable(struct clk *clk, int enable) /* clock selections */ -/* CPU EXTCLK input */ -static struct clk clk_ext = { - .name = "extclk", - .id = -1, -}; - static struct clk clk_erefclk = { .name = "erefclk", .id = -1, @@ -773,5 +767,6 @@ int __init s3c2412_baseclk_add(void) s3c2412_clkcon_enable(clkp, 0); } + s3c_pwmclk_init(); return 0; } diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c index ba0591e..919856c 100644 --- a/arch/arm/mach-s3c2412/dma.c +++ b/arch/arm/mach-s3c2412/dma.c @@ -18,7 +18,6 @@ #include <linux/serial_core.h> #include <linux/io.h> -#include <asm/dma.h> #include <mach/dma.h> #include <plat/dma.h> @@ -26,13 +25,13 @@ #include <plat/regs-serial.h> #include <mach/regs-gpio.h> -#include <asm/plat-s3c/regs-ac97.h> +#include <plat/regs-ac97.h> #include <mach/regs-mem.h> #include <mach/regs-lcd.h> #include <mach/regs-sdi.h> #include <asm/plat-s3c24xx/regs-s3c2412-iis.h> #include <asm/plat-s3c24xx/regs-iis.h> -#include <asm/plat-s3c24xx/regs-spi.h> +#include <plat/regs-spi.h> #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID } diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index b08f18c..ecddbbb 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c @@ -17,7 +17,6 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/sysdev.h> -#include <linux/delay.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/i2c.h> @@ -31,8 +30,8 @@ #include <asm/mach/irq.h> #include <plat/regs-serial.h> -#include <asm/plat-s3c/nand.h> -#include <asm/plat-s3c/iic.h> +#include <plat/nand.h> +#include <plat/iic.h> #include <mach/regs-power.h> #include <mach/regs-gpio.h> @@ -52,7 +51,8 @@ #include <plat/devs.h> #include <plat/cpu.h> #include <plat/pm.h> -#include <asm/plat-s3c24xx/udc.h> +#include <plat/udc.h> +#include <plat/iic.h> static struct map_desc jive_iodesc[] __initdata = { }; @@ -398,11 +398,12 @@ static struct s3c2410_spigpio_info jive_lcd_spi = { .bus_num = 1, .pin_clk = S3C2410_GPG8, .pin_mosi = S3C2410_GPB8, + .num_chipselect = 1, .chip_select = jive_lcd_spi_chipselect, }; static struct platform_device jive_device_lcdspi = { - .name = "s3c24xx-spi-gpio", + .name = "spi_s3c24xx_gpio", .id = 1, .num_resources = 0, .dev.platform_data = &jive_lcd_spi, @@ -419,11 +420,12 @@ static struct s3c2410_spigpio_info jive_wm8750_spi = { .bus_num = 2, .pin_clk = S3C2410_GPB4, .pin_mosi = S3C2410_GPB9, + .num_chipselect = 1, .chip_select = jive_wm8750_chipselect, }; static struct platform_device jive_device_wm8750 = { - .name = "s3c24xx-spi-gpio", + .name = "spi_s3c24xx_gpio", .id = 2, .num_resources = 0, .dev.platform_data = &jive_wm8750_spi, @@ -450,14 +452,14 @@ static struct spi_board_info __initdata jive_spi_devs[] = { /* I2C bus and device configuration. */ -static struct s3c2410_platform_i2c jive_i2c_cfg = { +static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = { .max_freq = 80 * 1000, .bus_freq = 50 * 1000, .flags = S3C_IICFLG_FILTER, .sda_delay = 2, }; -static struct i2c_board_info jive_i2c_devs[] = { +static struct i2c_board_info jive_i2c_devs[] __initdata = { [0] = { I2C_BOARD_INFO("lis302dl", 0x1c), .irq = IRQ_EINT14, @@ -470,7 +472,7 @@ static struct platform_device *jive_devices[] __initdata = { &s3c_device_usb, &s3c_device_rtc, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_lcd, &jive_device_lcdspi, &jive_device_wm8750, @@ -663,7 +665,7 @@ static void __init jive_machine_init(void) spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs)); - s3c_device_i2c.dev.platform_data = &jive_i2c_cfg; + s3c_i2c0_set_platdata(&jive_i2c_cfg); i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs)); pm_power_off = jive_power_off; diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c index c719b5a7..eba66aa 100644 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c @@ -37,7 +37,8 @@ #include <mach/regs-lcd.h> #include <mach/idle.h> -#include <asm/plat-s3c24xx/udc.h> +#include <plat/udc.h> +#include <plat/iic.h> #include <mach/fb.h> #include <plat/s3c2410.h> @@ -105,7 +106,7 @@ static struct platform_device *smdk2413_devices[] __initdata = { &s3c_device_usb, //&s3c_device_lcd, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_iis, &s3c_device_usbgadget, }; @@ -142,6 +143,7 @@ static void __init smdk2413_machine_init(void) s3c24xx_udc_set_platdata(&smdk2413_udc_cfg); + s3c_i2c0_set_platdata(NULL); platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices)); smdk_machine_init(); diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c index 4cfa19a..11e8ad4 100644 --- a/arch/arm/mach-s3c2412/mach-vstms.c +++ b/arch/arm/mach-s3c2412/mach-vstms.c @@ -39,7 +39,8 @@ #include <mach/idle.h> #include <mach/fb.h> -#include <asm/plat-s3c/nand.h> +#include <plat/iic.h> +#include <plat/nand.h> #include <plat/s3c2410.h> #include <plat/s3c2412.h> @@ -122,7 +123,7 @@ static struct s3c2410_platform_nand vstms_nand_info = { static struct platform_device *vstms_devices[] __initdata = { &s3c_device_usb, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_iis, &s3c_device_rtc, &s3c_device_nand, @@ -151,6 +152,7 @@ static void __init vstms_map_io(void) static void __init vstms_init(void) { + s3c_i2c0_set_platdata(NULL); platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices)); } diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index 313759c..5b5aba6 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -16,6 +16,7 @@ #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> +#include <linux/clk.h> #include <linux/delay.h> #include <linux/sysdev.h> #include <linux/serial_core.h> @@ -33,13 +34,15 @@ #include <mach/reset.h> #include <mach/idle.h> +#include <plat/cpu-freq.h> + #include <mach/regs-clock.h> #include <plat/regs-serial.h> #include <mach/regs-power.h> #include <mach/regs-gpio.h> #include <mach/regs-gpioj.h> #include <mach/regs-dsc.h> -#include <asm/plat-s3c24xx/regs-spi.h> +#include <plat/regs-spi.h> #include <mach/regs-s3c2412.h> #include <plat/s3c2412.h> @@ -47,6 +50,7 @@ #include <plat/devs.h> #include <plat/clock.h> #include <plat/pm.h> +#include <plat/pll.h> #ifndef CONFIG_CPU_S3C2412_ONLY void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; @@ -136,7 +140,7 @@ static void s3c2412_hard_reset(void) * machine specific initialisation. */ -void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size) +void __init s3c2412_map_io(void) { /* move base of IO */ @@ -153,20 +157,25 @@ void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size) /* register our io-tables */ iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc)); - iotable_init(mach_desc, mach_size); } -void __init s3c2412_init_clocks(int xtal) +void __init_or_cpufreq s3c2412_setup_clocks(void) { + struct clk *xtal_clk; unsigned long tmp; + unsigned long xtal; unsigned long fclk; unsigned long hclk; unsigned long pclk; + xtal_clk = clk_get(NULL, "xtal"); + xtal = clk_get_rate(xtal_clk); + clk_put(xtal_clk); + /* now we've got our machine bits initialised, work out what * clocks we've got */ - fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2); + fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2); clk_mpll.rate = fclk; @@ -183,11 +192,17 @@ void __init s3c2412_init_clocks(int xtal) printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); + s3c24xx_setup_clocks(fclk, hclk, pclk); +} + +void __init s3c2412_init_clocks(int xtal) +{ /* initialise the clocks here, to allow other things like the * console to use them */ - s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); + s3c24xx_register_baseclocks(xtal); + s3c2412_setup_clocks(); s3c2412_baseclk_add(); } diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index 25de042..cde5ae9 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig @@ -7,6 +7,7 @@ config CPU_S3C2440 bool depends on ARCH_S3C2410 + select CPU_ARM920T select S3C2410_CLOCK select S3C2410_PM if PM select S3C2410_GPIO @@ -28,8 +29,10 @@ menu "S3C2440 Machines" config MACH_ANUBIS bool "Simtec Electronics ANUBIS" select CPU_S3C2440 + select S3C24XX_DCLK select PM_SIMTEC if PM select HAVE_PATA_PLATFORM + select S3C24XX_GPIO_EXTRA64 help Say Y here if you are using the Simtec Electronics ANUBIS development system @@ -37,7 +40,9 @@ config MACH_ANUBIS config MACH_OSIRIS bool "Simtec IM2440D20 (OSIRIS) module" select CPU_S3C2440 + select S3C24XX_DCLK select PM_SIMTEC if PM + select S3C24XX_GPIO_EXTRA128 help Say Y here if you are using the Simtec IM2440D20 module, also known as the Osiris. diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c index 32303f6..5b5ee0b 100644 --- a/arch/arm/mach-s3c2440/dma.c +++ b/arch/arm/mach-s3c2440/dma.c @@ -17,7 +17,6 @@ #include <linux/sysdev.h> #include <linux/serial_core.h> -#include <asm/dma.h> #include <mach/dma.h> #include <plat/dma.h> @@ -25,12 +24,12 @@ #include <plat/regs-serial.h> #include <mach/regs-gpio.h> -#include <asm/plat-s3c/regs-ac97.h> +#include <plat/regs-ac97.h> #include <mach/regs-mem.h> #include <mach/regs-lcd.h> #include <mach/regs-sdi.h> #include <asm/plat-s3c24xx/regs-iis.h> -#include <asm/plat-s3c24xx/regs-spi.h> +#include <plat/regs-spi.h> static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = { [DMACH_XD0] = { diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c index e2beca4..b05d56e 100644 --- a/arch/arm/mach-s3c2440/mach-anubis.c +++ b/arch/arm/mach-s3c2440/mach-anubis.c @@ -39,7 +39,8 @@ #include <mach/regs-gpio.h> #include <mach/regs-mem.h> #include <mach/regs-lcd.h> -#include <asm/plat-s3c/nand.h> +#include <plat/nand.h> +#include <plat/iic.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> @@ -366,6 +367,8 @@ static struct sm501_initdata anubis_sm501_initdata = { .mask = 0, }, + .devices = SM501_USE_GPIO, + /* set the SDRAM and bus clocks */ .mclk = 72 * MHZ, .m1xclk = 144 * MHZ, @@ -373,10 +376,12 @@ static struct sm501_initdata anubis_sm501_initdata = { static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = { [0] = { + .bus_num = 1, .pin_scl = 44, .pin_sda = 45, }, [1] = { + .bus_num = 2, .pin_scl = 40, .pin_sda = 41, }, @@ -384,6 +389,7 @@ static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = { static struct sm501_platdata anubis_sm501_platdata = { .init = &anubis_sm501_initdata, + .gpio_base = -1, .gpio_i2c = anubis_sm501_gpio_i2c, .gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c), }; @@ -404,7 +410,7 @@ static struct platform_device *anubis_devices[] __initdata = { &s3c_device_usb, &s3c_device_wdt, &s3c_device_adc, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_rtc, &s3c_device_nand, &anubis_device_ide0, @@ -468,6 +474,7 @@ static void __init anubis_map_io(void) static void __init anubis_init(void) { + s3c_i2c0_set_platdata(NULL); platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices)); i2c_register_board_info(0, anubis_i2c_devs, diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c index 66876c6..0a6d0a5 100644 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c @@ -28,6 +28,7 @@ #include <asm/mach/irq.h> #include <mach/hardware.h> +#include <mach/fb.h> #include <asm/irq.h> #include <asm/mach-types.h> @@ -35,7 +36,8 @@ #include <mach/regs-gpio.h> #include <mach/regs-mem.h> #include <mach/regs-lcd.h> -#include <asm/plat-s3c/nand.h> +#include <plat/nand.h> +#include <plat/iic.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> @@ -45,6 +47,7 @@ #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> +#include <asm/plat-s3c24xx/mci.h> static struct map_desc at2440evb_iodesc[] __initdata = { /* Nothing here */ @@ -162,19 +165,60 @@ static struct platform_device at2440evb_device_eth = { }, }; +static struct s3c24xx_mci_pdata at2440evb_mci_pdata = { + .gpio_detect = S3C2410_GPG10, +}; + +/* 7" LCD panel */ + +static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = { + + .lcdcon5 = S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_INVVFRAME | + S3C2410_LCDCON5_PWREN | + S3C2410_LCDCON5_HWSWP, + + .type = S3C2410_LCDCON1_TFT, + + .width = 800, + .height = 480, + + .pixclock = 33333, /* HCLK 60 MHz, divisor 2 */ + .xres = 800, + .yres = 480, + .bpp = 16, + .left_margin = 88, + .right_margin = 40, + .hsync_len = 128, + .upper_margin = 32, + .lower_margin = 11, + .vsync_len = 2, +}; + +static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = { + .displays = &at2440evb_lcd_cfg, + .num_displays = 1, + .default_display = 0, +}; + static struct platform_device *at2440evb_devices[] __initdata = { &s3c_device_usb, &s3c_device_wdt, &s3c_device_adc, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_rtc, &s3c_device_nand, + &s3c_device_sdi, + &s3c_device_lcd, &at2440evb_device_eth, }; static void __init at2440evb_map_io(void) { s3c_device_nand.dev.platform_data = &at2440evb_nand_info; + s3c_device_sdi.name = "s3c2440-sdi"; + s3c_device_sdi.dev.platform_data = &at2440evb_mci_pdata; s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); s3c24xx_init_clocks(16934400); @@ -183,6 +227,9 @@ static void __init at2440evb_map_io(void) static void __init at2440evb_init(void) { + s3c24xx_fb_set_platdata(&at2440evb_fb_info); + s3c_i2c0_set_platdata(NULL); + platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices)); } diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c index a546307..7aeaa97 100644 --- a/arch/arm/mach-s3c2440/mach-nexcoder.c +++ b/arch/arm/mach-s3c2440/mach-nexcoder.c @@ -37,6 +37,7 @@ //#include <asm/debug-ll.h> #include <mach/regs-gpio.h> #include <plat/regs-serial.h> +#include <plat/iic.h> #include <plat/s3c2410.h> #include <plat/s3c2440.h> @@ -107,7 +108,7 @@ static struct platform_device *nexcoder_devices[] __initdata = { &s3c_device_usb, &s3c_device_lcd, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_iis, &s3c_device_rtc, &s3c_device_camif, @@ -142,6 +143,7 @@ static void __init nexcoder_map_io(void) static void __init nexcoder_init(void) { + s3c_i2c0_set_platdata(NULL); platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices)); }; diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index 2361d60..41a00f5 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c @@ -37,7 +37,8 @@ #include <mach/regs-gpio.h> #include <mach/regs-mem.h> #include <mach/regs-lcd.h> -#include <asm/plat-s3c/nand.h> +#include <plat/nand.h> +#include <plat/iic.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> @@ -335,7 +336,7 @@ static struct i2c_board_info osiris_i2c_devs[] __initdata = { /* Standard Osiris devices */ static struct platform_device *osiris_devices[] __initdata = { - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_wdt, &s3c_device_nand, &osiris_pcmcia, @@ -398,6 +399,8 @@ static void __init osiris_init(void) sysdev_class_register(&osiris_pm_sysclass); sysdev_register(&osiris_pm_sysdev); + s3c_i2c0_set_platdata(NULL); + i2c_register_board_info(0, osiris_i2c_devs, ARRAY_SIZE(osiris_i2c_devs)); diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index 4d14c7c..12d378f 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c @@ -42,7 +42,7 @@ #include <mach/regs-lcd.h> #include <mach/h1940.h> -#include <asm/plat-s3c/nand.h> +#include <plat/nand.h> #include <mach/fb.h> #include <plat/clock.h> @@ -179,7 +179,7 @@ static struct platform_device *rx3715_devices[] __initdata = { &s3c_device_usb, &s3c_device_lcd, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_iis, &s3c_device_nand, }; diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c index fefeaaa..db6eafb 100644 --- a/arch/arm/mach-s3c2440/mach-smdk2440.c +++ b/arch/arm/mach-s3c2440/mach-smdk2440.c @@ -37,6 +37,7 @@ #include <mach/idle.h> #include <mach/fb.h> +#include <plat/iic.h> #include <plat/s3c2410.h> #include <plat/s3c2440.h> @@ -152,7 +153,7 @@ static struct platform_device *smdk2440_devices[] __initdata = { &s3c_device_usb, &s3c_device_lcd, &s3c_device_wdt, - &s3c_device_i2c, + &s3c_device_i2c0, &s3c_device_iis, }; @@ -166,6 +167,7 @@ static void __init smdk2440_map_io(void) static void __init smdk2440_machine_init(void) { s3c24xx_fb_set_platdata(&smdk2440_fb_info); + s3c_i2c0_set_platdata(NULL); platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices)); smdk_machine_init(); diff --git a/arch/arm/mach-s3c2442/Kconfig b/arch/arm/mach-s3c2442/Kconfig index 26d131a..b289d19 100644 --- a/arch/arm/mach-s3c2442/Kconfig +++ b/arch/arm/mach-s3c2442/Kconfig @@ -7,6 +7,7 @@ config CPU_S3C2442 bool depends on ARCH_S3C2410 + select CPU_ARM920T select S3C2410_CLOCK select S3C2410_GPIO select S3C2410_PM if PM diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig index 14252f5..212141b 100644 --- a/arch/arm/mach-s3c2443/Kconfig +++ b/arch/arm/mach-s3c2443/Kconfig @@ -24,6 +24,7 @@ config MACH_SMDK2443 bool "SMDK2443" select CPU_S3C2443 select MACH_SMDK + select S3C_DEV_HSMMC help Say Y here if you are using an SMDK2443 diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index f854e73..2785d69 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -29,7 +29,6 @@ #include <linux/sysdev.h> #include <linux/clk.h> #include <linux/mutex.h> -#include <linux/delay.h> #include <linux/serial_core.h> #include <linux/io.h> @@ -39,6 +38,8 @@ #include <mach/regs-s3c2443-clock.h> +#include <plat/cpu-freq.h> + #include <plat/s3c2443.h> #include <plat/clock.h> #include <plat/cpu.h> @@ -145,12 +146,6 @@ static unsigned long s3c2443_roundrate_clksrc256(struct clk *clk, /* clock selections */ -/* CPU EXTCLK input */ -static struct clk clk_ext = { - .name = "ext", - .id = -1, -}; - static struct clk clk_mpllref = { .name = "mpllref", .parent = &clk_xtal, @@ -165,14 +160,6 @@ static struct clk clk_mpll = { }; #endif -static struct clk clk_epllref; - -static struct clk clk_epll = { - .name = "epll", - .parent = &clk_epllref, - .id = -1, -}; - static struct clk clk_i2s_ext = { .name = "i2s-ext", .id = -1, @@ -1011,22 +998,20 @@ static struct clk *clks[] __initdata = { &clk_prediv, }; -void __init s3c2443_init_clocks(int xtal) +void __init_or_cpufreq s3c2443_setup_clocks(void) { - unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); + struct clk *xtal_clk; + unsigned long xtal; unsigned long pll; unsigned long fclk; unsigned long hclk; unsigned long pclk; - struct clk *clkp; - int ret; - int ptr; - /* s3c2443 parents h and p clocks from prediv */ - clk_h.parent = &clk_prediv; - clk_p.parent = &clk_prediv; + xtal_clk = clk_get(NULL, "xtal"); + xtal = clk_get_rate(xtal_clk); + clk_put(xtal_clk); pll = s3c2443_get_mpll(mpllcon, xtal); clk_msysclk.rate = pll; @@ -1036,13 +1021,29 @@ void __init s3c2443_init_clocks(int xtal) hclk /= s3c2443_get_hdiv(clkdiv0); pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); - s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); + s3c24xx_setup_clocks(fclk, hclk, pclk); printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", print_mhz(pll), print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); + s3c24xx_setup_clocks(fclk, hclk, pclk); +} + +void __init s3c2443_init_clocks(int xtal) +{ + struct clk *clkp; + unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); + int ret; + int ptr; + + /* s3c2443 parents h and p clocks from prediv */ + clk_h.parent = &clk_prediv; + clk_p.parent = &clk_prediv; + + s3c24xx_register_baseclocks(xtal); + s3c2443_setup_clocks(); s3c2443_clk_initparents(); for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { @@ -1056,7 +1057,7 @@ void __init s3c2443_init_clocks(int xtal) } clk_epll.rate = s3c2443_get_epll(epllcon, xtal); - + clk_epll.parent = &clk_epllref; clk_usb_bus.parent = &clk_usb_bus_host; /* ensure usb bus clock is within correct rate of 48MHz */ @@ -1105,4 +1106,6 @@ void __init s3c2443_init_clocks(int xtal) (clkp->enable)(clkp, 0); } + + s3c_pwmclk_init(); } diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c index f73ccb2..2a58a4d 100644 --- a/arch/arm/mach-s3c2443/dma.c +++ b/arch/arm/mach-s3c2443/dma.c @@ -18,7 +18,6 @@ #include <linux/serial_core.h> #include <linux/io.h> -#include <asm/dma.h> #include <mach/dma.h> #include <plat/dma.h> @@ -26,12 +25,12 @@ #include <plat/regs-serial.h> #include <mach/regs-gpio.h> -#include <asm/plat-s3c/regs-ac97.h> +#include <plat/regs-ac97.h> #include <mach/regs-mem.h> #include <mach/regs-lcd.h> #include <mach/regs-sdi.h> #include <asm/plat-s3c24xx/regs-iis.h> -#include <asm/plat-s3c24xx/regs-spi.h> +#include <plat/regs-spi.h> #define MAP(x) { \ [0] = (x) | DMA_CH_VALID, \ diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c index a7fe65f..039a462 100644 --- a/arch/arm/mach-s3c2443/mach-smdk2443.c +++ b/arch/arm/mach-s3c2443/mach-smdk2443.c @@ -37,6 +37,7 @@ #include <mach/idle.h> #include <mach/fb.h> +#include <plat/iic.h> #include <plat/s3c2410.h> #include <plat/s3c2440.h> @@ -103,8 +104,8 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = { static struct platform_device *smdk2443_devices[] __initdata = { &s3c_device_wdt, - &s3c_device_i2c, - &s3c_device_hsmmc, + &s3c_device_i2c0, + &s3c_device_hsmmc0, }; static void __init smdk2443_map_io(void) @@ -116,6 +117,7 @@ static void __init smdk2443_map_io(void) static void __init smdk2443_machine_init(void) { + s3c_i2c0_set_platdata(NULL); platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices)); smdk_machine_init(); } diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c index bbeddf9..ce2ec32 100644 --- a/arch/arm/mach-s3c2443/s3c2443.c +++ b/arch/arm/mach-s3c2443/s3c2443.c @@ -81,10 +81,9 @@ void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no) * machine specific initialisation. */ -void __init s3c2443_map_io(struct map_desc *mach_desc, int mach_size) +void __init s3c2443_map_io(void) { iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc)); - iotable_init(mach_desc, mach_size); } /* need to register class before we actually register the device, and diff --git a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S new file mode 100644 index 0000000..f0ef0ab --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S @@ -0,0 +1,28 @@ +/* arch/arm/mach-s3c2410/include/mach/debug-macro.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* pull in the relevant register and map files. */ + +#include <mach/map.h> +#include <plat/regs-serial.h> + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 + ldreq \rx, = S3C24XX_PA_UART + ldrne \rx, = S3C24XX_VA_UART +#if CONFIG_DEBUG_S3C_UART != 0 + add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) +#endif + .endm + +/* include the reset of the code which will do the work, we're only + * compiling for a single cpu processor type so the default of s3c2440 + * will be fine with us. + */ + +#include <plat/debug-macro.S> diff --git a/arch/arm/mach-s3c24a0/include/mach/irqs.h b/arch/arm/mach-s3c24a0/include/mach/irqs.h new file mode 100644 index 0000000..ae8c0e3 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/irqs.h @@ -0,0 +1,115 @@ +/* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h + * + * Copyright (c) 2003-2005 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + + +#ifndef __ASM_ARCH_24A0_IRQS_H +#define __ASM_ARCH_24A0_IRQS_H __FILE__ + +#define IRQ_EINT0t2 S3C2410_IRQ(0) /* 16 */ +/* for generic entry-macro.S */ +#define IRQ_EINT0 IRQ_EINT0t2 + +#define IRQ_EINT3t6 S3C2410_IRQ(1) +#define IRQ_EINT7t10 S3C2410_IRQ(2) +#define IRQ_EINT11t14 S3C2410_IRQ(3) +#define IRQ_EINT15t18 S3C2410_IRQ(4) /* 20 */ +#define IRQ_TICK S3C2410_IRQ(5) +#define IRQ_DCTQ S3C2410_IRQ(6) +#define IRQ_MC S3C2410_IRQ(7) +#define IRQ_ME S3C2410_IRQ(8) /* 24 */ +#define IRQ_KEYPAD S3C2410_IRQ(9) +#define IRQ_TIMER0 S3C2410_IRQ(10) +#define IRQ_TIMER1 S3C2410_IRQ(11) +#define IRQ_TIMER2 S3C2410_IRQ(12) +#define IRQ_TIMER3_4 S3C2410_IRQ(13) +#define IRQ_OS_TIMER IRQ_TIMER3_4 +#define IRQ_LCD S3C2410_IRQ(14) +#define IRQ_CAM_C S3C2410_IRQ(15) +#define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */ +#define IRQ_UART0 S3C2410_IRQ(17) +#define IRQ_CAM_P S3C2410_IRQ(18) +#define IRQ_MODEM S3C2410_IRQ(19) +#define IRQ_DMA S3C2410_IRQ(20) +#define IRQ_SDI S3C2410_IRQ(21) +#define IRQ_SPI0 S3C2410_IRQ(22) +#define IRQ_UART1 S3C2410_IRQ(23) +#define IRQ_AC97_NFLASH S3C2410_IRQ(24) /* 40 */ +#define IRQ_USBD S3C2410_IRQ(25) +#define IRQ_USBH S3C2410_IRQ(26) +#define IRQ_IIC S3C2410_IRQ(27) +#define IRQ_IRDA_MSTICK S3C2410_IRQ(28) /* 44 */ +#define IRQ_VLX_SPI1 S3C2410_IRQ(29) +#define IRQ_RTC S3C2410_IRQ(30) /* 46 */ +#define IRQ_ADC_PEN S3C2410_IRQ(31) + +/* interrupts generated from the external interrupts sources */ +#define IRQ_EINT00 S3C2410_IRQ(32) /* 48 */ +#define IRQ_EINT1 S3C2410_IRQ(33) +#define IRQ_EINT2 S3C2410_IRQ(34) +#define IRQ_EINT3 S3C2410_IRQ(35) +#define IRQ_EINT4 S3C2410_IRQ(36) +#define IRQ_EINT5 S3C2410_IRQ(37) +#define IRQ_EINT6 S3C2410_IRQ(38) +#define IRQ_EINT7 S3C2410_IRQ(39) +#define IRQ_EINT8 S3C2410_IRQ(40) +#define IRQ_EINT9 S3C2410_IRQ(41) +#define IRQ_EINT10 S3C2410_IRQ(42) +#define IRQ_EINT11 S3C2410_IRQ(43) +#define IRQ_EINT12 S3C2410_IRQ(44) +#define IRQ_EINT13 S3C2410_IRQ(45) +#define IRQ_EINT14 S3C2410_IRQ(46) +#define IRQ_EINT15 S3C2410_IRQ(47) +#define IRQ_EINT16 S3C2410_IRQ(48) +#define IRQ_EINT17 S3C2410_IRQ(49) +#define IRQ_EINT18 S3C2410_IRQ(50) + +/* SUB IRQS */ +#define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */ +#define IRQ_S3CUART_TX0 S3C2410_IRQ(52) +#define IRQ_S3CUART_ERR0 S3C2410_IRQ(53) + +#define IRQ_S3CUART_RX1 S3C2410_IRQ(54) +#define IRQ_S3CUART_TX1 S3C2410_IRQ(55) +#define IRQ_S3CUART_ERR1 S3C2410_IRQ(56) + +#define IRQ_S3CUART_RX2 (0x0) +#define IRQ_S3CUART_TX2 (0x0) +#define IRQ_S3CUART_ERR2 (0x0) + + +#define IRQ_IRDA S3C2410_IRQ(57) +#define IRQ_MSTICK S3C2410_IRQ(58) +#define IRQ_RESERVED0 S3C2410_IRQ(59) +#define IRQ_RESERVED1 S3C2410_IRQ(60) +#define IRQ_RESERVED2 S3C2410_IRQ(61) +#define IRQ_TIMER3 S3C2410_IRQ(62) +#define IRQ_TIMER4 S3C2410_IRQ(63) +#define IRQ_WDT S3C2410_IRQ(64) +#define IRQ_BATFLT S3C2410_IRQ(65) +#define IRQ_POST S3C2410_IRQ(66) +#define IRQ_DISP_FIFO S3C2410_IRQ(67) +#define IRQ_PENUP S3C2410_IRQ(68) +#define IRQ_PENDN S3C2410_IRQ(69) +#define IRQ_ADC S3C2410_IRQ(70) +#define IRQ_DISP_FRAME S3C2410_IRQ(71) +#define IRQ_NFLASH S3C2410_IRQ(72) +#define IRQ_AC97 S3C2410_IRQ(73) +#define IRQ_SPI1 S3C2410_IRQ(74) +#define IRQ_VLX S3C2410_IRQ(75) +#define IRQ_DMA0 S3C2410_IRQ(76) +#define IRQ_DMA1 S3C2410_IRQ(77) +#define IRQ_DMA2 S3C2410_IRQ(78) +#define IRQ_DMA3 S3C2410_IRQ(79) + +#define IRQ_TC (0x0) + +#define NR_IRQS (IRQ_DMA3+1) + +#endif /* __ASM_ARCH_24A0_IRQS_H */ diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h new file mode 100644 index 0000000..a011327 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/map.h @@ -0,0 +1,85 @@ +/* linux/arch/arm/mach-s3c24a0/include/mach/map.h + * + * Copyright 2003,2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24A0 - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_24A0_MAP_H +#define __ASM_ARCH_24A0_MAP_H __FILE__ + +#include <plat/map-base.h> +#include <plat/map.h> + +#define S3C24A0_PA_IO_BASE (0x40000000) +#define S3C24A0_PA_CLKPWR (0x40000000) +#define S3C24A0_PA_IRQ (0x40200000) +#define S3C24A0_PA_DMA (0x40400000) +#define S3C24A0_PA_MEMCTRL (0x40C00000) +#define S3C24A0_PA_NAND (0x40C00000) +#define S3C24A0_PA_SROM (0x40C20000) +#define S3C24A0_PA_SDRAM (0x40C40000) +#define S3C24A0_PA_BUSM (0x40CE0000) +#define S3C24A0_PA_USBHOST (0x41000000) +#define S3C24A0_PA_MODEMIF (0x41180000) +#define S3C24A0_PA_IRDA (0x41800000) +#define S3C24A0_PA_TIMER (0x44000000) +#define S3C24A0_PA_WATCHDOG (0x44100000) +#define S3C24A0_PA_RTC (0x44200000) +#define S3C24A0_PA_UART (0x44400000) +#define S3C24A0_PA_UART0 (S3C24A0_PA_UART) +#define S3C24A0_PA_UART1 (S3C24A0_PA_UART + 0x4000) +#define S3C24A0_PA_SPI (0x44500000) +#define S3C24A0_PA_IIC (0x44600000) +#define S3C24A0_PA_IIS (0x44700000) +#define S3C24A0_PA_GPIO (0x44800000) +#define S3C24A0_PA_KEYIF (0x44900000) +#define S3C24A0_PA_USBDEV (0x44A00000) +#define S3C24A0_PA_AC97 (0x45000000) +#define S3C24A0_PA_ADC (0x45800000) +#define S3C24A0_PA_SDI (0x46000000) +#define S3C24A0_PA_MS (0x46100000) +#define S3C24A0_PA_LCD (0x4A000000) +#define S3C24A0_PA_VPOST (0x4A100000) + +/* physical addresses of all the chip-select areas */ + +#define S3C24A0_CS0 (0x00000000) +#define S3C24A0_CS1 (0x04000000) +#define S3C24A0_CS2 (0x08000000) +#define S3C24A0_CS3 (0x0C000000) +#define S3C24A0_CS4 (0x10000000) +#define S3C24A0_CS5 (0x40000000) + +#define S3C24A0_SDRAM_PA (S3C24A0_CS4) + +/* Use a single interface for common resources between S3C24XX cpus */ + +#define S3C24XX_PA_IRQ S3C24A0_PA_IRQ +#define S3C24XX_PA_MEMCTRL S3C24A0_PA_MEMCTRL +#define S3C24XX_PA_USBHOST S3C24A0_PA_USBHOST +#define S3C24XX_PA_DMA S3C24A0_PA_DMA +#define S3C24XX_PA_CLKPWR S3C24A0_PA_CLKPWR +#define S3C24XX_PA_LCD S3C24A0_PA_LCD +#define S3C24XX_PA_UART S3C24A0_PA_UART +#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER +#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV +#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG +#define S3C24XX_PA_IIS S3C24A0_PA_IIS +#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO +#define S3C24XX_PA_RTC S3C24A0_PA_RTC +#define S3C24XX_PA_ADC S3C24A0_PA_ADC +#define S3C24XX_PA_SPI S3C24A0_PA_SPI +#define S3C24XX_PA_SDI S3C24A0_PA_SDI +#define S3C24XX_PA_NAND S3C24A0_PA_NAND + +#define S3C_PA_UART S3C24A0_PA_UART +#define S3C_PA_IIC S3C24A0_PA_IIC + +#endif /* __ASM_ARCH_24A0_MAP_H */ diff --git a/arch/arm/mach-s3c24a0/include/mach/memory.h b/arch/arm/mach-s3c24a0/include/mach/memory.h new file mode 100644 index 0000000..585211c --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/memory.h @@ -0,0 +1,19 @@ +/* linux/arch/arm/mach-s3c24a0/include/mach/memory.h + * from linux/include/asm-arm/arch-rpc/memory.h + * + * Copyright (C) 1996,1997,1998 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_24A0_MEMORY_H +#define __ASM_ARCH_24A0_MEMORY_H __FILE__ + +#define PHYS_OFFSET UL(0x10000000) + +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#endif diff --git a/arch/arm/mach-s3c24a0/include/mach/regs-clock.h b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h new file mode 100644 index 0000000..af2abd7 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h @@ -0,0 +1,88 @@ +/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h + * + * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C24A0 clock register definitions +*/ + +#ifndef __ASM_ARCH_24A0_REGS_CLOCK_H +#define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__ + +#define S3C24A0_MPLLCON S3C2410_CLKREG(0x10) +#define S3C24A0_UPLLCON S3C2410_CLKREG(0x14) +#define S3C24A0_CLKCON S3C2410_CLKREG(0x20) +#define S3C24A0_CLKSRC S3C2410_CLKREG(0x24) +#define S3C24A0_CLKDIVN S3C2410_CLKREG(0x28) + +/* CLKCON register bits */ + +#define S3C24A0_CLKCON_VLX (1<<29) +#define S3C24A0_CLKCON_VPOST (1<<28) +#define S3C24A0_CLKCON_WDT (1<<27) /* reserved */ +#define S3C24A0_CLKCON_MPEGDCTQ (1<<26) +#define S3C24A0_CLKCON_VPOSTIF (1<<25) +#define S3C24A0_CLKCON_MPEG4IF (1<<24) +#define S3C24A0_CLKCON_CAM_UPLL (1<<23) +#define S3C24A0_CLKCON_LCDC (1<<22) +#define S3C24A0_CLKCON_CAM_HCLK (1<<21) +#define S3C24A0_CLKCON_MPEG4 (1<<20) +#define S3C24A0_CLKCON_KEYPAD (1<<19) +#define S3C24A0_CLKCON_ADC (1<<18) +#define S3C24A0_CLKCON_SDI (1<<17) +#define S3C24A0_CLKCON_MS (1<<16) /* memory stick */ +#define S3C24A0_CLKCON_USBD (1<<15) +#define S3C24A0_CLKCON_GPIO (1<<14) +#define S3C24A0_CLKCON_IIS (1<<13) +#define S3C24A0_CLKCON_IIC (1<<12) +#define S3C24A0_CLKCON_SPI (1<<11) +#define S3C24A0_CLKCON_UART1 (1<<10) +#define S3C24A0_CLKCON_UART0 (1<<9) +#define S3C24A0_CLKCON_PWMT (1<<8) +#define S3C24A0_CLKCON_USBH (1<<7) +#define S3C24A0_CLKCON_AC97 (1<<6) +#define S3C24A0_CLKCON_IrDA (1<<4) +#define S3C24A0_CLKCON_IDLE (1<<2) +#define S3C24A0_CLKCON_MON (1<<1) +#define S3C24A0_CLKCON_STOP (1<<0) + +/* CLKSRC register bits */ + +#define S3C24A0_CLKSRC_OSC (1<<8) /* CLKSRC */ +#define S3C24A0_CLKSRC_UPLL (1<<7) +#define S3C24A0_CLKSRC_MPLL (1<<5) +#define S3C24A0_CLKSRC_EXT (1<<4) + +/* Use a single interface with the common code, for s3c24xx */ + +#define S3C2410_MPLLCON S3C24A0_MPLLCON +#define S3C2410_UPLLCON S3C24A0_UPLLCON +#define S3C2410_CLKCON S3C24A0_CLKCON +#define S3C2410_CLKSLOW S3C24A0_CLKSRC +#define S3C2410_CLKDIVN S3C24A0_CLKDIVN + +#define S3C2410_CLKCON_IDLE S3C24A0_CLKCON_IDLE +#define S3C2410_CLKCON_POWER S3C24A0_CLKCON_STOP +#define S3C2410_CLKCON_LCDC S3C24A0_CLKCON_LCDC +#define S3C2410_CLKCON_USBH S3C24A0_CLKCON_USBH +#define S3C2410_CLKCON_USBD S3C24A0_CLKCON_USBD +#define S3C2410_CLKCON_PWMT S3C24A0_CLKCON_PWMT +#define S3C2410_CLKCON_SDI S3C24A0_CLKCON_SDI +#define S3C2410_CLKCON_UART0 S3C24A0_CLKCON_UART0 +#define S3C2410_CLKCON_UART1 S3C24A0_CLKCON_UART1 +#define S3C2410_CLKCON_GPIO S3C24A0_CLKCON_GPIO +#define S3C2410_CLKCON_ADC S3C24A0_CLKCON_ADC +#define S3C2410_CLKCON_IIC S3C24A0_CLKCON_IIC +#define S3C2410_CLKCON_IIS S3C24A0_CLKCON_IIS +#define S3C2410_CLKCON_SPI S3C24A0_CLKCON_SPI + +#define S3C2410_CLKSLOW_UCLK_OFF S3C24A0_CLKSRC_UPLL +#define S3C2410_CLKSLOW_MPLL_OFF S3C24A0_CLKSRC_MPLL +#define S3C2410_CLKSLOW_SLOW (0xFF) +#define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1) + +#endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */ diff --git a/arch/arm/mach-s3c24a0/include/mach/regs-irq.h b/arch/arm/mach-s3c24a0/include/mach/regs-irq.h new file mode 100644 index 0000000..6086f6f --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/regs-irq.h @@ -0,0 +1,25 @@ +/* linux/arch/arm/mach-s3c24a0/include/mach/regs-irq.h + * + * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> + * http://www.simtec.co.uk/products/SWLINUX/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + + +#ifndef ___ASM_ARCH_24A0_REGS_IRQ_H +#define ___ASM_ARCH_24A0_REGS_IRQ_H __FILE__ + + +#define S3C2410_EINTMASK S3C2410_EINTREG(0x034) +#define S3C2410_EINTPEND S3C2410_EINTREG(0X038) + +#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x034) +#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X038) + +#endif /* __ASM_ARCH_24A0_REGS_IRQ_H */ + + + diff --git a/arch/arm/mach-s3c24a0/include/mach/system.h b/arch/arm/mach-s3c24a0/include/mach/system.h new file mode 100644 index 0000000..bd1bd19 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/system.h @@ -0,0 +1,25 @@ +/* linux/arch/arm/mach-s3c24a0/include/mach/system.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24A0 - System function defines and includes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <mach/hardware.h> +#include <asm/io.h> + +#include <mach/map.h> + +static void arch_idle(void) +{ + /* currently no specific idle support. */ +} + +void (*s3c24xx_reset_hook)(void); + +#include <asm/plat-s3c24xx/system-reset.h> diff --git a/arch/arm/mach-s3c24a0/include/mach/tick.h b/arch/arm/mach-s3c24a0/include/mach/tick.h new file mode 100644 index 0000000..9dea8ba --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/tick.h @@ -0,0 +1,15 @@ +/* linux/arch/arm/mach-s3c24a0/include/mach/tick.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C24A0 - timer tick support + */ + +#define SUBSRC_TIMER4 (1 << (IRQ_TIMER4 - IRQ_S3CUART_RX0)) + +static inline int s3c24xx_ostimer_pending(void) +{ + return __raw_readl(S3C2410_SUBSRCPND) & SUBSRC_TIMER4; +} diff --git a/arch/arm/mach-s3c24a0/include/mach/timex.h b/arch/arm/mach-s3c24a0/include/mach/timex.h new file mode 100644 index 0000000..9857342 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/timex.h @@ -0,0 +1,18 @@ +/* linux/arch/arm/mach-s3c24a0/include/mach/timex.h + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C2410 - time parameters + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +#define CLOCK_TICK_RATE 12000000 + +#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h new file mode 100644 index 0000000..4d4fe48 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h @@ -0,0 +1,17 @@ +/* linux/include/asm-arm/arch-s3c24ao/vmalloc.h + * + * Copyright 2008 Simtec Electronics <linux@simtec.co.uk> + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C24A0 vmalloc definition +*/ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (0xE0000000) + +#endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s3c6400/Kconfig b/arch/arm/mach-s3c6400/Kconfig new file mode 100644 index 0000000..6da82b5 --- /dev/null +++ b/arch/arm/mach-s3c6400/Kconfig @@ -0,0 +1,8 @@ +# arch/arm/mach-s3c6400/Kconfig +# +# Copyright 2008 Openmoko, Inc. +# Simtec Electronics, Ben Dooks <ben@simtec.co.uk> +# +# Licensed under GPLv2 + +# Currently nothing here, this will be added later diff --git a/arch/arm/mach-s3c6400/Makefile b/arch/arm/mach-s3c6400/Makefile new file mode 100644 index 0000000..8f397db --- /dev/null +++ b/arch/arm/mach-s3c6400/Makefile @@ -0,0 +1,15 @@ +# arch/arm/mach-s3c6400/Makefile +# +# Copyright 2008 Openmoko, Inc. +# Copyright 2008 Simtec Electronics +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +# Core support for S3C6400 system + +obj-n += blank.o diff --git a/arch/arm/mach-s3c6400/Makefile.boot b/arch/arm/mach-s3c6400/Makefile.boot new file mode 100644 index 0000000..ba41fdc --- /dev/null +++ b/arch/arm/mach-s3c6400/Makefile.boot @@ -0,0 +1,2 @@ + zreladdr-y := 0x50008000 +params_phys-y := 0x50000100 diff --git a/arch/arm/mach-s3c6400/include/mach/debug-macro.S b/arch/arm/mach-s3c6400/include/mach/debug-macro.S new file mode 100644 index 0000000..b18ac52 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/debug-macro.S @@ -0,0 +1,39 @@ +/* arch/arm/mach-s3c6400/include/mach/debug-macro.S + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* pull in the relevant register and map files. */ + +#include <mach/map.h> +#include <plat/regs-serial.h> + + /* note, for the boot process to work we have to keep the UART + * virtual address aligned to an 1MiB boundary for the L1 + * mapping the head code makes. We keep the UART virtual address + * aligned and add in the offset when we load the value here. + */ + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 + ldreq \rx, = S3C_PA_UART + ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) +#if CONFIG_DEBUG_S3C_UART != 0 + add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) +#endif + .endm + +/* include the reset of the code which will do the work, we're only + * compiling for a single cpu processor type so the default of s3c2440 + * will be fine with us. + */ + +#include <plat/debug-macro.S> diff --git a/arch/arm/mach-s3c6400/include/mach/dma.h b/arch/arm/mach-s3c6400/include/mach/dma.h new file mode 100644 index 0000000..9771ac2 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/dma.h @@ -0,0 +1,16 @@ +/* linux/arch/arm/mach-s3c6400/include/mach/dma.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C6400 - DMA support + */ + +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H __FILE__ + +/* currently nothing here, placeholder */ + +#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c6400/include/mach/entry-macro.S b/arch/arm/mach-s3c6400/include/mach/entry-macro.S new file mode 100644 index 0000000..fbd90d2 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/entry-macro.S @@ -0,0 +1,44 @@ +/* arch/arm/mach-s3c6400/include/mach/entry-macro.S + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * Low-level IRQ helper macros for the Samsung S3C64XX series + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +#include <asm/hardware/vic.h> +#include <mach/map.h> +#include <plat/irqs.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =S3C_VA_VIC0 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + @ check the vic0 + mov \irqnr, # S3C_IRQ_OFFSET + 31 + ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] + teq \irqstat, #0 + + @ otherwise try vic1 + addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) + addeq \irqnr, \irqnr, #32 + ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] + teqeq \irqstat, #0 + + clzne \irqstat, \irqstat + subne \irqnr, \irqnr, \irqstat + .endm diff --git a/arch/arm/mach-s3c6400/include/mach/gpio-core.h b/arch/arm/mach-s3c6400/include/mach/gpio-core.h new file mode 100644 index 0000000..d89aae6 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/gpio-core.h @@ -0,0 +1,21 @@ +/* arch/arm/mach-s3c6400/include/mach/gpio-core.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - GPIO core support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_GPIO_CORE_H +#define __ASM_ARCH_GPIO_CORE_H __FILE__ + +/* currently we just include the platform support */ +#include <plat/gpio-core.h> + +#endif /* __ASM_ARCH_GPIO_CORE_H */ diff --git a/arch/arm/mach-s3c6400/include/mach/gpio.h b/arch/arm/mach-s3c6400/include/mach/gpio.h new file mode 100644 index 0000000..e8e35e8 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/gpio.h @@ -0,0 +1,96 @@ +/* arch/arm/mach-s3c6400/include/mach/gpio.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C6400 - GPIO lib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + +/* GPIO bank sizes */ +#define S3C64XX_GPIO_A_NR (8) +#define S3C64XX_GPIO_B_NR (7) +#define S3C64XX_GPIO_C_NR (8) +#define S3C64XX_GPIO_D_NR (5) +#define S3C64XX_GPIO_E_NR (5) +#define S3C64XX_GPIO_F_NR (16) +#define S3C64XX_GPIO_G_NR (7) +#define S3C64XX_GPIO_H_NR (10) +#define S3C64XX_GPIO_I_NR (16) +#define S3C64XX_GPIO_J_NR (12) +#define S3C64XX_GPIO_K_NR (16) +#define S3C64XX_GPIO_L_NR (15) +#define S3C64XX_GPIO_M_NR (6) +#define S3C64XX_GPIO_N_NR (16) +#define S3C64XX_GPIO_O_NR (16) +#define S3C64XX_GPIO_P_NR (15) +#define S3C64XX_GPIO_Q_NR (9) + +/* GPIO bank numbes */ + +/* CONFIG_S3C_GPIO_SPACE allows the user to select extra + * space for debugging purposes so that any accidental + * change from one gpio bank to another can be caught. +*/ + +#define S3C64XX_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) + +enum s3c_gpio_number { + S3C64XX_GPIO_A_START = 0, + S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A), + S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B), + S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C), + S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D), + S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E), + S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F), + S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G), + S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H), + S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I), + S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J), + S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K), + S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L), + S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M), + S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N), + S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O), + S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P), +}; + +/* S3C64XX GPIO number definitions. */ + +#define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr)) +#define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr)) +#define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr)) +#define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr)) +#define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr)) +#define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr)) +#define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr)) +#define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr)) +#define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr)) +#define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr)) +#define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr)) +#define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr)) +#define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr)) +#define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr)) +#define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr)) +#define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr)) +#define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr)) + +/* the end of the S3C64XX specific gpios */ +#define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) +#define S3C_GPIO_END S3C64XX_GPIO_END + +/* define the number of gpios we need to the one after the GPQ() range */ +#define ARCH_NR_GPIOS (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) + +#include <asm-generic/gpio.h> diff --git a/arch/arm/mach-s3c6400/include/mach/hardware.h b/arch/arm/mach-s3c6400/include/mach/hardware.h new file mode 100644 index 0000000..862d033 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/hardware.h @@ -0,0 +1,16 @@ +/* linux/arch/arm/mach-s3c6400/include/mach/hardware.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C6400 - Hardware support + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H __FILE__ + +/* currently nothing here, placeholder */ + +#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c6400/include/mach/irqs.h b/arch/arm/mach-s3c6400/include/mach/irqs.h new file mode 100644 index 0000000..b38c47c --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/irqs.h @@ -0,0 +1,20 @@ +/* linux/arch/arm/mach-s3c6400/include/mach/irqs.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C6400 - IRQ definitions + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H __FILE__ + +#ifndef __ASM_ARM_IRQ_H +#error "Do not include this directly, instead #include <asm/irq.h>" +#endif + +#include <plat/irqs.h> + +#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h new file mode 100644 index 0000000..cff27d8 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/map.h @@ -0,0 +1,68 @@ +/* linux/arch/arm/mach-s3c6400/include/mach/map.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C64XX - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MAP_H +#define __ASM_ARCH_MAP_H __FILE__ + +#include <plat/map-base.h> + +/* HSMMC units */ +#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000)) +#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0) +#define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1) +#define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2) + +#define S3C_PA_UART (0x7F005000) +#define S3C_PA_UART0 (S3C_PA_UART + 0x00) +#define S3C_PA_UART1 (S3C_PA_UART + 0x400) +#define S3C_PA_UART2 (S3C_PA_UART + 0x800) +#define S3C_PA_UART3 (S3C_PA_UART + 0xC00) +#define S3C_UART_OFFSET (0x400) + +/* See notes on UART VA mapping in debug-macro.S */ +#define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET)) + +#define S3C_VA_UART0 S3C_VA_UARTx(0) +#define S3C_VA_UART1 S3C_VA_UARTx(1) +#define S3C_VA_UART2 S3C_VA_UARTx(2) +#define S3C_VA_UART3 S3C_VA_UARTx(3) + +#define S3C64XX_PA_FB (0x77100000) +#define S3C64XX_PA_SYSCON (0x7E00F000) +#define S3C64XX_PA_TIMER (0x7F006000) +#define S3C64XX_PA_IIC0 (0x7F004000) +#define S3C64XX_PA_IIC1 (0x7F00F000) + +#define S3C64XX_PA_GPIO (0x7F008000) +#define S3C64XX_VA_GPIO S3C_ADDR(0x00500000) +#define S3C64XX_SZ_GPIO SZ_4K + +#define S3C64XX_PA_SDRAM (0x50000000) +#define S3C64XX_PA_VIC0 (0x71200000) +#define S3C64XX_PA_VIC1 (0x71300000) + +/* place VICs close together */ +#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) +#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) + +/* compatibiltiy defines. */ +#define S3C_PA_TIMER S3C64XX_PA_TIMER +#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0 +#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1 +#define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2 +#define S3C_PA_IIC S3C64XX_PA_IIC0 +#define S3C_PA_IIC1 S3C64XX_PA_IIC1 +#define S3C_PA_FB S3C64XX_PA_FB + +#endif /* __ASM_ARCH_6400_MAP_H */ diff --git a/arch/arm/mach-s3c6400/include/mach/memory.h b/arch/arm/mach-s3c6400/include/mach/memory.h new file mode 100644 index 0000000..a3ac84a --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/memory.h @@ -0,0 +1,18 @@ +/* arch/arm/mach-s3c6400/include/mach/memory.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x50000000) + +#endif diff --git a/arch/arm/mach-s3c6400/include/mach/pwm-clock.h b/arch/arm/mach-s3c6400/include/mach/pwm-clock.h new file mode 100644 index 0000000..b25bede --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/pwm-clock.h @@ -0,0 +1,56 @@ +/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64xx - pwm clock and timer support + */ + +/** + * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk + * @tcfg: The timer TCFG1 register bits shifted down to 0. + * + * Return true if the given configuration from TCFG1 is a TCLK instead + * any of the TDIV clocks. + */ +static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) +{ + return tcfg >= S3C64XX_TCFG1_MUX_TCLK; +} + +/** + * tcfg_to_divisor() - convert tcfg1 setting to a divisor + * @tcfg1: The tcfg1 setting, shifted down. + * + * Get the divisor value for the given tcfg1 setting. We assume the + * caller has already checked to see if this is not a TCLK source. + */ +static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) +{ + return 1 << tcfg1; +} + +/** + * pwm_tdiv_has_div1() - does the tdiv setting have a /1 + * + * Return true if we have a /1 in the tdiv setting. + */ +static inline unsigned int pwm_tdiv_has_div1(void) +{ + return 1; +} + +/** + * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. + * @div: The divisor to calculate the bit information for. + * + * Turn a divisor into the necessary bit field for TCFG1. + */ +static inline unsigned long pwm_tdiv_div_bits(unsigned int div) +{ + return ilog2(div); +} + +#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK diff --git a/arch/arm/mach-s3c6400/include/mach/regs-fb.h b/arch/arm/mach-s3c6400/include/mach/regs-fb.h new file mode 100644 index 0000000..4701979 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/regs-fb.h @@ -0,0 +1,259 @@ +/* arch/arm/mach-s3c6400/include/mach/regs-fb.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C64XX - new-style framebuffer register definitions + * + * This is the register set for the new style framebuffer interface + * found from the S3C2443 onwards and specifically the S3C64XX series + * S3C6400 and S3C6410. + * + * The file contains the cpu specific items which change between whichever + * architecture is selected. See <plat/regs-fb.h> for the core definitions + * that are the same. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* include the core definitions here, in case we really do need to + * override them at a later date. +*/ + +#include <plat/regs-fb.h> + +#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ +#define VIDCON1_FSTATUS_EVEN (1 << 15) + +/* Video timing controls */ +#define VIDTCON0 (0x10) +#define VIDTCON1 (0x14) +#define VIDTCON2 (0x18) + +/* Window position controls */ + +#define WINCON(_win) (0x20 + ((_win) * 4)) + +/* OSD1 and OSD4 do not have register D */ + +#define VIDOSD_A(_win) (0x40 + ((_win) * 16)) +#define VIDOSD_B(_win) (0x44 + ((_win) * 16)) +#define VIDOSD_C(_win) (0x48 + ((_win) * 16)) +#define VIDOSD_D(_win) (0x4C + ((_win) * 16)) + +/* Video buffer addresses */ + +#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8)) +#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8)) +#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8)) +#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) +#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) + +#define VIDINTCON0 (0x130) + +#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4)) + +/* WINCONx */ + +#define WINCONx_CSCWIDTH_MASK (0x3 << 26) +#define WINCONx_CSCWIDTH_SHIFT (26) +#define WINCONx_CSCWIDTH_WIDE (0x0 << 26) +#define WINCONx_CSCWIDTH_NARROW (0x3 << 26) + +#define WINCONx_ENLOCAL (1 << 22) +#define WINCONx_BUFSTATUS (1 << 21) +#define WINCONx_BUFSEL (1 << 20) +#define WINCONx_BUFAUTOEN (1 << 19) +#define WINCONx_YCbCr (1 << 13) + +#define WINCON1_LOCALSEL_CAMIF (1 << 23) + +#define WINCON2_LOCALSEL_CAMIF (1 << 23) +#define WINCON2_BLD_PIX (1 << 6) + +#define WINCON2_ALPHA_SEL (1 << 1) +#define WINCON2_BPPMODE_MASK (0xf << 2) +#define WINCON2_BPPMODE_SHIFT (2) +#define WINCON2_BPPMODE_1BPP (0x0 << 2) +#define WINCON2_BPPMODE_2BPP (0x1 << 2) +#define WINCON2_BPPMODE_4BPP (0x2 << 2) +#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2) +#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2) +#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2) +#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2) +#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2) +#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2) +#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2) +#define WINCON2_BPPMODE_24BPP_888 (0xb << 2) +#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2) +#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2) +#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2) + +#define WINCON3_BLD_PIX (1 << 6) + +#define WINCON3_ALPHA_SEL (1 << 1) +#define WINCON3_BPPMODE_MASK (0xf << 2) +#define WINCON3_BPPMODE_SHIFT (2) +#define WINCON3_BPPMODE_1BPP (0x0 << 2) +#define WINCON3_BPPMODE_2BPP (0x1 << 2) +#define WINCON3_BPPMODE_4BPP (0x2 << 2) +#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2) +#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2) +#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2) +#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2) +#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2) +#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2) +#define WINCON3_BPPMODE_24BPP_888 (0xb << 2) +#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2) +#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2) +#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2) + +#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) +#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) +#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) + +#define DITHMODE (0x170) +#define WINxMAP(_win) (0x180 + ((_win) * 4)) + + +#define DITHMODE_R_POS_MASK (0x3 << 5) +#define DITHMODE_R_POS_SHIFT (5) +#define DITHMODE_R_POS_8BIT (0x0 << 5) +#define DITHMODE_R_POS_6BIT (0x1 << 5) +#define DITHMODE_R_POS_5BIT (0x2 << 5) + +#define DITHMODE_G_POS_MASK (0x3 << 3) +#define DITHMODE_G_POS_SHIFT (3) +#define DITHMODE_G_POS_8BIT (0x0 << 3) +#define DITHMODE_G_POS_6BIT (0x1 << 3) +#define DITHMODE_G_POS_5BIT (0x2 << 3) + +#define DITHMODE_B_POS_MASK (0x3 << 1) +#define DITHMODE_B_POS_SHIFT (1) +#define DITHMODE_B_POS_8BIT (0x0 << 1) +#define DITHMODE_B_POS_6BIT (0x1 << 1) +#define DITHMODE_B_POS_5BIT (0x2 << 1) + +#define DITHMODE_DITH_EN (1 << 0) + +#define WPALCON (0x1A0) + +#define WPALCON_W4PAL_16BPP_A555 (1 << 8) +#define WPALCON_W3PAL_16BPP_A555 (1 << 7) +#define WPALCON_W2PAL_16BPP_A555 (1 << 6) + +/* Palette registers */ + +#define WIN2_PAL(_entry) (0x300 + ((_entry) * 2)) +#define WIN3_PAL(_entry) (0x320 + ((_entry) * 2)) +#define WIN4_PAL(_entry) (0x340 + ((_entry) * 2)) +#define WIN0_PAL(_entry) (0x400 + ((_entry) * 4)) +#define WIN1_PAL(_entry) (0x800 + ((_entry) * 4)) + +/* system specific implementation code for palette sizes, and other + * information that changes depending on which architecture is being + * compiled. +*/ + +/* return true if window _win has OSD register D */ +#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0) + +static inline unsigned int s3c_fb_win_pal_size(unsigned int win) +{ + if (win < 2) + return 256; + if (win < 4) + return 16; + if (win == 4) + return 4; + + BUG(); /* shouldn't get here */ +} + +static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp) +{ + /* all windows can do 1/2 bpp */ + + if ((bpp == 25 || bpp == 19) && win == 0) + return 0; /* win 0 does not have 19 or 25bpp modes */ + + if (bpp == 4 && win == 4) + return 0; + + if (bpp == 8 && (win >= 3)) + return 0; /* win 3/4 cannot do 8bpp in any mode */ + + return 1; +} + +static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) +{ + switch (window) { + case 0: return WIN0_PAL(reg); + case 1: return WIN1_PAL(reg); + case 2: return WIN2_PAL(reg); + case 3: return WIN3_PAL(reg); + case 4: return WIN4_PAL(reg); + } + + BUG(); +} + +static inline int s3c_fb_pal_is16(unsigned int window) +{ + return window > 1; +} + +struct s3c_fb_palette { + struct fb_bitfield r; + struct fb_bitfield g; + struct fb_bitfield b; + struct fb_bitfield a; +}; + +static inline void s3c_fb_init_palette(unsigned int window, + struct s3c_fb_palette *palette) +{ + if (window < 2) { + /* Windows 0/1 are 8/8/8 or A/8/8/8 */ + palette->r.offset = 16; + palette->r.length = 8; + palette->g.offset = 8; + palette->g.length = 8; + palette->b.offset = 0; + palette->b.length = 8; + } else { + /* currently we assume RGB 5/6/5 */ + palette->r.offset = 11; + palette->r.length = 5; + palette->g.offset = 5; + palette->g.length = 6; + palette->b.offset = 0; + palette->b.length = 5; + } +} + +/* Notes on per-window bpp settings + * + * Value Win0 Win1 Win2 Win3 Win 4 + * 0000 1(P) 1(P) 1(P) 1(P) 1(P) + * 0001 2(P) 2(P) 2(P) 2(P) 2(P) + * 0010 4(P) 4(P) 4(P) 4(P) -none- + * 0011 8(P) 8(P) -none- -none- -none- + * 0100 -none- 8(A232) 8(A232) -none- -none- + * 0101 16(565) 16(565) 16(565) 16(565) 16(565) + * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555) + * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555) + * 1000 18(666) 18(666) 18(666) 18(666) 18(666) + * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665) + * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666) + * 1011 24(888) 24(888) 24(888) 24(888) 24(888) + * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887) + * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888) + * 1110 -none- -none- -none- -none- -none- + * 1111 -none- -none- -none- -none- -none- +*/ diff --git a/arch/arm/mach-s3c6400/include/mach/regs-irq.h b/arch/arm/mach-s3c6400/include/mach/regs-irq.h new file mode 100644 index 0000000..bcce68a --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/regs-irq.h @@ -0,0 +1,20 @@ +/* linux/arch/arm/mach-s3c6400/include/mach/regs-irq.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C64XX - IRQ register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_IRQ_H +#define __ASM_ARCH_REGS_IRQ_H __FILE__ + +#include <asm/hardware/vic.h> + +#endif /* __ASM_ARCH_6400_REGS_IRQ_H */ diff --git a/arch/arm/mach-s3c6400/include/mach/system.h b/arch/arm/mach-s3c6400/include/mach/system.h new file mode 100644 index 0000000..652bbc40 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/system.h @@ -0,0 +1,24 @@ +/* linux/arch/arm/mach-s3c6400/include/mach/system.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C6400 - system implementation + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H __FILE__ + +static void arch_idle(void) +{ + /* nothing here yet */ +} + +static void arch_reset(char mode) +{ + /* nothing here yet */ +} + +#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c6400/include/mach/tick.h b/arch/arm/mach-s3c6400/include/mach/tick.h new file mode 100644 index 0000000..d9c0dc7 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/tick.h @@ -0,0 +1,29 @@ +/* linux/arch/arm/mach-s3c6400/include/mach/tick.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C64XX - Timer tick support definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TICK_H +#define __ASM_ARCH_TICK_H __FILE__ + +/* note, the timer interrutps turn up in 2 places, the vic and then + * the timer block. We take the VIC as the base at the moment. + */ +static inline u32 s3c24xx_ostimer_pending(void) +{ + u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); + return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0)); +} + +#define TICK_MAX (0xffffffff) + +#endif /* __ASM_ARCH_6400_TICK_H */ diff --git a/arch/arm/mach-s3c6400/include/mach/uncompress.h b/arch/arm/mach-s3c6400/include/mach/uncompress.h new file mode 100644 index 0000000..c6a82a2 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/uncompress.h @@ -0,0 +1,28 @@ +/* arch/arm/mach-s3c6400/include/mach/uncompress.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C6400 - uncompress code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include <mach/map.h> +#include <plat/uncompress.h> + +static void arch_detect_cpu(void) +{ + /* we do not need to do any cpu detection here at the moment. */ + fifo_mask = S3C2440_UFSTAT_TXMASK; + fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; +} + +#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c6410/Kconfig new file mode 100644 index 0000000..1d50100 --- /dev/null +++ b/arch/arm/mach-s3c6410/Kconfig @@ -0,0 +1,62 @@ +# arch/arm/mach-s3c6410/Kconfig +# +# Copyright 2008 Openmoko, Inc. +# Copyright 2008 Simtec Electronics +# +# Licensed under GPLv2 + +# Configuration options for the S3C6410 CPU + +config CPU_S3C6410 + bool + select CPU_S3C6400_INIT + select CPU_S3C6400_CLOCK + help + Enable S3C6410 CPU support + +config S3C6410_SETUP_SDHCI + bool + help + Internal helper functions for S3C6410 based SDHCI systems + +config MACH_SMDK6410 + bool "SMDK6410" + select CPU_S3C6410 + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_I2C1 + select S3C_DEV_FB + select S3C6410_SETUP_SDHCI + select S3C64XX_SETUP_I2C1 + select S3C64XX_SETUP_FB_24BPP + help + Machine support for the Samsung SMDK6410 + +# At least some of the SMDK6410s were shipped with the card detect +# for the MMC/SD slots connected to the same input. This means that +# either the boards need to be altered to have channel0 to an alternate +# configuration or that only one slot can be used. + +choice + prompt "SMDK6410 MMC/SD slot setup" + depends on MACH_SMDK6410 + +config SMDK6410_SD_CH0 + bool "Use channel 0 only" + depends on MACH_SMDK6410 + help + Select CON7 (channel 0) as the MMC/SD slot, as + at least some SMDK6410 boards come with the + resistors fitted so that the card detects for + channels 0 and 1 are the same. + +config SMDK6410_SD_CH1 + bool "Use channel 1 only" + depends on MACH_SMDK6410 + help + Select CON6 (channel 1) as the MMC/SD slot, as + at least some SMDK6410 boards come with the + resistors fitted so that the card detects for + channels 0 and 1 are the same. + +endchoice diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile new file mode 100644 index 0000000..2cd4f18 --- /dev/null +++ b/arch/arm/mach-s3c6410/Makefile @@ -0,0 +1,23 @@ +# arch/arm/plat-s3c6410/Makefile +# +# Copyright 2008 Openmoko, Inc. +# Copyright 2008 Simtec Electronics +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +# Core support for S3C6410 system + +obj-$(CONFIG_CPU_S3C6410) += cpu.o + +# Helper and device support + +obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o + +# machine support + +obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c new file mode 100644 index 0000000..6a73ca6 --- /dev/null +++ b/arch/arm/mach-s3c6410/cpu.c @@ -0,0 +1,101 @@ +/* linux/arch/arm/mach-s3c6410/cpu.c + * + * Copyright 2008 Simtec Electronics + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/sysdev.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <mach/hardware.h> +#include <asm/irq.h> + +#include <plat/cpu-freq.h> +#include <plat/regs-serial.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/clock.h> +#include <plat/sdhci.h> +#include <plat/iic-core.h> +#include <plat/s3c6400.h> +#include <plat/s3c6410.h> + +/* Initial IO mappings */ + +static struct map_desc s3c6410_iodesc[] __initdata = { +}; + +/* s3c6410_map_io + * + * register the standard cpu IO areas +*/ + +void __init s3c6410_map_io(void) +{ + iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc)); + + /* initialise device information early */ + s3c6410_default_sdhci0(); + s3c6410_default_sdhci1(); + + /* the i2c devices are directly compatible with s3c2440 */ + s3c_i2c0_setname("s3c2440-i2c"); + s3c_i2c1_setname("s3c2440-i2c"); +} + +void __init s3c6410_init_clocks(int xtal) +{ + printk(KERN_DEBUG "%s: initialising clocks\n", __func__); + s3c24xx_register_baseclocks(xtal); + s3c64xx_register_clocks(); + s3c6400_register_clocks(); + s3c6400_setup_clocks(); +} + +void __init s3c6410_init_irq(void) +{ + /* VIC0 is missing IRQ7, VIC1 is fully populated. */ + s3c64xx_init_irq(~0 & ~(1 << 7), ~0); +} + +struct sysdev_class s3c6410_sysclass = { + .name = "s3c6410-core", +}; + +static struct sys_device s3c6410_sysdev = { + .cls = &s3c6410_sysclass, +}; + +static int __init s3c6410_core_init(void) +{ + return sysdev_class_register(&s3c6410_sysclass); +} + +core_initcall(s3c6410_core_init); + +int __init s3c6410_init(void) +{ + printk("S3C6410: Initialising architecture\n"); + + return sysdev_register(&s3c6410_sysdev); +} diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c new file mode 100644 index 0000000..3c4d471 --- /dev/null +++ b/arch/arm/mach-s3c6410/mach-smdk6410.c @@ -0,0 +1,185 @@ +/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/i2c.h> +#include <linux/fb.h> +#include <linux/gpio.h> +#include <linux/delay.h> + +#include <video/platform_lcd.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <mach/hardware.h> +#include <mach/regs-fb.h> +#include <mach/map.h> + +#include <asm/irq.h> +#include <asm/mach-types.h> + +#include <plat/regs-serial.h> +#include <plat/iic.h> +#include <plat/fb.h> + +#include <plat/s3c6410.h> +#include <plat/clock.h> +#include <plat/devs.h> +#include <plat/cpu.h> + +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE + +static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + }, +}; + +/* framebuffer and LCD setup. */ + +/* GPF15 = LCD backlight control + * GPF13 => Panel power + * GPN5 = LCD nRESET signal + * PWM_TOUT1 => backlight brightness + */ + +static void smdk6410_lcd_power_set(struct plat_lcd_data *pd, + unsigned int power) +{ + if (power) { + gpio_direction_output(S3C64XX_GPF(13), 1); + gpio_direction_output(S3C64XX_GPF(15), 1); + + /* fire nRESET on power up */ + gpio_direction_output(S3C64XX_GPN(5), 0); + msleep(10); + gpio_direction_output(S3C64XX_GPN(5), 1); + msleep(1); + } else { + gpio_direction_output(S3C64XX_GPF(15), 0); + gpio_direction_output(S3C64XX_GPF(13), 0); + } +} + +static struct plat_lcd_data smdk6410_lcd_power_data = { + .set_power = smdk6410_lcd_power_set, +}; + +static struct platform_device smdk6410_lcd_powerdev = { + .name = "platform-lcd", + .dev.parent = &s3c_device_fb.dev, + .dev.platform_data = &smdk6410_lcd_power_data, +}; + +static struct s3c_fb_pd_win smdk6410_fb_win0 = { + /* this is to ensure we use win0 */ + .win_mode = { + .pixclock = 41094, + .left_margin = 8, + .right_margin = 13, + .upper_margin = 7, + .lower_margin = 5, + .hsync_len = 3, + .vsync_len = 1, + .xres = 800, + .yres = 480, + }, + .max_bpp = 32, + .default_bpp = 16, +}; + +/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */ +static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = { + .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, + .win[0] = &smdk6410_fb_win0, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, +}; + +struct map_desc smdk6410_iodesc[] = {}; + +static struct platform_device *smdk6410_devices[] __initdata = { +#ifdef CONFIG_SMDK6410_SD_CH0 + &s3c_device_hsmmc0, +#endif +#ifdef CONFIG_SMDK6410_SD_CH1 + &s3c_device_hsmmc1, +#endif + &s3c_device_i2c0, + &s3c_device_i2c1, + &s3c_device_fb, + &smdk6410_lcd_powerdev, +}; + +static struct i2c_board_info i2c_devs0[] __initdata = { + { I2C_BOARD_INFO("24c08", 0x50), }, + { I2C_BOARD_INFO("WM8580", 0X1b), }, +}; + +static struct i2c_board_info i2c_devs1[] __initdata = { + { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */ +}; + +static void __init smdk6410_map_io(void) +{ + s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); +} + +static void __init smdk6410_machine_init(void) +{ + s3c_i2c0_set_platdata(NULL); + s3c_i2c1_set_platdata(NULL); + s3c_fb_set_platdata(&smdk6410_lcd_pdata); + + i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); + i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); + + platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); +} + +MACHINE_START(SMDK6410, "SMDK6410") + /* Maintainer: Ben Dooks <ben@fluff.org> */ + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C64XX_PA_SDRAM + 0x100, + + .init_irq = s3c6410_init_irq, + .map_io = smdk6410_map_io, + .init_machine = smdk6410_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c6410/setup-sdhci.c b/arch/arm/mach-s3c6410/setup-sdhci.c new file mode 100644 index 0000000..0b5788b --- /dev/null +++ b/arch/arm/mach-s3c6410/setup-sdhci.c @@ -0,0 +1,102 @@ +/* linux/arch/arm/mach-s3c6410/setup-sdhci.c + * + * Copyright 2008 Simtec Electronics + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <linux/mmc/card.h> +#include <linux/mmc/host.h> + +#include <mach/gpio.h> +#include <plat/gpio-cfg.h> +#include <plat/regs-sdhci.h> +#include <plat/sdhci.h> + +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ + +char *s3c6410_hsmmc_clksrcs[4] = { + [0] = "hsmmc", + [1] = "hsmmc", + [2] = "mmc_bus", + /* [3] = "48m", - note not succesfully used yet */ +}; + +void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) +{ + unsigned int gpio; + unsigned int end; + + end = S3C64XX_GPG(2 + width); + + /* Set all the necessary GPG pins to special-function 0 */ + for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2)); +} + +void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card) +{ + u32 ctrl2, ctrl3; + + /* don't need to alter anything acording to card-type */ + + writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); + + ctrl2 = readl(r + S3C_SDHCI_CONTROL2); + ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; + ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | + S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | + S3C_SDHCI_CTRL2_ENFBCLKRX | + S3C_SDHCI_CTRL2_DFCNT_NONE | + S3C_SDHCI_CTRL2_ENCLKOUTHOLD); + + if (ios->clock < 25 * 1000000) + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | + S3C_SDHCI_CTRL3_FCSEL2 | + S3C_SDHCI_CTRL3_FCSEL1 | + S3C_SDHCI_CTRL3_FCSEL0); + else + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); + + printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3); + writel(ctrl2, r + S3C_SDHCI_CONTROL2); + writel(ctrl3, r + S3C_SDHCI_CONTROL3); +} + +void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) +{ + unsigned int gpio; + unsigned int end; + + end = S3C64XX_GPH(2 + width); + + /* Set all the necessary GPG pins to special-function 0 */ + for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); +} diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c index 43c30f8..dab3c63 100644 --- a/arch/arm/mach-sa1100/clock.c +++ b/arch/arm/mach-sa1100/clock.c @@ -3,6 +3,7 @@ */ #include <linux/module.h> #include <linux/kernel.h> +#include <linux/device.h> #include <linux/list.h> #include <linux/errno.h> #include <linux/err.h> @@ -14,36 +15,39 @@ #include <mach/hardware.h> /* - * Very simple clock implementation - we only have one clock to - * deal with at the moment, so we only match using the "name". + * Very simple clock implementation - we only have one clock to deal with. */ struct clk { - struct list_head node; - unsigned long rate; - const char *name; unsigned int enabled; - void (*enable)(void); - void (*disable)(void); }; -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); +static void clk_gpio27_enable(void) +{ + /* + * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: + * (SA-1110 Developer's Manual, section 9.1.2.1) + */ + GAFR |= GPIO_32_768kHz; + GPDR |= GPIO_32_768kHz; + TUCR = TUCR_3_6864MHz; +} + +static void clk_gpio27_disable(void) +{ + TUCR = 0; + GPDR &= ~GPIO_32_768kHz; + GAFR &= ~GPIO_32_768kHz; +} + +static struct clk clk_gpio27; + static DEFINE_SPINLOCK(clocks_lock); struct clk *clk_get(struct device *dev, const char *id) { - struct clk *p, *clk = ERR_PTR(-ENOENT); - - mutex_lock(&clocks_mutex); - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0) { - clk = p; - break; - } - } - mutex_unlock(&clocks_mutex); + const char *devname = dev_name(dev); - return clk; + return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27; } EXPORT_SYMBOL(clk_get); @@ -58,7 +62,7 @@ int clk_enable(struct clk *clk) spin_lock_irqsave(&clocks_lock, flags); if (clk->enabled++ == 0) - clk->enable(); + clk_gpio27_enable(); spin_unlock_irqrestore(&clocks_lock, flags); return 0; } @@ -72,63 +76,13 @@ void clk_disable(struct clk *clk) spin_lock_irqsave(&clocks_lock, flags); if (--clk->enabled == 0) - clk->disable(); + clk_gpio27_disable(); spin_unlock_irqrestore(&clocks_lock, flags); } EXPORT_SYMBOL(clk_disable); unsigned long clk_get_rate(struct clk *clk) { - return clk->rate; + return 3686400; } EXPORT_SYMBOL(clk_get_rate); - - -static void clk_gpio27_enable(void) -{ - /* - * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: - * (SA-1110 Developer's Manual, section 9.1.2.1) - */ - GAFR |= GPIO_32_768kHz; - GPDR |= GPIO_32_768kHz; - TUCR = TUCR_3_6864MHz; -} - -static void clk_gpio27_disable(void) -{ - TUCR = 0; - GPDR &= ~GPIO_32_768kHz; - GAFR &= ~GPIO_32_768kHz; -} - -static struct clk clk_gpio27 = { - .name = "SA1111_CLK", - .rate = 3686400, - .enable = clk_gpio27_enable, - .disable = clk_gpio27_disable, -}; - -int clk_register(struct clk *clk) -{ - mutex_lock(&clocks_mutex); - list_add(&clk->node, &clocks); - mutex_unlock(&clocks_mutex); - return 0; -} -EXPORT_SYMBOL(clk_register); - -void clk_unregister(struct clk *clk) -{ - mutex_lock(&clocks_mutex); - list_del(&clk->node); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL(clk_unregister); - -static int __init clk_init(void) -{ - clk_register(&clk_gpio27); - return 0; -} -arch_initcall(clk_init); diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index fe28999..2052eb8 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c @@ -68,23 +68,22 @@ struct platform_device colliescoop_device = { }; static struct scoop_pcmcia_dev collie_pcmcia_scoop[] = { -{ - .dev = &colliescoop_device.dev, - .irq = COLLIE_IRQ_GPIO_CF_IRQ, - .cd_irq = COLLIE_IRQ_GPIO_CF_CD, - .cd_irq_str = "PCMCIA0 CD", -}, + { + .dev = &colliescoop_device.dev, + .irq = COLLIE_IRQ_GPIO_CF_IRQ, + .cd_irq = COLLIE_IRQ_GPIO_CF_CD, + .cd_irq_str = "PCMCIA0 CD", + }, }; static struct scoop_pcmcia_config collie_pcmcia_config = { - .devs = &collie_pcmcia_scoop[0], - .num_devs = 1, + .devs = &collie_pcmcia_scoop[0], + .num_devs = 1, }; - static struct mcp_plat_data collie_mcp_data = { - .mccr0 = MCCR0_ADM | MCCR0_ExtClk, - .sclk_rate = 9216000, + .mccr0 = MCCR0_ADM | MCCR0_ExtClk, + .sclk_rate = 9216000, }; #ifdef CONFIG_SHARP_LOCOMO @@ -95,14 +94,14 @@ struct platform_device collie_locomo_device; static void collie_uart_set_mctrl(struct uart_port *port, u_int mctrl) { - if (mctrl & TIOCM_RTS) + if (mctrl & TIOCM_RTS) locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 0); - else + else locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_RTS, 1); - if (mctrl & TIOCM_DTR) + if (mctrl & TIOCM_DTR) locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 0); - else + else locomo_gpio_write(&collie_locomo_device.dev, LOCOMO_GPIO_DTR, 1); } diff --git a/arch/arm/mach-sa1100/collie_pm.c b/arch/arm/mach-sa1100/collie_pm.c index b1161fc..b39307f 100644 --- a/arch/arm/mach-sa1100/collie_pm.c +++ b/arch/arm/mach-sa1100/collie_pm.c @@ -26,7 +26,7 @@ #include <asm/irq.h> #include <mach/hardware.h> #include <asm/hardware/scoop.h> -#include <asm/dma.h> +#include <mach/dma.h> #include <mach/collie.h> #include <asm/mach/sharpsl_param.h> #include <asm/hardware/sharpsl_pm.h> @@ -263,24 +263,24 @@ static int __init collie_pm_ucb_add(struct ucb1x00_dev *pdev) } static struct ucb1x00_driver collie_pm_ucb_driver = { - .add = collie_pm_ucb_add, + .add = collie_pm_ucb_add, }; static struct platform_device *collie_pm_device; static int __init collie_pm_init(void) { - int ret; + int ret; - collie_pm_device = platform_device_alloc("sharpsl-pm", -1); - if (!collie_pm_device) - return -ENOMEM; + collie_pm_device = platform_device_alloc("sharpsl-pm", -1); + if (!collie_pm_device) + return -ENOMEM; - collie_pm_device->dev.platform_data = &collie_pm_machinfo; - ret = platform_device_add(collie_pm_device); + collie_pm_device->dev.platform_data = &collie_pm_machinfo; + ret = platform_device_add(collie_pm_device); - if (ret) - platform_device_put(collie_pm_device); + if (ret) + platform_device_put(collie_pm_device); if (!ret) ret = ucb1x00_register_driver(&collie_pm_ucb_driver); @@ -291,7 +291,7 @@ static int __init collie_pm_init(void) static void __exit collie_pm_exit(void) { ucb1x00_unregister_driver(&collie_pm_ucb_driver); - platform_device_unregister(collie_pm_device); + platform_device_unregister(collie_pm_device); } module_init(collie_pm_init); diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c index 244d595..ef81787 100644 --- a/arch/arm/mach-sa1100/cpu-sa1100.c +++ b/arch/arm/mach-sa1100/cpu-sa1100.c @@ -3,17 +3,17 @@ * * Copyright (C) 2000 2001, The Delft University of Technology * - * Authors: + * Authors: * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl): * - major rewrite for linux-2.3.99 - * - rewritten for the more generic power management scheme in + * - rewritten for the more generic power management scheme in * linux-2.4.5-rmk1 * * This software has been developed while working on the LART * computing board (http://www.lartmaker.nl/), which is * sponsored by the Mobile Multi-media Communications - * (http://www.mmc.tudelft.nl/) and Ubiquitous Communications + * (http://www.mmc.tudelft.nl/) and Ubiquitous Communications * (http://www.ubicom.tudelft.nl/) projects. * * The authors can be reached at: @@ -36,7 +36,7 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA @@ -44,7 +44,7 @@ * * Theory of operations * ==================== - * + * * Clock scaling can be used to lower the power consumption of the CPU * core. This will give you a somewhat longer running time. * @@ -58,11 +58,11 @@ * MDCNFG 0xA0000000 DRAM config * MDCAS0 0xA0000004 Access waveform * MDCAS1 0xA0000008 Access waveform - * MDCAS2 0xA000000C Access waveform + * MDCAS2 0xA000000C Access waveform * * Care must be taken to change the DRAM parameters the correct way, * because otherwise the DRAM becomes unusable and the kernel will - * crash. + * crash. * * The simple solution to avoid a kernel crash is to put the actual * clock change in ROM and jump to that code from the kernel. The main @@ -75,7 +75,7 @@ * as long as all re-configuration steps yield a valid DRAM * configuration. The advantages are clear: it will run on all SA-1100 * platforms, and the code is very simple. - * + * * If you really want to understand what is going on in * sa1100_update_dram_timings(), you'll have to read sections 8.2, * 9.5.7.3, and 10.2 from the "Intel StrongARM SA-1100 Microprocessor @@ -97,7 +97,7 @@ typedef struct { int speed; u32 mdcnfg; - u32 mdcas0; + u32 mdcas0; u32 mdcas1; u32 mdcas2; } sa1100_dram_regs_t; @@ -147,7 +147,7 @@ static void sa1100_update_dram_timings(int current_speed, int new_speed) /* No risk, no fun: run with interrupts on! */ if (new_speed > current_speed) { /* We're going FASTER, so first relax the memory - * timings before changing the core frequency + * timings before changing the core frequency */ /* Half the memory access clock */ diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c index 3e4fb21..63b32b6 100644 --- a/arch/arm/mach-sa1100/cpu-sa1110.c +++ b/arch/arm/mach-sa1100/cpu-sa1110.c @@ -81,14 +81,14 @@ static struct sdram_params sdram_tbl[] __initdata = { .twr = 9, .refresh = 64000, .cas_latency = 3, - }, { /* Samsung K4S281632B-1H */ - .name = "K4S281632B-1H", - .rows = 12, - .tck = 10, - .trp = 20, - .twr = 10, - .refresh = 64000, - .cas_latency = 3, + }, { /* Samsung K4S281632B-1H */ + .name = "K4S281632B-1H", + .rows = 12, + .tck = 10, + .trp = 20, + .twr = 10, + .refresh = 64000, + .cas_latency = 3, }, { /* Samsung KM416S4030CT */ .name = "KM416S4030CT", .rows = 13, @@ -220,7 +220,7 @@ sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram) } /* - * Ok, set the CPU frequency. + * Ok, set the CPU frequency. */ static int sa1110_target(struct cpufreq_policy *policy, unsigned int target_freq, diff --git a/arch/arm/mach-sa1100/dma.c b/arch/arm/mach-sa1100/dma.c index f990a3e..95f9c5a6 100644 --- a/arch/arm/mach-sa1100/dma.c +++ b/arch/arm/mach-sa1100/dma.c @@ -19,7 +19,7 @@ #include <asm/system.h> #include <asm/irq.h> #include <mach/hardware.h> -#include <asm/dma.h> +#include <mach/dma.h> #undef DEBUG @@ -113,10 +113,10 @@ int sa1100_request_dma (dma_device_t device, const char *device_id, } } if (!err) { - if (dma) - dma->device = device; - else - err = -ENOSR; + if (dma) + dma->device = device; + else + err = -ENOSR; } spin_unlock(&dma_list_lock); if (err) diff --git a/arch/arm/mach-sa1100/include/mach/h3600.h b/arch/arm/mach-sa1100/include/mach/h3600.h index 3ca0ecf..9cc47fd 100644 --- a/arch/arm/mach-sa1100/include/mach/h3600.h +++ b/arch/arm/mach-sa1100/include/mach/h3600.h @@ -32,14 +32,14 @@ typedef int __bitwise pm_request_t; #define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800()) /* Physical memory regions corresponding to chip selects */ -#define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) -#define H3600_BANK_2_PHYS SA1100_CS2_PHYS -#define H3600_BANK_4_PHYS SA1100_CS4_PHYS +#define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) +#define H3600_BANK_2_PHYS SA1100_CS2_PHYS +#define H3600_BANK_4_PHYS SA1100_CS4_PHYS /* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */ -#define H3600_EGPIO_VIRT 0xf0000000 -#define H3600_BANK_2_VIRT 0xf1000000 -#define H3600_BANK_4_VIRT 0xf3800000 +#define H3600_EGPIO_VIRT 0xf0000000 +#define H3600_BANK_2_VIRT 0xf1000000 +#define H3600_BANK_4_VIRT 0xf3800000 /* Machine-independent GPIO definitions diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h index b70846c..6071182 100644 --- a/arch/arm/mach-sa1100/include/mach/hardware.h +++ b/arch/arm/mach-sa1100/include/mach/hardware.h @@ -59,6 +59,10 @@ # define __REG(x) (*((volatile unsigned long *)io_p2v(x))) # define __PREG(x) (io_v2p((unsigned long)&(x))) +static inline unsigned long get_clock_tick_rate(void) +{ + return 3686400; +} #else # define __REG(x) io_p2v(x) diff --git a/arch/arm/mach-sa1100/include/mach/io.h b/arch/arm/mach-sa1100/include/mach/io.h index 0c070a6..d8b43f3 100644 --- a/arch/arm/mach-sa1100/include/mach/io.h +++ b/arch/arm/mach-sa1100/include/mach/io.h @@ -16,11 +16,7 @@ * We don't actually have real ISA nor PCI buses, but there is so many * drivers out there that might just work if we fake them... */ -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)addr; -} -#define __io(a) __io(a) -#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h index 1c127b6..e9f8eed 100644 --- a/arch/arm/mach-sa1100/include/mach/memory.h +++ b/arch/arm/mach-sa1100/include/mach/memory.h @@ -23,23 +23,12 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes); sa1111_adjust_zones(node, size, holes) #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1) +#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M) #endif #endif /* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - * - * On the SA1100, bus addresses are equivalent to physical addresses. - */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - -/* * Because of the wide memory address space between physical RAM banks on the * SA1100, it's much convenient to use Linux's SparseMEM support to implement * our memory map representation. Assuming all memory nodes have equal access diff --git a/arch/arm/mach-sa1100/include/mach/mtd-xip.h b/arch/arm/mach-sa1100/include/mach/mtd-xip.h index eaa09e8..b3d6840 100644 --- a/arch/arm/mach-sa1100/include/mach/mtd-xip.h +++ b/arch/arm/mach-sa1100/include/mach/mtd-xip.h @@ -15,6 +15,8 @@ #ifndef __ARCH_SA1100_MTD_XIP_H__ #define __ARCH_SA1100_MTD_XIP_H__ +#include <mach/hardware.h> + #define xip_irqpending() (ICIP & ICMR) /* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */ diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c index e45d3a1..e1458bc 100644 --- a/arch/arm/mach-sa1100/pleb.c +++ b/arch/arm/mach-sa1100/pleb.c @@ -122,12 +122,12 @@ static void __init pleb_map_io(void) sa1100_map_io(); sa1100_register_uart(0, 3); - sa1100_register_uart(1, 1); + sa1100_register_uart(1, 1); - GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD); - GPDR |= GPIO_UART_TXD; - GPDR &= ~GPIO_UART_RXD; - PPAR |= PPAR_UPR; + GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD); + GPDR |= GPIO_UART_TXD; + GPDR &= ~GPIO_UART_RXD; + PPAR |= PPAR_UPR; /* * Fix expansion memory timing for network card diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c index 9ccdd09..ddd917d 100644 --- a/arch/arm/mach-sa1100/shannon.c +++ b/arch/arm/mach-sa1100/shannon.c @@ -33,7 +33,7 @@ static struct mtd_partition shannon_partitions[] = { .offset = MTDPART_OFS_APPEND, .size = 0xe0000 }, - { + { .name = "initrd", .offset = MTDPART_OFS_APPEND, .size = MTDPART_SIZ_FULL diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S index 171441f..80f31ba 100644 --- a/arch/arm/mach-sa1100/sleep.S +++ b/arch/arm/mach-sa1100/sleep.S @@ -100,36 +100,36 @@ ENTRY(sa1100_cpu_suspend) ldr r1, =MSC1 ldr r2, =MSC2 - ldr r3, [r0] - bic r3, r3, #FMsk(MSC_RT) - bic r3, r3, #FMsk(MSC_RT)<<16 + ldr r3, [r0] + bic r3, r3, #FMsk(MSC_RT) + bic r3, r3, #FMsk(MSC_RT)<<16 - ldr r4, [r1] - bic r4, r4, #FMsk(MSC_RT) - bic r4, r4, #FMsk(MSC_RT)<<16 + ldr r4, [r1] + bic r4, r4, #FMsk(MSC_RT) + bic r4, r4, #FMsk(MSC_RT)<<16 - ldr r5, [r2] - bic r5, r5, #FMsk(MSC_RT) - bic r5, r5, #FMsk(MSC_RT)<<16 + ldr r5, [r2] + bic r5, r5, #FMsk(MSC_RT) + bic r5, r5, #FMsk(MSC_RT)<<16 - ldr r6, =MDREFR + ldr r6, =MDREFR - ldr r7, [r6] - bic r7, r7, #0x0000FF00 - bic r7, r7, #0x000000F0 - orr r8, r7, #MDREFR_SLFRSH + ldr r7, [r6] +bic r7, r7, #0x0000FF00 +bic r7, r7, #0x000000F0 +orr r8, r7, #MDREFR_SLFRSH - ldr r9, =MDCNFG - ldr r10, [r9] - bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1) - bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3) + ldr r9, =MDCNFG + ldr r10, [r9] + bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1) + bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3) - bic r11, r8, #MDREFR_SLFRSH - bic r11, r11, #MDREFR_E1PIN + bic r11, r8, #MDREFR_SLFRSH + bic r11, r11, #MDREFR_E1PIN - ldr r12, =PMCR + ldr r12, =PMCR - mov r13, #PMCR_SF + mov r13, #PMCR_SF b sa1110_sdram_controller_fix @@ -188,10 +188,10 @@ ENTRY(sa1100_cpu_resume) mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache mcr p15, 0, r1, c9, c0, 0 @ invalidate RB - mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB + mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB - mcr p15, 0, r4, c3, c0, 0 @ domain ID - mcr p15, 0, r5, c2, c0, 0 @ translation table base addr + mcr p15, 0, r4, c3, c0, 0 @ domain ID + mcr p15, 0, r5, c2, c0, 0 @ translation table base addr mcr p15, 0, r6, c13, c0, 0 @ PID b resume_turn_on_mmu @ cache align execution @@ -209,7 +209,7 @@ sleep_save_sp: .text resume_after_mmu: - mcr p15, 0, r1, c15, c1, 2 @ enable clock switching + mcr p15, 0, r1, c15, c1, 2 @ enable clock switching ldmfd sp!, {r4 - r12, pc} @ return to caller diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index 24c0a4b..8c5e727 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -2,8 +2,8 @@ * linux/arch/arm/mach-sa1100/time.c * * Copyright (C) 1998 Deborah Wallach. - * Twiddles (C) 1999 Hugo Fiennes <hugo@empeg.com> - * + * Twiddles (C) 1999 Hugo Fiennes <hugo@empeg.com> + * * 2000/03/29 (C) Nicolas Pitre <nico@cam.org> * Rewritten: big cleanup, much simpler, better HZ accuracy. * diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c index a9400d9..a23fd3d 100644 --- a/arch/arm/mach-shark/core.c +++ b/arch/arm/mach-shark/core.c @@ -16,6 +16,8 @@ #include <asm/leds.h> #include <asm/param.h> +#include <mach/hardware.h> + #include <asm/mach/map.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> diff --git a/arch/arm/mach-shark/include/mach/hardware.h b/arch/arm/mach-shark/include/mach/hardware.h index cb0ee29..01bf760 100644 --- a/arch/arm/mach-shark/include/mach/hardware.h +++ b/arch/arm/mach-shark/include/mach/hardware.h @@ -28,8 +28,6 @@ #define ROMCARD_SIZE 0x08000000 #define ROMCARD_START 0x10000000 -#define PCIO_BASE 0xe0000000 - /* defines for the Framebuffer */ #define FB_START 0x06000000 diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h index 9247592..c5cee82 100644 --- a/arch/arm/mach-shark/include/mach/io.h +++ b/arch/arm/mach-shark/include/mach/io.h @@ -11,46 +11,10 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#include <mach/hardware.h> +#define PCIO_BASE 0xe0000000 +#define IO_SPACE_LIMIT 0xffffffff -#define IO_SPACE_LIMIT 0xffffffff - -/* - * We use two different types of addressing - PC style addresses, and ARM - * addresses. PC style accesses the PC hardware with the normal PC IO - * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+ - * and are translated to the start of IO. - */ -#define __PORT_PCIO(x) (!((x) & 0x80000000)) - -#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) - - -static inline unsigned int __ioaddr (unsigned int port) \ -{ \ - if (__PORT_PCIO(port)) \ - return (unsigned int)(PCIO_BASE + (port)); \ - else \ - return (unsigned int)(IO_BASE + (port)); \ -} - -#define __mem_pci(addr) (addr) - -/* - * Translated address IO functions - * - * IO address has already been translated to a virtual address - */ -#define outb_t(v,p) \ - (*(volatile unsigned char *)(p) = (v)) - -#define inb_t(p) \ - (*(volatile unsigned char *)(p)) - -#define outl_t(v,p) \ - (*(volatile unsigned long *)(p) = (v)) - -#define inl_t(p) \ - (*(volatile unsigned long *)(p)) +#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) +#define __mem_pci(addr) (addr) #endif diff --git a/arch/arm/mach-shark/include/mach/dma.h b/arch/arm/mach-shark/include/mach/isa-dma.h index c0a29bd..864298ff 100644 --- a/arch/arm/mach-shark/include/mach/dma.h +++ b/arch/arm/mach-shark/include/mach/isa-dma.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-shark/include/mach/dma.h + * arch/arm/mach-shark/include/mach/isa-dma.h * * by Alexander Schulz */ @@ -10,7 +10,6 @@ * The rest is not DMAable. See dev / .properties * in OpenFirmware. */ -#define MAX_DMA_ADDRESS 0xC0400000 #define MAX_DMA_CHANNELS 8 #define DMA_ISA_CASCADE 4 diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h index b7874ad..c5ab038 100644 --- a/arch/arm/mach-shark/include/mach/memory.h +++ b/arch/arm/mach-shark/include/mach/memory.h @@ -33,12 +33,10 @@ static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsig __arch_adjust_zones(node, size, holes) #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1) +#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_4M) #endif -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - /* * Cache flushing area */ diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig index 95096af..c781f30 100644 --- a/arch/arm/mach-versatile/Kconfig +++ b/arch/arm/mach-versatile/Kconfig @@ -3,12 +3,14 @@ menu "Versatile platform type" config ARCH_VERSATILE_PB bool "Support Versatile/PB platform" + select CPU_ARM926T default y help Include support for the ARM(R) Versatile/PB platform. config MACH_VERSATILE_AB bool "Support Versatile/AB platform" + select CPU_ARM926T help Include support for the ARM(R) Versatile/AP platform. diff --git a/arch/arm/mach-versatile/clock.c b/arch/arm/mach-versatile/clock.c index 58937f1..c50a44e 100644 --- a/arch/arm/mach-versatile/clock.c +++ b/arch/arm/mach-versatile/clock.c @@ -10,6 +10,7 @@ */ #include <linux/module.h> #include <linux/kernel.h> +#include <linux/device.h> #include <linux/list.h> #include <linux/errno.h> #include <linux/err.h> @@ -17,36 +18,11 @@ #include <linux/clk.h> #include <linux/mutex.h> +#include <asm/clkdev.h> #include <asm/hardware/icst307.h> #include "clock.h" -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); - -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p, *clk = ERR_PTR(-ENOENT); - - mutex_lock(&clocks_mutex); - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { - clk = p; - break; - } - } - mutex_unlock(&clocks_mutex); - - return clk; -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ - module_put(clk->owner); -} -EXPORT_SYMBOL(clk_put); - int clk_enable(struct clk *clk) { return 0; @@ -66,7 +42,9 @@ EXPORT_SYMBOL(clk_get_rate); long clk_round_rate(struct clk *clk, unsigned long rate) { - return rate; + struct icst307_vco vco; + vco = icst307_khz_to_vco(clk->params, rate / 1000); + return icst307_khz(clk->params, vco) * 1000; } EXPORT_SYMBOL(clk_round_rate); @@ -79,57 +57,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate) vco = icst307_khz_to_vco(clk->params, rate / 1000); clk->rate = icst307_khz(clk->params, vco) * 1000; - - printk("Clock %s: setting VCO reg params: S=%d R=%d V=%d\n", - clk->name, vco.s, vco.r, vco.v); - clk->setvco(clk, vco); ret = 0; } return ret; } EXPORT_SYMBOL(clk_set_rate); - -/* - * These are fixed clocks. - */ -static struct clk kmi_clk = { - .name = "KMIREFCLK", - .rate = 24000000, -}; - -static struct clk uart_clk = { - .name = "UARTCLK", - .rate = 24000000, -}; - -static struct clk mmci_clk = { - .name = "MCLK", - .rate = 24000000, -}; - -int clk_register(struct clk *clk) -{ - mutex_lock(&clocks_mutex); - list_add(&clk->node, &clocks); - mutex_unlock(&clocks_mutex); - return 0; -} -EXPORT_SYMBOL(clk_register); - -void clk_unregister(struct clk *clk) -{ - mutex_lock(&clocks_mutex); - list_del(&clk->node); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL(clk_unregister); - -static int __init clk_init(void) -{ - clk_register(&kmi_clk); - clk_register(&uart_clk); - clk_register(&mmci_clk); - return 0; -} -arch_initcall(clk_init); diff --git a/arch/arm/mach-versatile/clock.h b/arch/arm/mach-versatile/clock.h index 8b0b61d..03468fdc 100644 --- a/arch/arm/mach-versatile/clock.h +++ b/arch/arm/mach-versatile/clock.h @@ -12,14 +12,9 @@ struct module; struct icst307_params; struct clk { - struct list_head node; unsigned long rate; - struct module *owner; - const char *name; const struct icst307_params *params; + u32 oscoff; void *data; void (*setvco)(struct clk *, struct icst307_vco vco); }; - -int clk_register(struct clk *clk); -void clk_unregister(struct clk *clk); diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 565e0ba..df25aa1 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -31,6 +31,7 @@ #include <linux/cnt32_to_63.h> #include <linux/io.h> +#include <asm/clkdev.h> #include <asm/system.h> #include <mach/hardware.h> #include <asm/irq.h> @@ -373,22 +374,60 @@ static const struct icst307_params versatile_oscvco_params = { static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco) { - void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET; - void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET; + void __iomem *sys = __io_address(VERSATILE_SYS_BASE); + void __iomem *sys_lock = sys + VERSATILE_SYS_LOCK_OFFSET; u32 val; - val = readl(sys_osc) & ~0x7ffff; + val = readl(sys + clk->oscoff) & ~0x7ffff; val |= vco.v | (vco.r << 9) | (vco.s << 16); writel(0xa05f, sys_lock); - writel(val, sys_osc); + writel(val, sys + clk->oscoff); writel(0, sys_lock); } -static struct clk versatile_clcd_clk = { - .name = "CLCDCLK", +static struct clk osc4_clk = { .params = &versatile_oscvco_params, - .setvco = versatile_oscvco_set, + .oscoff = VERSATILE_SYS_OSCCLCD_OFFSET, + .setvco = versatile_oscvco_set, +}; + +/* + * These are fixed clocks. + */ +static struct clk ref24_clk = { + .rate = 24000000, +}; + +static struct clk_lookup lookups[] __initdata = { + { /* UART0 */ + .dev_id = "dev:f1", + .clk = &ref24_clk, + }, { /* UART1 */ + .dev_id = "dev:f2", + .clk = &ref24_clk, + }, { /* UART2 */ + .dev_id = "dev:f3", + .clk = &ref24_clk, + }, { /* UART3 */ + .dev_id = "fpga:09", + .clk = &ref24_clk, + }, { /* KMI0 */ + .dev_id = "fpga:06", + .clk = &ref24_clk, + }, { /* KMI1 */ + .dev_id = "fpga:07", + .clk = &ref24_clk, + }, { /* MMC0 */ + .dev_id = "fpga:05", + .clk = &ref24_clk, + }, { /* MMC1 */ + .dev_id = "fpga:0b", + .clk = &ref24_clk, + }, { /* CLCD */ + .dev_id = "dev:20", + .clk = &osc4_clk, + } }; /* @@ -786,7 +825,8 @@ void __init versatile_init(void) { int i; - clk_register(&versatile_clcd_clk); + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); platform_device_register(&versatile_flash_device); platform_device_register(&versatile_i2c_device); diff --git a/arch/arm/mach-versatile/include/mach/clkdev.h b/arch/arm/mach-versatile/include/mach/clkdev.h new file mode 100644 index 0000000..04b37a8 --- /dev/null +++ b/arch/arm/mach-versatile/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/mach-versatile/include/mach/dma.h b/arch/arm/mach-versatile/include/mach/dma.h deleted file mode 100644 index 0aabf12..0000000 --- a/arch/arm/mach-versatile/include/mach/dma.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * arch/arm/mach-versatile/include/mach/dma.h - * - * Copyright (C) 2003 ARM Limited. - * Copyright (C) 1997,1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h index c0b9dd1..f067c14 100644 --- a/arch/arm/mach-versatile/include/mach/io.h +++ b/arch/arm/mach-versatile/include/mach/io.h @@ -22,11 +22,7 @@ #define IO_SPACE_LIMIT 0xffffffff -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)addr; -} -#define __io(a) __io(a) -#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) #endif diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h index 216a131..9bfdb30 100644 --- a/arch/arm/mach-versatile/include/mach/irqs.h +++ b/arch/arm/mach-versatile/include/mach/irqs.h @@ -60,39 +60,6 @@ #define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31) #define IRQ_VIC_END (IRQ_VIC_START + 31) -#define IRQMASK_WDOGINT INTMASK_WDOGINT -#define IRQMASK_SOFTINT INTMASK_SOFTINT -#define IRQMASK_COMMRx INTMASK_COMMRx -#define IRQMASK_COMMTx INTMASK_COMMTx -#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 -#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 -#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0 -#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1 -#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2 -#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3 -#define IRQMASK_RTCINT INTMASK_RTCINT -#define IRQMASK_SSPINT INTMASK_SSPINT -#define IRQMASK_UARTINT0 INTMASK_UARTINT0 -#define IRQMASK_UARTINT1 INTMASK_UARTINT1 -#define IRQMASK_UARTINT2 INTMASK_UARTINT2 -#define IRQMASK_SCIINT INTMASK_SCIINT -#define IRQMASK_CLCDINT INTMASK_CLCDINT -#define IRQMASK_DMAINT INTMASK_DMAINT -#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT -#define IRQMASK_MBXINT INTMASK_MBXINT -#define IRQMASK_GNDINT INTMASK_GNDINT -#define IRQMASK_VICSOURCE21 INTMASK_VICSOURCE21 -#define IRQMASK_VICSOURCE22 INTMASK_VICSOURCE22 -#define IRQMASK_VICSOURCE23 INTMASK_VICSOURCE23 -#define IRQMASK_VICSOURCE24 INTMASK_VICSOURCE24 -#define IRQMASK_VICSOURCE25 INTMASK_VICSOURCE25 -#define IRQMASK_VICSOURCE26 INTMASK_VICSOURCE26 -#define IRQMASK_VICSOURCE27 INTMASK_VICSOURCE27 -#define IRQMASK_VICSOURCE28 INTMASK_VICSOURCE28 -#define IRQMASK_VICSOURCE29 INTMASK_VICSOURCE29 -#define IRQMASK_VICSOURCE30 INTMASK_VICSOURCE30 -#define IRQMASK_VICSOURCE31 INTMASK_VICSOURCE31 - /* * FIQ interrupts definitions are the same as the INT definitions. */ @@ -130,39 +97,6 @@ #define FIQ_VICSOURCE31 INT_VICSOURCE31 -#define FIQMASK_WDOGINT INTMASK_WDOGINT -#define FIQMASK_SOFTINT INTMASK_SOFTINT -#define FIQMASK_COMMRx INTMASK_COMMRx -#define FIQMASK_COMMTx INTMASK_COMMTx -#define FIQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 -#define FIQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 -#define FIQMASK_GPIOINT0 INTMASK_GPIOINT0 -#define FIQMASK_GPIOINT1 INTMASK_GPIOINT1 -#define FIQMASK_GPIOINT2 INTMASK_GPIOINT2 -#define FIQMASK_GPIOINT3 INTMASK_GPIOINT3 -#define FIQMASK_RTCINT INTMASK_RTCINT -#define FIQMASK_SSPINT INTMASK_SSPINT -#define FIQMASK_UARTINT0 INTMASK_UARTINT0 -#define FIQMASK_UARTINT1 INTMASK_UARTINT1 -#define FIQMASK_UARTINT2 INTMASK_UARTINT2 -#define FIQMASK_SCIINT INTMASK_SCIINT -#define FIQMASK_CLCDINT INTMASK_CLCDINT -#define FIQMASK_DMAINT INTMASK_DMAINT -#define FIQMASK_PWRFAILINT INTMASK_PWRFAILINT -#define FIQMASK_MBXINT INTMASK_MBXINT -#define FIQMASK_GNDINT INTMASK_GNDINT -#define FIQMASK_VICSOURCE21 INTMASK_VICSOURCE21 -#define FIQMASK_VICSOURCE22 INTMASK_VICSOURCE22 -#define FIQMASK_VICSOURCE23 INTMASK_VICSOURCE23 -#define FIQMASK_VICSOURCE24 INTMASK_VICSOURCE24 -#define FIQMASK_VICSOURCE25 INTMASK_VICSOURCE25 -#define FIQMASK_VICSOURCE26 INTMASK_VICSOURCE26 -#define FIQMASK_VICSOURCE27 INTMASK_VICSOURCE27 -#define FIQMASK_VICSOURCE28 INTMASK_VICSOURCE28 -#define FIQMASK_VICSOURCE29 INTMASK_VICSOURCE29 -#define FIQMASK_VICSOURCE30 INTMASK_VICSOURCE30 -#define FIQMASK_VICSOURCE31 INTMASK_VICSOURCE31 - /* * Secondary interrupt controller */ @@ -188,24 +122,4 @@ #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) #define IRQ_SIC_END 63 -#define SIC_IRQMASK_MMCI0B SIC_INTMASK_MMCI0B -#define SIC_IRQMASK_MMCI1B SIC_INTMASK_MMCI1B -#define SIC_IRQMASK_KMI0 SIC_INTMASK_KMI0 -#define SIC_IRQMASK_KMI1 SIC_INTMASK_KMI1 -#define SIC_IRQMASK_SCI3 SIC_INTMASK_SCI3 -#define SIC_IRQMASK_UART3 SIC_INTMASK_UART3 -#define SIC_IRQMASK_CLCD SIC_INTMASK_CLCD -#define SIC_IRQMASK_TOUCH SIC_INTMASK_TOUCH -#define SIC_IRQMASK_KEYPAD SIC_INTMASK_KEYPAD -#define SIC_IRQMASK_DoC SIC_INTMASK_DoC -#define SIC_IRQMASK_MMCI0A SIC_INTMASK_MMCI0A -#define SIC_IRQMASK_MMCI1A SIC_INTMASK_MMCI1A -#define SIC_IRQMASK_AACI SIC_INTMASK_AACI -#define SIC_IRQMASK_ETH SIC_INTMASK_ETH -#define SIC_IRQMASK_USB SIC_INTMASK_USB -#define SIC_IRQMASK_PCI0 SIC_INTMASK_PCI0 -#define SIC_IRQMASK_PCI1 SIC_INTMASK_PCI1 -#define SIC_IRQMASK_PCI2 SIC_INTMASK_PCI2 -#define SIC_IRQMASK_PCI3 SIC_INTMASK_PCI3 - #define NR_IRQS 64 diff --git a/arch/arm/mach-versatile/include/mach/memory.h b/arch/arm/mach-versatile/include/mach/memory.h index b6315c0..79aeab8 100644 --- a/arch/arm/mach-versatile/include/mach/memory.h +++ b/arch/arm/mach-versatile/include/mach/memory.h @@ -25,14 +25,4 @@ */ #define PHYS_OFFSET UL(0x00000000) -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#define __virt_to_bus(x) ((x) - PAGE_OFFSET) -#define __bus_to_virt(x) ((x) + PAGE_OFFSET) - #endif diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h index f91ba93..8320739 100644 --- a/arch/arm/mach-versatile/include/mach/platform.h +++ b/arch/arm/mach-versatile/include/mach/platform.h @@ -347,44 +347,6 @@ #define INT_VICSOURCE30 30 /* PCI 3 */ #define INT_VICSOURCE31 31 /* SIC source */ -/* - * Interrupt bit positions - * - */ -#define INTMASK_WDOGINT (1 << INT_WDOGINT) -#define INTMASK_SOFTINT (1 << INT_SOFTINT) -#define INTMASK_COMMRx (1 << INT_COMMRx) -#define INTMASK_COMMTx (1 << INT_COMMTx) -#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1) -#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3) -#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0) -#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1) -#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2) -#define INTMASK_GPIOINT3 (1 << INT_GPIOINT3) -#define INTMASK_RTCINT (1 << INT_RTCINT) -#define INTMASK_SSPINT (1 << INT_SSPINT) -#define INTMASK_UARTINT0 (1 << INT_UARTINT0) -#define INTMASK_UARTINT1 (1 << INT_UARTINT1) -#define INTMASK_UARTINT2 (1 << INT_UARTINT2) -#define INTMASK_SCIINT (1 << INT_SCIINT) -#define INTMASK_CLCDINT (1 << INT_CLCDINT) -#define INTMASK_DMAINT (1 << INT_DMAINT) -#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT) -#define INTMASK_MBXINT (1 << INT_MBXINT) -#define INTMASK_GNDINT (1 << INT_GNDINT) -#define INTMASK_VICSOURCE21 (1 << INT_VICSOURCE21) -#define INTMASK_VICSOURCE22 (1 << INT_VICSOURCE22) -#define INTMASK_VICSOURCE23 (1 << INT_VICSOURCE23) -#define INTMASK_VICSOURCE24 (1 << INT_VICSOURCE24) -#define INTMASK_VICSOURCE25 (1 << INT_VICSOURCE25) -#define INTMASK_VICSOURCE26 (1 << INT_VICSOURCE26) -#define INTMASK_VICSOURCE27 (1 << INT_VICSOURCE27) -#define INTMASK_VICSOURCE28 (1 << INT_VICSOURCE28) -#define INTMASK_VICSOURCE29 (1 << INT_VICSOURCE29) -#define INTMASK_VICSOURCE30 (1 << INT_VICSOURCE30) -#define INTMASK_VICSOURCE31 (1 << INT_VICSOURCE31) - - #define VERSATILE_SC_VALID_INT 0x003FFFFF #define MAXIRQNUM 31 @@ -417,26 +379,6 @@ #define SIC_INT_PCI3 30 -#define SIC_INTMASK_MMCI0B (1 << SIC_INT_MMCI0B) -#define SIC_INTMASK_MMCI1B (1 << SIC_INT_MMCI1B) -#define SIC_INTMASK_KMI0 (1 << SIC_INT_KMI0) -#define SIC_INTMASK_KMI1 (1 << SIC_INT_KMI1) -#define SIC_INTMASK_SCI3 (1 << SIC_INT_SCI3) -#define SIC_INTMASK_UART3 (1 << SIC_INT_UART3) -#define SIC_INTMASK_CLCD (1 << SIC_INT_CLCD) -#define SIC_INTMASK_TOUCH (1 << SIC_INT_TOUCH) -#define SIC_INTMASK_KEYPAD (1 << SIC_INT_KEYPAD) -#define SIC_INTMASK_DoC (1 << SIC_INT_DoC) -#define SIC_INTMASK_MMCI0A (1 << SIC_INT_MMCI0A) -#define SIC_INTMASK_MMCI1A (1 << SIC_INT_MMCI1A) -#define SIC_INTMASK_AACI (1 << SIC_INT_AACI) -#define SIC_INTMASK_ETH (1 << SIC_INT_ETH) -#define SIC_INTMASK_USB (1 << SIC_INT_USB) -#define SIC_INTMASK_PCI0 (1 << SIC_INT_PCI0) -#define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1) -#define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2) -#define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3) - /* * Clean base - dummy * diff --git a/arch/arm/mach-w90x900/Kconfig b/arch/arm/mach-w90x900/Kconfig new file mode 100644 index 0000000..8e4178f --- /dev/null +++ b/arch/arm/mach-w90x900/Kconfig @@ -0,0 +1,19 @@ +if ARCH_W90X900 + +config CPU_W90P910 + bool + help + Support for W90P910 of Nuvoton W90X900 CPUs. + +menu "W90P910 Machines" + +config MACH_W90P910EVB + bool "Nuvoton W90P910 Evaluation Board" + default y + select CPU_W90P910 + help + Say Y here if you are using the Nuvoton W90P910EVB + +endmenu + +endif diff --git a/arch/arm/mach-w90x900/Makefile b/arch/arm/mach-w90x900/Makefile new file mode 100644 index 0000000..0c0c1d6 --- /dev/null +++ b/arch/arm/mach-w90x900/Makefile @@ -0,0 +1,15 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-y := irq.o time.o + +# W90X900 CPU support files + +obj-$(CONFIG_CPU_W90P910) += w90p910.o + +# machine support + +obj-$(CONFIG_MACH_W90P910EVB) += mach-w90p910evb.o diff --git a/arch/arm/mach-w90x900/Makefile.boot b/arch/arm/mach-w90x900/Makefile.boot new file mode 100644 index 0000000..a057b54 --- /dev/null +++ b/arch/arm/mach-w90x900/Makefile.boot @@ -0,0 +1,3 @@ +zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 + diff --git a/arch/arm/mach-w90x900/cpu.h b/arch/arm/mach-w90x900/cpu.h new file mode 100644 index 0000000..40ff408 --- /dev/null +++ b/arch/arm/mach-w90x900/cpu.h @@ -0,0 +1,77 @@ +/* + * arch/arm/mach-w90x900/cpu.h + * + * Based on linux/include/asm-arm/plat-s3c24xx/cpu.h by Ben Dooks + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Header file for W90X900 CPU support + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#define IODESC_ENT(y) \ +{ \ + .virtual = (unsigned long)W90X900_VA_##y, \ + .pfn = __phys_to_pfn(W90X900_PA_##y), \ + .length = W90X900_SZ_##y, \ + .type = MT_DEVICE, \ +} + +/*Cpu identifier register*/ + +#define W90X900PDID W90X900_VA_GCR +#define W90P910_CPUID 0x02900910 +#define W90P920_CPUID 0x02900920 +#define W90P950_CPUID 0x02900950 +#define W90N960_CPUID 0x02900960 + +struct w90x900_uartcfg; +struct map_desc; +struct sys_timer; + +/* core initialisation functions */ + +extern void w90x900_init_irq(void); +extern void w90p910_init_io(struct map_desc *mach_desc, int size); +extern void w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no); +extern void w90p910_init_clocks(int xtal); +extern void w90p910_map_io(struct map_desc *mach_desc, int size); +extern struct sys_timer w90x900_timer; + +#define W90X900_RES(name) \ +struct resource w90x900_##name##_resource[] = { \ + [0] = { \ + .start = name##_PA, \ + .end = name##_PA + 0x0ff, \ + .flags = IORESOURCE_MEM, \ + }, \ + [1] = { \ + .start = IRQ_##name, \ + .end = IRQ_##name, \ + .flags = IORESOURCE_IRQ, \ + } \ +} + +#define W90X900_DEVICE(devname, regname, devid, platdevname) \ +struct platform_device w90x900_##devname = { \ + .name = platdevname, \ + .id = devid, \ + .num_resources = ARRAY_SIZE(w90x900_##regname##_resource), \ + .resource = w90x900_##regname##_resource, \ +} + +#define W90X900_UARTCFG(port, flag, uc, ulc, ufc) \ +{ \ + .hwport = port, \ + .flags = flag, \ + .ucon = uc, \ + .ulcon = ulc, \ + .ufcon = ufc, \ +} diff --git a/arch/arm/mach-w90x900/include/mach/entry-macro.S b/arch/arm/mach-w90x900/include/mach/entry-macro.S new file mode 100644 index 0000000..d39aca5 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/entry-macro.S @@ -0,0 +1,34 @@ +/* + * arch/arm/mach-w90x900/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for W90P910-based platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + */ + +#include <mach/hardware.h> +#include <mach/regs-irq.h> + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + mov \base, #AIC_BA + + ldr \irqnr, [ \base, #AIC_IPER] + ldr \irqnr, [ \base, #AIC_ISNR] + cmp \irqnr, #0 + + .endm + + /* currently don't need an disable_fiq macro */ + + .macro disable_fiq + .endm diff --git a/arch/arm/mach-w90x900/include/mach/hardware.h b/arch/arm/mach-w90x900/include/mach/hardware.h new file mode 100644 index 0000000..fe3c626 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/hardware.h @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-w90x900/include/mach/hardware.h + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * Based on arch/arm/mach-s3c2410/include/mach/hardware.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/sizes.h> +#include <mach/map.h> + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-w90x900/include/mach/io.h b/arch/arm/mach-w90x900/include/mach/io.h new file mode 100644 index 0000000..d96ab99 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/io.h @@ -0,0 +1,30 @@ +/* + * arch/arm/mach-w90x900/include/mach/io.h + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * Based on arch/arm/mach-s3c2410/include/mach/io.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * 1:1 mapping for ioremapped regions. + */ + +#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) + +#endif diff --git a/arch/arm/mach-w90x900/include/mach/irqs.h b/arch/arm/mach-w90x900/include/mach/irqs.h new file mode 100644 index 0000000..1c583f9 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/irqs.h @@ -0,0 +1,45 @@ +/* + * arch/arm/mach-w90x900/include/mach/irqs.h + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * Based on arch/arm/mach-s3c2410/include/mach/irqs.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* + * we keep the first set of CPU IRQs out of the range of + * the ISA space, so that the PC104 has them to itself + * and we don't end up having to do horrible things to the + * standard ISA drivers.... + * + */ + +#define W90X900_IRQ(x) (x) + +/* Main cpu interrupts */ + +#define IRQ_WDT W90X900_IRQ(1) +#define IRQ_UART0 W90X900_IRQ(7) +#define IRQ_UART1 W90X900_IRQ(8) +#define IRQ_UART2 W90X900_IRQ(9) +#define IRQ_UART3 W90X900_IRQ(10) +#define IRQ_UART4 W90X900_IRQ(11) +#define IRQ_TIMER0 W90X900_IRQ(12) +#define IRQ_TIMER1 W90X900_IRQ(13) +#define IRQ_T_INT_GROUP W90X900_IRQ(14) +#define IRQ_ADC W90X900_IRQ(31) +#define NR_IRQS (IRQ_ADC+1) + +#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-w90x900/include/mach/map.h b/arch/arm/mach-w90x900/include/mach/map.h new file mode 100644 index 0000000..79320eb --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/map.h @@ -0,0 +1,76 @@ +/* + * arch/arm/mach-w90x900/include/mach/map.h + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * Based on arch/arm/mach-s3c2410/include/mach/map.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_MAP_H +#define __ASM_ARCH_MAP_H + +#ifndef __ASSEMBLY__ +#define W90X900_ADDR(x) ((void __iomem *)(0xF0000000 + (x))) +#else +#define W90X900_ADDR(x) (0xF0000000 + (x)) +#endif + +#define AHB_IO_BASE 0xB0000000 +#define APB_IO_BASE 0xB8000000 +#define CLOCKPW_BASE (APB_IO_BASE+0x200) +#define AIC_IO_BASE (APB_IO_BASE+0x2000) +#define TIMER_IO_BASE (APB_IO_BASE+0x1000) + +/* + * interrupt controller is the first thing we put in, to make + * the assembly code for the irq detection easier + */ + +#define W90X900_VA_IRQ W90X900_ADDR(0x00000000) +#define W90X900_PA_IRQ (0xB8002000) +#define W90X900_SZ_IRQ SZ_4K + +#define W90X900_VA_GCR W90X900_ADDR(0x08002000) +#define W90X900_PA_GCR (0xB0000000) +#define W90X900_SZ_GCR SZ_4K + +/* Clock and Power management */ + +#define W90X900_VA_CLKPWR (W90X900_VA_GCR+0x200) +#define W90X900_PA_CLKPWR (0xB0000200) +#define W90X900_SZ_CLKPWR SZ_4K + +/* EBI management */ + +#define W90X900_VA_EBI W90X900_ADDR(0x00001000) +#define W90X900_PA_EBI (0xB0001000) +#define W90X900_SZ_EBI SZ_4K + +/* UARTs */ + +#define W90X900_VA_UART W90X900_ADDR(0x08000000) +#define W90X900_PA_UART (0xB8000000) +#define W90X900_SZ_UART SZ_4K + +/* Timers */ + +#define W90X900_VA_TIMER W90X900_ADDR(0x08001000) +#define W90X900_PA_TIMER (0xB8001000) +#define W90X900_SZ_TIMER SZ_4K + +/* GPIO ports */ + +#define W90X900_VA_GPIO W90X900_ADDR(0x08003000) +#define W90X900_PA_GPIO (0xB8003000) +#define W90X900_SZ_GPIO SZ_4K + +#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-w90x900/include/mach/memory.h b/arch/arm/mach-w90x900/include/mach/memory.h new file mode 100644 index 0000000..971b807 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/memory.h @@ -0,0 +1,23 @@ +/* + * arch/arm/mach-w90x900/include/mach/memory.h + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * Based on arch/arm/mach-s3c2410/include/mach/memory.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x00000000) + +#endif diff --git a/arch/arm/mach-w90x900/include/mach/regs-irq.h b/arch/arm/mach-w90x900/include/mach/regs-irq.h new file mode 100644 index 0000000..8a3185f --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/regs-irq.h @@ -0,0 +1,51 @@ +/* + * arch/arm/mach-w90x900/include/mach/regs-irq.h + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * Based on arch/arm/mach-s3c2410/include/mach/regs-irq.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef ___ASM_ARCH_REGS_IRQ_H +#define ___ASM_ARCH_REGS_IRQ_H + +/* Advance Interrupt Controller (AIC) Registers */ + +#define AIC_BA W90X900_VA_IRQ + +#define REG_AIC_IRQSC (AIC_BA+0x80) +#define REG_AIC_GEN (AIC_BA+0x84) +#define REG_AIC_GASR (AIC_BA+0x88) +#define REG_AIC_GSCR (AIC_BA+0x8C) +#define REG_AIC_IRSR (AIC_BA+0x100) +#define REG_AIC_IASR (AIC_BA+0x104) +#define REG_AIC_ISR (AIC_BA+0x108) +#define REG_AIC_IPER (AIC_BA+0x10C) +#define REG_AIC_ISNR (AIC_BA+0x110) +#define REG_AIC_IMR (AIC_BA+0x114) +#define REG_AIC_OISR (AIC_BA+0x118) +#define REG_AIC_MECR (AIC_BA+0x120) +#define REG_AIC_MDCR (AIC_BA+0x124) +#define REG_AIC_SSCR (AIC_BA+0x128) +#define REG_AIC_SCCR (AIC_BA+0x12C) +#define REG_AIC_EOSCR (AIC_BA+0x130) +#define AIC_IPER (0x10C) +#define AIC_ISNR (0x110) + +/*16-18 bits of REG_AIC_GEN define irq(2-4) group*/ + +#define TIMER2_IRQ (1 << 16) +#define TIMER3_IRQ (1 << 17) +#define TIMER4_IRQ (1 << 18) +#define TIME_GROUP_IRQ (TIMER2_IRQ|TIMER3_IRQ|TIMER4_IRQ) + +#endif /* ___ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-w90x900/include/mach/regs-serial.h b/arch/arm/mach-w90x900/include/mach/regs-serial.h new file mode 100644 index 0000000..f08fa0d --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/regs-serial.h @@ -0,0 +1,59 @@ +/* + * arch/arm/mach-w90x900/include/mach/regs-serial.h + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * Based on arch/arm/mach-s3c2410/include/mach/regs-serial.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARM_REGS_SERIAL_H +#define __ASM_ARM_REGS_SERIAL_H + +#define UART0_BA W90X900_VA_UART +#define UART1_BA (W90X900_VA_UART+0x100) +#define UART2_BA (W90X900_VA_UART+0x200) +#define UART3_BA (W90X900_VA_UART+0x300) +#define UART4_BA (W90X900_VA_UART+0x400) + +#define UART0_PA W90X900_PA_UART +#define UART1_PA (W90X900_PA_UART+0x100) +#define UART2_PA (W90X900_PA_UART+0x200) +#define UART3_PA (W90X900_PA_UART+0x300) +#define UART4_PA (W90X900_PA_UART+0x400) + +#ifndef __ASSEMBLY__ + +struct w90x900_uart_clksrc { + const char *name; + unsigned int divisor; + unsigned int min_baud; + unsigned int max_baud; +}; + +struct w90x900_uartcfg { + unsigned char hwport; + unsigned char unused; + unsigned short flags; + unsigned long uart_flags; + + unsigned long ucon; + unsigned long ulcon; + unsigned long ufcon; + + struct w90x900_uart_clksrc *clocks; + unsigned int clocks_size; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARM_REGS_SERIAL_H */ + diff --git a/arch/arm/mach-w90x900/include/mach/regs-timer.h b/arch/arm/mach-w90x900/include/mach/regs-timer.h new file mode 100644 index 0000000..8f39062 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/regs-timer.h @@ -0,0 +1,42 @@ +/* + * arch/arm/mach-w90x900/include/mach/regs-timer.h + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * Based on arch/arm/mach-s3c2410/include/mach/regs-timer.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_REGS_TIMER_H +#define __ASM_ARCH_REGS_TIMER_H + +/* Timer Registers */ + +#define TMR_BA W90X900_VA_TIMER +#define REG_TCSR0 (TMR_BA+0x00) +#define REG_TCSR1 (TMR_BA+0x04) +#define REG_TICR0 (TMR_BA+0x08) +#define REG_TICR1 (TMR_BA+0x0C) +#define REG_TDR0 (TMR_BA+0x10) +#define REG_TDR1 (TMR_BA+0x14) +#define REG_TISR (TMR_BA+0x18) +#define REG_WTCR (TMR_BA+0x1C) +#define REG_TCSR2 (TMR_BA+0x20) +#define REG_TCSR3 (TMR_BA+0x24) +#define REG_TICR2 (TMR_BA+0x28) +#define REG_TICR3 (TMR_BA+0x2C) +#define REG_TDR2 (TMR_BA+0x30) +#define REG_TDR3 (TMR_BA+0x34) +#define REG_TCSR4 (TMR_BA+0x40) +#define REG_TICR4 (TMR_BA+0x48) +#define REG_TDR4 (TMR_BA+0x50) + +#endif /* __ASM_ARCH_REGS_TIMER_H */ diff --git a/arch/arm/mach-w90x900/include/mach/system.h b/arch/arm/mach-w90x900/include/mach/system.h new file mode 100644 index 0000000..93753f9 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/system.h @@ -0,0 +1,28 @@ +/* + * arch/arm/mach-w90x900/include/mach/system.h + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * Based on arch/arm/mach-s3c2410/include/mach/system.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include <asm/proc-fns.h> + +static void arch_idle(void) +{ +} + +static void arch_reset(char mode) +{ + cpu_reset(0); +} + diff --git a/arch/arm/mach-w90x900/include/mach/timex.h b/arch/arm/mach-w90x900/include/mach/timex.h new file mode 100644 index 0000000..164dce0 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/timex.h @@ -0,0 +1,25 @@ +/* + * arch/arm/mach-w90x900/include/mach/timex.h + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * Based on arch/arm/mach-s3c2410/include/mach/timex.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* CLOCK_TICK_RATE Now, I don't use it. */ + +#define CLOCK_TICK_RATE 15000000 + +#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-w90x900/include/mach/uncompress.h b/arch/arm/mach-w90x900/include/mach/uncompress.h new file mode 100644 index 0000000..050d9fe --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/uncompress.h @@ -0,0 +1,40 @@ +/* + * arch/arm/mach-w90x900/include/mach/uncompress.h + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * Based on arch/arm/mach-s3c2410/include/mach/uncompress.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +/* Defines for UART registers */ + +#include <mach/regs-serial.h> +#include <mach/map.h> + +#define arch_decomp_wdog() + +static void putc(int ch) +{ +} + +static inline void flush(void) +{ +} + +static void arch_decomp_setup(void) +{ +} + +#endif/* __ASM_W90X900_UNCOMPRESS_H */ diff --git a/arch/arm/mach-w90x900/include/mach/vmalloc.h b/arch/arm/mach-w90x900/include/mach/vmalloc.h new file mode 100644 index 0000000..2f9dfb9 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/vmalloc.h @@ -0,0 +1,23 @@ +/* + * arch/arm/mach-w90x900/include/mach/vmalloc.h + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * Based on arch/arm/mach-s3c2410/include/mach/vmalloc.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (0xE0000000) + +#endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c new file mode 100644 index 0000000..0b4fc19 --- /dev/null +++ b/arch/arm/mach-w90x900/irq.c @@ -0,0 +1,76 @@ +/* + * linux/arch/arm/mach-w90x900/irq.c + * + * based on linux/arch/arm/plat-s3c24xx/irq.c by Ben Dooks + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/ptrace.h> +#include <linux/sysdev.h> +#include <linux/io.h> + +#include <asm/irq.h> +#include <asm/mach/irq.h> + +#include <mach/hardware.h> +#include <mach/regs-irq.h> + +static void w90x900_irq_mask(unsigned int irq) +{ + __raw_writel(1 << irq, REG_AIC_MDCR); +} + +/* + * By the w90p910 spec,any irq,only write 1 + * to REG_AIC_EOSCR for ACK + */ + +static void w90x900_irq_ack(unsigned int irq) +{ + __raw_writel(0x01, REG_AIC_EOSCR); +} + +static void w90x900_irq_unmask(unsigned int irq) +{ + unsigned long mask; + + if (irq == IRQ_T_INT_GROUP) { + mask = __raw_readl(REG_AIC_GEN); + __raw_writel(TIME_GROUP_IRQ | mask, REG_AIC_GEN); + __raw_writel(1 << IRQ_T_INT_GROUP, REG_AIC_MECR); + } + __raw_writel(1 << irq, REG_AIC_MECR); +} + +static struct irq_chip w90x900_irq_chip = { + .ack = w90x900_irq_ack, + .mask = w90x900_irq_mask, + .unmask = w90x900_irq_unmask, +}; + +void __init w90x900_init_irq(void) +{ + int irqno; + + __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); + + for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { + set_irq_chip(irqno, &w90x900_irq_chip); + set_irq_handler(irqno, handle_level_irq); + set_irq_flags(irqno, IRQF_VALID); + } +} diff --git a/arch/arm/mach-w90x900/mach-w90p910evb.c b/arch/arm/mach-w90x900/mach-w90p910evb.c new file mode 100644 index 0000000..9307a24 --- /dev/null +++ b/arch/arm/mach-w90x900/mach-w90p910evb.c @@ -0,0 +1,72 @@ +/* + * linux/arch/arm/mach-w90x900/mach-w90p910evb.c + * + * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche + * + * Copyright (C) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/platform_device.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> +#include <asm/mach-types.h> + +#include <mach/regs-serial.h> + +#include "cpu.h" + +static struct map_desc w90p910_iodesc[] __initdata = { +}; + +static struct w90x900_uartcfg w90p910_uartcfgs[] = { + W90X900_UARTCFG(0, 0, 0, 0, 0), + W90X900_UARTCFG(1, 0, 0, 0, 0), + W90X900_UARTCFG(2, 0, 0, 0, 0), + W90X900_UARTCFG(3, 0, 0, 0, 0), + W90X900_UARTCFG(4, 0, 0, 0, 0), +}; + +/*Here should be your evb resourse,such as LCD*/ + +static struct platform_device *w90p910evb_dev[] __initdata = { +}; + +static void __init w90p910evb_map_io(void) +{ + w90p910_map_io(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc)); + w90p910_init_clocks(0); + w90p910_init_uarts(w90p910_uartcfgs, ARRAY_SIZE(w90p910_uartcfgs)); +} + +static void __init w90p910evb_init(void) +{ + platform_add_devices(w90p910evb_dev, ARRAY_SIZE(w90p910evb_dev)); +} + +MACHINE_START(W90P910EVB, "W90P910EVB") + /* Maintainer: Wan ZongShun */ + .phys_io = W90X900_PA_UART, + .io_pg_offst = (((u32)W90X900_VA_UART) >> 18) & 0xfffc, + .boot_params = 0, + .map_io = w90p910evb_map_io, + .init_irq = w90x900_init_irq, + .init_machine = w90p910evb_init, + .timer = &w90x900_timer, +MACHINE_END diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c new file mode 100644 index 0000000..3a69e38 --- /dev/null +++ b/arch/arm/mach-w90x900/time.c @@ -0,0 +1,80 @@ +/* + * linux/arch/arm/mach-w90x900/time.c + * + * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/leds.h> + +#include <asm/mach-types.h> +#include <asm/mach/irq.h> +#include <asm/mach/time.h> + +#include <mach/system.h> +#include <mach/map.h> +#include <mach/regs-timer.h> + +static unsigned long w90x900_gettimeoffset(void) +{ + return 0; +} + +/*IRQ handler for the timer*/ + +static irqreturn_t +w90x900_timer_interrupt(int irq, void *dev_id) +{ + timer_tick(); + __raw_writel(0x01, REG_TISR); /* clear TIF0 */ + return IRQ_HANDLED; +} + +static struct irqaction w90x900_timer_irq = { + .name = "w90x900 Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = w90x900_timer_interrupt, +}; + +/*Set up timer reg.*/ + +static void w90x900_timer_setup(void) +{ + __raw_writel(0, REG_TCSR0); + __raw_writel(0, REG_TCSR1); + __raw_writel(0, REG_TCSR2); + __raw_writel(0, REG_TCSR3); + __raw_writel(0, REG_TCSR4); + __raw_writel(0x1F, REG_TISR); + __raw_writel(15000000/(100 * 100), REG_TICR0); + __raw_writel(0x68000063, REG_TCSR0); +} + +static void __init w90x900_timer_init(void) +{ + w90x900_timer_setup(); + setup_irq(IRQ_TIMER0, &w90x900_timer_irq); +} + +struct sys_timer w90x900_timer = { + .init = w90x900_timer_init, + .offset = w90x900_gettimeoffset, + .resume = w90x900_timer_setup +}; diff --git a/arch/arm/mach-w90x900/w90p910.c b/arch/arm/mach-w90x900/w90p910.c new file mode 100644 index 0000000..aa783bc --- /dev/null +++ b/arch/arm/mach-w90x900/w90p910.c @@ -0,0 +1,134 @@ +/* + * linux/arch/arm/mach-w90x900/w90p910.c + * + * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * W90P910 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> +#include <asm/irq.h> + +#include <mach/hardware.h> +#include <mach/regs-serial.h> + +#include "cpu.h" + +/*W90P910 has five uarts*/ + +#define MAX_UART_COUNT 5 +static int uart_count; +static struct platform_device *uart_devs[MAX_UART_COUNT-1]; + +/* Initial IO mappings */ + +static struct map_desc w90p910_iodesc[] __initdata = { + IODESC_ENT(IRQ), + IODESC_ENT(GCR), + IODESC_ENT(UART), + IODESC_ENT(TIMER), + IODESC_ENT(EBI), + /*IODESC_ENT(LCD),*/ +}; + +/*Init the dev resource*/ + +static W90X900_RES(UART0); +static W90X900_RES(UART1); +static W90X900_RES(UART2); +static W90X900_RES(UART3); +static W90X900_RES(UART4); +static W90X900_DEVICE(uart0, UART0, 0, "w90x900-uart"); +static W90X900_DEVICE(uart1, UART1, 1, "w90x900-uart"); +static W90X900_DEVICE(uart2, UART2, 2, "w90x900-uart"); +static W90X900_DEVICE(uart3, UART3, 3, "w90x900-uart"); +static W90X900_DEVICE(uart4, UART4, 4, "w90x900-uart"); + +static struct platform_device *uart_devices[] __initdata = { + &w90x900_uart0, + &w90x900_uart1, + &w90x900_uart2, + &w90x900_uart3, + &w90x900_uart4 +}; + +/*Init W90P910 uart device*/ + +void __init w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no) +{ + struct platform_device *platdev; + int uart, uartdev; + + /*By min() to judge count of uart be used indeed*/ + + uartdev = ARRAY_SIZE(uart_devices); + no = min(uartdev, no); + + for (uart = 0; uart < no; uart++, cfg++) { + if (cfg->hwport != uart) + printk(KERN_ERR "w90x900_uartcfg[%d] error\n", uart); + platdev = uart_devices[cfg->hwport]; + uart_devs[uart] = platdev; + platdev->dev.platform_data = cfg; + } + uart_count = uart; +} + +/*Init W90P910 evb io*/ + +void __init w90p910_map_io(struct map_desc *mach_desc, int mach_size) +{ + unsigned long idcode = 0x0; + + iotable_init(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc)); + + idcode = __raw_readl(W90X900PDID); + if (idcode != W90P910_CPUID) + printk(KERN_ERR "CPU type 0x%08lx is not W90P910\n", idcode); +} + +/*Init W90P910 clock*/ + +void __init w90p910_init_clocks(int xtal) +{ +} + +static int __init w90p910_init_cpu(void) +{ + return 0; +} + +static int __init w90x900_arch_init(void) +{ + int ret; + + ret = w90p910_init_cpu(); + if (ret != 0) + return ret; + + return platform_add_devices(uart_devs, uart_count); + +} +arch_initcall(w90x900_arch_init); diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index ab5f7a2..d490f37 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -10,8 +10,7 @@ config CPU_32 # ARM610 config CPU_ARM610 - bool "Support ARM610 processor" - depends on ARCH_RPC + bool "Support ARM610 processor" if ARCH_RPC select CPU_32v3 select CPU_CACHE_V3 select CPU_CACHE_VIVT @@ -43,8 +42,7 @@ config CPU_ARM7TDMI # ARM710 config CPU_ARM710 - bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC - default y if ARCH_CLPS7500 + bool "Support ARM710 processor" if ARCH_RPC select CPU_32v3 select CPU_CACHE_V3 select CPU_CACHE_VIVT @@ -63,8 +61,7 @@ config CPU_ARM710 # ARM720T config CPU_ARM720T - bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR - default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X + bool "Support ARM720T processor" if ARCH_INTEGRATOR select CPU_32v4T select CPU_ABRT_LV4T select CPU_PABRT_NOIFAR @@ -114,9 +111,7 @@ config CPU_ARM9TDMI # ARM920T config CPU_ARM920T - bool "Support ARM920T processor" - depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 - default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 + bool "Support ARM920T processor" if ARCH_INTEGRATOR select CPU_32v4T select CPU_ABRT_EV4T select CPU_PABRT_NOIFAR @@ -138,8 +133,6 @@ config CPU_ARM920T # ARM922T config CPU_ARM922T bool "Support ARM922T processor" if ARCH_INTEGRATOR - depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695 - default y if ARCH_LH7A40X || ARCH_KS8695 select CPU_32v4T select CPU_ABRT_EV4T select CPU_PABRT_NOIFAR @@ -159,8 +152,6 @@ config CPU_ARM922T # ARM925T config CPU_ARM925T bool "Support ARM925T processor" if ARCH_OMAP1 - depends on ARCH_OMAP15XX - default y if ARCH_OMAP15XX select CPU_32v4T select CPU_ABRT_EV4T select CPU_PABRT_NOIFAR @@ -179,22 +170,7 @@ config CPU_ARM925T # ARM926T config CPU_ARM926T - bool "Support ARM926T processor" - depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \ - MACH_VERSATILE_AB || ARCH_OMAP730 || \ - ARCH_OMAP16XX || MACH_REALVIEW_EB || \ - ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \ - ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \ - ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \ - ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \ - ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2 - default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \ - ARCH_OMAP730 || ARCH_OMAP16XX || \ - ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \ - ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \ - ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \ - ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \ - ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2 + bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB select CPU_32v5 select CPU_ABRT_EV5TJ select CPU_PABRT_NOIFAR @@ -247,8 +223,7 @@ config CPU_ARM946E # ARM1020 - needs validating config CPU_ARM1020 - bool "Support ARM1020T (rev 0) processor" - depends on ARCH_INTEGRATOR + bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR select CPU_32v5 select CPU_ABRT_EV4T select CPU_PABRT_NOIFAR @@ -266,8 +241,7 @@ config CPU_ARM1020 # ARM1020E - needs validating config CPU_ARM1020E - bool "Support ARM1020E processor" - depends on ARCH_INTEGRATOR + bool "Support ARM1020E processor" if ARCH_INTEGRATOR select CPU_32v5 select CPU_ABRT_EV4T select CPU_PABRT_NOIFAR @@ -280,8 +254,7 @@ config CPU_ARM1020E # ARM1022E config CPU_ARM1022 - bool "Support ARM1022E processor" - depends on ARCH_INTEGRATOR + bool "Support ARM1022E processor" if ARCH_INTEGRATOR select CPU_32v5 select CPU_ABRT_EV4T select CPU_PABRT_NOIFAR @@ -299,8 +272,7 @@ config CPU_ARM1022 # ARM1026EJ-S config CPU_ARM1026 - bool "Support ARM1026EJ-S processor" - depends on ARCH_INTEGRATOR + bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR select CPU_32v5 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 select CPU_PABRT_NOIFAR @@ -317,8 +289,7 @@ config CPU_ARM1026 # SA110 config CPU_SA110 - bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC - default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI + bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC select CPU_32v3 if ARCH_RPC select CPU_32v4 if !ARCH_RPC select CPU_ABRT_EV4 @@ -340,8 +311,6 @@ config CPU_SA110 # SA1100 config CPU_SA1100 bool - depends on ARCH_SA1100 - default y select CPU_32v4 select CPU_ABRT_EV4 select CPU_PABRT_NOIFAR @@ -353,8 +322,6 @@ config CPU_SA1100 # XScale config CPU_XSCALE bool - depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000 - default y select CPU_32v5 select CPU_ABRT_EV5T select CPU_PABRT_NOIFAR @@ -365,8 +332,6 @@ config CPU_XSCALE # XScale Core Version 3 config CPU_XSC3 bool - depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx - default y select CPU_32v5 select CPU_ABRT_EV5T select CPU_PABRT_NOIFAR @@ -378,8 +343,6 @@ config CPU_XSC3 # Feroceon config CPU_FEROCEON bool - depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0 - default y select CPU_32v5 select CPU_ABRT_EV5T select CPU_PABRT_NOIFAR @@ -399,10 +362,7 @@ config CPU_FEROCEON_OLD_ID # ARMv6 config CPU_V6 - bool "Support ARM V6 processor" - depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 - default y if ARCH_MX3 - default y if ARCH_MSM + bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB select CPU_32v6 select CPU_ABRT_EV6 select CPU_PABRT_NOIFAR @@ -427,8 +387,7 @@ config CPU_32v6K # ARMv7 config CPU_V7 - bool "Support ARM V7 processor" - depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP3 + bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB select CPU_32v6K select CPU_32v7 select CPU_ABRT_EV7 @@ -745,7 +704,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH config CACHE_L2X0 bool "Enable the L2x0 outer cache controller" - depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 + depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || REALVIEW_EB_A9MP default y select OUTER_CACHE help diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 2d5884c..3a398be 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -17,6 +17,7 @@ #include <linux/string.h> #include <linux/proc_fs.h> #include <linux/init.h> +#include <linux/sched.h> #include <linux/uaccess.h> #include <asm/unaligned.h> diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S index 3b3639e..8a4abeb 100644 --- a/arch/arm/mm/cache-v3.S +++ b/arch/arm/mm/cache-v3.S @@ -9,7 +9,6 @@ */ #include <linux/linkage.h> #include <linux/init.h> -#include <mach/hardware.h> #include <asm/page.h> #include "proc-macros.S" diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S index 5786adf1..3668611 100644 --- a/arch/arm/mm/cache-v4.S +++ b/arch/arm/mm/cache-v4.S @@ -9,7 +9,6 @@ */ #include <linux/linkage.h> #include <linux/init.h> -#include <mach/hardware.h> #include <asm/page.h> #include "proc-macros.S" diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S index 51a9b0b..c54fa2c 100644 --- a/arch/arm/mm/cache-v4wt.S +++ b/arch/arm/mm/cache-v4wt.S @@ -13,7 +13,6 @@ */ #include <linux/linkage.h> #include <linux/init.h> -#include <mach/hardware.h> #include <asm/page.h> #include "proc-macros.S" diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index d19c2be..be93ff0 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -26,6 +26,7 @@ * - mm - mm_struct describing address space */ ENTRY(v7_flush_dcache_all) + dmb @ ensure ordering with previous memory accesses mrc p15, 1, r0, c0, c0, 1 @ read clidr ands r3, r0, #0x7000000 @ extract loc from clidr mov r3, r3, lsr #23 @ left align loc bit field @@ -64,6 +65,7 @@ skip: finished: mov r10, #0 @ swith back to cache level 0 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + dsb isb mov pc, lr ENDPROC(v7_flush_dcache_all) diff --git a/arch/arm/mm/copypage-feroceon.S b/arch/arm/mm/copypage-feroceon.S deleted file mode 100644 index 7eb0d32..0000000 --- a/arch/arm/mm/copypage-feroceon.S +++ /dev/null @@ -1,95 +0,0 @@ -/* - * linux/arch/arm/lib/copypage-feroceon.S - * - * Copyright (C) 2008 Marvell Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This handles copy_user_page and clear_user_page on Feroceon - * more optimally than the generic implementations. - */ -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/asm-offsets.h> - - .text - .align 5 - -ENTRY(feroceon_copy_user_page) - stmfd sp!, {r4-r9, lr} - mov ip, #PAGE_SZ -1: mov lr, r1 - ldmia r1!, {r2 - r9} - pld [lr, #32] - pld [lr, #64] - pld [lr, #96] - pld [lr, #128] - pld [lr, #160] - pld [lr, #192] - pld [lr, #224] - stmia r0, {r2 - r9} - ldmia r1!, {r2 - r9} - mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line - add r0, r0, #32 - stmia r0, {r2 - r9} - ldmia r1!, {r2 - r9} - mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line - add r0, r0, #32 - stmia r0, {r2 - r9} - ldmia r1!, {r2 - r9} - mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line - add r0, r0, #32 - stmia r0, {r2 - r9} - ldmia r1!, {r2 - r9} - mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line - add r0, r0, #32 - stmia r0, {r2 - r9} - ldmia r1!, {r2 - r9} - mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line - add r0, r0, #32 - stmia r0, {r2 - r9} - ldmia r1!, {r2 - r9} - mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line - add r0, r0, #32 - stmia r0, {r2 - r9} - ldmia r1!, {r2 - r9} - mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line - add r0, r0, #32 - stmia r0, {r2 - r9} - subs ip, ip, #(32 * 8) - mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line - add r0, r0, #32 - bne 1b - mcr p15, 0, ip, c7, c10, 4 @ drain WB - ldmfd sp!, {r4-r9, pc} - - .align 5 - -ENTRY(feroceon_clear_user_page) - stmfd sp!, {r4-r7, lr} - mov r1, #PAGE_SZ/32 - mov r2, #0 - mov r3, #0 - mov r4, #0 - mov r5, #0 - mov r6, #0 - mov r7, #0 - mov ip, #0 - mov lr, #0 -1: stmia r0, {r2-r7, ip, lr} - subs r1, r1, #1 - mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line - add r0, r0, #32 - bne 1b - mcr p15, 0, r1, c7, c10, 4 @ drain WB - ldmfd sp!, {r4-r7, pc} - - __INITDATA - - .type feroceon_user_fns, #object -ENTRY(feroceon_user_fns) - .long feroceon_clear_user_page - .long feroceon_copy_user_page - .size feroceon_user_fns, . - feroceon_user_fns diff --git a/arch/arm/mm/copypage-feroceon.c b/arch/arm/mm/copypage-feroceon.c new file mode 100644 index 0000000..c3ba6a9 --- /dev/null +++ b/arch/arm/mm/copypage-feroceon.c @@ -0,0 +1,111 @@ +/* + * linux/arch/arm/mm/copypage-feroceon.S + * + * Copyright (C) 2008 Marvell Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This handles copy_user_highpage and clear_user_page on Feroceon + * more optimally than the generic implementations. + */ +#include <linux/init.h> +#include <linux/highmem.h> + +static void __attribute__((naked)) +feroceon_copy_user_page(void *kto, const void *kfrom) +{ + asm("\ + stmfd sp!, {r4-r9, lr} \n\ + mov ip, %0 \n\ +1: mov lr, r1 \n\ + ldmia r1!, {r2 - r9} \n\ + pld [lr, #32] \n\ + pld [lr, #64] \n\ + pld [lr, #96] \n\ + pld [lr, #128] \n\ + pld [lr, #160] \n\ + pld [lr, #192] \n\ + pld [lr, #224] \n\ + stmia r0, {r2 - r9} \n\ + ldmia r1!, {r2 - r9} \n\ + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ + add r0, r0, #32 \n\ + stmia r0, {r2 - r9} \n\ + ldmia r1!, {r2 - r9} \n\ + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ + add r0, r0, #32 \n\ + stmia r0, {r2 - r9} \n\ + ldmia r1!, {r2 - r9} \n\ + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ + add r0, r0, #32 \n\ + stmia r0, {r2 - r9} \n\ + ldmia r1!, {r2 - r9} \n\ + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ + add r0, r0, #32 \n\ + stmia r0, {r2 - r9} \n\ + ldmia r1!, {r2 - r9} \n\ + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ + add r0, r0, #32 \n\ + stmia r0, {r2 - r9} \n\ + ldmia r1!, {r2 - r9} \n\ + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ + add r0, r0, #32 \n\ + stmia r0, {r2 - r9} \n\ + ldmia r1!, {r2 - r9} \n\ + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ + add r0, r0, #32 \n\ + stmia r0, {r2 - r9} \n\ + subs ip, ip, #(32 * 8) \n\ + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ + add r0, r0, #32 \n\ + bne 1b \n\ + mcr p15, 0, ip, c7, c10, 4 @ drain WB\n\ + ldmfd sp!, {r4-r9, pc}" + : + : "I" (PAGE_SIZE)); +} + +void feroceon_copy_user_highpage(struct page *to, struct page *from, + unsigned long vaddr) +{ + void *kto, *kfrom; + + kto = kmap_atomic(to, KM_USER0); + kfrom = kmap_atomic(from, KM_USER1); + feroceon_copy_user_page(kto, kfrom); + kunmap_atomic(kfrom, KM_USER1); + kunmap_atomic(kto, KM_USER0); +} + +void feroceon_clear_user_highpage(struct page *page, unsigned long vaddr) +{ + void *ptr, *kaddr = kmap_atomic(page, KM_USER0); + asm volatile ("\ + mov r1, %2 \n\ + mov r2, #0 \n\ + mov r3, #0 \n\ + mov r4, #0 \n\ + mov r5, #0 \n\ + mov r6, #0 \n\ + mov r7, #0 \n\ + mov ip, #0 \n\ + mov lr, #0 \n\ +1: stmia %0, {r2-r7, ip, lr} \n\ + subs r1, r1, #1 \n\ + mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ + add %0, %0, #32 \n\ + bne 1b \n\ + mcr p15, 0, r1, c7, c10, 4 @ drain WB" + : "=r" (ptr) + : "0" (kaddr), "I" (PAGE_SIZE / 32) + : "r1", "r2", "r3", "r4", "r5", "r6", "r7", "ip", "lr"); + kunmap_atomic(kaddr, KM_USER0); +} + +struct cpu_user_fns feroceon_user_fns __initdata = { + .cpu_clear_user_highpage = feroceon_clear_user_highpage, + .cpu_copy_user_highpage = feroceon_copy_user_highpage, +}; + diff --git a/arch/arm/mm/copypage-v3.S b/arch/arm/mm/copypage-v3.S deleted file mode 100644 index 2ee394b..0000000 --- a/arch/arm/mm/copypage-v3.S +++ /dev/null @@ -1,67 +0,0 @@ -/* - * linux/arch/arm/lib/copypage.S - * - * Copyright (C) 1995-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * ASM optimised string functions - */ -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/assembler.h> -#include <asm/asm-offsets.h> - - .text - .align 5 -/* - * ARMv3 optimised copy_user_page - * - * FIXME: do we need to handle cache stuff... - */ -ENTRY(v3_copy_user_page) - stmfd sp!, {r4, lr} @ 2 - mov r2, #PAGE_SZ/64 @ 1 - ldmia r1!, {r3, r4, ip, lr} @ 4+1 -1: stmia r0!, {r3, r4, ip, lr} @ 4 - ldmia r1!, {r3, r4, ip, lr} @ 4+1 - stmia r0!, {r3, r4, ip, lr} @ 4 - ldmia r1!, {r3, r4, ip, lr} @ 4+1 - stmia r0!, {r3, r4, ip, lr} @ 4 - ldmia r1!, {r3, r4, ip, lr} @ 4 - subs r2, r2, #1 @ 1 - stmia r0!, {r3, r4, ip, lr} @ 4 - ldmneia r1!, {r3, r4, ip, lr} @ 4 - bne 1b @ 1 - ldmfd sp!, {r4, pc} @ 3 - - .align 5 -/* - * ARMv3 optimised clear_user_page - * - * FIXME: do we need to handle cache stuff... - */ -ENTRY(v3_clear_user_page) - str lr, [sp, #-4]! - mov r1, #PAGE_SZ/64 @ 1 - mov r2, #0 @ 1 - mov r3, #0 @ 1 - mov ip, #0 @ 1 - mov lr, #0 @ 1 -1: stmia r0!, {r2, r3, ip, lr} @ 4 - stmia r0!, {r2, r3, ip, lr} @ 4 - stmia r0!, {r2, r3, ip, lr} @ 4 - stmia r0!, {r2, r3, ip, lr} @ 4 - subs r1, r1, #1 @ 1 - bne 1b @ 1 - ldr pc, [sp], #4 - - __INITDATA - - .type v3_user_fns, #object -ENTRY(v3_user_fns) - .long v3_clear_user_page - .long v3_copy_user_page - .size v3_user_fns, . - v3_user_fns diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c new file mode 100644 index 0000000..70ed96c --- /dev/null +++ b/arch/arm/mm/copypage-v3.c @@ -0,0 +1,81 @@ +/* + * linux/arch/arm/mm/copypage-v3.c + * + * Copyright (C) 1995-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/highmem.h> + +/* + * ARMv3 optimised copy_user_highpage + * + * FIXME: do we need to handle cache stuff... + */ +static void __attribute__((naked)) +v3_copy_user_page(void *kto, const void *kfrom) +{ + asm("\n\ + stmfd sp!, {r4, lr} @ 2\n\ + mov r2, %2 @ 1\n\ + ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\ +1: stmia %1!, {r3, r4, ip, lr} @ 4\n\ + ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\ + stmia %1!, {r3, r4, ip, lr} @ 4\n\ + ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\ + stmia %1!, {r3, r4, ip, lr} @ 4\n\ + ldmia %0!, {r3, r4, ip, lr} @ 4\n\ + subs r2, r2, #1 @ 1\n\ + stmia %1!, {r3, r4, ip, lr} @ 4\n\ + ldmneia %0!, {r3, r4, ip, lr} @ 4\n\ + bne 1b @ 1\n\ + ldmfd sp!, {r4, pc} @ 3" + : + : "r" (kfrom), "r" (kto), "I" (PAGE_SIZE / 64)); +} + +void v3_copy_user_highpage(struct page *to, struct page *from, + unsigned long vaddr) +{ + void *kto, *kfrom; + + kto = kmap_atomic(to, KM_USER0); + kfrom = kmap_atomic(from, KM_USER1); + v3_copy_user_page(kto, kfrom); + kunmap_atomic(kfrom, KM_USER1); + kunmap_atomic(kto, KM_USER0); +} + +/* + * ARMv3 optimised clear_user_page + * + * FIXME: do we need to handle cache stuff... + */ +void v3_clear_user_highpage(struct page *page, unsigned long vaddr) +{ + void *ptr, *kaddr = kmap_atomic(page, KM_USER0); + asm volatile("\n\ + mov r1, %2 @ 1\n\ + mov r2, #0 @ 1\n\ + mov r3, #0 @ 1\n\ + mov ip, #0 @ 1\n\ + mov lr, #0 @ 1\n\ +1: stmia %0!, {r2, r3, ip, lr} @ 4\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ + subs r1, r1, #1 @ 1\n\ + bne 1b @ 1" + : "=r" (ptr) + : "0" (kaddr), "I" (PAGE_SIZE / 64) + : "r1", "r2", "r3", "ip", "lr"); + kunmap_atomic(kaddr, KM_USER0); +} + +struct cpu_user_fns v3_user_fns __initdata = { + .cpu_clear_user_highpage = v3_clear_user_highpage, + .cpu_copy_user_highpage = v3_copy_user_highpage, +}; diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c index 8d33e25..bdb5fd9 100644 --- a/arch/arm/mm/copypage-v4mc.c +++ b/arch/arm/mm/copypage-v4mc.c @@ -15,8 +15,8 @@ */ #include <linux/init.h> #include <linux/mm.h> +#include <linux/highmem.h> -#include <asm/page.h> #include <asm/pgtable.h> #include <asm/tlbflush.h> #include <asm/cacheflush.h> @@ -33,7 +33,7 @@ static DEFINE_SPINLOCK(minicache_lock); /* - * ARMv4 mini-dcache optimised copy_user_page + * ARMv4 mini-dcache optimised copy_user_highpage * * We flush the destination cache lines just before we write the data into the * corresponding address. Since the Dcache is read-allocate, this removes the @@ -42,7 +42,7 @@ static DEFINE_SPINLOCK(minicache_lock); * * Note: We rely on all ARMv4 processors implementing the "invalidate D line" * instruction. If your processor does not supply this, you have to write your - * own copy_user_page that does the right thing. + * own copy_user_highpage that does the right thing. */ static void __attribute__((naked)) mc_copy_user_page(void *from, void *to) @@ -68,50 +68,53 @@ mc_copy_user_page(void *from, void *to) : "r" (from), "r" (to), "I" (PAGE_SIZE / 64)); } -void v4_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr) +void v4_mc_copy_user_highpage(struct page *from, struct page *to, + unsigned long vaddr) { - struct page *page = virt_to_page(kfrom); + void *kto = kmap_atomic(to, KM_USER1); - if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) - __flush_dcache_page(page_mapping(page), page); + if (test_and_clear_bit(PG_dcache_dirty, &from->flags)) + __flush_dcache_page(page_mapping(from), from); spin_lock(&minicache_lock); - set_pte_ext(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0); + set_pte_ext(TOP_PTE(0xffff8000), pfn_pte(page_to_pfn(from), minicache_pgprot), 0); flush_tlb_kernel_page(0xffff8000); mc_copy_user_page((void *)0xffff8000, kto); spin_unlock(&minicache_lock); + + kunmap_atomic(kto, KM_USER1); } /* * ARMv4 optimised clear_user_page */ -void __attribute__((naked)) -v4_mc_clear_user_page(void *kaddr, unsigned long vaddr) +void v4_mc_clear_user_highpage(struct page *page, unsigned long vaddr) { - asm volatile( - "str lr, [sp, #-4]!\n\ - mov r1, %0 @ 1\n\ + void *ptr, *kaddr = kmap_atomic(page, KM_USER0); + asm volatile("\ + mov r1, %2 @ 1\n\ mov r2, #0 @ 1\n\ mov r3, #0 @ 1\n\ mov ip, #0 @ 1\n\ mov lr, #0 @ 1\n\ -1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ - stmia r0!, {r2, r3, ip, lr} @ 4\n\ - stmia r0!, {r2, r3, ip, lr} @ 4\n\ - mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ - stmia r0!, {r2, r3, ip, lr} @ 4\n\ - stmia r0!, {r2, r3, ip, lr} @ 4\n\ +1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ + mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ subs r1, r1, #1 @ 1\n\ - bne 1b @ 1\n\ - ldr pc, [sp], #4" - : - : "I" (PAGE_SIZE / 64)); + bne 1b @ 1" + : "=r" (ptr) + : "0" (kaddr), "I" (PAGE_SIZE / 64) + : "r1", "r2", "r3", "ip", "lr"); + kunmap_atomic(kaddr, KM_USER0); } struct cpu_user_fns v4_mc_user_fns __initdata = { - .cpu_clear_user_page = v4_mc_clear_user_page, - .cpu_copy_user_page = v4_mc_copy_user_page, + .cpu_clear_user_highpage = v4_mc_clear_user_highpage, + .cpu_copy_user_highpage = v4_mc_copy_user_highpage, }; diff --git a/arch/arm/mm/copypage-v4wb.S b/arch/arm/mm/copypage-v4wb.S deleted file mode 100644 index 8311735..0000000 --- a/arch/arm/mm/copypage-v4wb.S +++ /dev/null @@ -1,79 +0,0 @@ -/* - * linux/arch/arm/lib/copypage.S - * - * Copyright (C) 1995-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * ASM optimised string functions - */ -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/asm-offsets.h> - - .text - .align 5 -/* - * ARMv4 optimised copy_user_page - * - * We flush the destination cache lines just before we write the data into the - * corresponding address. Since the Dcache is read-allocate, this removes the - * Dcache aliasing issue. The writes will be forwarded to the write buffer, - * and merged as appropriate. - * - * Note: We rely on all ARMv4 processors implementing the "invalidate D line" - * instruction. If your processor does not supply this, you have to write your - * own copy_user_page that does the right thing. - */ -ENTRY(v4wb_copy_user_page) - stmfd sp!, {r4, lr} @ 2 - mov r2, #PAGE_SZ/64 @ 1 - ldmia r1!, {r3, r4, ip, lr} @ 4 -1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line - stmia r0!, {r3, r4, ip, lr} @ 4 - ldmia r1!, {r3, r4, ip, lr} @ 4+1 - stmia r0!, {r3, r4, ip, lr} @ 4 - ldmia r1!, {r3, r4, ip, lr} @ 4 - mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line - stmia r0!, {r3, r4, ip, lr} @ 4 - ldmia r1!, {r3, r4, ip, lr} @ 4 - subs r2, r2, #1 @ 1 - stmia r0!, {r3, r4, ip, lr} @ 4 - ldmneia r1!, {r3, r4, ip, lr} @ 4 - bne 1b @ 1 - mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB - ldmfd sp!, {r4, pc} @ 3 - - .align 5 -/* - * ARMv4 optimised clear_user_page - * - * Same story as above. - */ -ENTRY(v4wb_clear_user_page) - str lr, [sp, #-4]! - mov r1, #PAGE_SZ/64 @ 1 - mov r2, #0 @ 1 - mov r3, #0 @ 1 - mov ip, #0 @ 1 - mov lr, #0 @ 1 -1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line - stmia r0!, {r2, r3, ip, lr} @ 4 - stmia r0!, {r2, r3, ip, lr} @ 4 - mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line - stmia r0!, {r2, r3, ip, lr} @ 4 - stmia r0!, {r2, r3, ip, lr} @ 4 - subs r1, r1, #1 @ 1 - bne 1b @ 1 - mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB - ldr pc, [sp], #4 - - __INITDATA - - .type v4wb_user_fns, #object -ENTRY(v4wb_user_fns) - .long v4wb_clear_user_page - .long v4wb_copy_user_page - .size v4wb_user_fns, . - v4wb_user_fns diff --git a/arch/arm/mm/copypage-v4wb.c b/arch/arm/mm/copypage-v4wb.c new file mode 100644 index 0000000..3ec93da --- /dev/null +++ b/arch/arm/mm/copypage-v4wb.c @@ -0,0 +1,94 @@ +/* + * linux/arch/arm/mm/copypage-v4wb.c + * + * Copyright (C) 1995-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/highmem.h> + +/* + * ARMv4 optimised copy_user_highpage + * + * We flush the destination cache lines just before we write the data into the + * corresponding address. Since the Dcache is read-allocate, this removes the + * Dcache aliasing issue. The writes will be forwarded to the write buffer, + * and merged as appropriate. + * + * Note: We rely on all ARMv4 processors implementing the "invalidate D line" + * instruction. If your processor does not supply this, you have to write your + * own copy_user_highpage that does the right thing. + */ +static void __attribute__((naked)) +v4wb_copy_user_page(void *kto, const void *kfrom) +{ + asm("\ + stmfd sp!, {r4, lr} @ 2\n\ + mov r2, %0 @ 1\n\ + ldmia r1!, {r3, r4, ip, lr} @ 4\n\ +1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ + stmia r0!, {r3, r4, ip, lr} @ 4\n\ + ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\ + stmia r0!, {r3, r4, ip, lr} @ 4\n\ + ldmia r1!, {r3, r4, ip, lr} @ 4\n\ + mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ + stmia r0!, {r3, r4, ip, lr} @ 4\n\ + ldmia r1!, {r3, r4, ip, lr} @ 4\n\ + subs r2, r2, #1 @ 1\n\ + stmia r0!, {r3, r4, ip, lr} @ 4\n\ + ldmneia r1!, {r3, r4, ip, lr} @ 4\n\ + bne 1b @ 1\n\ + mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\ + ldmfd sp!, {r4, pc} @ 3" + : + : "I" (PAGE_SIZE / 64)); +} + +void v4wb_copy_user_highpage(struct page *to, struct page *from, + unsigned long vaddr) +{ + void *kto, *kfrom; + + kto = kmap_atomic(to, KM_USER0); + kfrom = kmap_atomic(from, KM_USER1); + v4wb_copy_user_page(kto, kfrom); + kunmap_atomic(kfrom, KM_USER1); + kunmap_atomic(kto, KM_USER0); +} + +/* + * ARMv4 optimised clear_user_page + * + * Same story as above. + */ +void v4wb_clear_user_highpage(struct page *page, unsigned long vaddr) +{ + void *ptr, *kaddr = kmap_atomic(page, KM_USER0); + asm volatile("\ + mov r1, %2 @ 1\n\ + mov r2, #0 @ 1\n\ + mov r3, #0 @ 1\n\ + mov ip, #0 @ 1\n\ + mov lr, #0 @ 1\n\ +1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ + mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ + subs r1, r1, #1 @ 1\n\ + bne 1b @ 1\n\ + mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB" + : "=r" (ptr) + : "0" (kaddr), "I" (PAGE_SIZE / 64) + : "r1", "r2", "r3", "ip", "lr"); + kunmap_atomic(kaddr, KM_USER0); +} + +struct cpu_user_fns v4wb_user_fns __initdata = { + .cpu_clear_user_highpage = v4wb_clear_user_highpage, + .cpu_copy_user_highpage = v4wb_copy_user_highpage, +}; diff --git a/arch/arm/mm/copypage-v4wt.S b/arch/arm/mm/copypage-v4wt.S deleted file mode 100644 index e1f2af2..0000000 --- a/arch/arm/mm/copypage-v4wt.S +++ /dev/null @@ -1,73 +0,0 @@ -/* - * linux/arch/arm/lib/copypage-v4.S - * - * Copyright (C) 1995-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * ASM optimised string functions - * - * This is for CPUs with a writethrough cache and 'flush ID cache' is - * the only supported cache operation. - */ -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/asm-offsets.h> - - .text - .align 5 -/* - * ARMv4 optimised copy_user_page - * - * Since we have writethrough caches, we don't have to worry about - * dirty data in the cache. However, we do have to ensure that - * subsequent reads are up to date. - */ -ENTRY(v4wt_copy_user_page) - stmfd sp!, {r4, lr} @ 2 - mov r2, #PAGE_SZ/64 @ 1 - ldmia r1!, {r3, r4, ip, lr} @ 4 -1: stmia r0!, {r3, r4, ip, lr} @ 4 - ldmia r1!, {r3, r4, ip, lr} @ 4+1 - stmia r0!, {r3, r4, ip, lr} @ 4 - ldmia r1!, {r3, r4, ip, lr} @ 4 - stmia r0!, {r3, r4, ip, lr} @ 4 - ldmia r1!, {r3, r4, ip, lr} @ 4 - subs r2, r2, #1 @ 1 - stmia r0!, {r3, r4, ip, lr} @ 4 - ldmneia r1!, {r3, r4, ip, lr} @ 4 - bne 1b @ 1 - mcr p15, 0, r2, c7, c7, 0 @ flush ID cache - ldmfd sp!, {r4, pc} @ 3 - - .align 5 -/* - * ARMv4 optimised clear_user_page - * - * Same story as above. - */ -ENTRY(v4wt_clear_user_page) - str lr, [sp, #-4]! - mov r1, #PAGE_SZ/64 @ 1 - mov r2, #0 @ 1 - mov r3, #0 @ 1 - mov ip, #0 @ 1 - mov lr, #0 @ 1 -1: stmia r0!, {r2, r3, ip, lr} @ 4 - stmia r0!, {r2, r3, ip, lr} @ 4 - stmia r0!, {r2, r3, ip, lr} @ 4 - stmia r0!, {r2, r3, ip, lr} @ 4 - subs r1, r1, #1 @ 1 - bne 1b @ 1 - mcr p15, 0, r2, c7, c7, 0 @ flush ID cache - ldr pc, [sp], #4 - - __INITDATA - - .type v4wt_user_fns, #object -ENTRY(v4wt_user_fns) - .long v4wt_clear_user_page - .long v4wt_copy_user_page - .size v4wt_user_fns, . - v4wt_user_fns diff --git a/arch/arm/mm/copypage-v4wt.c b/arch/arm/mm/copypage-v4wt.c new file mode 100644 index 0000000..0f1188e --- /dev/null +++ b/arch/arm/mm/copypage-v4wt.c @@ -0,0 +1,88 @@ +/* + * linux/arch/arm/mm/copypage-v4wt.S + * + * Copyright (C) 1995-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This is for CPUs with a writethrough cache and 'flush ID cache' is + * the only supported cache operation. + */ +#include <linux/init.h> +#include <linux/highmem.h> + +/* + * ARMv4 optimised copy_user_highpage + * + * Since we have writethrough caches, we don't have to worry about + * dirty data in the cache. However, we do have to ensure that + * subsequent reads are up to date. + */ +static void __attribute__((naked)) +v4wt_copy_user_page(void *kto, const void *kfrom) +{ + asm("\ + stmfd sp!, {r4, lr} @ 2\n\ + mov r2, %0 @ 1\n\ + ldmia r1!, {r3, r4, ip, lr} @ 4\n\ +1: stmia r0!, {r3, r4, ip, lr} @ 4\n\ + ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\ + stmia r0!, {r3, r4, ip, lr} @ 4\n\ + ldmia r1!, {r3, r4, ip, lr} @ 4\n\ + stmia r0!, {r3, r4, ip, lr} @ 4\n\ + ldmia r1!, {r3, r4, ip, lr} @ 4\n\ + subs r2, r2, #1 @ 1\n\ + stmia r0!, {r3, r4, ip, lr} @ 4\n\ + ldmneia r1!, {r3, r4, ip, lr} @ 4\n\ + bne 1b @ 1\n\ + mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\ + ldmfd sp!, {r4, pc} @ 3" + : + : "I" (PAGE_SIZE / 64)); +} + +void v4wt_copy_user_highpage(struct page *to, struct page *from, + unsigned long vaddr) +{ + void *kto, *kfrom; + + kto = kmap_atomic(to, KM_USER0); + kfrom = kmap_atomic(from, KM_USER1); + v4wt_copy_user_page(kto, kfrom); + kunmap_atomic(kfrom, KM_USER1); + kunmap_atomic(kto, KM_USER0); +} + +/* + * ARMv4 optimised clear_user_page + * + * Same story as above. + */ +void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr) +{ + void *ptr, *kaddr = kmap_atomic(page, KM_USER0); + asm volatile("\ + mov r1, %2 @ 1\n\ + mov r2, #0 @ 1\n\ + mov r3, #0 @ 1\n\ + mov ip, #0 @ 1\n\ + mov lr, #0 @ 1\n\ +1: stmia %0!, {r2, r3, ip, lr} @ 4\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ + stmia %0!, {r2, r3, ip, lr} @ 4\n\ + subs r1, r1, #1 @ 1\n\ + bne 1b @ 1\n\ + mcr p15, 0, r2, c7, c7, 0 @ flush ID cache" + : "=r" (ptr) + : "0" (kaddr), "I" (PAGE_SIZE / 64) + : "r1", "r2", "r3", "ip", "lr"); + kunmap_atomic(kaddr, KM_USER0); +} + +struct cpu_user_fns v4wt_user_fns __initdata = { + .cpu_clear_user_highpage = v4wt_clear_user_highpage, + .cpu_copy_user_highpage = v4wt_copy_user_highpage, +}; diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c index 0e21c07..4127a7b 100644 --- a/arch/arm/mm/copypage-v6.c +++ b/arch/arm/mm/copypage-v6.c @@ -10,8 +10,8 @@ #include <linux/init.h> #include <linux/spinlock.h> #include <linux/mm.h> +#include <linux/highmem.h> -#include <asm/page.h> #include <asm/pgtable.h> #include <asm/shmparam.h> #include <asm/tlbflush.h> @@ -33,41 +33,56 @@ static DEFINE_SPINLOCK(v6_lock); * Copy the user page. No aliasing to deal with so we can just * attack the kernel's existing mapping of these pages. */ -static void v6_copy_user_page_nonaliasing(void *kto, const void *kfrom, unsigned long vaddr) +static void v6_copy_user_highpage_nonaliasing(struct page *to, + struct page *from, unsigned long vaddr) { + void *kto, *kfrom; + + kfrom = kmap_atomic(from, KM_USER0); + kto = kmap_atomic(to, KM_USER1); copy_page(kto, kfrom); + kunmap_atomic(kto, KM_USER1); + kunmap_atomic(kfrom, KM_USER0); } /* * Clear the user page. No aliasing to deal with so we can just * attack the kernel's existing mapping of this page. */ -static void v6_clear_user_page_nonaliasing(void *kaddr, unsigned long vaddr) +static void v6_clear_user_highpage_nonaliasing(struct page *page, unsigned long vaddr) { + void *kaddr = kmap_atomic(page, KM_USER0); clear_page(kaddr); + kunmap_atomic(kaddr, KM_USER0); } /* - * Copy the page, taking account of the cache colour. + * Discard data in the kernel mapping for the new page. + * FIXME: needs this MCRR to be supported. */ -static void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned long vaddr) +static void discard_old_kernel_data(void *kto) { - unsigned int offset = CACHE_COLOUR(vaddr); - unsigned long from, to; - struct page *page = virt_to_page(kfrom); - - if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) - __flush_dcache_page(page_mapping(page), page); - - /* - * Discard data in the kernel mapping for the new page. - * FIXME: needs this MCRR to be supported. - */ __asm__("mcrr p15, 0, %1, %0, c6 @ 0xec401f06" : : "r" (kto), "r" ((unsigned long)kto + PAGE_SIZE - L1_CACHE_BYTES) : "cc"); +} + +/* + * Copy the page, taking account of the cache colour. + */ +static void v6_copy_user_highpage_aliasing(struct page *to, + struct page *from, unsigned long vaddr) +{ + unsigned int offset = CACHE_COLOUR(vaddr); + unsigned long kfrom, kto; + + if (test_and_clear_bit(PG_dcache_dirty, &from->flags)) + __flush_dcache_page(page_mapping(from), from); + + /* FIXME: not highmem safe */ + discard_old_kernel_data(page_address(to)); /* * Now copy the page using the same cache colour as the @@ -75,16 +90,16 @@ static void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned lo */ spin_lock(&v6_lock); - set_pte_ext(TOP_PTE(from_address) + offset, pfn_pte(__pa(kfrom) >> PAGE_SHIFT, PAGE_KERNEL), 0); - set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(__pa(kto) >> PAGE_SHIFT, PAGE_KERNEL), 0); + set_pte_ext(TOP_PTE(from_address) + offset, pfn_pte(page_to_pfn(from), PAGE_KERNEL), 0); + set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(page_to_pfn(to), PAGE_KERNEL), 0); - from = from_address + (offset << PAGE_SHIFT); - to = to_address + (offset << PAGE_SHIFT); + kfrom = from_address + (offset << PAGE_SHIFT); + kto = to_address + (offset << PAGE_SHIFT); - flush_tlb_kernel_page(from); - flush_tlb_kernel_page(to); + flush_tlb_kernel_page(kfrom); + flush_tlb_kernel_page(kto); - copy_page((void *)to, (void *)from); + copy_page((void *)kto, (void *)kfrom); spin_unlock(&v6_lock); } @@ -94,20 +109,13 @@ static void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned lo * so remap the kernel page into the same cache colour as the user * page. */ -static void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr) +static void v6_clear_user_highpage_aliasing(struct page *page, unsigned long vaddr) { unsigned int offset = CACHE_COLOUR(vaddr); unsigned long to = to_address + (offset << PAGE_SHIFT); - /* - * Discard data in the kernel mapping for the new page - * FIXME: needs this MCRR to be supported. - */ - __asm__("mcrr p15, 0, %1, %0, c6 @ 0xec401f06" - : - : "r" (kaddr), - "r" ((unsigned long)kaddr + PAGE_SIZE - L1_CACHE_BYTES) - : "cc"); + /* FIXME: not highmem safe */ + discard_old_kernel_data(page_address(page)); /* * Now clear the page using the same cache colour as @@ -115,7 +123,7 @@ static void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr) */ spin_lock(&v6_lock); - set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(__pa(kaddr) >> PAGE_SHIFT, PAGE_KERNEL), 0); + set_pte_ext(TOP_PTE(to_address) + offset, pfn_pte(page_to_pfn(page), PAGE_KERNEL), 0); flush_tlb_kernel_page(to); clear_page((void *)to); @@ -123,15 +131,15 @@ static void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr) } struct cpu_user_fns v6_user_fns __initdata = { - .cpu_clear_user_page = v6_clear_user_page_nonaliasing, - .cpu_copy_user_page = v6_copy_user_page_nonaliasing, + .cpu_clear_user_highpage = v6_clear_user_highpage_nonaliasing, + .cpu_copy_user_highpage = v6_copy_user_highpage_nonaliasing, }; static int __init v6_userpage_init(void) { if (cache_is_vipt_aliasing()) { - cpu_user.cpu_clear_user_page = v6_clear_user_page_aliasing; - cpu_user.cpu_copy_user_page = v6_copy_user_page_aliasing; + cpu_user.cpu_clear_user_highpage = v6_clear_user_highpage_aliasing; + cpu_user.cpu_copy_user_highpage = v6_copy_user_highpage_aliasing; } return 0; diff --git a/arch/arm/mm/copypage-xsc3.S b/arch/arm/mm/copypage-xsc3.S deleted file mode 100644 index 9a2cb43..0000000 --- a/arch/arm/mm/copypage-xsc3.S +++ /dev/null @@ -1,97 +0,0 @@ -/* - * linux/arch/arm/lib/copypage-xsc3.S - * - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Adapted for 3rd gen XScale core, no more mini-dcache - * Author: Matt Gilbert (matthew.m.gilbert@intel.com) - */ - -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/asm-offsets.h> - -/* - * General note: - * We don't really want write-allocate cache behaviour for these functions - * since that will just eat through 8K of the cache. - */ - - .text - .align 5 -/* - * XSC3 optimised copy_user_page - * r0 = destination - * r1 = source - * r2 = virtual user address of ultimate destination page - * - * The source page may have some clean entries in the cache already, but we - * can safely ignore them - break_cow() will flush them out of the cache - * if we eventually end up using our copied page. - * - */ -ENTRY(xsc3_mc_copy_user_page) - stmfd sp!, {r4, r5, lr} - mov lr, #PAGE_SZ/64-1 - - pld [r1, #0] - pld [r1, #32] -1: pld [r1, #64] - pld [r1, #96] - -2: ldrd r2, [r1], #8 - mov ip, r0 - ldrd r4, [r1], #8 - mcr p15, 0, ip, c7, c6, 1 @ invalidate - strd r2, [r0], #8 - ldrd r2, [r1], #8 - strd r4, [r0], #8 - ldrd r4, [r1], #8 - strd r2, [r0], #8 - strd r4, [r0], #8 - ldrd r2, [r1], #8 - mov ip, r0 - ldrd r4, [r1], #8 - mcr p15, 0, ip, c7, c6, 1 @ invalidate - strd r2, [r0], #8 - ldrd r2, [r1], #8 - subs lr, lr, #1 - strd r4, [r0], #8 - ldrd r4, [r1], #8 - strd r2, [r0], #8 - strd r4, [r0], #8 - bgt 1b - beq 2b - - ldmfd sp!, {r4, r5, pc} - - .align 5 -/* - * XScale optimised clear_user_page - * r0 = destination - * r1 = virtual user address of ultimate destination page - */ -ENTRY(xsc3_mc_clear_user_page) - mov r1, #PAGE_SZ/32 - mov r2, #0 - mov r3, #0 -1: mcr p15, 0, r0, c7, c6, 1 @ invalidate line - strd r2, [r0], #8 - strd r2, [r0], #8 - strd r2, [r0], #8 - strd r2, [r0], #8 - subs r1, r1, #1 - bne 1b - mov pc, lr - - __INITDATA - - .type xsc3_mc_user_fns, #object -ENTRY(xsc3_mc_user_fns) - .long xsc3_mc_clear_user_page - .long xsc3_mc_copy_user_page - .size xsc3_mc_user_fns, . - xsc3_mc_user_fns diff --git a/arch/arm/mm/copypage-xsc3.c b/arch/arm/mm/copypage-xsc3.c new file mode 100644 index 0000000..39a9945 --- /dev/null +++ b/arch/arm/mm/copypage-xsc3.c @@ -0,0 +1,113 @@ +/* + * linux/arch/arm/mm/copypage-xsc3.S + * + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Adapted for 3rd gen XScale core, no more mini-dcache + * Author: Matt Gilbert (matthew.m.gilbert@intel.com) + */ +#include <linux/init.h> +#include <linux/highmem.h> + +/* + * General note: + * We don't really want write-allocate cache behaviour for these functions + * since that will just eat through 8K of the cache. + */ + +/* + * XSC3 optimised copy_user_highpage + * r0 = destination + * r1 = source + * + * The source page may have some clean entries in the cache already, but we + * can safely ignore them - break_cow() will flush them out of the cache + * if we eventually end up using our copied page. + * + */ +static void __attribute__((naked)) +xsc3_mc_copy_user_page(void *kto, const void *kfrom) +{ + asm("\ + stmfd sp!, {r4, r5, lr} \n\ + mov lr, %0 \n\ + \n\ + pld [r1, #0] \n\ + pld [r1, #32] \n\ +1: pld [r1, #64] \n\ + pld [r1, #96] \n\ + \n\ +2: ldrd r2, [r1], #8 \n\ + mov ip, r0 \n\ + ldrd r4, [r1], #8 \n\ + mcr p15, 0, ip, c7, c6, 1 @ invalidate\n\ + strd r2, [r0], #8 \n\ + ldrd r2, [r1], #8 \n\ + strd r4, [r0], #8 \n\ + ldrd r4, [r1], #8 \n\ + strd r2, [r0], #8 \n\ + strd r4, [r0], #8 \n\ + ldrd r2, [r1], #8 \n\ + mov ip, r0 \n\ + ldrd r4, [r1], #8 \n\ + mcr p15, 0, ip, c7, c6, 1 @ invalidate\n\ + strd r2, [r0], #8 \n\ + ldrd r2, [r1], #8 \n\ + subs lr, lr, #1 \n\ + strd r4, [r0], #8 \n\ + ldrd r4, [r1], #8 \n\ + strd r2, [r0], #8 \n\ + strd r4, [r0], #8 \n\ + bgt 1b \n\ + beq 2b \n\ + \n\ + ldmfd sp!, {r4, r5, pc}" + : + : "I" (PAGE_SIZE / 64 - 1)); +} + +void xsc3_mc_copy_user_highpage(struct page *to, struct page *from, + unsigned long vaddr) +{ + void *kto, *kfrom; + + kto = kmap_atomic(to, KM_USER0); + kfrom = kmap_atomic(from, KM_USER1); + xsc3_mc_copy_user_page(kto, kfrom); + kunmap_atomic(kfrom, KM_USER1); + kunmap_atomic(kto, KM_USER0); +} + +/* + * XScale optimised clear_user_page + * r0 = destination + * r1 = virtual user address of ultimate destination page + */ +void xsc3_mc_clear_user_highpage(struct page *page, unsigned long vaddr) +{ + void *ptr, *kaddr = kmap_atomic(page, KM_USER0); + asm volatile ("\ + mov r1, %2 \n\ + mov r2, #0 \n\ + mov r3, #0 \n\ +1: mcr p15, 0, %0, c7, c6, 1 @ invalidate line\n\ + strd r2, [%0], #8 \n\ + strd r2, [%0], #8 \n\ + strd r2, [%0], #8 \n\ + strd r2, [%0], #8 \n\ + subs r1, r1, #1 \n\ + bne 1b" + : "=r" (ptr) + : "0" (kaddr), "I" (PAGE_SIZE / 32) + : "r1", "r2", "r3"); + kunmap_atomic(kaddr, KM_USER0); +} + +struct cpu_user_fns xsc3_mc_user_fns __initdata = { + .cpu_clear_user_highpage = xsc3_mc_clear_user_highpage, + .cpu_copy_user_highpage = xsc3_mc_copy_user_highpage, +}; diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c index bad4933..d18f239 100644 --- a/arch/arm/mm/copypage-xscale.c +++ b/arch/arm/mm/copypage-xscale.c @@ -15,8 +15,8 @@ */ #include <linux/init.h> #include <linux/mm.h> +#include <linux/highmem.h> -#include <asm/page.h> #include <asm/pgtable.h> #include <asm/tlbflush.h> #include <asm/cacheflush.h> @@ -35,7 +35,7 @@ static DEFINE_SPINLOCK(minicache_lock); /* - * XScale mini-dcache optimised copy_user_page + * XScale mini-dcache optimised copy_user_highpage * * We flush the destination cache lines just before we write the data into the * corresponding address. Since the Dcache is read-allocate, this removes the @@ -90,48 +90,53 @@ mc_copy_user_page(void *from, void *to) : "r" (from), "r" (to), "I" (PAGE_SIZE / 64 - 1)); } -void xscale_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr) +void xscale_mc_copy_user_highpage(struct page *to, struct page *from, + unsigned long vaddr) { - struct page *page = virt_to_page(kfrom); + void *kto = kmap_atomic(to, KM_USER1); - if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) - __flush_dcache_page(page_mapping(page), page); + if (test_and_clear_bit(PG_dcache_dirty, &from->flags)) + __flush_dcache_page(page_mapping(from), from); spin_lock(&minicache_lock); - set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0); + set_pte_ext(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(page_to_pfn(from), minicache_pgprot), 0); flush_tlb_kernel_page(COPYPAGE_MINICACHE); mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto); spin_unlock(&minicache_lock); + + kunmap_atomic(kto, KM_USER1); } /* * XScale optimised clear_user_page */ -void __attribute__((naked)) -xscale_mc_clear_user_page(void *kaddr, unsigned long vaddr) +void +xscale_mc_clear_user_highpage(struct page *page, unsigned long vaddr) { + void *ptr, *kaddr = kmap_atomic(page, KM_USER0); asm volatile( - "mov r1, %0 \n\ + "mov r1, %2 \n\ mov r2, #0 \n\ mov r3, #0 \n\ -1: mov ip, r0 \n\ - strd r2, [r0], #8 \n\ - strd r2, [r0], #8 \n\ - strd r2, [r0], #8 \n\ - strd r2, [r0], #8 \n\ +1: mov ip, %0 \n\ + strd r2, [%0], #8 \n\ + strd r2, [%0], #8 \n\ + strd r2, [%0], #8 \n\ + strd r2, [%0], #8 \n\ mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\ subs r1, r1, #1 \n\ mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\ - bne 1b \n\ - mov pc, lr" - : - : "I" (PAGE_SIZE / 32)); + bne 1b" + : "=r" (ptr) + : "0" (kaddr), "I" (PAGE_SIZE / 32) + : "r1", "r2", "r3", "ip"); + kunmap_atomic(kaddr, KM_USER0); } struct cpu_user_fns xscale_mc_user_fns __initdata = { - .cpu_clear_user_page = xscale_mc_clear_user_page, - .cpu_copy_user_page = xscale_mc_copy_user_page, + .cpu_clear_user_highpage = xscale_mc_clear_user_highpage, + .cpu_copy_user_highpage = xscale_mc_copy_user_highpage, }; diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 22c9530..0455557 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -15,6 +15,7 @@ #include <linux/init.h> #include <linux/kprobes.h> #include <linux/uaccess.h> +#include <linux/page-flags.h> #include <asm/system.h> #include <asm/pgtable.h> @@ -84,13 +85,14 @@ void show_pte(struct mm_struct *mm, unsigned long addr) break; } -#ifndef CONFIG_HIGHMEM /* We must not map this if we have highmem enabled */ + if (PageHighMem(pfn_to_page(pmd_val(*pmd) >> PAGE_SHIFT))) + break; + pte = pte_offset_map(pmd, addr); printk(", *pte=%08lx", pte_val(*pte)); printk(", *ppte=%08lx", pte_val(pte[-PTRS_PER_PTE])); pte_unmap(pte); -#endif } while(0); printk("\n"); diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 82c4b42..34df4d9 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -17,6 +17,7 @@ #include <linux/initrd.h> #include <asm/mach-types.h> +#include <asm/sections.h> #include <asm/setup.h> #include <asm/sizes.h> #include <asm/tlb.h> @@ -64,10 +65,11 @@ static int __init parse_tag_initrd2(const struct tag *tag) __tagtable(ATAG_INITRD2, parse_tag_initrd2); /* - * This is used to pass memory configuration data from paging_init - * to mem_init, and by show_mem() to skip holes in the memory map. + * This keeps memory configuration data used by a couple memory + * initialization functions, as well as show_mem() for the skipping + * of holes in the memory map. It is populated by arm_add_memory(). */ -static struct meminfo meminfo = { 0, }; +struct meminfo meminfo; void show_mem(void) { @@ -128,7 +130,7 @@ find_bootmap_pfn(int node, struct meminfo *mi, unsigned int bootmap_pages) { unsigned int start_pfn, i, bootmap_pfn; - start_pfn = PAGE_ALIGN(__pa(&_end)) >> PAGE_SHIFT; + start_pfn = PAGE_ALIGN(__pa(_end)) >> PAGE_SHIFT; bootmap_pfn = 0; for_each_nodebank(i, mi, node) { @@ -331,13 +333,12 @@ static void __init bootmem_free_node(int node, struct meminfo *mi) free_area_init_node(node, zone_size, start_pfn, zhole_size); } -void __init bootmem_init(struct meminfo *mi) +void __init bootmem_init(void) { + struct meminfo *mi = &meminfo; unsigned long memend_pfn = 0; int node, initrd_node; - memcpy(&meminfo, mi, sizeof(meminfo)); - /* * Locate which node contains the ramdisk image, if any. */ @@ -394,20 +395,22 @@ void __init bootmem_init(struct meminfo *mi) max_pfn = max_low_pfn = memend_pfn - PHYS_PFN_OFFSET; } -static inline void free_area(unsigned long addr, unsigned long end, char *s) +static inline int free_area(unsigned long pfn, unsigned long end, char *s) { - unsigned int size = (end - addr) >> 10; + unsigned int pages = 0, size = (end - pfn) << (PAGE_SHIFT - 10); - for (; addr < end; addr += PAGE_SIZE) { - struct page *page = virt_to_page(addr); + for (; pfn < end; pfn++) { + struct page *page = pfn_to_page(pfn); ClearPageReserved(page); init_page_count(page); - free_page(addr); - totalram_pages++; + __free_page(page); + pages++; } if (size && s) printk(KERN_INFO "Freeing %s memory: %dK\n", s, size); + + return pages; } static inline void @@ -478,13 +481,9 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi) */ void __init mem_init(void) { - unsigned int codepages, datapages, initpages; + unsigned int codesize, datasize, initsize; int i, node; - codepages = &_etext - &_text; - datapages = &_end - &__data_start; - initpages = &__init_end - &__init_begin; - #ifndef CONFIG_DISCONTIGMEM max_mapnr = virt_to_page(high_memory) - mem_map; #endif @@ -501,7 +500,8 @@ void __init mem_init(void) #ifdef CONFIG_SA1111 /* now that our DMA memory is actually so designated, we can free it */ - free_area(PAGE_OFFSET, (unsigned long)swapper_pg_dir, NULL); + totalram_pages += free_area(PHYS_PFN_OFFSET, + __phys_to_pfn(__pa(swapper_pg_dir)), NULL); #endif /* @@ -509,18 +509,21 @@ void __init mem_init(void) * real number of pages we have in this system */ printk(KERN_INFO "Memory:"); - num_physpages = 0; for (i = 0; i < meminfo.nr_banks; i++) { num_physpages += bank_pfn_size(&meminfo.bank[i]); printk(" %ldMB", bank_phys_size(&meminfo.bank[i]) >> 20); } - printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT)); + + codesize = _etext - _text; + datasize = _end - _data; + initsize = __init_end - __init_begin; + printk(KERN_NOTICE "Memory: %luKB available (%dK code, " "%dK data, %dK init)\n", (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), - codepages >> 10, datapages >> 10, initpages >> 10); + codesize >> 10, datasize >> 10, initsize >> 10); if (PAGE_SIZE >= 16384 && num_physpages <= 128) { extern int sysctl_overcommit_memory; @@ -535,11 +538,10 @@ void __init mem_init(void) void free_initmem(void) { - if (!machine_is_integrator() && !machine_is_cintegrator()) { - free_area((unsigned long)(&__init_begin), - (unsigned long)(&__init_end), - "init"); - } + if (!machine_is_integrator() && !machine_is_cintegrator()) + totalram_pages += free_area(__phys_to_pfn(__pa(__init_begin)), + __phys_to_pfn(__pa(__init_end)), + "init"); } #ifdef CONFIG_BLK_DEV_INITRD @@ -549,7 +551,9 @@ static int keep_initrd; void free_initrd_mem(unsigned long start, unsigned long end) { if (!keep_initrd) - free_area(start, end, "initrd"); + totalram_pages += free_area(__phys_to_pfn(__pa(start)), + __phys_to_pfn(__pa(end)), + "initrd"); } static int __init keepinitrd_setup(char *__unused) diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index 5d9f539..95bbe11 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h @@ -32,7 +32,5 @@ struct meminfo; struct pglist_data; void __init create_mapping(struct map_desc *md); -void __init bootmem_init(struct meminfo *mi); +void __init bootmem_init(void); void reserve_node_zero(struct pglist_data *pgdat); - -extern void _text, _stext, _etext, __data_start, _end, __init_begin, __init_end; diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 7f36c82..9b36c5c 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -17,6 +17,7 @@ #include <asm/cputype.h> #include <asm/mach-types.h> +#include <asm/sections.h> #include <asm/setup.h> #include <asm/sizes.h> #include <asm/tlb.h> @@ -646,61 +647,79 @@ static void __init early_vmalloc(char **arg) "vmalloc area too small, limiting to %luMB\n", vmalloc_reserve >> 20); } + + if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { + vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); + printk(KERN_WARNING + "vmalloc area is too big, limiting to %luMB\n", + vmalloc_reserve >> 20); + } } __early_param("vmalloc=", early_vmalloc); #define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve) -static int __init check_membank_valid(struct membank *mb) +static void __init sanity_check_meminfo(void) { - /* - * Check whether this memory region has non-zero size or - * invalid node number. - */ - if (mb->size == 0 || mb->node >= MAX_NUMNODES) - return 0; - - /* - * Check whether this memory region would entirely overlap - * the vmalloc area. - */ - if (phys_to_virt(mb->start) >= VMALLOC_MIN) { - printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " - "(vmalloc region overlap).\n", - mb->start, mb->start + mb->size - 1); - return 0; - } - - /* - * Check whether this memory region would partially overlap - * the vmalloc area. - */ - if (phys_to_virt(mb->start + mb->size) < phys_to_virt(mb->start) || - phys_to_virt(mb->start + mb->size) > VMALLOC_MIN) { - unsigned long newsize = VMALLOC_MIN - phys_to_virt(mb->start); - - printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx " - "to -%.8lx (vmalloc region overlap).\n", - mb->start, mb->start + mb->size - 1, - mb->start + newsize - 1); - mb->size = newsize; - } + int i, j; - return 1; -} + for (i = 0, j = 0; i < meminfo.nr_banks; i++) { + struct membank *bank = &meminfo.bank[j]; + *bank = meminfo.bank[i]; -static void __init sanity_check_meminfo(struct meminfo *mi) -{ - int i, j; +#ifdef CONFIG_HIGHMEM + /* + * Split those memory banks which are partially overlapping + * the vmalloc area greatly simplifying things later. + */ + if (__va(bank->start) < VMALLOC_MIN && + bank->size > VMALLOC_MIN - __va(bank->start)) { + if (meminfo.nr_banks >= NR_BANKS) { + printk(KERN_CRIT "NR_BANKS too low, " + "ignoring high memory\n"); + } else { + memmove(bank + 1, bank, + (meminfo.nr_banks - i) * sizeof(*bank)); + meminfo.nr_banks++; + i++; + bank[1].size -= VMALLOC_MIN - __va(bank->start); + bank[1].start = __pa(VMALLOC_MIN - 1) + 1; + j++; + } + bank->size = VMALLOC_MIN - __va(bank->start); + } +#else + /* + * Check whether this memory bank would entirely overlap + * the vmalloc area. + */ + if (__va(bank->start) >= VMALLOC_MIN) { + printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " + "(vmalloc region overlap).\n", + bank->start, bank->start + bank->size - 1); + continue; + } - for (i = 0, j = 0; i < mi->nr_banks; i++) { - if (check_membank_valid(&mi->bank[i])) - mi->bank[j++] = mi->bank[i]; + /* + * Check whether this memory bank would partially overlap + * the vmalloc area. + */ + if (__va(bank->start + bank->size) > VMALLOC_MIN || + __va(bank->start + bank->size) < __va(bank->start)) { + unsigned long newsize = VMALLOC_MIN - __va(bank->start); + printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx " + "to -%.8lx (vmalloc region overlap).\n", + bank->start, bank->start + bank->size - 1, + bank->start + newsize - 1); + bank->size = newsize; + } +#endif + j++; } - mi->nr_banks = j; + meminfo.nr_banks = j; } -static inline void prepare_page_table(struct meminfo *mi) +static inline void prepare_page_table(void) { unsigned long addr; @@ -712,7 +731,7 @@ static inline void prepare_page_table(struct meminfo *mi) #ifdef CONFIG_XIP_KERNEL /* The XIP kernel is mapped in the module area -- skip over it */ - addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK; + addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK; #endif for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) pmd_clear(pmd_off_k(addr)); @@ -721,7 +740,7 @@ static inline void prepare_page_table(struct meminfo *mi) * Clear out all the kernel space mappings, except for the first * memory bank, up to the end of the vmalloc region. */ - for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size); + for (addr = __phys_to_virt(bank_phys_end(&meminfo.bank[0])); addr < VMALLOC_END; addr += PGDIR_SIZE) pmd_clear(pmd_off_k(addr)); } @@ -738,10 +757,10 @@ void __init reserve_node_zero(pg_data_t *pgdat) * Note that this can only be in node 0. */ #ifdef CONFIG_XIP_KERNEL - reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start, + reserve_bootmem_node(pgdat, __pa(_data), _end - _data, BOOTMEM_DEFAULT); #else - reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext, + reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext, BOOTMEM_DEFAULT); #endif @@ -808,7 +827,6 @@ static void __init devicemaps_init(struct machine_desc *mdesc) * Allocate the vector page early. */ vectors = alloc_bootmem_low_pages(PAGE_SIZE); - BUG_ON(!vectors); for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) pmd_clear(pmd_off_k(addr)); @@ -820,7 +838,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc) #ifdef CONFIG_XIP_KERNEL map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); map.virtual = MODULES_VADDR; - map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; + map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; map.type = MT_ROM; create_mapping(&map); #endif @@ -880,23 +898,23 @@ static void __init devicemaps_init(struct machine_desc *mdesc) * paging_init() sets up the page tables, initialises the zone memory * maps, and sets up the zero page, bad page and bad page tables. */ -void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc) +void __init paging_init(struct machine_desc *mdesc) { void *zero_page; build_mem_type_table(); - sanity_check_meminfo(mi); - prepare_page_table(mi); - bootmem_init(mi); + sanity_check_meminfo(); + prepare_page_table(); + bootmem_init(); devicemaps_init(mdesc); top_pmd = pmd_off_k(0xffff0000); /* - * allocate the zero page. Note that we count on this going ok. + * allocate the zero page. Note that this always succeeds and + * returns a zeroed result. */ zero_page = alloc_bootmem_low_pages(PAGE_SIZE); - memzero(zero_page, PAGE_SIZE); empty_zero_page = virt_to_page(zero_page); flush_dcache_page(empty_zero_page); } diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 07b62b2..ad7bacc 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -10,6 +10,7 @@ #include <linux/io.h> #include <asm/cacheflush.h> +#include <asm/sections.h> #include <asm/page.h> #include <asm/mach/arch.h> @@ -25,10 +26,10 @@ void __init reserve_node_zero(pg_data_t *pgdat) * Note that this can only be in node 0. */ #ifdef CONFIG_XIP_KERNEL - reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start, + reserve_bootmem_node(pgdat, __pa(_data), _end - _data, BOOTMEM_DEFAULT); #else - reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext, + reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext, BOOTMEM_DEFAULT); #endif @@ -41,27 +42,13 @@ void __init reserve_node_zero(pg_data_t *pgdat) BOOTMEM_DEFAULT); } -static void __init sanity_check_meminfo(struct meminfo *mi) -{ - int i, j; - - for (i = 0, j = 0; i < mi->nr_banks; i++) { - struct membank *mb = &mi->bank[i]; - - if (mb->size != 0 && mb->node < MAX_NUMNODES) - mi->bank[j++] = mi->bank[i]; - } - mi->nr_banks = j; -} - /* * paging_init() sets up the page tables, initialises the zone memory * maps, and sets up the zero page, bad page and bad page tables. */ -void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc) +void __init paging_init(struct machine_desc *mdesc) { - sanity_check_meminfo(mi); - bootmem_init(mi); + bootmem_init(); } /* diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index e0f19ab..2690146 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -31,7 +31,7 @@ pgd_t *get_pgd_slow(struct mm_struct *mm) if (!new_pgd) goto no_pgd; - memzero(new_pgd, FIRST_KERNEL_PGD_NR * sizeof(pgd_t)); + memset(new_pgd, 0, FIRST_KERNEL_PGD_NR * sizeof(pgd_t)); /* * Copy over the kernel and IO PGD entries diff --git a/arch/arm/mm/proc-syms.c b/arch/arm/mm/proc-syms.c index 2b5ba39..4ad3bf2 100644 --- a/arch/arm/mm/proc-syms.c +++ b/arch/arm/mm/proc-syms.c @@ -33,8 +33,8 @@ EXPORT_SYMBOL(cpu_cache); #ifdef CONFIG_MMU #ifndef MULTI_USER -EXPORT_SYMBOL(__cpu_clear_user_page); -EXPORT_SYMBOL(__cpu_copy_user_page); +EXPORT_SYMBOL(__cpu_clear_user_highpage); +EXPORT_SYMBOL(__cpu_copy_user_highpage); #else EXPORT_SYMBOL(cpu_user); #endif diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 294943b..f0cc599 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -71,6 +71,8 @@ ENTRY(cpu_v6_reset) * IRQs are already disabled. */ ENTRY(cpu_v6_do_idle) + mov r1, #0 + mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt mov pc, lr diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 4d3c0a7..d1ebec4 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -20,9 +20,17 @@ #define TTB_C (1 << 0) #define TTB_S (1 << 1) +#define TTB_RGN_NC (0 << 3) +#define TTB_RGN_OC_WBWA (1 << 3) #define TTB_RGN_OC_WT (2 << 3) #define TTB_RGN_OC_WB (3 << 3) +#ifndef CONFIG_SMP +#define TTB_FLAGS TTB_C|TTB_RGN_OC_WB @ mark PTWs cacheable, outer WB +#else +#define TTB_FLAGS TTB_C|TTB_S|TTB_RGN_OC_WBWA @ mark PTWs cacheable and shared, outer WBWA +#endif + ENTRY(cpu_v7_proc_init) mov pc, lr ENDPROC(cpu_v7_proc_init) @@ -55,6 +63,7 @@ ENDPROC(cpu_v7_reset) * IRQs are already disabled. */ ENTRY(cpu_v7_do_idle) + dsb @ WFI may enter a low-power mode wfi mov pc, lr ENDPROC(cpu_v7_do_idle) @@ -85,7 +94,7 @@ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id - orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB + orr r0, r0, #TTB_FLAGS mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID isb 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 @@ -162,6 +171,11 @@ cpu_v7_name: * - cache type register is implemented */ __v7_setup: +#ifdef CONFIG_SMP + mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode + orr r0, r0, #(0x1 << 6) + mcr p15, 0, r0, c1, c0, 1 +#endif adr r12, __v7_setup_stack @ the local stack stmia r12, {r0-r5, r7, r9, r11, lr} bl v7_flush_dcache_all @@ -174,8 +188,7 @@ __v7_setup: #ifdef CONFIG_MMU mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs mcr p15, 0, r10, c2, c0, 2 @ TTB control register - orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB - mcr p15, 0, r4, c2, c0, 0 @ load TTB0 + orr r4, r4, #TTB_FLAGS mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 8f6cf56..33515c2 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -481,3 +481,28 @@ __xsc3_proc_info: .long xsc3_mc_user_fns .long xsc3_cache_fns .size __xsc3_proc_info, . - __xsc3_proc_info + +/* Note: PXA935 changed its implementor ID from Intel to Marvell */ + + .type __xsc3_pxa935_proc_info,#object +__xsc3_pxa935_proc_info: + .long 0x56056000 + .long 0xffffe000 + .long PMD_TYPE_SECT | \ + PMD_SECT_BUFFERABLE | \ + PMD_SECT_CACHEABLE | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + .long PMD_TYPE_SECT | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + b __xsc3_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP + .long cpu_xsc3_name + .long xsc3_processor_functions + .long v4wbi_tlb_fns + .long xsc3_mc_user_fns + .long xsc3_cache_fns + .size __xsc3_pxa935_proc_info, . - __xsc3_pxa935_proc_info diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index b2a7e3f..9cc2b16 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -6,18 +6,27 @@ choice prompt "MXC/iMX Base Type" default ARCH_MX3 +config ARCH_MX1 + bool "MX1-based" + select CPU_ARM920T + help + This enables support for systems based on the Freescale i.MX1 family + config ARCH_MX2 bool "MX2-based" + select CPU_ARM926T help This enables support for systems based on the Freescale i.MX2 family config ARCH_MX3 bool "MX3-based" + select CPU_V6 help This enables support for systems based on the Freescale i.MX3 family endchoice +source "arch/arm/mach-mx1/Kconfig" source "arch/arm/mach-mx2/Kconfig" source "arch/arm/mach-mx3/Kconfig" diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 067556f..db74a92 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -5,4 +5,5 @@ # Common support obj-y := irq.o clock.o gpio.o time.o devices.o +obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c index b296f19..2905ec7 100644 --- a/arch/arm/plat-mxc/dma-mx1-mx2.c +++ b/arch/arm/plat-mxc/dma-mx1-mx2.c @@ -34,7 +34,6 @@ #include <asm/system.h> #include <asm/irq.h> #include <mach/hardware.h> -#include <asm/dma.h> #include <mach/dma-mx1-mx2.h> #define DMA_DCR 0x00 /* Control Register */ @@ -114,7 +113,7 @@ struct imx_dma_channel { void (*err_handler) (int, void *, int errcode); void (*prog_handler) (int, void *, struct scatterlist *); void *data; - dmamode_t dma_mode; + unsigned int dma_mode; struct scatterlist *sg; unsigned int resbytes; int dma_num; @@ -193,7 +192,7 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg) int imx_dma_setup_single(int channel, dma_addr_t dma_address, unsigned int dma_length, unsigned int dev_addr, - dmamode_t dmamode) + unsigned int dmamode) { struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; @@ -288,7 +287,7 @@ int imx_dma_setup_sg(int channel, struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, unsigned int dev_addr, - dmamode_t dmamode) + unsigned int dmamode) { struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; @@ -512,6 +511,7 @@ void imx_dma_disable(int channel) } EXPORT_SYMBOL(imx_dma_disable); +#ifdef CONFIG_ARCH_MX2 static void imx_dma_watchdog(unsigned long chno) { struct imx_dma_channel *imxdma = &imx_dma_channels[chno]; @@ -523,6 +523,7 @@ static void imx_dma_watchdog(unsigned long chno) if (imxdma->err_handler) imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT); } +#endif static irqreturn_t dma_err_handler(int irq, void *dev_id) { @@ -675,7 +676,7 @@ int imx_dma_request(int channel, const char *name) { struct imx_dma_channel *imxdma = &imx_dma_channels[channel]; unsigned long flags; - int ret; + int ret = 0; /* basic sanity checks */ if (!name) @@ -697,6 +698,7 @@ int imx_dma_request(int channel, const char *name) ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA", NULL); if (ret) { + local_irq_restore(flags); printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n", MXC_INT_DMACH0 + channel, channel); return ret; @@ -713,7 +715,7 @@ int imx_dma_request(int channel, const char *name) imxdma->sg = NULL; local_irq_restore(flags); - return 0; + return ret; } EXPORT_SYMBOL(imx_dma_request); diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index de5c474..ccbd94a 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -115,8 +115,8 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) } } -#ifdef CONFIG_ARCH_MX3 -/* MX3 has one interrupt *per* gpio port */ +#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1) +/* MX1 and MX3 has one interrupt *per* gpio port */ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) { u32 irq_stat; @@ -237,7 +237,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) /* its a serious configuration bug when it fails */ BUG_ON( gpiochip_add(&port[i].chip) < 0 ); -#ifdef CONFIG_ARCH_MX3 +#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1) /* setup one handler for each entry */ set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); set_irq_data(port[i].irq, &port[i]); diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h index 61e66da..8f34a05 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h @@ -15,7 +15,7 @@ #define __ASM_ARCH_MXC_BOARD_MX27ADS_H__ /* external interrupt multiplexer */ -#define MXC_EXP_IO_BASE (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES) +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) #define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES) #define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE @@ -28,11 +28,6 @@ /* * MXC UART EVB board level configurations */ - -#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x20000) -#define MXC_LL_EXTUART_VADDR (CS4_BASE_ADDR_VIRT + 0x20000) -#define MXC_LL_EXTUART_16BIT_BUS - #define MXC_LL_UART_PADDR UART1_BASE_ADDR #define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h index 745b488..451d510 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h @@ -90,7 +90,7 @@ #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) -#define MXC_EXP_IO_BASE (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES) +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) #define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0) diff --git a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h new file mode 100644 index 0000000..2b6b316 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h @@ -0,0 +1,19 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__ +#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__ + +/* mandatory for CONFIG_LL_DEBUG */ + +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) + +#endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index b9907be..602768b 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -28,6 +28,9 @@ #ifdef CONFIG_MACH_PCM038 #include <mach/board-pcm038.h> #endif +#ifdef CONFIG_MACH_MX31_3DS +#include <mach/board-mx31pdk.h> +#endif .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h index e85fd94..b3876cc 100644 --- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h @@ -22,13 +22,15 @@ * MA 02110-1301, USA. */ -#include <asm/dma.h> - #ifndef __ASM_ARCH_MXC_DMA_H #define __ASM_ARCH_MXC_DMA_H #define IMX_DMA_CHANNELS 16 +#define DMA_MODE_READ 0 +#define DMA_MODE_WRITE 1 +#define DMA_MODE_MASK 1 + #define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR) #define IMX_DMA_MEMSIZE_32 (0 << 4) @@ -54,12 +56,12 @@ imx_dma_config_burstlen(int channel, unsigned int burstlen); int imx_dma_setup_single(int channel, dma_addr_t dma_address, unsigned int dma_length, unsigned int dev_addr, - dmamode_t dmamode); + unsigned int dmamode); int imx_dma_setup_sg(int channel, struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, - unsigned int dev_addr, dmamode_t dmamode); + unsigned int dev_addr, unsigned int dmamode); int imx_dma_setup_handlers(int channel, diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h deleted file mode 100644 index c822d56..0000000 --- a/arch/arm/plat-mxc/include/mach/dma.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MXC_DMA_H__ -#define __ASM_ARCH_MXC_DMA_H__ - -#endif diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index 1163202..5f01d60 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S @@ -9,6 +9,8 @@ * published by the Free Software Foundation. */ +#include <mach/hardware.h> + #define AVIC_NIMASK 0x04 @ this macro disables fast irq (not implemented) diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index 65eedc0..ea509f1 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -27,8 +27,8 @@ #define gpio_set_value __gpio_set_value #define gpio_cansleep __gpio_cansleep -#define gpio_to_irq(gpio) (MXC_MAX_INT_LINES + (gpio)) -#define irq_to_gpio(irq) ((irq) - MXC_MAX_INT_LINES) +#define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio)) +#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START) struct mxc_gpio_port { void __iomem *base; diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 3caadee..a612d8b 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -32,6 +32,10 @@ # endif #endif +#ifdef CONFIG_ARCH_MX1 +# include <mach/mx1.h> +#endif + #include <mach/mxc.h> #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h index 5d4cb11..b4f2de7 100644 --- a/arch/arm/plat-mxc/include/mach/io.h +++ b/arch/arm/plat-mxc/include/mach/io.h @@ -25,8 +25,8 @@ __mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) /* Access all peripherals below 0x80000000 as nonshared device * but leave l2cc alone. */ - if ((phys_addr < 0x80000000) && ((phys_addr < L2CC_BASE_ADDR) || - (phys_addr >= L2CC_BASE_ADDR + L2CC_SIZE))) + if ((phys_addr < 0x80000000) && ((phys_addr < 0x30000000) || + (phys_addr >= 0x30000000 + SZ_1M))) mtype = MT_DEVICE_NONSHARED; } @@ -35,8 +35,8 @@ __mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) #endif /* io address mapping macro */ -#define __io(a) ((void __iomem *)(a)) +#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) +#define __mem_pci(a) (a) #endif diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h index 3d09bfd..95a383b 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h @@ -21,12 +21,6 @@ #include <linux/io.h> -#define MXC_GPIO_ALLOC_MODE_NORMAL 0 -#define MXC_GPIO_ALLOC_MODE_NO_ALLOC 1 -#define MXC_GPIO_ALLOC_MODE_TRY_ALLOC 2 -#define MXC_GPIO_ALLOC_MODE_ALLOC_ONLY 4 -#define MXC_GPIO_ALLOC_MODE_RELEASE 8 - /* * GPIO Module and I/O Multiplexer * x = 0..3 for reg_A, reg_B, reg_C, reg_D @@ -103,7 +97,8 @@ extern void mxc_gpio_mode(int gpio_mode); extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, - int alloc_mode, const char *label); + const char *label); +extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); /*-------------------------------------------------------------------------*/ @@ -113,9 +108,9 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, * missing on some (many) pins */ #ifdef CONFIG_ARCH_MX1 -#define PA0_AIN_SPI2_CLK (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0) +#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_OUT | 0) #define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) -#define PA1_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1) +#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_IN | 1) #define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) #define PA2_PF_PWM0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2) #define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) @@ -133,7 +128,7 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, #define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15) #define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16) #define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) -#define PA17_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17) +#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_OUT | 17) #define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) #define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) #define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) @@ -201,27 +196,27 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, #define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) #define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) #define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) -#define PC24_BIN_UART3_RI (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24) -#define PC25_BIN_UART3_DSR (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25) -#define PC26_AOUT_UART3_DTR (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26) -#define PC27_BIN_UART3_DCD (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27) -#define PC28_BIN_UART3_CTS (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28) -#define PC29_AOUT_UART3_RTS (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29) -#define PC30_BIN_UART3_TX (GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30) -#define PC31_AOUT_UART3_RX (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) +#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24) +#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25) +#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_IN | 26) +#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27) +#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28) +#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_IN | 29) +#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30) +#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_IN | 31) #define PD6_PF_LSCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6) #define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) -#define PD7_AF_UART2_DTR (GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7) -#define PD7_AIN_SPI2_SCLK (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7) +#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_IN | GPIO_AF | 7) +#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7) #define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) #define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8) -#define PD8_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8) +#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8) #define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) #define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9) -#define PD9_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9) +#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_IN | 9) #define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10) #define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10) -#define PD10_AIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10) +#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_OUT | 10) #define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11) #define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12) #define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13) @@ -243,7 +238,7 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, #define PD29_PF_LD14 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29) #define PD30_PF_LD15 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30) #define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) -#define PD31_BIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31) +#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31) #endif #ifdef CONFIG_ARCH_MX2 @@ -279,6 +274,12 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, #define PA29_PF_VSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29) #define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30) #define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31) +#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) +#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) +#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) +#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) +#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) +#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) #define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10) #define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10) #define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11) @@ -315,6 +316,13 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, #define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 31) #define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_IN | GPIO_PF | 5) #define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_IN | GPIO_PF | 6) +#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) +#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) +#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) +#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) +#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) +#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) +#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) #define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 16) #define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 17) #define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 18) @@ -365,6 +373,9 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, #define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30) #define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31) #define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) +#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) +#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) +#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) #define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) #define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) #define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) @@ -379,18 +390,27 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, #define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) #define PE16_AF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 16) #define PE16_PF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 16) +#define PE18_PF_SDHC1_D0 (GPIO_PORTE | GPIO_PF | 18) #define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18) +#define PE19_PF_SDHC1_D1 (GPIO_PORTE | GPIO_PF | 19) +#define PE20_PF_SDHC1_D2 (GPIO_PORTE | GPIO_PF | 20) +#define PE21_PF_SDHC1_D3 (GPIO_PORTE | GPIO_PF | 21) #define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21) +#define PE22_PF_SDHC1_CMD (GPIO_PORTE | GPIO_PF | 22) #define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22) +#define PE22_PF_SDHC1_CLK (GPIO_PORTE | GPIO_PF | 23) #define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23) +#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) +#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) #endif /* decode irq number to use with IMR(x), ISR(x) and friends */ -#define IRQ_TO_REG(irq) ((irq - MXC_MAX_INT_LINES) >> 5) +#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5) -#define IRQ_GPIOA(x) (MXC_MAX_INT_LINES + x) +#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x) #define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) #define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) +#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) #endif /* _MXC_GPIO_MX1_MX2_H */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index c9f39c2..c9198c0 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -141,7 +141,7 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, bool); ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) #define IOMUX_TO_IRQ(iomux_pin) \ (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \ - MXC_GPIO_INT_BASE) + MXC_GPIO_IRQ_START) /* * This enumeration is constructed based on the Section @@ -491,6 +491,14 @@ enum iomux_pins { #define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) #define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) #define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) +#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) +#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) +#define MX31_PIN_PC_BVD1__RXD5 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2) #define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC) @@ -509,6 +517,15 @@ enum iomux_pins { #define MX31_PIN_CSPI3_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC) +#define MX31_PIN_BATT_LINE__OWIRE IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CS4__CS4 IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA3__SD1_DATA3 IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA2__SD1_DATA2 IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA1__SD1_DATA1 IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) + /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 * cspi1_ss1*/ diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index b55bba3..e06d3cb 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -11,7 +11,37 @@ #ifndef __ASM_ARCH_MXC_IRQS_H__ #define __ASM_ARCH_MXC_IRQS_H__ -#include <mach/hardware.h> +/* + * So far all i.MX SoCs have 64 internal interrupts + */ +#define MXC_INTERNAL_IRQS 64 + +#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS + +#if defined CONFIG_ARCH_MX1 +#define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX2 +#define MXC_GPIO_IRQS (32 * 6) +#elif defined CONFIG_ARCH_MX3 +#define MXC_GPIO_IRQS (32 * 3) +#endif + +/* + * The next 16 interrupts are for board specific purposes. Since + * the kernel can only run on one machine at a time, we can re-use + * these. If you need more, increase MXC_BOARD_IRQS, but keep it + * within sensible limits. + */ +#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS) +#define MXC_BOARD_IRQS 16 + +#define NR_IRQS (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) + extern void imx_irq_set_priority(unsigned char irq, unsigned char prio); +/* all normal IRQs can be FIQs */ +#define FIQ_START 0 +/* switch betwean IRQ and FIQ */ +extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type); + #endif /* __ASM_ARCH_MXC_IRQS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index d7a8d3e..0b80839 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -11,19 +11,12 @@ #ifndef __ASM_ARCH_MXC_MEMORY_H__ #define __ASM_ARCH_MXC_MEMORY_H__ -#include <mach/hardware.h> - -/* - * Virtual view <-> DMA view memory address translations - * This macro is used to translate the virtual address to an address - * suitable to be passed to set_dma_addr() - */ -#define __virt_to_bus(a) __virt_to_phys(a) - -/* - * Used to convert an address for DMA operations to an address that the - * kernel can use. - */ -#define __bus_to_virt(a) __phys_to_virt(a) +#if defined CONFIG_ARCH_MX1 +#define PHYS_OFFSET UL(0x08000000) +#elif defined CONFIG_ARCH_MX2 +#define PHYS_OFFSET UL(0xA0000000) +#elif defined CONFIG_ARCH_MX3 +#define PHYS_OFFSET UL(0x80000000) +#endif #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mtd-xip.h b/arch/arm/plat-mxc/include/mach/mtd-xip.h new file mode 100644 index 0000000..1ab1bba --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mtd-xip.h @@ -0,0 +1,34 @@ +/* + * MTD primitives for XIP support. Architecture specific functions + * + * Do not include this file directly. It's included from linux/mtd/xip.h + * + * Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com>, Teltonika, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <mach/mxc_timer.h> + +#ifndef __ARCH_IMX_MTD_XIP_H__ +#define __ARCH_IMX_MTD_XIP_H__ + +#ifdef CONFIG_ARCH_MX1 +/* AITC registers */ +#define AITC_BASE IO_ADDRESS(AVIC_BASE_ADDR) +#define NIPNDH (AITC_BASE + 0x58) +#define NIPNDL (AITC_BASE + 0x5C) +#define INTENABLEH (AITC_BASE + 0x10) +#define INTENABLEL (AITC_BASE + 0x14) +/* MTD macros */ +#define xip_irqpending() ((__raw_readl(INTENABLEH) & __raw_readl(NIPNDH)) \ + || (__raw_readl(INTENABLEL) & __raw_readl(NIPNDL))) +#define xip_currtime() (__raw_readl(TIMER_BASE + MXC_TCN)) +#define xip_elapsed_since(x) (signed)((__raw_readl(TIMER_BASE + MXC_TCN) - (x)) / 96) +#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (0)) +#endif /* CONFIG_ARCH_MX1 */ + +#endif /* __ARCH_IMX_MTD_XIP_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h new file mode 100644 index 0000000..b92e023 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -0,0 +1,186 @@ +/* + * Copyright (C) 1997,1998 Russell King + * Copyright (C) 1999 ARM Limited + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_MX1_H__ +#define __ASM_ARCH_MXC_MX1_H__ + +#ifndef __ASM_ARCH_MXC_HARDWARE_H__ +#error "Do not include directly." +#endif + +#include <mach/vmalloc.h> + +/* + * Memory map + */ +#define IMX_IO_PHYS 0x00200000 +#define IMX_IO_SIZE 0x00100000 +#define IMX_IO_BASE VMALLOC_END + +#define IMX_CS0_PHYS 0x10000000 +#define IMX_CS0_SIZE 0x02000000 + +#define IMX_CS1_PHYS 0x12000000 +#define IMX_CS1_SIZE 0x01000000 + +#define IMX_CS2_PHYS 0x13000000 +#define IMX_CS2_SIZE 0x01000000 + +#define IMX_CS3_PHYS 0x14000000 +#define IMX_CS3_SIZE 0x01000000 + +#define IMX_CS4_PHYS 0x15000000 +#define IMX_CS4_SIZE 0x01000000 + +#define IMX_CS5_PHYS 0x16000000 +#define IMX_CS5_SIZE 0x01000000 + +/* + * Register BASEs, based on OFFSETs + */ +#define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS) +#define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS) +#define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS) +#define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS) +#define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS) +#define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS) +#define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS) +#define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS) +#define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS) +#define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS) +#define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS) +#define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS) +#define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS) +#define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS) +#define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS) +#define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS) +#define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS) +#define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS) +#define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS) +#define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS) +#define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS) +#define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS) +#define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS) +#define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS) +#define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS) +#define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS) +#define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS) +#define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS) +#define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS) + +/* macro to get at IO space when running virtually */ +#define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE) + +/* define macros needed for entry-macro.S */ +#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) + +/* fixed interrput numbers */ +#define INT_SOFTINT 0 +#define CSI_INT 6 +#define DSPA_MAC_INT 7 +#define DSPA_INT 8 +#define COMP_INT 9 +#define MSHC_XINT 10 +#define GPIO_INT_PORTA 11 +#define GPIO_INT_PORTB 12 +#define GPIO_INT_PORTC 13 +#define LCDC_INT 14 +#define SIM_INT 15 +#define SIM_DATA_INT 16 +#define RTC_INT 17 +#define RTC_SAMINT 18 +#define UART2_MINT_PFERR 19 +#define UART2_MINT_RTS 20 +#define UART2_MINT_DTR 21 +#define UART2_MINT_UARTC 22 +#define UART2_MINT_TX 23 +#define UART2_MINT_RX 24 +#define UART1_MINT_PFERR 25 +#define UART1_MINT_RTS 26 +#define UART1_MINT_DTR 27 +#define UART1_MINT_UARTC 28 +#define UART1_MINT_TX 29 +#define UART1_MINT_RX 30 +#define VOICE_DAC_INT 31 +#define VOICE_ADC_INT 32 +#define PEN_DATA_INT 33 +#define PWM_INT 34 +#define SDHC_INT 35 +#define I2C_INT 39 +#define CSPI_INT 41 +#define SSI_TX_INT 42 +#define SSI_TX_ERR_INT 43 +#define SSI_RX_INT 44 +#define SSI_RX_ERR_INT 45 +#define TOUCH_INT 46 +#define USBD_INT0 47 +#define USBD_INT1 48 +#define USBD_INT2 49 +#define USBD_INT3 50 +#define USBD_INT4 51 +#define USBD_INT5 52 +#define USBD_INT6 53 +#define BTSYS_INT 55 +#define BTTIM_INT 56 +#define BTWUI_INT 57 +#define TIM2_INT 58 +#define TIM1_INT 59 +#define DMA_ERR 60 +#define DMA_INT 61 +#define GPIO_INT_PORTD 62 +#define WDT_INT 63 + +/* gpio and gpio based interrupt handling */ +#define GPIO_DR 0x1C +#define GPIO_GDIR 0x00 +#define GPIO_PSR 0x24 +#define GPIO_ICR1 0x28 +#define GPIO_ICR2 0x2C +#define GPIO_IMR 0x30 +#define GPIO_ISR 0x34 +#define GPIO_INT_LOW_LEV 0x3 +#define GPIO_INT_HIGH_LEV 0x2 +#define GPIO_INT_RISE_EDGE 0x0 +#define GPIO_INT_FALL_EDGE 0x1 +#define GPIO_INT_NONE 0x4 + +/* DMA */ +#define DMA_REQ_UART3_T 2 +#define DMA_REQ_UART3_R 3 +#define DMA_REQ_SSI2_T 4 +#define DMA_REQ_SSI2_R 5 +#define DMA_REQ_CSI_STAT 6 +#define DMA_REQ_CSI_R 7 +#define DMA_REQ_MSHC 8 +#define DMA_REQ_DSPA_DCT_DOUT 9 +#define DMA_REQ_DSPA_DCT_DIN 10 +#define DMA_REQ_DSPA_MAC 11 +#define DMA_REQ_EXT 12 +#define DMA_REQ_SDHC 13 +#define DMA_REQ_SPI1_R 14 +#define DMA_REQ_SPI1_T 15 +#define DMA_REQ_SSI_T 16 +#define DMA_REQ_SSI_R 17 +#define DMA_REQ_ASP_DAC 18 +#define DMA_REQ_ASP_ADC 19 +#define DMA_REQ_USP_EP(x) (20 + (x)) +#define DMA_REQ_SPI2_R 26 +#define DMA_REQ_SPI2_T 27 +#define DMA_REQ_UART2_T 28 +#define DMA_REQ_UART2_R 29 +#define DMA_REQ_UART1_T 30 +#define DMA_REQ_UART1_R 31 + +/* mandatory for CONFIG_LL_DEBUG */ +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR IO_ADDRESS(UART1_BASE_ADDR) + +#endif /* __ASM_ARCH_MXC_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index a86db64..0313be7 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -72,7 +72,8 @@ /* for mx27*/ #define OTG_BASE_ADDR USBOTG_BASE_ADDR #define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) -#define EMMA_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) +#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000) +#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) #define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) #define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) #define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) @@ -288,16 +289,4 @@ extern int mx27_revision(void); /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ #define ARCH_NR_GPIOS (192 + 16) -/* OS clock tick rate */ -#define CLOCK_TICK_RATE 13300000 - -/* Start of RAM */ -#define PHYS_OFFSET SDRAM_BASE_ADDR - -/* max interrupt lines count */ -#define NR_IRQS 256 - -/* count of internal interrupt sources */ -#define MXC_MAX_INT_LINES 64 - #endif /* __ASM_ARCH_MXC_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 0536f89..de02665 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -15,11 +15,6 @@ #error "Do not include directly." #endif -/*! - * defines the hardware clock tick rate - */ -#define CLOCK_TICK_RATE 16625000 - /* * MX31 memory map: * @@ -244,9 +239,6 @@ #define PCMCIA_IO_ADDRESS(x) \ (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) -/* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */ -#define PHYS_OFFSET CSD0_BASE_ADDR - /* * Interrupt numbers */ @@ -315,23 +307,6 @@ #define MXC_INT_EXT_WDOG 62 #define MXC_INT_EXT_TV 63 -#define MXC_MAX_INT_LINES 64 - -#define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES -#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) -#define MXC_MAX_VIRTUAL_INTS 16 - -#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS) - -/*! - * Number of GPIO port as defined in the IC Spec - */ -#define GPIO_PORT_NUM 3 -/*! - * Number of GPIO pins per port - */ -#define GPIO_NUM_PIN 32 - #define PROD_SIGNATURE 0x1 /* For MX31 */ /* silicon revisions specific to i.MX31 */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_timer.h b/arch/arm/plat-mxc/include/mach/mxc_timer.h index 130aebf..6c19a13 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_timer.h +++ b/arch/arm/plat-mxc/include/mach/mxc_timer.h @@ -26,7 +26,7 @@ #include <linux/clk.h> #include <mach/hardware.h> -#ifdef CONFIG_ARCH_IMX +#ifdef CONFIG_ARCH_MX1 #define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR) #define TIMER_INTERRUPT TIM1_INT @@ -65,7 +65,7 @@ static void gpt_irq_acknowledge(void) { __raw_writel(0, TIMER_BASE + MXC_TSTAT); } -#endif /* CONFIG_ARCH_IMX */ +#endif /* CONFIG_ARCH_MX1 */ #ifdef CONFIG_ARCH_MX2 #define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR) diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 0b0af02..07b4a73 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -20,6 +20,12 @@ #ifndef __ASM_ARCH_MXC_TIMEX_H__ #define __ASM_ARCH_MXC_TIMEX_H__ -#include <mach/hardware.h> /* for CLOCK_TICK_RATE */ +#if defined CONFIG_ARCH_MX1 +#define CLOCK_TICK_RATE 16000000 +#elif defined CONFIG_ARCH_MX2 +#define CLOCK_TICK_RATE 13300000 +#elif defined CONFIG_ARCH_MX3 +#define CLOCK_TICK_RATE 16625000 +#endif #endif /* __ASM_ARCH_MXC_TIMEX_H__ */ diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c index d97387a..df6f183 100644 --- a/arch/arm/plat-mxc/iomux-mx1-mx2.c +++ b/arch/arm/plat-mxc/iomux-mx1-mx2.c @@ -110,12 +110,13 @@ void mxc_gpio_mode(int gpio_mode) EXPORT_SYMBOL(mxc_gpio_mode); int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, - int alloc_mode, const char *label) + const char *label) { const int *p = pin_list; int i; unsigned gpio; unsigned mode; + int ret = -EINVAL; for (i = 0; i < count; i++) { gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); @@ -124,33 +125,33 @@ int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, if (gpio >= (GPIO_PORT_MAX + 1) * 32) goto setup_error; - if (alloc_mode & MXC_GPIO_ALLOC_MODE_RELEASE) - gpio_free(gpio); - else if (!(alloc_mode & MXC_GPIO_ALLOC_MODE_NO_ALLOC)) - if (gpio_request(gpio, label) - && !(alloc_mode & MXC_GPIO_ALLOC_MODE_TRY_ALLOC)) - goto setup_error; + ret = gpio_request(gpio, label); + if (ret) + goto setup_error; - if (!(alloc_mode & (MXC_GPIO_ALLOC_MODE_ALLOC_ONLY | - MXC_GPIO_ALLOC_MODE_RELEASE))) - mxc_gpio_mode(gpio | mode); + mxc_gpio_mode(gpio | mode); p++; } return 0; setup_error: - if (alloc_mode & (MXC_GPIO_ALLOC_MODE_NO_ALLOC | - MXC_GPIO_ALLOC_MODE_TRY_ALLOC)) - return -EINVAL; + mxc_gpio_release_multiple_pins(pin_list, i); + return ret; +} +EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins); - while (p != pin_list) { - p--; - gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); +void mxc_gpio_release_multiple_pins(const int *pin_list, int count) +{ + const int *p = pin_list; + int i; + + for (i = 0; i < count; i++) { + unsigned gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); gpio_free(gpio); + p++; } - return -EINVAL; } -EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins); +EXPORT_SYMBOL(mxc_gpio_release_multiple_pins); diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c index d862c9e..6e7578a 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/irq.c @@ -17,9 +17,12 @@ * MA 02110-1301, USA. */ +#include <linux/module.h> #include <linux/irq.h> #include <linux/io.h> #include <mach/common.h> +#include <asm/mach/irq.h> +#include <mach/hardware.h> #define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR) #define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */ @@ -65,6 +68,28 @@ void imx_irq_set_priority(unsigned char irq, unsigned char prio) EXPORT_SYMBOL(imx_irq_set_priority); #endif +#ifdef CONFIG_FIQ +int mxc_set_irq_fiq(unsigned int irq, unsigned int type) +{ + unsigned int irqt; + + if (irq >= MXC_INTERNAL_IRQS) + return -EINVAL; + + if (irq < MXC_INTERNAL_IRQS / 2) { + irqt = __raw_readl(AVIC_INTTYPEL) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEL); + } else { + irq -= MXC_INTERNAL_IRQS / 2; + irqt = __raw_readl(AVIC_INTTYPEH) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEH); + } + + return 0; +} +EXPORT_SYMBOL(mxc_set_irq_fiq); +#endif /* CONFIG_FIQ */ + /* Disable interrupt number "irq" in the AVIC */ static void mxc_mask_irq(unsigned int irq) { @@ -91,7 +116,6 @@ static struct irq_chip mxc_avic_chip = { void __init mxc_init_irq(void) { int i; - u32 reg; /* put the AVIC into the reset value with * all interrupts disabled @@ -106,7 +130,7 @@ void __init mxc_init_irq(void) /* all IRQ no FIQ */ __raw_writel(0, AVIC_INTTYPEH); __raw_writel(0, AVIC_INTTYPEL); - for (i = 0; i < MXC_MAX_INT_LINES; i++) { + for (i = 0; i < MXC_INTERNAL_IRQS; i++) { set_irq_chip(i, &mxc_avic_chip); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); @@ -119,5 +143,10 @@ void __init mxc_init_irq(void) /* init architectures chained interrupt handler */ mxc_register_gpios(); +#ifdef CONFIG_FIQ + /* Initialize FIQ */ + init_FIQ(); +#endif + printk(KERN_INFO "MXC IRQ initialized\n"); } diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index a94f0c4..46d3b0b 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -14,9 +14,11 @@ config ARCH_OMAP1 config ARCH_OMAP2 bool "TI OMAP2" + select CPU_V6 config ARCH_OMAP3 bool "TI OMAP3" + select CPU_V7 endchoice diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c index e31154b..f668483 100644 --- a/arch/arm/plat-omap/debug-devices.c +++ b/arch/arm/plat-omap/debug-devices.c @@ -69,15 +69,15 @@ int __init debug_card_init(u32 addr, unsigned gpio) smc91x_resources[0].start = addr + 0x300; smc91x_resources[0].end = addr + 0x30f; - smc91x_resources[1].start = OMAP_GPIO_IRQ(gpio); - smc91x_resources[1].end = OMAP_GPIO_IRQ(gpio); + smc91x_resources[1].start = gpio_to_irq(gpio); + smc91x_resources[1].end = gpio_to_irq(gpio); - status = omap_request_gpio(gpio); + status = gpio_request(gpio, "SMC91x irq"); if (status < 0) { printk(KERN_ERR "GPIO%d unavailable for smc91x IRQ\n", gpio); return status; } - omap_set_gpio_direction(gpio, 1); + gpio_direction_input(gpio); led_resources[0].start = addr; led_resources[0].end = addr + SZ_4K - 1; diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c index 2f4c0ca..be4eefd 100644 --- a/arch/arm/plat-omap/debug-leds.c +++ b/arch/arm/plat-omap/debug-leds.c @@ -83,8 +83,8 @@ static void h2p2_dbg_leds_event(led_event_t evt) /* all leds off during suspend or shutdown */ if (!(machine_is_omap_perseus2() || machine_is_omap_h4())) { - omap_set_gpio_dataout(GPIO_TIMER, 0); - omap_set_gpio_dataout(GPIO_IDLE, 0); + gpio_set_value(GPIO_TIMER, 0); + gpio_set_value(GPIO_IDLE, 0); } __raw_writew(~0, &fpga->leds); @@ -107,7 +107,7 @@ static void h2p2_dbg_leds_event(led_event_t evt) if (machine_is_omap_perseus2() || machine_is_omap_h4()) hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER; else { - omap_set_gpio_dataout(GPIO_TIMER, + gpio_set_value(GPIO_TIMER, led_state & LED_TIMER_ON); goto done; } @@ -121,7 +121,7 @@ static void h2p2_dbg_leds_event(led_event_t evt) if (machine_is_omap_perseus2() || machine_is_omap_h4()) hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE; else { - omap_set_gpio_dataout(GPIO_IDLE, 1); + gpio_set_value(GPIO_IDLE, 1); goto done; } @@ -131,7 +131,7 @@ static void h2p2_dbg_leds_event(led_event_t evt) if (machine_is_omap_perseus2() || machine_is_omap_h4()) hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE; else { - omap_set_gpio_dataout(GPIO_IDLE, 0); + gpio_set_value(GPIO_IDLE, 0); goto done; } diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 0cb2b22..ac15c23 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -192,202 +192,48 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, /*-------------------------------------------------------------------------*/ -#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) -#define OMAP_MMC1_BASE 0x4809c000 -#define OMAP_MMC1_END (OMAP_MMC1_BASE + 0x1fc) -#define OMAP_MMC1_INT INT_24XX_MMC_IRQ +#define OMAP_MMC_NR_RES 2 -#define OMAP_MMC2_BASE 0x480b4000 -#define OMAP_MMC2_END (OMAP_MMC2_BASE + 0x1fc) -#define OMAP_MMC2_INT INT_24XX_MMC2_IRQ - -#else - -#define OMAP_MMC1_BASE 0xfffb7800 -#define OMAP_MMC1_END (OMAP_MMC1_BASE + 0x7f) -#define OMAP_MMC1_INT INT_MMC - -#define OMAP_MMC2_BASE 0xfffb7c00 /* omap16xx only */ -#define OMAP_MMC2_END (OMAP_MMC2_BASE + 0x7f) -#define OMAP_MMC2_INT INT_1610_MMC2 - -#endif - -static struct omap_mmc_platform_data mmc1_data; - -static u64 mmc1_dmamask = 0xffffffff; - -static struct resource mmc1_resources[] = { - { - .start = OMAP_MMC1_BASE, - .end = OMAP_MMC1_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP_MMC1_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mmc_omap_device1 = { - .name = "mmci-omap", - .id = 1, - .dev = { - .dma_mask = &mmc1_dmamask, - .platform_data = &mmc1_data, - }, - .num_resources = ARRAY_SIZE(mmc1_resources), - .resource = mmc1_resources, -}; - -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2430) || \ - defined(CONFIG_ARCH_OMAP34XX) - -static struct omap_mmc_platform_data mmc2_data; - -static u64 mmc2_dmamask = 0xffffffff; - -static struct resource mmc2_resources[] = { - { - .start = OMAP_MMC2_BASE, - .end = OMAP_MMC2_END, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP_MMC2_INT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device mmc_omap_device2 = { - .name = "mmci-omap", - .id = 2, - .dev = { - .dma_mask = &mmc2_dmamask, - .platform_data = &mmc2_data, - }, - .num_resources = ARRAY_SIZE(mmc2_resources), - .resource = mmc2_resources, -}; -#endif - -static inline void omap_init_mmc_conf(const struct omap_mmc_config *mmc_conf) -{ - if (cpu_is_omap2430() || cpu_is_omap34xx()) - return; - - if (mmc_conf->mmc[0].enabled) { - if (cpu_is_omap24xx()) { - omap_cfg_reg(H18_24XX_MMC_CMD); - omap_cfg_reg(H15_24XX_MMC_CLKI); - omap_cfg_reg(G19_24XX_MMC_CLKO); - omap_cfg_reg(F20_24XX_MMC_DAT0); - omap_cfg_reg(F19_24XX_MMC_DAT_DIR0); - omap_cfg_reg(G18_24XX_MMC_CMD_DIR); - } else { - omap_cfg_reg(MMC_CMD); - omap_cfg_reg(MMC_CLK); - omap_cfg_reg(MMC_DAT0); - if (cpu_is_omap1710()) { - omap_cfg_reg(M15_1710_MMC_CLKI); - omap_cfg_reg(P19_1710_MMC_CMDDIR); - omap_cfg_reg(P20_1710_MMC_DATDIR0); - } - } - if (mmc_conf->mmc[0].wire4) { - if (cpu_is_omap24xx()) { - omap_cfg_reg(H14_24XX_MMC_DAT1); - omap_cfg_reg(E19_24XX_MMC_DAT2); - omap_cfg_reg(D19_24XX_MMC_DAT3); - omap_cfg_reg(E20_24XX_MMC_DAT_DIR1); - omap_cfg_reg(F18_24XX_MMC_DAT_DIR2); - omap_cfg_reg(E18_24XX_MMC_DAT_DIR3); - } else { - omap_cfg_reg(MMC_DAT1); - /* NOTE: DAT2 can be on W10 (here) or M15 */ - if (!mmc_conf->mmc[0].nomux) - omap_cfg_reg(MMC_DAT2); - omap_cfg_reg(MMC_DAT3); - } - } - } - -#ifdef CONFIG_ARCH_OMAP16XX - /* block 2 is on newer chips, and has many pinout options */ - if (mmc_conf->mmc[1].enabled) { - if (!mmc_conf->mmc[1].nomux) { - omap_cfg_reg(Y8_1610_MMC2_CMD); - omap_cfg_reg(Y10_1610_MMC2_CLK); - omap_cfg_reg(R18_1610_MMC2_CLKIN); - omap_cfg_reg(W8_1610_MMC2_DAT0); - if (mmc_conf->mmc[1].wire4) { - omap_cfg_reg(V8_1610_MMC2_DAT1); - omap_cfg_reg(W15_1610_MMC2_DAT2); - omap_cfg_reg(R10_1610_MMC2_DAT3); - } - - /* These are needed for the level shifter */ - omap_cfg_reg(V9_1610_MMC2_CMDDIR); - omap_cfg_reg(V5_1610_MMC2_DATDIR0); - omap_cfg_reg(W19_1610_MMC2_DATDIR1); - } - - /* Feedback clock must be set on OMAP-1710 MMC2 */ - if (cpu_is_omap1710()) - omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24), - MOD_CONF_CTRL_1); - } -#endif -} - -static void __init omap_init_mmc(void) +/* + * Register MMC devices. Called from mach-omap1 and mach-omap2 device init. + */ +int __init omap_mmc_add(int id, unsigned long base, unsigned long size, + unsigned int irq, struct omap_mmc_platform_data *data) { - const struct omap_mmc_config *mmc_conf; - - /* NOTE: assumes MMC was never (wrongly) enabled */ - mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config); - if (!mmc_conf) - return; - - omap_init_mmc_conf(mmc_conf); - - if (mmc_conf->mmc[0].enabled) { - mmc1_data.conf = mmc_conf->mmc[0]; - (void) platform_device_register(&mmc_omap_device1); - } - -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2430) || \ - defined(CONFIG_ARCH_OMAP34XX) - if (mmc_conf->mmc[1].enabled) { - mmc2_data.conf = mmc_conf->mmc[1]; - (void) platform_device_register(&mmc_omap_device2); - } -#endif -} + struct platform_device *pdev; + struct resource res[OMAP_MMC_NR_RES]; + int ret; + + pdev = platform_device_alloc("mmci-omap", id); + if (!pdev) + return -ENOMEM; + + memset(res, 0, OMAP_MMC_NR_RES * sizeof(struct resource)); + res[0].start = base; + res[0].end = base + size - 1; + res[0].flags = IORESOURCE_MEM; + res[1].start = res[1].end = irq; + res[1].flags = IORESOURCE_IRQ; + + ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); + if (ret == 0) + ret = platform_device_add_data(pdev, data, sizeof(*data)); + if (ret) + goto fail; + + ret = platform_device_add(pdev); + if (ret) + goto fail; + return 0; -void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info) -{ - switch (host) { - case 1: - mmc1_data = *info; - break; -#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2430) || \ - defined(CONFIG_ARCH_OMAP34XX) - case 2: - mmc2_data = *info; - break; -#endif - default: - BUG(); - } +fail: + platform_device_put(pdev); + return ret; } -#else -static inline void omap_init_mmc(void) {} -void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info) {} #endif /*-------------------------------------------------------------------------*/ @@ -532,7 +378,6 @@ static int __init omap_init_devices(void) */ omap_init_dsp(); omap_init_kp(); - omap_init_mmc(); omap_init_uwire(); omap_init_wdt(); omap_init_rng(); diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 50f8b4a..692d2b4 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -29,7 +29,7 @@ #include <asm/system.h> #include <mach/hardware.h> -#include <asm/dma.h> +#include <mach/dma.h> #include <mach/tc.h> @@ -1848,9 +1848,22 @@ static int omap2_dma_handle_ch(int ch) printk(KERN_INFO "DMA synchronization event drop occurred with device " "%d\n", dma_chan[ch].dev_id); - if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) + if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { printk(KERN_INFO "DMA transaction error with device %d\n", dma_chan[ch].dev_id); + if (cpu_class_is_omap2()) { + /* Errata: sDMA Channel is not disabled + * after a transaction error. So we explicitely + * disable the channel + */ + u32 ccr; + + ccr = dma_read(CCR(ch)); + ccr &= ~OMAP_DMA_CCR_EN; + dma_write(ccr, CCR(ch)); + dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; + } + } if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ)) printk(KERN_INFO "DMA secure error with device %d\n", dma_chan[ch].dev_id); diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 963c31c..e4f0ce0 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -539,10 +539,6 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); - /* REVISIT: hw feature, ttgr overtaking tldr? */ - while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))) - cpu_relax(); - omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); } @@ -553,14 +549,15 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, u32 l; l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); - if (autoreload) + if (autoreload) { l |= OMAP_TIMER_CTRL_AR; - else + omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); + } else { l &= ~OMAP_TIMER_CTRL_AR; + } l |= OMAP_TIMER_CTRL_ST; omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load); - omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); } diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 424049d..07b6968 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -152,6 +152,7 @@ struct gpio_bank { u32 level_mask; spinlock_t lock; struct gpio_chip chip; + struct clk *dbck; }; #define METHOD_MPUIO 0 @@ -244,6 +245,8 @@ static inline struct gpio_bank *get_gpio_bank(int gpio) return &gpio_bank[gpio >> 5]; if (cpu_is_omap34xx()) return &gpio_bank[gpio >> 5]; + BUG(); + return NULL; } static inline int get_gpio_index(int gpio) @@ -332,19 +335,6 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) __raw_writel(l, reg); } -void omap_set_gpio_direction(int gpio, int is_input) -{ - struct gpio_bank *bank; - unsigned long flags; - - if (check_gpio(gpio) < 0) - return; - bank = get_gpio_bank(gpio); - spin_lock_irqsave(&bank->lock, flags); - _set_gpio_direction(bank, get_gpio_index(gpio), is_input); - spin_unlock_irqrestore(&bank->lock, flags); -} - static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) { void __iomem *reg = bank->base; @@ -406,20 +396,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) __raw_writel(l, reg); } -void omap_set_gpio_dataout(int gpio, int enable) -{ - struct gpio_bank *bank; - unsigned long flags; - - if (check_gpio(gpio) < 0) - return; - bank = get_gpio_bank(gpio); - spin_lock_irqsave(&bank->lock, flags); - _set_gpio_dataout(bank, get_gpio_index(gpio), enable); - spin_unlock_irqrestore(&bank->lock, flags); -} - -int omap_get_gpio_datain(int gpio) +static int __omap_get_gpio_datain(int gpio) { struct gpio_bank *bank; void __iomem *reg; @@ -473,6 +450,7 @@ void omap_set_gpio_debounce(int gpio, int enable) { struct gpio_bank *bank; void __iomem *reg; + unsigned long flags; u32 val, l = 1 << get_gpio_index(gpio); if (cpu_class_is_omap1()) @@ -480,16 +458,28 @@ void omap_set_gpio_debounce(int gpio, int enable) bank = get_gpio_bank(gpio); reg = bank->base; - reg += OMAP24XX_GPIO_DEBOUNCE_EN; + + spin_lock_irqsave(&bank->lock, flags); val = __raw_readl(reg); - if (enable) + if (enable && !(val & l)) val |= l; - else + else if (!enable && (val & l)) val &= ~l; + else + goto done; + + if (cpu_is_omap34xx()) { + if (enable) + clk_enable(bank->dbck); + else + clk_disable(bank->dbck); + } __raw_writel(val, reg); +done: + spin_unlock_irqrestore(&bank->lock, flags); } EXPORT_SYMBOL(omap_set_gpio_debounce); @@ -906,26 +896,17 @@ static int gpio_wake_enable(unsigned int irq, unsigned int enable) return retval; } -int omap_request_gpio(int gpio) +static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) { - struct gpio_bank *bank; + struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); unsigned long flags; - int status; - - if (check_gpio(gpio) < 0) - return -EINVAL; - status = gpio_request(gpio, NULL); - if (status < 0) - return status; - - bank = get_gpio_bank(gpio); spin_lock_irqsave(&bank->lock, flags); /* Set trigger to none. You need to enable the desired trigger with * request_irq() or set_irq_type(). */ - _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); + _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); #ifdef CONFIG_ARCH_OMAP15XX if (bank->method == METHOD_GPIO_1510) { @@ -933,7 +914,7 @@ int omap_request_gpio(int gpio) /* Claim the pin for MPU */ reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; - __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg); + __raw_writel(__raw_readl(reg) | (1 << offset), reg); } #endif spin_unlock_irqrestore(&bank->lock, flags); @@ -941,39 +922,28 @@ int omap_request_gpio(int gpio) return 0; } -void omap_free_gpio(int gpio) +static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) { - struct gpio_bank *bank; + struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); unsigned long flags; - if (check_gpio(gpio) < 0) - return; - bank = get_gpio_bank(gpio); spin_lock_irqsave(&bank->lock, flags); - if (unlikely(!gpiochip_is_requested(&bank->chip, - get_gpio_index(gpio)))) { - spin_unlock_irqrestore(&bank->lock, flags); - printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); - dump_stack(); - return; - } #ifdef CONFIG_ARCH_OMAP16XX if (bank->method == METHOD_GPIO_1610) { /* Disable wake-up during idle for dynamic tick */ void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; - __raw_writel(1 << get_gpio_index(gpio), reg); + __raw_writel(1 << offset, reg); } #endif #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) if (bank->method == METHOD_GPIO_24XX) { /* Disable wake-up during idle for dynamic tick */ void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; - __raw_writel(1 << get_gpio_index(gpio), reg); + __raw_writel(1 << offset, reg); } #endif - _reset_gpio(bank, gpio); + _reset_gpio(bank, bank->chip.base + offset); spin_unlock_irqrestore(&bank->lock, flags); - gpio_free(gpio); } /* @@ -1252,7 +1222,7 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset) static int gpio_get(struct gpio_chip *chip, unsigned offset) { - return omap_get_gpio_datain(chip->base + offset); + return __omap_get_gpio_datain(chip->base + offset); } static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) @@ -1279,6 +1249,14 @@ static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) spin_unlock_irqrestore(&bank->lock, flags); } +static int gpio_2irq(struct gpio_chip *chip, unsigned offset) +{ + struct gpio_bank *bank; + + bank = container_of(chip, struct gpio_bank, chip); + return bank->virtual_irq_start + offset; +} + /*---------------------------------------------------------------------*/ static int initialized; @@ -1296,7 +1274,6 @@ static struct clk * gpio5_fck; #endif #if defined(CONFIG_ARCH_OMAP3) -static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS]; static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; #endif @@ -1310,9 +1287,7 @@ static int __init _omap_gpio_init(void) int i; int gpio = 0; struct gpio_bank *bank; -#if defined(CONFIG_ARCH_OMAP3) char clk_name[11]; -#endif initialized = 1; @@ -1367,12 +1342,6 @@ static int __init _omap_gpio_init(void) printk(KERN_ERR "Could not get %s\n", clk_name); else clk_enable(gpio_iclks[i]); - sprintf(clk_name, "gpio%d_fck", i + 1); - gpio_fclks[i] = clk_get(NULL, clk_name); - if (IS_ERR(gpio_fclks[i])) - printk(KERN_ERR "Could not get %s\n", clk_name); - else - clk_enable(gpio_fclks[i]); } } #endif @@ -1479,10 +1448,13 @@ static int __init _omap_gpio_init(void) /* REVISIT eventually switch from OMAP-specific gpio structs * over to the generic ones */ + bank->chip.request = omap_gpio_request; + bank->chip.free = omap_gpio_free; bank->chip.direction_input = gpio_input; bank->chip.get = gpio_get; bank->chip.direction_output = gpio_output; bank->chip.set = gpio_set; + bank->chip.to_irq = gpio_2irq; if (bank_is_mpuio(bank)) { bank->chip.label = "mpuio"; #ifdef CONFIG_ARCH_OMAP16XX @@ -1511,6 +1483,13 @@ static int __init _omap_gpio_init(void) } set_irq_chained_handler(bank->irq, gpio_irq_handler); set_irq_data(bank->irq, bank); + + if (cpu_is_omap34xx()) { + sprintf(clk_name, "gpio%d_dbck", i + 1); + bank->dbck = clk_get(NULL, clk_name); + if (IS_ERR(bank->dbck)) + printk(KERN_ERR "Could not get %s\n", clk_name); + } } /* Enable system clock for GPIO module. @@ -1739,12 +1718,6 @@ static int __init omap_gpio_sysinit(void) return ret; } -EXPORT_SYMBOL(omap_request_gpio); -EXPORT_SYMBOL(omap_free_gpio); -EXPORT_SYMBOL(omap_set_gpio_direction); -EXPORT_SYMBOL(omap_set_gpio_dataout); -EXPORT_SYMBOL(omap_get_gpio_datain); - arch_initcall(omap_gpio_sysinit); @@ -1801,14 +1774,14 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) continue; irq = bank->virtual_irq_start + j; - value = omap_get_gpio_datain(gpio); + value = gpio_get_value(gpio); is_in = gpio_is_input(bank, mask); if (bank_is_mpuio(bank)) seq_printf(s, "MPUIO %2d ", j); else seq_printf(s, "GPIO %3d ", gpio); - seq_printf(s, "(%10s): %s %s", + seq_printf(s, "(%-20.20s): %s %s", label, is_in ? "in " : "out", value ? "hi" : "lo"); diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index 0e6d147..89a6ab0 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c @@ -79,26 +79,43 @@ static struct platform_device omap_i2c_devices[] = { #endif }; -static void __init omap_i2c_mux_pins(int bus_id) +#if defined(CONFIG_ARCH_OMAP24XX) +static const int omap24xx_pins[][2] = { + { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA }, + { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA }, +}; +#else +static const int omap24xx_pins[][2] = {}; +#endif +#if defined(CONFIG_ARCH_OMAP34XX) +static const int omap34xx_pins[][2] = { + { K21_34XX_I2C1_SCL, J21_34XX_I2C1_SDA}, + { AF15_34XX_I2C2_SCL, AE15_34XX_I2C2_SDA}, + { AF14_34XX_I2C3_SCL, AG14_34XX_I2C3_SDA}, +}; +#else +static const int omap34xx_pins[][2] = {}; +#endif + +static void __init omap_i2c_mux_pins(int bus) { - /* TODO: Muxing for OMAP3 */ - switch (bus_id) { - case 1: - if (cpu_class_is_omap1()) { - omap_cfg_reg(I2C_SCL); - omap_cfg_reg(I2C_SDA); - } else if (cpu_is_omap24xx()) { - omap_cfg_reg(M19_24XX_I2C1_SCL); - omap_cfg_reg(L15_24XX_I2C1_SDA); - } - break; - case 2: - if (cpu_is_omap24xx()) { - omap_cfg_reg(J15_24XX_I2C2_SCL); - omap_cfg_reg(H19_24XX_I2C2_SDA); - } - break; + int scl, sda; + + if (cpu_class_is_omap1()) { + scl = I2C_SCL; + sda = I2C_SDA; + } else if (cpu_is_omap24xx()) { + scl = omap24xx_pins[bus][0]; + sda = omap24xx_pins[bus][1]; + } else if (cpu_is_omap34xx()) { + scl = omap34xx_pins[bus][0]; + sda = omap34xx_pins[bus][1]; + } else { + return; } + + omap_cfg_reg(sda); + omap_cfg_reg(scl); } int __init omap_register_i2c_bus(int bus_id, u32 clkrate, @@ -142,6 +159,6 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate, res[1].start = irq; } - omap_i2c_mux_pins(bus_id); + omap_i2c_mux_pins(bus_id - 1); return platform_device_register(pdev); } diff --git a/arch/arm/plat-omap/include/mach/board-apollon.h b/arch/arm/plat-omap/include/mach/board-apollon.h index 731c858..61bd5e8 100644 --- a/arch/arm/plat-omap/include/mach/board-apollon.h +++ b/arch/arm/plat-omap/include/mach/board-apollon.h @@ -29,12 +29,14 @@ #ifndef __ASM_ARCH_OMAP_APOLLON_H #define __ASM_ARCH_OMAP_APOLLON_H +#include <mach/cpu.h> + extern void apollon_mmc_init(void); static inline int apollon_plus(void) { /* The apollon plus has IDCODE revision 5 */ - return system_rev & 0xc0; + return omap_rev() & 0xc0; } /* Placeholder for APOLLON specific defines */ diff --git a/arch/arm/plat-omap/include/mach/board-h2.h b/arch/arm/plat-omap/include/mach/board-h2.h index 2a050e9..15531c8 100644 --- a/arch/arm/plat-omap/include/mach/board-h2.h +++ b/arch/arm/plat-omap/include/mach/board-h2.h @@ -29,13 +29,13 @@ #ifndef __ASM_ARCH_OMAP_H2_H #define __ASM_ARCH_OMAP_H2_H -/* Placeholder for H2 specific defines */ - /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ #define OMAP1610_ETHR_START 0x04000300 +#define H2_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) +# define H2_TPS_GPIO_MMC_PWR_EN (H2_TPS_GPIO_BASE + 3) + extern void h2_mmc_init(void); -extern void h2_mmc_slot_cover_handler(void *arg, int state); #endif /* __ASM_ARCH_OMAP_H2_H */ diff --git a/arch/arm/plat-omap/include/mach/board-ldp.h b/arch/arm/plat-omap/include/mach/board-ldp.h index 66e2746..f233996 100644 --- a/arch/arm/plat-omap/include/mach/board-ldp.h +++ b/arch/arm/plat-omap/include/mach/board-ldp.h @@ -32,5 +32,8 @@ extern void twl4030_bci_battery_init(void); #define TWL4030_IRQNUM INT_34XX_SYS_NIRQ - +#define LDP_SMC911X_CS 1 +#define LDP_SMC911X_GPIO 152 +#define DEBUG_BASE 0x08000000 +#define OMAP34XX_ETHR_START DEBUG_BASE #endif /* __ASM_ARCH_OMAP_LDP_H */ diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/mach/board.h index c23c12c..9466772 100644 --- a/arch/arm/plat-omap/include/mach/board.h +++ b/arch/arm/plat-omap/include/mach/board.h @@ -16,7 +16,6 @@ /* Different peripheral ids */ #define OMAP_TAG_CLOCK 0x4f01 -#define OMAP_TAG_MMC 0x4f02 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 #define OMAP_TAG_USB 0x4f04 #define OMAP_TAG_LCD 0x4f05 @@ -35,27 +34,6 @@ struct omap_clock_config { u8 system_clock_type; }; -struct omap_mmc_conf { - unsigned enabled:1; - /* nomux means "standard" muxing is wrong on this board, and that - * board-specific code handled it before common init logic. - */ - unsigned nomux:1; - /* switch pin can be for card detect (default) or card cover */ - unsigned cover:1; - /* 4 wire signaling is optional, and is only used for SD/SDIO */ - unsigned wire4:1; - /* use the internal clock */ - unsigned internal_clock:1; - s16 power_pin; - s16 switch_pin; - s16 wp_pin; -}; - -struct omap_mmc_config { - struct omap_mmc_conf mmc[2]; -}; - struct omap_serial_console_config { u8 console_uart; u32 console_speed; diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h index dc988676..269147f 100644 --- a/arch/arm/plat-omap/include/mach/control.h +++ b/arch/arm/plat-omap/include/mach/control.h @@ -74,6 +74,7 @@ #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) +#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) /* 24xx-only CONTROL_GENERAL register offsets */ #define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) @@ -140,6 +141,7 @@ #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) +#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0) #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) /* @@ -154,11 +156,14 @@ * and the security mode (secure, non-secure, don't care) */ /* CONTROL_DEVCONF0 bits */ +#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ #define OMAP24XX_USBSTANDBYCTRL (1 << 15) #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) /* CONTROL_DEVCONF1 bits */ +#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) +#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ #define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ @@ -172,6 +177,18 @@ #define OMAP2_SYSBOOT_1_MASK (1 << 1) #define OMAP2_SYSBOOT_0_MASK (1 << 0) +/* CONTROL_PBIAS_LITE bits */ +#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) +#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) +#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) +#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) +#define OMAP343X_PBIASLITEVMODE1 (1 << 8) +#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) +#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) +#define OMAP2_PBIASSPEEDCTRL0 (1 << 2) +#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) +#define OMAP2_PBIASLITEVMODE0 (1 << 0) + #ifndef __ASSEMBLY__ #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) extern void __iomem *omap_ctrl_base_get(void); diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h index e046418..b2062f1 100644 --- a/arch/arm/plat-omap/include/mach/cpu.h +++ b/arch/arm/plat-omap/include/mach/cpu.h @@ -28,13 +28,18 @@ struct omap_chip_id { u8 oc; + u8 type; }; #define OMAP_CHIP_INIT(x) { .oc = x } -extern unsigned int system_rev; - -#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f) +/* + * omap_rev bits: + * CPU id bits (0730, 1510, 1710, 2422...) [31:16] + * CPU revision (See _REV_ defined in cpu.h) [15:08] + * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00] + */ +unsigned int omap_rev(void); /* * Test if multicore OMAP support is needed @@ -108,7 +113,7 @@ extern unsigned int system_rev; * cpu_is_omap243x(): True for OMAP2430 * cpu_is_omap343x(): True for OMAP3430 */ -#define GET_OMAP_CLASS ((system_rev >> 24) & 0xff) +#define GET_OMAP_CLASS (omap_rev() & 0xff) #define IS_OMAP_CLASS(class, id) \ static inline int is_omap ##class (void) \ @@ -116,7 +121,7 @@ static inline int is_omap ##class (void) \ return (GET_OMAP_CLASS == (id)) ? 1 : 0; \ } -#define GET_OMAP_SUBCLASS ((system_rev >> 20) & 0x0fff) +#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff) #define IS_OMAP_SUBCLASS(subclass, id) \ static inline int is_omap ##subclass (void) \ @@ -226,7 +231,7 @@ IS_OMAP_SUBCLASS(343x, 0x343) * cpu_is_omap2430(): True for OMAP2430 * cpu_is_omap3430(): True for OMAP3430 */ -#define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff) +#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff) #define IS_OMAP_TYPE(type, id) \ static inline int is_omap ##type (void) \ @@ -320,44 +325,20 @@ IS_OMAP_TYPE(3430, 0x3430) #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx()) #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) -/* - * Macros to detect silicon revision of OMAP2/3 processors. - * is_sil_rev_greater_than: true if passed cpu type & its rev is greater. - * is_sil_rev_lesser_than: true if passed cpu type & its rev is lesser. - * is_sil_rev_equal_to: true if passed cpu type & its rev is equal. - * get_sil_rev: return the silicon rev value. - */ -#define get_sil_omap_type(rev) ((rev & 0xffff0000) >> 16) -#define get_sil_revision(rev) ((rev & 0x0000f000) >> 12) -#define is_sil_rev_greater_than(rev) \ - ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ - (get_sil_revision(system_rev) > get_sil_revision(rev))) +/* Various silicon revisions for omap2 */ +#define OMAP242X_CLASS 0x24200024 +#define OMAP2420_REV_ES1_0 0x24200024 +#define OMAP2420_REV_ES2_0 0x24201024 -#define is_sil_rev_less_than(rev) \ - ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ - (get_sil_revision(system_rev) < get_sil_revision(rev))) +#define OMAP243X_CLASS 0x24300024 +#define OMAP2430_REV_ES1_0 0x24300024 -#define is_sil_rev_equal_to(rev) \ - ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ - (get_sil_revision(system_rev) == get_sil_revision(rev))) - -#define get_sil_rev() \ - get_sil_revision(system_rev) - -/* Various silicon macros defined here */ -#define OMAP242X_CLASS 0x24200000 -#define OMAP2420_REV_ES1_0 0x24200000 -#define OMAP2420_REV_ES2_0 0x24201000 - -#define OMAP243X_CLASS 0x24300000 -#define OMAP2430_REV_ES1_0 0x24300000 - -#define OMAP343X_CLASS 0x34300000 -#define OMAP3430_REV_ES1_0 0x34300000 -#define OMAP3430_REV_ES2_0 0x34301000 -#define OMAP3430_REV_ES2_1 0x34302000 -#define OMAP3430_REV_ES2_2 0x34303000 +#define OMAP343X_CLASS 0x34300034 +#define OMAP3430_REV_ES1_0 0x34300034 +#define OMAP3430_REV_ES2_0 0x34301034 +#define OMAP3430_REV_ES2_1 0x34302034 +#define OMAP3430_REV_ES3_0 0x34303034 /* * omap_chip bits @@ -382,23 +363,16 @@ IS_OMAP_TYPE(3430, 0x3430) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) int omap_chip_is(struct omap_chip_id oci); - +int omap_type(void); /* * Macro to detect device type i.e. EMU/HS/TST/GP/BAD */ -#define DEVICE_TYPE_TEST 0 -#define DEVICE_TYPE_EMU 1 -#define DEVICE_TYPE_SEC 2 -#define DEVICE_TYPE_GP 3 -#define DEVICE_TYPE_BAD 4 - -#define get_device_type() ((system_rev & 0x700) >> 8) -#define is_device_type_test() (get_device_type() == DEVICE_TYPE_TEST) -#define is_device_type_emu() (get_device_type() == DEVICE_TYPE_EMU) -#define is_device_type_sec() (get_device_type() == DEVICE_TYPE_SEC) -#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP) -#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD) +#define OMAP2_DEVICE_TYPE_TEST 0 +#define OMAP2_DEVICE_TYPE_EMU 1 +#define OMAP2_DEVICE_TYPE_SEC 2 +#define OMAP2_DEVICE_TYPE_GP 3 +#define OMAP2_DEVICE_TYPE_BAD 4 void omap2_check_revision(void); diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h index 98e9008..04e68e8 100644 --- a/arch/arm/plat-omap/include/mach/gpio.h +++ b/arch/arm/plat-omap/include/mach/gpio.h @@ -71,11 +71,6 @@ IH_GPIO_BASE + (nr)) extern int omap_gpio_init(void); /* Call from board init only */ -extern int omap_request_gpio(int gpio); -extern void omap_free_gpio(int gpio); -extern void omap_set_gpio_direction(int gpio, int is_input); -extern void omap_set_gpio_dataout(int gpio, int enable); -extern int omap_get_gpio_datain(int gpio); extern void omap2_gpio_prepare_for_retention(void); extern void omap2_gpio_resume_after_retention(void); extern void omap_set_gpio_debounce(int gpio, int enable); @@ -92,6 +87,16 @@ extern void omap_set_gpio_debounce_time(int gpio, int enable); #include <linux/errno.h> #include <asm-generic/gpio.h> +static inline int omap_request_gpio(int gpio) +{ + return gpio_request(gpio, "FIXME"); +} + +static inline void omap_free_gpio(int gpio) +{ + gpio_free(gpio); +} + static inline int gpio_get_value(unsigned gpio) { return __gpio_get_value(gpio); @@ -109,16 +114,24 @@ static inline int gpio_cansleep(unsigned gpio) static inline int gpio_to_irq(unsigned gpio) { - if (gpio < (OMAP_MAX_GPIO_LINES + 16)) - return OMAP_GPIO_IRQ(gpio); - return -EINVAL; + return __gpio_to_irq(gpio); } static inline int irq_to_gpio(unsigned irq) { + int tmp; + + /* omap1 SOC mpuio */ if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16))) return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES; - return irq - IH_GPIO_BASE; + + /* SOC gpio */ + tmp = irq - IH_GPIO_BASE; + if (tmp < OMAP_MAX_GPIO_LINES) + return tmp; + + /* we don't supply reverse mappings for non-SOC gpios */ + return -EIO; } #endif diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h index adc83b7..d92bf79 100644 --- a/arch/arm/plat-omap/include/mach/io.h +++ b/arch/arm/plat-omap/include/mach/io.h @@ -42,8 +42,8 @@ * We don't actually have real ISA nor PCI buses, but there is so many * drivers out there that might just work if we fake them... */ -#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) -#define __mem_pci(a) (a) +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) /* * ---------------------------------------------------------------------------- @@ -51,8 +51,6 @@ * ---------------------------------------------------------------------------- */ -#define PCIO_BASE 0 - #if defined(CONFIG_ARCH_OMAP1) #define IO_PHYS 0xFFFB0000 diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h index d40cac6..211c9f6 100644 --- a/arch/arm/plat-omap/include/mach/memory.h +++ b/arch/arm/plat-omap/include/mach/memory.h @@ -43,18 +43,7 @@ #endif /* - * Conversion between SDRAM and fake PCI bus, used by USB - * NOTE: Physical address must be converted to Local Bus address - * on OMAP-1510 only - */ - -/* * Bus address is physical address, except for OMAP-1510 Local Bus. - */ -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt(x) __phys_to_virt(x) - -/* * OMAP-1510 bus address is translated into a Local Bus address if the * OMAP bus type is lbus. We do the address translation based on the * device overriding the defaults used in the dma-mapping API. @@ -74,16 +63,16 @@ #define __arch_page_to_dma(dev, page) ({is_lbus_device(dev) ? \ (dma_addr_t)virt_to_lbus(page_address(page)) : \ - (dma_addr_t)__virt_to_bus(page_address(page));}) + (dma_addr_t)__virt_to_phys(page_address(page));}) #define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \ lbus_to_virt(addr) : \ - __bus_to_virt(addr)); }) + __phys_to_virt(addr)); }) #define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \ (dma_addr_t) (is_lbus_device(dev) ? \ virt_to_lbus(__addr) : \ - __virt_to_bus(__addr)); }) + __virt_to_phys(__addr)); }) #endif /* CONFIG_ARCH_OMAP15XX */ diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/mach/mmc.h index fc15d13..031250f 100644 --- a/arch/arm/plat-omap/include/mach/mmc.h +++ b/arch/arm/plat-omap/include/mach/mmc.h @@ -17,12 +17,28 @@ #include <mach/board.h> +#define OMAP15XX_NR_MMC 1 +#define OMAP16XX_NR_MMC 2 +#define OMAP1_MMC_SIZE 0x080 +#define OMAP1_MMC1_BASE 0xfffb7800 +#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */ + +#define OMAP24XX_NR_MMC 2 +#define OMAP34XX_NR_MMC 3 +#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE +#define HSMMC_SIZE 0x200 +#define OMAP2_MMC1_BASE 0x4809c000 +#define OMAP2_MMC2_BASE 0x480b4000 +#define OMAP3_MMC3_BASE 0x480ad000 +#define HSMMC3 (1 << 2) +#define HSMMC2 (1 << 1) +#define HSMMC1 (1 << 0) + #define OMAP_MMC_MAX_SLOTS 2 struct omap_mmc_platform_data { - struct omap_mmc_conf conf; - /* number of slots on board */ + /* number of slots per controller */ unsigned nr_slots:2; /* set if your board has components or wiring that limits the @@ -41,7 +57,31 @@ struct omap_mmc_platform_data { int (*suspend)(struct device *dev, int slot); int (*resume)(struct device *dev, int slot); + u64 dma_mask; + struct omap_mmc_slot_data { + + /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC; + * 8 wire signaling is also optional, and is used with HSMMC + */ + u8 wires; + + /* + * nomux means "standard" muxing is wrong on this board, and + * that board-specific code handled it before common init logic. + */ + unsigned nomux:1; + + /* switch pin can be for card detect (default) or card cover */ + unsigned cover:1; + + /* use the internal clock */ + unsigned internal_clock:1; + s16 power_pin; + + int switch_pin; /* gpio (card detect) */ + int gpio_wp; /* gpio (write protect) */ + int (* set_bus_mode)(struct device *dev, int slot, int bus_mode); int (* set_power)(struct device *dev, int slot, int power_on, int vdd); int (* get_ro)(struct device *dev, int slot); @@ -49,8 +89,8 @@ struct omap_mmc_platform_data { /* return MMC cover switch state, can be NULL if not supported. * * possible return values: - * 0 - open - * 1 - closed + * 0 - closed + * 1 - open */ int (* get_cover_state)(struct device *dev, int slot); @@ -66,9 +106,31 @@ struct omap_mmc_platform_data { } slots[OMAP_MMC_MAX_SLOTS]; }; -extern void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info); - /* called from board-specific card detection service routine */ extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed); +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ + defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) +void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, + int nr_controllers); +void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, + int nr_controllers); +int omap_mmc_add(int id, unsigned long base, unsigned long size, + unsigned int irq, struct omap_mmc_platform_data *data); +#else +static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, + int nr_controllers) +{ +} +static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, + int nr_controllers) +{ +} +static inline int omap_mmc_add(int id, unsigned long base, unsigned long size, + unsigned int irq, struct omap_mmc_platform_data *data) +{ + return 0; +} + +#endif #endif diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h index 6bbf178..f4362b8 100644 --- a/arch/arm/plat-omap/include/mach/mux.h +++ b/arch/arm/plat-omap/include/mach/mux.h @@ -632,6 +632,15 @@ enum omap24xx_index { AC7_2430_USB0HS_DATA7, /* 2430 McBSP */ + AD6_2430_MCBSP_CLKS, + + AB2_2430_MCBSP1_CLKR, + AD5_2430_MCBSP1_FSR, + AA1_2430_MCBSP1_DX, + AF3_2430_MCBSP1_DR, + AB3_2430_MCBSP1_FSX, + Y9_2430_MCBSP1_CLKX, + AC10_2430_MCBSP2_FSX, AD16_2430_MCBSP2_CLX, AE13_2430_MCBSP2_DX, @@ -641,6 +650,30 @@ enum omap24xx_index { AE13_2430_MCBSP2_DX_OFF, AD13_2430_MCBSP2_DR_OFF, + AC9_2430_MCBSP3_CLKX, + AE4_2430_MCBSP3_FSX, + AE2_2430_MCBSP3_DR, + AF4_2430_MCBSP3_DX, + + N3_2430_MCBSP4_CLKX, + AD23_2430_MCBSP4_DR, + AB25_2430_MCBSP4_DX, + AC25_2430_MCBSP4_FSX, + + AE16_2430_MCBSP5_CLKX, + AF12_2430_MCBSP5_FSX, + K7_2430_MCBSP5_DX, + M1_2430_MCBSP5_DR, + + /* 2430 McSPI*/ + Y18_2430_MCSPI1_CLK, + AD15_2430_MCSPI1_SIMO, + AE17_2430_MCSPI1_SOMI, + U1_2430_MCSPI1_CS0, + + /* Touchscreen GPIO */ + AF19_2430_GPIO_85, + }; enum omap34xx_index { @@ -749,6 +782,14 @@ enum omap34xx_index { AD2_3430_USB3FS_PHY_MM3_TXDAT, AC1_3430_USB3FS_PHY_MM3_TXEN_N, + /* 34xx GPIO + * - normally these are bidirectional, no internal pullup/pulldown + * - "_UP" suffix (GPIO3_UP) if internal pullup is configured + * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown + * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx) + */ + AH8_34XX_GPIO29, + J25_34XX_GPIO170, }; struct omap_mux_cfg { diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index dcd9d16..be7bcaf 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -24,6 +24,7 @@ #include <mach/sram.h> #include <mach/board.h> +#include <mach/cpu.h> #include <mach/control.h> @@ -87,7 +88,7 @@ static int is_sram_locked(void) int type = 0; if (cpu_is_omap242x()) - type = system_rev & OMAP2_DEVICETYPE_MASK; + type = omap_rev() & OMAP2_DEVICETYPE_MASK; if (type == GP_DEVICE) { /* RAMFW: R/W access to all initiators for all qualifier sets */ diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index 198f3dd..56021a7 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -6,3 +6,5 @@ obj-y := irq.o pcie.o time.o obj-m := obj-n := obj- := + +obj-$(CONFIG_GENERIC_GPIO) += gpio.o diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c new file mode 100644 index 0000000..9671864 --- /dev/null +++ b/arch/arm/plat-orion/gpio.c @@ -0,0 +1,415 @@ +/* + * arch/arm/plat-orion/gpio.c + * + * Marvell Orion SoC GPIO handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/module.h> +#include <linux/spinlock.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <asm/gpio.h> + +static DEFINE_SPINLOCK(gpio_lock); +static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ +static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; + +static inline void __set_direction(unsigned pin, int input) +{ + u32 u; + + u = readl(GPIO_IO_CONF(pin)); + if (input) + u |= 1 << (pin & 31); + else + u &= ~(1 << (pin & 31)); + writel(u, GPIO_IO_CONF(pin)); +} + +static void __set_level(unsigned pin, int high) +{ + u32 u; + + u = readl(GPIO_OUT(pin)); + if (high) + u |= 1 << (pin & 31); + else + u &= ~(1 << (pin & 31)); + writel(u, GPIO_OUT(pin)); +} + + +/* + * GENERIC_GPIO primitives. + */ +int gpio_direction_input(unsigned pin) +{ + unsigned long flags; + + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { + pr_debug("%s: invalid GPIO %d\n", __func__, pin); + return -EINVAL; + } + + spin_lock_irqsave(&gpio_lock, flags); + + /* + * Some callers might not have used gpio_request(), + * so flag this pin as requested now. + */ + if (gpio_label[pin] == NULL) + gpio_label[pin] = "?"; + + /* + * Configure GPIO direction. + */ + __set_direction(pin, 1); + + spin_unlock_irqrestore(&gpio_lock, flags); + + return 0; +} +EXPORT_SYMBOL(gpio_direction_input); + +int gpio_direction_output(unsigned pin, int value) +{ + unsigned long flags; + u32 u; + + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { + pr_debug("%s: invalid GPIO %d\n", __func__, pin); + return -EINVAL; + } + + spin_lock_irqsave(&gpio_lock, flags); + + /* + * Some callers might not have used gpio_request(), + * so flag this pin as requested now. + */ + if (gpio_label[pin] == NULL) + gpio_label[pin] = "?"; + + /* + * Disable blinking. + */ + u = readl(GPIO_BLINK_EN(pin)); + u &= ~(1 << (pin & 31)); + writel(u, GPIO_BLINK_EN(pin)); + + /* + * Configure GPIO output value. + */ + __set_level(pin, value); + + /* + * Configure GPIO direction. + */ + __set_direction(pin, 0); + + spin_unlock_irqrestore(&gpio_lock, flags); + + return 0; +} +EXPORT_SYMBOL(gpio_direction_output); + +int gpio_get_value(unsigned pin) +{ + int val; + + if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31))) + val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin)); + else + val = readl(GPIO_OUT(pin)); + + return (val >> (pin & 31)) & 1; +} +EXPORT_SYMBOL(gpio_get_value); + +void gpio_set_value(unsigned pin, int value) +{ + unsigned long flags; + u32 u; + + spin_lock_irqsave(&gpio_lock, flags); + + /* + * Disable blinking. + */ + u = readl(GPIO_BLINK_EN(pin)); + u &= ~(1 << (pin & 31)); + writel(u, GPIO_BLINK_EN(pin)); + + /* + * Configure GPIO output value. + */ + __set_level(pin, value); + + spin_unlock_irqrestore(&gpio_lock, flags); +} +EXPORT_SYMBOL(gpio_set_value); + +int gpio_request(unsigned pin, const char *label) +{ + unsigned long flags; + int ret; + + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { + pr_debug("%s: invalid GPIO %d\n", __func__, pin); + return -EINVAL; + } + + spin_lock_irqsave(&gpio_lock, flags); + if (gpio_label[pin] == NULL) { + gpio_label[pin] = label ? label : "?"; + ret = 0; + } else { + pr_debug("%s: GPIO %d already used as %s\n", + __func__, pin, gpio_label[pin]); + ret = -EBUSY; + } + spin_unlock_irqrestore(&gpio_lock, flags); + + return ret; +} +EXPORT_SYMBOL(gpio_request); + +void gpio_free(unsigned pin) +{ + if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { + pr_debug("%s: invalid GPIO %d\n", __func__, pin); + return; + } + + if (gpio_label[pin] == NULL) + pr_warning("%s: GPIO %d already freed\n", __func__, pin); + else + gpio_label[pin] = NULL; +} +EXPORT_SYMBOL(gpio_free); + + +/* + * Orion-specific GPIO API extensions. + */ +void __init orion_gpio_set_unused(unsigned pin) +{ + /* + * Configure as output, drive low. + */ + __set_level(pin, 0); + __set_direction(pin, 0); +} + +void __init orion_gpio_set_valid(unsigned pin, int valid) +{ + if (valid) + __set_bit(pin, gpio_valid); + else + __clear_bit(pin, gpio_valid); +} + +void orion_gpio_set_blink(unsigned pin, int blink) +{ + unsigned long flags; + u32 u; + + spin_lock_irqsave(&gpio_lock, flags); + + /* + * Set output value to zero. + */ + __set_level(pin, 0); + + u = readl(GPIO_BLINK_EN(pin)); + if (blink) + u |= 1 << (pin & 31); + else + u &= ~(1 << (pin & 31)); + writel(u, GPIO_BLINK_EN(pin)); + + spin_unlock_irqrestore(&gpio_lock, flags); +} +EXPORT_SYMBOL(orion_gpio_set_blink); + + +/***************************************************************************** + * Orion GPIO IRQ + * + * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same + * value of the line or the opposite value. + * + * Level IRQ handlers: DATA_IN is used directly as cause register. + * Interrupt are masked by LEVEL_MASK registers. + * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. + * Interrupt are masked by EDGE_MASK registers. + * Both-edge handlers: Similar to regular Edge handlers, but also swaps + * the polarity to catch the next line transaction. + * This is a race condition that might not perfectly + * work on some use cases. + * + * Every eight GPIO lines are grouped (OR'ed) before going up to main + * cause register. + * + * EDGE cause mask + * data-in /--------| |-----| |----\ + * -----| |----- ---- to main cause reg + * X \----------------| |----/ + * polarity LEVEL mask + * + ****************************************************************************/ +static void gpio_irq_edge_ack(u32 irq) +{ + int pin = irq_to_gpio(irq); + + writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin)); +} + +static void gpio_irq_edge_mask(u32 irq) +{ + int pin = irq_to_gpio(irq); + u32 u; + + u = readl(GPIO_EDGE_MASK(pin)); + u &= ~(1 << (pin & 31)); + writel(u, GPIO_EDGE_MASK(pin)); +} + +static void gpio_irq_edge_unmask(u32 irq) +{ + int pin = irq_to_gpio(irq); + u32 u; + + u = readl(GPIO_EDGE_MASK(pin)); + u |= 1 << (pin & 31); + writel(u, GPIO_EDGE_MASK(pin)); +} + +static void gpio_irq_level_mask(u32 irq) +{ + int pin = irq_to_gpio(irq); + u32 u; + + u = readl(GPIO_LEVEL_MASK(pin)); + u &= ~(1 << (pin & 31)); + writel(u, GPIO_LEVEL_MASK(pin)); +} + +static void gpio_irq_level_unmask(u32 irq) +{ + int pin = irq_to_gpio(irq); + u32 u; + + u = readl(GPIO_LEVEL_MASK(pin)); + u |= 1 << (pin & 31); + writel(u, GPIO_LEVEL_MASK(pin)); +} + +static int gpio_irq_set_type(u32 irq, u32 type) +{ + int pin = irq_to_gpio(irq); + struct irq_desc *desc; + u32 u; + + u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)); + if (!u) { + printk(KERN_ERR "orion gpio_irq_set_type failed " + "(irq %d, pin %d).\n", irq, pin); + return -EINVAL; + } + + desc = irq_desc + irq; + + /* + * Set edge/level type. + */ + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { + desc->chip = &orion_gpio_irq_edge_chip; + } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { + desc->chip = &orion_gpio_irq_level_chip; + } else { + printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type); + return -EINVAL; + } + + /* + * Configure interrupt polarity. + */ + if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) { + u = readl(GPIO_IN_POL(pin)); + u &= ~(1 << (pin & 31)); + writel(u, GPIO_IN_POL(pin)); + } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) { + u = readl(GPIO_IN_POL(pin)); + u |= 1 << (pin & 31); + writel(u, GPIO_IN_POL(pin)); + } else if (type == IRQ_TYPE_EDGE_BOTH) { + u32 v; + + v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin)); + + /* + * set initial polarity based on current input level + */ + u = readl(GPIO_IN_POL(pin)); + if (v & (1 << (pin & 31))) + u |= 1 << (pin & 31); /* falling */ + else + u &= ~(1 << (pin & 31)); /* rising */ + writel(u, GPIO_IN_POL(pin)); + } + + desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type; + + return 0; +} + +struct irq_chip orion_gpio_irq_edge_chip = { + .name = "orion_gpio_irq_edge", + .ack = gpio_irq_edge_ack, + .mask = gpio_irq_edge_mask, + .unmask = gpio_irq_edge_unmask, + .set_type = gpio_irq_set_type, +}; + +struct irq_chip orion_gpio_irq_level_chip = { + .name = "orion_gpio_irq_level", + .mask = gpio_irq_level_mask, + .mask_ack = gpio_irq_level_mask, + .unmask = gpio_irq_level_unmask, + .set_type = gpio_irq_set_type, +}; + +void orion_gpio_irq_handler(int pinoff) +{ + u32 cause; + int pin; + + cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff)); + cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff)); + + for (pin = pinoff; pin < pinoff + 8; pin++) { + int irq = gpio_to_irq(pin); + struct irq_desc *desc = irq_desc + irq; + + if (!(cause & (1 << (pin & 31)))) + continue; + + if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { + /* Swap polarity (race with GPIO line) */ + u32 polarity; + + polarity = readl(GPIO_IN_POL(pin)); + polarity ^= 1 << (pin & 31); + writel(polarity, GPIO_IN_POL(pin)); + } + desc_handle_irq(irq, desc); + } +} diff --git a/arch/arm/plat-orion/include/plat/ehci-orion.h b/arch/arm/plat-orion/include/plat/ehci-orion.h index 6434305..4ec668e 100644 --- a/arch/arm/plat-orion/include/plat/ehci-orion.h +++ b/arch/arm/plat-orion/include/plat/ehci-orion.h @@ -11,8 +11,16 @@ #include <linux/mbus.h> +enum orion_ehci_phy_ver { + EHCI_PHY_ORION, + EHCI_PHY_DD, + EHCI_PHY_KW, + EHCI_PHY_NA, +}; + struct orion_ehci_data { struct mbus_dram_target_info *dram; + enum orion_ehci_phy_ver phy_version; }; diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h new file mode 100644 index 0000000..54deaf2 --- /dev/null +++ b/arch/arm/plat-orion/include/plat/gpio.h @@ -0,0 +1,39 @@ +/* + * arch/arm/plat-orion/include/plat/gpio.h + * + * Marvell Orion SoC GPIO handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_GPIO_H +#define __PLAT_GPIO_H + +/* + * GENERIC_GPIO primitives. + */ +int gpio_request(unsigned pin, const char *label); +void gpio_free(unsigned pin); +int gpio_direction_input(unsigned pin); +int gpio_direction_output(unsigned pin, int value); +int gpio_get_value(unsigned pin); +void gpio_set_value(unsigned pin, int value); + +/* + * Orion-specific GPIO API extensions. + */ +void orion_gpio_set_unused(unsigned pin); +void orion_gpio_set_valid(unsigned pin, int valid); +void orion_gpio_set_blink(unsigned pin, int blink); + +/* + * GPIO interrupt handling. + */ +extern struct irq_chip orion_gpio_irq_edge_chip; +extern struct irq_chip orion_gpio_irq_level_chip; +void orion_gpio_irq_handler(int irqoff); + + +#endif diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig index 31656c3..de93838 100644 --- a/arch/arm/plat-s3c/Kconfig +++ b/arch/arm/plat-s3c/Kconfig @@ -6,34 +6,32 @@ config PLAT_S3C bool - depends on ARCH_S3C2410 - default y if ARCH_S3C2410 + depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX + default y select NO_IOPORT help Base platform code for any Samsung S3C device # low-level serial option nodes +if PLAT_S3C + config CPU_LLSERIAL_S3C2410_ONLY bool - depends on ARCH_S3C2410 default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440 config CPU_LLSERIAL_S3C2440_ONLY bool - depends on ARCH_S3C2410 default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410 config CPU_LLSERIAL_S3C2410 bool - depends on ARCH_S3C2410 help Selected if there is an S3C2410 (or register compatible) serial low-level implementation needed config CPU_LLSERIAL_S3C2440 bool - depends on ARCH_S3C2410 help Selected if there is an S3C2440 (or register compatible) serial low-level implementation needed @@ -44,7 +42,7 @@ comment "Boot options" config S3C_BOOT_WATCHDOG bool "S3C Initialisation watchdog" - depends on PLAT_S3C && S3C2410_WATCHDOG + depends on S3C2410_WATCHDOG help Say y to enable the watchdog during the kernel decompression stage. If the kernel fails to uncompress, then the watchdog @@ -52,16 +50,22 @@ config S3C_BOOT_WATCHDOG config S3C_BOOT_ERROR_RESET bool "S3C Reboot on decompression error" - depends on PLAT_S3C help Say y here to use the watchdog to reset the system if the kernel decompressor detects an error during decompression. +config S3C_BOOT_UART_FORCE_FIFO + bool "Force UART FIFO on during boot process" + default y + help + Say Y here to force the UART FIFOs on during the kernel + uncompressor + comment "Power management" config S3C2410_PM_DEBUG bool "S3C2410 PM Suspend debug" - depends on PLAT_S3C && PM + depends on PM help Say Y here if you want verbose debugging from the PM Suspend and Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> @@ -69,7 +73,7 @@ config S3C2410_PM_DEBUG config S3C2410_PM_CHECK bool "S3C2410 PM Suspend Memory CRC" - depends on PLAT_S3C && PM && CRC32 + depends on PM && CRC32 help Enable the PM code's memory area checksum over sleep. This option will generate CRCs of all blocks of memory, and store them before @@ -83,7 +87,7 @@ config S3C2410_PM_CHECK config S3C2410_PM_CHECK_CHUNKSIZE int "S3C2410 PM Suspend CRC Chunksize (KiB)" - depends on PLAT_S3C && PM && S3C2410_PM_CHECK + depends on PM && S3C2410_PM_CHECK default 64 help Set the chunksize in Kilobytes of the CRC for checking memory @@ -95,10 +99,77 @@ config S3C2410_PM_CHECK_CHUNKSIZE config S3C_LOWLEVEL_UART_PORT int "S3C UART to use for low-level messages" - depends on PLAT_S3C default 0 help Choice of which UART port to use for the low-level messages, such as the `Uncompressing...` at start time. The value of this configuration should be between zero and two. The port must have been initialised by the boot-loader before use. + +# options for gpiolib support + +config S3C_GPIO_SPACE + int "Space between gpio banks" + default 0 + help + Add a number of spare GPIO entries between each bank for debugging + purposes. This allows any problems where an counter overflows from + one bank to another to be caught, at the expense of using a little + more memory. + +config S3C_GPIO_TRACK + bool + help + Internal configuration option to enable the s3c specific gpio + chip tracking if the platform requires it. + +config S3C_GPIO_PULL_UPDOWN + bool + help + Internal configuration to enable the correct GPIO pull helper + +config S3C_GPIO_PULL_DOWN + bool + help + Internal configuration to enable the correct GPIO pull helper + +config S3C_GPIO_PULL_UP + bool + help + Internal configuration to enable the correct GPIO pull helper + +config S3C_GPIO_CFG_S3C24XX + bool + help + Internal configuration to enable S3C24XX style GPIO configuration + functions. + +config S3C_GPIO_CFG_S3C64XX + bool + help + Internal configuration to enable S3C64XX style GPIO configuration + functions. + +# device definitions to compile in + +config S3C_DEV_HSMMC + bool + help + Compile in platform device definitions for HSMMC code + +config S3C_DEV_HSMMC1 + bool + help + Compile in platform device definitions for HSMMC channel 1 + +config S3C_DEV_I2C1 + bool + help + Compile in platform device definitions for I2C channel 1 + +config S3C_DEV_FB + bool + help + Compile in platform device definition for framebuffer + +endif diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index f03d7b3..39195f9 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -1,3 +1,27 @@ -# dummy makefile, currently just including asm/arm/plat-s3c/include/plat +# arch/arm/plat-s3c/Makefile +# +# Copyright 2008 Simtec Electronics +# +# Licensed under GPLv2 -obj-n := dummy.o +obj-y := +obj-m := +obj-n := +obj- := + +# Core support for all Samsung SoCs + +obj-y += init.o +obj-y += time.o +obj-y += clock.o +obj-y += pwm-clock.o +obj-y += gpio.o +obj-y += gpio-config.o + +# devices + +obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o +obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o +obj-y += dev-i2c0.o +obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o +obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c new file mode 100644 index 0000000..b6be76e --- /dev/null +++ b/arch/arm/plat-s3c/clock.c @@ -0,0 +1,368 @@ +/* linux/arch/arm/plat-s3c24xx/clock.c + * + * Copyright (c) 2004-2005 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24XX Core clock control support + * + * Based on, and code from linux/arch/arm/mach-versatile/clock.c + ** + ** Copyright (C) 2004 ARM Limited. + ** Written by Deep Blue Solutions Limited. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/sysdev.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/clk.h> +#include <linux/spinlock.h> +#include <linux/io.h> + +#include <mach/hardware.h> +#include <asm/irq.h> + +#include <plat/cpu-freq.h> + +#include <plat/clock.h> +#include <plat/cpu.h> + +/* clock information */ + +static LIST_HEAD(clocks); + +/* We originally used an mutex here, but some contexts (see resume) + * are calling functions such as clk_set_parent() with IRQs disabled + * causing an BUG to be triggered. + */ +DEFINE_SPINLOCK(clocks_lock); + +/* enable and disable calls for use with the clk struct */ + +static int clk_null_enable(struct clk *clk, int enable) +{ + return 0; +} + +/* Clock API calls */ + +struct clk *clk_get(struct device *dev, const char *id) +{ + struct clk *p; + struct clk *clk = ERR_PTR(-ENOENT); + int idno; + + if (dev == NULL || dev->bus != &platform_bus_type) + idno = -1; + else + idno = to_platform_device(dev)->id; + + spin_lock(&clocks_lock); + + list_for_each_entry(p, &clocks, list) { + if (p->id == idno && + strcmp(id, p->name) == 0 && + try_module_get(p->owner)) { + clk = p; + break; + } + } + + /* check for the case where a device was supplied, but the + * clock that was being searched for is not device specific */ + + if (IS_ERR(clk)) { + list_for_each_entry(p, &clocks, list) { + if (p->id == -1 && strcmp(id, p->name) == 0 && + try_module_get(p->owner)) { + clk = p; + break; + } + } + } + + spin_unlock(&clocks_lock); + return clk; +} + +void clk_put(struct clk *clk) +{ + module_put(clk->owner); +} + +int clk_enable(struct clk *clk) +{ + if (IS_ERR(clk) || clk == NULL) + return -EINVAL; + + clk_enable(clk->parent); + + spin_lock(&clocks_lock); + + if ((clk->usage++) == 0) + (clk->enable)(clk, 1); + + spin_unlock(&clocks_lock); + return 0; +} + +void clk_disable(struct clk *clk) +{ + if (IS_ERR(clk) || clk == NULL) + return; + + spin_lock(&clocks_lock); + + if ((--clk->usage) == 0) + (clk->enable)(clk, 0); + + spin_unlock(&clocks_lock); + clk_disable(clk->parent); +} + + +unsigned long clk_get_rate(struct clk *clk) +{ + if (IS_ERR(clk)) + return 0; + + if (clk->rate != 0) + return clk->rate; + + if (clk->get_rate != NULL) + return (clk->get_rate)(clk); + + if (clk->parent != NULL) + return clk_get_rate(clk->parent); + + return clk->rate; +} + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (!IS_ERR(clk) && clk->round_rate) + return (clk->round_rate)(clk, rate); + + return rate; +} + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret; + + if (IS_ERR(clk)) + return -EINVAL; + + /* We do not default just do a clk->rate = rate as + * the clock may have been made this way by choice. + */ + + WARN_ON(clk->set_rate == NULL); + + if (clk->set_rate == NULL) + return -EINVAL; + + spin_lock(&clocks_lock); + ret = (clk->set_rate)(clk, rate); + spin_unlock(&clocks_lock); + + return ret; +} + +struct clk *clk_get_parent(struct clk *clk) +{ + return clk->parent; +} + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = 0; + + if (IS_ERR(clk)) + return -EINVAL; + + spin_lock(&clocks_lock); + + if (clk->set_parent) + ret = (clk->set_parent)(clk, parent); + + spin_unlock(&clocks_lock); + + return ret; +} + +EXPORT_SYMBOL(clk_get); +EXPORT_SYMBOL(clk_put); +EXPORT_SYMBOL(clk_enable); +EXPORT_SYMBOL(clk_disable); +EXPORT_SYMBOL(clk_get_rate); +EXPORT_SYMBOL(clk_round_rate); +EXPORT_SYMBOL(clk_set_rate); +EXPORT_SYMBOL(clk_get_parent); +EXPORT_SYMBOL(clk_set_parent); + +/* base clocks */ + +static int clk_default_setrate(struct clk *clk, unsigned long rate) +{ + clk->rate = rate; + return 0; +} + +struct clk clk_xtal = { + .name = "xtal", + .id = -1, + .rate = 0, + .parent = NULL, + .ctrlbit = 0, +}; + +struct clk clk_ext = { + .name = "ext", + .id = -1, +}; + +struct clk clk_epll = { + .name = "epll", + .id = -1, +}; + +struct clk clk_mpll = { + .name = "mpll", + .id = -1, + .set_rate = clk_default_setrate, +}; + +struct clk clk_upll = { + .name = "upll", + .id = -1, + .parent = NULL, + .ctrlbit = 0, +}; + +struct clk clk_f = { + .name = "fclk", + .id = -1, + .rate = 0, + .parent = &clk_mpll, + .ctrlbit = 0, + .set_rate = clk_default_setrate, +}; + +struct clk clk_h = { + .name = "hclk", + .id = -1, + .rate = 0, + .parent = NULL, + .ctrlbit = 0, + .set_rate = clk_default_setrate, +}; + +struct clk clk_p = { + .name = "pclk", + .id = -1, + .rate = 0, + .parent = NULL, + .ctrlbit = 0, + .set_rate = clk_default_setrate, +}; + +struct clk clk_usb_bus = { + .name = "usb-bus", + .id = -1, + .rate = 0, + .parent = &clk_upll, +}; + + + +struct clk s3c24xx_uclk = { + .name = "uclk", + .id = -1, +}; + +/* initialise the clock system */ + +int s3c24xx_register_clock(struct clk *clk) +{ + clk->owner = THIS_MODULE; + + if (clk->enable == NULL) + clk->enable = clk_null_enable; + + /* add to the list of available clocks */ + + /* Quick check to see if this clock has already been registered. */ + BUG_ON(clk->list.prev != clk->list.next); + + spin_lock(&clocks_lock); + list_add(&clk->list, &clocks); + spin_unlock(&clocks_lock); + + return 0; +} + +int s3c24xx_register_clocks(struct clk **clks, int nr_clks) +{ + int fails = 0; + + for (; nr_clks > 0; nr_clks--, clks++) { + if (s3c24xx_register_clock(*clks) < 0) + fails++; + } + + return fails; +} + +/* initalise all the clocks */ + +int __init s3c24xx_register_baseclocks(unsigned long xtal) +{ + printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); + + clk_xtal.rate = xtal; + + /* register our clocks */ + + if (s3c24xx_register_clock(&clk_xtal) < 0) + printk(KERN_ERR "failed to register master xtal\n"); + + if (s3c24xx_register_clock(&clk_mpll) < 0) + printk(KERN_ERR "failed to register mpll clock\n"); + + if (s3c24xx_register_clock(&clk_upll) < 0) + printk(KERN_ERR "failed to register upll clock\n"); + + if (s3c24xx_register_clock(&clk_f) < 0) + printk(KERN_ERR "failed to register cpu fclk\n"); + + if (s3c24xx_register_clock(&clk_h) < 0) + printk(KERN_ERR "failed to register cpu hclk\n"); + + if (s3c24xx_register_clock(&clk_p) < 0) + printk(KERN_ERR "failed to register cpu pclk\n"); + + return 0; +} + diff --git a/arch/arm/plat-s3c/dev-fb.c b/arch/arm/plat-s3c/dev-fb.c new file mode 100644 index 0000000..0454b8e --- /dev/null +++ b/arch/arm/plat-s3c/dev-fb.c @@ -0,0 +1,72 @@ +/* linux/arch/arm/plat-s3c/dev-fb.c + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C series device definition for framebuffer device + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> +#include <linux/fb.h> + +#include <mach/map.h> +#include <mach/regs-fb.h> + +#include <plat/fb.h> +#include <plat/devs.h> +#include <plat/cpu.h> + +static struct resource s3c_fb_resource[] = { + [0] = { + .start = S3C_PA_FB, + .end = S3C_PA_FB + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_LCD_VSYNC, + .end = IRQ_LCD_VSYNC, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_LCD_FIFO, + .end = IRQ_LCD_FIFO, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_LCD_SYSTEM, + .end = IRQ_LCD_SYSTEM, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c_device_fb = { + .name = "s3c-fb", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_fb_resource), + .resource = s3c_fb_resource, + .dev.dma_mask = &s3c_device_fb.dev.coherent_dma_mask, + .dev.coherent_dma_mask = 0xffffffffUL, +}; + +void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd) +{ + struct s3c_fb_platdata *npd; + + if (!pd) { + printk(KERN_ERR "%s: no platform data\n", __func__); + return; + } + + npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + + s3c_device_fb.dev.platform_data = npd; +} diff --git a/arch/arm/plat-s3c/dev-hsmmc.c b/arch/arm/plat-s3c/dev-hsmmc.c new file mode 100644 index 0000000..4c05b39 --- /dev/null +++ b/arch/arm/plat-s3c/dev-hsmmc.c @@ -0,0 +1,68 @@ +/* linux/arch/arm/plat-s3c/dev-hsmmc.c + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C series device definition for hsmmc devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/mmc/host.h> + +#include <mach/map.h> +#include <plat/sdhci.h> +#include <plat/devs.h> +#include <plat/cpu.h> + +#define S3C_SZ_HSMMC (0x1000) + +static struct resource s3c_hsmmc_resource[] = { + [0] = { + .start = S3C_PA_HSMMC0, + .end = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_HSMMC0, + .end = IRQ_HSMMC0, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL; + +struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = { + .max_width = 4, + .host_caps = (MMC_CAP_4_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), +}; + +struct platform_device s3c_device_hsmmc0 = { + .name = "s3c-sdhci", + .id = 0, + .num_resources = ARRAY_SIZE(s3c_hsmmc_resource), + .resource = s3c_hsmmc_resource, + .dev = { + .dma_mask = &s3c_device_hsmmc_dmamask, + .coherent_dma_mask = 0xffffffffUL, + .platform_data = &s3c_hsmmc0_def_platdata, + }, +}; + +void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd) +{ + struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata; + + set->max_width = pd->max_width; + + if (pd->cfg_gpio) + set->cfg_gpio = pd->cfg_gpio; + if (pd->cfg_card) + set->cfg_card = pd->cfg_card; +} diff --git a/arch/arm/plat-s3c/dev-hsmmc1.c b/arch/arm/plat-s3c/dev-hsmmc1.c new file mode 100644 index 0000000..e49bc4c --- /dev/null +++ b/arch/arm/plat-s3c/dev-hsmmc1.c @@ -0,0 +1,68 @@ +/* linux/arch/arm/plat-s3c/dev-hsmmc1.c + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C series device definition for hsmmc device 1 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/mmc/host.h> + +#include <mach/map.h> +#include <plat/sdhci.h> +#include <plat/devs.h> +#include <plat/cpu.h> + +#define S3C_SZ_HSMMC (0x1000) + +static struct resource s3c_hsmmc1_resource[] = { + [0] = { + .start = S3C_PA_HSMMC1, + .end = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_HSMMC1, + .end = IRQ_HSMMC1, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL; + +struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = { + .max_width = 4, + .host_caps = (MMC_CAP_4_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), +}; + +struct platform_device s3c_device_hsmmc1 = { + .name = "s3c-sdhci", + .id = 1, + .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource), + .resource = s3c_hsmmc1_resource, + .dev = { + .dma_mask = &s3c_device_hsmmc1_dmamask, + .coherent_dma_mask = 0xffffffffUL, + .platform_data = &s3c_hsmmc1_def_platdata, + }, +}; + +void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd) +{ + struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata; + + set->max_width = pd->max_width; + + if (pd->cfg_gpio) + set->cfg_gpio = pd->cfg_gpio; + if (pd->cfg_card) + set->cfg_card = pd->cfg_card; +} diff --git a/arch/arm/plat-s3c/dev-i2c0.c b/arch/arm/plat-s3c/dev-i2c0.c new file mode 100644 index 0000000..2c0128c --- /dev/null +++ b/arch/arm/plat-s3c/dev-i2c0.c @@ -0,0 +1,71 @@ +/* linux/arch/arm/plat-s3c/dev-i2c0.c + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C series device definition for i2c device 0 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/map.h> + +#include <plat/regs-iic.h> +#include <plat/iic.h> +#include <plat/devs.h> +#include <plat/cpu.h> + +static struct resource s3c_i2c_resource[] = { + [0] = { + .start = S3C_PA_IIC, + .end = S3C_PA_IIC + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IIC, + .end = IRQ_IIC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c_device_i2c0 = { + .name = "s3c2410-i2c", +#ifdef CONFIG_S3C_DEV_I2C1 + .id = 0, +#else + .id = -1, +#endif + .num_resources = ARRAY_SIZE(s3c_i2c_resource), + .resource = s3c_i2c_resource, +}; + +static struct s3c2410_platform_i2c default_i2c_data0 __initdata = { + .flags = 0, + .slave_addr = 0x10, + .bus_freq = 100*1000, + .max_freq = 400*1000, + .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, +}; + +void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd) +{ + struct s3c2410_platform_i2c *npd; + + if (!pd) + pd = &default_i2c_data0; + + npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + else if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_i2c0_cfg_gpio; + + s3c_device_i2c0.dev.platform_data = npd; +} diff --git a/arch/arm/plat-s3c/dev-i2c1.c b/arch/arm/plat-s3c/dev-i2c1.c new file mode 100644 index 0000000..9658fb0 --- /dev/null +++ b/arch/arm/plat-s3c/dev-i2c1.c @@ -0,0 +1,68 @@ +/* linux/arch/arm/plat-s3c/dev-i2c1.c + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C series device definition for i2c device 1 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/map.h> + +#include <plat/regs-iic.h> +#include <plat/iic.h> +#include <plat/devs.h> +#include <plat/cpu.h> + +static struct resource s3c_i2c_resource[] = { + [0] = { + .start = S3C_PA_IIC1, + .end = S3C_PA_IIC1 + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_IIC1, + .end = IRQ_IIC1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c_device_i2c1 = { + .name = "s3c2410-i2c", + .id = 1, + .num_resources = ARRAY_SIZE(s3c_i2c_resource), + .resource = s3c_i2c_resource, +}; + +static struct s3c2410_platform_i2c default_i2c_data1 __initdata = { + .flags = 0, + .bus_num = 1, + .slave_addr = 0x10, + .bus_freq = 100*1000, + .max_freq = 400*1000, + .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, +}; + +void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd) +{ + struct s3c2410_platform_i2c *npd; + + if (!pd) + pd = &default_i2c_data1; + + npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + else if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_i2c1_cfg_gpio; + + s3c_device_i2c1.dev.platform_data = npd; +} diff --git a/arch/arm/plat-s3c/gpio-config.c b/arch/arm/plat-s3c/gpio-config.c new file mode 100644 index 0000000..7642b97 --- /dev/null +++ b/arch/arm/plat-s3c/gpio-config.c @@ -0,0 +1,163 @@ +/* linux/arch/arm/plat-s3c/gpio-config.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C series GPIO configuration core + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <linux/io.h> + +#include <mach/gpio-core.h> +#include <plat/gpio-cfg.h> +#include <plat/gpio-cfg-helpers.h> + +int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) +{ + struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); + unsigned long flags; + int offset; + int ret; + + if (!chip) + return -EINVAL; + + offset = pin - chip->chip.base; + + local_irq_save(flags); + ret = s3c_gpio_do_setcfg(chip, offset, config); + local_irq_restore(flags); + + return ret; +} + +int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull) +{ + struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); + unsigned long flags; + int offset, ret; + + if (!chip) + return -EINVAL; + + offset = pin - chip->chip.base; + + local_irq_save(flags); + ret = s3c_gpio_do_setpull(chip, offset, pull); + local_irq_restore(flags); + + return ret; +} + +#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX +int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int cfg) +{ + void __iomem *reg = chip->base; + unsigned int shift = off; + u32 con; + + if (s3c_gpio_is_cfg_special(cfg)) { + cfg &= 0xf; + + /* Map output to 0, and SFN2 to 1 */ + cfg -= 1; + if (cfg > 1) + return -EINVAL; + + cfg <<= shift; + } + + con = __raw_readl(reg); + con &= ~(0x1 << shift); + con |= cfg; + __raw_writel(con, reg); + + return 0; +} + +int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int cfg) +{ + void __iomem *reg = chip->base; + unsigned int shift = off * 2; + u32 con; + + if (s3c_gpio_is_cfg_special(cfg)) { + cfg &= 0xf; + if (cfg > 3) + return -EINVAL; + + cfg <<= shift; + } + + con = __raw_readl(reg); + con &= ~(0x3 << shift); + con |= cfg; + __raw_writel(con, reg); + + return 0; +} +#endif + +#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX +int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int cfg) +{ + void __iomem *reg = chip->base; + unsigned int shift = (off & 7) * 4; + u32 con; + + if (off < 8 && chip->chip.ngpio >= 8) + reg -= 4; + + if (s3c_gpio_is_cfg_special(cfg)) { + cfg &= 0xf; + cfg <<= shift; + } + + con = __raw_readl(reg); + con &= ~(0xf << shift); + con |= cfg; + __raw_writel(con, reg); + + return 0; +} +#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */ + +#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN +int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t pull) +{ + void __iomem *reg = chip->base + 0x08; + int shift = off * 2; + u32 pup; + + pup = __raw_readl(reg); + pup &= ~(3 << shift); + pup |= pull << shift; + __raw_writel(pup, reg); + + return 0; +} + +s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, + unsigned int off) +{ + void __iomem *reg = chip->base + 0x08; + int shift = off * 2; + u32 pup = __raw_readl(reg); + + pup >>= shift; + pup &= 0x3; + return (__force s3c_gpio_pull_t)pup; +} +#endif diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-s3c/gpio.c new file mode 100644 index 0000000..d71dd6d --- /dev/null +++ b/arch/arm/plat-s3c/gpio.c @@ -0,0 +1,147 @@ +/* linux/arch/arm/plat-s3c/gpio.c + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C series GPIO core + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/gpio.h> + +#include <plat/gpio-core.h> + +#ifdef CONFIG_S3C_GPIO_TRACK +struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; + +static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip) +{ + unsigned int gpn; + int i; + + gpn = chip->chip.base; + for (i = 0; i < chip->chip.ngpio; i++, gpn++) { + BUG_ON(gpn > ARRAY_SIZE(s3c_gpios)); + s3c_gpios[gpn] = chip; + } +} +#endif /* CONFIG_S3C_GPIO_TRACK */ + +/* Default routines for controlling GPIO, based on the original S3C24XX + * GPIO functions which deal with the case where each gpio bank of the + * chip is as following: + * + * base + 0x00: Control register, 2 bits per gpio + * gpio n: 2 bits starting at (2*n) + * 00 = input, 01 = output, others mean special-function + * base + 0x04: Data register, 1 bit per gpio + * bit n: data bit n +*/ + +static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long flags; + unsigned long con; + + local_irq_save(flags); + + con = __raw_readl(base + 0x00); + con &= ~(3 << (offset * 2)); + + __raw_writel(con, base + 0x00); + + local_irq_restore(flags); + return 0; +} + +static int s3c_gpiolib_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long flags; + unsigned long dat; + unsigned long con; + + local_irq_save(flags); + + dat = __raw_readl(base + 0x04); + dat &= ~(1 << offset); + if (value) + dat |= 1 << offset; + __raw_writel(dat, base + 0x04); + + con = __raw_readl(base + 0x00); + con &= ~(3 << (offset * 2)); + con |= 1 << (offset * 2); + + __raw_writel(con, base + 0x00); + __raw_writel(dat, base + 0x04); + + local_irq_restore(flags); + return 0; +} + +static void s3c_gpiolib_set(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long flags; + unsigned long dat; + + local_irq_save(flags); + + dat = __raw_readl(base + 0x04); + dat &= ~(1 << offset); + if (value) + dat |= 1 << offset; + __raw_writel(dat, base + 0x04); + + local_irq_restore(flags); +} + +static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + unsigned long val; + + val = __raw_readl(ourchip->base + 0x04); + val >>= offset; + val &= 1; + + return val; +} + +__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip) +{ + struct gpio_chip *gc = &chip->chip; + int ret; + + BUG_ON(!chip->base); + BUG_ON(!gc->label); + BUG_ON(!gc->ngpio); + + if (!gc->direction_input) + gc->direction_input = s3c_gpiolib_input; + if (!gc->direction_output) + gc->direction_output = s3c_gpiolib_output; + if (!gc->set) + gc->set = s3c_gpiolib_set; + if (!gc->get) + gc->get = s3c_gpiolib_get; + + /* gpiochip_add() prints own failure message on error. */ + ret = gpiochip_add(gc); + if (ret >= 0) + s3c_gpiolib_track(chip); +} diff --git a/arch/arm/plat-s3c/include/mach/io.h b/arch/arm/plat-s3c/include/mach/io.h new file mode 100644 index 0000000..f6a5363 --- /dev/null +++ b/arch/arm/plat-s3c/include/mach/io.h @@ -0,0 +1,18 @@ +/* arch/arm/plat-s3c/include/mach/io.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben-linux@fluff.org> + * + * Default IO routines for plat-s3c based systems, such as S3C24A0 + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +/* No current ISA/PCI bus support. */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#define IO_SPACE_LIMIT (0xFFFFFFFF) + +#endif diff --git a/arch/arm/mach-s3c2410/include/mach/timex.h b/arch/arm/plat-s3c/include/mach/timex.h index 2a425ed..2a425ed 100644 --- a/arch/arm/mach-s3c2410/include/mach/timex.h +++ b/arch/arm/plat-s3c/include/mach/timex.h diff --git a/arch/arm/mach-s3c2410/include/mach/vmalloc.h b/arch/arm/plat-s3c/include/mach/vmalloc.h index 315b007..bfd2ca6 100644 --- a/arch/arm/mach-s3c2410/include/mach/vmalloc.h +++ b/arch/arm/plat-s3c/include/mach/vmalloc.h @@ -1,4 +1,4 @@ -/* arch/arm/mach-s3c2410/include/mach/vmalloc.h +/* arch/arm/plat-s3c/include/mach/vmalloc.h * * from arch/arm/mach-iop3xx/include/mach/vmalloc.h * diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-s3c/include/plat/adc.h new file mode 100644 index 0000000..43df2a4 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/adc.h @@ -0,0 +1,29 @@ +/* arch/arm/plat-s3c/include/plat/adc.h + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simnte.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24XX ADC driver information + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_ADC_H +#define __ASM_PLAT_ADC_H __FILE__ + +struct s3c_adc_client; + +extern int s3c_adc_start(struct s3c_adc_client *client, + unsigned int channel, unsigned int nr_samples); + +extern struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, + void (*select)(unsigned selected), + void (*conv)(unsigned d0, unsigned d1), + unsigned int is_ts); + +extern void s3c_adc_release(struct s3c_adc_client *client); + +#endif /* __ASM_PLAT_ADC_H */ diff --git a/arch/arm/plat-s3c24xx/include/plat/clock.h b/arch/arm/plat-s3c/include/plat/clock.h index 235b753..a10622e 100644 --- a/arch/arm/plat-s3c24xx/include/plat/clock.h +++ b/arch/arm/plat-s3c/include/plat/clock.h @@ -1,5 +1,4 @@ -/* linux/include/asm-arm/plat-s3c24xx/clock.h - * linux/arch/arm/mach-s3c2410/clock.h +/* linux/arch/arm/plat-s3c/include/plat/clock.h * * Copyright (c) 2004-2005 Simtec Electronics * http://www.simtec.co.uk/products/SWLINUX/ @@ -10,6 +9,8 @@ * published by the Free Software Foundation. */ +#include <linux/spinlock.h> + struct clk { struct list_head list; struct module *owner; @@ -44,21 +45,44 @@ extern struct clk clk_h; extern struct clk clk_p; extern struct clk clk_mpll; extern struct clk clk_upll; +extern struct clk clk_epll; extern struct clk clk_xtal; +extern struct clk clk_ext; + +/* S3C64XX specific clocks */ +extern struct clk clk_27m; +extern struct clk clk_48m; /* exports for arch/arm/mach-s3c2410 * * Please DO NOT use these outside of arch/arm/mach-s3c2410 */ -extern struct mutex clocks_mutex; +extern spinlock_t clocks_lock; extern int s3c2410_clkcon_enable(struct clk *clk, int enable); extern int s3c24xx_register_clock(struct clk *clk); extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); -extern int s3c24xx_setup_clocks(unsigned long xtal, - unsigned long fclk, - unsigned long hclk, - unsigned long pclk); +extern int s3c24xx_register_baseclocks(unsigned long xtal); + +extern void s3c64xx_register_clocks(void); + +extern void s3c24xx_setup_clocks(unsigned long fclk, + unsigned long hclk, + unsigned long pclk); + +extern void s3c2410_setup_clocks(void); +extern void s3c2412_setup_clocks(void); +extern void s3c244x_setup_clocks(void); +extern void s3c2443_setup_clocks(void); + +/* S3C64XX specific functions and clocks */ + +extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable); + +/* Init for pwm clock code */ + +extern void s3c_pwmclk_init(void); + diff --git a/arch/arm/plat-s3c/include/plat/cpu-freq.h b/arch/arm/plat-s3c/include/plat/cpu-freq.h new file mode 100644 index 0000000..c86a133 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/cpu-freq.h @@ -0,0 +1,94 @@ +/* arch/arm/plat-s3c/include/plat/cpu-freq.h + * + * Copyright (c) 2006,2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C CPU frequency scaling support - driver and board + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/cpufreq.h> + +struct s3c_cpufreq_info; +struct s3c_cpufreq_board; +struct s3c_iotimings; + +struct s3c_freq { + unsigned long fclk; + unsigned long armclk; + unsigned long hclk_tns; /* in 10ths of ns */ + unsigned long hclk; + unsigned long pclk; +}; + +/* wrapper 'struct cpufreq_freqs' so that any drivers receiving the + * notification can use this information that is not provided by just + * having the core frequency alone. + */ + +struct s3c_cpufreq_freqs { + struct cpufreq_freqs freqs; + struct s3c_freq old; + struct s3c_freq new; +}; + +#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs) + +struct s3c_clkdivs { + int p_divisor; /* fclk / pclk */ + int h_divisor; /* fclk / hclk */ + int arm_divisor; /* not all cpus have this. */ + unsigned char dvs; /* using dvs mode to arm. */ +}; + +#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s)) + +struct s3c_pllval { + unsigned long freq; + unsigned long pll_reg; +}; + +struct s3c_cpufreq_config { + struct s3c_freq freq; + struct s3c_pllval pll; + struct s3c_clkdivs divs; + struct s3c_cpufreq_info *info; /* for core, not drivers */ + struct s3c_cpufreq_board *board; +}; + +/* s3c_cpufreq_board + * + * per-board configuraton information, such as memory refresh and + * how to initialise IO timings. + */ +struct s3c_cpufreq_board { + unsigned int refresh; /* refresh period in ns */ + unsigned int auto_io:1; /* automatically init io timings. */ + unsigned int need_io:1; /* set if needs io timing support. */ + + /* any non-zero field in here is taken as an upper limit. */ + struct s3c_freq max; /* frequency limits */ +}; + +/* Things depending on frequency scaling. */ +#ifdef CONFIG_CPU_FREQ_S3C +#define __init_or_cpufreq +#else +#define __init_or_cpufreq __init +#endif + +/* Board functions */ + +#ifdef CONFIG_CPU_FREQ_S3C +extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board); +#else + +static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) +{ + return 0; +} +#endif /* CONFIG_CPU_FREQ_S3C */ diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h index 23e420e..e62ae0f 100644 --- a/arch/arm/plat-s3c24xx/include/plat/cpu.h +++ b/arch/arm/plat-s3c/include/plat/cpu.h @@ -1,4 +1,4 @@ -/* linux/include/asm-arm/plat-s3c24xx/cpu.h +/* linux/arch/arm/plat-s3c/include/plat/cpu.h * * Copyright (c) 2004-2005 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> @@ -18,7 +18,7 @@ #define MHZ (1000*1000) #endif -#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000) +#define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000) /* forward declaration */ struct s3c24xx_uart_resources; @@ -26,11 +26,28 @@ struct platform_device; struct s3c2410_uartcfg; struct map_desc; +/* per-cpu initialisation function table. */ + +struct cpu_table { + unsigned long idcode; + unsigned long idmask; + void (*map_io)(void); + void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no); + void (*init_clocks)(int xtal); + int (*init)(void); + const char *name; +}; + +extern void s3c_init_cpu(unsigned long idcode, + struct cpu_table *cpus, unsigned int cputab_size); + /* core initialisation functions */ extern void s3c24xx_init_irq(void); +extern void s3c64xx_init_irq(u32 vic0, u32 vic1); extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); +extern void s3c64xx_init_io(struct map_desc *mach_desc, int size); extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); diff --git a/arch/arm/plat-s3c/include/plat/debug-macro.S b/arch/arm/plat-s3c/include/plat/debug-macro.S index 4aa7e2e..3634d4e 100644 --- a/arch/arm/plat-s3c/include/plat/debug-macro.S +++ b/arch/arm/plat-s3c/include/plat/debug-macro.S @@ -20,7 +20,7 @@ .endm #ifndef fifo_level -#define fifo_level fifo_level_s3c2410 +#define fifo_level fifo_level_s3c2440 #endif .macro fifo_full_s3c2440 rd, rx diff --git a/arch/arm/plat-s3c24xx/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index badaac9..6b1b523 100644 --- a/arch/arm/plat-s3c24xx/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -17,21 +17,26 @@ struct s3c24xx_uart_resources { }; extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; +extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; extern struct platform_device *s3c24xx_uart_devs[]; extern struct platform_device *s3c24xx_uart_src[]; extern struct platform_device s3c_device_timer[]; +extern struct platform_device s3c_device_fb; extern struct platform_device s3c_device_usb; extern struct platform_device s3c_device_lcd; extern struct platform_device s3c_device_wdt; -extern struct platform_device s3c_device_i2c; +extern struct platform_device s3c_device_i2c0; +extern struct platform_device s3c_device_i2c1; extern struct platform_device s3c_device_iis; extern struct platform_device s3c_device_rtc; extern struct platform_device s3c_device_adc; extern struct platform_device s3c_device_sdi; -extern struct platform_device s3c_device_hsmmc; +extern struct platform_device s3c_device_hsmmc0; +extern struct platform_device s3c_device_hsmmc1; +extern struct platform_device s3c_device_hsmmc2; extern struct platform_device s3c_device_spi0; extern struct platform_device s3c_device_spi1; diff --git a/arch/arm/plat-s3c/include/plat/fb.h b/arch/arm/plat-s3c/include/plat/fb.h new file mode 100644 index 0000000..214ff56 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/fb.h @@ -0,0 +1,73 @@ +/* linux/arch/arm/plat-s3c/include/plat/fb.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C - FB platform data definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S3C_FB_H +#define __PLAT_S3C_FB_H __FILE__ + +/** + * struct s3c_fb_pd_win - per window setup data + * @win_mode: The display parameters to initialise (not for window 0) + * @virtual_x: The virtual X size. + * @virtual_y: The virtual Y size. + */ +struct s3c_fb_pd_win { + struct fb_videomode win_mode; + + unsigned short default_bpp; + unsigned short max_bpp; + unsigned short virtual_x; + unsigned short virtual_y; +}; + +/** + * struct s3c_fb_platdata - S3C driver platform specific information + * @setup_gpio: Setup the external GPIO pins to the right state to transfer + * the data from the display system to the connected display + * device. + * @vidcon0: The base vidcon0 values to control the panel data format. + * @vidcon1: The base vidcon1 values to control the panel data output. + * @win: The setup data for each hardware window, or NULL for unused. + * @display_mode: The LCD output display mode. + * + * The platform data supplies the video driver with all the information + * it requires to work with the display(s) attached to the machine. It + * controls the initial mode, the number of display windows (0 is always + * the base framebuffer) that are initialised etc. + * + */ +struct s3c_fb_platdata { + void (*setup_gpio)(void); + + struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN]; + + u32 vidcon0; + u32 vidcon1; +}; + +/** + * s3c_fb_set_platdata() - Setup the FB device with platform data. + * @pd: The platform data to set. The data is copied from the passed structure + * so the machine data can mark the data __initdata so that any unused + * machines will end up dumping their data at runtime. + */ +extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); + +/** + * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD + * + * Initialise the GPIO for an 24bpp LCD display on the RGB interface. + */ +extern void s3c64xx_fb_gpio_setup_24bpp(void); + +#endif /* __PLAT_S3C_FB_H */ diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h new file mode 100644 index 0000000..652e2bb --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h @@ -0,0 +1,176 @@ +/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C Platform - GPIO pin configuration helper definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* This is meant for core cpu support, machine or other driver files + * should not be including this header. + */ + +#ifndef __PLAT_GPIO_CFG_HELPERS_H +#define __PLAT_GPIO_CFG_HELPERS_H __FILE__ + +/* As a note, all gpio configuration functions are entered exclusively, either + * with the relevant lock held or the system prevented from doing anything else + * by disabling interrupts. +*/ + +static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int config) +{ + return (chip->config->set_config)(chip, off, config); +} + +static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t pull) +{ + return (chip->config->set_pull)(chip, off, pull); +} + +/** + * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @cfg: The configuration value to set. + * + * This helper deal with the GPIO cases where the control register + * has two bits of configuration per gpio, which have the following + * functions: + * 00 = input + * 01 = output + * 1x = special function +*/ +extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int cfg); + +/** + * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A) + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @cfg: The configuration value to set. + * + * This helper deal with the GPIO cases where the control register + * has one bit of configuration for the gpio, where setting the bit + * means the pin is in special function mode and unset means output. +*/ +extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int cfg); + +/** + * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @cfg: The configuration value to set. + * + * This helper deal with the GPIO cases where the control register has 4 bits + * of control per GPIO, generally in the form of: + * 0000 = Input + * 0001 = Output + * others = Special functions (dependant on bank) + * + * Note, since the code to deal with the case where there are two control + * registers instead of one, we do not have a seperate set of functions for + * each case. +*/ +extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int cfg); + + +/* Pull-{up,down} resistor controls. + * + * S3C2410,S3C2440,S3C24A0 = Pull-UP, + * S3C2412,S3C2413 = Pull-Down + * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef] + * S3C2443 = Pull-Both [not same as S3C6400] + */ + +/** + * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @param: pull: The pull mode being requested. + * + * This is a helper function for the case where we have GPIOs with one + * bit configuring the presence of a pull-up resistor. + */ +extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t pull); + +/** + * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none + * @chip: The gpio chip that is being configured + * @off: The offset for the GPIO being configured + * @param: pull: The pull mode being requested + * + * This is a helper function for the case where we have GPIOs with one + * bit configuring the presence of a pull-down resistor. + */ +extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t pull); + +/** + * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @param: pull: The pull mode being requested. + * + * This is a helper function for the case where we have GPIOs with two + * bits configuring the presence of a pull resistor, in the following + * order: + * 00 = No pull resistor connected + * 01 = Pull-up resistor connected + * 10 = Pull-down resistor connected + */ +extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t pull); + + +/** + * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none + * @chip: The gpio chip that the GPIO pin belongs to + * @off: The offset to the pin to get the configuration of. + * + * This helper function reads the state of the pull-{up,down} resistor for the + * given GPIO in the same case as s3c_gpio_setpull_upown. +*/ +extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, + unsigned int off); + +/** + * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @param: pull: The pull mode being requested. + * + * This is a helper function for the case where we have GPIOs with two + * bits configuring the presence of a pull resistor, in the following + * order: + * 00 = Pull-up resistor connected + * 10 = Pull-down resistor connected + * x1 = No pull up resistor + */ +extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip, + unsigned int off, s3c_gpio_pull_t pull); + +/** + * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors + * @chip: The gpio chip that the GPIO pin belongs to. + * @off: The offset to the pin to get the configuration of. + * + * This helper function reads the state of the pull-{up,down} resistor for the + * given GPIO in the same case as s3c_gpio_setpull_upown. +*/ +extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip, + unsigned int off); + +#endif /* __PLAT_GPIO_CFG_HELPERS_H */ + diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg.h b/arch/arm/plat-s3c/include/plat/gpio-cfg.h new file mode 100644 index 0000000..29cd6a8 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/gpio-cfg.h @@ -0,0 +1,110 @@ +/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C Platform - GPIO pin configuration + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* This file contains the necessary definitions to get the basic gpio + * pin configuration done such as setting a pin to input or output or + * changing the pull-{up,down} configurations. + */ + +/* Note, this interface is being added to the s3c64xx arch first and will + * be added to the s3c24xx systems later. + */ + +#ifndef __PLAT_GPIO_CFG_H +#define __PLAT_GPIO_CFG_H __FILE__ + +typedef unsigned int __bitwise__ s3c_gpio_pull_t; + +/* forward declaration if gpio-core.h hasn't been included */ +struct s3c_gpio_chip; + +/** + * struct s3c_gpio_cfg GPIO configuration + * @cfg_eint: Configuration setting when used for external interrupt source + * @get_pull: Read the current pull configuration for the GPIO + * @set_pull: Set the current pull configuraiton for the GPIO + * @set_config: Set the current configuration for the GPIO + * @get_config: Read the current configuration for the GPIO + * + * Each chip can have more than one type of GPIO bank available and some + * have different capabilites even when they have the same control register + * layouts. Provide an point to vector control routine and provide any + * per-bank configuration information that other systems such as the + * external interrupt code will need. + */ +struct s3c_gpio_cfg { + unsigned int cfg_eint; + + s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs); + int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs, + s3c_gpio_pull_t pull); + + unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs); + int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs, + unsigned config); +}; + +#define S3C_GPIO_SPECIAL_MARK (0xfffffff0) +#define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x)) + +/* Defines for generic pin configurations */ +#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0)) +#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1)) +#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x)) + +#define s3c_gpio_is_cfg_special(_cfg) \ + (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK) + +/** + * s3c_gpio_cfgpin() - Change the GPIO function of a pin. + * @pin pin The pin number to configure. + * @pin to The configuration for the pin's function. + * + * Configure which function is actually connected to the external + * pin, such as an gpio input, output or some form of special function + * connected to an internal peripheral block. + */ +extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to); + +/* Define values for the pull-{up,down} available for each gpio pin. + * + * These values control the state of the weak pull-{up,down} resistors + * available on most pins on the S3C series. Not all chips support both + * up or down settings, and it may be dependant on the chip that is being + * used to whether the particular mode is available. + */ +#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00) +#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01) +#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02) + +/** + * s3c_gpio_setpull() - set the state of a gpio pin pull resistor + * @pin: The pin number to configure the pull resistor. + * @pull: The configuration for the pull resistor. + * + * This function sets the state of the pull-{up,down} resistor for the + * specified pin. It will return 0 if successfull, or a negative error + * code if the pin cannot support the requested pull setting. +*/ +extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); + +/** + * s3c_gpio_getpull() - get the pull resistor state of a gpio pin + * @pin: The pin number to get the settings for + * + * Read the pull resistor value for the specified pin. +*/ +extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); + +#endif /* __PLAT_GPIO_CFG_H */ diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-s3c/include/plat/gpio-core.h new file mode 100644 index 0000000..2fc60a5 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/gpio-core.h @@ -0,0 +1,77 @@ +/* linux/arch/arm/plat-s3c/include/plat/gpio-core.h + * + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C Platform - GPIO core + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Define the core gpiolib support functions that the s3c platforms may + * need to extend or change depending on the hardware and the s3c chip + * selected at build or found at run time. + * + * These definitions are not intended for driver inclusion, there is + * nothing here that should not live outside the platform and core + * specific code. +*/ + +struct s3c_gpio_cfg; + +/** + * struct s3c_gpio_chip - wrapper for specific implementation of gpio + * @chip: The chip structure to be exported via gpiolib. + * @base: The base pointer to the gpio configuration registers. + * @config: special function and pull-resistor control information. + * + * This wrapper provides the necessary information for the Samsung + * specific gpios being registered with gpiolib. + */ +struct s3c_gpio_chip { + struct gpio_chip chip; + struct s3c_gpio_cfg *config; + void __iomem *base; +}; + +static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) +{ + return container_of(gpc, struct s3c_gpio_chip, chip); +} + +/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip. + * @chip: The chip to register + * + * This is a wrapper to gpiochip_add() that takes our specific gpio chip + * information and makes the necessary alterations for the platform and + * notes the information for use with the configuration systems and any + * other parts of the system. + */ +extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); + +/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios + * for use with the configuration calls, and other parts of the s3c gpiolib + * support code. + * + * Not all s3c support code will need this, as some configurations of cpu + * may only support one or two different configuration options and have an + * easy gpio to s3c_gpio_chip mapping function. If this is the case, then + * the machine support file should provide its own s3c_gpiolib_getchip() + * and any other necessary functions. + */ + +#ifdef CONFIG_S3C_GPIO_TRACK +extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; + +static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) +{ + return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL; +} +#else +/* machine specific code should provide s3c_gpiolib_getchip */ + +static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } +#endif diff --git a/arch/arm/plat-s3c/include/plat/iic-core.h b/arch/arm/plat-s3c/include/plat/iic-core.h new file mode 100644 index 0000000..36397ca --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/iic-core.h @@ -0,0 +1,35 @@ +/* arch/arm/mach-s3c2410/include/mach/iic-core.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C - I2C Controller core functions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_IIC_CORE_H +#define __ASM_ARCH_IIC_CORE_H __FILE__ + +/* These functions are only for use with the core support code, such as + * the cpu specific initialisation code + */ + +/* re-define device name depending on support. */ +static inline void s3c_i2c0_setname(char *name) +{ + /* currently this device is always compiled in */ + s3c_device_i2c0.name = name; +} + +static inline void s3c_i2c1_setname(char *name) +{ +#ifdef CONFIG_S3C_DEV_I2C1 + s3c_device_i2c1.name = name; +#endif +} + +#endif /* __ASM_ARCH_IIC_H */ diff --git a/include/asm-arm/plat-s3c/iic.h b/arch/arm/plat-s3c/include/plat/iic.h index 5106aca..dc1dfcb 100644 --- a/include/asm-arm/plat-s3c/iic.h +++ b/arch/arm/plat-s3c/include/plat/iic.h @@ -28,6 +28,30 @@ struct s3c2410_platform_i2c { unsigned long max_freq; /* max frequency for the bus */ unsigned long min_freq; /* min frequency for the bus */ unsigned int sda_delay; /* pclks (s3c2440 only) */ + + void (*cfg_gpio)(struct platform_device *dev); }; +/** + * s3c_i2c0_set_platdata - set platform data for i2c0 device + * @i2c: The platform data to set, or NULL for default data. + * + * Register the given platform data for use with the i2c0 device. This + * call copies the platform data, so the caller can use __initdata for + * their copy. + * + * This call will set cfg_gpio if is null to the default platform + * implementation. + * + * Any user of s3c_device_i2c0 should call this, even if it is with + * NULL to ensure that the device is given the default platform data + * as the driver will no longer carry defaults. + */ +extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c); +extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c); + +/* defined by architecture to configure gpio */ +extern void s3c_i2c0_cfg_gpio(struct platform_device *dev); +extern void s3c_i2c1_cfg_gpio(struct platform_device *dev); + #endif /* __ASM_ARCH_IIC_H */ diff --git a/arch/arm/plat-s3c/include/plat/map.h b/arch/arm/plat-s3c/include/plat/map-base.h index b84289d..b84289d 100644 --- a/arch/arm/plat-s3c/include/plat/map.h +++ b/arch/arm/plat-s3c/include/plat/map-base.h diff --git a/include/asm-arm/plat-s3c/nand.h b/arch/arm/plat-s3c/include/plat/nand.h index f4dcd14..f4dcd14 100644 --- a/include/asm-arm/plat-s3c/nand.h +++ b/arch/arm/plat-s3c/include/plat/nand.h diff --git a/include/asm-arm/plat-s3c/regs-ac97.h b/arch/arm/plat-s3c/include/plat/regs-ac97.h index c3878f7..c3878f7 100644 --- a/include/asm-arm/plat-s3c/regs-ac97.h +++ b/arch/arm/plat-s3c/include/plat/regs-ac97.h diff --git a/arch/arm/plat-s3c/include/plat/regs-fb.h b/arch/arm/plat-s3c/include/plat/regs-fb.h new file mode 100644 index 0000000..e9ee599 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/regs-fb.h @@ -0,0 +1,366 @@ +/* arch/arm/plat-s3c/include/plat/regs-fb.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C Platform - new-style framebuffer register definitions + * + * This is the register set for the new style framebuffer interface + * found from the S3C2443 onwards into the S3C2416, S3C2450 and the + * S3C64XX series such as the S3C6400 and S3C6410. + * + * The file does not contain the cpu specific items which are based on + * whichever architecture is selected, it only contains the core of the + * register set. See <mach/regs-fb.h> to get the specifics. + * + * Note, we changed to using regs-fb.h as it avoids any clashes with + * the original regs-lcd.h so out of the way of regs-lcd.h as well as + * indicating the newer block is much more than just an LCD interface. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Please do not include this file directly, use <mach/regs-fb.h> to + * ensure all the localised SoC support is included as necessary. +*/ + +/* VIDCON0 */ + +#define VIDCON0 (0x00) +#define VIDCON0_INTERLACE (1 << 29) +#define VIDCON0_VIDOUT_MASK (0x3 << 26) +#define VIDCON0_VIDOUT_SHIFT (26) +#define VIDCON0_VIDOUT_RGB (0x0 << 26) +#define VIDCON0_VIDOUT_TV (0x1 << 26) +#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) +#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) + +#define VIDCON0_L1_DATA_MASK (0x7 << 23) +#define VIDCON0_L1_DATA_SHIFT (23) +#define VIDCON0_L1_DATA_16BPP (0x0 << 23) +#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23) +#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23) +#define VIDCON0_L1_DATA_24BPP (0x3 << 23) +#define VIDCON0_L1_DATA_18BPP (0x4 << 23) +#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23) + +#define VIDCON0_L0_DATA_MASK (0x7 << 20) +#define VIDCON0_L0_DATA_SHIFT (20) +#define VIDCON0_L0_DATA_16BPP (0x0 << 20) +#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20) +#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20) +#define VIDCON0_L0_DATA_24BPP (0x3 << 20) +#define VIDCON0_L0_DATA_18BPP (0x4 << 20) +#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20) + +#define VIDCON0_PNRMODE_MASK (0x3 << 17) +#define VIDCON0_PNRMODE_SHIFT (17) +#define VIDCON0_PNRMODE_RGB (0x0 << 17) +#define VIDCON0_PNRMODE_BGR (0x1 << 17) +#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17) +#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17) + +#define VIDCON0_CLKVALUP (1 << 16) +#define VIDCON0_CLKVAL_F_MASK (0xff << 6) +#define VIDCON0_CLKVAL_F_SHIFT (6) +#define VIDCON0_CLKVAL_F_LIMIT (0xff) +#define VIDCON0_CLKVAL_F(_x) ((_x) << 6) +#define VIDCON0_VLCKFREE (1 << 5) +#define VIDCON0_CLKDIR (1 << 4) + +#define VIDCON0_CLKSEL_MASK (0x3 << 2) +#define VIDCON0_CLKSEL_SHIFT (2) +#define VIDCON0_CLKSEL_HCLK (0x0 << 2) +#define VIDCON0_CLKSEL_LCD (0x1 << 2) +#define VIDCON0_CLKSEL_27M (0x3 << 2) + +#define VIDCON0_ENVID (1 << 1) +#define VIDCON0_ENVID_F (1 << 0) + +#define VIDCON1 (0x04) +#define VIDCON1_LINECNT_MASK (0x7ff << 16) +#define VIDCON1_LINECNT_SHIFT (16) +#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) +#define VIDCON1_VSTATUS_MASK (0x3 << 13) +#define VIDCON1_VSTATUS_SHIFT (13) +#define VIDCON1_VSTATUS_VSYNC (0x0 << 13) +#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13) +#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13) +#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13) + +#define VIDCON1_INV_VCLK (1 << 7) +#define VIDCON1_INV_HSYNC (1 << 6) +#define VIDCON1_INV_VSYNC (1 << 5) +#define VIDCON1_INV_VDEN (1 << 4) + +/* VIDCON2 */ + +#define VIDCON2 (0x08) +#define VIDCON2_EN601 (1 << 23) +#define VIDCON2_TVFMTSEL_SW (1 << 14) + +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12) +#define VIDCON2_TVFMTSEL1_SHIFT (12) +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) + +#define VIDCON2_ORGYCbCr (1 << 8) +#define VIDCON2_YUVORDCrCb (1 << 7) + +/* VIDTCON0 */ + +#define VIDTCON0_VBPDE_MASK (0xff << 24) +#define VIDTCON0_VBPDE_SHIFT (24) +#define VIDTCON0_VBPDE_LIMIT (0xff) +#define VIDTCON0_VBPDE(_x) ((_x) << 24) + +#define VIDTCON0_VBPD_MASK (0xff << 16) +#define VIDTCON0_VBPD_SHIFT (16) +#define VIDTCON0_VBPD_LIMIT (0xff) +#define VIDTCON0_VBPD(_x) ((_x) << 16) + +#define VIDTCON0_VFPD_MASK (0xff << 8) +#define VIDTCON0_VFPD_SHIFT (8) +#define VIDTCON0_VFPD_LIMIT (0xff) +#define VIDTCON0_VFPD(_x) ((_x) << 8) + +#define VIDTCON0_VSPW_MASK (0xff << 0) +#define VIDTCON0_VSPW_SHIFT (0) +#define VIDTCON0_VSPW_LIMIT (0xff) +#define VIDTCON0_VSPW(_x) ((_x) << 0) + +/* VIDTCON1 */ + +#define VIDTCON1_VFPDE_MASK (0xff << 24) +#define VIDTCON1_VFPDE_SHIFT (24) +#define VIDTCON1_VFPDE_LIMIT (0xff) +#define VIDTCON1_VFPDE(_x) ((_x) << 24) + +#define VIDTCON1_HBPD_MASK (0xff << 16) +#define VIDTCON1_HBPD_SHIFT (16) +#define VIDTCON1_HBPD_LIMIT (0xff) +#define VIDTCON1_HBPD(_x) ((_x) << 16) + +#define VIDTCON1_HFPD_MASK (0xff << 8) +#define VIDTCON1_HFPD_SHIFT (8) +#define VIDTCON1_HFPD_LIMIT (0xff) +#define VIDTCON1_HFPD(_x) ((_x) << 8) + +#define VIDTCON1_HSPW_MASK (0xff << 0) +#define VIDTCON1_HSPW_SHIFT (0) +#define VIDTCON1_HSPW_LIMIT (0xff) +#define VIDTCON1_HSPW(_x) ((_x) << 0) + +#define VIDTCON2 (0x18) +#define VIDTCON2_LINEVAL_MASK (0x7ff << 11) +#define VIDTCON2_LINEVAL_SHIFT (11) +#define VIDTCON2_LINEVAL_LIMIT (0x7ff) +#define VIDTCON2_LINEVAL(_x) ((_x) << 11) + +#define VIDTCON2_HOZVAL_MASK (0x7ff << 0) +#define VIDTCON2_HOZVAL_SHIFT (0) +#define VIDTCON2_HOZVAL_LIMIT (0x7ff) +#define VIDTCON2_HOZVAL(_x) ((_x) << 0) + +/* WINCONx */ + + +#define WINCONx_BITSWP (1 << 18) +#define WINCONx_BYTSWP (1 << 17) +#define WINCONx_HAWSWP (1 << 16) +#define WINCONx_BURSTLEN_MASK (0x3 << 9) +#define WINCONx_BURSTLEN_SHIFT (9) +#define WINCONx_BURSTLEN_16WORD (0x0 << 9) +#define WINCONx_BURSTLEN_8WORD (0x1 << 9) +#define WINCONx_BURSTLEN_4WORD (0x2 << 9) + +#define WINCONx_ENWIN (1 << 0) +#define WINCON0_BPPMODE_MASK (0xf << 2) +#define WINCON0_BPPMODE_SHIFT (2) +#define WINCON0_BPPMODE_1BPP (0x0 << 2) +#define WINCON0_BPPMODE_2BPP (0x1 << 2) +#define WINCON0_BPPMODE_4BPP (0x2 << 2) +#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2) +#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2) +#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2) +#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2) +#define WINCON0_BPPMODE_24BPP_888 (0xb << 2) + +#define WINCON1_BLD_PIX (1 << 6) + +#define WINCON1_ALPHA_SEL (1 << 1) +#define WINCON1_BPPMODE_MASK (0xf << 2) +#define WINCON1_BPPMODE_SHIFT (2) +#define WINCON1_BPPMODE_1BPP (0x0 << 2) +#define WINCON1_BPPMODE_2BPP (0x1 << 2) +#define WINCON1_BPPMODE_4BPP (0x2 << 2) +#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2) +#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2) +#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2) +#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2) +#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2) +#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2) +#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2) +#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2) +#define WINCON1_BPPMODE_24BPP_888 (0xb << 2) +#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2) +#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2) +#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2) + + +#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) +#define VIDOSDxA_TOPLEFT_X_SHIFT (11) +#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff) +#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11) + +#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0) +#define VIDOSDxA_TOPLEFT_Y_SHIFT (0) +#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff) +#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0) + +#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11) +#define VIDOSDxB_BOTRIGHT_X_SHIFT (11) +#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff) +#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11) + +#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0) +#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0) +#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff) +#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0) + +/* For VIDOSD[1..4]C */ +#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20) +#define VIDISD14C_ALPHA0_G_MASK (0xf << 16) +#define VIDISD14C_ALPHA0_G_SHIFT (16) +#define VIDISD14C_ALPHA0_G_LIMIT (0xf) +#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16) +#define VIDISD14C_ALPHA0_B_MASK (0xf << 12) +#define VIDISD14C_ALPHA0_B_SHIFT (12) +#define VIDISD14C_ALPHA0_B_LIMIT (0xf) +#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12) +#define VIDISD14C_ALPHA1_R_MASK (0xf << 8) +#define VIDISD14C_ALPHA1_R_SHIFT (8) +#define VIDISD14C_ALPHA1_R_LIMIT (0xf) +#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8) +#define VIDISD14C_ALPHA1_G_MASK (0xf << 4) +#define VIDISD14C_ALPHA1_G_SHIFT (4) +#define VIDISD14C_ALPHA1_G_LIMIT (0xf) +#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4) +#define VIDISD14C_ALPHA1_B_MASK (0xf << 0) +#define VIDISD14C_ALPHA1_B_SHIFT (0) +#define VIDISD14C_ALPHA1_B_LIMIT (0xf) +#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0) + +/* Video buffer addresses */ +#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8)) +#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8)) +#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8)) +#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) +#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) + +#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13) +#define VIDW_BUF_SIZE_OFFSET_SHIFT (13) +#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff) +#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13) + +#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0) +#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0) +#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff) +#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0) + +/* Interrupt controls and status */ + +#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20) +#define VIDINTCON0_FIFOINTERVAL_SHIFT (20) +#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f) +#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20) + +#define VIDINTCON0_INT_SYSMAINCON (1 << 19) +#define VIDINTCON0_INT_SYSSUBCON (1 << 18) +#define VIDINTCON0_INT_I80IFDONE (1 << 17) + +#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15) +#define VIDINTCON0_FRAMESEL0_SHIFT (15) +#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15) +#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15) +#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15) +#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15) + +#define VIDINTCON0_FRAMESEL1 (1 << 14) +#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 14) +#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 14) +#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 14) +#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 14) + +#define VIDINTCON0_INT_FRAME (1 << 12) +#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5) +#define VIDINTCON0_FIFIOSEL_SHIFT (5) +#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5) +#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5) + +#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2) +#define VIDINTCON0_FIFOLEVEL_SHIFT (2) +#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2) +#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2) +#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2) +#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2) +#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2) + +#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0) +#define VIDINTCON0_INT_FIFO_SHIFT (0) +#define VIDINTCON0_INT_ENABLE (1 << 0) + +#define VIDINTCON1 (0x134) +#define VIDINTCON1_INT_I180 (1 << 2) +#define VIDINTCON1_INT_FRAME (1 << 1) +#define VIDINTCON1_INT_FIFO (1 << 0) + +/* Window colour-key control registers */ + +#define WxKEYCON0_KEYBL_EN (1 << 26) +#define WxKEYCON0_KEYEN_F (1 << 25) +#define WxKEYCON0_DIRCON (1 << 24) +#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0) +#define WxKEYCON0_COMPKEY_SHIFT (0) +#define WxKEYCON0_COMPKEY_LIMIT (0xffffff) +#define WxKEYCON0_COMPKEY(_x) ((_x) << 0) +#define WxKEYCON1_COLVAL_MASK (0xffffff << 0) +#define WxKEYCON1_COLVAL_SHIFT (0) +#define WxKEYCON1_COLVAL_LIMIT (0xffffff) +#define WxKEYCON1_COLVAL(_x) ((_x) << 0) + + +/* Window blanking (MAP) */ + +#define WINxMAP_MAP (1 << 24) +#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) +#define WINxMAP_MAP_COLOUR_SHIFT (0) +#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff) +#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) + +#define WPALCON_PAL_UPDATE (1 << 9) +#define WPALCON_W1PAL_MASK (0x7 << 3) +#define WPALCON_W1PAL_SHIFT (3) +#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3) +#define WPALCON_W1PAL_24BPP (0x1 << 3) +#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3) +#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3) +#define WPALCON_W1PAL_18BPP (0x4 << 3) +#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3) +#define WPALCON_W1PAL_16BPP_565 (0x6 << 3) + +#define WPALCON_W0PAL_MASK (0x7 << 0) +#define WPALCON_W0PAL_SHIFT (0) +#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0) +#define WPALCON_W0PAL_24BPP (0x1 << 0) +#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0) +#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0) +#define WPALCON_W0PAL_18BPP (0x4 << 0) +#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0) +#define WPALCON_W0PAL_16BPP_565 (0x6 << 0) + diff --git a/include/asm-arm/plat-s3c/regs-iic.h b/arch/arm/plat-s3c/include/plat/regs-iic.h index 2f7c17d..2f7c17d 100644 --- a/include/asm-arm/plat-s3c/regs-iic.h +++ b/arch/arm/plat-s3c/include/plat/regs-iic.h diff --git a/arch/arm/plat-s3c/include/plat/regs-irqtype.h b/arch/arm/plat-s3c/include/plat/regs-irqtype.h new file mode 100644 index 0000000..c63cd3f --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/regs-irqtype.h @@ -0,0 +1,21 @@ +/* arch/arm/plat-s3c/include/plat/regs-irqtype.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C - IRQ detection types. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* values for S3C2410_EXTINT0/1/2 and other cpus in the series, including + * the S3C64XX +*/ +#define S3C2410_EXTINT_LOWLEV (0x00) +#define S3C2410_EXTINT_HILEV (0x01) +#define S3C2410_EXTINT_FALLEDGE (0x02) +#define S3C2410_EXTINT_RISEEDGE (0x04) +#define S3C2410_EXTINT_BOTHEDGE (0x06) diff --git a/include/asm-arm/plat-s3c/regs-nand.h b/arch/arm/plat-s3c/include/plat/regs-nand.h index b2caa4b..b2caa4b 100644 --- a/include/asm-arm/plat-s3c/regs-nand.h +++ b/arch/arm/plat-s3c/include/plat/regs-nand.h diff --git a/include/asm-arm/plat-s3c/regs-rtc.h b/arch/arm/plat-s3c/include/plat/regs-rtc.h index d5837cf..d5837cf 100644 --- a/include/asm-arm/plat-s3c/regs-rtc.h +++ b/arch/arm/plat-s3c/include/plat/regs-rtc.h diff --git a/arch/arm/plat-s3c/include/plat/regs-sdhci.h b/arch/arm/plat-s3c/include/plat/regs-sdhci.h new file mode 100644 index 0000000..e34049ad --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/regs-sdhci.h @@ -0,0 +1,87 @@ +/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C Platform - SDHCI (HSMMC) register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S3C_SDHCI_REGS_H +#define __PLAT_S3C_SDHCI_REGS_H __FILE__ + +#define S3C_SDHCI_CONTROL2 (0x80) +#define S3C_SDHCI_CONTROL3 (0x84) +#define S3C64XX_SDHCI_CONTROL4 (0x8C) + +#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) +#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) +#define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29) +#define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28) + +#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) +#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) +#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) + +#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) +#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16) +#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) + +#define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15) +#define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14) +#define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13) +#define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12) +#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) + +#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9) +#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9) +#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9) +#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9) +#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9) +#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9) + +#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) +#define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7) +#define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6) +#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4) +#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4) +#define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3) +#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) +#define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0) + +#define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31) +#define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23) +#define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15) +#define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7) + +#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24) +#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24) +#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24) + +#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16) +#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16) +#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16) + +#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8) +#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8) +#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8) + +#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0) +#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0) +#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0) + +#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16) +#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16) +#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16) +#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16) +#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16) +#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16) + +#define S3C64XX_SDHCI_CONTROL4_BUSY (1) + +#endif /* __PLAT_S3C_SDHCI_REGS_H */ diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h index a0daa64..487d7d2 100644 --- a/arch/arm/plat-s3c/include/plat/regs-serial.h +++ b/arch/arm/plat-s3c/include/plat/regs-serial.h @@ -77,6 +77,12 @@ #define S3C2440_UCON_FCLK (3<<10) #define S3C2443_UCON_EPLL (3<<10) +#define S3C6400_UCON_CLKMASK (3<<10) +#define S3C6400_UCON_PCLK (0<<10) +#define S3C6400_UCON_PCLK2 (2<<10) +#define S3C6400_UCON_UCLK0 (1<<10) +#define S3C6400_UCON_UCLK1 (3<<10) + #define S3C2440_UCON2_FCLK_EN (1<<15) #define S3C2440_UCON0_DIVMASK (15 << 12) #define S3C2440_UCON1_DIVMASK (15 << 12) @@ -149,6 +155,14 @@ #define S3C2410_UFSTAT_RXMASK (15<<0) #define S3C2410_UFSTAT_RXSHIFT (0) +/* UFSTAT S3C24A0 */ +#define S3C24A0_UFSTAT_TXFULL (1 << 14) +#define S3C24A0_UFSTAT_RXFULL (1 << 6) +#define S3C24A0_UFSTAT_TXMASK (63 << 8) +#define S3C24A0_UFSTAT_TXSHIFT (8) +#define S3C24A0_UFSTAT_RXMASK (63) +#define S3C24A0_UFSTAT_RXSHIFT (0) + /* UFSTAT S3C2443 same as S3C2440 */ #define S3C2440_UFSTAT_TXFULL (1<<14) #define S3C2440_UFSTAT_RXFULL (1<<6) @@ -224,7 +238,7 @@ struct s3c2410_uartcfg { * or platform_add_device() before the console_initcall() */ -extern struct platform_device *s3c24xx_uart_devs[3]; +extern struct platform_device *s3c24xx_uart_devs[4]; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/plat-s3c/include/plat/regs-timer.h b/arch/arm/plat-s3c/include/plat/regs-timer.h index cc0eedd..d097d92 100644 --- a/arch/arm/plat-s3c/include/plat/regs-timer.h +++ b/arch/arm/plat-s3c/include/plat/regs-timer.h @@ -10,7 +10,6 @@ * S3C2410 Timer configuration */ - #ifndef __ASM_ARCH_REGS_TIMER_H #define __ASM_ARCH_REGS_TIMER_H @@ -21,6 +20,8 @@ #define S3C2410_TCFG1 S3C_TIMERREG(0x04) #define S3C2410_TCON S3C_TIMERREG(0x08) +#define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44) + #define S3C2410_TCFG_PRESCALER0_MASK (255<<0) #define S3C2410_TCFG_PRESCALER1_MASK (255<<8) #define S3C2410_TCFG_PRESCALER1_SHIFT (8) @@ -72,6 +73,14 @@ #define S3C2410_TCFG1_MUX_TCLK (4<<0) #define S3C2410_TCFG1_MUX_MASK (15<<0) +#define S3C64XX_TCFG1_MUX_DIV1 (0<<0) +#define S3C64XX_TCFG1_MUX_DIV2 (1<<0) +#define S3C64XX_TCFG1_MUX_DIV4 (2<<0) +#define S3C64XX_TCFG1_MUX_DIV8 (3<<0) +#define S3C64XX_TCFG1_MUX_DIV16 (4<<0) +#define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */ +#define S3C64XX_TCFG1_MUX_MASK (15<<0) + #define S3C2410_TCFG1_SHIFT(x) ((x) * 4) /* for each timer, we have an count buffer, an compare buffer and diff --git a/include/asm-arm/plat-s3c/regs-watchdog.h b/arch/arm/plat-s3c/include/plat/regs-watchdog.h index 4938492..4938492 100644 --- a/include/asm-arm/plat-s3c/regs-watchdog.h +++ b/arch/arm/plat-s3c/include/plat/regs-watchdog.h diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h new file mode 100644 index 0000000..c4ca392 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/sdhci.h @@ -0,0 +1,108 @@ +/* linux/arch/arm/plat-s3c/include/plat/sdhci.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C Platform - SDHCI (HSMMC) platform data definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S3C_SDHCI_H +#define __PLAT_S3C_SDHCI_H __FILE__ + +struct platform_device; +struct mmc_host; +struct mmc_card; +struct mmc_ios; + +/** + * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI + * @max_width: The maximum number of data bits supported. + * @host_caps: Standard MMC host capabilities bit field. + * @cfg_gpio: Configure the GPIO for a specific card bit-width + * @cfg_card: Configure the interface for a specific card and speed. This + * is necessary the controllers and/or GPIO blocks require the + * changing of driver-strength and other controls dependant on + * the card and speed of operation. + * + * Initialisation data specific to either the machine or the platform + * for the device driver to use or call-back when configuring gpio or + * card speed information. +*/ +struct s3c_sdhci_platdata { + unsigned int max_width; + unsigned int host_caps; + + char **clocks; /* set of clock sources */ + + void (*cfg_gpio)(struct platform_device *dev, int width); + void (*cfg_card)(struct platform_device *dev, + void __iomem *regbase, + struct mmc_ios *ios, + struct mmc_card *card); +}; + +/** + * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device. + * @pd: Platform data to register to device. + * + * Register the given platform data for use withe S3C SDHCI device. + * The call will copy the platform data, so the board definitions can + * make the structure itself __initdata. + */ +extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd); +extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd); + +/* Default platform data, exported so that per-cpu initialisation can + * set the correct one when there are more than one cpu type selected. +*/ + +extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata; +extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; + +/* Helper function availablity */ + +#ifdef CONFIG_S3C6410_SETUP_SDHCI +extern char *s3c6410_hsmmc_clksrcs[4]; + +extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w); +extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w); + +extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card); + +#ifdef CONFIG_S3C_DEV_HSMMC +static inline void s3c6410_default_sdhci0(void) +{ + s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs; + s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio; + s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; +} +#else +static inline void s3c6410_default_sdhci0(void) { } +#endif /* CONFIG_S3C_DEV_HSMMC */ + +#ifdef CONFIG_S3C_DEV_HSMMC1 +static inline void s3c6410_default_sdhci1(void) +{ + s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs; + s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio; + s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; +} +#else +static inline void s3c6410_default_sdhci1(void) { } +#endif /* CONFIG_S3C_DEV_HSMMC1 */ + +#else +static inline void s3c6410_default_sdhci0(void) { } +static inline void s3c6410_default_sdhci1(void) { } +#endif /* CONFIG_S3C6410_SETUP_SDHCI */ + +#endif /* __PLAT_S3C_SDHCI_H */ diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h index 4df006b..6061de8 100644 --- a/arch/arm/plat-s3c/include/plat/uncompress.h +++ b/arch/arm/plat-s3c/include/plat/uncompress.h @@ -28,7 +28,7 @@ static void arch_detect_cpu(void); /* defines for UART registers */ #include <plat/regs-serial.h> -#include <asm/plat-s3c/regs-watchdog.h> +#include <plat/regs-watchdog.h> /* working in physical space... */ #undef S3C2410_WDOGREG @@ -37,7 +37,7 @@ static void arch_detect_cpu(void); /* how many bytes we allow into the FIFO at a time in FIFO mode */ #define FIFO_MAX (14) -#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT) +#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT) static __inline__ void uart_wr(unsigned int reg, unsigned int val) @@ -139,6 +139,28 @@ static void arch_decomp_error(const char *x) static void error(char *err); +#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO +static inline void arch_enable_uart_fifo(void) +{ + u32 fifocon = uart_rd(S3C2410_UFCON); + + if (!(fifocon & S3C2410_UFCON_FIFOMODE)) { + fifocon |= S3C2410_UFCON_RESETBOTH; + uart_wr(S3C2410_UFCON, fifocon); + + /* wait for fifo reset to complete */ + while (1) { + fifocon = uart_rd(S3C2410_UFCON); + if (!(fifocon & S3C2410_UFCON_RESETBOTH)) + break; + } + } +} +#else +#define arch_enable_uart_fifo() do { } while(0) +#endif + + static void arch_decomp_setup(void) { @@ -149,6 +171,12 @@ arch_decomp_setup(void) arch_detect_cpu(); arch_decomp_wdog_start(); + + /* Enable the UART FIFOs if they where not enabled and our + * configuration says we should turn them on. + */ + + arch_enable_uart_fifo(); } diff --git a/arch/arm/plat-s3c/init.c b/arch/arm/plat-s3c/init.c new file mode 100644 index 0000000..6790edf --- /dev/null +++ b/arch/arm/plat-s3c/init.c @@ -0,0 +1,160 @@ +/* linux/arch/arm/plat-s3c/init.c + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C series CPU initialisation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> + +#include <mach/hardware.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/clock.h> + +#include <plat/regs-serial.h> + +static struct cpu_table *cpu; + +static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode, + struct cpu_table *tab, + unsigned int count) +{ + for (; count != 0; count--, tab++) { + if ((idcode & tab->idmask) == tab->idcode) + return tab; + } + + return NULL; +} + +void __init s3c_init_cpu(unsigned long idcode, + struct cpu_table *cputab, unsigned int cputab_size) +{ + cpu = s3c_lookup_cpu(idcode, cputab, cputab_size); + + if (cpu == NULL) { + printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); + panic("Unknown S3C24XX CPU"); + } + + printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode); + + if (cpu->map_io == NULL || cpu->init == NULL) { + printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); + panic("Unsupported Samsung CPU"); + } + + cpu->map_io(); +} + +/* s3c24xx_init_clocks + * + * Initialise the clock subsystem and associated information from the + * given master crystal value. + * + * xtal = 0 -> use default PLL crystal value (normally 12MHz) + * != 0 -> PLL crystal value in Hz +*/ + +void __init s3c24xx_init_clocks(int xtal) +{ + if (xtal == 0) + xtal = 12*1000*1000; + + if (cpu == NULL) + panic("s3c24xx_init_clocks: no cpu setup?\n"); + + if (cpu->init_clocks == NULL) + panic("s3c24xx_init_clocks: cpu has no clock init\n"); + else + (cpu->init_clocks)(xtal); +} + +/* uart management */ + +static int nr_uarts __initdata = 0; + +static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS]; + +/* s3c24xx_init_uartdevs + * + * copy the specified platform data and configuration into our central + * set of devices, before the data is thrown away after the init process. + * + * This also fills in the array passed to the serial driver for the + * early initialisation of the console. +*/ + +void __init s3c24xx_init_uartdevs(char *name, + struct s3c24xx_uart_resources *res, + struct s3c2410_uartcfg *cfg, int no) +{ + struct platform_device *platdev; + struct s3c2410_uartcfg *cfgptr = uart_cfgs; + struct s3c24xx_uart_resources *resp; + int uart; + + memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no); + + for (uart = 0; uart < no; uart++, cfg++, cfgptr++) { + platdev = s3c24xx_uart_src[cfgptr->hwport]; + + resp = res + cfgptr->hwport; + + s3c24xx_uart_devs[uart] = platdev; + + platdev->name = name; + platdev->resource = resp->resources; + platdev->num_resources = resp->nr_resources; + + platdev->dev.platform_data = cfgptr; + } + + nr_uarts = no; +} + +void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + if (cpu == NULL) + return; + + if (cpu->init_uarts == NULL) { + printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); + } else + (cpu->init_uarts)(cfg, no); +} + +static int __init s3c_arch_init(void) +{ + int ret; + + // do the correct init for cpu + + if (cpu == NULL) + panic("s3c_arch_init: NULL cpu\n"); + + ret = (cpu->init)(); + if (ret != 0) + return ret; + + ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); + return ret; +} + +arch_initcall(s3c_arch_init); diff --git a/arch/arm/plat-s3c24xx/pwm-clock.c b/arch/arm/plat-s3c/pwm-clock.c index 3fad68a..a318215 100644 --- a/arch/arm/plat-s3c24xx/pwm-clock.c +++ b/arch/arm/plat-s3c/pwm-clock.c @@ -14,20 +14,20 @@ #include <linux/kernel.h> #include <linux/list.h> #include <linux/errno.h> +#include <linux/log2.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> #include <mach/hardware.h> +#include <mach/map.h> #include <asm/irq.h> -#include <mach/regs-clock.h> -#include <mach/regs-gpio.h> - #include <plat/clock.h> #include <plat/cpu.h> #include <plat/regs-timer.h> +#include <mach/pwm-clock.h> /* Each of the timers 0 through 5 go through the following * clock tree, with the inputs depending on the timers. @@ -73,11 +73,13 @@ * tclk -------------------------/ */ -static unsigned long clk_pwm_scaler_getrate(struct clk *clk) +static struct clk clk_timer_scaler[]; + +static unsigned long clk_pwm_scaler_get_rate(struct clk *clk) { unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0); - if (clk->id == 1) { + if (clk == &clk_timer_scaler[1]) { tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK; tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT; } else { @@ -87,18 +89,61 @@ static unsigned long clk_pwm_scaler_getrate(struct clk *clk) return clk_get_rate(clk->parent) / (tcfg0 + 1); } -/* TODO - add set rate calls. */ +static unsigned long clk_pwm_scaler_round_rate(struct clk *clk, + unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + unsigned long divisor = parent_rate / rate; + + if (divisor > 256) + divisor = 256; + else if (divisor < 2) + divisor = 2; + + return parent_rate / divisor; +} + +static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long round = clk_pwm_scaler_round_rate(clk, rate); + unsigned long tcfg0; + unsigned long divisor; + unsigned long flags; + + divisor = clk_get_rate(clk->parent) / round; + divisor--; + + local_irq_save(flags); + tcfg0 = __raw_readl(S3C2410_TCFG0); + + if (clk == &clk_timer_scaler[1]) { + tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK; + tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT; + } else { + tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK; + tcfg0 |= divisor; + } + + __raw_writel(tcfg0, S3C2410_TCFG0); + local_irq_restore(flags); + + return 0; +} static struct clk clk_timer_scaler[] = { [0] = { .name = "pwm-scaler0", .id = -1, - .get_rate = clk_pwm_scaler_getrate, + .get_rate = clk_pwm_scaler_get_rate, + .set_rate = clk_pwm_scaler_set_rate, + .round_rate = clk_pwm_scaler_round_rate, }, [1] = { .name = "pwm-scaler1", .id = -1, - .get_rate = clk_pwm_scaler_getrate, + .get_rate = clk_pwm_scaler_get_rate, + .set_rate = clk_pwm_scaler_set_rate, + .round_rate = clk_pwm_scaler_round_rate, }, }; @@ -123,11 +168,6 @@ static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk) return container_of(clk, struct pwm_tdiv_clk, clk); } -static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) -{ - return 1 << (1 + tcfg1); -} - static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk) { unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); @@ -136,7 +176,7 @@ static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk) tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); tcfg1 &= S3C2410_TCFG1_MUX_MASK; - if (tcfg1 == S3C2410_TCFG1_MUX_TCLK) + if (pwm_cfg_src_is_tclk(tcfg1)) divisor = to_tdiv(clk)->divisor; else divisor = tcfg_to_divisor(tcfg1); @@ -153,7 +193,9 @@ static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk, parent_rate = clk_get_rate(clk->parent); divisor = parent_rate / rate; - if (divisor <= 2) + if (divisor <= 1 && pwm_tdiv_has_div1()) + divisor = 1; + else if (divisor <= 2) divisor = 2; else if (divisor <= 4) divisor = 4; @@ -167,25 +209,7 @@ static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk, static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk) { - unsigned long bits; - - switch (divclk->divisor) { - case 2: - bits = S3C2410_TCFG1_MUX_DIV2; - break; - case 4: - bits = S3C2410_TCFG1_MUX_DIV4; - break; - case 8: - bits = S3C2410_TCFG1_MUX_DIV8; - break; - case 16: - default: - bits = S3C2410_TCFG1_MUX_DIV16; - break; - } - - return bits; + return pwm_tdiv_div_bits(divclk->divisor); } static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk) @@ -226,7 +250,7 @@ static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate) /* Update the current MUX settings if we are currently * selected as the clock source for this clock. */ - if (tcfg1 != S3C2410_TCFG1_MUX_TCLK) + if (!pwm_cfg_src_is_tclk(tcfg1)) clk_pwm_tdiv_update(divclk); return 0; @@ -313,7 +337,7 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent) unsigned long shift = S3C2410_TCFG1_SHIFT(id); if (parent == s3c24xx_pwmclk_tclk(id)) - bits = S3C2410_TCFG1_MUX_TCLK << shift; + bits = S3C_TCFG1_MUX_TCLK << shift; else if (parent == s3c24xx_pwmclk_tdiv(id)) bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift; else @@ -375,7 +399,7 @@ static __init int clk_pwm_tin_register(struct clk *pwm) tcfg1 >>= S3C2410_TCFG1_SHIFT(id); tcfg1 &= S3C2410_TCFG1_MUX_MASK; - if (tcfg1 == S3C2410_TCFG1_MUX_TCLK) + if (pwm_cfg_src_is_tclk(tcfg1)) parent = s3c24xx_pwmclk_tclk(id); else parent = s3c24xx_pwmclk_tdiv(id); @@ -383,7 +407,16 @@ static __init int clk_pwm_tin_register(struct clk *pwm) return clk_set_parent(pwm, parent); } -static __init int s3c24xx_pwmclk_init(void) +/** + * s3c_pwmclk_init() - initialise pwm clocks + * + * Initialise and register the clocks which provide the inputs for the + * pwm timer blocks. + * + * Note, this call is required by the time core, so must be called after + * the base clocks are added and before any of the initcalls are run. + */ +__init void s3c_pwmclk_init(void) { struct clk *clk_timers; unsigned int clk; @@ -392,7 +425,7 @@ static __init int s3c24xx_pwmclk_init(void) clk_timers = clk_get(NULL, "timers"); if (IS_ERR(clk_timers)) { printk(KERN_ERR "%s: no parent clock\n", __func__); - return -EINVAL; + return; } for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) { @@ -400,7 +433,7 @@ static __init int s3c24xx_pwmclk_init(void) ret = s3c24xx_register_clock(&clk_timer_scaler[clk]); if (ret < 0) { printk(KERN_ERR "error adding pwm scaler%d clock\n", clk); - goto err; + return; } } @@ -408,7 +441,7 @@ static __init int s3c24xx_pwmclk_init(void) ret = s3c24xx_register_clock(&clk_timer_tclk[clk]); if (ret < 0) { printk(KERN_ERR "error adding pww tclk%d\n", clk); - goto err; + return; } } @@ -416,7 +449,7 @@ static __init int s3c24xx_pwmclk_init(void) ret = clk_pwm_tdiv_register(clk); if (ret < 0) { printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk); - goto err; + return; } } @@ -424,14 +457,7 @@ static __init int s3c24xx_pwmclk_init(void) ret = clk_pwm_tin_register(&clk_tin[clk]); if (ret < 0) { printk(KERN_ERR "error adding pwm%d tin clock\n", clk); - goto err; + return; } } - - return 0; - - err: - return ret; } - -arch_initcall(s3c24xx_pwmclk_init); diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c/time.c index c519162..3b27b29 100644 --- a/arch/arm/plat-s3c24xx/time.c +++ b/arch/arm/plat-s3c/time.c @@ -26,6 +26,7 @@ #include <linux/err.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/platform_device.h> #include <asm/system.h> #include <asm/leds.h> @@ -36,6 +37,7 @@ #include <plat/regs-timer.h> #include <mach/regs-irq.h> #include <asm/mach/time.h> +#include <mach/tick.h> #include <plat/clock.h> #include <plat/cpu.h> @@ -43,6 +45,10 @@ static unsigned long timer_startval; static unsigned long timer_usec_ticks; +#ifndef TICK_MAX +#define TICK_MAX (0xffff) +#endif + #define TIMER_USEC_SHIFT 16 /* we use the shifted arithmetic to work out the ratio of timer ticks @@ -91,23 +97,19 @@ static inline unsigned long timer_ticks_to_usec(unsigned long ticks) * IRQs are disabled before entering here from do_gettimeofday() */ -#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0)) - static unsigned long s3c2410_gettimeoffset (void) { unsigned long tdone; - unsigned long irqpend; unsigned long tval; /* work out how many ticks have gone since last timer interrupt */ - tval = __raw_readl(S3C2410_TCNTO(4)); + tval = __raw_readl(S3C2410_TCNTO(4)); tdone = timer_startval - tval; /* check to see if there is an interrupt pending */ - irqpend = __raw_readl(S3C2410_SRCPND); - if (irqpend & SRCPND_TIMER4) { + if (s3c24xx_ostimer_pending()) { /* re-read the timer, and try and fix up for the missed * interrupt. Note, the interrupt may go off before the * timer has re-loaded from wrapping. @@ -144,7 +146,11 @@ static struct irqaction s3c2410_timer_irq = { machine_is_bast() || \ machine_is_vr1000() || \ machine_is_anubis() || \ - machine_is_osiris() ) + machine_is_osiris()) + +static struct clk *tin; +static struct clk *tdiv; +static struct clk *timerclk; /* * Set up timer interrupt, and return the current time in seconds. @@ -159,13 +165,7 @@ static void s3c2410_timer_setup (void) unsigned long tcfg1; unsigned long tcfg0; - tcnt = 0xffff; /* default value for tcnt */ - - /* read the current timer configuration bits */ - - tcon = __raw_readl(S3C2410_TCON); - tcfg1 = __raw_readl(S3C2410_TCFG1); - tcfg0 = __raw_readl(S3C2410_TCFG0); + tcnt = TICK_MAX; /* default value for tcnt */ /* configure the system for whichever machine is in use */ @@ -174,11 +174,13 @@ static void s3c2410_timer_setup (void) timer_usec_ticks = timer_mask_usec_ticks(1, 12000000); tcnt = 12000000 / HZ; + tcfg1 = __raw_readl(S3C2410_TCFG1); tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1; + __raw_writel(tcfg1, S3C2410_TCFG1); } else { unsigned long pclk; - struct clk *clk; + struct clk *tscaler; /* for the h1940 (and others), we use the pclk from the core * to generate the timer values. since values around 50 to @@ -189,38 +191,34 @@ static void s3c2410_timer_setup (void) * (8.45 ticks per usec) */ - /* this is used as default if no other timer can be found */ - - clk = clk_get(NULL, "timers"); - if (IS_ERR(clk)) - panic("failed to get clock for system timer"); - - clk_enable(clk); - - pclk = clk_get_rate(clk); + pclk = clk_get_rate(timerclk); /* configure clock tick */ timer_usec_ticks = timer_mask_usec_ticks(6, pclk); - tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; - tcfg1 |= S3C2410_TCFG1_MUX4_DIV2; + tscaler = clk_get_parent(tdiv); - tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK; - tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT; + clk_set_rate(tscaler, pclk / 3); + clk_set_rate(tdiv, pclk / 6); + clk_set_parent(tin, tdiv); - tcnt = (pclk / 6) / HZ; + tcnt = clk_get_rate(tin) / HZ; } + tcon = __raw_readl(S3C2410_TCON); + tcfg0 = __raw_readl(S3C2410_TCFG0); + tcfg1 = __raw_readl(S3C2410_TCFG1); + /* timers reload after counting zero, so reduce the count by 1 */ tcnt--; - printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n", + printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n", tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks); /* check to see if timer is within 16bit range... */ - if (tcnt > 0xffff) { + if (tcnt > TICK_MAX) { panic("setup_timer: HZ is too small, cannot configure timer!"); return; } @@ -247,8 +245,35 @@ static void s3c2410_timer_setup (void) __raw_writel(tcon, S3C2410_TCON); } -static void __init s3c2410_timer_init (void) +static void __init s3c2410_timer_resources(void) +{ + struct platform_device tmpdev; + + tmpdev.dev.bus = &platform_bus_type; + tmpdev.id = 4; + + timerclk = clk_get(NULL, "timers"); + if (IS_ERR(timerclk)) + panic("failed to get clock for system timer"); + + clk_enable(timerclk); + + if (!use_tclk1_12()) { + tin = clk_get(&tmpdev.dev, "pwm-tin"); + if (IS_ERR(tin)) + panic("failed to get pwm-tin clock for system timer"); + + tdiv = clk_get(&tmpdev.dev, "pwm-tdiv"); + if (IS_ERR(tdiv)) + panic("failed to get pwm-tdiv clock for system timer"); + } + + clk_enable(tin); +} + +static void __init s3c2410_timer_init(void) { + s3c2410_timer_resources(); s3c2410_timer_setup(); setup_irq(IRQ_TIMER4, &s3c2410_timer_irq); } diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 0af3872..2c8a2f5 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -6,8 +6,8 @@ config PLAT_S3C24XX bool - depends on ARCH_S3C2410 - default y if ARCH_S3C2410 + depends on ARCH_S3C2410 || ARCH_S3C24A0 + default y select NO_IOPORT select ARCH_REQUIRE_GPIOLIB help @@ -15,6 +15,19 @@ config PLAT_S3C24XX if PLAT_S3C24XX +# code that is shared between a number of the s3c24xx implementations + +config S3C2410_CLOCK + bool + help + Clock code for the S3C2410, and similar processors which + is currently includes the S3C2410, S3C2440, S3C2442. + +config S3C24XX_DCLK + bool + help + Clock code for supporting DCLK/CLKOUT on S3C24XX architectures + config CPU_S3C244X bool depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442) @@ -28,6 +41,27 @@ config S3C24XX_PWM Support for exporting the PWM timer blocks via the pwm device system. + +# gpio configurations + +config S3C24XX_GPIO_EXTRA + int + default 128 if S3C24XX_GPIO_EXTRA128 + default 64 if S3C24XX_GPIO_EXTRA64 + default 0 + +config S3C24XX_GPIO_EXTRA64 + bool + help + Add an extra 64 gpio numbers to the available GPIO pool. This is + available for boards that need extra gpios for external devices. + +config S3C24XX_GPIO_EXTRA128 + bool + help + Add an extra 128 gpio numbers to the available GPIO pool. This is + available for boards that need extra gpios for external devices. + config PM_SIMTEC bool help @@ -49,6 +83,29 @@ config S3C2410_DMA_DEBUG Enable debugging output for the DMA code. This option sends info to the kernel log, at priority KERN_DEBUG. +config S3C24XX_ADC + bool "ADC common driver support" + help + Core support for the ADC block found in the S3C24XX SoC systems + for drivers such as the touchscreen and hwmon to use to share + this resource. + +# SPI default pin configuration code + +config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13 + bool + help + SPI GPIO configuration code for BUS0 when connected to + GPE11, GPE12 and GPE13. + +config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7 + bool + help + SPI GPIO configuration code for BUS 1 when connected to + GPG5, GPG6 and GPG7. + +# common code for s3c24xx based machines, such as the SMDKs. + config MACH_SMDK bool help diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index d82767b..1e0767b 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile @@ -17,9 +17,8 @@ obj-y += irq.o obj-y += devs.o obj-y += gpio.o obj-y += gpiolib.o -obj-y += time.o obj-y += clock.o -obj-y += pwm-clock.o +obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o # Architecture dependant builds @@ -30,5 +29,18 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += sleep.o obj-$(CONFIG_HAVE_PWM) += pwm.o +obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o obj-$(CONFIG_S3C2410_DMA) += dma.o +obj-$(CONFIG_S3C24XX_ADC) += adc.o + +# device specific setup and/or initialisation +obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o + +# SPI gpio central GPIO functions + +obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o +obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7) += spi-bus1-gpg5_6_7.o + +# machine common support + obj-$(CONFIG_MACH_SMDK) += common-smdk.o diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-s3c24xx/adc.c new file mode 100644 index 0000000..9a5c767 --- /dev/null +++ b/arch/arm/plat-s3c24xx/adc.c @@ -0,0 +1,372 @@ +/* arch/arm/plat-s3c24xx/adc.c + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> + * + * S3C24XX ADC device core + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. +*/ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/list.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/interrupt.h> +#include <linux/io.h> + +#include <plat/regs-adc.h> +#include <plat/adc.h> + +/* This driver is designed to control the usage of the ADC block between + * the touchscreen and any other drivers that may need to use it, such as + * the hwmon driver. + * + * Priority will be given to the touchscreen driver, but as this itself is + * rate limited it should not starve other requests which are processed in + * order that they are received. + * + * Each user registers to get a client block which uniquely identifies it + * and stores information such as the necessary functions to callback when + * action is required. + */ + +struct s3c_adc_client { + struct platform_device *pdev; + struct list_head pend; + + unsigned int nr_samples; + unsigned char is_ts; + unsigned char channel; + + void (*select_cb)(unsigned selected); + void (*convert_cb)(unsigned val1, unsigned val2); +}; + +struct adc_device { + struct platform_device *pdev; + struct platform_device *owner; + struct clk *clk; + struct s3c_adc_client *cur; + struct s3c_adc_client *ts_pend; + void __iomem *regs; + + unsigned int prescale; + + int irq; +}; + +static struct adc_device *adc_dev; + +static LIST_HEAD(adc_pending); + +#define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg) + +static inline void s3c_adc_convert(struct adc_device *adc) +{ + unsigned con = readl(adc->regs + S3C2410_ADCCON); + + con |= S3C2410_ADCCON_ENABLE_START; + writel(con, adc->regs + S3C2410_ADCCON); +} + +static inline void s3c_adc_select(struct adc_device *adc, + struct s3c_adc_client *client) +{ + unsigned con = readl(adc->regs + S3C2410_ADCCON); + + client->select_cb(1); + + con &= ~S3C2410_ADCCON_MUXMASK; + con &= ~S3C2410_ADCCON_STDBM; + con &= ~S3C2410_ADCCON_STARTMASK; + + if (!client->is_ts) + con |= S3C2410_ADCCON_SELMUX(client->channel); + + writel(con, adc->regs + S3C2410_ADCCON); +} + +static void s3c_adc_dbgshow(struct adc_device *adc) +{ + adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n", + readl(adc->regs + S3C2410_ADCCON), + readl(adc->regs + S3C2410_ADCTSC), + readl(adc->regs + S3C2410_ADCDLY)); +} + +void s3c_adc_try(struct adc_device *adc) +{ + struct s3c_adc_client *next = adc->ts_pend; + + if (!next && !list_empty(&adc_pending)) { + next = list_first_entry(&adc_pending, + struct s3c_adc_client, pend); + list_del(&next->pend); + } else + adc->ts_pend = NULL; + + if (next) { + adc_dbg(adc, "new client is %p\n", next); + adc->cur = next; + s3c_adc_select(adc, next); + s3c_adc_convert(adc); + s3c_adc_dbgshow(adc); + } +} + +int s3c_adc_start(struct s3c_adc_client *client, + unsigned int channel, unsigned int nr_samples) +{ + struct adc_device *adc = adc_dev; + unsigned long flags; + + if (!adc) { + printk(KERN_ERR "%s: failed to find adc\n", __func__); + return -EINVAL; + } + + if (client->is_ts && adc->ts_pend) + return -EAGAIN; + + local_irq_save(flags); + + client->channel = channel; + client->nr_samples = nr_samples; + + if (client->is_ts) + adc->ts_pend = client; + else + list_add_tail(&client->pend, &adc_pending); + + if (!adc->cur) + s3c_adc_try(adc); + local_irq_restore(flags); + + return 0; +} +EXPORT_SYMBOL_GPL(s3c_adc_start); + +static void s3c_adc_default_select(unsigned select) +{ +} + +struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, + void (*select)(unsigned int selected), + void (*conv)(unsigned d0, unsigned d1), + unsigned int is_ts) +{ + struct s3c_adc_client *client; + + WARN_ON(!pdev); + WARN_ON(!conv); + + if (!select) + select = s3c_adc_default_select; + + if (!conv || !pdev) + return ERR_PTR(-EINVAL); + + client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL); + if (!client) { + dev_err(&pdev->dev, "no memory for adc client\n"); + return ERR_PTR(-ENOMEM); + } + + client->pdev = pdev; + client->is_ts = is_ts; + client->select_cb = select; + client->convert_cb = conv; + + return client; +} +EXPORT_SYMBOL_GPL(s3c_adc_register); + +void s3c_adc_release(struct s3c_adc_client *client) +{ + /* We should really check that nothing is in progress. */ + kfree(client); +} +EXPORT_SYMBOL_GPL(s3c_adc_release); + +static irqreturn_t s3c_adc_irq(int irq, void *pw) +{ + struct adc_device *adc = pw; + struct s3c_adc_client *client = adc->cur; + unsigned long flags; + unsigned data0, data1; + + if (!client) { + dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__); + return IRQ_HANDLED; + } + + data0 = readl(adc->regs + S3C2410_ADCDAT0); + data1 = readl(adc->regs + S3C2410_ADCDAT1); + adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1); + + (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff); + + if (--client->nr_samples > 0) { + /* fire another conversion for this */ + + client->select_cb(1); + s3c_adc_convert(adc); + } else { + local_irq_save(flags); + (client->select_cb)(0); + adc->cur = NULL; + + s3c_adc_try(adc); + local_irq_restore(flags); + } + + return IRQ_HANDLED; +} + +static int s3c_adc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct adc_device *adc; + struct resource *regs; + int ret; + + adc = kzalloc(sizeof(struct adc_device), GFP_KERNEL); + if (adc == NULL) { + dev_err(dev, "failed to allocate adc_device\n"); + return -ENOMEM; + } + + adc->pdev = pdev; + adc->prescale = S3C2410_ADCCON_PRSCVL(49); + + adc->irq = platform_get_irq(pdev, 1); + if (adc->irq <= 0) { + dev_err(dev, "failed to get adc irq\n"); + ret = -ENOENT; + goto err_alloc; + } + + ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc); + if (ret < 0) { + dev_err(dev, "failed to attach adc irq\n"); + goto err_alloc; + } + + adc->clk = clk_get(dev, "adc"); + if (IS_ERR(adc->clk)) { + dev_err(dev, "failed to get adc clock\n"); + ret = PTR_ERR(adc->clk); + goto err_irq; + } + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!regs) { + dev_err(dev, "failed to find registers\n"); + ret = -ENXIO; + goto err_clk; + } + + adc->regs = ioremap(regs->start, resource_size(regs)); + if (!adc->regs) { + dev_err(dev, "failed to map registers\n"); + ret = -ENXIO; + goto err_clk; + } + + clk_enable(adc->clk); + + writel(adc->prescale | S3C2410_ADCCON_PRSCEN, + adc->regs + S3C2410_ADCCON); + + dev_info(dev, "attached adc driver\n"); + + platform_set_drvdata(pdev, adc); + adc_dev = adc; + + return 0; + + err_clk: + clk_put(adc->clk); + + err_irq: + free_irq(adc->irq, adc); + + err_alloc: + kfree(adc); + return ret; +} + +static int s3c_adc_remove(struct platform_device *pdev) +{ + struct adc_device *adc = platform_get_drvdata(pdev); + + iounmap(adc->regs); + free_irq(adc->irq, adc); + clk_disable(adc->clk); + clk_put(adc->clk); + kfree(adc); + + return 0; +} + +#ifdef CONFIG_PM +static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct adc_device *adc = platform_get_drvdata(pdev); + u32 con; + + con = readl(adc->regs + S3C2410_ADCCON); + con |= S3C2410_ADCCON_STDBM; + writel(con, adc->regs + S3C2410_ADCCON); + + clk_disable(adc->clk); + + return 0; +} + +static int s3c_adc_resume(struct platform_device *pdev) +{ + struct adc_device *adc = platform_get_drvdata(pdev); + + clk_enable(adc->clk); + + writel(adc->prescale | S3C2410_ADCCON_PRSCEN, + adc->regs + S3C2410_ADCCON); + + return 0; +} + +#else +#define s3c_adc_suspend NULL +#define s3c_adc_resume NULL +#endif + +static struct platform_driver s3c_adc_driver = { + .driver = { + .name = "s3c24xx-adc", + .owner = THIS_MODULE, + }, + .probe = s3c_adc_probe, + .remove = __devexit_p(s3c_adc_remove), + .suspend = s3c_adc_suspend, + .resume = s3c_adc_resume, +}; + +static int __init adc_init(void) +{ + int ret; + + ret = platform_driver_register(&s3c_adc_driver); + if (ret) + printk(KERN_ERR "%s: failed to add adc driver\n", __func__); + + return ret; +} + +arch_initcall(adc_init); diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c new file mode 100644 index 0000000..5b75a79 --- /dev/null +++ b/arch/arm/plat-s3c24xx/clock-dclk.c @@ -0,0 +1,194 @@ +/* linux/arch/arm/plat-s3c24xx/clock-dclk.c + * + * Copyright (c) 2004,2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C24XX - definitions for DCLK and CLKOUT registers + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <mach/regs-clock.h> +#include <mach/regs-gpio.h> + +#include <plat/clock.h> +#include <plat/cpu.h> + +/* clocks that could be registered by external code */ + +static int s3c24xx_dclk_enable(struct clk *clk, int enable) +{ + unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON); + + if (enable) + dclkcon |= clk->ctrlbit; + else + dclkcon &= ~clk->ctrlbit; + + __raw_writel(dclkcon, S3C24XX_DCLKCON); + + return 0; +} + +static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) +{ + unsigned long dclkcon; + unsigned int uclk; + + if (parent == &clk_upll) + uclk = 1; + else if (parent == &clk_p) + uclk = 0; + else + return -EINVAL; + + clk->parent = parent; + + dclkcon = __raw_readl(S3C24XX_DCLKCON); + + if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) { + if (uclk) + dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK; + else + dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK; + } else { + if (uclk) + dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK; + else + dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK; + } + + __raw_writel(dclkcon, S3C24XX_DCLKCON); + + return 0; +} +static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate) +{ + unsigned long div; + + if ((rate == 0) || !clk->parent) + return 0; + + div = clk_get_rate(clk->parent) / rate; + if (div < 2) + div = 2; + else if (div > 16) + div = 16; + + return div; +} + +static unsigned long s3c24xx_round_dclk_rate(struct clk *clk, + unsigned long rate) +{ + unsigned long div = s3c24xx_calc_div(clk, rate); + + if (div == 0) + return 0; + + return clk_get_rate(clk->parent) / div; +} + +static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate) +{ + unsigned long mask, data, div = s3c24xx_calc_div(clk, rate); + + if (div == 0) + return -EINVAL; + + if (clk == &s3c24xx_dclk0) { + mask = S3C2410_DCLKCON_DCLK0_DIV_MASK | + S3C2410_DCLKCON_DCLK0_CMP_MASK; + data = S3C2410_DCLKCON_DCLK0_DIV(div) | + S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2); + } else if (clk == &s3c24xx_dclk1) { + mask = S3C2410_DCLKCON_DCLK1_DIV_MASK | + S3C2410_DCLKCON_DCLK1_CMP_MASK; + data = S3C2410_DCLKCON_DCLK1_DIV(div) | + S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2); + } else + return -EINVAL; + + clk->rate = clk_get_rate(clk->parent) / div; + __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data), + S3C24XX_DCLKCON); + return clk->rate; +} +static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) +{ + unsigned long mask; + unsigned long source; + + /* calculate the MISCCR setting for the clock */ + + if (parent == &clk_xtal) + source = S3C2410_MISCCR_CLK0_MPLL; + else if (parent == &clk_upll) + source = S3C2410_MISCCR_CLK0_UPLL; + else if (parent == &clk_f) + source = S3C2410_MISCCR_CLK0_FCLK; + else if (parent == &clk_h) + source = S3C2410_MISCCR_CLK0_HCLK; + else if (parent == &clk_p) + source = S3C2410_MISCCR_CLK0_PCLK; + else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0) + source = S3C2410_MISCCR_CLK0_DCLK0; + else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1) + source = S3C2410_MISCCR_CLK0_DCLK0; + else + return -EINVAL; + + clk->parent = parent; + + if (clk == &s3c24xx_clkout0) + mask = S3C2410_MISCCR_CLK0_MASK; + else { + source <<= 4; + mask = S3C2410_MISCCR_CLK1_MASK; + } + + s3c2410_modify_misccr(mask, source); + return 0; +} + +/* external clock definitions */ + +struct clk s3c24xx_dclk0 = { + .name = "dclk0", + .id = -1, + .ctrlbit = S3C2410_DCLKCON_DCLK0EN, + .enable = s3c24xx_dclk_enable, + .set_parent = s3c24xx_dclk_setparent, + .set_rate = s3c24xx_set_dclk_rate, + .round_rate = s3c24xx_round_dclk_rate, +}; + +struct clk s3c24xx_dclk1 = { + .name = "dclk1", + .id = -1, + .ctrlbit = S3C2410_DCLKCON_DCLK1EN, + .enable = s3c24xx_dclk_enable, + .set_parent = s3c24xx_dclk_setparent, + .set_rate = s3c24xx_set_dclk_rate, + .round_rate = s3c24xx_round_dclk_rate, +}; + +struct clk s3c24xx_clkout0 = { + .name = "clkout0", + .id = -1, + .set_parent = s3c24xx_clkout_setparent, +}; + +struct clk s3c24xx_clkout1 = { + .name = "clkout1", + .id = -1, + .set_parent = s3c24xx_clkout_setparent, +}; diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c index a005ddb..8474d05 100644 --- a/arch/arm/plat-s3c24xx/clock.c +++ b/arch/arm/plat-s3c24xx/clock.c @@ -27,18 +27,8 @@ */ #include <linux/init.h> -#include <linux/module.h> #include <linux/kernel.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/platform_device.h> -#include <linux/sysdev.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> #include <linux/clk.h> -#include <linux/mutex.h> -#include <linux/delay.h> #include <linux/io.h> #include <mach/hardware.h> @@ -47,490 +37,23 @@ #include <mach/regs-clock.h> #include <mach/regs-gpio.h> +#include <plat/cpu-freq.h> + #include <plat/clock.h> #include <plat/cpu.h> - -/* clock information */ - -static LIST_HEAD(clocks); - -DEFINE_MUTEX(clocks_mutex); - -/* enable and disable calls for use with the clk struct */ - -static int clk_null_enable(struct clk *clk, int enable) -{ - return 0; -} - -/* Clock API calls */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p; - struct clk *clk = ERR_PTR(-ENOENT); - int idno; - - if (dev == NULL || dev->bus != &platform_bus_type) - idno = -1; - else - idno = to_platform_device(dev)->id; - - mutex_lock(&clocks_mutex); - - list_for_each_entry(p, &clocks, list) { - if (p->id == idno && - strcmp(id, p->name) == 0 && - try_module_get(p->owner)) { - clk = p; - break; - } - } - - /* check for the case where a device was supplied, but the - * clock that was being searched for is not device specific */ - - if (IS_ERR(clk)) { - list_for_each_entry(p, &clocks, list) { - if (p->id == -1 && strcmp(id, p->name) == 0 && - try_module_get(p->owner)) { - clk = p; - break; - } - } - } - - mutex_unlock(&clocks_mutex); - return clk; -} - -void clk_put(struct clk *clk) -{ - module_put(clk->owner); -} - -int clk_enable(struct clk *clk) -{ - if (IS_ERR(clk) || clk == NULL) - return -EINVAL; - - clk_enable(clk->parent); - - mutex_lock(&clocks_mutex); - - if ((clk->usage++) == 0) - (clk->enable)(clk, 1); - - mutex_unlock(&clocks_mutex); - return 0; -} - -void clk_disable(struct clk *clk) -{ - if (IS_ERR(clk) || clk == NULL) - return; - - mutex_lock(&clocks_mutex); - - if ((--clk->usage) == 0) - (clk->enable)(clk, 0); - - mutex_unlock(&clocks_mutex); - clk_disable(clk->parent); -} - - -unsigned long clk_get_rate(struct clk *clk) -{ - if (IS_ERR(clk)) - return 0; - - if (clk->rate != 0) - return clk->rate; - - if (clk->get_rate != NULL) - return (clk->get_rate)(clk); - - if (clk->parent != NULL) - return clk_get_rate(clk->parent); - - return clk->rate; -} - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (!IS_ERR(clk) && clk->round_rate) - return (clk->round_rate)(clk, rate); - - return rate; -} - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret; - - if (IS_ERR(clk)) - return -EINVAL; - - /* We do not default just do a clk->rate = rate as - * the clock may have been made this way by choice. - */ - - WARN_ON(clk->set_rate == NULL); - - if (clk->set_rate == NULL) - return -EINVAL; - - mutex_lock(&clocks_mutex); - ret = (clk->set_rate)(clk, rate); - mutex_unlock(&clocks_mutex); - - return ret; -} - -struct clk *clk_get_parent(struct clk *clk) -{ - return clk->parent; -} - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - int ret = 0; - - if (IS_ERR(clk)) - return -EINVAL; - - mutex_lock(&clocks_mutex); - - if (clk->set_parent) - ret = (clk->set_parent)(clk, parent); - - mutex_unlock(&clocks_mutex); - - return ret; -} - -EXPORT_SYMBOL(clk_get); -EXPORT_SYMBOL(clk_put); -EXPORT_SYMBOL(clk_enable); -EXPORT_SYMBOL(clk_disable); -EXPORT_SYMBOL(clk_get_rate); -EXPORT_SYMBOL(clk_round_rate); -EXPORT_SYMBOL(clk_set_rate); -EXPORT_SYMBOL(clk_get_parent); -EXPORT_SYMBOL(clk_set_parent); - -/* base clocks */ - -static int clk_default_setrate(struct clk *clk, unsigned long rate) -{ - clk->rate = rate; - return 0; -} - -struct clk clk_xtal = { - .name = "xtal", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, -}; - -struct clk clk_mpll = { - .name = "mpll", - .id = -1, - .set_rate = clk_default_setrate, -}; - -struct clk clk_upll = { - .name = "upll", - .id = -1, - .parent = NULL, - .ctrlbit = 0, -}; - -struct clk clk_f = { - .name = "fclk", - .id = -1, - .rate = 0, - .parent = &clk_mpll, - .ctrlbit = 0, - .set_rate = clk_default_setrate, -}; - -struct clk clk_h = { - .name = "hclk", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, - .set_rate = clk_default_setrate, -}; - -struct clk clk_p = { - .name = "pclk", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, - .set_rate = clk_default_setrate, -}; - -struct clk clk_usb_bus = { - .name = "usb-bus", - .id = -1, - .rate = 0, - .parent = &clk_upll, -}; - -/* clocks that could be registered by external code */ - -static int s3c24xx_dclk_enable(struct clk *clk, int enable) -{ - unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON); - - if (enable) - dclkcon |= clk->ctrlbit; - else - dclkcon &= ~clk->ctrlbit; - - __raw_writel(dclkcon, S3C24XX_DCLKCON); - - return 0; -} - -static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) -{ - unsigned long dclkcon; - unsigned int uclk; - - if (parent == &clk_upll) - uclk = 1; - else if (parent == &clk_p) - uclk = 0; - else - return -EINVAL; - - clk->parent = parent; - - dclkcon = __raw_readl(S3C24XX_DCLKCON); - - if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) { - if (uclk) - dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK; - else - dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK; - } else { - if (uclk) - dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK; - else - dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK; - } - - __raw_writel(dclkcon, S3C24XX_DCLKCON); - - return 0; -} - -static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate) -{ - unsigned long div; - - if ((rate == 0) || !clk->parent) - return 0; - - div = clk_get_rate(clk->parent) / rate; - if (div < 2) - div = 2; - else if (div > 16) - div = 16; - - return div; -} - -static unsigned long s3c24xx_round_dclk_rate(struct clk *clk, - unsigned long rate) -{ - unsigned long div = s3c24xx_calc_div(clk, rate); - - if (div == 0) - return 0; - - return clk_get_rate(clk->parent) / div; -} - -static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate) -{ - unsigned long mask, data, div = s3c24xx_calc_div(clk, rate); - - if (div == 0) - return -EINVAL; - - if (clk == &s3c24xx_dclk0) { - mask = S3C2410_DCLKCON_DCLK0_DIV_MASK | - S3C2410_DCLKCON_DCLK0_CMP_MASK; - data = S3C2410_DCLKCON_DCLK0_DIV(div) | - S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2); - } else if (clk == &s3c24xx_dclk1) { - mask = S3C2410_DCLKCON_DCLK1_DIV_MASK | - S3C2410_DCLKCON_DCLK1_CMP_MASK; - data = S3C2410_DCLKCON_DCLK1_DIV(div) | - S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2); - } else - return -EINVAL; - - clk->rate = clk_get_rate(clk->parent) / div; - __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data), - S3C24XX_DCLKCON); - return clk->rate; -} - -static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) -{ - unsigned long mask; - unsigned long source; - - /* calculate the MISCCR setting for the clock */ - - if (parent == &clk_xtal) - source = S3C2410_MISCCR_CLK0_MPLL; - else if (parent == &clk_upll) - source = S3C2410_MISCCR_CLK0_UPLL; - else if (parent == &clk_f) - source = S3C2410_MISCCR_CLK0_FCLK; - else if (parent == &clk_h) - source = S3C2410_MISCCR_CLK0_HCLK; - else if (parent == &clk_p) - source = S3C2410_MISCCR_CLK0_PCLK; - else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0) - source = S3C2410_MISCCR_CLK0_DCLK0; - else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1) - source = S3C2410_MISCCR_CLK0_DCLK0; - else - return -EINVAL; - - clk->parent = parent; - - if (clk == &s3c24xx_clkout0) - mask = S3C2410_MISCCR_CLK0_MASK; - else { - source <<= 4; - mask = S3C2410_MISCCR_CLK1_MASK; - } - - s3c2410_modify_misccr(mask, source); - return 0; -} - -/* external clock definitions */ - -struct clk s3c24xx_dclk0 = { - .name = "dclk0", - .id = -1, - .ctrlbit = S3C2410_DCLKCON_DCLK0EN, - .enable = s3c24xx_dclk_enable, - .set_parent = s3c24xx_dclk_setparent, - .set_rate = s3c24xx_set_dclk_rate, - .round_rate = s3c24xx_round_dclk_rate, -}; - -struct clk s3c24xx_dclk1 = { - .name = "dclk1", - .id = -1, - .ctrlbit = S3C2410_DCLKCON_DCLK1EN, - .enable = s3c24xx_dclk_enable, - .set_parent = s3c24xx_dclk_setparent, - .set_rate = s3c24xx_set_dclk_rate, - .round_rate = s3c24xx_round_dclk_rate, -}; - -struct clk s3c24xx_clkout0 = { - .name = "clkout0", - .id = -1, - .set_parent = s3c24xx_clkout_setparent, -}; - -struct clk s3c24xx_clkout1 = { - .name = "clkout1", - .id = -1, - .set_parent = s3c24xx_clkout_setparent, -}; - -struct clk s3c24xx_uclk = { - .name = "uclk", - .id = -1, -}; - -/* initialise the clock system */ - -int s3c24xx_register_clock(struct clk *clk) -{ - clk->owner = THIS_MODULE; - - if (clk->enable == NULL) - clk->enable = clk_null_enable; - - /* add to the list of available clocks */ - - mutex_lock(&clocks_mutex); - list_add(&clk->list, &clocks); - mutex_unlock(&clocks_mutex); - - return 0; -} - -int s3c24xx_register_clocks(struct clk **clks, int nr_clks) -{ - int fails = 0; - - for (; nr_clks > 0; nr_clks--, clks++) { - if (s3c24xx_register_clock(*clks) < 0) - fails++; - } - - return fails; -} +#include <plat/pll.h> /* initalise all the clocks */ -int __init s3c24xx_setup_clocks(unsigned long xtal, - unsigned long fclk, - unsigned long hclk, - unsigned long pclk) +void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, + unsigned long hclk, + unsigned long pclk) { - printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); - - /* initialise the main system clocks */ - - clk_xtal.rate = xtal; - clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal); + clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), + clk_xtal.rate); clk_mpll.rate = fclk; clk_h.rate = hclk; clk_p.rate = pclk; clk_f.rate = fclk; - - /* assume uart clocks are correctly setup */ - - /* register our clocks */ - - if (s3c24xx_register_clock(&clk_xtal) < 0) - printk(KERN_ERR "failed to register master xtal\n"); - - if (s3c24xx_register_clock(&clk_mpll) < 0) - printk(KERN_ERR "failed to register mpll clock\n"); - - if (s3c24xx_register_clock(&clk_upll) < 0) - printk(KERN_ERR "failed to register upll clock\n"); - - if (s3c24xx_register_clock(&clk_f) < 0) - printk(KERN_ERR "failed to register cpu fclk\n"); - - if (s3c24xx_register_clock(&clk_h) < 0) - printk(KERN_ERR "failed to register cpu hclk\n"); - - if (s3c24xx_register_clock(&clk_p) < 0) - printk(KERN_ERR "failed to register cpu pclk\n"); - - return 0; } diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c index 3098736..3d48370 100644 --- a/arch/arm/plat-s3c24xx/common-smdk.c +++ b/arch/arm/plat-s3c24xx/common-smdk.c @@ -38,7 +38,7 @@ #include <mach/regs-gpio.h> #include <mach/leds-gpio.h> -#include <asm/plat-s3c/nand.h> +#include <plat/nand.h> #include <plat/common-smdk.h> #include <plat/devs.h> diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index 22a3295..542062f 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c @@ -30,7 +30,6 @@ #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/io.h> -#include <linux/delay.h> #include <mach/hardware.h> #include <asm/irq.h> @@ -55,16 +54,6 @@ #include <plat/s3c2442.h> #include <plat/s3c2443.h> -struct cpu_table { - unsigned long idcode; - unsigned long idmask; - void (*map_io)(struct map_desc *mach_desc, int size); - void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no); - void (*init_clocks)(int xtal); - int (*init)(void); - const char *name; -}; - /* table of supported CPUs */ static const char name_s3c2400[] = "S3C2400"; @@ -169,23 +158,7 @@ static struct map_desc s3c_iodesc[] __initdata = { IODESC_ENT(UART) }; -static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode) -{ - struct cpu_table *tab; - int count; - - tab = cpu_ids; - for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) { - if ((idcode & tab->idmask) == tab->idcode) - return tab; - } - - return NULL; -} - -/* cpu information */ - -static struct cpu_table *cpu; +/* read cpu identificaiton code */ static unsigned long s3c24xx_read_idcode_v5(void) { @@ -231,6 +204,7 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) unsigned long idcode = 0x0; /* initialise the io descriptors we need for initialisation */ + iotable_init(mach_desc, size); iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); if (cpu_architecture() >= CPU_ARCH_ARMv5) { @@ -239,117 +213,7 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) idcode = s3c24xx_read_idcode_v4(); } - cpu = s3c_lookup_cpu(idcode); - - if (cpu == NULL) { - printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); - panic("Unknown S3C24XX CPU"); - } - - printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode); - - if (cpu->map_io == NULL || cpu->init == NULL) { - printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); - panic("Unsupported S3C24XX CPU"); - } - arm_pm_restart = s3c24xx_pm_restart; - (cpu->map_io)(mach_desc, size); -} - -/* s3c24xx_init_clocks - * - * Initialise the clock subsystem and associated information from the - * given master crystal value. - * - * xtal = 0 -> use default PLL crystal value (normally 12MHz) - * != 0 -> PLL crystal value in Hz -*/ - -void __init s3c24xx_init_clocks(int xtal) -{ - if (xtal == 0) - xtal = 12*1000*1000; - - if (cpu == NULL) - panic("s3c24xx_init_clocks: no cpu setup?\n"); - - if (cpu->init_clocks == NULL) - panic("s3c24xx_init_clocks: cpu has no clock init\n"); - else - (cpu->init_clocks)(xtal); + s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); } - -/* uart management */ - -static int nr_uarts __initdata = 0; - -static struct s3c2410_uartcfg uart_cfgs[3]; - -/* s3c24xx_init_uartdevs - * - * copy the specified platform data and configuration into our central - * set of devices, before the data is thrown away after the init process. - * - * This also fills in the array passed to the serial driver for the - * early initialisation of the console. -*/ - -void __init s3c24xx_init_uartdevs(char *name, - struct s3c24xx_uart_resources *res, - struct s3c2410_uartcfg *cfg, int no) -{ - struct platform_device *platdev; - struct s3c2410_uartcfg *cfgptr = uart_cfgs; - struct s3c24xx_uart_resources *resp; - int uart; - - memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no); - - for (uart = 0; uart < no; uart++, cfg++, cfgptr++) { - platdev = s3c24xx_uart_src[cfgptr->hwport]; - - resp = res + cfgptr->hwport; - - s3c24xx_uart_devs[uart] = platdev; - - platdev->name = name; - platdev->resource = resp->resources; - platdev->num_resources = resp->nr_resources; - - platdev->dev.platform_data = cfgptr; - } - - nr_uarts = no; -} - -void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) -{ - if (cpu == NULL) - return; - - if (cpu->init_uarts == NULL) { - printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); - } else - (cpu->init_uarts)(cfg, no); -} - -static int __init s3c_arch_init(void) -{ - int ret; - - // do the correct init for cpu - - if (cpu == NULL) - panic("s3c_arch_init: NULL cpu\n"); - - ret = (cpu->init)(); - if (ret != 0) - return ret; - - ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); - return ret; -} - -arch_initcall(s3c_arch_init); diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index e93f8bf..16ac01d 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -29,11 +29,11 @@ #include <asm/irq.h> #include <plat/regs-serial.h> -#include <asm/plat-s3c24xx/udc.h> +#include <plat/udc.h> #include <plat/devs.h> #include <plat/cpu.h> -#include <asm/plat-s3c24xx/regs-spi.h> +#include <plat/regs-spi.h> /* Serial port registrations */ @@ -76,6 +76,19 @@ static struct resource s3c2410_uart2_resource[] = { } }; +static struct resource s3c2410_uart3_resource[] = { + [0] = { + .start = S3C2443_PA_UART3, + .end = S3C2443_PA_UART3 + 0x3fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3CUART_RX3, + .end = IRQ_S3CUART_ERR3, + .flags = IORESOURCE_IRQ, + }, +}; + struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { [0] = { .resources = s3c2410_uart0_resource, @@ -89,6 +102,10 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { .resources = s3c2410_uart2_resource, .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource), }, + [3] = { + .resources = s3c2410_uart3_resource, + .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource), + }, }; /* yart devices */ @@ -105,13 +122,18 @@ static struct platform_device s3c24xx_uart_device2 = { .id = 2, }; -struct platform_device *s3c24xx_uart_src[3] = { +static struct platform_device s3c24xx_uart_device3 = { + .id = 3, +}; + +struct platform_device *s3c24xx_uart_src[4] = { &s3c24xx_uart_device0, &s3c24xx_uart_device1, &s3c24xx_uart_device2, + &s3c24xx_uart_device3, }; -struct platform_device *s3c24xx_uart_devs[3] = { +struct platform_device *s3c24xx_uart_devs[4] = { }; /* USB Host Controller */ @@ -192,8 +214,8 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) static struct resource s3c_nand_resource[] = { [0] = { - .start = S3C2410_PA_NAND, - .end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1, + .start = S3C24XX_PA_NAND, + .end = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1, .flags = IORESOURCE_MEM, } }; @@ -271,31 +293,6 @@ struct platform_device s3c_device_wdt = { EXPORT_SYMBOL(s3c_device_wdt); -/* I2C */ - -static struct resource s3c_i2c_resource[] = { - [0] = { - .start = S3C24XX_PA_IIC, - .end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IIC, - .end = IRQ_IIC, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_i2c = { - .name = "s3c2410-i2c", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_i2c_resource), - .resource = s3c_i2c_resource, -}; - -EXPORT_SYMBOL(s3c_device_i2c); - /* IIS */ static struct resource s3c_iis_resource[] = { @@ -372,18 +369,26 @@ static struct resource s3c_adc_resource[] = { }; struct platform_device s3c_device_adc = { - .name = "s3c2410-adc", + .name = "s3c24xx-adc", .id = -1, .num_resources = ARRAY_SIZE(s3c_adc_resource), .resource = s3c_adc_resource, }; +/* HWMON */ + +struct platform_device s3c_device_hwmon = { + .name = "s3c24xx-hwmon", + .id = -1, + .dev.parent = &s3c_device_adc.dev, +}; + /* SDI */ static struct resource s3c_sdi_resource[] = { [0] = { - .start = S3C2410_PA_SDI, - .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1, + .start = S3C24XX_PA_SDI, + .end = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -403,36 +408,6 @@ struct platform_device s3c_device_sdi = { EXPORT_SYMBOL(s3c_device_sdi); -/* High-speed MMC/SD */ - -static struct resource s3c_hsmmc_resource[] = { - [0] = { - .start = S3C2443_PA_HSMMC, - .end = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_S3C2443_HSMMC, - .end = IRQ_S3C2443_HSMMC, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_hsmmc = { - .name = "s3c-sdhci", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_hsmmc_resource), - .resource = s3c_hsmmc_resource, - .dev = { - .dma_mask = &s3c_device_hsmmc_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - - - /* SPI (0) */ static struct resource s3c_spi0_resource[] = { diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 1baf941..aee2aeb 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -25,15 +25,13 @@ #include <linux/sysdev.h> #include <linux/slab.h> #include <linux/errno.h> -#include <linux/delay.h> #include <linux/io.h> #include <asm/system.h> #include <asm/irq.h> #include <mach/hardware.h> -#include <asm/dma.h> +#include <mach/dma.h> -#include <asm/mach/dma.h> #include <mach/map.h> #include <plat/dma.h> @@ -804,7 +802,7 @@ EXPORT_SYMBOL(s3c2410_dma_request); * allowed to go through. */ -int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) +int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client) { struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); unsigned long flags; @@ -995,7 +993,7 @@ static int s3c2410_dma_started(struct s3c2410_dma_chan *chan) } int -s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op) +s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op) { struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); @@ -1043,7 +1041,7 @@ EXPORT_SYMBOL(s3c2410_dma_ctrl); * dcon: base value of the DCONx register */ -int s3c2410_dma_config(dmach_t channel, +int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon) { @@ -1092,7 +1090,7 @@ int s3c2410_dma_config(dmach_t channel, EXPORT_SYMBOL(s3c2410_dma_config); -int s3c2410_dma_setflags(dmach_t channel, unsigned int flags) +int s3c2410_dma_setflags(unsigned int channel, unsigned int flags) { struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); @@ -1113,7 +1111,7 @@ EXPORT_SYMBOL(s3c2410_dma_setflags); * irq? */ -int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn) +int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn) { struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); @@ -1129,7 +1127,7 @@ int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn) EXPORT_SYMBOL(s3c2410_dma_set_opfn); -int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn) +int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn) { struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); @@ -1219,7 +1217,7 @@ EXPORT_SYMBOL(s3c2410_dma_devconfig); * returns the current transfer points for the dma source and destination */ -int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst) +int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst) { struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c index 3caec6b..f95c6c9 100644 --- a/arch/arm/plat-s3c24xx/gpiolib.c +++ b/arch/arm/plat-s3c24xx/gpiolib.c @@ -19,104 +19,12 @@ #include <linux/io.h> #include <linux/gpio.h> +#include <plat/gpio-core.h> #include <mach/hardware.h> #include <asm/irq.h> #include <mach/regs-gpio.h> -struct s3c24xx_gpio_chip { - struct gpio_chip chip; - void __iomem *base; -}; - -static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc) -{ - return container_of(gpc, struct s3c24xx_gpio_chip, chip); -} - -/* these routines are exported for use by other parts of the platform - * and system support, but are not intended to be used directly by the - * drivers themsevles. - */ - -static int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset) -{ - struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); - void __iomem *base = ourchip->base; - unsigned long flags; - unsigned long con; - - local_irq_save(flags); - - con = __raw_readl(base + 0x00); - con &= ~(3 << (offset * 2)); - con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2); - - __raw_writel(con, base + 0x00); - - local_irq_restore(flags); - return 0; -} - -static int s3c24xx_gpiolib_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); - void __iomem *base = ourchip->base; - unsigned long flags; - unsigned long dat; - unsigned long con; - - local_irq_save(flags); - - dat = __raw_readl(base + 0x04); - dat &= ~(1 << offset); - if (value) - dat |= 1 << offset; - __raw_writel(dat, base + 0x04); - - con = __raw_readl(base + 0x00); - con &= ~(3 << (offset * 2)); - con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2); - - __raw_writel(con, base + 0x00); - __raw_writel(dat, base + 0x04); - - local_irq_restore(flags); - return 0; -} - -static void s3c24xx_gpiolib_set(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); - void __iomem *base = ourchip->base; - unsigned long flags; - unsigned long dat; - - local_irq_save(flags); - - dat = __raw_readl(base + 0x04); - dat &= ~(1 << offset); - if (value) - dat |= 1 << offset; - __raw_writel(dat, base + 0x04); - - local_irq_restore(flags); -} - -static int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset) -{ - struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); - unsigned long val; - - val = __raw_readl(ourchip->base + 0x04); - val >>= offset; - val &= 1; - - return val; -} - static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) { return -EINVAL; @@ -125,7 +33,7 @@ static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, unsigned offset, int value) { - struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); void __iomem *base = ourchip->base; unsigned long flags; unsigned long dat; @@ -151,7 +59,7 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, return 0; } -static struct s3c24xx_gpio_chip gpios[] = { +struct s3c_gpio_chip s3c24xx_gpios[] = { [0] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), .chip = { @@ -161,8 +69,6 @@ static struct s3c24xx_gpio_chip gpios[] = { .ngpio = 24, .direction_input = s3c24xx_gpiolib_banka_input, .direction_output = s3c24xx_gpiolib_banka_output, - .set = s3c24xx_gpiolib_set, - .get = s3c24xx_gpiolib_get, }, }, [1] = { @@ -172,10 +78,6 @@ static struct s3c24xx_gpio_chip gpios[] = { .owner = THIS_MODULE, .label = "GPIOB", .ngpio = 16, - .direction_input = s3c24xx_gpiolib_input, - .direction_output = s3c24xx_gpiolib_output, - .set = s3c24xx_gpiolib_set, - .get = s3c24xx_gpiolib_get, }, }, [2] = { @@ -185,10 +87,6 @@ static struct s3c24xx_gpio_chip gpios[] = { .owner = THIS_MODULE, .label = "GPIOC", .ngpio = 16, - .direction_input = s3c24xx_gpiolib_input, - .direction_output = s3c24xx_gpiolib_output, - .set = s3c24xx_gpiolib_set, - .get = s3c24xx_gpiolib_get, }, }, [3] = { @@ -198,10 +96,6 @@ static struct s3c24xx_gpio_chip gpios[] = { .owner = THIS_MODULE, .label = "GPIOD", .ngpio = 16, - .direction_input = s3c24xx_gpiolib_input, - .direction_output = s3c24xx_gpiolib_output, - .set = s3c24xx_gpiolib_set, - .get = s3c24xx_gpiolib_get, }, }, [4] = { @@ -211,10 +105,6 @@ static struct s3c24xx_gpio_chip gpios[] = { .label = "GPIOE", .owner = THIS_MODULE, .ngpio = 16, - .direction_input = s3c24xx_gpiolib_input, - .direction_output = s3c24xx_gpiolib_output, - .set = s3c24xx_gpiolib_set, - .get = s3c24xx_gpiolib_get, }, }, [5] = { @@ -224,10 +114,6 @@ static struct s3c24xx_gpio_chip gpios[] = { .owner = THIS_MODULE, .label = "GPIOF", .ngpio = 8, - .direction_input = s3c24xx_gpiolib_input, - .direction_output = s3c24xx_gpiolib_output, - .set = s3c24xx_gpiolib_set, - .get = s3c24xx_gpiolib_get, }, }, [6] = { @@ -237,21 +123,17 @@ static struct s3c24xx_gpio_chip gpios[] = { .owner = THIS_MODULE, .label = "GPIOG", .ngpio = 10, - .direction_input = s3c24xx_gpiolib_input, - .direction_output = s3c24xx_gpiolib_output, - .set = s3c24xx_gpiolib_set, - .get = s3c24xx_gpiolib_get, }, }, }; static __init int s3c24xx_gpiolib_init(void) { - struct s3c24xx_gpio_chip *chip = gpios; + struct s3c_gpio_chip *chip = s3c24xx_gpios; int gpn; - for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++) - gpiochip_add(&chip->chip); + for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) + s3c_gpiolib_add(chip); return 0; } diff --git a/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h new file mode 100644 index 0000000..a087de2 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h @@ -0,0 +1,55 @@ +/* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C24xx - pwm clock and timer support + */ + +/** + * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk + * @cfg: The timer TCFG1 register bits shifted down to 0. + * + * Return true if the given configuration from TCFG1 is a TCLK instead + * any of the TDIV clocks. + */ +static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) +{ + return tcfg == S3C2410_TCFG1_MUX_TCLK; +} + +/** + * tcfg_to_divisor() - convert tcfg1 setting to a divisor + * @tcfg1: The tcfg1 setting, shifted down. + * + * Get the divisor value for the given tcfg1 setting. We assume the + * caller has already checked to see if this is not a TCLK source. + */ +static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) +{ + return 1 << (1 + tcfg1); +} + +/** + * pwm_tdiv_has_div1() - does the tdiv setting have a /1 + * + * Return true if we have a /1 in the tdiv setting. + */ +static inline unsigned int pwm_tdiv_has_div1(void) +{ + return 0; +} + +/** + * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. + * @div: The divisor to calculate the bit information for. + * + * Turn a divisor into the necessary bit field for TCFG1. + */ +static inline unsigned long pwm_tdiv_div_bits(unsigned int div) +{ + return ilog2(div) - 1; +} + +#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h new file mode 100644 index 0000000..fef8ea8 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/map.h @@ -0,0 +1,99 @@ +/* linux/include/asm-arm/plat-s3c24xx/map.h + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24XX - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S3C24XX_MAP_H +#define __ASM_PLAT_S3C24XX_MAP_H + +/* interrupt controller is the first thing we put in, to make + * the assembly code for the irq detection easier + */ +#define S3C24XX_VA_IRQ S3C_VA_IRQ +#define S3C2410_PA_IRQ (0x4A000000) +#define S3C24XX_SZ_IRQ SZ_1M + +/* memory controller registers */ +#define S3C24XX_VA_MEMCTRL S3C_VA_MEM +#define S3C2410_PA_MEMCTRL (0x48000000) +#define S3C24XX_SZ_MEMCTRL SZ_1M + +/* UARTs */ +#define S3C24XX_VA_UART S3C_VA_UART +#define S3C2410_PA_UART (0x50000000) +#define S3C24XX_SZ_UART SZ_1M +#define S3C_UART_OFFSET (0x4000) + +/* Timers */ +#define S3C24XX_VA_TIMER S3C_VA_TIMER +#define S3C2410_PA_TIMER (0x51000000) +#define S3C24XX_SZ_TIMER SZ_1M + +/* Clock and Power management */ +#define S3C24XX_VA_CLKPWR S3C_VA_SYS +#define S3C24XX_SZ_CLKPWR SZ_1M + +/* USB Device port */ +#define S3C2410_PA_USBDEV (0x52000000) +#define S3C24XX_SZ_USBDEV SZ_1M + +/* Watchdog */ +#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG +#define S3C2410_PA_WATCHDOG (0x53000000) +#define S3C24XX_SZ_WATCHDOG SZ_1M + +/* Standard size definitions for peripheral blocks. */ + +#define S3C24XX_SZ_IIS SZ_1M +#define S3C24XX_SZ_ADC SZ_1M +#define S3C24XX_SZ_SPI SZ_1M +#define S3C24XX_SZ_SDI SZ_1M +#define S3C24XX_SZ_NAND SZ_1M +#define S3C24XX_SZ_USBHOST SZ_1M + +/* GPIO ports */ + +/* the calculation for the VA of this must ensure that + * it is the same distance apart from the UART in the + * phsyical address space, as the initial mapping for the IO + * is done as a 1:1 maping. This puts it (currently) at + * 0xFA800000, which is not in the way of any current mapping + * by the base system. +*/ + +#define S3C2410_PA_GPIO (0x56000000) +#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) +#define S3C24XX_SZ_GPIO SZ_1M + + +/* ISA style IO, for each machine to sort out mappings for, if it + * implements it. We reserve two 16M regions for ISA. + */ + +#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) +#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) + +/* deal with the registers that move under the 2412/2413 */ + +#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) +#ifndef __ASSEMBLY__ +extern void __iomem *s3c24xx_va_gpio2; +#endif +#ifdef CONFIG_CPU_S3C2412_ONLY +#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) +#else +#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 +#endif +#else +#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO +#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO +#endif + +#endif /* __ASM_PLAT_S3C24XX_MAP_H */ diff --git a/include/asm-arm/plat-s3c24xx/mci.h b/arch/arm/plat-s3c24xx/include/plat/mci.h index 2d0852a..2d0852a 100644 --- a/include/asm-arm/plat-s3c24xx/mci.h +++ b/arch/arm/plat-s3c24xx/include/plat/mci.h diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h new file mode 100644 index 0000000..7ea8bff --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/pll.h @@ -0,0 +1,37 @@ +/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C24xx - common pll registers and code + */ + +#define S3C24XX_PLLCON_MDIVSHIFT 12 +#define S3C24XX_PLLCON_PDIVSHIFT 4 +#define S3C24XX_PLLCON_SDIVSHIFT 0 +#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) +#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1) +#define S3C24XX_PLLCON_SDIVMASK 3 + +#include <asm/div64.h> + +static inline unsigned int +s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk) +{ + unsigned int mdiv, pdiv, sdiv; + uint64_t fvco; + + mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT; + pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT; + sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT; + + mdiv &= S3C24XX_PLLCON_MDIVMASK; + pdiv &= S3C24XX_PLLCON_PDIVMASK; + sdiv &= S3C24XX_PLLCON_SDIVMASK; + + fvco = (uint64_t)baseclk * (mdiv + 8); + do_div(fvco, (pdiv + 2) << sdiv); + + return (unsigned int)fvco; +} diff --git a/include/asm-arm/plat-s3c24xx/regs-spi.h b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h index 2b35479..2b35479 100644 --- a/include/asm-arm/plat-s3c24xx/regs-spi.h +++ b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h diff --git a/include/asm-arm/plat-s3c24xx/regs-udc.h b/arch/arm/plat-s3c24xx/include/plat/regs-udc.h index f0dd4a4..f0dd4a4 100644 --- a/include/asm-arm/plat-s3c24xx/regs-udc.h +++ b/arch/arm/plat-s3c24xx/include/plat/regs-udc.h diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h b/arch/arm/plat-s3c24xx/include/plat/s3c2400.h index 3a5a168..b3feaea 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2400.h @@ -17,7 +17,7 @@ extern int s3c2400_init(void); -extern void s3c2400_map_io(struct map_desc *mach_desc, int size); +extern void s3c2400_map_io(void); extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no); diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h index 3cd1ec6..a9ac9e2 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h @@ -15,7 +15,7 @@ extern int s3c2410_init(void); -extern void s3c2410_map_io(struct map_desc *mach_desc, int size); +extern void s3c2410_map_io(void); extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2412.h b/arch/arm/plat-s3c24xx/include/plat/s3c2412.h index 3ec9768..bb15d3b 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2412.h +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2412.h @@ -14,7 +14,7 @@ extern int s3c2412_init(void); -extern void s3c2412_map_io(struct map_desc *mach_desc, int size); +extern void s3c2412_map_io(void); extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h index 11d83b5..815b107 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h @@ -16,7 +16,7 @@ struct s3c2410_uartcfg; extern int s3c2443_init(void); -extern void s3c2443_map_io(struct map_desc *mach_desc, int size); +extern void s3c2443_map_io(void); extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); diff --git a/include/asm-arm/plat-s3c24xx/udc.h b/arch/arm/plat-s3c24xx/include/plat/udc.h index 546bb40..546bb40 100644 --- a/include/asm-arm/plat-s3c24xx/udc.h +++ b/arch/arm/plat-s3c24xx/include/plat/udc.h diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index 963f7a4..0192ecd 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c @@ -62,6 +62,7 @@ #include <asm/mach/irq.h> +#include <plat/regs-irqtype.h> #include <mach/regs-irq.h> #include <mach/regs-gpio.h> diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c index 8efb57a..34ef18e 100644 --- a/arch/arm/plat-s3c24xx/pm.c +++ b/arch/arm/plat-s3c24xx/pm.c @@ -33,7 +33,6 @@ #include <linux/interrupt.h> #include <linux/crc32.h> #include <linux/ioport.h> -#include <linux/delay.h> #include <linux/serial_core.h> #include <linux/io.h> @@ -76,11 +75,13 @@ static struct sleep_save core_save[] = { SAVE_ITEM(S3C2410_BANKCON4), SAVE_ITEM(S3C2410_BANKCON5), +#ifndef CONFIG_CPU_FREQ SAVE_ITEM(S3C2410_CLKDIVN), SAVE_ITEM(S3C2410_MPLLCON), + SAVE_ITEM(S3C2410_REFRESH), +#endif SAVE_ITEM(S3C2410_UPLLCON), SAVE_ITEM(S3C2410_CLKSLOW), - SAVE_ITEM(S3C2410_REFRESH), }; static struct gpio_sleep { diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c index 4e07943..b61bdb7 100644 --- a/arch/arm/mach-s3c2410/clock.c +++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c @@ -272,5 +272,6 @@ int __init s3c2410_baseclk_add(void) (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on", (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on"); + s3c_pwmclk_init(); return 0; } diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c index 7c09773..dde41f17 100644 --- a/arch/arm/plat-s3c24xx/s3c244x-clock.c +++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c @@ -31,7 +31,6 @@ #include <linux/sysdev.h> #include <linux/interrupt.h> #include <linux/ioport.h> -#include <linux/mutex.h> #include <linux/clk.h> #include <linux/io.h> @@ -102,13 +101,13 @@ static int s3c244x_clk_add(struct sys_device *sysdev) if (clk_get_rate(clock_upll) > (94 * MHZ)) { clk_usb_bus.rate = clk_get_rate(clock_upll) / 2; - mutex_lock(&clocks_mutex); + spin_lock(&clocks_lock); clkdivn = __raw_readl(S3C2410_CLKDIVN); clkdivn |= S3C2440_CLKDIVN_UCLK; __raw_writel(clkdivn, S3C2410_CLKDIVN); - mutex_unlock(&clocks_mutex); + spin_unlock(&clocks_lock); } return 0; diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c index c0344fa..c1de6bb 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.c +++ b/arch/arm/plat-s3c24xx/s3c244x.c @@ -29,6 +29,8 @@ #include <mach/hardware.h> #include <asm/irq.h> +#include <plat/cpu-freq.h> + #include <mach/regs-clock.h> #include <plat/regs-serial.h> #include <mach/regs-gpio.h> @@ -42,6 +44,7 @@ #include <plat/devs.h> #include <plat/cpu.h> #include <plat/pm.h> +#include <plat/pll.h> static struct map_desc s3c244x_iodesc[] __initdata = { IODESC_ENT(CLKPWR), @@ -56,32 +59,34 @@ void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no) s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no); } -void __init s3c244x_map_io(struct map_desc *mach_desc, int size) +void __init s3c244x_map_io(void) { /* register our io-tables */ iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc)); - iotable_init(mach_desc, size); /* rename any peripherals used differing from the s3c2410 */ s3c_device_sdi.name = "s3c2440-sdi"; - s3c_device_i2c.name = "s3c2440-i2c"; + s3c_device_i2c0.name = "s3c2440-i2c"; s3c_device_nand.name = "s3c2440-nand"; s3c_device_usbgadget.name = "s3c2440-usbgadget"; } -void __init s3c244x_init_clocks(int xtal) +void __init_or_cpufreq s3c244x_setup_clocks(void) { + struct clk *xtal_clk; unsigned long clkdiv; unsigned long camdiv; + unsigned long xtal; unsigned long hclk, fclk, pclk; int hdiv = 1; - /* now we've got our machine bits initialised, work out what - * clocks we've got */ + xtal_clk = clk_get(NULL, "xtal"); + xtal = clk_get_rate(xtal_clk); + clk_put(xtal_clk); - fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; + fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; clkdiv = __raw_readl(S3C2410_CLKDIVN); camdiv = __raw_readl(S3C2440_CAMDIVN); @@ -107,18 +112,24 @@ void __init s3c244x_init_clocks(int xtal) } hclk = fclk / hdiv; - pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1); + pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1); /* print brief summary of clocks, etc */ printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); + s3c24xx_setup_clocks(fclk, hclk, pclk); +} + +void __init s3c244x_init_clocks(int xtal) +{ /* initialise the clocks here, to allow other things like the * console to use them, and to add new ones after the initialisation */ - s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); + s3c24xx_register_baseclocks(xtal); + s3c244x_setup_clocks(); s3c2410_baseclk_add(); } diff --git a/arch/arm/plat-s3c24xx/s3c244x.h b/arch/arm/plat-s3c24xx/s3c244x.h index f8ed176..6aab5ea 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.h +++ b/arch/arm/plat-s3c24xx/s3c244x.h @@ -12,7 +12,7 @@ #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) -extern void s3c244x_map_io(struct map_desc *mach_desc, int size); +extern void s3c244x_map_io(void); extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c new file mode 100644 index 0000000..d62b7e7 --- /dev/null +++ b/arch/arm/plat-s3c24xx/setup-i2c.c @@ -0,0 +1,25 @@ +/* linux/arch/arm/plat-s3c24xx/setup-i2c.c + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24XX Base setup for i2c device + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> + +struct platform_device; + +#include <plat/iic.h> +#include <mach/hardware.h> +#include <mach/regs-gpio.h> + +void s3c_i2c0_cfg_gpio(struct platform_device *dev) +{ + s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA); + s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL); +} diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c new file mode 100644 index 0000000..8b403cb --- /dev/null +++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c @@ -0,0 +1,37 @@ +/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24XX SPI - gpio configuration for bus 0 on gpe11,12,13 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. +*/ + +#include <linux/kernel.h> + +#include <mach/hardware.h> + +#include <mach/spi.h> +#include <mach/regs-gpio.h> + +void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, + int enable) +{ + if (enable) { + s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0); + s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0); + s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0); + s3c2410_gpio_pullup(S3C2410_GPE11, 0); + s3c2410_gpio_pullup(S3C2410_GPE13, 0); + } else { + s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT); + s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT); + s3c2410_gpio_pullup(S3C2410_GPE11, 1); + s3c2410_gpio_pullup(S3C2410_GPE12, 1); + s3c2410_gpio_pullup(S3C2410_GPE13, 1); + } +} diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c new file mode 100644 index 0000000..8fccd4e --- /dev/null +++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c @@ -0,0 +1,37 @@ +/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpg5_6_7.c + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24XX SPI - gpio configuration for bus 1 on gpg5,6,7 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. +*/ + +#include <linux/kernel.h> + +#include <mach/hardware.h> + +#include <mach/spi.h> +#include <mach/regs-gpio.h> + +void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, + int enable) +{ + if (enable) { + s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1); + s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1); + s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1); + s3c2410_gpio_pullup(S3C2410_GPG5, 0); + s3c2410_gpio_pullup(S3C2410_GPG6, 0); + } else { + s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT); + s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT); + s3c2410_gpio_pullup(S3C2410_GPG5, 1); + s3c2410_gpio_pullup(S3C2410_GPG6, 1); + s3c2410_gpio_pullup(S3C2410_GPG7, 1); + } +} diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig new file mode 100644 index 0000000..54375a0 --- /dev/null +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -0,0 +1,62 @@ +# arch/arm/plat-s3c64xx/Kconfig +# +# Copyright 2008 Openmoko, Inc. +# Copyright 2008 Simtec Electronics +# Ben Dooks <ben@simtec.co.uk> +# +# Licensed under GPLv2 + +config PLAT_S3C64XX + bool + depends on ARCH_S3C64XX + default y + select CPU_V6 + select PLAT_S3C + select ARM_VIC + select NO_IOPORT + select ARCH_REQUIRE_GPIOLIB + select S3C_GPIO_TRACK + select S3C_GPIO_PULL_UPDOWN + select S3C_GPIO_CFG_S3C24XX + select S3C_GPIO_CFG_S3C64XX + help + Base platform code for any Samsung S3C64XX device + +if PLAT_S3C64XX + +# Configuration options shared by all S3C64XX implementations + +config CPU_S3C6400_INIT + bool + help + Common initialisation code for the S3C6400 that is shared + by other CPUs in the series, such as the S3C6410. + +config CPU_S3C6400_CLOCK + bool + help + Common clock support code for the S3C6400 that is shared + by other CPUs in the series, such as the S3C6410. + +# platform specific device setup + +config S3C64XX_SETUP_I2C0 + bool + default y + help + Common setup code for i2c bus 0. + + Note, currently since i2c0 is always compiled, this setup helper + is always compiled with it. + +config S3C64XX_SETUP_I2C1 + bool + help + Common setup code for i2c bus 1. + +config S3C64XX_SETUP_FB_24BPP + bool + help + Common setup code for S3C64XX with an 24bpp RGB display helper. + +endif diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile new file mode 100644 index 0000000..2e6d79b --- /dev/null +++ b/arch/arm/plat-s3c64xx/Makefile @@ -0,0 +1,31 @@ +# arch/arm/plat-s3c64xx/Makefile +# +# Copyright 2008 Openmoko, Inc. +# Copyright 2008 Simtec Electronics +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := dummy.o +obj- := + +# Core files + +obj-y += dev-uart.o +obj-y += cpu.o +obj-y += irq.o +obj-y += irq-eint.o +obj-y += clock.o +obj-y += gpiolib.o + +# CPU support + +obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o +obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o + +# Device setup + +obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o +obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o +obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c new file mode 100644 index 0000000..136c982 --- /dev/null +++ b/arch/arm/plat-s3c64xx/clock.c @@ -0,0 +1,281 @@ +/* linux/arch/arm/plat-s3c64xx/clock.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX Base clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/io.h> + +#include <mach/hardware.h> +#include <mach/map.h> + +#include <plat/regs-sys.h> +#include <plat/regs-clock.h> +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/clock.h> + +struct clk clk_27m = { + .name = "clk_27m", + .id = -1, + .rate = 27000000, +}; + +static int clk_48m_ctrl(struct clk *clk, int enable) +{ + unsigned long flags; + u32 val; + + /* can't rely on clock lock, this register has other usages */ + local_irq_save(flags); + + val = __raw_readl(S3C64XX_OTHERS); + if (enable) + val |= S3C64XX_OTHERS_USBMASK; + else + val &= ~S3C64XX_OTHERS_USBMASK; + + __raw_writel(val, S3C64XX_OTHERS); + local_irq_restore(flags); + + return 0; +} + +struct clk clk_48m = { + .name = "clk_48m", + .id = -1, + .rate = 48000000, + .enable = clk_48m_ctrl, +}; + +static int inline s3c64xx_gate(void __iomem *reg, + struct clk *clk, + int enable) +{ + unsigned int ctrlbit = clk->ctrlbit; + u32 con; + + con = __raw_readl(reg); + + if (enable) + con |= ctrlbit; + else + con &= ~ctrlbit; + + __raw_writel(con, reg); + return 0; +} + +static int s3c64xx_pclk_ctrl(struct clk *clk, int enable) +{ + return s3c64xx_gate(S3C_PCLK_GATE, clk, enable); +} + +static int s3c64xx_hclk_ctrl(struct clk *clk, int enable) +{ + return s3c64xx_gate(S3C_HCLK_GATE, clk, enable); +} + +int s3c64xx_sclk_ctrl(struct clk *clk, int enable) +{ + return s3c64xx_gate(S3C_SCLK_GATE, clk, enable); +} + +static struct clk init_clocks_disable[] = { + { + .name = "nand", + .id = -1, + .parent = &clk_h, + }, { + .name = "adc", + .id = -1, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_TSADC, + }, { + .name = "i2c", + .id = -1, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_IIC, + }, { + .name = "iis", + .id = 0, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_IIS0, + }, { + .name = "iis", + .id = 1, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_IIS1, + }, { + .name = "spi", + .id = 0, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_SPI0, + }, { + .name = "spi", + .id = 1, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_SPI1, + }, { + .name = "48m", + .id = 0, + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, + }, { + .name = "48m", + .id = 1, + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, + }, { + .name = "48m", + .id = 2, + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, + }, +}; + +static struct clk init_clocks[] = { + { + .name = "lcd", + .id = -1, + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_LCD, + }, { + .name = "gpio", + .id = -1, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_GPIO, + }, { + .name = "usb-host", + .id = -1, + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_UHOST, + }, { + .name = "hsmmc", + .id = 0, + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, + }, { + .name = "hsmmc", + .id = 1, + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, + }, { + .name = "hsmmc", + .id = 2, + .parent = &clk_h, + .enable = s3c64xx_hclk_ctrl, + .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, + }, { + .name = "timers", + .id = -1, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_PWM, + }, { + .name = "uart", + .id = 0, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_UART0, + }, { + .name = "uart", + .id = 1, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_UART1, + }, { + .name = "uart", + .id = 2, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_UART2, + }, { + .name = "uart", + .id = 3, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_UART3, + }, { + .name = "rtc", + .id = -1, + .parent = &clk_p, + .enable = s3c64xx_pclk_ctrl, + .ctrlbit = S3C_CLKCON_PCLK_RTC, + }, { + .name = "watchdog", + .id = -1, + .parent = &clk_p, + .ctrlbit = S3C_CLKCON_PCLK_WDT, + }, { + .name = "ac97", + .id = -1, + .parent = &clk_p, + .ctrlbit = S3C_CLKCON_PCLK_AC97, + } +}; + +static struct clk *clks[] __initdata = { + &clk_ext, + &clk_epll, + &clk_27m, + &clk_48m, +}; + +void s3c64xx_register_clocks(void) +{ + struct clk *clkp; + int ret; + int ptr; + + s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); + + clkp = init_clocks; + for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + } + + clkp = init_clocks_disable; + for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { + + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + + (clkp->enable)(clkp, 0); + } + + s3c_pwmclk_init(); +} diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c new file mode 100644 index 0000000..fbde183 --- /dev/null +++ b/arch/arm/plat-s3c64xx/cpu.c @@ -0,0 +1,114 @@ +/* linux/arch/arm/plat-s3c64xx/cpu.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX CPU Support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <mach/hardware.h> +#include <mach/map.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <plat/regs-serial.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/clock.h> + +#include <plat/s3c6400.h> +#include <plat/s3c6410.h> + +/* table of supported CPUs */ + +static const char name_s3c6400[] = "S3C6400"; +static const char name_s3c6410[] = "S3C6410"; + +static struct cpu_table cpu_ids[] __initdata = { + { + .idcode = 0x36400000, + .idmask = 0xfffff000, + .map_io = s3c6400_map_io, + .init_clocks = s3c6400_init_clocks, + .init_uarts = s3c6400_init_uarts, + .init = s3c6400_init, + .name = name_s3c6400, + }, { + .idcode = 0x36410100, + .idmask = 0xffffff00, + .map_io = s3c6410_map_io, + .init_clocks = s3c6410_init_clocks, + .init_uarts = s3c6410_init_uarts, + .init = s3c6410_init, + .name = name_s3c6410, + }, +}; + +/* minimal IO mapping */ + +/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */ +#define UART_OFFS (S3C_PA_UART & 0xfffff) + +static struct map_desc s3c_iodesc[] __initdata = { + { + .virtual = (unsigned long)S3C_VA_SYS, + .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS), + .pfn = __phys_to_pfn(S3C_PA_UART), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_VIC0, + .pfn = __phys_to_pfn(S3C64XX_PA_VIC0), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_VIC1, + .pfn = __phys_to_pfn(S3C64XX_PA_VIC1), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_TIMER, + .pfn = __phys_to_pfn(S3C_PA_TIMER), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C64XX_VA_GPIO, + .pfn = __phys_to_pfn(S3C64XX_PA_GPIO), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +/* read cpu identification code */ + +void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) +{ + unsigned long idcode; + + /* initialise the io descriptors we need for initialisation */ + iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); + iotable_init(mach_desc, size); + + idcode = __raw_readl(S3C_VA_SYS + 0x118); + s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); +} diff --git a/arch/arm/plat-s3c64xx/dev-uart.c b/arch/arm/plat-s3c64xx/dev-uart.c new file mode 100644 index 0000000..62c11a6 --- /dev/null +++ b/arch/arm/plat-s3c64xx/dev-uart.c @@ -0,0 +1,176 @@ +/* linux/arch/arm/plat-s3c64xx/dev-uart.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Base S3C64XX UART resource and device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/platform_device.h> + +#include <asm/mach/arch.h> +#include <asm/mach/irq.h> +#include <mach/hardware.h> +#include <mach/map.h> + +#include <plat/devs.h> + +/* Serial port registrations */ + +/* 64xx uarts are closer together */ + +static struct resource s3c64xx_uart0_resource[] = { + [0] = { + .start = S3C_PA_UART0, + .end = S3C_PA_UART0 + 0x100, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3CUART_RX0, + .end = IRQ_S3CUART_RX0, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S3CUART_TX0, + .end = IRQ_S3CUART_TX0, + .flags = IORESOURCE_IRQ, + + }, + [3] = { + .start = IRQ_S3CUART_ERR0, + .end = IRQ_S3CUART_ERR0, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource s3c64xx_uart1_resource[] = { + [0] = { + .start = S3C_PA_UART1, + .end = S3C_PA_UART1 + 0x100, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3CUART_RX1, + .end = IRQ_S3CUART_RX1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S3CUART_TX1, + .end = IRQ_S3CUART_TX1, + .flags = IORESOURCE_IRQ, + + }, + [3] = { + .start = IRQ_S3CUART_ERR1, + .end = IRQ_S3CUART_ERR1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource s3c6xx_uart2_resource[] = { + [0] = { + .start = S3C_PA_UART2, + .end = S3C_PA_UART2 + 0x100, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3CUART_RX2, + .end = IRQ_S3CUART_RX2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S3CUART_TX2, + .end = IRQ_S3CUART_TX2, + .flags = IORESOURCE_IRQ, + + }, + [3] = { + .start = IRQ_S3CUART_ERR2, + .end = IRQ_S3CUART_ERR2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource s3c64xx_uart3_resource[] = { + [0] = { + .start = S3C_PA_UART3, + .end = S3C_PA_UART3 + 0x100, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3CUART_RX3, + .end = IRQ_S3CUART_RX3, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S3CUART_TX3, + .end = IRQ_S3CUART_TX3, + .flags = IORESOURCE_IRQ, + + }, + [3] = { + .start = IRQ_S3CUART_ERR3, + .end = IRQ_S3CUART_ERR3, + .flags = IORESOURCE_IRQ, + }, +}; + + +struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = { + [0] = { + .resources = s3c64xx_uart0_resource, + .nr_resources = ARRAY_SIZE(s3c64xx_uart0_resource), + }, + [1] = { + .resources = s3c64xx_uart1_resource, + .nr_resources = ARRAY_SIZE(s3c64xx_uart1_resource), + }, + [2] = { + .resources = s3c6xx_uart2_resource, + .nr_resources = ARRAY_SIZE(s3c6xx_uart2_resource), + }, + [3] = { + .resources = s3c64xx_uart3_resource, + .nr_resources = ARRAY_SIZE(s3c64xx_uart3_resource), + }, +}; + +/* uart devices */ + +static struct platform_device s3c24xx_uart_device0 = { + .id = 0, +}; + +static struct platform_device s3c24xx_uart_device1 = { + .id = 1, +}; + +static struct platform_device s3c24xx_uart_device2 = { + .id = 2, +}; + +static struct platform_device s3c24xx_uart_device3 = { + .id = 3, +}; + +struct platform_device *s3c24xx_uart_src[4] = { + &s3c24xx_uart_device0, + &s3c24xx_uart_device1, + &s3c24xx_uart_device2, + &s3c24xx_uart_device3, +}; + +struct platform_device *s3c24xx_uart_devs[4] = { +}; + diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c new file mode 100644 index 0000000..cc62941 --- /dev/null +++ b/arch/arm/plat-s3c64xx/gpiolib.c @@ -0,0 +1,420 @@ +/* arch/arm/plat-s3c64xx/gpiolib.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - GPIOlib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <mach/map.h> +#include <mach/gpio.h> +#include <mach/gpio-core.h> + +#include <plat/gpio-cfg.h> +#include <plat/gpio-cfg-helpers.h> +#include <plat/regs-gpio.h> + +/* GPIO bank summary: + * + * Bank GPIOs Style SlpCon ExtInt Group + * A 8 4Bit Yes 1 + * B 7 4Bit Yes 1 + * C 8 4Bit Yes 2 + * D 5 4Bit Yes 3 + * E 5 4Bit Yes None + * F 16 2Bit Yes 4 [1] + * G 7 4Bit Yes 5 + * H 10 4Bit[2] Yes 6 + * I 16 2Bit Yes None + * J 12 2Bit Yes None + * K 16 4Bit[2] No None + * L 15 4Bit[2] No None + * M 6 4Bit No IRQ_EINT + * N 16 2Bit No IRQ_EINT + * O 16 2Bit Yes 7 + * P 15 2Bit Yes 8 + * Q 9 2Bit Yes 9 + * + * [1] BANKF pins 14,15 do not form part of the external interrupt sources + * [2] BANK has two control registers, GPxCON0 and GPxCON1 + */ + +#define OFF_GPCON (0x00) +#define OFF_GPDAT (0x04) + +#define con_4bit_shift(__off) ((__off) * 4) + +#if 1 +#define gpio_dbg(x...) do { } while(0) +#else +#define gpio_dbg(x...) printk(KERN_DEBUG ## x) +#endif + +/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where + * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the + * following example: + * + * base + 0x00: Control register, 4 bits per gpio + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x04: Data register, 1 bit per gpio + * bit n: data bit n + * + * Note, since the data register is one bit per gpio and is at base + 0x4 + * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of + * the output. +*/ + +static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long con; + + con = __raw_readl(base + OFF_GPCON); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, base + OFF_GPCON); + + gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); + + return 0; +} + +static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long con; + unsigned long dat; + + con = __raw_readl(base + OFF_GPCON); + con &= ~(0xf << con_4bit_shift(offset)); + con |= 0x1 << con_4bit_shift(offset); + + dat = __raw_readl(base + OFF_GPDAT); + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(dat, base + OFF_GPDAT); + __raw_writel(con, base + OFF_GPCON); + __raw_writel(dat, base + OFF_GPDAT); + + gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); + + return 0; +} + +/* The next set of routines are for the case where the GPIO configuration + * registers are 4 bits per GPIO but there is more than one register (the + * bank has more than 8 GPIOs. + * + * This case is the similar to the 4 bit case, but the registers are as + * follows: + * + * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x08: Data register, 1 bit per gpio + * bit n: data bit n + * + * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we + * store the 'base + 0x4' address so that these routines see the data + * register at ourchip->base + 0x04. +*/ + +static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + + if (offset > 7) + offset -= 8; + else + regcon -= 4; + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, regcon); + + gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); + + return 0; + +} + +static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + unsigned long dat; + + if (offset > 7) + offset -= 8; + else + regcon -= 4; + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(offset)); + con |= 0x1 << con_4bit_shift(offset); + + dat = __raw_readl(base + OFF_GPDAT); + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(dat, base + OFF_GPDAT); + __raw_writel(con, regcon); + __raw_writel(dat, base + OFF_GPDAT); + + gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); + + return 0; +} + +static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = { + .cfg_eint = 7, + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = { + .cfg_eint = 3, + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_chip gpio_4bit[] = { + { + .base = S3C64XX_GPA_BASE, + .config = &gpio_4bit_cfg_eint0111, + .chip = { + .base = S3C64XX_GPA(0), + .ngpio = S3C64XX_GPIO_A_NR, + .label = "GPA", + }, + }, { + .base = S3C64XX_GPB_BASE, + .config = &gpio_4bit_cfg_eint0111, + .chip = { + .base = S3C64XX_GPB(0), + .ngpio = S3C64XX_GPIO_B_NR, + .label = "GPB", + }, + }, { + .base = S3C64XX_GPC_BASE, + .config = &gpio_4bit_cfg_eint0111, + .chip = { + .base = S3C64XX_GPC(0), + .ngpio = S3C64XX_GPIO_C_NR, + .label = "GPC", + }, + }, { + .base = S3C64XX_GPD_BASE, + .config = &gpio_4bit_cfg_eint0111, + .chip = { + .base = S3C64XX_GPD(0), + .ngpio = S3C64XX_GPIO_D_NR, + .label = "GPD", + }, + }, { + .base = S3C64XX_GPE_BASE, + .config = &gpio_4bit_cfg_noint, + .chip = { + .base = S3C64XX_GPE(0), + .ngpio = S3C64XX_GPIO_E_NR, + .label = "GPE", + }, + }, { + .base = S3C64XX_GPG_BASE, + .config = &gpio_4bit_cfg_eint0111, + .chip = { + .base = S3C64XX_GPG(0), + .ngpio = S3C64XX_GPIO_G_NR, + .label = "GPG", + }, + }, { + .base = S3C64XX_GPM_BASE, + .config = &gpio_4bit_cfg_eint0011, + .chip = { + .base = S3C64XX_GPM(0), + .ngpio = S3C64XX_GPIO_M_NR, + .label = "GPM", + }, + }, +}; + +static struct s3c_gpio_chip gpio_4bit2[] = { + { + .base = S3C64XX_GPH_BASE + 0x4, + .config = &gpio_4bit_cfg_eint0111, + .chip = { + .base = S3C64XX_GPH(0), + .ngpio = S3C64XX_GPIO_H_NR, + .label = "GPH", + }, + }, { + .base = S3C64XX_GPK_BASE + 0x4, + .config = &gpio_4bit_cfg_noint, + .chip = { + .base = S3C64XX_GPK(0), + .ngpio = S3C64XX_GPIO_K_NR, + .label = "GPK", + }, + }, { + .base = S3C64XX_GPL_BASE + 0x4, + .config = &gpio_4bit_cfg_eint0011, + .chip = { + .base = S3C64XX_GPL(0), + .ngpio = S3C64XX_GPIO_L_NR, + .label = "GPL", + }, + }, +}; + +static struct s3c_gpio_cfg gpio_2bit_cfg_noint = { + .set_config = s3c_gpio_setcfg_s3c24xx, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = { + .cfg_eint = 2, + .set_config = s3c_gpio_setcfg_s3c24xx, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { + .cfg_eint = 3, + .set_config = s3c_gpio_setcfg_s3c24xx, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_chip gpio_2bit[] = { + { + .base = S3C64XX_GPF_BASE, + .config = &gpio_2bit_cfg_eint11, + .chip = { + .base = S3C64XX_GPF(0), + .ngpio = S3C64XX_GPIO_F_NR, + .label = "GPF", + }, + }, { + .base = S3C64XX_GPI_BASE, + .config = &gpio_2bit_cfg_noint, + .chip = { + .base = S3C64XX_GPI(0), + .ngpio = S3C64XX_GPIO_I_NR, + .label = "GPI", + }, + }, { + .base = S3C64XX_GPJ_BASE, + .config = &gpio_2bit_cfg_noint, + .chip = { + .base = S3C64XX_GPJ(0), + .ngpio = S3C64XX_GPIO_J_NR, + .label = "GPJ", + }, + }, { + .base = S3C64XX_GPN_BASE, + .config = &gpio_2bit_cfg_eint10, + .chip = { + .base = S3C64XX_GPN(0), + .ngpio = S3C64XX_GPIO_N_NR, + .label = "GPN", + }, + }, { + .base = S3C64XX_GPO_BASE, + .config = &gpio_2bit_cfg_eint11, + .chip = { + .base = S3C64XX_GPO(0), + .ngpio = S3C64XX_GPIO_O_NR, + .label = "GPO", + }, + }, { + .base = S3C64XX_GPP_BASE, + .config = &gpio_2bit_cfg_eint11, + .chip = { + .base = S3C64XX_GPP(0), + .ngpio = S3C64XX_GPIO_P_NR, + .label = "GPP", + }, + }, { + .base = S3C64XX_GPQ_BASE, + .config = &gpio_2bit_cfg_eint11, + .chip = { + .base = S3C64XX_GPQ(0), + .ngpio = S3C64XX_GPIO_Q_NR, + .label = "GPQ", + }, + }, +}; + +static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip) +{ + chip->chip.direction_input = s3c64xx_gpiolib_4bit_input; + chip->chip.direction_output = s3c64xx_gpiolib_4bit_output; +} + +static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) +{ + chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input; + chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output; +} + +static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips, + int nr_chips, + void (*fn)(struct s3c_gpio_chip *)) +{ + for (; nr_chips > 0; nr_chips--, chips++) { + if (fn) + (fn)(chips); + s3c_gpiolib_add(chips); + } +} + +static __init int s3c64xx_gpiolib_init(void) +{ + s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit), + s3c64xx_gpiolib_add_4bit); + + s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), + s3c64xx_gpiolib_add_4bit2); + + s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL); + + return 0; +} + +arch_initcall(s3c64xx_gpiolib_init); diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h new file mode 100644 index 0000000..9aa0e42 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h @@ -0,0 +1,48 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank A register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPACON (S3C64XX_GPA_BASE + 0x00) +#define S3C64XX_GPADAT (S3C64XX_GPA_BASE + 0x04) +#define S3C64XX_GPAPUD (S3C64XX_GPA_BASE + 0x08) +#define S3C64XX_GPACONSLP (S3C64XX_GPA_BASE + 0x0c) +#define S3C64XX_GPAPUDSLP (S3C64XX_GPA_BASE + 0x10) + +#define S3C64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPA0_UART_RXD0 (0x02 << 0) +#define S3C64XX_GPA0_EINT_G1_0 (0x07 << 0) + +#define S3C64XX_GPA1_UART_TXD0 (0x02 << 4) +#define S3C64XX_GPA1_EINT_G1_1 (0x07 << 4) + +#define S3C64XX_GPA2_UART_nCTS0 (0x02 << 8) +#define S3C64XX_GPA2_EINT_G1_2 (0x07 << 8) + +#define S3C64XX_GPA3_UART_nRTS0 (0x02 << 12) +#define S3C64XX_GPA3_EINT_G1_3 (0x07 << 12) + +#define S3C64XX_GPA4_UART_RXD1 (0x02 << 16) +#define S3C64XX_GPA4_EINT_G1_4 (0x07 << 16) + +#define S3C64XX_GPA5_UART_TXD1 (0x02 << 20) +#define S3C64XX_GPA5_EINT_G1_5 (0x07 << 20) + +#define S3C64XX_GPA6_UART_nCTS1 (0x02 << 24) +#define S3C64XX_GPA6_EINT_G1_6 (0x07 << 24) + +#define S3C64XX_GPA7_UART_nRTS1 (0x02 << 28) +#define S3C64XX_GPA7_EINT_G1_7 (0x07 << 28) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h new file mode 100644 index 0000000..3933adb --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h @@ -0,0 +1,60 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank B register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00) +#define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04) +#define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08) +#define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c) +#define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10) + +#define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPB0_UART_RXD2 (0x02 << 0) +#define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0) +#define S3C64XX_GPB0_IrDA_RXD (0x04 << 0) +#define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0) +#define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0) + +#define S3C64XX_GPB1_UART_TXD2 (0x02 << 4) +#define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4) +#define S3C64XX_GPB1_IrDA_TXD (0x04 << 4) +#define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4) +#define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4) + +#define S3C64XX_GPB2_UART_RXD3 (0x02 << 8) +#define S3C64XX_GPB2_IrDA_RXD (0x03 << 8) +#define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8) +#define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8) +#define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8) +#define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8) + +#define S3C64XX_GPB3_UART_TXD3 (0x02 << 12) +#define S3C64XX_GPB3_IrDA_TXD (0x03 << 12) +#define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12) +#define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12) +#define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12) + +#define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16) +#define S3C64XX_GPB4_CAM_FIELD (0x03 << 16) +#define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16) +#define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16) + +#define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20) +#define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20) + +#define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24) +#define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h new file mode 100644 index 0000000..c47daf7 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h @@ -0,0 +1,53 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank C register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPCCON (S3C64XX_GPC_BASE + 0x00) +#define S3C64XX_GPCDAT (S3C64XX_GPC_BASE + 0x04) +#define S3C64XX_GPCPUD (S3C64XX_GPC_BASE + 0x08) +#define S3C64XX_GPCCONSLP (S3C64XX_GPC_BASE + 0x0c) +#define S3C64XX_GPCPUDSLP (S3C64XX_GPC_BASE + 0x10) + +#define S3C64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPC0_SPI_MISO0 (0x02 << 0) +#define S3C64XX_GPC0_EINT_G2_0 (0x07 << 0) + +#define S3C64XX_GPC1_SPI_CLKO (0x02 << 4) +#define S3C64XX_GPC1_EINT_G2_1 (0x07 << 4) + +#define S3C64XX_GPC2_SPI_MOSIO (0x02 << 8) +#define S3C64XX_GPC2_EINT_G2_2 (0x07 << 8) + +#define S3C64XX_GPC3_SPI_nCSO (0x02 << 12) +#define S3C64XX_GPC3_EINT_G2_3 (0x07 << 12) + +#define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16) +#define S3C64XX_GPC4_MMC2_CMD (0x03 << 16) +#define S3C64XX_GPC4_I2S0_V40_DO (0x05 << 16) +#define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16) + +#define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20) +#define S3C64XX_GPC5_MMC2_CLK (0x03 << 20) +#define S3C64XX_GPC5_I2S1_V40_DO (0x05 << 20) +#define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20) + +#define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24) +#define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24) + +#define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28) +#define S3C64XX_GPC7_I2S2_V40_DO (0x05 << 28) +#define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h new file mode 100644 index 0000000..6fe4a49 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h @@ -0,0 +1,49 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank D register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPDCON (S3C64XX_GPD_BASE + 0x00) +#define S3C64XX_GPDDAT (S3C64XX_GPD_BASE + 0x04) +#define S3C64XX_GPDPUD (S3C64XX_GPD_BASE + 0x08) +#define S3C64XX_GPDCONSLP (S3C64XX_GPD_BASE + 0x0c) +#define S3C64XX_GPDPUDSLP (S3C64XX_GPD_BASE + 0x10) + +#define S3C64XX_GPD_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPD_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPD_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPD0_PCM0_SCLK (0x02 << 0) +#define S3C64XX_GPD0_I2S0_CLK (0x03 << 0) +#define S3C64XX_GPD0_AC97_BITCLK (0x04 << 0) +#define S3C64XX_GPD0_EINT_G3_0 (0x07 << 0) + +#define S3C64XX_GPD1_PCM0_EXTCLK (0x02 << 4) +#define S3C64XX_GPD1_I2S0_CDCLK (0x03 << 4) +#define S3C64XX_GPD1_AC97_nRESET (0x04 << 4) +#define S3C64XX_GPD1_EINT_G3_1 (0x07 << 4) + +#define S3C64XX_GPD2_PCM0_FSYNC (0x02 << 8) +#define S3C64XX_GPD2_I2S0_LRCLK (0x03 << 8) +#define S3C64XX_GPD2_AC97_SYNC (0x04 << 8) +#define S3C64XX_GPD2_EINT_G3_2 (0x07 << 8) + +#define S3C64XX_GPD3_PCM0_SIN (0x02 << 12) +#define S3C64XX_GPD3_I2S0_DI (0x03 << 12) +#define S3C64XX_GPD3_AC97_SDI (0x04 << 12) +#define S3C64XX_GPD3_EINT_G3_3 (0x07 << 12) + +#define S3C64XX_GPD4_PCM0_SOUT (0x02 << 16) +#define S3C64XX_GPD4_I2S0_D0 (0x03 << 16) +#define S3C64XX_GPD4_AC97_SDO (0x04 << 16) +#define S3C64XX_GPD4_EINT_G3_4 (0x07 << 16) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h new file mode 100644 index 0000000..7fcf3d8 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h @@ -0,0 +1,44 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank E register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00) +#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04) +#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08) +#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c) +#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10) + +#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0) +#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0) +#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0) + +#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4) +#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4) +#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4) + +#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8) +#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8) +#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8) + +#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12) +#define S3C64XX_GPE3_I2S1_DI (0x03 << 12) +#define S3C64XX_GPE3_AC97_SDI (0x04 << 12) + +#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16) +#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16) +#define S3C64XX_GPE4_AC97_SDO (0x04 << 16) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h new file mode 100644 index 0000000..f3faff9 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h @@ -0,0 +1,71 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank F register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00) +#define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04) +#define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08) +#define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c) +#define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10) + +#define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0) +#define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0) + +#define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2) +#define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2) + +#define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4) +#define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4) + +#define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6) +#define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6) + +#define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8) +#define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8) + +#define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10) +#define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10) + +#define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12) +#define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12) + +#define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14) +#define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14) + +#define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16) +#define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16) + +#define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18) +#define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18) + +#define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20) +#define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20) + +#define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22) +#define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22) + +#define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24) +#define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24) + +#define S3C64XX_GPF13_PWM_ECLK (0x02 << 26) +#define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26) + +#define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28) +#define S3C64XX_GPF14_CLKOUT0 (0x03 << 28) + +#define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h new file mode 100644 index 0000000..35bbd23 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h @@ -0,0 +1,42 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank G register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPGCON (S3C64XX_GPG_BASE + 0x00) +#define S3C64XX_GPGDAT (S3C64XX_GPG_BASE + 0x04) +#define S3C64XX_GPGPUD (S3C64XX_GPG_BASE + 0x08) +#define S3C64XX_GPGCONSLP (S3C64XX_GPG_BASE + 0x0c) +#define S3C64XX_GPGPUDSLP (S3C64XX_GPG_BASE + 0x10) + +#define S3C64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPG0_MMC0_CLK (0x02 << 0) +#define S3C64XX_GPG0_EINT_G5_0 (0x07 << 0) + +#define S3C64XX_GPG1_MMC0_CMD (0x02 << 4) +#define S3C64XX_GPG1_EINT_G5_1 (0x07 << 4) + +#define S3C64XX_GPG2_MMC0_DATA0 (0x02 << 8) +#define S3C64XX_GPG2_EINT_G5_2 (0x07 << 8) + +#define S3C64XX_GPG3_MMC0_DATA1 (0x02 << 12) +#define S3C64XX_GPG3_EINT_G5_3 (0x07 << 12) + +#define S3C64XX_GPG4_MMC0_DATA2 (0x02 << 16) +#define S3C64XX_GPG4_EINT_G5_4 (0x07 << 16) + +#define S3C64XX_GPG5_MMC0_DATA3 (0x02 << 20) +#define S3C64XX_GPG5_EINT_G5_5 (0x07 << 20) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h new file mode 100644 index 0000000..8154951 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h @@ -0,0 +1,74 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank H register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPHCON0 (S3C64XX_GPH_BASE + 0x00) +#define S3C64XX_GPHCON1 (S3C64XX_GPH_BASE + 0x04) +#define S3C64XX_GPHDAT (S3C64XX_GPH_BASE + 0x08) +#define S3C64XX_GPHPUD (S3C64XX_GPH_BASE + 0x0c) +#define S3C64XX_GPHCONSLP (S3C64XX_GPH_BASE + 0x10) +#define S3C64XX_GPHPUDSLP (S3C64XX_GPH_BASE + 0x14) + +#define S3C64XX_GPH_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPH_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPH_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPH0_MMC1_CLK (0x02 << 0) +#define S3C64XX_GPH0_KP_COL0 (0x04 << 0) +#define S3C64XX_GPH0_EINT_G6_0 (0x07 << 0) + +#define S3C64XX_GPH1_MMC1_CMD (0x02 << 4) +#define S3C64XX_GPH1_KP_COL1 (0x04 << 4) +#define S3C64XX_GPH1_EINT_G6_1 (0x07 << 4) + +#define S3C64XX_GPH2_MMC1_DATA0 (0x02 << 8) +#define S3C64XX_GPH2_KP_COL2 (0x04 << 8) +#define S3C64XX_GPH2_EINT_G6_2 (0x07 << 8) + +#define S3C64XX_GPH3_MMC1_DATA1 (0x02 << 12) +#define S3C64XX_GPH3_KP_COL3 (0x04 << 12) +#define S3C64XX_GPH3_EINT_G6_3 (0x07 << 12) + +#define S3C64XX_GPH4_MMC1_DATA2 (0x02 << 16) +#define S3C64XX_GPH4_KP_COL4 (0x04 << 16) +#define S3C64XX_GPH4_EINT_G6_4 (0x07 << 16) + +#define S3C64XX_GPH5_MMC1_DATA3 (0x02 << 20) +#define S3C64XX_GPH5_KP_COL5 (0x04 << 20) +#define S3C64XX_GPH5_EINT_G6_5 (0x07 << 20) + +#define S3C64XX_GPH6_MMC1_DATA4 (0x02 << 24) +#define S3C64XX_GPH6_MMC2_DATA0 (0x03 << 24) +#define S3C64XX_GPH6_KP_COL6 (0x04 << 24) +#define S3C64XX_GPH6_I2S_V40_BCLK (0x05 << 24) +#define S3C64XX_GPH6_ADDR_CF0 (0x06 << 24) +#define S3C64XX_GPH6_EINT_G6_6 (0x07 << 24) + +#define S3C64XX_GPH7_MMC1_DATA5 (0x02 << 28) +#define S3C64XX_GPH7_MMC2_DATA1 (0x03 << 28) +#define S3C64XX_GPH7_KP_COL7 (0x04 << 28) +#define S3C64XX_GPH7_I2S_V40_CDCLK (0x05 << 28) +#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28) +#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28) + +#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 32) +#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 32) +#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 32) +#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 32) +#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 32) + +#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 36) +#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 36) +#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 36) +#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 36) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h new file mode 100644 index 0000000..ce9ebe3 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h @@ -0,0 +1,40 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank I register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPICON (S3C64XX_GPI_BASE + 0x00) +#define S3C64XX_GPIDAT (S3C64XX_GPI_BASE + 0x04) +#define S3C64XX_GPIPUD (S3C64XX_GPI_BASE + 0x08) +#define S3C64XX_GPICONSLP (S3C64XX_GPI_BASE + 0x0c) +#define S3C64XX_GPIPUDSLP (S3C64XX_GPI_BASE + 0x10) + +#define S3C64XX_GPI_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPI_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPI_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPI0_VD0 (0x02 << 0) +#define S3C64XX_GPI1_VD1 (0x02 << 2) +#define S3C64XX_GPI2_VD2 (0x02 << 4) +#define S3C64XX_GPI3_VD3 (0x02 << 6) +#define S3C64XX_GPI4_VD4 (0x02 << 8) +#define S3C64XX_GPI5_VD5 (0x02 << 10) +#define S3C64XX_GPI6_VD6 (0x02 << 12) +#define S3C64XX_GPI7_VD7 (0x02 << 14) +#define S3C64XX_GPI8_VD8 (0x02 << 16) +#define S3C64XX_GPI9_VD9 (0x02 << 18) +#define S3C64XX_GPI10_VD10 (0x02 << 20) +#define S3C64XX_GPI11_VD11 (0x02 << 22) +#define S3C64XX_GPI12_VD12 (0x02 << 24) +#define S3C64XX_GPI13_VD13 (0x02 << 26) +#define S3C64XX_GPI14_VD14 (0x02 << 28) +#define S3C64XX_GPI15_VD15 (0x02 << 30) diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h new file mode 100644 index 0000000..21a9062 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h @@ -0,0 +1,36 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank J register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPJCON (S3C64XX_GPJ_BASE + 0x00) +#define S3C64XX_GPJDAT (S3C64XX_GPJ_BASE + 0x04) +#define S3C64XX_GPJPUD (S3C64XX_GPJ_BASE + 0x08) +#define S3C64XX_GPJCONSLP (S3C64XX_GPJ_BASE + 0x0c) +#define S3C64XX_GPJPUDSLP (S3C64XX_GPJ_BASE + 0x10) + +#define S3C64XX_GPJ_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPJ_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPJ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPJ0_VD16 (0x02 << 0) +#define S3C64XX_GPJ1_VD17 (0x02 << 2) +#define S3C64XX_GPJ2_VD18 (0x02 << 4) +#define S3C64XX_GPJ3_VD19 (0x02 << 6) +#define S3C64XX_GPJ4_VD20 (0x02 << 8) +#define S3C64XX_GPJ5_VD21 (0x02 << 10) +#define S3C64XX_GPJ6_VD22 (0x02 << 12) +#define S3C64XX_GPJ7_VD23 (0x02 << 14) +#define S3C64XX_GPJ8_LCD_HSYNC (0x02 << 16) +#define S3C64XX_GPJ9_LCD_VSYNC (0x02 << 18) +#define S3C64XX_GPJ10_LCD_VDEN (0x02 << 20) +#define S3C64XX_GPJ11_LCD_VCLK (0x02 << 22) diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h new file mode 100644 index 0000000..569e761 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h @@ -0,0 +1,54 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank N register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00) +#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04) +#define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08) + +#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPN0_EINT0 (0x02 << 0) +#define S3C64XX_GPN0_KP_ROW0 (0x03 << 0) + +#define S3C64XX_GPN1_EINT1 (0x02 << 2) +#define S3C64XX_GPN1_KP_ROW1 (0x03 << 2) + +#define S3C64XX_GPN2_EINT2 (0x02 << 4) +#define S3C64XX_GPN2_KP_ROW2 (0x03 << 4) + +#define S3C64XX_GPN3_EINT3 (0x02 << 6) +#define S3C64XX_GPN3_KP_ROW3 (0x03 << 6) + +#define S3C64XX_GPN4_EINT4 (0x02 << 8) +#define S3C64XX_GPN4_KP_ROW4 (0x03 << 8) + +#define S3C64XX_GPN5_EINT5 (0x02 << 10) +#define S3C64XX_GPN5_KP_ROW5 (0x03 << 10) + +#define S3C64XX_GPN6_EINT6 (0x02 << 12) +#define S3C64XX_GPN6_KP_ROW6 (0x03 << 12) + +#define S3C64XX_GPN7_EINT7 (0x02 << 14) +#define S3C64XX_GPN7_KP_ROW7 (0x03 << 14) + +#define S3C64XX_GPN8_EINT8 (0x02 << 16) +#define S3C64XX_GPN9_EINT9 (0x02 << 18) +#define S3C64XX_GPN10_EINT10 (0x02 << 20) +#define S3C64XX_GPN11_EINT11 (0x02 << 22) +#define S3C64XX_GPN12_EINT12 (0x02 << 24) +#define S3C64XX_GPN13_EINT13 (0x02 << 26) +#define S3C64XX_GPN14_EINT14 (0x02 << 28) +#define S3C64XX_GPN15_EINT15 (0x02 << 30) diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h new file mode 100644 index 0000000..b09e129 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h @@ -0,0 +1,70 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank O register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00) +#define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04) +#define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08) +#define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c) +#define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10) + +#define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0) +#define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0) + +#define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2) +#define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2) + +#define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4) +#define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4) + +#define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6) +#define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6) + +#define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8) + +#define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10) + +#define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12) +#define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12) + +#define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14) +#define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14) + +#define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16) +#define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16) + +#define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18) +#define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18) + +#define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20) +#define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20) + +#define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22) +#define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22) + +#define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24) +#define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24) + +#define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26) +#define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26) + +#define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28) +#define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28) + +#define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30) +#define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h new file mode 100644 index 0000000..92f0051 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h @@ -0,0 +1,69 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank P register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00) +#define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04) +#define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08) +#define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c) +#define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10) + +#define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0) +#define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0) + +#define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2) +#define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2) + +#define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4) +#define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4) + +#define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6) +#define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6) + +#define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8) +#define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8) + +#define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10) +#define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10) + +#define S3C64XX_GPP6_MEM0_(null) (0x02 << 12) +#define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12) + +#define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14) +#define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14) + +#define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16) +#define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16) + +#define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18) +#define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18) + +#define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20) +#define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20) + +#define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22) +#define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22) + +#define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24) +#define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24) + +#define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26) +#define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26) + +#define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28) +#define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h new file mode 100644 index 0000000..565e60a --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h @@ -0,0 +1,46 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank Q register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00) +#define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04) +#define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08) +#define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c) +#define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10) + +#define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0) +#define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0) + +#define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2) +#define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2) + +#define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4) + +#define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6) + +#define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8) + +#define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10) + +#define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12) + +#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14) +#define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14) + +#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16) +#define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16) + diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h new file mode 100644 index 0000000..02e8dd4 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h @@ -0,0 +1,201 @@ +/* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - Common IRQ support + */ + +#ifndef __ASM_PLAT_S3C64XX_IRQS_H +#define __ASM_PLAT_S3C64XX_IRQS_H __FILE__ + +/* we keep the first set of CPU IRQs out of the range of + * the ISA space, so that the PC104 has them to itself + * and we don't end up having to do horrible things to the + * standard ISA drivers.... + * + * note, since we're using the VICs, our start must be a + * mulitple of 32 to allow the common code to work + */ + +#define S3C_IRQ_OFFSET (32) + +#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) + +#define S3C_VIC0_BASE S3C_IRQ(0) +#define S3C_VIC1_BASE S3C_IRQ(32) + +/* UART interrupts, each UART has 4 intterupts per channel so + * use the space between the ISA and S3C main interrupts. Note, these + * are not in the same order as the S3C24XX series! */ + +#define IRQ_S3CUART_BASE0 (16) +#define IRQ_S3CUART_BASE1 (20) +#define IRQ_S3CUART_BASE2 (24) +#define IRQ_S3CUART_BASE3 (28) + +#define UART_IRQ_RXD (0) +#define UART_IRQ_ERR (1) +#define UART_IRQ_TXD (2) +#define UART_IRQ_MODEM (3) + +#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD) +#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD) +#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR) + +#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD) +#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD) +#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR) + +#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD) +#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD) +#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR) + +#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD) +#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD) +#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR) + +/* VIC based IRQs */ + +#define S3C64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x)) +#define S3C64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x)) + +/* VIC0 */ + +#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) +#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) +#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) +#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) +#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) +#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) +#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) +#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) +#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) +#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) +#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) +#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) +#define IRQ_POST0 S3C64XX_IRQ_VIC0(9) +#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) +#define IRQ_2D S3C64XX_IRQ_VIC0(11) +#define IRQ_TVENC S3C64XX_IRQ_VIC0(12) +#define IRQ_SCALER S3C64XX_IRQ_VIC0(13) +#define IRQ_BATF S3C64XX_IRQ_VIC0(14) +#define IRQ_JPEG S3C64XX_IRQ_VIC0(15) +#define IRQ_MFC S3C64XX_IRQ_VIC0(16) +#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) +#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) +#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) +#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) +#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) +#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) +#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) +#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) +#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) +#define IRQ_WDT S3C64XX_IRQ_VIC0(26) +#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) +#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) +#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) +#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) +#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) + +/* VIC1 */ + +#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) +#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) +#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) +#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) +#define IRQ_AC97 S3C64XX_IRQ_VIC1(4) +#define IRQ_UART0 S3C64XX_IRQ_VIC1(5) +#define IRQ_UART1 S3C64XX_IRQ_VIC1(6) +#define IRQ_UART2 S3C64XX_IRQ_VIC1(7) +#define IRQ_UART3 S3C64XX_IRQ_VIC1(8) +#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) +#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) +#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) +#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) +#define IRQ_NFC S3C64XX_IRQ_VIC1(13) +#define IRQ_CFCON S3C64XX_IRQ_VIC1(14) +#define IRQ_UHOST S3C64XX_IRQ_VIC1(15) +#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) +#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) +#define IRQ_IIC S3C64XX_IRQ_VIC1(18) +#define IRQ_HSItx S3C64XX_IRQ_VIC1(19) +#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) +#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) +#define IRQ_MSM S3C64XX_IRQ_VIC1(22) +#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) +#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) +#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) +#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ +#define IRQ_OTG S3C64XX_IRQ_VIC1(26) +#define IRQ_IRDA S3C64XX_IRQ_VIC1(27) +#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) +#define IRQ_SEC S3C64XX_IRQ_VIC1(29) +#define IRQ_PENDN S3C64XX_IRQ_VIC1(30) +#define IRQ_TC IRQ_PENDN +#define IRQ_ADC S3C64XX_IRQ_VIC1(31) + +#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x)) + +#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0) +#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1) +#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2) +#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3) +#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4) + +/* compatibility for device defines */ + +#define IRQ_IIC1 IRQ_S3C6410_IIC1 + +/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series + * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE + * which we place after the pair of VICs. */ + +#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) + +#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) +#define IRQ_EINT(x) S3C_EINT(x) + +/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) + * that they are sourced from the GPIO pins but with a different scheme for + * priority and source indication. + * + * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO + * interrupts, but for historical reasons they are kept apart from these + * next interrupts. + * + * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the + * machine specific support files. + */ + +#define IRQ_EINT_GROUP1_NR (15) +#define IRQ_EINT_GROUP2_NR (8) +#define IRQ_EINT_GROUP3_NR (5) +#define IRQ_EINT_GROUP4_NR (14) +#define IRQ_EINT_GROUP5_NR (7) +#define IRQ_EINT_GROUP6_NR (10) +#define IRQ_EINT_GROUP7_NR (16) +#define IRQ_EINT_GROUP8_NR (15) +#define IRQ_EINT_GROUP9_NR (9) + +#define IRQ_EINT_GROUP_BASE S3C_EINT(28) +#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) +#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) +#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) +#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) +#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) +#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) +#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) +#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) +#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) + +#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##__BASE + (x)) + +/* Set the default NR_IRQS */ + +#define NR_IRQS (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) + +#endif /* __ASM_PLAT_S3C64XX_IRQS_H */ + diff --git a/arch/arm/plat-s3c64xx/include/plat/pll.h b/arch/arm/plat-s3c64xx/include/plat/pll.h new file mode 100644 index 0000000..90bbd72 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/pll.h @@ -0,0 +1,74 @@ +/* arch/arm/plat-s3c64xx/include/plat/pll.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX PLL code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1) +#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1) +#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1) +#define S3C6400_PLL_MDIV_SHIFT (16) +#define S3C6400_PLL_PDIV_SHIFT (8) +#define S3C6400_PLL_SDIV_SHIFT (0) + +#include <asm/div64.h> + +static inline unsigned long s3c6400_get_pll(unsigned long baseclk, + u32 pllcon) +{ + u32 mdiv, pdiv, sdiv; + u64 fvco = baseclk; + + mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK; + pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK; + sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +#define S3C6400_EPLL_MDIV_MASK ((1 << (23-16)) - 1) +#define S3C6400_EPLL_PDIV_MASK ((1 << (13-8)) - 1) +#define S3C6400_EPLL_SDIV_MASK ((1 << (2-0)) - 1) +#define S3C6400_EPLL_MDIV_SHIFT (16) +#define S3C6400_EPLL_PDIV_SHIFT (8) +#define S3C6400_EPLL_SDIV_SHIFT (0) +#define S3C6400_EPLL_KDIV_MASK (0xffff) + +static inline unsigned long s3c6400_get_epll(unsigned long baseclk) +{ + unsigned long result; + u32 epll0 = __raw_readl(S3C_EPLL_CON0); + u32 epll1 = __raw_readl(S3C_EPLL_CON1); + u32 mdiv, pdiv, sdiv, kdiv; + u64 tmp; + + mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK; + pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK; + sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK; + kdiv = epll1 & S3C6400_EPLL_KDIV_MASK; + + /* We need to multiple baseclk by mdiv (the integer part) and kdiv + * which is in 2^16ths, so shift mdiv up (does not overflow) and + * add kdiv before multiplying. The use of tmp is to avoid any + * overflows before shifting bac down into result when multipling + * by the mdiv and kdiv pair. + */ + + tmp = baseclk; + tmp *= (mdiv << 16) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 16; + + return result; +} diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h new file mode 100644 index 0000000..b1082c1 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -0,0 +1,224 @@ +/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_REGS_CLOCK_H +#define __PLAT_REGS_CLOCK_H __FILE__ + +#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) + +#define S3C_APLL_LOCK S3C_CLKREG(0x00) +#define S3C_MPLL_LOCK S3C_CLKREG(0x04) +#define S3C_EPLL_LOCK S3C_CLKREG(0x08) +#define S3C_APLL_CON S3C_CLKREG(0x0C) +#define S3C_MPLL_CON S3C_CLKREG(0x10) +#define S3C_EPLL_CON0 S3C_CLKREG(0x14) +#define S3C_EPLL_CON1 S3C_CLKREG(0x18) +#define S3C_CLK_SRC S3C_CLKREG(0x1C) +#define S3C_CLK_DIV0 S3C_CLKREG(0x20) +#define S3C_CLK_DIV1 S3C_CLKREG(0x24) +#define S3C_CLK_DIV2 S3C_CLKREG(0x28) +#define S3C_CLK_OUT S3C_CLKREG(0x2C) +#define S3C_HCLK_GATE S3C_CLKREG(0x30) +#define S3C_PCLK_GATE S3C_CLKREG(0x34) +#define S3C_SCLK_GATE S3C_CLKREG(0x38) + +/* CLKDIV0 */ +#define S3C6400_CLKDIV0_MFC_MASK (0xf << 28) +#define S3C6400_CLKDIV0_MFC_SHIFT (28) +#define S3C6400_CLKDIV0_JPEG_MASK (0xf << 24) +#define S3C6400_CLKDIV0_JPEG_SHIFT (24) +#define S3C6400_CLKDIV0_CAM_MASK (0xf << 20) +#define S3C6400_CLKDIV0_CAM_SHIFT (20) +#define S3C6400_CLKDIV0_SECURITY_MASK (0x3 << 18) +#define S3C6400_CLKDIV0_SECURITY_SHIFT (18) +#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) +#define S3C6400_CLKDIV0_PCLK_SHIFT (12) +#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9) +#define S3C6400_CLKDIV0_HCLK2_SHIFT (9) +#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8) +#define S3C6400_CLKDIV0_HCLK_SHIFT (8) +#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) +#define S3C6400_CLKDIV0_MPLL_SHIFT (4) +#define S3C6400_CLKDIV0_ARM_MASK (0x3 << 0) +#define S3C6410_CLKDIV0_ARM_MASK (0x7 << 0) +#define S3C6400_CLKDIV0_ARM_SHIFT (0) + +/* CLKDIV1 */ +#define S3C6410_CLKDIV1_FIMC_MASK (0xf << 24) +#define S3C6410_CLKDIV1_FIMC_SHIFT (24) +#define S3C6400_CLKDIV1_UHOST_MASK (0xf << 20) +#define S3C6400_CLKDIV1_UHOST_SHIFT (20) +#define S3C6400_CLKDIV1_SCALER_MASK (0xf << 16) +#define S3C6400_CLKDIV1_SCALER_SHIFT (16) +#define S3C6400_CLKDIV1_LCD_MASK (0xf << 12) +#define S3C6400_CLKDIV1_LCD_SHIFT (12) +#define S3C6400_CLKDIV1_MMC2_MASK (0xf << 8) +#define S3C6400_CLKDIV1_MMC2_SHIFT (8) +#define S3C6400_CLKDIV1_MMC1_MASK (0xf << 4) +#define S3C6400_CLKDIV1_MMC1_SHIFT (4) +#define S3C6400_CLKDIV1_MMC0_MASK (0xf << 0) +#define S3C6400_CLKDIV1_MMC0_SHIFT (0) + +/* CLKDIV2 */ +#define S3C6410_CLKDIV2_AUDIO2_MASK (0xf << 24) +#define S3C6410_CLKDIV2_AUDIO2_SHIFT (24) +#define S3C6400_CLKDIV2_IRDA_MASK (0xf << 20) +#define S3C6400_CLKDIV2_IRDA_SHIFT (20) +#define S3C6400_CLKDIV2_UART_MASK (0xf << 16) +#define S3C6400_CLKDIV2_UART_SHIFT (16) +#define S3C6400_CLKDIV2_AUDIO1_MASK (0xf << 12) +#define S3C6400_CLKDIV2_AUDIO1_SHIFT (12) +#define S3C6400_CLKDIV2_AUDIO0_MASK (0xf << 8) +#define S3C6400_CLKDIV2_AUDIO0_SHIFT (8) +#define S3C6400_CLKDIV2_SPI1_MASK (0xf << 4) +#define S3C6400_CLKDIV2_SPI1_SHIFT (4) +#define S3C6400_CLKDIV2_SPI0_MASK (0xf << 0) +#define S3C6400_CLKDIV2_SPI0_SHIFT (0) + +/* HCLK GATE Registers */ +#define S3C_CLKCON_HCLK_BUS (1<<30) +#define S3C_CLKCON_HCLK_SECUR (1<<29) +#define S3C_CLKCON_HCLK_SDMA1 (1<<28) +#define S3C_CLKCON_HCLK_SDMA2 (1<<27) +#define S3C_CLKCON_HCLK_UHOST (1<<26) +#define S3C_CLKCON_HCLK_IROM (1<<25) +#define S3C_CLKCON_HCLK_DDR1 (1<<24) +#define S3C_CLKCON_HCLK_DDR0 (1<<23) +#define S3C_CLKCON_HCLK_MEM1 (1<<22) +#define S3C_CLKCON_HCLK_MEM0 (1<<21) +#define S3C_CLKCON_HCLK_USB (1<<20) +#define S3C_CLKCON_HCLK_HSMMC2 (1<<19) +#define S3C_CLKCON_HCLK_HSMMC1 (1<<18) +#define S3C_CLKCON_HCLK_HSMMC0 (1<<17) +#define S3C_CLKCON_HCLK_MDP (1<<16) +#define S3C_CLKCON_HCLK_DHOST (1<<15) +#define S3C_CLKCON_HCLK_IHOST (1<<14) +#define S3C_CLKCON_HCLK_DMA1 (1<<13) +#define S3C_CLKCON_HCLK_DMA0 (1<<12) +#define S3C_CLKCON_HCLK_JPEG (1<<11) +#define S3C_CLKCON_HCLK_CAMIF (1<<10) +#define S3C_CLKCON_HCLK_SCALER (1<<9) +#define S3C_CLKCON_HCLK_2D (1<<8) +#define S3C_CLKCON_HCLK_TV (1<<7) +#define S3C_CLKCON_HCLK_POST0 (1<<5) +#define S3C_CLKCON_HCLK_ROT (1<<4) +#define S3C_CLKCON_HCLK_LCD (1<<3) +#define S3C_CLKCON_HCLK_TZIC (1<<2) +#define S3C_CLKCON_HCLK_INTC (1<<1) +#define S3C_CLKCON_HCLK_MFC (1<<0) + +/* PCLK GATE Registers */ +#define S3C6410_CLKCON_PCLK_I2C1 (1<<27) +#define S3C6410_CLKCON_PCLK_IIS2 (1<<26) +#define S3C_CLKCON_PCLK_SKEY (1<<24) +#define S3C_CLKCON_PCLK_CHIPID (1<<23) +#define S3C_CLKCON_PCLK_SPI1 (1<<22) +#define S3C_CLKCON_PCLK_SPI0 (1<<21) +#define S3C_CLKCON_PCLK_HSIRX (1<<20) +#define S3C_CLKCON_PCLK_HSITX (1<<19) +#define S3C_CLKCON_PCLK_GPIO (1<<18) +#define S3C_CLKCON_PCLK_IIC (1<<17) +#define S3C_CLKCON_PCLK_IIS1 (1<<16) +#define S3C_CLKCON_PCLK_IIS0 (1<<15) +#define S3C_CLKCON_PCLK_AC97 (1<<14) +#define S3C_CLKCON_PCLK_TZPC (1<<13) +#define S3C_CLKCON_PCLK_TSADC (1<<12) +#define S3C_CLKCON_PCLK_KEYPAD (1<<11) +#define S3C_CLKCON_PCLK_IRDA (1<<10) +#define S3C_CLKCON_PCLK_PCM1 (1<<9) +#define S3C_CLKCON_PCLK_PCM0 (1<<8) +#define S3C_CLKCON_PCLK_PWM (1<<7) +#define S3C_CLKCON_PCLK_RTC (1<<6) +#define S3C_CLKCON_PCLK_WDT (1<<5) +#define S3C_CLKCON_PCLK_UART3 (1<<4) +#define S3C_CLKCON_PCLK_UART2 (1<<3) +#define S3C_CLKCON_PCLK_UART1 (1<<2) +#define S3C_CLKCON_PCLK_UART0 (1<<1) +#define S3C_CLKCON_PCLK_MFC (1<<0) + +/* SCLK GATE Registers */ +#define S3C_CLKCON_SCLK_UHOST (1<<30) +#define S3C_CLKCON_SCLK_MMC2_48 (1<<29) +#define S3C_CLKCON_SCLK_MMC1_48 (1<<28) +#define S3C_CLKCON_SCLK_MMC0_48 (1<<27) +#define S3C_CLKCON_SCLK_MMC2 (1<<26) +#define S3C_CLKCON_SCLK_MMC1 (1<<25) +#define S3C_CLKCON_SCLK_MMC0 (1<<24) +#define S3C_CLKCON_SCLK_SPI1_48 (1<<23) +#define S3C_CLKCON_SCLK_SPI0_48 (1<<22) +#define S3C_CLKCON_SCLK_SPI1 (1<<21) +#define S3C_CLKCON_SCLK_SPI0 (1<<20) +#define S3C_CLKCON_SCLK_DAC27 (1<<19) +#define S3C_CLKCON_SCLK_TV27 (1<<18) +#define S3C_CLKCON_SCLK_SCALER27 (1<<17) +#define S3C_CLKCON_SCLK_SCALER (1<<16) +#define S3C_CLKCON_SCLK_LCD27 (1<<15) +#define S3C_CLKCON_SCLK_LCD (1<<14) +#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13) +#define S3C6410_CLKCON_FIMC (1<<13) +#define S3C_CLKCON_SCLK_POST0_27 (1<<12) +#define S3C6400_CLKCON_SCLK_POST1 (1<<11) +#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11) +#define S3C_CLKCON_SCLK_POST0 (1<<10) +#define S3C_CLKCON_SCLK_AUDIO1 (1<<9) +#define S3C_CLKCON_SCLK_AUDIO0 (1<<8) +#define S3C_CLKCON_SCLK_SECUR (1<<7) +#define S3C_CLKCON_SCLK_IRDA (1<<6) +#define S3C_CLKCON_SCLK_UART (1<<5) +#define S3C_CLKCON_SCLK_ONENAND (1<<4) +#define S3C_CLKCON_SCLK_MFC (1<<3) +#define S3C_CLKCON_SCLK_CAM (1<<2) +#define S3C_CLKCON_SCLK_JPEG (1<<1) + +/* CLKSRC */ + +#define S3C6400_CLKSRC_APLL_MOUT (1 << 0) +#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1) +#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2) +#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0) +#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1) +#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) +#define S3C6400_CLKSRC_MFC (1 << 4) + +#define S3C6410_CLKSRC_TV27_MASK (0x1 << 31) +#define S3C6410_CLKSRC_TV27_SHIFT (31) +#define S3C6410_CLKSRC_DAC27_MASK (0x1 << 30) +#define S3C6410_CLKSRC_DAC27_SHIFT (30) +#define S3C6400_CLKSRC_SCALER_MASK (0x3 << 28) +#define S3C6400_CLKSRC_SCALER_SHIFT (28) +#define S3C6400_CLKSRC_LCD_MASK (0x3 << 26) +#define S3C6400_CLKSRC_LCD_SHIFT (26) +#define S3C6400_CLKSRC_IRDA_MASK (0x3 << 24) +#define S3C6400_CLKSRC_IRDA_SHIFT (24) +#define S3C6400_CLKSRC_MMC2_MASK (0x3 << 22) +#define S3C6400_CLKSRC_MMC2_SHIFT (22) +#define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20) +#define S3C6400_CLKSRC_MMC1_SHIFT (20) +#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18) +#define S3C6400_CLKSRC_MMC0_SHIFT (18) +#define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16) +#define S3C6400_CLKSRC_SPI1_SHIFT (16) +#define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14) +#define S3C6400_CLKSRC_SPI0_SHIFT (14) +#define S3C6400_CLKSRC_UART_MASK (0x1 << 13) +#define S3C6400_CLKSRC_UART_SHIFT (13) +#define S3C6400_CLKSRC_AUDIO1_MASK (0x7 << 10) +#define S3C6400_CLKSRC_AUDIO1_SHIFT (10) +#define S3C6400_CLKSRC_AUDIO0_MASK (0x7 << 7) +#define S3C6400_CLKSRC_AUDIO0_SHIFT (7) +#define S3C6400_CLKSRC_UHOST_MASK (0x3 << 5) +#define S3C6400_CLKSRC_UHOST_SHIFT (5) + + +#endif /* _PLAT_REGS_CLOCK_H */ diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h new file mode 100644 index 0000000..75b873d --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h @@ -0,0 +1,35 @@ +/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - GPIO register definitions + */ + +#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H +#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__ + +/* Base addresses for each of the banks */ + +#define S3C64XX_GPA_BASE (S3C64XX_VA_GPIO + 0x0000) +#define S3C64XX_GPB_BASE (S3C64XX_VA_GPIO + 0x0020) +#define S3C64XX_GPC_BASE (S3C64XX_VA_GPIO + 0x0040) +#define S3C64XX_GPD_BASE (S3C64XX_VA_GPIO + 0x0060) +#define S3C64XX_GPE_BASE (S3C64XX_VA_GPIO + 0x0080) +#define S3C64XX_GPF_BASE (S3C64XX_VA_GPIO + 0x00A0) +#define S3C64XX_GPG_BASE (S3C64XX_VA_GPIO + 0x00C0) +#define S3C64XX_GPH_BASE (S3C64XX_VA_GPIO + 0x00E0) +#define S3C64XX_GPI_BASE (S3C64XX_VA_GPIO + 0x0100) +#define S3C64XX_GPJ_BASE (S3C64XX_VA_GPIO + 0x0120) +#define S3C64XX_GPK_BASE (S3C64XX_VA_GPIO + 0x0800) +#define S3C64XX_GPL_BASE (S3C64XX_VA_GPIO + 0x0810) +#define S3C64XX_GPM_BASE (S3C64XX_VA_GPIO + 0x0820) +#define S3C64XX_GPN_BASE (S3C64XX_VA_GPIO + 0x0830) +#define S3C64XX_GPO_BASE (S3C64XX_VA_GPIO + 0x0140) +#define S3C64XX_GPP_BASE (S3C64XX_VA_GPIO + 0x0160) +#define S3C64XX_GPQ_BASE (S3C64XX_VA_GPIO + 0x0180) + +#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ + diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-sys.h b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h new file mode 100644 index 0000000..d8ed829 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h @@ -0,0 +1,24 @@ +/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX system register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_REGS_SYS_H +#define __PLAT_REGS_SYS_H __FILE__ + +#define S3C_SYSREG(x) (S3C_VA_SYS + (x)) + +#define S3C64XX_OTHERS S3C_SYSREG(0x900) + +#define S3C64XX_OTHERS_USBMASK (1 << 16) + +#endif /* _PLAT_REGS_SYS_H */ diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h new file mode 100644 index 0000000..571eaa2 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h @@ -0,0 +1,35 @@ +/* arch/arm/plat-s3c64xx/include/plat/s3c6400.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Header file for s3c6400 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Common init code for S3C6400 related SoCs */ + +extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); +extern void s3c6400_register_clocks(void); +extern void s3c6400_setup_clocks(void); + +#ifdef CONFIG_CPU_S3C6400 + +extern int s3c6400_init(void); +extern void s3c6400_map_io(void); +extern void s3c6400_init_clocks(int xtal); + +#define s3c6400_init_uarts s3c6400_common_init_uarts + +#else +#define s3c6400_init_clocks NULL +#define s3c6400_init_uarts NULL +#define s3c6400_map_io NULL +#define s3c6400_init NULL +#endif + diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6410.h b/arch/arm/plat-s3c64xx/include/plat/s3c6410.h new file mode 100644 index 0000000..50dcdd6 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/s3c6410.h @@ -0,0 +1,29 @@ +/* arch/arm/plat-s3c64xx/include/plat/s3c6410.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Header file for s3c6410 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifdef CONFIG_CPU_S3C6410 + +extern int s3c6410_init(void); +extern void s3c6410_init_irq(void); +extern void s3c6410_map_io(void); +extern void s3c6410_init_clocks(int xtal); + +#define s3c6410_init_uarts s3c6400_common_init_uarts + +#else +#define s3c6410_init_clocks NULL +#define s3c6410_init_uarts NULL +#define s3c6410_map_io NULL +#define s3c6410_init NULL +#endif diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c new file mode 100644 index 0000000..1f7cc00 --- /dev/null +++ b/arch/arm/plat-s3c64xx/irq-eint.c @@ -0,0 +1,202 @@ +/* arch/arm/plat-s3c64xx/irq-eint.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - Interrupt handling for IRQ_EINT(x) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <asm/hardware/vic.h> + +#include <plat/regs-irqtype.h> + +#include <mach/map.h> +#include <plat/cpu.h> + +/* GPIO is 0x7F008xxx, */ +#define S3C64XX_GPIOREG(x) (S3C64XX_VA_GPIO + (x)) + +#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) +#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) +#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) +#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) +#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) +#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) + +#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) +#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) + + +#define eint_offset(irq) ((irq) - IRQ_EINT(0)) +#define eint_irq_to_bit(irq) (1 << eint_offset(irq)) + +static inline void s3c_irq_eint_mask(unsigned int irq) +{ + u32 mask; + + mask = __raw_readl(S3C64XX_EINT0MASK); + mask |= eint_irq_to_bit(irq); + __raw_writel(mask, S3C64XX_EINT0MASK); +} + +static void s3c_irq_eint_unmask(unsigned int irq) +{ + u32 mask; + + mask = __raw_readl(S3C64XX_EINT0MASK); + mask |= eint_irq_to_bit(irq); + __raw_writel(mask, S3C64XX_EINT0MASK); +} + +static inline void s3c_irq_eint_ack(unsigned int irq) +{ + __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND); +} + +static void s3c_irq_eint_maskack(unsigned int irq) +{ + /* compiler should in-line these */ + s3c_irq_eint_mask(irq); + s3c_irq_eint_ack(irq); +} + +static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) +{ + int offs = eint_offset(irq); + int shift; + u32 ctrl, mask; + u32 newvalue = 0; + void __iomem *reg; + + if (offs > 27) + return -EINVAL; + + if (offs <= 15) + reg = S3C64XX_EINT0CON0; + else + reg = S3C64XX_EINT0CON1; + + switch (type) { + case IRQ_TYPE_NONE: + printk(KERN_WARNING "No edge setting!\n"); + break; + + case IRQ_TYPE_EDGE_RISING: + newvalue = S3C2410_EXTINT_RISEEDGE; + break; + + case IRQ_TYPE_EDGE_FALLING: + newvalue = S3C2410_EXTINT_FALLEDGE; + break; + + case IRQ_TYPE_EDGE_BOTH: + newvalue = S3C2410_EXTINT_BOTHEDGE; + break; + + case IRQ_TYPE_LEVEL_LOW: + newvalue = S3C2410_EXTINT_LOWLEV; + break; + + case IRQ_TYPE_LEVEL_HIGH: + newvalue = S3C2410_EXTINT_HILEV; + break; + + default: + printk(KERN_ERR "No such irq type %d", type); + return -1; + } + + shift = (offs / 2) * 4; + mask = 0x7 << shift; + + ctrl = __raw_readl(reg); + ctrl &= ~mask; + ctrl |= newvalue << shift; + __raw_writel(ctrl, reg); + + return 0; +} + +static struct irq_chip s3c_irq_eint = { + .name = "s3c-eint", + .mask = s3c_irq_eint_mask, + .unmask = s3c_irq_eint_unmask, + .mask_ack = s3c_irq_eint_maskack, + .ack = s3c_irq_eint_ack, + .set_type = s3c_irq_eint_set_type, +}; + +/* s3c_irq_demux_eint + * + * This function demuxes the IRQ from the group0 external interrupts, + * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into + * the specific handlers s3c_irq_demux_eintX_Y. + */ +static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end) +{ + u32 status = __raw_readl(S3C64XX_EINT0PEND); + u32 mask = __raw_readl(S3C64XX_EINT0MASK); + unsigned int irq; + + status &= ~mask; + status >>= start; + status &= (1 << (end - start + 1)) - 1; + + for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { + if (status & 1) + generic_handle_irq(irq); + + status >>= 1; + } +} + +static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +{ + s3c_irq_demux_eint(0, 3); +} + +static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc) +{ + s3c_irq_demux_eint(4, 11); +} + +static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc) +{ + s3c_irq_demux_eint(12, 19); +} + +static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc) +{ + s3c_irq_demux_eint(20, 27); +} + +int __init s3c64xx_init_irq_eint(void) +{ + int irq; + + for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { + set_irq_chip(irq, &s3c_irq_eint); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + + set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); + set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); + set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); + set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); + + return 0; +} + +arch_initcall(s3c64xx_init_irq_eint); diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c new file mode 100644 index 0000000..a94f1d5 --- /dev/null +++ b/arch/arm/plat-s3c64xx/irq.c @@ -0,0 +1,257 @@ +/* arch/arm/plat-s3c64xx/irq.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - Interrupt handling + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <asm/hardware/vic.h> + +#include <mach/map.h> +#include <plat/regs-timer.h> +#include <plat/cpu.h> + +/* Timer interrupt handling */ + +static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq) +{ + generic_handle_irq(sub_irq); +} + +static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc) +{ + s3c_irq_demux_timer(irq, IRQ_TIMER0); +} + +static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc) +{ + s3c_irq_demux_timer(irq, IRQ_TIMER1); +} + +static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc) +{ + s3c_irq_demux_timer(irq, IRQ_TIMER2); +} + +static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc) +{ + s3c_irq_demux_timer(irq, IRQ_TIMER3); +} + +static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc) +{ + s3c_irq_demux_timer(irq, IRQ_TIMER4); +} + +/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ + +static void s3c_irq_timer_mask(unsigned int irq) +{ + u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); + + reg &= 0x1f; /* mask out pending interrupts */ + reg &= ~(1 << (irq - IRQ_TIMER0)); + __raw_writel(reg, S3C64XX_TINT_CSTAT); +} + +static void s3c_irq_timer_unmask(unsigned int irq) +{ + u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); + + reg &= 0x1f; /* mask out pending interrupts */ + reg |= 1 << (irq - IRQ_TIMER0); + __raw_writel(reg, S3C64XX_TINT_CSTAT); +} + +static void s3c_irq_timer_ack(unsigned int irq) +{ + u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); + + reg &= 0x1f; + reg |= (1 << 5) << (irq - IRQ_TIMER0); + __raw_writel(reg, S3C64XX_TINT_CSTAT); +} + +static struct irq_chip s3c_irq_timer = { + .name = "s3c-timer", + .mask = s3c_irq_timer_mask, + .unmask = s3c_irq_timer_unmask, + .ack = s3c_irq_timer_ack, +}; + +struct uart_irq { + void __iomem *regs; + unsigned int base_irq; + unsigned int parent_irq; +}; + +/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] + * are consecutive when looking up the interrupt in the demux routines. + */ +static struct uart_irq uart_irqs[] = { + [0] = { + .regs = S3C_VA_UART0, + .base_irq = IRQ_S3CUART_BASE0, + .parent_irq = IRQ_UART0, + }, + [1] = { + .regs = S3C_VA_UART1, + .base_irq = IRQ_S3CUART_BASE1, + .parent_irq = IRQ_UART1, + }, + [2] = { + .regs = S3C_VA_UART2, + .base_irq = IRQ_S3CUART_BASE2, + .parent_irq = IRQ_UART2, + }, + [3] = { + .regs = S3C_VA_UART3, + .base_irq = IRQ_S3CUART_BASE3, + .parent_irq = IRQ_UART3, + }, +}; + +static inline void __iomem *s3c_irq_uart_base(unsigned int irq) +{ + struct uart_irq *uirq = get_irq_chip_data(irq); + return uirq->regs; +} + +static inline unsigned int s3c_irq_uart_bit(unsigned int irq) +{ + return irq & 3; +} + +/* UART interrupt registers, not worth adding to seperate include header */ +#define S3C64XX_UINTP 0x30 +#define S3C64XX_UINTSP 0x34 +#define S3C64XX_UINTM 0x38 + +static void s3c_irq_uart_mask(unsigned int irq) +{ + void __iomem *regs = s3c_irq_uart_base(irq); + unsigned int bit = s3c_irq_uart_bit(irq); + u32 reg; + + reg = __raw_readl(regs + S3C64XX_UINTM); + reg |= (1 << bit); + __raw_writel(reg, regs + S3C64XX_UINTM); +} + +static void s3c_irq_uart_maskack(unsigned int irq) +{ + void __iomem *regs = s3c_irq_uart_base(irq); + unsigned int bit = s3c_irq_uart_bit(irq); + u32 reg; + + reg = __raw_readl(regs + S3C64XX_UINTM); + reg |= (1 << bit); + __raw_writel(reg, regs + S3C64XX_UINTM); + __raw_writel(1 << bit, regs + S3C64XX_UINTP); +} + +static void s3c_irq_uart_unmask(unsigned int irq) +{ + void __iomem *regs = s3c_irq_uart_base(irq); + unsigned int bit = s3c_irq_uart_bit(irq); + u32 reg; + + reg = __raw_readl(regs + S3C64XX_UINTM); + reg &= ~(1 << bit); + __raw_writel(reg, regs + S3C64XX_UINTM); +} + +static void s3c_irq_uart_ack(unsigned int irq) +{ + void __iomem *regs = s3c_irq_uart_base(irq); + unsigned int bit = s3c_irq_uart_bit(irq); + + __raw_writel(1 << bit, regs + S3C64XX_UINTP); +} + +static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) +{ + struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0]; + u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); + int base = uirq->base_irq; + + if (pend & (1 << 0)) + generic_handle_irq(base); + if (pend & (1 << 1)) + generic_handle_irq(base + 1); + if (pend & (1 << 2)) + generic_handle_irq(base + 2); + if (pend & (1 << 3)) + generic_handle_irq(base + 3); +} + +static struct irq_chip s3c_irq_uart = { + .name = "s3c-uart", + .mask = s3c_irq_uart_mask, + .unmask = s3c_irq_uart_unmask, + .mask_ack = s3c_irq_uart_maskack, + .ack = s3c_irq_uart_ack, +}; + +static void __init s3c64xx_uart_irq(struct uart_irq *uirq) +{ + void *reg_base = uirq->regs; + unsigned int irq; + int offs; + + /* mask all interrupts at the start. */ + __raw_writel(0xf, reg_base + S3C64XX_UINTM); + + for (offs = 0; offs < 3; offs++) { + irq = uirq->base_irq + offs; + + set_irq_chip(irq, &s3c_irq_uart); + set_irq_chip_data(irq, uirq); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + + set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); +} + +void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) +{ + int uart, irq; + + printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); + + /* initialise the pair of VICs */ + vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid); + vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid); + + /* add the timer sub-irqs */ + + set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0); + set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1); + set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2); + set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3); + set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4); + + for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) { + set_irq_chip(irq, &s3c_irq_timer); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + + for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) + s3c64xx_uart_irq(&uart_irqs[uart]); +} + + diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c new file mode 100644 index 0000000..8d9a0ca --- /dev/null +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -0,0 +1,655 @@ +/* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C6400 based common clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/sysdev.h> +#include <linux/io.h> + +#include <mach/hardware.h> +#include <mach/map.h> + +#include <plat/cpu-freq.h> + +#include <plat/regs-clock.h> +#include <plat/clock.h> +#include <plat/cpu.h> +#include <plat/pll.h> + +/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call + * ext_xtal_mux for want of an actual name from the manual. +*/ + +struct clk clk_ext_xtal_mux = { + .name = "ext_xtal", + .id = -1, +}; + +#define clk_fin_apll clk_ext_xtal_mux +#define clk_fin_mpll clk_ext_xtal_mux +#define clk_fin_epll clk_ext_xtal_mux + +#define clk_fout_mpll clk_mpll + +struct clk_sources { + unsigned int nr_sources; + struct clk **sources; +}; + +struct clksrc_clk { + struct clk clk; + unsigned int mask; + unsigned int shift; + + struct clk_sources *sources; + + unsigned int divider_shift; + void __iomem *reg_divider; +}; + +struct clk clk_fout_apll = { + .name = "fout_apll", + .id = -1, +}; + +static struct clk *clk_src_apll_list[] = { + [0] = &clk_fin_apll, + [1] = &clk_fout_apll, +}; + +static struct clk_sources clk_src_apll = { + .sources = clk_src_apll_list, + .nr_sources = ARRAY_SIZE(clk_src_apll_list), +}; + +struct clksrc_clk clk_mout_apll = { + .clk = { + .name = "mout_apll", + .id = -1, + }, + .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT, + .mask = S3C6400_CLKSRC_APLL_MOUT, + .sources = &clk_src_apll, +}; + +struct clk clk_fout_epll = { + .name = "fout_epll", + .id = -1, +}; + +static struct clk *clk_src_epll_list[] = { + [0] = &clk_fin_epll, + [1] = &clk_fout_epll, +}; + +static struct clk_sources clk_src_epll = { + .sources = clk_src_epll_list, + .nr_sources = ARRAY_SIZE(clk_src_epll_list), +}; + +struct clksrc_clk clk_mout_epll = { + .clk = { + .name = "mout_epll", + .id = -1, + }, + .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT, + .mask = S3C6400_CLKSRC_EPLL_MOUT, + .sources = &clk_src_epll, +}; + +static struct clk *clk_src_mpll_list[] = { + [0] = &clk_fin_mpll, + [1] = &clk_fout_mpll, +}; + +static struct clk_sources clk_src_mpll = { + .sources = clk_src_mpll_list, + .nr_sources = ARRAY_SIZE(clk_src_mpll_list), +}; + +struct clksrc_clk clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + .id = -1, + }, + .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT, + .mask = S3C6400_CLKSRC_MPLL_MOUT, + .sources = &clk_src_mpll, +}; + +static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + + printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); + + if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK) + rate /= 2; + + return rate; +} + +struct clk clk_dout_mpll = { + .name = "dout_mpll", + .id = -1, + .parent = &clk_mout_mpll.clk, + .get_rate = s3c64xx_clk_doutmpll_get_rate, +}; + +static struct clk *clkset_spi_mmc_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, + &clk_27m, +}; + +static struct clk_sources clkset_spi_mmc = { + .sources = clkset_spi_mmc_list, + .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), +}; + +static struct clk *clkset_irda_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + NULL, + &clk_27m, +}; + +static struct clk_sources clkset_irda = { + .sources = clkset_irda_list, + .nr_sources = ARRAY_SIZE(clkset_irda_list), +}; + +static struct clk *clkset_uart_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + NULL, + NULL +}; + +static struct clk_sources clkset_uart = { + .sources = clkset_uart_list, + .nr_sources = ARRAY_SIZE(clkset_uart_list), +}; + +static struct clk *clkset_uhost_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, + &clk_48m, +}; + +static struct clk_sources clkset_uhost = { + .sources = clkset_uhost_list, + .nr_sources = ARRAY_SIZE(clkset_uhost_list), +}; + + +/* The peripheral clocks are all controlled via clocksource followed + * by an optional divider and gate stage. We currently roll this into + * one clock which hides the intermediate clock from the mux. + * + * Note, the JPEG clock can only be an even divider... + * + * The scaler and LCD clocks depend on the S3C64XX version, and also + * have a common parent divisor so are not included here. + */ + +static inline struct clksrc_clk *to_clksrc(struct clk *clk) +{ + return container_of(clk, struct clksrc_clk, clk); +} + +static unsigned long s3c64xx_getrate_clksrc(struct clk *clk) +{ + struct clksrc_clk *sclk = to_clksrc(clk); + unsigned long rate = clk_get_rate(clk->parent); + u32 clkdiv = __raw_readl(sclk->reg_divider); + + clkdiv >>= sclk->divider_shift; + clkdiv &= 0xf; + clkdiv++; + + rate /= clkdiv; + return rate; +} + +static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate) +{ + struct clksrc_clk *sclk = to_clksrc(clk); + void __iomem *reg = sclk->reg_divider; + unsigned int div; + u32 val; + + rate = clk_round_rate(clk, rate); + div = clk_get_rate(clk->parent) / rate; + + val = __raw_readl(reg); + val &= ~sclk->mask; + val |= (rate - 1) << sclk->shift; + __raw_writel(val, reg); + + return 0; +} + +static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent) +{ + struct clksrc_clk *sclk = to_clksrc(clk); + struct clk_sources *srcs = sclk->sources; + u32 clksrc = __raw_readl(S3C_CLK_SRC); + int src_nr = -1; + int ptr; + + for (ptr = 0; ptr < srcs->nr_sources; ptr++) + if (srcs->sources[ptr] == parent) { + src_nr = ptr; + break; + } + + if (src_nr >= 0) { + clksrc &= ~sclk->mask; + clksrc |= src_nr << sclk->shift; + + __raw_writel(clksrc, S3C_CLK_SRC); + return 0; + } + + return -EINVAL; +} + +static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk, + unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + int div; + + if (rate > parent_rate) + rate = parent_rate; + else { + div = rate / parent_rate; + + if (div == 0) + div = 1; + if (div > 16) + div = 16; + + rate = parent_rate / div; + } + + return rate; +} + +static struct clksrc_clk clk_mmc0 = { + .clk = { + .name = "mmc_bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_MMC0, + .enable = s3c64xx_sclk_ctrl, + .set_parent = s3c64xx_setparent_clksrc, + .get_rate = s3c64xx_getrate_clksrc, + .set_rate = s3c64xx_setrate_clksrc, + .round_rate = s3c64xx_roundrate_clksrc, + }, + .shift = S3C6400_CLKSRC_MMC0_SHIFT, + .mask = S3C6400_CLKSRC_MMC0_MASK, + .sources = &clkset_spi_mmc, + .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT, + .reg_divider = S3C_CLK_DIV1, +}; + +static struct clksrc_clk clk_mmc1 = { + .clk = { + .name = "mmc_bus", + .id = 1, + .ctrlbit = S3C_CLKCON_SCLK_MMC1, + .enable = s3c64xx_sclk_ctrl, + .get_rate = s3c64xx_getrate_clksrc, + .set_rate = s3c64xx_setrate_clksrc, + .set_parent = s3c64xx_setparent_clksrc, + .round_rate = s3c64xx_roundrate_clksrc, + }, + .shift = S3C6400_CLKSRC_MMC1_SHIFT, + .mask = S3C6400_CLKSRC_MMC1_MASK, + .sources = &clkset_spi_mmc, + .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT, + .reg_divider = S3C_CLK_DIV1, +}; + +static struct clksrc_clk clk_mmc2 = { + .clk = { + .name = "mmc_bus", + .id = 2, + .ctrlbit = S3C_CLKCON_SCLK_MMC2, + .enable = s3c64xx_sclk_ctrl, + .get_rate = s3c64xx_getrate_clksrc, + .set_rate = s3c64xx_setrate_clksrc, + .set_parent = s3c64xx_setparent_clksrc, + .round_rate = s3c64xx_roundrate_clksrc, + }, + .shift = S3C6400_CLKSRC_MMC2_SHIFT, + .mask = S3C6400_CLKSRC_MMC2_MASK, + .sources = &clkset_spi_mmc, + .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT, + .reg_divider = S3C_CLK_DIV1, +}; + +static struct clksrc_clk clk_usbhost = { + .clk = { + .name = "usb-host-bus", + .id = -1, + .ctrlbit = S3C_CLKCON_SCLK_UHOST, + .enable = s3c64xx_sclk_ctrl, + .set_parent = s3c64xx_setparent_clksrc, + .get_rate = s3c64xx_getrate_clksrc, + .set_rate = s3c64xx_setrate_clksrc, + .round_rate = s3c64xx_roundrate_clksrc, + }, + .shift = S3C6400_CLKSRC_UHOST_SHIFT, + .mask = S3C6400_CLKSRC_UHOST_MASK, + .sources = &clkset_uhost, + .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT, + .reg_divider = S3C_CLK_DIV1, +}; + +static struct clksrc_clk clk_uart_uclk1 = { + .clk = { + .name = "uclk1", + .id = -1, + .ctrlbit = S3C_CLKCON_SCLK_UART, + .enable = s3c64xx_sclk_ctrl, + .set_parent = s3c64xx_setparent_clksrc, + .get_rate = s3c64xx_getrate_clksrc, + .set_rate = s3c64xx_setrate_clksrc, + .round_rate = s3c64xx_roundrate_clksrc, + }, + .shift = S3C6400_CLKSRC_UART_SHIFT, + .mask = S3C6400_CLKSRC_UART_MASK, + .sources = &clkset_uart, + .divider_shift = S3C6400_CLKDIV2_UART_SHIFT, + .reg_divider = S3C_CLK_DIV2, +}; + +/* Where does UCLK0 come from? */ + +static struct clksrc_clk clk_spi0 = { + .clk = { + .name = "spi-bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_SPI0, + .enable = s3c64xx_sclk_ctrl, + .set_parent = s3c64xx_setparent_clksrc, + .get_rate = s3c64xx_getrate_clksrc, + .set_rate = s3c64xx_setrate_clksrc, + .round_rate = s3c64xx_roundrate_clksrc, + }, + .shift = S3C6400_CLKSRC_SPI0_SHIFT, + .mask = S3C6400_CLKSRC_SPI0_MASK, + .sources = &clkset_spi_mmc, + .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT, + .reg_divider = S3C_CLK_DIV2, +}; + +static struct clksrc_clk clk_spi1 = { + .clk = { + .name = "spi-bus", + .id = 1, + .ctrlbit = S3C_CLKCON_SCLK_SPI1, + .enable = s3c64xx_sclk_ctrl, + .set_parent = s3c64xx_setparent_clksrc, + .get_rate = s3c64xx_getrate_clksrc, + .set_rate = s3c64xx_setrate_clksrc, + .round_rate = s3c64xx_roundrate_clksrc, + }, + .shift = S3C6400_CLKSRC_SPI1_SHIFT, + .mask = S3C6400_CLKSRC_SPI1_MASK, + .sources = &clkset_spi_mmc, + .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT, + .reg_divider = S3C_CLK_DIV2, +}; + +static struct clk clk_iis_cd0 = { + .name = "iis_cdclk0", + .id = -1, +}; + +static struct clk clk_iis_cd1 = { + .name = "iis_cdclk1", + .id = -1, +}; + +static struct clk clk_pcm_cd = { + .name = "pcm_cdclk", + .id = -1, +}; + +static struct clk *clkset_audio0_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_dout_mpll, + [2] = &clk_fin_epll, + [3] = &clk_iis_cd0, + [4] = &clk_pcm_cd, +}; + +static struct clk_sources clkset_audio0 = { + .sources = clkset_audio0_list, + .nr_sources = ARRAY_SIZE(clkset_audio0_list), +}; + +static struct clksrc_clk clk_audio0 = { + .clk = { + .name = "audio-bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, + .enable = s3c64xx_sclk_ctrl, + .set_parent = s3c64xx_setparent_clksrc, + .get_rate = s3c64xx_getrate_clksrc, + .set_rate = s3c64xx_setrate_clksrc, + .round_rate = s3c64xx_roundrate_clksrc, + }, + .shift = S3C6400_CLKSRC_AUDIO0_SHIFT, + .mask = S3C6400_CLKSRC_AUDIO0_MASK, + .sources = &clkset_audio0, + .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT, + .reg_divider = S3C_CLK_DIV2, +}; + +static struct clk *clkset_audio1_list[] = { + [0] = &clk_mout_epll.clk, + [1] = &clk_dout_mpll, + [2] = &clk_fin_epll, + [3] = &clk_iis_cd1, + [4] = &clk_pcm_cd, +}; + +static struct clk_sources clkset_audio1 = { + .sources = clkset_audio1_list, + .nr_sources = ARRAY_SIZE(clkset_audio1_list), +}; + +static struct clksrc_clk clk_audio1 = { + .clk = { + .name = "audio-bus", + .id = 1, + .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, + .enable = s3c64xx_sclk_ctrl, + .set_parent = s3c64xx_setparent_clksrc, + .get_rate = s3c64xx_getrate_clksrc, + .set_rate = s3c64xx_setrate_clksrc, + .round_rate = s3c64xx_roundrate_clksrc, + }, + .shift = S3C6400_CLKSRC_AUDIO1_SHIFT, + .mask = S3C6400_CLKSRC_AUDIO1_MASK, + .sources = &clkset_audio1, + .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT, + .reg_divider = S3C_CLK_DIV2, +}; + +static struct clksrc_clk clk_irda = { + .clk = { + .name = "irda-bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_IRDA, + .enable = s3c64xx_sclk_ctrl, + .set_parent = s3c64xx_setparent_clksrc, + .get_rate = s3c64xx_getrate_clksrc, + .set_rate = s3c64xx_setrate_clksrc, + .round_rate = s3c64xx_roundrate_clksrc, + }, + .shift = S3C6400_CLKSRC_IRDA_SHIFT, + .mask = S3C6400_CLKSRC_IRDA_MASK, + .sources = &clkset_irda, + .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT, + .reg_divider = S3C_CLK_DIV2, +}; + +/* Clock initialisation code */ + +static struct clksrc_clk *init_parents[] = { + &clk_mout_apll, + &clk_mout_epll, + &clk_mout_mpll, + &clk_mmc0, + &clk_mmc1, + &clk_mmc2, + &clk_usbhost, + &clk_uart_uclk1, + &clk_spi0, + &clk_spi1, + &clk_audio0, + &clk_audio1, + &clk_irda, +}; + +static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) +{ + struct clk_sources *srcs = clk->sources; + u32 clksrc = __raw_readl(S3C_CLK_SRC); + + clksrc &= clk->mask; + clksrc >>= clk->shift; + + if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { + printk(KERN_ERR "%s: bad source %d\n", + clk->clk.name, clksrc); + return; + } + + clk->clk.parent = srcs->sources[clksrc]; + + printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", + clk->clk.name, clk->clk.parent->name, clksrc, + clk_get_rate(&clk->clk)); +} + +#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) + +void __init_or_cpufreq s3c6400_setup_clocks(void) +{ + struct clk *xtal_clk; + unsigned long xtal; + unsigned long fclk; + unsigned long hclk; + unsigned long hclk2; + unsigned long pclk; + unsigned long epll; + unsigned long apll; + unsigned long mpll; + unsigned int ptr; + u32 clkdiv0; + + printk(KERN_DEBUG "%s: registering clocks\n", __func__); + + clkdiv0 = __raw_readl(S3C_CLK_DIV0); + printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0); + + xtal_clk = clk_get(NULL, "xtal"); + BUG_ON(IS_ERR(xtal_clk)); + + xtal = clk_get_rate(xtal_clk); + clk_put(xtal_clk); + + printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); + + epll = s3c6400_get_epll(xtal); + mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); + apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); + + fclk = mpll; + + printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", + apll, mpll, epll); + + hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); + hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); + pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); + + printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n", + hclk2, hclk, pclk); + + clk_fout_mpll.rate = mpll; + clk_fout_epll.rate = epll; + clk_fout_apll.rate = apll; + + clk_h.rate = hclk; + clk_p.rate = pclk; + clk_f.rate = fclk; + + for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) + s3c6400_set_clksrc(init_parents[ptr]); +} + +static struct clk *clks[] __initdata = { + &clk_ext_xtal_mux, + &clk_iis_cd0, + &clk_iis_cd1, + &clk_pcm_cd, + &clk_mout_epll.clk, + &clk_fout_epll, + &clk_mout_mpll.clk, + &clk_dout_mpll, + &clk_mmc0.clk, + &clk_mmc1.clk, + &clk_mmc2.clk, + &clk_usbhost.clk, + &clk_uart_uclk1.clk, + &clk_spi0.clk, + &clk_spi1.clk, + &clk_audio0.clk, + &clk_audio1.clk, + &clk_irda.clk, +}; + +void __init s3c6400_register_clocks(void) +{ + struct clk *clkp; + int ret; + int ptr; + + for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { + clkp = clks[ptr]; + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + } + + clk_mpll.parent = &clk_mout_mpll.clk; + clk_epll.parent = &clk_mout_epll.clk; +} diff --git a/arch/arm/plat-s3c64xx/s3c6400-init.c b/arch/arm/plat-s3c64xx/s3c6400-init.c new file mode 100644 index 0000000..6c28f39 --- /dev/null +++ b/arch/arm/plat-s3c64xx/s3c6400-init.c @@ -0,0 +1,29 @@ +/* linux/arch/arm/plat-s3c64xx/s3c6400-init.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C6400 - CPU initialisation (common with other S3C64XX chips) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/s3c6400.h> +#include <plat/s3c6410.h> + +/* uart registration process */ + +void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); +} diff --git a/arch/arm/plat-s3c64xx/setup-fb-24bpp.c b/arch/arm/plat-s3c64xx/setup-fb-24bpp.c new file mode 100644 index 0000000..8e28e44 --- /dev/null +++ b/arch/arm/plat-s3c64xx/setup-fb-24bpp.c @@ -0,0 +1,37 @@ +/* linux/arch/arm/plat-s3c64xx/setup-fb-24bpp.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Base S3C64XX setup information for 24bpp LCD framebuffer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/fb.h> + +#include <mach/regs-fb.h> +#include <mach/gpio.h> +#include <plat/fb.h> +#include <plat/gpio-cfg.h> + +extern void s3c64xx_fb_gpio_setup_24bpp(void) +{ + unsigned int gpio; + + for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } +} diff --git a/arch/arm/plat-s3c64xx/setup-i2c0.c b/arch/arm/plat-s3c64xx/setup-i2c0.c new file mode 100644 index 0000000..3644807 --- /dev/null +++ b/arch/arm/plat-s3c64xx/setup-i2c0.c @@ -0,0 +1,31 @@ +/* linux/arch/arm/plat-s3c64xx/setup-i2c0.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Base S3C64XX I2C bus 0 gpio configuration + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct platform_device; /* don't need the contents */ + +#include <mach/gpio.h> +#include <plat/iic.h> +#include <plat/gpio-bank-b.h> +#include <plat/gpio-cfg.h> + +void s3c_i2c0_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0); + s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0); + s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/plat-s3c64xx/setup-i2c1.c b/arch/arm/plat-s3c64xx/setup-i2c1.c new file mode 100644 index 0000000..bbe229b --- /dev/null +++ b/arch/arm/plat-s3c64xx/setup-i2c1.c @@ -0,0 +1,31 @@ +/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Base S3C64XX I2C bus 1 gpio configuration + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct platform_device; /* don't need the contents */ + +#include <mach/gpio.h> +#include <plat/iic.h> +#include <plat/gpio-bank-b.h> +#include <plat/gpio-cfg.h> + +void s3c_i2c1_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgpin(S3C64XX_GPB(2), S3C64XX_GPB2_I2C_SCL1); + s3c_gpio_cfgpin(S3C64XX_GPB(3), S3C64XX_GPB3_I2C_SDA1); + s3c_gpio_setpull(S3C64XX_GPB(2), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S3C64XX_GPB(3), S3C_GPIO_PULL_UP); +} diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 43aa202..fd23c0e 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -12,7 +12,7 @@ # # http://www.arm.linux.org.uk/developer/machines/?action=new # -# Last update: Thu Sep 25 10:10:50 2008 +# Last update: Sun Nov 30 16:39:36 2008 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -1380,7 +1380,7 @@ holon MACH_HOLON HOLON 1377 olip8 MACH_OLIP8 OLIP8 1378 ghi270hg MACH_GHI270HG GHI270HG 1379 davinci_dm6467_evm MACH_DAVINCI_DM6467_EVM DAVINCI_DM6467_EVM 1380 -davinci_dm355_evm MACH_DAVINCI_DM350_EVM DAVINCI_DM350_EVM 1381 +davinci_dm355_evm MACH_DAVINCI_DM355_EVM DAVINCI_DM355_EVM 1381 blackriver MACH_BLACKRIVER BLACKRIVER 1383 sandgate_wp MACH_SANDGATEWP SANDGATEWP 1384 cdotbwsg MACH_CDOTBWSG CDOTBWSG 1385 @@ -1771,7 +1771,7 @@ axs_ultrax MACH_AXS_ULTRAX AXS_ULTRAX 1779 at572d940deb MACH_AT572D940DEB AT572D940DEB 1780 davinci_da8xx_evm MACH_DAVINCI_DA8XX_EVM DAVINCI_DA8XX_EVM 1781 ep9302 MACH_EP9302 EP9302 1782 -at572d940hfeb MACH_AT572D940HFEB AT572D940HFEB 1783 +at572d940hfek MACH_AT572D940HFEB AT572D940HFEB 1783 cybook3 MACH_CYBOOK3 CYBOOK3 1784 wdg002 MACH_WDG002 WDG002 1785 sg560adsl MACH_SG560ADSL SG560ADSL 1786 @@ -1899,3 +1899,98 @@ rut100 MACH_RUT100 RUT100 1908 asusp535 MACH_ASUSP535 ASUSP535 1909 htcraphael MACH_HTCRAPHAEL HTCRAPHAEL 1910 sygdg1 MACH_SYGDG1 SYGDG1 1911 +sygdg2 MACH_SYGDG2 SYGDG2 1912 +seoul MACH_SEOUL SEOUL 1913 +salerno MACH_SALERNO SALERNO 1914 +ucn_s3c64xx MACH_UCN_S3C64XX UCN_S3C64XX 1915 +msm7201a MACH_MSM7201A MSM7201A 1916 +lpr1 MACH_LPR1 LPR1 1917 +armadillo500fx MACH_ARMADILLO500FX ARMADILLO500FX 1918 +g3evm MACH_G3EVM G3EVM 1919 +z3_dm355 MACH_Z3_DM355 Z3_DM355 1920 +w90p910evb MACH_W90P910EVB W90P910EVB 1921 +w90p920evb MACH_W90P920EVB W90P920EVB 1922 +w90p950evb MACH_W90P950EVB W90P950EVB 1923 +w90n960evb MACH_W90N960EVB W90N960EVB 1924 +camhd MACH_CAMHD CAMHD 1925 +mvc100 MACH_MVC100 MVC100 1926 +electrum_200 MACH_ELECTRUM_200 ELECTRUM_200 1927 +htcjade MACH_HTCJADE HTCJADE 1928 +memphis MACH_MEMPHIS MEMPHIS 1929 +imx27sbc MACH_IMX27SBC IMX27SBC 1930 +lextar MACH_LEXTAR LEXTAR 1931 +mv88f6281gtw_ge MACH_MV88F6281GTW_GE MV88F6281GTW_GE 1932 +ncp MACH_NCP NCP 1933 +z32an_series MACH_Z32AN Z32AN 1934 +tmq_capd MACH_TMQ_CAPD TMQ_CAPD 1935 +omap3_wl MACH_OMAP3_WL OMAP3_WL 1936 +chumby MACH_CHUMBY CHUMBY 1937 +atsarm9 MACH_ATSARM9 ATSARM9 1938 +davinci_dm365_evm MACH_DAVINCI_DM365_EVM DAVINCI_DM365_EVM 1939 +bahamas MACH_BAHAMAS BAHAMAS 1940 +das MACH_DAS DAS 1941 +minidas MACH_MINIDAS MINIDAS 1942 +vk1000 MACH_VK1000 VK1000 1943 +centro MACH_CENTRO CENTRO 1944 +ctera_2bay MACH_CTERA_2BAY CTERA_2BAY 1945 +edgeconnect MACH_EDGECONNECT EDGECONNECT 1946 +nd27000 MACH_ND27000 ND27000 1947 +cobra MACH_GEMALTO_COBRA GEMALTO_COBRA 1948 +ingelabs_comet MACH_INGELABS_COMET INGELABS_COMET 1949 +pollux_wiz MACH_POLLUX_WIZ POLLUX_WIZ 1950 +blackstone MACH_BLACKSTONE BLACKSTONE 1951 +topaz MACH_TOPAZ TOPAZ 1952 +aixle MACH_AIXLE AIXLE 1953 +mw998 MACH_MW998 MW998 1954 +nokia_rx51 MACH_NOKIA_RX51 NOKIA_RX51 1955 +vsc5605ev MACH_VSC5605EV VSC5605EV 1956 +nt98700dk MACH_NT98700DK NT98700DK 1957 +icontact MACH_ICONTACT ICONTACT 1958 +swarco_frcpu MACH_SWARCO_FRCPU SWARCO_FRCPU 1959 +swarco_scpu MACH_SWARCO_SCPU SWARCO_SCPU 1960 +bbox_p16 MACH_BBOX_P16 BBOX_P16 1961 +bstd MACH_BSTD BSTD 1962 +sbc2440ii MACH_SBC2440II SBC2440II 1963 +pcm034 MACH_PCM034 PCM034 1964 +neso MACH_NESO NESO 1965 +wlnx_9g20 MACH_WLNX_9G20 WLNX_9G20 1966 +omap_zoom2 MACH_OMAP_ZOOM2 OMAP_ZOOM2 1967 +totemnova MACH_TOTEMNOVA TOTEMNOVA 1968 +c5000 MACH_C5000 C5000 1969 +unipo_at91sam9263 MACH_UNIPO_AT91SAM9263 UNIPO_AT91SAM9263 1970 +ethernut5 MACH_ETHERNUT5 ETHERNUT5 1971 +arm11 MACH_ARM11 ARM11 1972 +cpuat9260 MACH_CPUAT9260 CPUAT9260 1973 +cpupxa255 MACH_CPUPXA255 CPUPXA255 1974 +cpuimx27 MACH_CPUIMX27 CPUIMX27 1975 +cheflux MACH_CHEFLUX CHEFLUX 1976 +eb_cpux9k2 MACH_EB_CPUX9K2 EB_CPUX9K2 1977 +opcotec MACH_OPCOTEC OPCOTEC 1978 +yt MACH_YT YT 1979 +motoq MACH_MOTOQ MOTOQ 1980 +bsb1 MACH_BSB1 BSB1 1981 +acs5k MACH_ACS5K ACS5K 1982 +milan MACH_MILAN MILAN 1983 +quartzv2 MACH_QUARTZV2 QUARTZV2 1984 +rsvp MACH_RSVP RSVP 1985 +rmp200 MACH_RMP200 RMP200 1986 +snapper_9260 MACH_SNAPPER_9260 SNAPPER_9260 1987 +dsm320 MACH_DSM320 DSM320 1988 +adsgcm MACH_ADSGCM ADSGCM 1989 +ase2_400 MACH_ASE2_400 ASE2_400 1990 +pizza MACH_PIZZA PIZZA 1991 +spot_ngpl MACH_SPOT_NGPL SPOT_NGPL 1992 +armata MACH_ARMATA ARMATA 1993 +exeda MACH_EXEDA EXEDA 1994 +mx31sf005 MACH_MX31SF005 MX31SF005 1995 +f5d8231_4_v2 MACH_F5D8231_4_V2 F5D8231_4_V2 1996 +q2440 MACH_Q2440 Q2440 1997 +qq2440 MACH_QQ2440 QQ2440 1998 +mini2440 MACH_MINI2440 MINI2440 1999 +colibri300 MACH_COLIBRI300 COLIBRI300 2000 +jades MACH_JADES JADES 2001 +spark MACH_SPARK SPARK 2002 +benzina MACH_BENZINA BENZINA 2003 +blaze MACH_BLAZE BLAZE 2004 +linkstation_ls_hgl MACH_LINKSTATION_LS_HGL LINKSTATION_LS_HGL 2005 +htcvenus MACH_HTCVENUS HTCVENUS 2006 diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h index c85860b..8de86e4 100644 --- a/arch/arm/vfp/vfp.h +++ b/arch/arm/vfp/vfp.h @@ -377,6 +377,6 @@ struct op { u32 flags; }; -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) || defined(CONFIG_PM) extern void vfp_save_state(void *location, u32 fpexc); #endif diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index a62dcf7..c92a08b 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -101,9 +101,12 @@ ENTRY(vfp_support_entry) VFPFSTMIA r4, r5 @ save the working registers VFPFMRX r5, FPSCR @ current status tst r1, #FPEXC_EX @ is there additional state to save? - VFPFMRX r6, FPINST, NE @ FPINST (only if FPEXC.EX is set) - tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read? - VFPFMRX r8, FPINST2, NE @ FPINST2 if needed (and present) + beq 1f + VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set) + tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? + beq 1f + VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present) +1: stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 @ and point r4 at the word at the @ start of the register dump @@ -117,9 +120,12 @@ no_old_VFP_process: @ FPEXC is in a safe state ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 tst r1, #FPEXC_EX @ is there additional state to restore? - VFPFMXR FPINST, r6, NE @ restore FPINST (only if FPEXC.EX is set) - tstne r1, #FPEXC_FP2V @ is there an FPINST2 to write? - VFPFMXR FPINST2, r8, NE @ FPINST2 if needed (and present) + beq 1f + VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set) + tst r1, #FPEXC_FP2V @ is there an FPINST2 to write? + beq 1f + VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present) +1: VFPFMXR FPSCR, r5 @ restore status check_for_exception: @@ -166,7 +172,7 @@ process_exception: @ retry the faulted instruction ENDPROC(vfp_support_entry) -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) || defined(CONFIG_PM) ENTRY(vfp_save_state) @ Save the current VFP state @ r0 - save location @@ -175,9 +181,12 @@ ENTRY(vfp_save_state) VFPFSTMIA r0, r2 @ save the working registers VFPFMRX r2, FPSCR @ current status tst r1, #FPEXC_EX @ is there additional state to save? - VFPFMRX r3, FPINST, NE @ FPINST (only if FPEXC.EX is set) - tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read? - VFPFMRX r12, FPINST2, NE @ FPINST2 if needed (and present) + beq 1f + VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set) + tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? + beq 1f + VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present) +1: stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 mov pc, lr ENDPROC(vfp_save_state) diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index c0d2c9b..9f476a1 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -322,6 +322,61 @@ static void vfp_enable(void *unused) set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11)); } +#ifdef CONFIG_PM +#include <linux/sysdev.h> + +static int vfp_pm_suspend(struct sys_device *dev, pm_message_t state) +{ + struct thread_info *ti = current_thread_info(); + u32 fpexc = fmrx(FPEXC); + + /* if vfp is on, then save state for resumption */ + if (fpexc & FPEXC_EN) { + printk(KERN_DEBUG "%s: saving vfp state\n", __func__); + vfp_save_state(&ti->vfpstate, fpexc); + + /* disable, just in case */ + fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); + } + + /* clear any information we had about last context state */ + memset(last_VFP_context, 0, sizeof(last_VFP_context)); + + return 0; +} + +static int vfp_pm_resume(struct sys_device *dev) +{ + /* ensure we have access to the vfp */ + vfp_enable(NULL); + + /* and disable it to ensure the next usage restores the state */ + fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); + + return 0; +} + +static struct sysdev_class vfp_pm_sysclass = { + .name = "vfp", + .suspend = vfp_pm_suspend, + .resume = vfp_pm_resume, +}; + +static struct sys_device vfp_pm_sysdev = { + .cls = &vfp_pm_sysclass, +}; + +static void vfp_pm_init(void) +{ + sysdev_class_register(&vfp_pm_sysclass); + sysdev_register(&vfp_pm_sysdev); +} + + +#else +static inline void vfp_pm_init(void) { } +#endif /* CONFIG_PM */ + #include <linux/smp.h> /* @@ -365,12 +420,22 @@ static int __init vfp_init(void) vfp_vector = vfp_support_entry; thread_register_notifier(&vfp_notifier_block); + vfp_pm_init(); /* * We detected VFP, and the support code is * in place; report VFP support to userspace. */ elf_hwcap |= HWCAP_VFP; +#ifdef CONFIG_NEON + /* + * Check for the presence of the Advanced SIMD + * load/store instructions, integer and single + * precision floating point operations. + */ + if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100) + elf_hwcap |= HWCAP_NEON; +#endif } return 0; } diff --git a/drivers/char/ds1620.c b/drivers/char/ds1620.c index 74e9cd8..61f0146 100644 --- a/drivers/char/ds1620.c +++ b/drivers/char/ds1620.c @@ -43,52 +43,51 @@ static const char *fan_state[] = { "off", "on", "on (hardwired)" }; * chance that the WaveArtist driver could touch these bits to * enable or disable the speaker. */ -extern spinlock_t gpio_lock; extern unsigned int system_rev; static inline void netwinder_ds1620_set_clk(int clk) { - gpio_modify_op(GPIO_DSCLK, clk ? GPIO_DSCLK : 0); + nw_gpio_modify_op(GPIO_DSCLK, clk ? GPIO_DSCLK : 0); } static inline void netwinder_ds1620_set_data(int dat) { - gpio_modify_op(GPIO_DATA, dat ? GPIO_DATA : 0); + nw_gpio_modify_op(GPIO_DATA, dat ? GPIO_DATA : 0); } static inline int netwinder_ds1620_get_data(void) { - return gpio_read() & GPIO_DATA; + return nw_gpio_read() & GPIO_DATA; } static inline void netwinder_ds1620_set_data_dir(int dir) { - gpio_modify_io(GPIO_DATA, dir ? GPIO_DATA : 0); + nw_gpio_modify_io(GPIO_DATA, dir ? GPIO_DATA : 0); } static inline void netwinder_ds1620_reset(void) { - cpld_modify(CPLD_DS_ENABLE, 0); - cpld_modify(CPLD_DS_ENABLE, CPLD_DS_ENABLE); + nw_cpld_modify(CPLD_DS_ENABLE, 0); + nw_cpld_modify(CPLD_DS_ENABLE, CPLD_DS_ENABLE); } static inline void netwinder_lock(unsigned long *flags) { - spin_lock_irqsave(&gpio_lock, *flags); + spin_lock_irqsave(&nw_gpio_lock, *flags); } static inline void netwinder_unlock(unsigned long *flags) { - spin_unlock_irqrestore(&gpio_lock, *flags); + spin_unlock_irqrestore(&nw_gpio_lock, *flags); } static inline void netwinder_set_fan(int i) { unsigned long flags; - spin_lock_irqsave(&gpio_lock, flags); - gpio_modify_op(GPIO_FAN, i ? GPIO_FAN : 0); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_gpio_modify_op(GPIO_FAN, i ? GPIO_FAN : 0); + spin_unlock_irqrestore(&nw_gpio_lock, flags); } static inline int netwinder_get_fan(void) @@ -96,7 +95,7 @@ static inline int netwinder_get_fan(void) if ((system_rev & 0xf000) == 0x4000) return FAN_ALWAYS_ON; - return (gpio_read() & GPIO_FAN) ? FAN_ON : FAN_OFF; + return (nw_gpio_read() & GPIO_FAN) ? FAN_ON : FAN_OFF; } /* diff --git a/drivers/char/nwflash.c b/drivers/char/nwflash.c index 006be92..8c7df5b 100644 --- a/drivers/char/nwflash.c +++ b/drivers/char/nwflash.c @@ -58,8 +58,6 @@ static volatile unsigned char *FLASH_BASE; static int gbFlashSize = KFLASH_SIZE; static DEFINE_MUTEX(nwflash_mutex); -extern spinlock_t gpio_lock; - static int get_flash_id(void) { volatile unsigned int c1, c2; @@ -616,9 +614,9 @@ static void kick_open(void) * we want to write a bit pattern XXX1 to Xilinx to enable * the write gate, which will be open for about the next 2ms. */ - spin_lock_irqsave(&gpio_lock, flags); - cpld_modify(1, 1); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE); + spin_unlock_irqrestore(&nw_gpio_lock, flags); /* * let the ISA bus to catch on... diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c index 906f9b9..587f5b2 100644 --- a/drivers/i2c/busses/i2c-pxa.c +++ b/drivers/i2c/busses/i2c-pxa.c @@ -1016,7 +1016,7 @@ static int i2c_pxa_probe(struct platform_device *dev) snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u", i2c->adap.nr); - i2c->clk = clk_get(&dev->dev, "I2CCLK"); + i2c->clk = clk_get(&dev->dev, NULL); if (IS_ERR(i2c->clk)) { ret = PTR_ERR(i2c->clk); goto eclk; diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c index b7434d2..c39079f 100644 --- a/drivers/i2c/busses/i2c-s3c2410.c +++ b/drivers/i2c/busses/i2c-s3c2410.c @@ -40,8 +40,8 @@ #include <asm/io.h> #include <mach/regs-gpio.h> -#include <asm/plat-s3c/regs-iic.h> -#include <asm/plat-s3c/iic.h> +#include <plat/regs-iic.h> +#include <plat/iic.h> /* i2c controller state */ diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig index 7a0a84b..c9f21e3 100644 --- a/drivers/ide/Kconfig +++ b/drivers/ide/Kconfig @@ -727,7 +727,7 @@ config BLK_DEV_IDE_TX4939 config IDE_ARM tristate "ARM IDE support" - depends on ARM && (ARCH_CLPS7500 || ARCH_RPC || ARCH_SHARK) + depends on ARM && (ARCH_RPC || ARCH_SHARK) default y config BLK_DEV_IDE_ICSIDE diff --git a/drivers/ide/ide_arm.c b/drivers/ide/ide_arm.c index f728f29..bdcac94 100644 --- a/drivers/ide/ide_arm.c +++ b/drivers/ide/ide_arm.c @@ -15,15 +15,8 @@ #define DRV_NAME "ide_arm" -#ifdef CONFIG_ARCH_CLPS7500 -# include <mach/hardware.h> -# -# define IDE_ARM_IO (ISASLOT_IO + 0x1f0) -# define IDE_ARM_IRQ IRQ_ISA_14 -#else -# define IDE_ARM_IO 0x1f0 -# define IDE_ARM_IRQ IRQ_HARDDISK -#endif +#define IDE_ARM_IO 0x1f0 +#define IDE_ARM_IRQ IRQ_HARDDISK static int __init ide_arm_init(void) { diff --git a/drivers/input/keyboard/omap-keypad.c b/drivers/input/keyboard/omap-keypad.c index 69e674e..db22fd9 100644 --- a/drivers/input/keyboard/omap-keypad.c +++ b/drivers/input/keyboard/omap-keypad.c @@ -101,7 +101,7 @@ static irqreturn_t omap_kp_interrupt(int irq, void *dev_id) if (cpu_is_omap24xx()) { int i; for (i = 0; i < omap_kp->rows; i++) - disable_irq(OMAP_GPIO_IRQ(row_gpios[i])); + disable_irq(gpio_to_irq(row_gpios[i])); } else /* disable keyboard interrupt and schedule for handling */ omap_writew(1, OMAP_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT); @@ -224,7 +224,7 @@ static void omap_kp_tasklet(unsigned long data) if (cpu_is_omap24xx()) { int i; for (i = 0; i < omap_kp_data->rows; i++) - enable_irq(OMAP_GPIO_IRQ(row_gpios[i])); + enable_irq(gpio_to_irq(row_gpios[i])); } else { omap_writew(0, OMAP_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT); kp_cur_group = -1; @@ -397,7 +397,7 @@ static int __init omap_kp_probe(struct platform_device *pdev) omap_writew(0, OMAP_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT); } else { for (irq_idx = 0; irq_idx < omap_kp->rows; irq_idx++) { - if (request_irq(OMAP_GPIO_IRQ(row_gpios[irq_idx]), + if (request_irq(gpio_to_irq(row_gpios[irq_idx]), omap_kp_interrupt, IRQF_TRIGGER_FALLING, "omap-keypad", omap_kp) < 0) @@ -438,7 +438,7 @@ static int omap_kp_remove(struct platform_device *pdev) gpio_free(col_gpios[i]); for (i = 0; i < omap_kp->rows; i++) { gpio_free(row_gpios[i]); - free_irq(OMAP_GPIO_IRQ(row_gpios[i]), 0); + free_irq(gpio_to_irq(row_gpios[i]), 0); } } else { omap_writew(1, OMAP_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT); diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c index 6d30c6d..0d2fc64 100644 --- a/drivers/input/keyboard/pxa27x_keypad.c +++ b/drivers/input/keyboard/pxa27x_keypad.c @@ -475,7 +475,7 @@ static int __devinit pxa27x_keypad_probe(struct platform_device *pdev) goto failed_free_mem; } - keypad->clk = clk_get(&pdev->dev, "KBDCLK"); + keypad->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(keypad->clk)) { dev_err(&pdev->dev, "failed to get keypad clock\n"); error = PTR_ERR(keypad->clk); diff --git a/drivers/input/serio/Kconfig b/drivers/input/serio/Kconfig index 27d70d32..da3c3a5 100644 --- a/drivers/input/serio/Kconfig +++ b/drivers/input/serio/Kconfig @@ -79,7 +79,7 @@ config SERIO_PARKBD config SERIO_RPCKBD tristate "Acorn RiscPC keyboard controller" - depends on ARCH_ACORN || ARCH_CLPS7500 + depends on ARCH_ACORN default y help Say Y here if you have the Acorn RiscPC and want to use an AT diff --git a/drivers/input/touchscreen/mainstone-wm97xx.c b/drivers/input/touchscreen/mainstone-wm97xx.c index ba64875..1d11e2b 100644 --- a/drivers/input/touchscreen/mainstone-wm97xx.c +++ b/drivers/input/touchscreen/mainstone-wm97xx.c @@ -31,7 +31,7 @@ #include <linux/interrupt.h> #include <linux/wm97xx.h> #include <linux/io.h> -#include <mach/pxa-regs.h> +#include <mach/regs-ac97.h> #define VERSION "0.13" diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c index eb6be58..70a7762 100644 --- a/drivers/media/video/pxa_camera.c +++ b/drivers/media/video/pxa_camera.c @@ -39,6 +39,8 @@ #include <mach/pxa-regs.h> #include <mach/camera.h> +#include "pxa_camera.h" + #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) #define PXA_CAM_DRV_NAME "pxa27x-camera" @@ -1071,7 +1073,7 @@ static int pxa_camera_probe(struct platform_device *pdev) goto exit; } - pcdev->clk = clk_get(&pdev->dev, "CAMCLK"); + pcdev->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(pcdev->clk)) { err = PTR_ERR(pcdev->clk); goto exit_kfree; diff --git a/drivers/media/video/pxa_camera.h b/drivers/media/video/pxa_camera.h new file mode 100644 index 0000000..89cbfc9 --- /dev/null +++ b/drivers/media/video/pxa_camera.h @@ -0,0 +1,95 @@ +/* Camera Interface */ +#define CICR0 __REG(0x50000000) +#define CICR1 __REG(0x50000004) +#define CICR2 __REG(0x50000008) +#define CICR3 __REG(0x5000000C) +#define CICR4 __REG(0x50000010) +#define CISR __REG(0x50000014) +#define CIFR __REG(0x50000018) +#define CITOR __REG(0x5000001C) +#define CIBR0 __REG(0x50000028) +#define CIBR1 __REG(0x50000030) +#define CIBR2 __REG(0x50000038) + +#define CICR0_DMAEN (1 << 31) /* DMA request enable */ +#define CICR0_PAR_EN (1 << 30) /* Parity enable */ +#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ +#define CICR0_ENB (1 << 28) /* Camera interface enable */ +#define CICR0_DIS (1 << 27) /* Camera interface disable */ +#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ +#define CICR0_TOM (1 << 9) /* Time-out mask */ +#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ +#define CICR0_FEM (1 << 7) /* FIFO-empty mask */ +#define CICR0_EOLM (1 << 6) /* End-of-line mask */ +#define CICR0_PERRM (1 << 5) /* Parity-error mask */ +#define CICR0_QDM (1 << 4) /* Quick-disable mask */ +#define CICR0_CDM (1 << 3) /* Disable-done mask */ +#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ +#define CICR0_EOFM (1 << 1) /* End-of-frame mask */ +#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ + +#define CICR1_TBIT (1 << 31) /* Transparency bit */ +#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ +#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ +#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ +#define CICR1_RGB_F (1 << 11) /* RGB format */ +#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ +#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ +#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ +#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ +#define CICR1_DW (0x7 << 0) /* Data width mask */ + +#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock + wait count mask */ +#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock + wait count mask */ +#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ +#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock + wait count mask */ +#define CICR2_FSW (0x7 << 0) /* Frame stabilization + wait count mask */ + +#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock + wait count mask */ +#define CICR3_EFW (0xff << 16) /* End-of-frame line clock + wait count mask */ +#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ +#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock + wait count mask */ +#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ + +#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ +#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ +#define CICR4_PCP (1 << 22) /* Pixel clock polarity */ +#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ +#define CICR4_VSP (1 << 20) /* Vertical sync polarity */ +#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ +#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ +#define CICR4_DIV (0xff << 0) /* Clock divisor mask */ + +#define CISR_FTO (1 << 15) /* FIFO time-out */ +#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ +#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ +#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ +#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ +#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ +#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ +#define CISR_EOL (1 << 8) /* End of line */ +#define CISR_PAR_ERR (1 << 7) /* Parity error */ +#define CISR_CQD (1 << 6) /* Camera interface quick disable */ +#define CISR_CDD (1 << 5) /* Camera interface disable done */ +#define CISR_SOF (1 << 4) /* Start of frame */ +#define CISR_EOF (1 << 3) /* End of frame */ +#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ +#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ +#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ + +#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ +#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ +#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ +#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ +#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ +#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ +#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ +#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ + diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c index e4c0db4..9e48545 100644 --- a/drivers/mfd/asic3.c +++ b/drivers/mfd/asic3.c @@ -474,9 +474,9 @@ static __init int asic3_gpio_probe(struct platform_device *pdev, u16 dir_reg[ASIC3_NUM_GPIO_BANKS]; int i; - memzero(alt_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); - memzero(out_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); - memzero(dir_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); + memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); + memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); + memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); /* Enable all GPIOs */ asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff); diff --git a/drivers/mfd/mcp-core.c b/drivers/mfd/mcp-core.c index b4ed57e..6063dc2 100644 --- a/drivers/mfd/mcp-core.c +++ b/drivers/mfd/mcp-core.c @@ -18,7 +18,7 @@ #include <linux/slab.h> #include <linux/string.h> -#include <asm/dma.h> +#include <mach/dma.h> #include <asm/system.h> #include "mcp.h" diff --git a/drivers/mfd/mcp-sa11x0.c b/drivers/mfd/mcp-sa11x0.c index 28380b2..62b32da 100644 --- a/drivers/mfd/mcp-sa11x0.c +++ b/drivers/mfd/mcp-sa11x0.c @@ -20,7 +20,7 @@ #include <linux/slab.h> #include <linux/platform_device.h> -#include <asm/dma.h> +#include <mach/dma.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/system.h> diff --git a/drivers/mfd/ucb1x00-assabet.c b/drivers/mfd/ucb1x00-assabet.c index 61aeaf7..86fed48 100644 --- a/drivers/mfd/ucb1x00-assabet.c +++ b/drivers/mfd/ucb1x00-assabet.c @@ -15,7 +15,7 @@ #include <linux/proc_fs.h> #include <linux/device.h> -#include <asm/dma.h> +#include <mach/dma.h> #include "ucb1x00.h" diff --git a/drivers/mfd/ucb1x00-core.c b/drivers/mfd/ucb1x00-core.c index a316f1b..6860c92 100644 --- a/drivers/mfd/ucb1x00-core.c +++ b/drivers/mfd/ucb1x00-core.c @@ -25,7 +25,7 @@ #include <linux/device.h> #include <linux/mutex.h> -#include <asm/dma.h> +#include <mach/dma.h> #include <mach/hardware.h> #include "ucb1x00.h" diff --git a/drivers/mfd/ucb1x00-ts.c b/drivers/mfd/ucb1x00-ts.c index 44762ca..61b7d3e 100644 --- a/drivers/mfd/ucb1x00-ts.c +++ b/drivers/mfd/ucb1x00-ts.c @@ -31,7 +31,7 @@ #include <linux/slab.h> #include <linux/kthread.h> -#include <asm/dma.h> +#include <mach/dma.h> #include <mach/collie.h> #include <asm/mach-types.h> diff --git a/drivers/mmc/host/imxmmc.c b/drivers/mmc/host/imxmmc.c index 2f0fcdb..eb29b1d 100644 --- a/drivers/mmc/host/imxmmc.c +++ b/drivers/mmc/host/imxmmc.c @@ -10,20 +10,6 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz> - * Changed to conform redesigned i.MX scatter gather DMA interface - * - * 2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz> - * Updated for 2.6.14 kernel - * - * 2005-12-13 Jay Monkman <jtm@smoothsmoothie.com> - * Found and corrected problems in the write path - * - * 2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz> - * The event handling rewritten right way in softirq. - * Added many ugly hacks and delays to overcome SDHC - * deficiencies - * */ #include <linux/module.h> @@ -37,9 +23,9 @@ #include <linux/mmc/card.h> #include <linux/delay.h> #include <linux/clk.h> +#include <linux/io.h> #include <asm/dma.h> -#include <asm/io.h> #include <asm/irq.h> #include <asm/sizes.h> #include <mach/mmc.h> @@ -50,17 +36,16 @@ #define DRIVER_NAME "imx-mmc" #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \ - INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \ - INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO) + INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \ + INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO) struct imxmci_host { struct mmc_host *mmc; spinlock_t lock; struct resource *res; + void __iomem *base; int irq; imx_dmach_t dma; - unsigned int clkrt; - unsigned int cmdat; volatile unsigned int imask; unsigned int power_mode; unsigned int present; @@ -74,7 +59,7 @@ struct imxmci_host { struct tasklet_struct tasklet; unsigned int status_reg; unsigned long pending_events; - /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */ + /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */ u16 *data_ptr; unsigned int data_cnt; atomic_t stuck_timeout; @@ -114,14 +99,22 @@ struct imxmci_host { static void imxmci_stop_clock(struct imxmci_host *host) { int i = 0; - MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK; - while(i < 0x1000) { - if(!(i & 0x7f)) - MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK; + u16 reg; + + reg = readw(host->base + MMC_REG_STR_STP_CLK); + writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); + while (i < 0x1000) { + if (!(i & 0x7f)) { + reg = readw(host->base + MMC_REG_STR_STP_CLK); + writew(reg | STR_STP_CLK_STOP_CLK, + host->base + MMC_REG_STR_STP_CLK); + } - if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) { + reg = readw(host->base + MMC_REG_STATUS); + if (!(reg & STATUS_CARD_BUS_CLK_RUN)) { /* Check twice before cut */ - if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) + reg = readw(host->base + MMC_REG_STATUS); + if (!(reg & STATUS_CARD_BUS_CLK_RUN)) return; } @@ -135,8 +128,10 @@ static int imxmci_start_clock(struct imxmci_host *host) unsigned int trials = 0; unsigned int delay_limit = 128; unsigned long flags; + u16 reg; - MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK; + reg = readw(host->base + MMC_REG_STR_STP_CLK); + writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK); clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events); @@ -145,18 +140,21 @@ static int imxmci_start_clock(struct imxmci_host *host) * then 6 delay loops, but during card detection (low clockrate) * it takes up to 5000 delay loops and sometimes fails for the first time */ - MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK; + reg = readw(host->base + MMC_REG_STR_STP_CLK); + writew(reg | STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); do { unsigned int delay = delay_limit; - while(delay--){ - if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN) + while (delay--) { + reg = readw(host->base + MMC_REG_STATUS); + if (reg & STATUS_CARD_BUS_CLK_RUN) /* Check twice before cut */ - if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN) + reg = readw(host->base + MMC_REG_STATUS); + if (reg & STATUS_CARD_BUS_CLK_RUN) return 0; - if(test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) + if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) return 0; } @@ -167,58 +165,59 @@ static int imxmci_start_clock(struct imxmci_host *host) * IRQ or schedule delays this function execution and the clocks has * been already stopped by other means (response processing, SDHC HW) */ - if(!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) - MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK; + if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) { + reg = readw(host->base + MMC_REG_STR_STP_CLK); + writew(reg | STR_STP_CLK_START_CLK, + host->base + MMC_REG_STR_STP_CLK); + } local_irq_restore(flags); - } while(++trials<256); + } while (++trials < 256); dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n"); return -1; } -static void imxmci_softreset(void) +static void imxmci_softreset(struct imxmci_host *host) { + int i; + /* reset sequence */ - MMC_STR_STP_CLK = 0x8; - MMC_STR_STP_CLK = 0xD; - MMC_STR_STP_CLK = 0x5; - MMC_STR_STP_CLK = 0x5; - MMC_STR_STP_CLK = 0x5; - MMC_STR_STP_CLK = 0x5; - MMC_STR_STP_CLK = 0x5; - MMC_STR_STP_CLK = 0x5; - MMC_STR_STP_CLK = 0x5; - MMC_STR_STP_CLK = 0x5; - - MMC_RES_TO = 0xff; - MMC_BLK_LEN = 512; - MMC_NOB = 1; + writew(0x08, host->base + MMC_REG_STR_STP_CLK); + writew(0x0D, host->base + MMC_REG_STR_STP_CLK); + + for (i = 0; i < 8; i++) + writew(0x05, host->base + MMC_REG_STR_STP_CLK); + + writew(0xff, host->base + MMC_REG_RES_TO); + writew(512, host->base + MMC_REG_BLK_LEN); + writew(1, host->base + MMC_REG_NOB); } static int imxmci_busy_wait_for_status(struct imxmci_host *host, - unsigned int *pstat, unsigned int stat_mask, - int timeout, const char *where) + unsigned int *pstat, unsigned int stat_mask, + int timeout, const char *where) { - int loops=0; - while(!(*pstat & stat_mask)) { - loops+=2; - if(loops >= timeout) { + int loops = 0; + + while (!(*pstat & stat_mask)) { + loops += 2; + if (loops >= timeout) { dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n", where, *pstat, stat_mask); return -1; } udelay(2); - *pstat |= MMC_STATUS; + *pstat |= readw(host->base + MMC_REG_STATUS); } - if(!loops) + if (!loops) return 0; /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */ - if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000)) + if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000)) dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n", - loops, where, *pstat, stat_mask); + loops, where, *pstat, stat_mask); return loops; } @@ -235,8 +234,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) host->data = data; data->bytes_xfered = 0; - MMC_NOB = nob; - MMC_BLK_LEN = blksz; + writew(nob, host->base + MMC_REG_NOB); + writew(blksz, host->base + MMC_REG_BLK_LEN); /* * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise. @@ -252,14 +251,14 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) host->dma_dir = DMA_FROM_DEVICE; /* Hack to enable read SCR */ - MMC_NOB = 1; - MMC_BLK_LEN = 512; + writew(1, host->base + MMC_REG_NOB); + writew(512, host->base + MMC_REG_BLK_LEN); } else { host->dma_dir = DMA_TO_DEVICE; } /* Convert back to virtual address */ - host->data_ptr = (u16*)sg_virt(data->sg); + host->data_ptr = (u16 *)sg_virt(data->sg); host->data_cnt = 0; clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events); @@ -271,10 +270,11 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) if (data->flags & MMC_DATA_READ) { host->dma_dir = DMA_FROM_DEVICE; host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, - data->sg_len, host->dma_dir); + data->sg_len, host->dma_dir); imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, - host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ); + host->res->start + MMC_REG_BUFFER_ACCESS, + DMA_MODE_READ); /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/ CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN; @@ -282,10 +282,11 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) host->dma_dir = DMA_TO_DEVICE; host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, - data->sg_len, host->dma_dir); + data->sg_len, host->dma_dir); imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, - host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE); + host->res->start + MMC_REG_BUFFER_ACCESS, + DMA_MODE_WRITE); /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/ CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN; @@ -293,12 +294,12 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) #if 1 /* This code is there only for consistency checking and can be disabled in future */ host->dma_size = 0; - for(i=0; i<host->dma_nents; i++) - host->dma_size+=data->sg[i].length; + for (i = 0; i < host->dma_nents; i++) + host->dma_size += data->sg[i].length; if (datasz > host->dma_size) { dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n", - datasz, host->dma_size); + datasz, host->dma_size); } #endif @@ -306,7 +307,7 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) wmb(); - if(host->actual_bus_width == MMC_BUS_WIDTH_4) + if (host->actual_bus_width == MMC_BUS_WIDTH_4) BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */ else BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */ @@ -317,9 +318,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events); /* start DMA engine for read, write is delayed after initial response */ - if (host->dma_dir == DMA_FROM_DEVICE) { + if (host->dma_dir == DMA_FROM_DEVICE) imx_dma_enable(host->dma); - } } static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat) @@ -351,16 +351,16 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, break; } - if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) ) + if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events)) cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */ - if ( host->actual_bus_width == MMC_BUS_WIDTH_4 ) + if (host->actual_bus_width == MMC_BUS_WIDTH_4) cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; - MMC_CMD = cmd->opcode; - MMC_ARGH = cmd->arg >> 16; - MMC_ARGL = cmd->arg & 0xffff; - MMC_CMD_DAT_CONT = cmdat; + writew(cmd->opcode, host->base + MMC_REG_CMD); + writew(cmd->arg >> 16, host->base + MMC_REG_ARGH); + writew(cmd->arg & 0xffff, host->base + MMC_REG_ARGL); + writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT); atomic_set(&host->stuck_timeout, 0); set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events); @@ -368,18 +368,18 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, imask = IMXMCI_INT_MASK_DEFAULT; imask &= ~INT_MASK_END_CMD_RES; - if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) { - /*imask &= ~INT_MASK_BUF_READY;*/ + if (cmdat & CMD_DAT_CONT_DATA_ENABLE) { + /* imask &= ~INT_MASK_BUF_READY; */ imask &= ~INT_MASK_DATA_TRAN; - if ( cmdat & CMD_DAT_CONT_WRITE ) + if (cmdat & CMD_DAT_CONT_WRITE) imask &= ~INT_MASK_WRITE_OP_DONE; - if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) + if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) imask &= ~INT_MASK_BUF_READY; } spin_lock_irqsave(&host->lock, flags); host->imask = imask; - MMC_INT_MASK = host->imask; + writew(host->imask, host->base + MMC_REG_INT_MASK); spin_unlock_irqrestore(&host->lock, flags); dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n", @@ -395,14 +395,14 @@ static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request * spin_lock_irqsave(&host->lock, flags); host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m | - IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m); + IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m); host->imask = IMXMCI_INT_MASK_DEFAULT; - MMC_INT_MASK = host->imask; + writew(host->imask, host->base + MMC_REG_INT_MASK); spin_unlock_irqrestore(&host->lock, flags); - if(req && req->cmd) + if (req && req->cmd) host->prev_cmd_code = req->cmd->opcode; host->req = NULL; @@ -416,17 +416,17 @@ static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat) struct mmc_data *data = host->data; int data_error; - if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){ + if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { imx_dma_disable(host->dma); dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents, host->dma_dir); } - if ( stat & STATUS_ERR_MASK ) { - dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat); - if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR)) + if (stat & STATUS_ERR_MASK) { + dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat); + if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR)) data->error = -EILSEQ; - else if(stat & STATUS_TIME_OUT_READ) + else if (stat & STATUS_TIME_OUT_READ) data->error = -ETIMEDOUT; else data->error = -EIO; @@ -445,7 +445,7 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat) { struct mmc_command *cmd = host->cmd; int i; - u32 a,b,c; + u32 a, b, c; struct mmc_data *data = host->data; if (!cmd) @@ -461,18 +461,18 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat) cmd->error = -EILSEQ; } - if(cmd->flags & MMC_RSP_PRESENT) { - if(cmd->flags & MMC_RSP_136) { + if (cmd->flags & MMC_RSP_PRESENT) { + if (cmd->flags & MMC_RSP_136) { for (i = 0; i < 4; i++) { - u32 a = MMC_RES_FIFO & 0xffff; - u32 b = MMC_RES_FIFO & 0xffff; - cmd->resp[i] = a<<16 | b; + a = readw(host->base + MMC_REG_RES_FIFO); + b = readw(host->base + MMC_REG_RES_FIFO); + cmd->resp[i] = a << 16 | b; } } else { - a = MMC_RES_FIFO & 0xffff; - b = MMC_RES_FIFO & 0xffff; - c = MMC_RES_FIFO & 0xffff; - cmd->resp[0] = a<<24 | b<<8 | c>>8; + a = readw(host->base + MMC_REG_RES_FIFO); + b = readw(host->base + MMC_REG_RES_FIFO); + c = readw(host->base + MMC_REG_RES_FIFO); + cmd->resp[0] = a << 24 | b << 8 | c >> 8; } } @@ -484,36 +484,34 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat) /* Wait for FIFO to be empty before starting DMA write */ - stat = MMC_STATUS; - if(imxmci_busy_wait_for_status(host, &stat, - STATUS_APPL_BUFF_FE, - 40, "imxmci_cmd_done DMA WR") < 0) { + stat = readw(host->base + MMC_REG_STATUS); + if (imxmci_busy_wait_for_status(host, &stat, + STATUS_APPL_BUFF_FE, + 40, "imxmci_cmd_done DMA WR") < 0) { cmd->error = -EIO; imxmci_finish_data(host, stat); - if(host->req) + if (host->req) imxmci_finish_request(host, host->req); dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n", - stat); + stat); return 0; } - if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { + if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) imx_dma_enable(host->dma); - } } } else { struct mmc_request *req; imxmci_stop_clock(host); req = host->req; - if(data) + if (data) imxmci_finish_data(host, stat); - if( req ) { + if (req) imxmci_finish_request(host, req); - } else { + else dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n"); - } } return 1; @@ -535,11 +533,10 @@ static int imxmci_data_done(struct imxmci_host *host, unsigned int stat) } else { struct mmc_request *req; req = host->req; - if( req ) { + if (req) imxmci_finish_request(host, req); - } else { + else dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n"); - } } return 1; @@ -552,7 +549,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat) int trans_done = 0; unsigned int stat = *pstat; - if(host->actual_bus_width != MMC_BUS_WIDTH_4) + if (host->actual_bus_width != MMC_BUS_WIDTH_4) burst_len = 16; else burst_len = 64; @@ -563,44 +560,44 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat) udelay(20); /* required for clocks < 8MHz*/ - if(host->dma_dir == DMA_FROM_DEVICE) { + if (host->dma_dir == DMA_FROM_DEVICE) { imxmci_busy_wait_for_status(host, &stat, - STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE | - STATUS_TIME_OUT_READ, - 50, "imxmci_cpu_driven_data read"); + STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE | + STATUS_TIME_OUT_READ, + 50, "imxmci_cpu_driven_data read"); - while((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) && - !(stat & STATUS_TIME_OUT_READ) && - (host->data_cnt < 512)) { + while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) && + !(stat & STATUS_TIME_OUT_READ) && + (host->data_cnt < 512)) { udelay(20); /* required for clocks < 8MHz*/ - for(i = burst_len; i>=2 ; i-=2) { + for (i = burst_len; i >= 2 ; i -= 2) { u16 data; - data = MMC_BUFFER_ACCESS; + data = readw(host->base + MMC_REG_BUFFER_ACCESS); udelay(10); /* required for clocks < 8MHz*/ - if(host->data_cnt+2 <= host->dma_size) { + if (host->data_cnt+2 <= host->dma_size) { *(host->data_ptr++) = data; } else { - if(host->data_cnt < host->dma_size) - *(u8*)(host->data_ptr) = data; + if (host->data_cnt < host->dma_size) + *(u8 *)(host->data_ptr) = data; } host->data_cnt += 2; } - stat = MMC_STATUS; + stat = readw(host->base + MMC_REG_STATUS); dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n", host->data_cnt, burst_len, stat); } - if((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512)) + if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512)) trans_done = 1; - if(host->dma_size & 0x1ff) + if (host->dma_size & 0x1ff) stat &= ~STATUS_CRC_READ_ERR; - if(stat & STATUS_TIME_OUT_READ) { + if (stat & STATUS_TIME_OUT_READ) { dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n", stat); trans_done = -1; @@ -608,12 +605,12 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat) } else { imxmci_busy_wait_for_status(host, &stat, - STATUS_APPL_BUFF_FE, - 20, "imxmci_cpu_driven_data write"); + STATUS_APPL_BUFF_FE, + 20, "imxmci_cpu_driven_data write"); - while((stat & STATUS_APPL_BUFF_FE) && - (host->data_cnt < host->dma_size)) { - if(burst_len >= host->dma_size - host->data_cnt) { + while ((stat & STATUS_APPL_BUFF_FE) && + (host->data_cnt < host->dma_size)) { + if (burst_len >= host->dma_size - host->data_cnt) { burst_len = host->dma_size - host->data_cnt; host->data_cnt = host->dma_size; trans_done = 1; @@ -621,10 +618,10 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat) host->data_cnt += burst_len; } - for(i = burst_len; i>0 ; i-=2) - MMC_BUFFER_ACCESS = *(host->data_ptr++); + for (i = burst_len; i > 0 ; i -= 2) + writew(*(host->data_ptr++), host->base + MMC_REG_BUFFER_ACCESS); - stat = MMC_STATUS; + stat = readw(host->base + MMC_REG_STATUS); dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n", burst_len, stat); @@ -639,7 +636,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat) static void imxmci_dma_irq(int dma, void *devid) { struct imxmci_host *host = devid; - uint32_t stat = MMC_STATUS; + u32 stat = readw(host->base + MMC_REG_STATUS); atomic_set(&host->stuck_timeout, 0); host->status_reg = stat; @@ -650,10 +647,11 @@ static void imxmci_dma_irq(int dma, void *devid) static irqreturn_t imxmci_irq(int irq, void *devid) { struct imxmci_host *host = devid; - uint32_t stat = MMC_STATUS; + u32 stat = readw(host->base + MMC_REG_STATUS); int handled = 1; - MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT; + writew(host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT, + host->base + MMC_REG_INT_MASK); atomic_set(&host->stuck_timeout, 0); host->status_reg = stat; @@ -671,10 +669,10 @@ static void imxmci_tasklet_fnc(unsigned long data) unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */ int timeout = 0; - if(atomic_read(&host->stuck_timeout) > 4) { + if (atomic_read(&host->stuck_timeout) > 4) { char *what; timeout = 1; - stat = MMC_STATUS; + stat = readw(host->base + MMC_REG_STATUS); host->status_reg = stat; if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) @@ -683,29 +681,37 @@ static void imxmci_tasklet_fnc(unsigned long data) what = "RESP"; else if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) - if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events)) + if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events)) what = "DATA"; else what = "DMA"; else what = "???"; - dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n", - what, stat, MMC_INT_MASK); - dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n", - MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma)); + dev_err(mmc_dev(host->mmc), + "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n", + what, stat, + readw(host->base + MMC_REG_INT_MASK)); + dev_err(mmc_dev(host->mmc), + "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n", + readw(host->base + MMC_REG_CMD_DAT_CONT), + readw(host->base + MMC_REG_BLK_LEN), + readw(host->base + MMC_REG_NOB), + CCR(host->dma)); dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n", - host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1<<host->actual_bus_width, host->dma_size); + host->cmd ? host->cmd->opcode : 0, + host->prev_cmd_code, + 1 << host->actual_bus_width, host->dma_size); } - if(!host->present || timeout) + if (!host->present || timeout) host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ | - STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR; + STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR; - if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) { + if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) { clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events); - stat = MMC_STATUS; + stat = readw(host->base + MMC_REG_STATUS); /* * This is not required in theory, but there is chance to miss some flag * which clears automatically by mask write, FreeScale original code keeps @@ -713,63 +719,62 @@ static void imxmci_tasklet_fnc(unsigned long data) */ stat |= host->status_reg; - if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) + if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) stat &= ~STATUS_CRC_READ_ERR; - if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { + if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { imxmci_busy_wait_for_status(host, &stat, - STATUS_END_CMD_RESP | STATUS_ERR_MASK, - 20, "imxmci_tasklet_fnc resp (ERRATUM #4)"); + STATUS_END_CMD_RESP | STATUS_ERR_MASK, + 20, "imxmci_tasklet_fnc resp (ERRATUM #4)"); } - if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) { - if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) + if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) { + if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) imxmci_cmd_done(host, stat); - if(host->data && (stat & STATUS_ERR_MASK)) + if (host->data && (stat & STATUS_ERR_MASK)) imxmci_data_done(host, stat); } - if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) { - stat |= MMC_STATUS; - if(imxmci_cpu_driven_data(host, &stat)){ - if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) + if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) { + stat |= readw(host->base + MMC_REG_STATUS); + if (imxmci_cpu_driven_data(host, &stat)) { + if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) imxmci_cmd_done(host, stat); atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m, - &host->pending_events); + &host->pending_events); imxmci_data_done(host, stat); } } } - if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) && - !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { + if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) && + !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { - stat = MMC_STATUS; + stat = readw(host->base + MMC_REG_STATUS); /* Same as above */ stat |= host->status_reg; - if(host->dma_dir == DMA_TO_DEVICE) { + if (host->dma_dir == DMA_TO_DEVICE) data_dir_mask = STATUS_WRITE_OP_DONE; - } else { + else data_dir_mask = STATUS_DATA_TRANS_DONE; - } - if(stat & data_dir_mask) { + if (stat & data_dir_mask) { clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events); imxmci_data_done(host, stat); } } - if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) { + if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) { - if(host->cmd) + if (host->cmd) imxmci_cmd_done(host, STATUS_TIME_OUT_RESP); - if(host->data) + if (host->data) imxmci_data_done(host, STATUS_TIME_OUT_READ | STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR); - if(host->req) + if (host->req) imxmci_finish_request(host, host->req); mmc_detect_change(host->mmc, msecs_to_jiffies(100)); @@ -796,9 +801,8 @@ static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req) if (req->data->flags & MMC_DATA_WRITE) cmdat |= CMD_DAT_CONT_WRITE; - if (req->data->flags & MMC_DATA_STREAM) { + if (req->data->flags & MMC_DATA_STREAM) cmdat |= CMD_DAT_CONT_STREAM_BLOCK; - } } imxmci_start_cmd(host, req->cmd, cmdat); @@ -811,36 +815,37 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) struct imxmci_host *host = mmc_priv(mmc); int prescaler; - if( ios->bus_width==MMC_BUS_WIDTH_4 ) { + if (ios->bus_width == MMC_BUS_WIDTH_4) { host->actual_bus_width = MMC_BUS_WIDTH_4; imx_gpio_mode(PB11_PF_SD_DAT3); - }else{ + } else { host->actual_bus_width = MMC_BUS_WIDTH_1; imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11); } - if ( host->power_mode != ios->power_mode ) { + if (host->power_mode != ios->power_mode) { switch (ios->power_mode) { case MMC_POWER_OFF: - break; + break; case MMC_POWER_UP: set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); - break; + break; case MMC_POWER_ON: - break; + break; } host->power_mode = ios->power_mode; } - if ( ios->clock ) { + if (ios->clock) { unsigned int clk; + u16 reg; /* The prescaler is 5 for PERCLK2 equal to 96MHz * then 96MHz / 5 = 19.2 MHz */ clk = clk_get_rate(host->clk); - prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE; - switch(prescaler) { + prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE; + switch (prescaler) { case 0: case 1: prescaler = 0; break; @@ -858,24 +863,29 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n", clk, prescaler); - for(clk=0; clk<8; clk++) { + for (clk = 0; clk < 8; clk++) { int x; - x = CLK_RATE / (1<<clk); - if( x <= ios->clock) + x = CLK_RATE / (1 << clk); + if (x <= ios->clock) break; } - MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */ + /* enable controller */ + reg = readw(host->base + MMC_REG_STR_STP_CLK); + writew(reg | STR_STP_CLK_ENABLE, + host->base + MMC_REG_STR_STP_CLK); imxmci_stop_clock(host); - MMC_CLK_RATE = (prescaler<<3) | clk; + writew((prescaler << 3) | clk, host->base + MMC_REG_CLK_RATE); /* * Under my understanding, clock should not be started there, because it would * initiate SDHC sequencer and send last or random command into card */ - /*imxmci_start_clock(host);*/ + /* imxmci_start_clock(host); */ - dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE); + dev_dbg(mmc_dev(host->mmc), + "MMC_CLK_RATE: 0x%08x\n", + readw(host->base + MMC_REG_CLK_RATE)); } else { imxmci_stop_clock(host); } @@ -915,10 +925,10 @@ static void imxmci_check_status(unsigned long data) tasklet_schedule(&host->tasklet); } - if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) || - test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { + if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) || + test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { atomic_inc(&host->stuck_timeout); - if(atomic_read(&host->stuck_timeout) > 4) + if (atomic_read(&host->stuck_timeout) > 4) tasklet_schedule(&host->tasklet); } else { atomic_set(&host->stuck_timeout, 0); @@ -934,6 +944,7 @@ static int imxmci_probe(struct platform_device *pdev) struct imxmci_host *host = NULL; struct resource *r; int ret = 0, irq; + u16 rev_no; printk(KERN_INFO "i.MX mmc driver\n"); @@ -942,7 +953,8 @@ static int imxmci_probe(struct platform_device *pdev) if (!r || irq < 0) return -ENXIO; - if (!request_mem_region(r->start, 0x100, pdev->name)) + r = request_mem_region(r->start, resource_size(r), pdev->name); + if (!r) return -EBUSY; mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev); @@ -966,6 +978,12 @@ static int imxmci_probe(struct platform_device *pdev) mmc->max_blk_count = 65535; host = mmc_priv(mmc); + host->base = ioremap(r->start, resource_size(r)); + if (!host->base) { + ret = -ENOMEM; + goto out; + } + host->mmc = mmc; host->dma_allocated = 0; host->pdata = pdev->dev.platform_data; @@ -993,18 +1011,20 @@ static int imxmci_probe(struct platform_device *pdev) imx_gpio_mode(PB12_PF_SD_CLK); imx_gpio_mode(PB13_PF_SD_CMD); - imxmci_softreset(); + imxmci_softreset(host); - if ( MMC_REV_NO != 0x390 ) { + rev_no = readw(host->base + MMC_REG_REV_NO); + if (rev_no != 0x390) { dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", - MMC_REV_NO); + readw(host->base + MMC_REG_REV_NO)); goto out; } - MMC_READ_TO = 0x2db4; /* recommended in data sheet */ + /* recommended in data sheet */ + writew(0x2db4, host->base + MMC_REG_READ_TO); host->imask = IMXMCI_INT_MASK_DEFAULT; - MMC_INT_MASK = host->imask; + writew(host->imask, host->base + MMC_REG_INT_MASK); host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW); if(host->dma < 0) { @@ -1012,7 +1032,7 @@ static int imxmci_probe(struct platform_device *pdev) ret = -EBUSY; goto out; } - host->dma_allocated=1; + host->dma_allocated = 1; imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host); tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host); @@ -1032,7 +1052,7 @@ static int imxmci_probe(struct platform_device *pdev) host->timer.data = (unsigned long)host; host->timer.function = imxmci_check_status; add_timer(&host->timer); - mod_timer(&host->timer, jiffies + (HZ>>1)); + mod_timer(&host->timer, jiffies + (HZ >> 1)); platform_set_drvdata(pdev, mmc); @@ -1042,18 +1062,20 @@ static int imxmci_probe(struct platform_device *pdev) out: if (host) { - if(host->dma_allocated){ + if (host->dma_allocated) { imx_dma_free(host->dma); - host->dma_allocated=0; + host->dma_allocated = 0; } if (host->clk) { clk_disable(host->clk); clk_put(host->clk); } + if (host->base) + iounmap(host->base); } if (mmc) mmc_free_host(mmc); - release_mem_region(r->start, 0x100); + release_mem_region(r->start, resource_size(r)); return ret; } @@ -1072,9 +1094,10 @@ static int imxmci_remove(struct platform_device *pdev) mmc_remove_host(mmc); free_irq(host->irq, host); - if(host->dma_allocated){ + iounmap(host->base); + if (host->dma_allocated) { imx_dma_free(host->dma); - host->dma_allocated=0; + host->dma_allocated = 0; } tasklet_kill(&host->tasklet); @@ -1082,7 +1105,7 @@ static int imxmci_remove(struct platform_device *pdev) clk_disable(host->clk); clk_put(host->clk); - release_mem_region(host->res->start, 0x100); + release_mem_region(host->res->start, resource_size(host->res)); mmc_free_host(mmc); } @@ -1109,7 +1132,7 @@ static int imxmci_resume(struct platform_device *dev) if (mmc) { host = mmc_priv(mmc); - if(host) + if (host) set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); ret = mmc_resume_host(mmc); } diff --git a/drivers/mmc/host/imxmmc.h b/drivers/mmc/host/imxmmc.h index e5339e3..09d5d4e 100644 --- a/drivers/mmc/host/imxmmc.h +++ b/drivers/mmc/host/imxmmc.h @@ -1,24 +1,21 @@ +#define MMC_REG_STR_STP_CLK 0x00 +#define MMC_REG_STATUS 0x04 +#define MMC_REG_CLK_RATE 0x08 +#define MMC_REG_CMD_DAT_CONT 0x0C +#define MMC_REG_RES_TO 0x10 +#define MMC_REG_READ_TO 0x14 +#define MMC_REG_BLK_LEN 0x18 +#define MMC_REG_NOB 0x1C +#define MMC_REG_REV_NO 0x20 +#define MMC_REG_INT_MASK 0x24 +#define MMC_REG_CMD 0x28 +#define MMC_REG_ARGH 0x2C +#define MMC_REG_ARGL 0x30 +#define MMC_REG_RES_FIFO 0x34 +#define MMC_REG_BUFFER_ACCESS 0x38 -# define __REG16(x) (*((volatile u16 *)IO_ADDRESS(x))) - -#define MMC_STR_STP_CLK __REG16(IMX_MMC_BASE + 0x00) -#define MMC_STATUS __REG16(IMX_MMC_BASE + 0x04) -#define MMC_CLK_RATE __REG16(IMX_MMC_BASE + 0x08) -#define MMC_CMD_DAT_CONT __REG16(IMX_MMC_BASE + 0x0C) -#define MMC_RES_TO __REG16(IMX_MMC_BASE + 0x10) -#define MMC_READ_TO __REG16(IMX_MMC_BASE + 0x14) -#define MMC_BLK_LEN __REG16(IMX_MMC_BASE + 0x18) -#define MMC_NOB __REG16(IMX_MMC_BASE + 0x1C) -#define MMC_REV_NO __REG16(IMX_MMC_BASE + 0x20) -#define MMC_INT_MASK __REG16(IMX_MMC_BASE + 0x24) -#define MMC_CMD __REG16(IMX_MMC_BASE + 0x28) -#define MMC_ARGH __REG16(IMX_MMC_BASE + 0x2C) -#define MMC_ARGL __REG16(IMX_MMC_BASE + 0x30) -#define MMC_RES_FIFO __REG16(IMX_MMC_BASE + 0x34) -#define MMC_BUFFER_ACCESS __REG16(IMX_MMC_BASE + 0x38) -#define MMC_BUFFER_ACCESS_OFS 0x38 - - +#define STR_STP_CLK_IPG_CLK_GATE_DIS (1<<15) +#define STR_STP_CLK_IPG_PERCLK_GATE_DIS (1<<14) #define STR_STP_CLK_ENDIAN (1<<5) #define STR_STP_CLK_RESET (1<<3) #define STR_STP_CLK_ENABLE (1<<2) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 2fadf32..1bcbdd6 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -500,7 +500,7 @@ static int mmci_probe(struct amba_device *dev, void *id) } host = mmc_priv(mmc); - host->clk = clk_get(&dev->dev, "MCLK"); + host->clk = clk_get(&dev->dev, NULL); if (IS_ERR(host->clk)) { ret = PTR_ERR(host->clk); host->clk = NULL; diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c index 1b9fc3c..67d7b7f 100644 --- a/drivers/mmc/host/omap.c +++ b/drivers/mmc/host/omap.c @@ -1015,7 +1015,7 @@ static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data } if (is_read) { - if (host->id == 1) { + if (host->id == 0) { sync_dev = OMAP_DMA_MMC_RX; dma_dev_name = "MMC1 read"; } else { @@ -1023,7 +1023,7 @@ static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data dma_dev_name = "MMC2 read"; } } else { - if (host->id == 1) { + if (host->id == 0) { sync_dev = OMAP_DMA_MMC_TX; dma_dev_name = "MMC1 write"; } else { @@ -1317,7 +1317,7 @@ static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id) host->slots[id] = slot; mmc->caps = 0; - if (host->pdata->conf.wire4) + if (host->pdata->slots[id].wires >= 4) mmc->caps |= MMC_CAP_4_BIT_DATA; mmc->ops = &mmc_omap_ops; @@ -1451,6 +1451,7 @@ static int __init mmc_omap_probe(struct platform_device *pdev) host->irq = irq; host->use_dma = 1; + host->dev->dma_mask = &pdata->dma_mask; host->dma_ch = -1; host->irq = irq; diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c index ebfaa99..f88cc74 100644 --- a/drivers/mmc/host/pxamci.c +++ b/drivers/mmc/host/pxamci.c @@ -26,11 +26,12 @@ #include <linux/clk.h> #include <linux/err.h> #include <linux/mmc/host.h> +#include <linux/io.h> -#include <asm/dma.h> -#include <asm/io.h> #include <asm/sizes.h> +#include <mach/dma.h> +#include <mach/hardware.h> #include <mach/pxa-regs.h> #include <mach/mmc.h> @@ -533,7 +534,7 @@ static int pxamci_probe(struct platform_device *pdev) host->pdata = pdev->dev.platform_data; host->clkrt = CLKRT_OFF; - host->clk = clk_get(&pdev->dev, "MMCCLK"); + host->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(host->clk)) { ret = PTR_ERR(host->clk); host->clk = NULL; diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c index 3b2085b..fcc98a4 100644 --- a/drivers/mmc/host/s3cmci.c +++ b/drivers/mmc/host/s3cmci.c @@ -25,7 +25,7 @@ #include <mach/regs-sdi.h> #include <mach/regs-gpio.h> -#include <asm/plat-s3c24xx/mci.h> +#include <plat/mci.h> #include "s3cmci.h" diff --git a/drivers/mtd/maps/dc21285.c b/drivers/mtd/maps/dc21285.c index 3aa018c..42969fe 100644 --- a/drivers/mtd/maps/dc21285.c +++ b/drivers/mtd/maps/dc21285.c @@ -32,16 +32,15 @@ static struct mtd_info *dc21285_mtd; */ static void nw_en_write(void) { - extern spinlock_t gpio_lock; unsigned long flags; /* * we want to write a bit pattern XXX1 to Xilinx to enable * the write gate, which will be open for about the next 2ms. */ - spin_lock_irqsave(&gpio_lock, flags); - cpld_modify(1, 1); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE); + spin_unlock_irqrestore(&nw_gpio_lock, flags); /* * let the ISA bus to catch on... diff --git a/drivers/mtd/maps/ixp2000.c b/drivers/mtd/maps/ixp2000.c index dcdb1f1..3ea1de9 100644 --- a/drivers/mtd/maps/ixp2000.c +++ b/drivers/mtd/maps/ixp2000.c @@ -170,7 +170,7 @@ static int ixp2000_flash_probe(struct platform_device *dev) err = -ENOMEM; goto Error; } - memzero(info, sizeof(struct ixp2000_flash_info)); + memset(info, 0, sizeof(struct ixp2000_flash_info)); platform_set_drvdata(dev, info); diff --git a/drivers/mtd/maps/ixp4xx.c b/drivers/mtd/maps/ixp4xx.c index 9c7a5fb..16555cb 100644 --- a/drivers/mtd/maps/ixp4xx.c +++ b/drivers/mtd/maps/ixp4xx.c @@ -201,7 +201,7 @@ static int ixp4xx_flash_probe(struct platform_device *dev) err = -ENOMEM; goto Error; } - memzero(info, sizeof(struct ixp4xx_flash_info)); + memset(info, 0, sizeof(struct ixp4xx_flash_info)); platform_set_drvdata(dev, info); diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 1c2e945..f8ae040 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -408,7 +408,7 @@ config MTD_NAND_FSL_UPM config MTD_NAND_MXC tristate "MXC NAND support" - depends on ARCH_MX2 + depends on ARCH_MX2 || ARCH_MX3 help This enables the driver for the NAND flash controller on the MXC processors. diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 15f0a26..fc41444 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -20,8 +20,8 @@ #include <linux/mtd/partitions.h> #include <linux/io.h> #include <linux/irq.h> -#include <asm/dma.h> +#include <mach/dma.h> #include <mach/pxa-regs.h> #include <mach/pxa3xx_nand.h> @@ -1080,7 +1080,7 @@ static int pxa3xx_nand_probe(struct platform_device *pdev) this = &info->nand_chip; mtd->priv = info; - info->clk = clk_get(&pdev->dev, "NANDCLK"); + info->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(info->clk)) { dev_err(&pdev->dev, "failed to get nand clock\n"); ret = PTR_ERR(info->clk); diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 556139e..8e375d5 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -45,8 +45,8 @@ #include <asm/io.h> -#include <asm/plat-s3c/regs-nand.h> -#include <asm/plat-s3c/nand.h> +#include <plat/regs-nand.h> +#include <plat/nand.h> #ifdef CONFIG_MTD_NAND_S3C2410_HWECC static int hardware_ecc = 1; @@ -818,7 +818,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev, goto exit_error; } - memzero(info, sizeof(*info)); + memset(info, 0, sizeof(*info)); platform_set_drvdata(pdev, info); spin_lock_init(&info->controller.lock); @@ -883,7 +883,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev, goto exit_error; } - memzero(info->mtds, size); + memset(info->mtds, 0, size); /* initialise all possible chips */ diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c index a7e4d98..d1e0b8e 100644 --- a/drivers/mtd/onenand/omap2.c +++ b/drivers/mtd/onenand/omap2.c @@ -149,7 +149,7 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state) INIT_COMPLETION(c->irq_done); if (c->gpio_irq) { - result = omap_get_gpio_datain(c->gpio_irq); + result = gpio_get_value(c->gpio_irq); if (result == -1) { ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); intr = read_reg(c, ONENAND_REG_INTERRUPT); @@ -634,9 +634,9 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev) "OneNAND\n", c->gpio_irq); goto err_iounmap; } - omap_set_gpio_direction(c->gpio_irq, 1); + gpio_direction_input(c->gpio_irq); - if ((r = request_irq(OMAP_GPIO_IRQ(c->gpio_irq), + if ((r = request_irq(gpio_to_irq(c->gpio_irq), omap2_onenand_interrupt, IRQF_TRIGGER_RISING, pdev->dev.driver->name, c)) < 0) goto err_release_gpio; @@ -723,7 +723,7 @@ err_release_dma: if (c->dma_channel != -1) omap_free_dma(c->dma_channel); if (c->gpio_irq) - free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c); + free_irq(gpio_to_irq(c->gpio_irq), c); err_release_gpio: if (c->gpio_irq) omap_free_gpio(c->gpio_irq); @@ -760,7 +760,7 @@ static int __devexit omap2_onenand_remove(struct platform_device *pdev) omap2_onenand_shutdown(pdev); platform_set_drvdata(pdev, NULL); if (c->gpio_irq) { - free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c); + free_irq(gpio_to_irq(c->gpio_irq), c); omap_free_gpio(c->gpio_irq); } iounmap(c->onenand.base); diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c index d548a45..ff64976 100644 --- a/drivers/net/cs89x0.c +++ b/drivers/net/cs89x0.c @@ -170,11 +170,7 @@ static char version[] __initdata = /* The cs8900 has 4 IRQ pins, software selectable. cs8900_irq_map maps them to system IRQ numbers. This mapping is card specific and is set to the configuration of the Cirrus Eval board for this chip. */ -#ifdef CONFIG_ARCH_CLPS7500 -static unsigned int netcard_portlist[] __used __initdata = - { 0x80090303, 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0}; -static unsigned int cs8900_irq_map[] = {12,0,0,0}; -#elif defined(CONFIG_SH_HICOSH4) +#if defined(CONFIG_SH_HICOSH4) static unsigned int netcard_portlist[] __used __initdata = { 0x0300, 0}; static unsigned int cs8900_irq_map[] = {1,0,0,0}; diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c index a0ee053..004a9aa 100644 --- a/drivers/net/irda/pxaficp_ir.c +++ b/drivers/net/irda/pxaficp_ir.c @@ -22,9 +22,53 @@ #include <net/irda/wrapper.h> #include <net/irda/irda_device.h> -#include <asm/dma.h> +#include <mach/dma.h> #include <mach/irda.h> +#include <mach/hardware.h> #include <mach/pxa-regs.h> +#include <mach/regs-uart.h> + +#define FICP __REG(0x40800000) /* Start of FICP area */ +#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ +#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ +#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ +#define ICDR __REG(0x4080000c) /* ICP Data Register */ +#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ +#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ + +#define ICCR0_AME (1 << 7) /* Address match enable */ +#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ +#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ +#define ICCR0_RXE (1 << 4) /* Receive enable */ +#define ICCR0_TXE (1 << 3) /* Transmit enable */ +#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ +#define ICCR0_LBM (1 << 1) /* Loopback mode */ +#define ICCR0_ITR (1 << 0) /* IrDA transmission */ + +#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ +#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ +#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ +#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ +#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ +#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ + +#ifdef CONFIG_PXA27x +#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ +#endif +#define ICSR0_FRE (1 << 5) /* Framing error */ +#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ +#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ +#define ICSR0_RAB (1 << 2) /* Receiver abort */ +#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ +#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ + +#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ +#define ICSR1_CRE (1 << 5) /* CRC error */ +#define ICSR1_EOF (1 << 4) /* End of frame */ +#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ +#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ +#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ +#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ #define IrSR_RXPL_NEG_IS_ZERO (1<<4) #define IrSR_RXPL_POS_IS_ZERO 0x0 diff --git a/drivers/net/irda/sa1100_ir.c b/drivers/net/irda/sa1100_ir.c index ccde5829..d302bcf 100644 --- a/drivers/net/irda/sa1100_ir.c +++ b/drivers/net/irda/sa1100_ir.c @@ -36,7 +36,7 @@ #include <net/irda/irda_device.h> #include <asm/irq.h> -#include <asm/dma.h> +#include <mach/dma.h> #include <mach/hardware.h> #include <asm/mach/irda.h> diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h index cc7d85b..870b4c3 100644 --- a/drivers/net/smc911x.h +++ b/drivers/net/smc911x.h @@ -200,6 +200,9 @@ static inline void SMC_outsl(struct smc911x_local *lp, int reg, #ifdef SMC_USE_PXA_DMA + +#include <mach/dma.h> + /* * Define the request and free functions * These are unfortunately architecture specific as no generic allocation diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h index 3e7c6a3..c4ccd12 100644 --- a/drivers/net/smc91x.h +++ b/drivers/net/smc91x.h @@ -493,7 +493,8 @@ struct smc_local { * as RX which can overrun memory and lose packets. */ #include <linux/dma-mapping.h> -#include <asm/dma.h> +#include <mach/dma.h> +#include <mach/hardware.h> #include <mach/pxa-regs.h> #ifdef SMC_insl diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index 2229044..2764735 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -217,7 +217,7 @@ config PCMCIA_PXA2XX depends on ARM && ARCH_PXA && PCMCIA depends on (ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL \ || MACH_ARMCORE || ARCH_PXA_PALM || TRIZEPS_PCMCIA \ - || ARCH_VIPER) + || ARCH_VIPER || ARCH_PXA_ESERIES) help Say Y here to include support for the PXA2xx PCMCIA controller diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index 238629a..bbac463 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -72,5 +72,6 @@ pxa2xx-obj-$(CONFIG_ARCH_VIPER) += pxa2xx_viper.o pxa2xx-obj-$(CONFIG_TRIZEPS_PCMCIA) += pxa2xx_trizeps4.o pxa2xx-obj-$(CONFIG_MACH_PALMTX) += pxa2xx_palmtx.o pxa2xx-obj-$(CONFIG_MACH_PALMLD) += pxa2xx_palmld.o +pxa2xx-obj-$(CONFIG_MACH_E740) += pxa2xx_e740.o obj-$(CONFIG_PCMCIA_PXA2XX) += pxa2xx_core.o $(pxa2xx-obj-y) diff --git a/drivers/pcmcia/pxa2xx_e740.c b/drivers/pcmcia/pxa2xx_e740.c new file mode 100644 index 0000000..f663a01 --- /dev/null +++ b/drivers/pcmcia/pxa2xx_e740.c @@ -0,0 +1,176 @@ +/* + * Toshiba e740 PCMCIA specific routines. + * + * (c) 2004 Ian Molton <spyro@f2s.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> + +#include <mach/hardware.h> +#include <mach/pxa-regs.h> +#include <mach/eseries-gpio.h> + +#include <asm/irq.h> +#include <asm/mach-types.h> + +#include "soc_common.h" + +static struct pcmcia_irqs cd_irqs[] = { + { + .sock = 0, + .irq = IRQ_GPIO(GPIO_E740_PCMCIA_CD0), + .str = "CF card detect" + }, + { + .sock = 1, + .irq = IRQ_GPIO(GPIO_E740_PCMCIA_CD1), + .str = "Wifi switch" + }, +}; + +static int e740_pcmcia_hw_init(struct soc_pcmcia_socket *skt) +{ + skt->irq = skt->nr == 0 ? IRQ_GPIO(GPIO_E740_PCMCIA_RDY0) : + IRQ_GPIO(GPIO_E740_PCMCIA_RDY1); + + return soc_pcmcia_request_irqs(skt, &cd_irqs[skt->nr], 1); +} + +/* + * Release all resources. + */ +static void e740_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) +{ + soc_pcmcia_free_irqs(skt, &cd_irqs[skt->nr], 1); +} + +static void e740_pcmcia_socket_state(struct soc_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + if (skt->nr == 0) { + state->detect = gpio_get_value(GPIO_E740_PCMCIA_CD0) ? 0 : 1; + state->ready = gpio_get_value(GPIO_E740_PCMCIA_RDY0) ? 1 : 0; + } else { + state->detect = gpio_get_value(GPIO_E740_PCMCIA_CD1) ? 0 : 1; + state->ready = gpio_get_value(GPIO_E740_PCMCIA_RDY1) ? 1 : 0; + } + + state->vs_3v = 1; + state->bvd1 = 1; + state->bvd2 = 1; + state->wrprot = 0; + state->vs_Xv = 0; +} + +static int e740_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, + const socket_state_t *state) +{ + if (state->flags & SS_RESET) { + if (skt->nr == 0) + gpio_set_value(GPIO_E740_PCMCIA_RST0, 1); + else + gpio_set_value(GPIO_E740_PCMCIA_RST1, 1); + } else { + if (skt->nr == 0) + gpio_set_value(GPIO_E740_PCMCIA_RST0, 0); + else + gpio_set_value(GPIO_E740_PCMCIA_RST1, 0); + } + + switch (state->Vcc) { + case 0: /* Socket off */ + if (skt->nr == 0) + gpio_set_value(GPIO_E740_PCMCIA_PWR0, 0); + else + gpio_set_value(GPIO_E740_PCMCIA_PWR1, 1); + break; + case 50: + case 33: /* socket on */ + if (skt->nr == 0) + gpio_set_value(GPIO_E740_PCMCIA_PWR0, 1); + else + gpio_set_value(GPIO_E740_PCMCIA_PWR1, 0); + break; + default: + printk(KERN_ERR "e740_cs: Unsupported Vcc: %d\n", state->Vcc); + } + + return 0; +} + +/* + * Enable card status IRQs on (re-)initialisation. This can + * be called at initialisation, power management event, or + * pcmcia event. + */ +static void e740_pcmcia_socket_init(struct soc_pcmcia_socket *skt) +{ + soc_pcmcia_enable_irqs(skt, cd_irqs, ARRAY_SIZE(cd_irqs)); +} + +/* + * Disable card status IRQs on suspend. + */ +static void e740_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) +{ + soc_pcmcia_disable_irqs(skt, cd_irqs, ARRAY_SIZE(cd_irqs)); +} + +static struct pcmcia_low_level e740_pcmcia_ops = { + .owner = THIS_MODULE, + .hw_init = e740_pcmcia_hw_init, + .hw_shutdown = e740_pcmcia_hw_shutdown, + .socket_state = e740_pcmcia_socket_state, + .configure_socket = e740_pcmcia_configure_socket, + .socket_init = e740_pcmcia_socket_init, + .socket_suspend = e740_pcmcia_socket_suspend, + .nr = 2, +}; + +static struct platform_device *e740_pcmcia_device; + +static int __init e740_pcmcia_init(void) +{ + int ret; + + if (!machine_is_e740()) + return -ENODEV; + + e740_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); + if (!e740_pcmcia_device) + return -ENOMEM; + + ret = platform_device_add_data(e740_pcmcia_device, &e740_pcmcia_ops, + sizeof(e740_pcmcia_ops)); + + if (!ret) + ret = platform_device_add(e740_pcmcia_device); + + if (ret) + platform_device_put(e740_pcmcia_device); + + return ret; +} + +static void __exit e740_pcmcia_exit(void) +{ + platform_device_unregister(e740_pcmcia_device); +} + +module_init(e740_pcmcia_init); +module_exit(e740_pcmcia_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Ian Molton <spyro@f2s.com>"); +MODULE_ALIAS("platform:pxa2xx-pcmcia"); +MODULE_DESCRIPTION("e740 PCMCIA platform support"); diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c index 2133f37..d5e4e63 100644 --- a/drivers/rtc/rtc-at91sam9.c +++ b/drivers/rtc/rtc-at91sam9.c @@ -21,6 +21,7 @@ #include <mach/board.h> #include <mach/at91_rtt.h> +#include <mach/cpu.h> /* diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c index f59277b..7a568be 100644 --- a/drivers/rtc/rtc-s3c.c +++ b/drivers/rtc/rtc-s3c.c @@ -26,7 +26,7 @@ #include <asm/uaccess.h> #include <asm/io.h> #include <asm/irq.h> -#include <asm/plat-s3c/regs-rtc.h> +#include <plat/regs-rtc.h> /* I have yet to find an S3C implementation with more than one * of these rtc blocks in */ diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c index 66a9bb8..d26a5f8 100644 --- a/drivers/rtc/rtc-sa1100.c +++ b/drivers/rtc/rtc-sa1100.c @@ -38,11 +38,11 @@ #include <mach/pxa-regs.h> #endif -#define TIMER_FREQ CLOCK_TICK_RATE #define RTC_DEF_DIVIDER 32768 - 1 #define RTC_DEF_TRIM 0 static unsigned long rtc_freq = 1024; +static unsigned long timer_freq; static struct rtc_time rtc_alarm; static DEFINE_SPINLOCK(sa1100_rtc_lock); @@ -157,7 +157,7 @@ static irqreturn_t timer1_interrupt(int irq, void *dev_id) rtc_update_irq(rtc, rtc_timer1_count, RTC_PF | RTC_IRQF); if (rtc_timer1_count == 1) - rtc_timer1_count = (rtc_freq * ((1<<30)/(TIMER_FREQ>>2))); + rtc_timer1_count = (rtc_freq * ((1 << 30) / (timer_freq >> 2))); return IRQ_HANDLED; } @@ -166,7 +166,7 @@ static int sa1100_rtc_read_callback(struct device *dev, int data) { if (data & RTC_PF) { /* interpolate missed periods and set match for the next */ - unsigned long period = TIMER_FREQ/rtc_freq; + unsigned long period = timer_freq / rtc_freq; unsigned long oscr = OSCR; unsigned long osmr1 = OSMR1; unsigned long missed = (oscr - osmr1)/period; @@ -263,7 +263,7 @@ static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd, return 0; case RTC_PIE_ON: spin_lock_irq(&sa1100_rtc_lock); - OSMR1 = TIMER_FREQ/rtc_freq + OSCR; + OSMR1 = timer_freq / rtc_freq + OSCR; OIER |= OIER_E1; rtc_timer1_count = 1; spin_unlock_irq(&sa1100_rtc_lock); @@ -271,7 +271,7 @@ static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd, case RTC_IRQP_READ: return put_user(rtc_freq, (unsigned long *)arg); case RTC_IRQP_SET: - if (arg < 1 || arg > TIMER_FREQ) + if (arg < 1 || arg > timer_freq) return -EINVAL; rtc_freq = arg; return 0; @@ -352,6 +352,8 @@ static int sa1100_rtc_probe(struct platform_device *pdev) { struct rtc_device *rtc; + timer_freq = get_clock_tick_rate(); + /* * According to the manual we should be able to let RTTR be zero * and then a default diviser for a 32.768KHz clock is used. diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 579d63a..b695ab3 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -447,7 +447,7 @@ config SERIAL_CLPS711X_CONSOLE config SERIAL_SAMSUNG tristate "Samsung SoC serial support" - depends on ARM && PLAT_S3C24XX + depends on ARM && PLAT_S3C select SERIAL_CORE help Support for the on-chip UARTs on the Samsung S3C24XX series CPUs, @@ -455,6 +455,16 @@ config SERIAL_SAMSUNG provide all of these ports, depending on how the serial port pins are configured. +config SERIAL_SAMSUNG_UARTS + int + depends on SERIAL_SAMSUNG + default 2 if ARCH_S3C2400 + default 4 if ARCH_S3C64XX || CPU_S3C2443 + default 3 + help + Select the number of available UART ports for the Samsung S3C + serial driver + config SERIAL_SAMSUNG_DEBUG bool "Samsung SoC serial debug" depends on SERIAL_SAMSUNG && DEBUG_LL @@ -508,7 +518,20 @@ config SERIAL_S3C2440 help Serial port support for the Samsung S3C2440 and S3C2442 SoC +config SERIAL_S3C24A0 + tristate "Samsung S3C24A0 Serial port support" + depends on SERIAL_SAMSUNG && CPU_S3C24A0 + default y if CPU_S3C24A0 + help + Serial port support for the Samsung S3C24A0 SoC +config SERIAL_S3C6400 + tristate "Samsung S3C6400/S3C6410 Serial port support" + depends on SERIAL_SAMSUNG && (CPU_S3C600 || CPU_S3C6410) + default y + help + Serial port support for the Samsung S3C6400 and S3C6410 + SoCs config SERIAL_DZ bool "DECstation DZ serial driver" diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 0c17c8d..dfe775a 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -41,6 +41,8 @@ obj-$(CONFIG_SERIAL_S3C2400) += s3c2400.o obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o +obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o +obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o obj-$(CONFIG_SERIAL_MUX) += mux.o obj-$(CONFIG_SERIAL_68328) += 68328serial.o diff --git a/drivers/serial/amba-pl010.c b/drivers/serial/amba-pl010.c index 7156268..e3a5ad5 100644 --- a/drivers/serial/amba-pl010.c +++ b/drivers/serial/amba-pl010.c @@ -692,7 +692,7 @@ static int pl010_probe(struct amba_device *dev, void *id) goto free; } - uap->clk = clk_get(&dev->dev, "UARTCLK"); + uap->clk = clk_get(&dev->dev, NULL); if (IS_ERR(uap->clk)) { ret = PTR_ERR(uap->clk); goto unmap; diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c index b718004..8b2b970 100644 --- a/drivers/serial/amba-pl011.c +++ b/drivers/serial/amba-pl011.c @@ -756,7 +756,7 @@ static int pl011_probe(struct amba_device *dev, void *id) goto free; } - uap->clk = clk_get(&dev->dev, "UARTCLK"); + uap->clk = clk_get(&dev->dev, NULL); if (IS_ERR(uap->clk)) { ret = PTR_ERR(uap->clk); goto unmap; diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c index 3f90f1b..a509546 100644 --- a/drivers/serial/imx.c +++ b/drivers/serial/imx.c @@ -66,7 +66,7 @@ #define ONEMS 0xb0 /* One Millisecond register */ #define UTS 0xb4 /* UART Test Register */ #endif -#ifdef CONFIG_ARCH_IMX +#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1) #define BIPR1 0xb0 /* Incremental Preset Register 1 */ #define BIPR2 0xb4 /* Incremental Preset Register 2 */ #define BIPR3 0xb8 /* Incremental Preset Register 3 */ @@ -96,7 +96,7 @@ #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ #define UCR1_SNDBRK (1<<4) /* Send break */ #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ -#ifdef CONFIG_ARCH_IMX +#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1) #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ #endif #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 @@ -187,11 +187,11 @@ #define MAX_INTERNAL_IRQ IMX_IRQS #endif -#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 +#ifdef CONFIG_ARCH_MXC #define SERIAL_IMX_MAJOR 207 #define MINOR_START 16 #define DEV_NAME "ttymxc" -#define MAX_INTERNAL_IRQ MXC_MAX_INT_LINES +#define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS #endif /* diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c index abc00be..f6e3b86 100644 --- a/drivers/serial/pxa.c +++ b/drivers/serial/pxa.c @@ -48,6 +48,7 @@ #include <mach/hardware.h> #include <asm/irq.h> #include <mach/pxa-regs.h> +#include <mach/regs-uart.h> struct uart_pxa_port { @@ -766,7 +767,7 @@ static int serial_pxa_probe(struct platform_device *dev) if (!sport) return -ENOMEM; - sport->clk = clk_get(&dev->dev, "UARTCLK"); + sport->clk = clk_get(&dev->dev, NULL); if (IS_ERR(sport->clk)) { ret = PTR_ERR(sport->clk); goto err_free; diff --git a/drivers/serial/s3c24a0.c b/drivers/serial/s3c24a0.c new file mode 100644 index 0000000..ebf2fd3 --- /dev/null +++ b/drivers/serial/s3c24a0.c @@ -0,0 +1,118 @@ +/* linux/drivers/serial/s3c24a0.c + * + * Driver for Samsung S3C24A0 SoC onboard UARTs. + * + * Based on drivers/serial/s3c2410.c + * + * Author: Sandeep Patil <sandeep.patil@azingo.com> + * + * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/module.h> +#include <linux/ioport.h> +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/serial.h> +#include <linux/io.h> +#include <linux/irq.h> + +#include <mach/hardware.h> + +#include <plat/regs-serial.h> +#include <mach/regs-gpio.h> + +#include "samsung.h" + +static int s3c24a0_serial_setsource(struct uart_port *port, + struct s3c24xx_uart_clksrc *clk) +{ + unsigned long ucon = rd_regl(port, S3C2410_UCON); + + if (strcmp(clk->name, "uclk") == 0) + ucon |= S3C2410_UCON_UCLK; + else + ucon &= ~S3C2410_UCON_UCLK; + + wr_regl(port, S3C2410_UCON, ucon); + return 0; +} + +static int s3c24a0_serial_getsource(struct uart_port *port, + struct s3c24xx_uart_clksrc *clk) +{ + unsigned long ucon = rd_regl(port, S3C2410_UCON); + + clk->divisor = 1; + clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk"; + + return 0; +} + +static int s3c24a0_serial_resetport(struct uart_port *port, + struct s3c2410_uartcfg *cfg) +{ + dbg("s3c24a0_serial_resetport: port=%p (%08lx), cfg=%p\n", + port, port->mapbase, cfg); + + wr_regl(port, S3C2410_UCON, cfg->ucon); + wr_regl(port, S3C2410_ULCON, cfg->ulcon); + + /* reset both fifos */ + + wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); + wr_regl(port, S3C2410_UFCON, cfg->ufcon); + + return 0; +} + +static struct s3c24xx_uart_info s3c24a0_uart_inf = { + .name = "Samsung S3C24A0 UART", + .type = PORT_S3C2410, + .fifosize = 16, + .rx_fifomask = S3C24A0_UFSTAT_RXMASK, + .rx_fifoshift = S3C24A0_UFSTAT_RXSHIFT, + .rx_fifofull = S3C24A0_UFSTAT_RXFULL, + .tx_fifofull = S3C24A0_UFSTAT_TXFULL, + .tx_fifomask = S3C24A0_UFSTAT_TXMASK, + .tx_fifoshift = S3C24A0_UFSTAT_TXSHIFT, + .get_clksrc = s3c24a0_serial_getsource, + .set_clksrc = s3c24a0_serial_setsource, + .reset_port = s3c24a0_serial_resetport, +}; + +static int s3c24a0_serial_probe(struct platform_device *dev) +{ + return s3c24xx_serial_probe(dev, &s3c24a0_uart_inf); +} + +static struct platform_driver s3c24a0_serial_drv = { + .probe = s3c24a0_serial_probe, + .remove = s3c24xx_serial_remove, + .driver = { + .name = "s3c24a0-uart", + .owner = THIS_MODULE, + }, +}; + +s3c24xx_console_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf); + +static int __init s3c24a0_serial_init(void) +{ + return s3c24xx_serial_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf); +} + +static void __exit s3c24a0_serial_exit(void) +{ + platform_driver_unregister(&s3c24a0_serial_drv); +} + +module_init(s3c24a0_serial_init); +module_exit(s3c24a0_serial_exit); + diff --git a/drivers/serial/s3c6400.c b/drivers/serial/s3c6400.c new file mode 100644 index 0000000..06936d1 --- /dev/null +++ b/drivers/serial/s3c6400.c @@ -0,0 +1,151 @@ +/* linux/drivers/serial/s3c6400.c + * + * Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs. + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/module.h> +#include <linux/ioport.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/serial.h> + +#include <asm/irq.h> +#include <mach/hardware.h> + +#include <plat/regs-serial.h> + +#include "samsung.h" + +static int s3c6400_serial_setsource(struct uart_port *port, + struct s3c24xx_uart_clksrc *clk) +{ + unsigned long ucon = rd_regl(port, S3C2410_UCON); + + if (strcmp(clk->name, "uclk0") == 0) { + ucon &= ~S3C6400_UCON_CLKMASK; + ucon |= S3C6400_UCON_UCLK0; + } else if (strcmp(clk->name, "uclk1") == 0) + ucon |= S3C6400_UCON_UCLK1; + else if (strcmp(clk->name, "pclk") == 0) { + /* See notes about transitioning from UCLK to PCLK */ + ucon &= ~S3C6400_UCON_UCLK0; + } else { + printk(KERN_ERR "unknown clock source %s\n", clk->name); + return -EINVAL; + } + + wr_regl(port, S3C2410_UCON, ucon); + return 0; +} + + +static int s3c6400_serial_getsource(struct uart_port *port, + struct s3c24xx_uart_clksrc *clk) +{ + u32 ucon = rd_regl(port, S3C2410_UCON); + + clk->divisor = 1; + + switch (ucon & S3C6400_UCON_CLKMASK) { + case S3C6400_UCON_UCLK0: + clk->name = "uclk0"; + break; + + case S3C6400_UCON_UCLK1: + clk->name = "uclk1"; + break; + + case S3C6400_UCON_PCLK: + case S3C6400_UCON_PCLK2: + clk->name = "pclk"; + break; + } + + return 0; +} + +static int s3c6400_serial_resetport(struct uart_port *port, + struct s3c2410_uartcfg *cfg) +{ + unsigned long ucon = rd_regl(port, S3C2410_UCON); + + dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n", + port, port->mapbase, cfg); + + /* ensure we don't change the clock settings... */ + + ucon &= S3C6400_UCON_CLKMASK; + + wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); + wr_regl(port, S3C2410_ULCON, cfg->ulcon); + + /* reset both fifos */ + + wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); + wr_regl(port, S3C2410_UFCON, cfg->ufcon); + + return 0; +} + +static struct s3c24xx_uart_info s3c6400_uart_inf = { + .name = "Samsung S3C6400 UART", + .type = PORT_S3C6400, + .fifosize = 64, + .rx_fifomask = S3C2440_UFSTAT_RXMASK, + .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, + .rx_fifofull = S3C2440_UFSTAT_RXFULL, + .tx_fifofull = S3C2440_UFSTAT_TXFULL, + .tx_fifomask = S3C2440_UFSTAT_TXMASK, + .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, + .get_clksrc = s3c6400_serial_getsource, + .set_clksrc = s3c6400_serial_setsource, + .reset_port = s3c6400_serial_resetport, +}; + +/* device management */ + +static int s3c6400_serial_probe(struct platform_device *dev) +{ + dbg("s3c6400_serial_probe: dev=%p\n", dev); + return s3c24xx_serial_probe(dev, &s3c6400_uart_inf); +} + +static struct platform_driver s3c6400_serial_drv = { + .probe = s3c6400_serial_probe, + .remove = s3c24xx_serial_remove, + .driver = { + .name = "s3c6400-uart", + .owner = THIS_MODULE, + }, +}; + +s3c24xx_console_init(&s3c6400_serial_drv, &s3c6400_uart_inf); + +static int __init s3c6400_serial_init(void) +{ + return s3c24xx_serial_init(&s3c6400_serial_drv, &s3c6400_uart_inf); +} + +static void __exit s3c6400_serial_exit(void) +{ + platform_driver_unregister(&s3c6400_serial_drv); +} + +module_init(s3c6400_serial_init); +module_exit(s3c6400_serial_exit); + +MODULE_DESCRIPTION("Samsung S3C6400,S3C6410 SoC Serial port driver"); +MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:s3c6400-uart"); diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c index 1e219d3..41ac948 100644 --- a/drivers/serial/samsung.c +++ b/drivers/serial/samsung.c @@ -42,13 +42,14 @@ #include <linux/serial.h> #include <linux/delay.h> #include <linux/clk.h> +#include <linux/cpufreq.h> #include <asm/irq.h> #include <mach/hardware.h> +#include <mach/map.h> #include <plat/regs-serial.h> -#include <mach/regs-gpio.h> #include "samsung.h" @@ -58,19 +59,6 @@ #define S3C24XX_SERIAL_MAJOR 204 #define S3C24XX_SERIAL_MINOR 64 -/* we can support 3 uarts, but not always use them */ - -#ifdef CONFIG_CPU_S3C2400 -#define NR_PORTS (2) -#else -#define NR_PORTS (3) -#endif - -/* port irq numbers */ - -#define TX_IRQ(port) ((port)->irq + 1) -#define RX_IRQ(port) ((port)->irq) - /* macros to change one thing to another */ #define tx_enabled(port) ((port)->unused[0]) @@ -136,8 +124,10 @@ static void s3c24xx_serial_rx_disable(struct uart_port *port) static void s3c24xx_serial_stop_tx(struct uart_port *port) { + struct s3c24xx_uart_port *ourport = to_ourport(port); + if (tx_enabled(port)) { - disable_irq(TX_IRQ(port)); + disable_irq(ourport->tx_irq); tx_enabled(port) = 0; if (port->flags & UPF_CONS_FLOW) s3c24xx_serial_rx_enable(port); @@ -146,11 +136,13 @@ static void s3c24xx_serial_stop_tx(struct uart_port *port) static void s3c24xx_serial_start_tx(struct uart_port *port) { + struct s3c24xx_uart_port *ourport = to_ourport(port); + if (!tx_enabled(port)) { if (port->flags & UPF_CONS_FLOW) s3c24xx_serial_rx_disable(port); - enable_irq(TX_IRQ(port)); + enable_irq(ourport->tx_irq); tx_enabled(port) = 1; } } @@ -158,9 +150,11 @@ static void s3c24xx_serial_start_tx(struct uart_port *port) static void s3c24xx_serial_stop_rx(struct uart_port *port) { + struct s3c24xx_uart_port *ourport = to_ourport(port); + if (rx_enabled(port)) { dbg("s3c24xx_serial_stop_rx: port=%p\n", port); - disable_irq(RX_IRQ(port)); + disable_irq(ourport->rx_irq); rx_enabled(port) = 0; } } @@ -384,13 +378,13 @@ static void s3c24xx_serial_shutdown(struct uart_port *port) struct s3c24xx_uart_port *ourport = to_ourport(port); if (ourport->tx_claimed) { - free_irq(TX_IRQ(port), ourport); + free_irq(ourport->tx_irq, ourport); tx_enabled(port) = 0; ourport->tx_claimed = 0; } if (ourport->rx_claimed) { - free_irq(RX_IRQ(port), ourport); + free_irq(ourport->rx_irq, ourport); ourport->rx_claimed = 0; rx_enabled(port) = 0; } @@ -407,12 +401,11 @@ static int s3c24xx_serial_startup(struct uart_port *port) rx_enabled(port) = 1; - ret = request_irq(RX_IRQ(port), - s3c24xx_serial_rx_chars, 0, + ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0, s3c24xx_serial_portname(port), ourport); if (ret != 0) { - printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port)); + printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq); return ret; } @@ -422,12 +415,11 @@ static int s3c24xx_serial_startup(struct uart_port *port) tx_enabled(port) = 1; - ret = request_irq(TX_IRQ(port), - s3c24xx_serial_tx_chars, 0, + ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0, s3c24xx_serial_portname(port), ourport); if (ret) { - printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port)); + printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq); goto err; } @@ -452,6 +444,8 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, { struct s3c24xx_uart_port *ourport = to_ourport(port); + ourport->pm_level = level; + switch (level) { case 3: if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL) @@ -661,6 +655,7 @@ static void s3c24xx_serial_set_termios(struct uart_port *port, ourport->clksrc = clksrc; ourport->baudclk = clk; + ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; } switch (termios->c_cflag & CSIZE) { @@ -752,6 +747,8 @@ static const char *s3c24xx_serial_type(struct uart_port *port) return "S3C2440"; case PORT_S3C2412: return "S3C2412"; + case PORT_S3C6400: + return "S3C6400/10"; default: return NULL; } @@ -827,14 +824,14 @@ static struct uart_ops s3c24xx_serial_ops = { static struct uart_driver s3c24xx_uart_drv = { .owner = THIS_MODULE, .dev_name = "s3c2410_serial", - .nr = 3, + .nr = CONFIG_SERIAL_SAMSUNG_UARTS, .cons = S3C24XX_SERIAL_CONSOLE, .driver_name = S3C24XX_SERIAL_NAME, .major = S3C24XX_SERIAL_MAJOR, .minor = S3C24XX_SERIAL_MINOR, }; -static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = { +static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = { [0] = { .port = { .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock), @@ -859,7 +856,7 @@ static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = { .line = 1, } }, -#if NR_PORTS > 2 +#if CONFIG_SERIAL_SAMSUNG_UARTS > 2 [2] = { .port = { @@ -872,6 +869,20 @@ static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = { .flags = UPF_BOOT_AUTOCONF, .line = 2, } + }, +#endif +#if CONFIG_SERIAL_SAMSUNG_UARTS > 3 + [3] = { + .port = { + .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock), + .iotype = UPIO_MEM, + .irq = IRQ_S3CUART_RX3, + .uartclk = 0, + .fifosize = 16, + .ops = &s3c24xx_serial_ops, + .flags = UPF_BOOT_AUTOCONF, + .line = 3, + } } #endif }; @@ -890,6 +901,89 @@ static inline int s3c24xx_serial_resetport(struct uart_port *port, return (info->reset_port)(port, cfg); } + +#ifdef CONFIG_CPU_FREQ + +static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb, + unsigned long val, void *data) +{ + struct s3c24xx_uart_port *port; + struct uart_port *uport; + + port = container_of(nb, struct s3c24xx_uart_port, freq_transition); + uport = &port->port; + + /* check to see if port is enabled */ + + if (port->pm_level != 0) + return 0; + + /* try and work out if the baudrate is changing, we can detect + * a change in rate, but we do not have support for detecting + * a disturbance in the clock-rate over the change. + */ + + if (IS_ERR(port->clk)) + goto exit; + + if (port->baudclk_rate == clk_get_rate(port->clk)) + goto exit; + + if (val == CPUFREQ_PRECHANGE) { + /* we should really shut the port down whilst the + * frequency change is in progress. */ + + } else if (val == CPUFREQ_POSTCHANGE) { + struct ktermios *termios; + struct tty_struct *tty; + + if (uport->info == NULL) + goto exit; + + tty = uport->info->port.tty; + + if (tty == NULL) + goto exit; + + termios = tty->termios; + + if (termios == NULL) { + printk(KERN_WARNING "%s: no termios?\n", __func__); + goto exit; + } + + s3c24xx_serial_set_termios(uport, termios, NULL); + } + + exit: + return 0; +} + +static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) +{ + port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition; + + return cpufreq_register_notifier(&port->freq_transition, + CPUFREQ_TRANSITION_NOTIFIER); +} + +static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) +{ + cpufreq_unregister_notifier(&port->freq_transition, + CPUFREQ_TRANSITION_NOTIFIER); +} + +#else +static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) +{ + return 0; +} + +static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) +{ +} +#endif + /* s3c24xx_serial_init_port * * initialise a single serial port from the platform device given @@ -914,8 +1008,11 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, if (port->mapbase != 0) return 0; - if (cfg->hwport > 3) - return -EINVAL; + if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) { + printk(KERN_ERR "%s: port %d bigger than %d\n", __func__, + cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS); + return -ERANGE; + } /* setup info for port */ port->dev = &platdev->dev; @@ -943,18 +1040,26 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, dbg("resource %p (%lx..%lx)\n", res, res->start, res->end); - port->mapbase = res->start; - port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART); + port->mapbase = res->start; + port->membase = S3C_VA_UART + res->start - (S3C_PA_UART & 0xfff00000); ret = platform_get_irq(platdev, 0); if (ret < 0) port->irq = 0; - else + else { port->irq = ret; + ourport->rx_irq = ret; + ourport->tx_irq = ret + 1; + } + + ret = platform_get_irq(platdev, 1); + if (ret > 0) + ourport->tx_irq = ret; ourport->clk = clk_get(&platdev->dev, "uart"); - dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n", - port->mapbase, port->membase, port->irq, port->uartclk); + dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n", + port->mapbase, port->membase, port->irq, + ourport->rx_irq, ourport->tx_irq, port->uartclk); /* reset the fifos (and setup the uart) */ s3c24xx_serial_resetport(port, cfg); @@ -1002,6 +1107,10 @@ int s3c24xx_serial_probe(struct platform_device *dev, if (ret < 0) printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__); + ret = s3c24xx_serial_cpufreq_register(ourport); + if (ret < 0) + dev_err(&dev->dev, "failed to add cpufreq notifier\n"); + return 0; probe_err: @@ -1015,6 +1124,7 @@ int s3c24xx_serial_remove(struct platform_device *dev) struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); if (port) { + s3c24xx_serial_cpufreq_deregister(to_ourport(port)); device_remove_file(&dev->dev, &dev_attr_clock_source); uart_remove_one_port(&s3c24xx_uart_drv, port); } @@ -1219,7 +1329,7 @@ static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info) platdev_ptr = s3c24xx_uart_devs; - for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) { + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) { s3c24xx_serial_init_port(ptr, info, *platdev_ptr); } @@ -1240,7 +1350,7 @@ s3c24xx_serial_console_setup(struct console *co, char *options) /* is this a valid port */ - if (co->index == -1 || co->index >= NR_PORTS) + if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS) co->index = 0; port = &s3c24xx_serial_ports[co->index].port; diff --git a/drivers/serial/samsung.h b/drivers/serial/samsung.h index 5c92ebb..571d6b9 100644 --- a/drivers/serial/samsung.h +++ b/drivers/serial/samsung.h @@ -33,12 +33,21 @@ struct s3c24xx_uart_info { struct s3c24xx_uart_port { unsigned char rx_claimed; unsigned char tx_claimed; + unsigned int pm_level; + unsigned long baudclk_rate; + + unsigned int rx_irq; + unsigned int tx_irq; struct s3c24xx_uart_info *info; struct s3c24xx_uart_clksrc *clksrc; struct clk *clk; struct clk *baudclk; struct uart_port port; + +#ifdef CONFIG_CPU_FREQ + struct notifier_block freq_transition; +#endif }; /* conversion functions */ diff --git a/drivers/serial/serial_lh7a40x.c b/drivers/serial/serial_lh7a40x.c index 61dc8b3..a7bf024 100644 --- a/drivers/serial/serial_lh7a40x.c +++ b/drivers/serial/serial_lh7a40x.c @@ -41,9 +41,10 @@ #include <linux/tty_flip.h> #include <linux/serial_core.h> #include <linux/serial.h> +#include <linux/io.h> -#include <asm/io.h> #include <asm/irq.h> +#include <mach/hardware.h> #define DEV_MAJOR 204 #define DEV_MINOR 16 diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c index cf12f2d..6104f46 100644 --- a/drivers/spi/pxa2xx_spi.c +++ b/drivers/spi/pxa2xx_spi.c @@ -32,8 +32,8 @@ #include <asm/io.h> #include <asm/irq.h> #include <asm/delay.h> -#include <asm/dma.h> +#include <mach/dma.h> #include <mach/hardware.h> #include <mach/pxa-regs.h> #include <mach/regs-ssp.h> diff --git a/drivers/spi/spi_s3c24xx.c b/drivers/spi/spi_s3c24xx.c index c252cba..256d183 100644 --- a/drivers/spi/spi_s3c24xx.c +++ b/drivers/spi/spi_s3c24xx.c @@ -28,7 +28,7 @@ #include <mach/hardware.h> #include <mach/regs-gpio.h> -#include <asm/plat-s3c24xx/regs-spi.h> +#include <plat/regs-spi.h> #include <mach/spi.h> struct s3c24xx_spi { diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c index 2dbc0db..8c5026b 100644 --- a/drivers/usb/gadget/pxa25x_udc.c +++ b/drivers/usb/gadget/pxa25x_udc.c @@ -2145,7 +2145,7 @@ static int __init pxa25x_udc_probe(struct platform_device *pdev) if (irq < 0) return -ENODEV; - dev->clk = clk_get(&pdev->dev, "UDCCLK"); + dev->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(dev->clk)) { retval = PTR_ERR(dev->clk); goto err_clk; diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c index caa37c9..944e4ff 100644 --- a/drivers/usb/gadget/pxa27x_udc.c +++ b/drivers/usb/gadget/pxa27x_udc.c @@ -2226,7 +2226,7 @@ static int __init pxa_udc_probe(struct platform_device *pdev) udc->dev = &pdev->dev; udc->mach = pdev->dev.platform_data; - udc->clk = clk_get(&pdev->dev, "UDCCLK"); + udc->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(udc->clk)) { retval = PTR_ERR(udc->clk); goto err_clk; diff --git a/drivers/usb/gadget/s3c2410_udc.c b/drivers/usb/gadget/s3c2410_udc.c index 00ba06b..8d8d651 100644 --- a/drivers/usb/gadget/s3c2410_udc.c +++ b/drivers/usb/gadget/s3c2410_udc.c @@ -53,8 +53,8 @@ #include <mach/hardware.h> #include <mach/regs-gpio.h> -#include <asm/plat-s3c24xx/regs-udc.h> -#include <asm/plat-s3c24xx/udc.h> +#include <plat/regs-udc.h> +#include <plat/udc.h> #include "s3c2410_udc.h" diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c index 5416cf9..9d48790 100644 --- a/drivers/usb/host/ehci-orion.c +++ b/drivers/usb/host/ehci-orion.c @@ -33,8 +33,9 @@ /* * Implement Orion USB controller specification guidelines */ -static void orion_usb_setup(struct usb_hcd *hcd) +static void orion_usb_phy_v1_setup(struct usb_hcd *hcd) { + /* The below GLs are according to the Orion Errata document */ /* * Clear interrupt cause and mask */ @@ -258,9 +259,19 @@ static int __init ehci_orion_drv_probe(struct platform_device *pdev) ehci_orion_conf_mbus_windows(hcd, pd->dram); /* - * setup Orion USB controller + * setup Orion USB controller. */ - orion_usb_setup(hcd); + switch (pd->phy_version) { + case EHCI_PHY_NA: /* dont change USB phy settings */ + break; + case EHCI_PHY_ORION: + orion_usb_phy_v1_setup(hcd); + break; + case EHCI_PHY_DD: + case EHCI_PHY_KW: + default: + printk(KERN_WARNING "Orion ehci -USB phy version isn't supported.\n"); + } err = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_DISABLED); if (err) diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c index 91697bd..4bbddb7 100644 --- a/drivers/usb/host/ohci-omap.c +++ b/drivers/usb/host/ohci-omap.c @@ -18,6 +18,7 @@ #include <linux/jiffies.h> #include <linux/platform_device.h> #include <linux/clk.h> +#include <linux/gpio.h> #include <mach/hardware.h> #include <asm/io.h> @@ -25,7 +26,6 @@ #include <mach/mux.h> #include <mach/irqs.h> -#include <mach/gpio.h> #include <mach/fpga.h> #include <mach/usb.h> @@ -254,8 +254,8 @@ static int ohci_omap_init(struct usb_hcd *hcd) /* gpio9 for overcurrent detction */ omap_cfg_reg(W8_1610_GPIO9); - omap_request_gpio(9); - omap_set_gpio_direction(9, 1 /* IN */); + gpio_request(9, "OHCI overcurrent"); + gpio_direction_input(9); /* for paranoia's sake: disable USB.PUEN */ omap_cfg_reg(W4_USB_HIGHZ); @@ -407,7 +407,7 @@ usb_hcd_omap_remove (struct usb_hcd *hcd, struct platform_device *pdev) put_device(ohci->transceiver->dev); } if (machine_is_omap_osk()) - omap_free_gpio(9); + gpio_free(9); iounmap(hcd->regs); release_mem_region(hcd->rsrc_start, hcd->rsrc_len); usb_put_hcd(hcd); diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c index e294d43..e44dc2c 100644 --- a/drivers/usb/host/ohci-pxa27x.c +++ b/drivers/usb/host/ohci-pxa27x.c @@ -296,7 +296,7 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device return -ENXIO; } - usb_clk = clk_get(&pdev->dev, "USBCLK"); + usb_clk = clk_get(&pdev->dev, NULL); if (IS_ERR(usb_clk)) return PTR_ERR(usb_clk); diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index d0c8219..6372f8b 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -362,7 +362,7 @@ endchoice config FB_ACORN bool "Acorn VIDC support" - depends on (FB = y) && ARM && (ARCH_ACORN || ARCH_CLPS7500) + depends on (FB = y) && ARM && ARCH_ACORN select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT @@ -1817,6 +1817,11 @@ config FB_PXA If unsure, say N. +config FB_PXA_OVERLAY + bool "Support PXA27x/PXA3xx Overlay(s) as framebuffer" + default n + depends on FB_PXA && (PXA27x || PXA3xx) + config FB_PXA_SMARTPANEL bool "PXA Smartpanel LCD support" default n diff --git a/drivers/video/amba-clcd.c b/drivers/video/amba-clcd.c index a7a1c89..2ac52fd 100644 --- a/drivers/video/amba-clcd.c +++ b/drivers/video/amba-clcd.c @@ -343,14 +343,14 @@ static int clcdfb_register(struct clcd_fb *fb) { int ret; - fb->clk = clk_get(&fb->dev->dev, "CLCDCLK"); + fb->clk = clk_get(&fb->dev->dev, NULL); if (IS_ERR(fb->clk)) { ret = PTR_ERR(fb->clk); goto out; } fb->fb.fix.mmio_start = fb->dev->res.start; - fb->fb.fix.mmio_len = SZ_4K; + fb->fb.fix.mmio_len = 4096; fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len); if (!fb->regs) { diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c index ccd9861..d58c68c 100644 --- a/drivers/video/imxfb.c +++ b/drivers/video/imxfb.c @@ -1,6 +1,4 @@ /* - * linux/drivers/video/imxfb.c - * * Freescale i.MX Frame Buffer device driver * * Copyright (C) 2004 Sascha Hauer, Pengutronix @@ -16,7 +14,6 @@ * linux-arm-kernel@lists.arm.linux.org.uk */ -//#define DEBUG 1 #include <linux/module.h> #include <linux/kernel.h> @@ -32,9 +29,8 @@ #include <linux/cpufreq.h> #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/io.h> -#include <mach/hardware.h> -#include <asm/io.h> #include <mach/imxfb.h> /* @@ -42,23 +38,150 @@ */ #define DEBUG_VAR 1 -#include "imxfb.h" +#define DRIVER_NAME "imx-fb" + +#define LCDC_SSA 0x00 + +#define LCDC_SIZE 0x04 +#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) +#define SIZE_YMAX(y) ((y) & 0x1ff) + +#define LCDC_VPW 0x08 +#define VPW_VPW(x) ((x) & 0x3ff) + +#define LCDC_CPOS 0x0C +#define CPOS_CC1 (1<<31) +#define CPOS_CC0 (1<<30) +#define CPOS_OP (1<<28) +#define CPOS_CXP(x) (((x) & 3ff) << 16) +#define CPOS_CYP(y) ((y) & 0x1ff) + +#define LCDC_LCWHB 0x10 +#define LCWHB_BK_EN (1<<31) +#define LCWHB_CW(w) (((w) & 0x1f) << 24) +#define LCWHB_CH(h) (((h) & 0x1f) << 16) +#define LCWHB_BD(x) ((x) & 0xff) + +#define LCDC_LCHCC 0x14 +#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) +#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) +#define LCHCC_CUR_COL_B(b) ((b) & 0x1f) + +#define LCDC_PCR 0x18 + +#define LCDC_HCR 0x1C +#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) +#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) +#define HCR_H_WAIT_2(x) ((x) & 0xff) + +#define LCDC_VCR 0x20 +#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) +#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) +#define VCR_V_WAIT_2(x) ((x) & 0xff) + +#define LCDC_POS 0x24 +#define POS_POS(x) ((x) & 1f) + +#define LCDC_LSCR1 0x28 +/* bit fields in imxfb.h */ + +#define LCDC_PWMR 0x2C +/* bit fields in imxfb.h */ + +#define LCDC_DMACR 0x30 +/* bit fields in imxfb.h */ + +#define LCDC_RMCR 0x34 +#define RMCR_LCDC_EN (1<<1) +#define RMCR_SELF_REF (1<<0) + +#define LCDC_LCDICR 0x38 +#define LCDICR_INT_SYN (1<<2) +#define LCDICR_INT_CON (1) + +#define LCDC_LCDISR 0x40 +#define LCDISR_UDR_ERR (1<<3) +#define LCDISR_ERR_RES (1<<2) +#define LCDISR_EOF (1<<1) +#define LCDISR_BOF (1<<0) + +/* + * These are the bitfields for each + * display depth that we support. + */ +struct imxfb_rgb { + struct fb_bitfield red; + struct fb_bitfield green; + struct fb_bitfield blue; + struct fb_bitfield transp; +}; + +struct imxfb_info { + struct platform_device *pdev; + void __iomem *regs; -static struct imxfb_rgb def_rgb_16 = { - .red = { .offset = 8, .length = 4, }, - .green = { .offset = 4, .length = 4, }, - .blue = { .offset = 0, .length = 4, }, - .transp = { .offset = 0, .length = 0, }, + u_int max_bpp; + u_int max_xres; + u_int max_yres; + + /* + * These are the addresses we mapped + * the framebuffer memory region to. + */ + dma_addr_t map_dma; + u_char *map_cpu; + u_int map_size; + + u_char *screen_cpu; + dma_addr_t screen_dma; + u_int palette_size; + + dma_addr_t dbar1; + dma_addr_t dbar2; + + u_int pcr; + u_int pwmr; + u_int lscr1; + u_int dmacr; + u_int cmap_inverse:1, + cmap_static:1, + unused:30; + + void (*lcd_power)(int); + void (*backlight_power)(int); +}; + +#define IMX_NAME "IMX" + +/* + * Minimum X and Y resolutions + */ +#define MIN_XRES 64 +#define MIN_YRES 64 + +static struct imxfb_rgb def_rgb_16_tft = { + .red = {.offset = 11, .length = 5,}, + .green = {.offset = 5, .length = 6,}, + .blue = {.offset = 0, .length = 5,}, + .transp = {.offset = 0, .length = 0,}, +}; + +static struct imxfb_rgb def_rgb_16_stn = { + .red = {.offset = 8, .length = 4,}, + .green = {.offset = 4, .length = 4,}, + .blue = {.offset = 0, .length = 4,}, + .transp = {.offset = 0, .length = 0,}, }; static struct imxfb_rgb def_rgb_8 = { - .red = { .offset = 0, .length = 8, }, - .green = { .offset = 0, .length = 8, }, - .blue = { .offset = 0, .length = 8, }, - .transp = { .offset = 0, .length = 0, }, + .red = {.offset = 0, .length = 8,}, + .green = {.offset = 0, .length = 8,}, + .blue = {.offset = 0, .length = 8,}, + .transp = {.offset = 0, .length = 0,}, }; -static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info); +static int imxfb_activate_var(struct fb_var_screeninfo *var, + struct fb_info *info); static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) { @@ -67,10 +190,8 @@ static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) return chan << bf->offset; } -#define LCDC_PALETTE(x) __REG2(IMX_LCDC_BASE+0x800, (x)<<2) -static int -imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, - u_int trans, struct fb_info *info) +static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, + u_int trans, struct fb_info *info) { struct imxfb_info *fbi = info->par; u_int val, ret = 1; @@ -81,14 +202,13 @@ imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, (CNVT_TOHW(green,4) << 4) | CNVT_TOHW(blue, 4); - LCDC_PALETTE(regno) = val; + writel(val, fbi->regs + 0x800 + (regno << 2)); ret = 0; } return ret; } -static int -imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, +static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, u_int trans, struct fb_info *info) { struct imxfb_info *fbi = info->par; @@ -148,11 +268,10 @@ imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, * bitfields, horizontal timing, vertical timing. */ -static int -imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { struct imxfb_info *fbi = info->par; - int rgbidx; + struct imxfb_rgb *rgb; if (var->xres < MIN_XRES) var->xres = MIN_XRES; @@ -168,23 +287,25 @@ imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); switch (var->bits_per_pixel) { case 16: - rgbidx = RGB_16; + default: + if (readl(fbi->regs + LCDC_PCR) & PCR_TFT) + rgb = &def_rgb_16_tft; + else + rgb = &def_rgb_16_stn; break; case 8: - rgbidx = RGB_8; + rgb = &def_rgb_8; break; - default: - rgbidx = RGB_16; } /* * Copy the RGB parameters for this display * from the machine specific parameters. */ - var->red = fbi->rgb[rgbidx]->red; - var->green = fbi->rgb[rgbidx]->green; - var->blue = fbi->rgb[rgbidx]->blue; - var->transp = fbi->rgb[rgbidx]->transp; + var->red = rgb->red; + var->green = rgb->green; + var->blue = rgb->blue; + var->transp = rgb->transp; pr_debug("RGBT length = %d:%d:%d:%d\n", var->red.length, var->green.length, var->blue.length, @@ -221,8 +342,7 @@ static int imxfb_set_par(struct fb_info *info) info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; } - info->fix.line_length = var->xres_virtual * - var->bits_per_pixel / 8; + info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8; fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16; imxfb_activate_var(var, info); @@ -235,22 +355,27 @@ static void imxfb_enable_controller(struct imxfb_info *fbi) pr_debug("Enabling LCD controller\n"); /* initialize LCDC */ - LCDC_RMCR &= ~RMCR_LCDC_EN; /* just to be safe... */ + writel(readl(fbi->regs + LCDC_RMCR) & ~RMCR_LCDC_EN, + fbi->regs + LCDC_RMCR); /* just to be safe... */ + + writel(fbi->screen_dma, fbi->regs + LCDC_SSA); - LCDC_SSA = fbi->screen_dma; /* physical screen start address */ - LCDC_VPW = VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4); + writel(VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4), + fbi->regs + LCDC_VPW); - LCDC_POS = 0x00000000; /* panning offset 0 (0 pixel offset) */ + /* panning offset 0 (0 pixel offset) */ + writel(0x00000000, fbi->regs + LCDC_POS); /* disable hardware cursor */ - LCDC_CPOS &= ~(CPOS_CC0 | CPOS_CC1); + writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1), + fbi->regs + LCDC_CPOS); - LCDC_RMCR = RMCR_LCDC_EN; + writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR); - if(fbi->backlight_power) + if (fbi->backlight_power) fbi->backlight_power(1); - if(fbi->lcd_power) + if (fbi->lcd_power) fbi->lcd_power(1); } @@ -258,12 +383,12 @@ static void imxfb_disable_controller(struct imxfb_info *fbi) { pr_debug("Disabling LCD controller\n"); - if(fbi->backlight_power) + if (fbi->backlight_power) fbi->backlight_power(0); - if(fbi->lcd_power) + if (fbi->lcd_power) fbi->lcd_power(0); - LCDC_RMCR = 0; + writel(0, fbi->regs + LCDC_RMCR); } static int imxfb_blank(int blank, struct fb_info *info) @@ -340,74 +465,26 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf info->fix.id, var->lower_margin); #endif - LCDC_HCR = HCR_H_WIDTH(var->hsync_len) | - HCR_H_WAIT_1(var->left_margin) | - HCR_H_WAIT_2(var->right_margin); + writel(HCR_H_WIDTH(var->hsync_len) | + HCR_H_WAIT_1(var->right_margin) | + HCR_H_WAIT_2(var->left_margin), + fbi->regs + LCDC_HCR); - LCDC_VCR = VCR_V_WIDTH(var->vsync_len) | - VCR_V_WAIT_1(var->upper_margin) | - VCR_V_WAIT_2(var->lower_margin); + writel(VCR_V_WIDTH(var->vsync_len) | + VCR_V_WAIT_1(var->lower_margin) | + VCR_V_WAIT_2(var->upper_margin), + fbi->regs + LCDC_VCR); - LCDC_SIZE = SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres); - LCDC_PCR = fbi->pcr; - LCDC_PWMR = fbi->pwmr; - LCDC_LSCR1 = fbi->lscr1; - LCDC_DMACR = fbi->dmacr; + writel(SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres), + fbi->regs + LCDC_SIZE); + writel(fbi->pcr, fbi->regs + LCDC_PCR); + writel(fbi->pwmr, fbi->regs + LCDC_PWMR); + writel(fbi->lscr1, fbi->regs + LCDC_LSCR1); + writel(fbi->dmacr, fbi->regs + LCDC_DMACR); return 0; } -static void imxfb_setup_gpio(struct imxfb_info *fbi) -{ - int width; - - LCDC_RMCR &= ~(RMCR_LCDC_EN | RMCR_SELF_REF); - - if( fbi->pcr & PCR_TFT ) - width = 16; - else - width = 1 << ((fbi->pcr >> 28) & 0x3); - - switch(width) { - case 16: - imx_gpio_mode(PD30_PF_LD15); - imx_gpio_mode(PD29_PF_LD14); - imx_gpio_mode(PD28_PF_LD13); - imx_gpio_mode(PD27_PF_LD12); - imx_gpio_mode(PD26_PF_LD11); - imx_gpio_mode(PD25_PF_LD10); - imx_gpio_mode(PD24_PF_LD9); - imx_gpio_mode(PD23_PF_LD8); - case 8: - imx_gpio_mode(PD22_PF_LD7); - imx_gpio_mode(PD21_PF_LD6); - imx_gpio_mode(PD20_PF_LD5); - imx_gpio_mode(PD19_PF_LD4); - case 4: - imx_gpio_mode(PD18_PF_LD3); - imx_gpio_mode(PD17_PF_LD2); - case 2: - imx_gpio_mode(PD16_PF_LD1); - case 1: - imx_gpio_mode(PD15_PF_LD0); - } - - /* initialize GPIOs */ - imx_gpio_mode(PD6_PF_LSCLK); - imx_gpio_mode(PD11_PF_CONTRAST); - imx_gpio_mode(PD14_PF_FLM_VSYNC); - imx_gpio_mode(PD13_PF_LP_HSYNC); - imx_gpio_mode(PD12_PF_ACD_OE); - - /* These are only needed for Sharp HR TFT displays */ - if (fbi->pcr & PCR_SHARP) { - imx_gpio_mode(PD7_PF_REV); - imx_gpio_mode(PD8_PF_CLS); - imx_gpio_mode(PD9_PF_PS); - imx_gpio_mode(PD10_PF_SPL_SPR); - } -} - #ifdef CONFIG_PM /* * Power management hooks. Note that we won't be called from IRQ context, @@ -416,7 +493,8 @@ static void imxfb_setup_gpio(struct imxfb_info *fbi) static int imxfb_suspend(struct platform_device *dev, pm_message_t state) { struct imxfb_info *fbi = platform_get_drvdata(dev); - pr_debug("%s\n",__func__); + + pr_debug("%s\n", __func__); imxfb_disable_controller(fbi); return 0; @@ -425,7 +503,8 @@ static int imxfb_suspend(struct platform_device *dev, pm_message_t state) static int imxfb_resume(struct platform_device *dev) { struct imxfb_info *fbi = platform_get_drvdata(dev); - pr_debug("%s\n",__func__); + + pr_debug("%s\n", __func__); imxfb_enable_controller(fbi); return 0; @@ -435,149 +514,136 @@ static int imxfb_resume(struct platform_device *dev) #define imxfb_resume NULL #endif -static int __init imxfb_init_fbinfo(struct device *dev) +static int __init imxfb_init_fbinfo(struct platform_device *pdev) { - struct imxfb_mach_info *inf = dev->platform_data; - struct fb_info *info = dev_get_drvdata(dev); + struct imx_fb_platform_data *pdata = pdev->dev.platform_data; + struct fb_info *info = dev_get_drvdata(&pdev->dev); struct imxfb_info *fbi = info->par; pr_debug("%s\n",__func__); - info->pseudo_palette = kmalloc( sizeof(u32) * 16, GFP_KERNEL); + info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL); if (!info->pseudo_palette) return -ENOMEM; memset(fbi, 0, sizeof(struct imxfb_info)); - fbi->dev = dev; strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id)); - info->fix.type = FB_TYPE_PACKED_PIXELS; + info->fix.type = FB_TYPE_PACKED_PIXELS; info->fix.type_aux = 0; info->fix.xpanstep = 0; info->fix.ypanstep = 0; info->fix.ywrapstep = 0; - info->fix.accel = FB_ACCEL_NONE; + info->fix.accel = FB_ACCEL_NONE; info->var.nonstd = 0; info->var.activate = FB_ACTIVATE_NOW; info->var.height = -1; info->var.width = -1; info->var.accel_flags = 0; - info->var.vmode = FB_VMODE_NONINTERLACED; + info->var.vmode = FB_VMODE_NONINTERLACED; info->fbops = &imxfb_ops; - info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; - - fbi->rgb[RGB_16] = &def_rgb_16; - fbi->rgb[RGB_8] = &def_rgb_8; - - fbi->max_xres = inf->xres; - info->var.xres = inf->xres; - info->var.xres_virtual = inf->xres; - fbi->max_yres = inf->yres; - info->var.yres = inf->yres; - info->var.yres_virtual = inf->yres; - fbi->max_bpp = inf->bpp; - info->var.bits_per_pixel = inf->bpp; - info->var.nonstd = inf->nonstd; - info->var.pixclock = inf->pixclock; - info->var.hsync_len = inf->hsync_len; - info->var.left_margin = inf->left_margin; - info->var.right_margin = inf->right_margin; - info->var.vsync_len = inf->vsync_len; - info->var.upper_margin = inf->upper_margin; - info->var.lower_margin = inf->lower_margin; - info->var.sync = inf->sync; - info->var.grayscale = inf->cmap_greyscale; - fbi->cmap_inverse = inf->cmap_inverse; - fbi->cmap_static = inf->cmap_static; - fbi->pcr = inf->pcr; - fbi->lscr1 = inf->lscr1; - fbi->dmacr = inf->dmacr; - fbi->pwmr = inf->pwmr; - fbi->lcd_power = inf->lcd_power; - fbi->backlight_power = inf->backlight_power; + info->flags = FBINFO_FLAG_DEFAULT | + FBINFO_READS_FAST; + + fbi->max_xres = pdata->xres; + info->var.xres = pdata->xres; + info->var.xres_virtual = pdata->xres; + fbi->max_yres = pdata->yres; + info->var.yres = pdata->yres; + info->var.yres_virtual = pdata->yres; + fbi->max_bpp = pdata->bpp; + info->var.bits_per_pixel = pdata->bpp; + info->var.nonstd = pdata->nonstd; + info->var.pixclock = pdata->pixclock; + info->var.hsync_len = pdata->hsync_len; + info->var.left_margin = pdata->left_margin; + info->var.right_margin = pdata->right_margin; + info->var.vsync_len = pdata->vsync_len; + info->var.upper_margin = pdata->upper_margin; + info->var.lower_margin = pdata->lower_margin; + info->var.sync = pdata->sync; + info->var.grayscale = pdata->cmap_greyscale; + fbi->cmap_inverse = pdata->cmap_inverse; + fbi->cmap_static = pdata->cmap_static; + fbi->pcr = pdata->pcr; + fbi->lscr1 = pdata->lscr1; + fbi->dmacr = pdata->dmacr; + fbi->pwmr = pdata->pwmr; + fbi->lcd_power = pdata->lcd_power; + fbi->backlight_power = pdata->backlight_power; info->fix.smem_len = fbi->max_xres * fbi->max_yres * fbi->max_bpp / 8; return 0; } -/* - * Allocates the DRAM memory for the frame buffer. This buffer is - * remapped into a non-cached, non-buffered, memory region to - * allow pixel writes to occur without flushing the cache. - * Once this area is remapped, all virtual memory access to the - * video memory should occur at the new region. - */ -static int __init imxfb_map_video_memory(struct fb_info *info) -{ - struct imxfb_info *fbi = info->par; - - fbi->map_size = PAGE_ALIGN(info->fix.smem_len); - fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size, - &fbi->map_dma,GFP_KERNEL); - - if (fbi->map_cpu) { - info->screen_base = fbi->map_cpu; - fbi->screen_cpu = fbi->map_cpu; - fbi->screen_dma = fbi->map_dma; - info->fix.smem_start = fbi->screen_dma; - } - - return fbi->map_cpu ? 0 : -ENOMEM; -} - static int __init imxfb_probe(struct platform_device *pdev) { struct imxfb_info *fbi; struct fb_info *info; - struct imxfb_mach_info *inf; + struct imx_fb_platform_data *pdata; struct resource *res; int ret; printk("i.MX Framebuffer driver\n"); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if(!res) + if (!res) return -ENODEV; - inf = pdev->dev.platform_data; - if(!inf) { + pdata = pdev->dev.platform_data; + if (!pdata) { dev_err(&pdev->dev,"No platform_data available\n"); return -ENOMEM; } info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev); - if(!info) + if (!info) return -ENOMEM; fbi = info->par; platform_set_drvdata(pdev, info); - ret = imxfb_init_fbinfo(&pdev->dev); - if( ret < 0 ) + ret = imxfb_init_fbinfo(pdev); + if (ret < 0) goto failed_init; - res = request_mem_region(res->start, res->end - res->start + 1, "IMXFB"); + res = request_mem_region(res->start, resource_size(res), + DRIVER_NAME); if (!res) { ret = -EBUSY; - goto failed_regs; + goto failed_req; + } + + fbi->regs = ioremap(res->start, resource_size(res)); + if (fbi->regs == NULL) { + printk(KERN_ERR"Cannot map frame buffer registers\n"); + goto failed_ioremap; } - if (!inf->fixed_screen_cpu) { - ret = imxfb_map_video_memory(info); - if (ret) { + if (!pdata->fixed_screen_cpu) { + fbi->map_size = PAGE_ALIGN(info->fix.smem_len); + fbi->map_cpu = dma_alloc_writecombine(&pdev->dev, + fbi->map_size, &fbi->map_dma, GFP_KERNEL); + + if (!fbi->map_cpu) { dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret); ret = -ENOMEM; goto failed_map; } + + info->screen_base = fbi->map_cpu; + fbi->screen_cpu = fbi->map_cpu; + fbi->screen_dma = fbi->map_dma; + info->fix.smem_start = fbi->screen_dma; } else { /* Fixed framebuffer mapping enables location of the screen in eSRAM */ - fbi->map_cpu = inf->fixed_screen_cpu; - fbi->map_dma = inf->fixed_screen_dma; + fbi->map_cpu = pdata->fixed_screen_cpu; + fbi->map_dma = pdata->fixed_screen_dma; info->screen_base = fbi->map_cpu; fbi->screen_cpu = fbi->map_cpu; fbi->screen_dma = fbi->map_dma; @@ -590,12 +656,10 @@ static int __init imxfb_probe(struct platform_device *pdev) */ imxfb_check_var(&info->var, info); - ret = fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0); + ret = fb_alloc_cmap(&info->cmap, 1 << info->var.bits_per_pixel, 0); if (ret < 0) goto failed_cmap; - imxfb_setup_gpio(fbi); - imxfb_set_par(info); ret = register_framebuffer(info); if (ret < 0) { @@ -610,20 +674,22 @@ static int __init imxfb_probe(struct platform_device *pdev) failed_register: fb_dealloc_cmap(&info->cmap); failed_cmap: - if (!inf->fixed_screen_cpu) + if (!pdata->fixed_screen_cpu) dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu, - fbi->map_dma); + fbi->map_dma); failed_map: - kfree(info->pseudo_palette); -failed_regs: + iounmap(fbi->regs); +failed_ioremap: release_mem_region(res->start, res->end - res->start); +failed_req: + kfree(info->pseudo_palette); failed_init: platform_set_drvdata(pdev, NULL); framebuffer_release(info); return ret; } -static int imxfb_remove(struct platform_device *pdev) +static int __devexit imxfb_remove(struct platform_device *pdev) { struct fb_info *info = platform_get_drvdata(pdev); struct imxfb_info *fbi = info->par; @@ -639,6 +705,7 @@ static int imxfb_remove(struct platform_device *pdev) kfree(info->pseudo_palette); framebuffer_release(info); + iounmap(fbi->regs); release_mem_region(res->start, res->end - res->start + 1); platform_set_drvdata(pdev, NULL); @@ -653,19 +720,18 @@ void imxfb_shutdown(struct platform_device * dev) } static struct platform_driver imxfb_driver = { - .probe = imxfb_probe, .suspend = imxfb_suspend, .resume = imxfb_resume, - .remove = imxfb_remove, + .remove = __devexit_p(imxfb_remove), .shutdown = imxfb_shutdown, .driver = { - .name = "imx-fb", + .name = DRIVER_NAME, }, }; int __init imxfb_init(void) { - return platform_driver_register(&imxfb_driver); + return platform_driver_probe(&imxfb_driver, imxfb_probe); } static void __exit imxfb_cleanup(void) diff --git a/drivers/video/imxfb.h b/drivers/video/imxfb.h deleted file mode 100644 index e837a8b..0000000 --- a/drivers/video/imxfb.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * linux/drivers/video/imxfb.h - * - * Freescale i.MX Frame Buffer device driver - * - * Copyright (C) 2004 S.Hauer, Pengutronix - * - * Copyright (C) 1999 Eric A. Thomas - * Based on acornfb.c Copyright (C) Russell King. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -/* - * These are the bitfields for each - * display depth that we support. - */ -struct imxfb_rgb { - struct fb_bitfield red; - struct fb_bitfield green; - struct fb_bitfield blue; - struct fb_bitfield transp; -}; - -#define RGB_16 (0) -#define RGB_8 (1) -#define NR_RGB 2 - -struct imxfb_info { - struct device *dev; - struct imxfb_rgb *rgb[NR_RGB]; - - u_int max_bpp; - u_int max_xres; - u_int max_yres; - - /* - * These are the addresses we mapped - * the framebuffer memory region to. - */ - dma_addr_t map_dma; - u_char * map_cpu; - u_int map_size; - - u_char * screen_cpu; - dma_addr_t screen_dma; - u_int palette_size; - - dma_addr_t dbar1; - dma_addr_t dbar2; - - u_int pcr; - u_int pwmr; - u_int lscr1; - u_int dmacr; - u_int cmap_inverse:1, - cmap_static:1, - unused:30; - - void (*lcd_power)(int); - void (*backlight_power)(int); -}; - -#define IMX_NAME "IMX" - -/* - * Minimum X and Y resolutions - */ -#define MIN_XRES 64 -#define MIN_YRES 64 - diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index cc59c52..48ff701 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c @@ -20,6 +20,16 @@ * * linux-arm-kernel@lists.arm.linux.org.uk * + * Add support for overlay1 and overlay2 based on pxafb_overlay.c: + * + * Copyright (C) 2004, Intel Corporation + * + * 2003/08/27: <yu.tang@intel.com> + * 2004/03/10: <stanley.cai@intel.com> + * 2004/10/28: <yan.yin@intel.com> + * + * Copyright (C) 2006-2008 Marvell International Ltd. + * All Rights Reserved */ #include <linux/module.h> @@ -50,7 +60,6 @@ #include <asm/irq.h> #include <asm/div64.h> #include <mach/pxa-regs.h> -#include <mach/pxa2xx-gpio.h> #include <mach/bitfield.h> #include <mach/pxafb.h> @@ -67,14 +76,16 @@ LCCR0_SFM | LCCR0_LDM | LCCR0_ENB) #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\ - LCCR3_PCD | LCCR3_BPP) - -static void (*pxafb_backlight_power)(int); -static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); + LCCR3_PCD | LCCR3_BPP(0xf)) static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *); static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); +static void setup_base_frame(struct pxafb_info *fbi, int branch); +static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, + unsigned long offset, size_t size); + +static unsigned long video_mem_size = 0; static inline unsigned long lcd_readl(struct pxafb_info *fbi, unsigned int off) @@ -156,6 +167,12 @@ pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, val |= ((blue >> 8) & 0x000000fc); ((u32 *)(fbi->palette_cpu))[regno] = val; break; + case LCCR4_PAL_FOR_3: + val = ((red << 8) & 0x00ff0000); + val |= ((green >> 0) & 0x0000ff00); + val |= ((blue >> 8) & 0x000000ff); + ((u32 *)(fbi->palette_cpu))[regno] = val; + break; } return 0; @@ -216,37 +233,110 @@ pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, return ret; } -/* - * pxafb_bpp_to_lccr3(): - * Convert a bits per pixel value to the correct bit pattern for LCCR3 - */ -static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var) +/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */ +static inline int var_to_depth(struct fb_var_screeninfo *var) { - int ret = 0; + return var->red.length + var->green.length + + var->blue.length + var->transp.length; +} + +/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */ +static int pxafb_var_to_bpp(struct fb_var_screeninfo *var) +{ + int bpp = -EINVAL; + switch (var->bits_per_pixel) { - case 1: ret = LCCR3_1BPP; break; - case 2: ret = LCCR3_2BPP; break; - case 4: ret = LCCR3_4BPP; break; - case 8: ret = LCCR3_8BPP; break; - case 16: ret = LCCR3_16BPP; break; + case 1: bpp = 0; break; + case 2: bpp = 1; break; + case 4: bpp = 2; break; + case 8: bpp = 3; break; + case 16: bpp = 4; break; case 24: - switch (var->red.length + var->green.length + - var->blue.length + var->transp.length) { - case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break; - case 19: ret = LCCR3_19BPP_P; break; + switch (var_to_depth(var)) { + case 18: bpp = 6; break; /* 18-bits/pixel packed */ + case 19: bpp = 8; break; /* 19-bits/pixel packed */ + case 24: bpp = 9; break; } break; case 32: - switch (var->red.length + var->green.length + - var->blue.length + var->transp.length) { - case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break; - case 19: ret = LCCR3_19BPP; break; - case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break; - case 25: ret = LCCR3_25BPP; break; + switch (var_to_depth(var)) { + case 18: bpp = 5; break; /* 18-bits/pixel unpacked */ + case 19: bpp = 7; break; /* 19-bits/pixel unpacked */ + case 25: bpp = 10; break; } break; } - return ret; + return bpp; +} + +/* + * pxafb_var_to_lccr3(): + * Convert a bits per pixel value to the correct bit pattern for LCCR3 + * + * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an + * implication of the acutal use of transparency bit, which we handle it + * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel + * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP. + * + * Transparency for palette pixel formats is not supported at the moment. + */ +static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var) +{ + int bpp = pxafb_var_to_bpp(var); + uint32_t lccr3; + + if (bpp < 0) + return 0; + + lccr3 = LCCR3_BPP(bpp); + + switch (var_to_depth(var)) { + case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break; + case 18: lccr3 |= LCCR3_PDFOR_3; break; + case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3; + break; + case 19: + case 25: lccr3 |= LCCR3_PDFOR_0; break; + } + return lccr3; +} + +#define SET_PIXFMT(v, r, g, b, t) \ +({ \ + (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \ + (v)->transp.length = (t) ? (t) : 0; \ + (v)->blue.length = (b); (v)->blue.offset = 0; \ + (v)->green.length = (g); (v)->green.offset = (b); \ + (v)->red.length = (r); (v)->red.offset = (b) + (g); \ +}) + +/* set the RGBT bitfields of fb_var_screeninf according to + * var->bits_per_pixel and given depth + */ +static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth) +{ + if (depth == 0) + depth = var->bits_per_pixel; + + if (var->bits_per_pixel < 16) { + /* indexed pixel formats */ + var->red.offset = 0; var->red.length = 8; + var->green.offset = 0; var->green.length = 8; + var->blue.offset = 0; var->blue.length = 8; + var->transp.offset = 0; var->transp.length = 8; + } + + switch (depth) { + case 16: var->transp.length ? + SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */ + SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */ + case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */ + case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */ + case 24: var->transp.length ? + SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */ + SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */ + case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */ + } } #ifdef CONFIG_CPU_FREQ @@ -308,8 +398,49 @@ static void pxafb_setmode(struct fb_var_screeninfo *var, var->lower_margin = mode->lower_margin; var->sync = mode->sync; var->grayscale = mode->cmap_greyscale; - var->xres_virtual = var->xres; - var->yres_virtual = var->yres; + + /* set the initial RGBA bitfields */ + pxafb_set_pixfmt(var, mode->depth); +} + +static int pxafb_adjust_timing(struct pxafb_info *fbi, + struct fb_var_screeninfo *var) +{ + int line_length; + + var->xres = max_t(int, var->xres, MIN_XRES); + var->yres = max_t(int, var->yres, MIN_YRES); + + if (!(fbi->lccr0 & LCCR0_LCDT)) { + clamp_val(var->hsync_len, 1, 64); + clamp_val(var->vsync_len, 1, 64); + clamp_val(var->left_margin, 1, 255); + clamp_val(var->right_margin, 1, 255); + clamp_val(var->upper_margin, 1, 255); + clamp_val(var->lower_margin, 1, 255); + } + + /* make sure each line is aligned on word boundary */ + line_length = var->xres * var->bits_per_pixel / 8; + line_length = ALIGN(line_length, 4); + var->xres = line_length * 8 / var->bits_per_pixel; + + /* we don't support xpan, force xres_virtual to be equal to xres */ + var->xres_virtual = var->xres; + + if (var->accel_flags & FB_ACCELF_TEXT) + var->yres_virtual = fbi->fb.fix.smem_len / line_length; + else + var->yres_virtual = max(var->yres_virtual, var->yres); + + /* check for limits */ + if (var->xres > MAX_XRES || var->yres > MAX_YRES) + return -EINVAL; + + if (var->yres > var->yres_virtual) + return -EINVAL; + + return 0; } /* @@ -325,11 +456,7 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { struct pxafb_info *fbi = (struct pxafb_info *)info; struct pxafb_mach_info *inf = fbi->dev->platform_data; - - if (var->xres < MIN_XRES) - var->xres = MIN_XRES; - if (var->yres < MIN_YRES) - var->yres = MIN_YRES; + int err; if (inf->fixed_modes) { struct pxafb_mode_info *mode; @@ -338,74 +465,18 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) if (!mode) return -EINVAL; pxafb_setmode(var, mode); - } else { - if (var->xres > inf->modes->xres) - return -EINVAL; - if (var->yres > inf->modes->yres) - return -EINVAL; - if (var->bits_per_pixel > inf->modes->bpp) - return -EINVAL; } - var->xres_virtual = - max(var->xres_virtual, var->xres); - var->yres_virtual = - max(var->yres_virtual, var->yres); + /* do a test conversion to BPP fields to check the color formats */ + err = pxafb_var_to_bpp(var); + if (err < 0) + return err; - /* - * Setup the RGB parameters for this display. - * - * The pixel packing format is described on page 7-11 of the - * PXA2XX Developer's Manual. - */ - if (var->bits_per_pixel == 16) { - var->red.offset = 11; var->red.length = 5; - var->green.offset = 5; var->green.length = 6; - var->blue.offset = 0; var->blue.length = 5; - var->transp.offset = var->transp.length = 0; - } else if (var->bits_per_pixel > 16) { - struct pxafb_mode_info *mode; + pxafb_set_pixfmt(var, var_to_depth(var)); - mode = pxafb_getmode(inf, var); - if (!mode) - return -EINVAL; - - switch (mode->depth) { - case 18: /* RGB666 */ - var->transp.offset = var->transp.length = 0; - var->red.offset = 12; var->red.length = 6; - var->green.offset = 6; var->green.length = 6; - var->blue.offset = 0; var->blue.length = 6; - break; - case 19: /* RGBT666 */ - var->transp.offset = 18; var->transp.length = 1; - var->red.offset = 12; var->red.length = 6; - var->green.offset = 6; var->green.length = 6; - var->blue.offset = 0; var->blue.length = 6; - break; - case 24: /* RGB888 */ - var->transp.offset = var->transp.length = 0; - var->red.offset = 16; var->red.length = 8; - var->green.offset = 8; var->green.length = 8; - var->blue.offset = 0; var->blue.length = 8; - break; - case 25: /* RGBT888 */ - var->transp.offset = 24; var->transp.length = 1; - var->red.offset = 16; var->red.length = 8; - var->green.offset = 8; var->green.length = 8; - var->blue.offset = 0; var->blue.length = 8; - break; - default: - return -EINVAL; - } - } else { - var->red.offset = var->green.offset = 0; - var->blue.offset = var->transp.offset = 0; - var->red.length = 8; - var->green.length = 8; - var->blue.length = 8; - var->transp.length = 0; - } + err = pxafb_adjust_timing(fbi, var); + if (err) + return err; #ifdef CONFIG_CPU_FREQ pr_debug("pxafb: dma period = %d ps\n", @@ -415,11 +486,6 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) return 0; } -static inline void pxafb_set_truecolor(u_int is_true_color) -{ - /* do your machine-specific setup if needed */ -} - /* * pxafb_set_par(): * Set the user defined part of the display for the specified console @@ -452,11 +518,6 @@ static int pxafb_set_par(struct fb_info *info) fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0]; - /* - * Set (any) board control register to handle new color depth - */ - pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR); - if (fbi->fb.var.bits_per_pixel >= 16) fb_dealloc_cmap(&fbi->fb.cmap); else @@ -467,6 +528,24 @@ static int pxafb_set_par(struct fb_info *info) return 0; } +static int pxafb_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct pxafb_info *fbi = (struct pxafb_info *)info; + int dma = DMA_MAX + DMA_BASE; + + if (fbi->state != C_ENABLE) + return 0; + + setup_base_frame(fbi, 1); + + if (fbi->lccr0 & LCCR0_SDS) + lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1); + + lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1); + return 0; +} + /* * pxafb_blank(): * Blank the display by setting all palette values to zero. Note, the @@ -502,32 +581,342 @@ static int pxafb_blank(int blank, struct fb_info *info) return 0; } -static int pxafb_mmap(struct fb_info *info, - struct vm_area_struct *vma) -{ - struct pxafb_info *fbi = (struct pxafb_info *)info; - unsigned long off = vma->vm_pgoff << PAGE_SHIFT; - - if (off < info->fix.smem_len) { - vma->vm_pgoff += fbi->video_offset / PAGE_SIZE; - return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu, - fbi->map_dma, fbi->map_size); - } - return -EINVAL; -} - static struct fb_ops pxafb_ops = { .owner = THIS_MODULE, .fb_check_var = pxafb_check_var, .fb_set_par = pxafb_set_par, + .fb_pan_display = pxafb_pan_display, .fb_setcolreg = pxafb_setcolreg, .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, .fb_imageblit = cfb_imageblit, .fb_blank = pxafb_blank, - .fb_mmap = pxafb_mmap, }; +#ifdef CONFIG_FB_PXA_OVERLAY +static void overlay1fb_setup(struct pxafb_layer *ofb) +{ + int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual; + unsigned long start = ofb->video_mem_phys; + setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size); +} + +/* Depending on the enable status of overlay1/2, the DMA should be + * updated from FDADRx (when disabled) or FBRx (when enabled). + */ +static void overlay1fb_enable(struct pxafb_layer *ofb) +{ + int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN; + uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0); + + lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1); + lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]); + lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN); +} + +static void overlay1fb_disable(struct pxafb_layer *ofb) +{ + uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5); + + lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN); + + lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1)); + lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1)); + lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3); + + if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0) + pr_warning("%s: timeout disabling overlay1\n", __func__); + + lcd_writel(ofb->fbi, LCCR5, lccr5); +} + +static void overlay2fb_setup(struct pxafb_layer *ofb) +{ + int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd); + unsigned long start[3] = { ofb->video_mem_phys, 0, 0 }; + + if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) { + size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual; + setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size); + } else { + size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual; + switch (pfor) { + case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break; + case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break; + case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break; + } + start[1] = start[0] + size; + start[2] = start[1] + size / div; + setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size); + setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div); + setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div); + } +} + +static void overlay2fb_enable(struct pxafb_layer *ofb) +{ + int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd); + int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN; + uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0); + uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0); + uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0); + + if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) + lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2); + else { + lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2); + lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3); + lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4); + } + lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]); + lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN); +} + +static void overlay2fb_disable(struct pxafb_layer *ofb) +{ + uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5); + + lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN); + + lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2)); + lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2)); + lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3); + lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3); + lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3); + + if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0) + pr_warning("%s: timeout disabling overlay2\n", __func__); +} + +static struct pxafb_layer_ops ofb_ops[] = { + [0] = { + .enable = overlay1fb_enable, + .disable = overlay1fb_disable, + .setup = overlay1fb_setup, + }, + [1] = { + .enable = overlay2fb_enable, + .disable = overlay2fb_disable, + .setup = overlay2fb_setup, + }, +}; + +static int overlayfb_open(struct fb_info *info, int user) +{ + struct pxafb_layer *ofb = (struct pxafb_layer *)info; + + /* no support for framebuffer console on overlay */ + if (user == 0) + return -ENODEV; + + /* allow only one user at a time */ + if (atomic_inc_and_test(&ofb->usage)) + return -EBUSY; + + /* unblank the base framebuffer */ + fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK); + return 0; +} + +static int overlayfb_release(struct fb_info *info, int user) +{ + struct pxafb_layer *ofb = (struct pxafb_layer*) info; + + atomic_dec(&ofb->usage); + ofb->ops->disable(ofb); + + free_pages_exact(ofb->video_mem, ofb->video_mem_size); + ofb->video_mem = NULL; + ofb->video_mem_size = 0; + return 0; +} + +static int overlayfb_check_var(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct pxafb_layer *ofb = (struct pxafb_layer *)info; + struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var; + int xpos, ypos, pfor, bpp; + + xpos = NONSTD_TO_XPOS(var->nonstd); + ypos = NONSTD_TO_XPOS(var->nonstd); + pfor = NONSTD_TO_PFOR(var->nonstd); + + bpp = pxafb_var_to_bpp(var); + if (bpp < 0) + return -EINVAL; + + /* no support for YUV format on overlay1 */ + if (ofb->id == OVERLAY1 && pfor != 0) + return -EINVAL; + + /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */ + switch (pfor) { + case OVERLAY_FORMAT_RGB: + bpp = pxafb_var_to_bpp(var); + if (bpp < 0) + return -EINVAL; + + pxafb_set_pixfmt(var, var_to_depth(var)); + break; + case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break; + case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break; + case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break; + case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break; + default: + return -EINVAL; + } + + /* each line must start at a 32-bit word boundary */ + if ((xpos * bpp) % 32) + return -EINVAL; + + /* xres must align on 32-bit word boundary */ + var->xres = roundup(var->xres * bpp, 32) / bpp; + + if ((xpos + var->xres > base_var->xres) || + (ypos + var->yres > base_var->yres)) + return -EINVAL; + + var->xres_virtual = var->xres; + var->yres_virtual = max(var->yres, var->yres_virtual); + return 0; +} + +static int overlayfb_map_video_memory(struct pxafb_layer *ofb) +{ + struct fb_var_screeninfo *var = &ofb->fb.var; + int pfor = NONSTD_TO_PFOR(var->nonstd); + int size, bpp = 0; + + switch (pfor) { + case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break; + case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break; + case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break; + case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break; + case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break; + } + + ofb->fb.fix.line_length = var->xres_virtual * bpp / 8; + + size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual); + + /* don't re-allocate if the original video memory is enough */ + if (ofb->video_mem) { + if (ofb->video_mem_size >= size) + return 0; + + free_pages_exact(ofb->video_mem, ofb->video_mem_size); + } + + ofb->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO); + if (ofb->video_mem == NULL) + return -ENOMEM; + + ofb->video_mem_phys = virt_to_phys(ofb->video_mem); + ofb->video_mem_size = size; + + ofb->fb.fix.smem_start = ofb->video_mem_phys; + ofb->fb.fix.smem_len = ofb->fb.fix.line_length * var->yres_virtual; + ofb->fb.screen_base = ofb->video_mem; + return 0; +} + +static int overlayfb_set_par(struct fb_info *info) +{ + struct pxafb_layer *ofb = (struct pxafb_layer *)info; + struct fb_var_screeninfo *var = &info->var; + int xpos, ypos, pfor, bpp, ret; + + ret = overlayfb_map_video_memory(ofb); + if (ret) + return ret; + + bpp = pxafb_var_to_bpp(var); + xpos = NONSTD_TO_XPOS(var->nonstd); + ypos = NONSTD_TO_XPOS(var->nonstd); + pfor = NONSTD_TO_PFOR(var->nonstd); + + ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) | + OVLxC1_BPP(bpp); + ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos); + + if (ofb->id == OVERLAY2) + ofb->control[1] |= OVL2C2_PFOR(pfor); + + ofb->ops->setup(ofb); + ofb->ops->enable(ofb); + return 0; +} + +static struct fb_ops overlay_fb_ops = { + .owner = THIS_MODULE, + .fb_open = overlayfb_open, + .fb_release = overlayfb_release, + .fb_check_var = overlayfb_check_var, + .fb_set_par = overlayfb_set_par, +}; + +static void __devinit init_pxafb_overlay(struct pxafb_info *fbi, + struct pxafb_layer *ofb, int id) +{ + sprintf(ofb->fb.fix.id, "overlay%d", id + 1); + + ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS; + ofb->fb.fix.xpanstep = 0; + ofb->fb.fix.ypanstep = 1; + + ofb->fb.var.activate = FB_ACTIVATE_NOW; + ofb->fb.var.height = -1; + ofb->fb.var.width = -1; + ofb->fb.var.vmode = FB_VMODE_NONINTERLACED; + + ofb->fb.fbops = &overlay_fb_ops; + ofb->fb.flags = FBINFO_FLAG_DEFAULT; + ofb->fb.node = -1; + ofb->fb.pseudo_palette = NULL; + + ofb->id = id; + ofb->ops = &ofb_ops[id]; + atomic_set(&ofb->usage, 0); + ofb->fbi = fbi; + init_completion(&ofb->branch_done); +} + +static int __devinit pxafb_overlay_init(struct pxafb_info *fbi) +{ + int i, ret; + + for (i = 0; i < 2; i++) { + init_pxafb_overlay(fbi, &fbi->overlay[i], i); + ret = register_framebuffer(&fbi->overlay[i].fb); + if (ret) { + dev_err(fbi->dev, "failed to register overlay %d\n", i); + return ret; + } + } + + /* mask all IU/BS/EOF/SOF interrupts */ + lcd_writel(fbi, LCCR5, ~0); + + /* place overlay(s) on top of base */ + fbi->lccr0 |= LCCR0_OUC; + pr_info("PXA Overlay driver loaded successfully!\n"); + return 0; +} + +static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi) +{ + int i; + + for (i = 0; i < 2; i++) + unregister_framebuffer(&fbi->overlay[i].fb); +} +#else +static inline void pxafb_overlay_init(struct pxafb_info *fbi) {} +static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {} +#endif /* CONFIG_FB_PXA_OVERLAY */ + /* * Calculate the PCD value from the clock rate (in picoseconds). * We take account of the PPCR clock setting. @@ -607,22 +996,22 @@ unsigned long pxafb_get_hsync_time(struct device *dev) EXPORT_SYMBOL(pxafb_get_hsync_time); static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, - unsigned int offset, size_t size) + unsigned long start, size_t size) { struct pxafb_dma_descriptor *dma_desc, *pal_desc; unsigned int dma_desc_off, pal_desc_off; - if (dma < 0 || dma >= DMA_MAX) + if (dma < 0 || dma >= DMA_MAX * 2) return -EINVAL; dma_desc = &fbi->dma_buff->dma_desc[dma]; dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]); - dma_desc->fsadr = fbi->screen_dma + offset; + dma_desc->fsadr = start; dma_desc->fidr = 0; dma_desc->ldcmd = size; - if (pal < 0 || pal >= PAL_MAX) { + if (pal < 0 || pal >= PAL_MAX * 2) { dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; } else { @@ -648,6 +1037,27 @@ static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, return 0; } +static void setup_base_frame(struct pxafb_info *fbi, int branch) +{ + struct fb_var_screeninfo *var = &fbi->fb.var; + struct fb_fix_screeninfo *fix = &fbi->fb.fix; + int nbytes, dma, pal, bpp = var->bits_per_pixel; + unsigned long offset; + + dma = DMA_BASE + (branch ? DMA_MAX : 0); + pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0); + + nbytes = fix->line_length * var->yres; + offset = fix->line_length * var->yoffset + fbi->video_mem_phys; + + if (fbi->lccr0 & LCCR0_SDS) { + nbytes = nbytes / 2; + setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes); + } + + setup_frame_dma(fbi, dma, pal, offset, nbytes); +} + #ifdef CONFIG_FB_PXA_SMARTPANEL static int setup_smart_dma(struct pxafb_info *fbi) { @@ -701,6 +1111,7 @@ int pxafb_smart_flush(struct fb_info *info) lcd_writel(fbi, LCCR1, fbi->reg_lccr1); lcd_writel(fbi, LCCR2, fbi->reg_lccr2); lcd_writel(fbi, LCCR3, fbi->reg_lccr3); + lcd_writel(fbi, LCCR4, fbi->reg_lccr4); lcd_writel(fbi, FDADR0, fbi->fdadr[0]); lcd_writel(fbi, FDADR6, fbi->fdadr[6]); @@ -727,12 +1138,19 @@ int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds) int i; struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb); - /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */ - for (i = 0; i < n_cmds; i++) { + for (i = 0; i < n_cmds; i++, cmds++) { + /* if it is a software delay, flush and delay */ + if ((*cmds & 0xff00) == SMART_CMD_DELAY) { + pxafb_smart_flush(info); + mdelay(*cmds & 0xff); + continue; + } + + /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */ if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8) pxafb_smart_flush(info); - fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++; + fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds; } return 0; @@ -764,7 +1182,9 @@ static void setup_smart_timing(struct pxafb_info *fbi, LCCR1_HorSnchWdth(__smart_timing(t3, lclk)); fbi->reg_lccr2 = LCCR2_DisHght(var->yres); - fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk)); + fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk)); + fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0; + fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0; /* FIXME: make this configurable */ fbi->reg_cmdcr = 1; @@ -789,11 +1209,15 @@ static int pxafb_smart_thread(void *arg) if (try_to_freeze()) continue; + mutex_lock(&fbi->ctrlr_lock); + if (fbi->state == C_ENABLE) { inf->smart_update(&fbi->fb); complete(&fbi->refresh_done); } + mutex_unlock(&fbi->ctrlr_lock); + set_current_state(TASK_INTERRUPTIBLE); schedule_timeout(30 * HZ / 1000); } @@ -804,16 +1228,22 @@ static int pxafb_smart_thread(void *arg) static int pxafb_smart_init(struct pxafb_info *fbi) { - if (!(fbi->lccr0 | LCCR0_LCDT)) + if (!(fbi->lccr0 & LCCR0_LCDT)) return 0; + fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff; + fbi->n_smart_cmds = 0; + + init_completion(&fbi->command_done); + init_completion(&fbi->refresh_done); + fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi, "lcd_refresh"); if (IS_ERR(fbi->smart_thread)) { - printk(KERN_ERR "%s: unable to create kernel thread\n", - __func__); + pr_err("%s: unable to create kernel thread\n", __func__); return PTR_ERR(fbi->smart_thread); } + return 0; } #else @@ -826,7 +1256,9 @@ int pxafb_smart_flush(struct fb_info *info) { return 0; } -#endif /* CONFIG_FB_SMART_PANEL */ + +static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; } +#endif /* CONFIG_FB_PXA_SMARTPANEL */ static void setup_parallel_timing(struct pxafb_info *fbi, struct fb_var_screeninfo *var) @@ -874,51 +1306,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi) { u_long flags; - size_t nbytes; - -#if DEBUG_VAR - if (!(fbi->lccr0 & LCCR0_LCDT)) { - if (var->xres < 16 || var->xres > 1024) - printk(KERN_ERR "%s: invalid xres %d\n", - fbi->fb.fix.id, var->xres); - switch (var->bits_per_pixel) { - case 1: - case 2: - case 4: - case 8: - case 16: - case 24: - case 32: - break; - default: - printk(KERN_ERR "%s: invalid bit depth %d\n", - fbi->fb.fix.id, var->bits_per_pixel); - break; - } - if (var->hsync_len < 1 || var->hsync_len > 64) - printk(KERN_ERR "%s: invalid hsync_len %d\n", - fbi->fb.fix.id, var->hsync_len); - if (var->left_margin < 1 || var->left_margin > 255) - printk(KERN_ERR "%s: invalid left_margin %d\n", - fbi->fb.fix.id, var->left_margin); - if (var->right_margin < 1 || var->right_margin > 255) - printk(KERN_ERR "%s: invalid right_margin %d\n", - fbi->fb.fix.id, var->right_margin); - if (var->yres < 1 || var->yres > 1024) - printk(KERN_ERR "%s: invalid yres %d\n", - fbi->fb.fix.id, var->yres); - if (var->vsync_len < 1 || var->vsync_len > 64) - printk(KERN_ERR "%s: invalid vsync_len %d\n", - fbi->fb.fix.id, var->vsync_len); - if (var->upper_margin < 0 || var->upper_margin > 255) - printk(KERN_ERR "%s: invalid upper_margin %d\n", - fbi->fb.fix.id, var->upper_margin); - if (var->lower_margin < 0 || var->lower_margin > 255) - printk(KERN_ERR "%s: invalid lower_margin %d\n", - fbi->fb.fix.id, var->lower_margin); - } -#endif /* Update shadow copy atomically */ local_irq_save(flags); @@ -929,23 +1317,13 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var, #endif setup_parallel_timing(fbi, var); + setup_base_frame(fbi, 0); + fbi->reg_lccr0 = fbi->lccr0 | (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | LCCR0_QDM | LCCR0_BM | LCCR0_OUM); - fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var); - - nbytes = var->yres * fbi->fb.fix.line_length; - - if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) { - nbytes = nbytes / 2; - setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes); - } - - if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT)) - setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes); - else - setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes); + fbi->reg_lccr3 |= pxafb_var_to_lccr3(var); fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK; fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK); @@ -959,6 +1337,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var, (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) || (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) || (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) || + (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) || (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) || (lcd_readl(fbi, FDADR1) != fbi->fdadr[1])) pxafb_schedule_work(fbi, C_REENABLE); @@ -976,67 +1355,16 @@ static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on) { pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff"); - if (pxafb_backlight_power) - pxafb_backlight_power(on); + if (fbi->backlight_power) + fbi->backlight_power(on); } static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) { pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff"); - if (pxafb_lcd_power) - pxafb_lcd_power(on, &fbi->fb.var); -} - -static void pxafb_setup_gpio(struct pxafb_info *fbi) -{ - int gpio, ldd_bits; - unsigned int lccr0 = fbi->lccr0; - - /* - * setup is based on type of panel supported - */ - - /* 4 bit interface */ - if ((lccr0 & LCCR0_CMS) == LCCR0_Mono && - (lccr0 & LCCR0_SDS) == LCCR0_Sngl && - (lccr0 & LCCR0_DPD) == LCCR0_4PixMono) - ldd_bits = 4; - - /* 8 bit interface */ - else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono && - ((lccr0 & LCCR0_SDS) == LCCR0_Dual || - (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) || - ((lccr0 & LCCR0_CMS) == LCCR0_Color && - (lccr0 & LCCR0_PAS) == LCCR0_Pas && - (lccr0 & LCCR0_SDS) == LCCR0_Sngl)) - ldd_bits = 8; - - /* 16 bit interface */ - else if ((lccr0 & LCCR0_CMS) == LCCR0_Color && - ((lccr0 & LCCR0_SDS) == LCCR0_Dual || - (lccr0 & LCCR0_PAS) == LCCR0_Act)) - ldd_bits = 16; - - else { - printk(KERN_ERR "pxafb_setup_gpio: unable to determine " - "bits per pixel\n"); - return; - } - - for (gpio = 58; ldd_bits; gpio++, ldd_bits--) - pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT); - /* 18 bit interface */ - if (fbi->fb.var.bits_per_pixel > 16) { - pxa_gpio_mode(86 | GPIO_ALT_FN_2_OUT); - pxa_gpio_mode(87 | GPIO_ALT_FN_2_OUT); - } - pxa_gpio_mode(GPIO74_LCD_FCLK_MD); - pxa_gpio_mode(GPIO75_LCD_LCLK_MD); - pxa_gpio_mode(GPIO76_LCD_PCLK_MD); - - if ((lccr0 & LCCR0_PAS) == 0) - pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD); + if (fbi->lcd_power) + fbi->lcd_power(on, &fbi->fb.var); } static void pxafb_enable_controller(struct pxafb_info *fbi) @@ -1056,6 +1384,7 @@ static void pxafb_enable_controller(struct pxafb_info *fbi) return; /* Sequence from 11.7.10 */ + lcd_writel(fbi, LCCR4, fbi->reg_lccr4); lcd_writel(fbi, LCCR3, fbi->reg_lccr3); lcd_writel(fbi, LCCR2, fbi->reg_lccr2); lcd_writel(fbi, LCCR1, fbi->reg_lccr1); @@ -1097,8 +1426,9 @@ static void pxafb_disable_controller(struct pxafb_info *fbi) static irqreturn_t pxafb_handle_irq(int irq, void *dev_id) { struct pxafb_info *fbi = dev_id; - unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR); + unsigned int lccr0, lcsr, lcsr1; + lcsr = lcd_readl(fbi, LCSR); if (lcsr & LCSR_LDD) { lccr0 = lcd_readl(fbi, LCCR0); lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM); @@ -1109,8 +1439,18 @@ static irqreturn_t pxafb_handle_irq(int irq, void *dev_id) if (lcsr & LCSR_CMD_INT) complete(&fbi->command_done); #endif - lcd_writel(fbi, LCSR, lcsr); + +#ifdef CONFIG_FB_PXA_OVERLAY + lcsr1 = lcd_readl(fbi, LCSR1); + if (lcsr1 & LCSR1_BS(1)) + complete(&fbi->overlay[0].branch_done); + + if (lcsr1 & LCSR1_BS(2)) + complete(&fbi->overlay[1].branch_done); + + lcd_writel(fbi, LCSR1, lcsr1); +#endif return IRQ_HANDLED; } @@ -1181,7 +1521,6 @@ static void set_ctrlr_state(struct pxafb_info *fbi, u_int state) if (old_state == C_ENABLE) { __pxafb_lcd_power(fbi, 0); pxafb_disable_controller(fbi); - pxafb_setup_gpio(fbi); pxafb_enable_controller(fbi); __pxafb_lcd_power(fbi, 1); } @@ -1204,7 +1543,6 @@ static void set_ctrlr_state(struct pxafb_info *fbi, u_int state) */ if (old_state != C_ENABLE) { fbi->state = C_ENABLE; - pxafb_setup_gpio(fbi); pxafb_enable_controller(fbi); __pxafb_lcd_power(fbi, 1); __pxafb_backlight_power(fbi, 1); @@ -1303,77 +1641,34 @@ static int pxafb_resume(struct platform_device *dev) #define pxafb_resume NULL #endif -/* - * pxafb_map_video_memory(): - * Allocates the DRAM memory for the frame buffer. This buffer is - * remapped into a non-cached, non-buffered, memory region to - * allow palette and pixel writes to occur without flushing the - * cache. Once this area is remapped, all virtual memory - * access to the video memory should occur at the new region. - */ -static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi) +static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi) { - /* - * We reserve one page for the palette, plus the size - * of the framebuffer. - */ - fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff)); - fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset); - fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size, - &fbi->map_dma, GFP_KERNEL); - - if (fbi->map_cpu) { - /* prevent initial garbage on screen */ - memset(fbi->map_cpu, 0, fbi->map_size); - fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset; - fbi->screen_dma = fbi->map_dma + fbi->video_offset; - - /* - * FIXME: this is actually the wrong thing to place in - * smem_start. But fbdev suffers from the problem that - * it needs an API which doesn't exist (in this case, - * dma_writecombine_mmap) - */ - fbi->fb.fix.smem_start = fbi->screen_dma; - fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16; - - fbi->dma_buff = (void *) fbi->map_cpu; - fbi->dma_buff_phys = fbi->map_dma; - fbi->palette_cpu = (u16 *) fbi->dma_buff->palette; + int size = PAGE_ALIGN(fbi->video_mem_size); - pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16)); + fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO); + if (fbi->video_mem == NULL) + return -ENOMEM; -#ifdef CONFIG_FB_PXA_SMARTPANEL - fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff; - fbi->n_smart_cmds = 0; -#endif - } - - return fbi->map_cpu ? 0 : -ENOMEM; -} + fbi->video_mem_phys = virt_to_phys(fbi->video_mem); + fbi->video_mem_size = size; -static void pxafb_decode_mode_info(struct pxafb_info *fbi, - struct pxafb_mode_info *modes, - unsigned int num_modes) -{ - unsigned int i, smemlen; - - pxafb_setmode(&fbi->fb.var, &modes[0]); + fbi->fb.fix.smem_start = fbi->video_mem_phys; + fbi->fb.fix.smem_len = fbi->video_mem_size; + fbi->fb.screen_base = fbi->video_mem; - for (i = 0; i < num_modes; i++) { - smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8; - if (smemlen > fbi->fb.fix.smem_len) - fbi->fb.fix.smem_len = smemlen; - } + return fbi->video_mem ? 0 : -ENOMEM; } static void pxafb_decode_mach_info(struct pxafb_info *fbi, struct pxafb_mach_info *inf) { unsigned int lcd_conn = inf->lcd_conn; + struct pxafb_mode_info *m; + int i; fbi->cmap_inverse = inf->cmap_inverse; fbi->cmap_static = inf->cmap_static; + fbi->lccr4 = inf->lccr4; switch (lcd_conn & LCD_TYPE_MASK) { case LCD_TYPE_MONO_STN: @@ -1398,7 +1693,6 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi, /* fall back to backward compatibility way */ fbi->lccr0 = inf->lccr0; fbi->lccr3 = inf->lccr3; - fbi->lccr4 = inf->lccr4; goto decode_mode; } @@ -1412,7 +1706,22 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi, fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0; decode_mode: - pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes); + pxafb_setmode(&fbi->fb.var, &inf->modes[0]); + + /* decide video memory size as follows: + * 1. default to mode of maximum resolution + * 2. allow platform to override + * 3. allow module parameter to override + */ + for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++) + fbi->video_mem_size = max_t(size_t, fbi->video_mem_size, + m->xres * m->yres * m->bpp / 8); + + if (inf->video_mem_size > fbi->video_mem_size) + fbi->video_mem_size = inf->video_mem_size; + + if (video_mem_size > fbi->video_mem_size) + fbi->video_mem_size = video_mem_size; } static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev) @@ -1429,7 +1738,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev) memset(fbi, 0, sizeof(struct pxafb_info)); fbi->dev = dev; - fbi->clk = clk_get(dev, "LCDCLK"); + fbi->clk = clk_get(dev, NULL); if (IS_ERR(fbi->clk)) { kfree(fbi); return NULL; @@ -1440,7 +1749,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev) fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; fbi->fb.fix.type_aux = 0; fbi->fb.fix.xpanstep = 0; - fbi->fb.fix.ypanstep = 0; + fbi->fb.fix.ypanstep = 1; fbi->fb.fix.ywrapstep = 0; fbi->fb.fix.accel = FB_ACCEL_NONE; @@ -1448,7 +1757,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev) fbi->fb.var.activate = FB_ACTIVATE_NOW; fbi->fb.var.height = -1; fbi->fb.var.width = -1; - fbi->fb.var.accel_flags = 0; + fbi->fb.var.accel_flags = FB_ACCELF_TEXT; fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; fbi->fb.fbops = &pxafb_ops; @@ -1468,10 +1777,6 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev) INIT_WORK(&fbi->task, pxafb_task); mutex_init(&fbi->ctrlr_lock); init_completion(&fbi->disable_done); -#ifdef CONFIG_FB_PXA_SMARTPANEL - init_completion(&fbi->command_done); - init_completion(&fbi->refresh_done); -#endif return fbi; } @@ -1544,7 +1849,9 @@ static int __devinit parse_opt(struct device *dev, char *this_opt) s[0] = '\0'; - if (!strncmp(this_opt, "mode:", 5)) { + if (!strncmp(this_opt, "vmem:", 5)) { + video_mem_size = memparse(this_opt + 5, NULL); + } else if (!strncmp(this_opt, "mode:", 5)) { return parse_opt_mode(dev, this_opt); } else if (!strncmp(this_opt, "pixclock:", 9)) { mode->pixclock = simple_strtoul(this_opt+9, NULL, 0); @@ -1748,8 +2055,7 @@ static int __devinit pxafb_probe(struct platform_device *dev) ret = -EINVAL; goto failed; } - pxafb_backlight_power = inf->pxafb_backlight_power; - pxafb_lcd_power = inf->pxafb_lcd_power; + fbi = pxafb_init_fbinfo(&dev->dev); if (!fbi) { /* only reason for pxafb_init_fbinfo to fail is kmalloc */ @@ -1758,6 +2064,9 @@ static int __devinit pxafb_probe(struct platform_device *dev) goto failed; } + fbi->backlight_power = inf->pxafb_backlight_power; + fbi->lcd_power = inf->pxafb_lcd_power; + r = platform_get_resource(dev, IORESOURCE_MEM, 0); if (r == NULL) { dev_err(&dev->dev, "no I/O memory resource defined\n"); @@ -1779,12 +2088,20 @@ static int __devinit pxafb_probe(struct platform_device *dev) goto failed_free_res; } - /* Initialize video memory */ - ret = pxafb_map_video_memory(fbi); + fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff)); + fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size, + &fbi->dma_buff_phys, GFP_KERNEL); + if (fbi->dma_buff == NULL) { + dev_err(&dev->dev, "failed to allocate memory for DMA\n"); + ret = -ENOMEM; + goto failed_free_io; + } + + ret = pxafb_init_video_memory(fbi); if (ret) { dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret); ret = -ENOMEM; - goto failed_free_io; + goto failed_free_dma; } irq = platform_get_irq(dev, 0); @@ -1801,13 +2118,12 @@ static int __devinit pxafb_probe(struct platform_device *dev) goto failed_free_mem; } -#ifdef CONFIG_FB_PXA_SMARTPANEL ret = pxafb_smart_init(fbi); if (ret) { dev_err(&dev->dev, "failed to initialize smartpanel\n"); goto failed_free_irq; } -#endif + /* * This makes sure that our colour bitfield * descriptors are correctly initialised. @@ -1833,6 +2149,8 @@ static int __devinit pxafb_probe(struct platform_device *dev) goto failed_free_cmap; } + pxafb_overlay_init(fbi); + #ifdef CONFIG_CPU_FREQ fbi->freq_transition.notifier_call = pxafb_freq_transition; fbi->freq_policy.notifier_call = pxafb_freq_policy; @@ -1855,8 +2173,10 @@ failed_free_cmap: failed_free_irq: free_irq(irq, fbi); failed_free_mem: - dma_free_writecombine(&dev->dev, fbi->map_size, - fbi->map_cpu, fbi->map_dma); + free_pages_exact(fbi->video_mem, fbi->video_mem_size); +failed_free_dma: + dma_free_coherent(&dev->dev, fbi->dma_buff_size, + fbi->dma_buff, fbi->dma_buff_phys); failed_free_io: iounmap(fbi->mmio_base); failed_free_res: @@ -1881,6 +2201,7 @@ static int __devexit pxafb_remove(struct platform_device *dev) info = &fbi->fb; + pxafb_overlay_exit(fbi); unregister_framebuffer(info); pxafb_disable_controller(fbi); @@ -1891,8 +2212,10 @@ static int __devexit pxafb_remove(struct platform_device *dev) irq = platform_get_irq(dev, 0); free_irq(irq, fbi); - dma_free_writecombine(&dev->dev, fbi->map_size, - fbi->map_cpu, fbi->map_dma); + free_pages_exact(fbi->video_mem, fbi->video_mem_size); + + dma_free_writecombine(&dev->dev, fbi->dma_buff_size, + fbi->dma_buff, fbi->dma_buff_phys); iounmap(fbi->mmio_base); diff --git a/drivers/video/pxafb.h b/drivers/video/pxafb.h index 31541b8..2353521 100644 --- a/drivers/video/pxafb.h +++ b/drivers/video/pxafb.h @@ -54,11 +54,55 @@ enum { #define PALETTE_SIZE (256 * 4) #define CMD_BUFF_SIZE (1024 * 50) +/* NOTE: the palette and frame dma descriptors are doubled to allow + * the 2nd set for branch settings (FBRx) + */ struct pxafb_dma_buff { unsigned char palette[PAL_MAX * PALETTE_SIZE]; uint16_t cmd_buff[CMD_BUFF_SIZE]; - struct pxafb_dma_descriptor pal_desc[PAL_MAX]; - struct pxafb_dma_descriptor dma_desc[DMA_MAX]; + struct pxafb_dma_descriptor pal_desc[PAL_MAX * 2]; + struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2]; +}; + +enum { + OVERLAY1, + OVERLAY2, +}; + +enum { + OVERLAY_FORMAT_RGB = 0, + OVERLAY_FORMAT_YUV444_PACKED, + OVERLAY_FORMAT_YUV444_PLANAR, + OVERLAY_FORMAT_YUV422_PLANAR, + OVERLAY_FORMAT_YUV420_PLANAR, +}; + +#define NONSTD_TO_XPOS(x) (((x) >> 0) & 0x3ff) +#define NONSTD_TO_YPOS(x) (((x) >> 10) & 0x3ff) +#define NONSTD_TO_PFOR(x) (((x) >> 20) & 0x7) + +struct pxafb_layer; + +struct pxafb_layer_ops { + void (*enable)(struct pxafb_layer *); + void (*disable)(struct pxafb_layer *); + void (*setup)(struct pxafb_layer *); +}; + +struct pxafb_layer { + struct fb_info fb; + int id; + atomic_t usage; + uint32_t control[2]; + + struct pxafb_layer_ops *ops; + + void __iomem *video_mem; + unsigned long video_mem_phys; + size_t video_mem_size; + struct completion branch_done; + + struct pxafb_info *fbi; }; struct pxafb_info { @@ -69,24 +113,15 @@ struct pxafb_info { void __iomem *mmio_base; struct pxafb_dma_buff *dma_buff; + size_t dma_buff_size; dma_addr_t dma_buff_phys; - dma_addr_t fdadr[DMA_MAX]; - - /* - * These are the addresses we mapped - * the framebuffer memory region to. - */ - /* raw memory addresses */ - dma_addr_t map_dma; /* physical */ - u_char * map_cpu; /* virtual */ - u_int map_size; - - /* addresses of pieces placed in raw buffer */ - u_char * screen_cpu; /* virtual address of frame buffer */ - dma_addr_t screen_dma; /* physical address of frame buffer */ + dma_addr_t fdadr[DMA_MAX * 2]; + + void __iomem *video_mem; /* virtual address of frame buffer */ + unsigned long video_mem_phys; /* physical address of frame buffer */ + size_t video_mem_size; /* size of the frame buffer */ u16 * palette_cpu; /* virtual address of palette memory */ u_int palette_size; - ssize_t video_offset; u_int lccr0; u_int lccr3; @@ -120,10 +155,17 @@ struct pxafb_info { struct task_struct *smart_thread; #endif +#ifdef CONFIG_FB_PXA_OVERLAY + struct pxafb_layer overlay[2]; +#endif + #ifdef CONFIG_CPU_FREQ struct notifier_block freq_transition; struct notifier_block freq_policy; #endif + + void (*lcd_power)(int, struct fb_var_screeninfo *); + void (*backlight_power)(int); }; #define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member) @@ -148,4 +190,10 @@ struct pxafb_info { #define MIN_XRES 64 #define MIN_YRES 64 +/* maximum X and Y resolutions - note these are limits from the register + * bits length instead of the real ones + */ +#define MAX_XRES 1024 +#define MAX_YRES 1024 + #endif /* __PXAFB_H__ */ diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c index c052bd4..076f946 100644 --- a/drivers/video/sa1100fb.c +++ b/drivers/video/sa1100fb.c @@ -114,7 +114,7 @@ * - convert dma address types to dma_addr_t * - remove unused 'montype' stuff * - remove redundant zero inits of init_var after the initial - * memzero. + * memset. * - remove allow_modeset (acornfb idea does not belong here) * * 2001/05/28: <rmk@arm.linux.org.uk> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index f7f6ce8..e31925e 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -42,7 +42,7 @@ #undef S3C_VA_WATCHDOG #define S3C_VA_WATCHDOG (0) -#include <asm/plat-s3c/regs-watchdog.h> +#include <plat/regs-watchdog.h> #define PFX "s3c2410-wdt: " diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c index ed01e4c..e19b457 100644 --- a/drivers/watchdog/sa1100_wdt.c +++ b/drivers/watchdog/sa1100_wdt.c @@ -27,6 +27,7 @@ #include <linux/init.h> #include <linux/bitops.h> #include <linux/uaccess.h> +#include <linux/timex.h> #ifdef CONFIG_ARCH_PXA #include <mach/pxa-regs.h> @@ -35,8 +36,7 @@ #include <mach/reset.h> #include <mach/hardware.h> -#define OSCR_FREQ CLOCK_TICK_RATE - +static unsigned long oscr_freq; static unsigned long sa1100wdt_users; static int pre_margin; static int boot_status; @@ -123,12 +123,12 @@ static long sa1100dog_ioctl(struct file *file, unsigned int cmd, break; } - pre_margin = OSCR_FREQ * time; + pre_margin = oscr_freq * time; OSMR3 = OSCR + pre_margin; /*fall through*/ case WDIOC_GETTIMEOUT: - ret = put_user(pre_margin / OSCR_FREQ, p); + ret = put_user(pre_margin / oscr_freq, p); break; } return ret; @@ -155,6 +155,8 @@ static int __init sa1100dog_init(void) { int ret; + oscr_freq = get_clock_tick_rate(); + /* * Read the reset status, and save it for later. If * we suspend, RCSR will be cleared, and the watchdog @@ -162,7 +164,7 @@ static int __init sa1100dog_init(void) */ boot_status = (reset_status & RESET_STATUS_WATCHDOG) ? WDIOF_CARDRESET : 0; - pre_margin = OSCR_FREQ * margin; + pre_margin = oscr_freq * margin; ret = misc_register(&sa1100dog_miscdev); if (ret == 0) diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index 4e4f127..feb3b93 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -158,6 +158,8 @@ /* SH-SCI */ #define PORT_SCIFA 83 +#define PORT_S3C6400 84 + #ifdef __KERNEL__ #include <linux/compiler.h> diff --git a/sound/arm/pxa2xx-ac97-lib.c b/sound/arm/pxa2xx-ac97-lib.c index 34c1d94..ef6539e 100644 --- a/sound/arm/pxa2xx-ac97-lib.c +++ b/sound/arm/pxa2xx-ac97-lib.c @@ -22,7 +22,7 @@ #include <asm/irq.h> #include <mach/hardware.h> -#include <mach/pxa-regs.h> +#include <mach/regs-ac97.h> #include <mach/pxa2xx-gpio.h> #include <mach/audio.h> diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c index c2635be..85cf591 100644 --- a/sound/arm/pxa2xx-ac97.c +++ b/sound/arm/pxa2xx-ac97.c @@ -22,6 +22,7 @@ #include <mach/hardware.h> #include <mach/pxa-regs.h> +#include <mach/regs-ac97.h> #include <mach/audio.h> #include "pxa2xx-pcm.h" diff --git a/sound/arm/pxa2xx-pcm.h b/sound/arm/pxa2xx-pcm.h index 5c4a4d3..65f86b5 100644 --- a/sound/arm/pxa2xx-pcm.h +++ b/sound/arm/pxa2xx-pcm.h @@ -9,7 +9,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include <asm/dma.h> +#include <mach/dma.h> struct pxa2xx_runtime_data { int dma_ch; diff --git a/sound/oss/waveartist.c b/sound/oss/waveartist.c index c47842f..2c63bb9 100644 --- a/sound/oss/waveartist.c +++ b/sound/oss/waveartist.c @@ -1483,16 +1483,14 @@ static void __exit unload_waveartist(struct address_info *hw) #define VNC_HANDSET_DETECT 0x40 #define VNC_DISABLE_AUTOSWITCH 0x80 -extern spinlock_t gpio_lock; - static inline void vnc_mute_spkr(wavnc_info *devc) { unsigned long flags; - spin_lock_irqsave(&gpio_lock, flags); - cpld_modify(CPLD_UNMUTE, devc->spkr_mute_state ? 0 : CPLD_UNMUTE); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_cpld_modify(CPLD_UNMUTE, devc->spkr_mute_state ? 0 : CPLD_UNMUTE); + spin_unlock_irqrestore(&nw_gpio_lock, flags); } static void diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c index 780db67..812c2b4 100644 --- a/sound/soc/pxa/pxa2xx-ac97.c +++ b/sound/soc/pxa/pxa2xx-ac97.c @@ -21,6 +21,7 @@ #include <mach/hardware.h> #include <mach/pxa-regs.h> +#include <mach/regs-ac97.h> #include "pxa2xx-pcm.h" #include "pxa2xx-ac97.h" diff --git a/sound/soc/s3c24xx/s3c2443-ac97.c b/sound/soc/s3c24xx/s3c2443-ac97.c index 1bfce40..5822d2d 100644 --- a/sound/soc/s3c24xx/s3c2443-ac97.c +++ b/sound/soc/s3c24xx/s3c2443-ac97.c @@ -28,7 +28,7 @@ #include <sound/soc.h> #include <mach/hardware.h> -#include <asm/plat-s3c/regs-ac97.h> +#include <plat/regs-ac97.h> #include <mach/regs-gpio.h> #include <mach/regs-clock.h> #include <mach/audio.h> |
