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-rw-r--r--arch/arc/kernel/traps.c2
-rw-r--r--arch/arc/plat-eznps/Kconfig11
-rw-r--r--arch/arc/plat-eznps/mtm.c9
3 files changed, 21 insertions, 1 deletions
diff --git a/arch/arc/kernel/traps.c b/arch/arc/kernel/traps.c
index ff83e78..62675b9 100644
--- a/arch/arc/kernel/traps.c
+++ b/arch/arc/kernel/traps.c
@@ -80,7 +80,7 @@ int name(unsigned long address, struct pt_regs *regs) \
DO_ERROR_INFO(SIGILL, "Priv Op/Disabled Extn", do_privilege_fault, ILL_PRVOPC)
DO_ERROR_INFO(SIGILL, "Invalid Extn Insn", do_extension_fault, ILL_ILLOPC)
DO_ERROR_INFO(SIGILL, "Illegal Insn (or Seq)", insterror_is_error, ILL_ILLOPC)
-DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", do_memory_error, BUS_ADRERR)
+DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", __weak do_memory_error, BUS_ADRERR)
DO_ERROR_INFO(SIGTRAP, "Breakpoint Set", trap_is_brkpt, TRAP_BRKPT)
DO_ERROR_INFO(SIGBUS, "Misaligned Access", do_misaligned_error, BUS_ADRALN)
diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index feaa471..b36afb1 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
any of them seem like CPU from Linux point of view.
All threads within same core share the execution unit of the
core and HW scheduler round robin between them.
+
+config EZNPS_MEM_ERROR_ALIGN
+ bool "ARC-EZchip Memory error as an exception"
+ depends on EZNPS_MTM_EXT
+ default n
+ help
+ On the real chip of the NPS, user memory errors are handled
+ as a machine check exception, which is fatal, whereas on
+ simulator platform for NPS, is handled as a Level 2 interrupt
+ (just a stock ARC700) which is recoverable. This option makes
+ simulator behave like hardware.
diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index e0cb36b..dcbf8f6 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -25,6 +25,15 @@
#define MT_CTRL_ST_CNT 0xF
#define NPS_NUM_HW_THREADS 0x10
+#ifdef CONFIG_EZNPS_MEM_ERROR_ALIGN
+int do_memory_error(unsigned long address, struct pt_regs *regs)
+{
+ die("Invalid Mem Access", regs, address);
+
+ return 1;
+}
+#endif
+
static void mtm_init_nat(int cpu)
{
struct nps_host_reg_mtm_cfg mtm_cfg;
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