diff options
| -rw-r--r-- | arch/powerpc/boot/44x.h | 4 | ||||
| -rw-r--r-- | arch/powerpc/boot/4xx.c | 35 | ||||
| -rw-r--r-- | arch/powerpc/boot/4xx.h | 20 | ||||
| -rw-r--r-- | arch/powerpc/boot/dcr.h | 3 | ||||
| -rw-r--r-- | arch/powerpc/boot/ebony.c | 3 |
5 files changed, 55 insertions, 10 deletions
diff --git a/arch/powerpc/boot/44x.h b/arch/powerpc/boot/44x.h index 577982c..490a1cb 100644 --- a/arch/powerpc/boot/44x.h +++ b/arch/powerpc/boot/44x.h @@ -10,10 +10,6 @@ #ifndef _PPC_BOOT_44X_H_ #define _PPC_BOOT_44X_H_ -void ibm44x_fixup_memsize(void); -void ibm4xx_fixup_ebc_ranges(const char *ebc); - -void ibm44x_dbcr_reset(void); void ebony_init(void *mac0, void *mac1); #endif /* _PPC_BOOT_44X_H_ */ diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index 9f64e84..59026e4 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c @@ -21,8 +21,8 @@ #include "reg.h" #include "dcr.h" -/* Read the 44x memory controller to get size of system memory. */ -void ibm44x_fixup_memsize(void) +/* Read the 4xx SDRAM controller to get size of system memory. */ +void ibm4xx_fixup_memsize(void) { int i; unsigned long memsize, bank_config; @@ -39,8 +39,9 @@ void ibm44x_fixup_memsize(void) dt_fixup_memory(0, memsize); } -#define SPRN_DBCR0 0x134 -#define DBCR0_RST_SYSTEM 0x30000000 +#define SPRN_DBCR0_40X 0x3F2 +#define SPRN_DBCR0_44X 0x134 +#define DBCR0_RST_SYSTEM 0x30000000 void ibm44x_dbcr_reset(void) { @@ -50,11 +51,35 @@ void ibm44x_dbcr_reset(void) "mfspr %0,%1\n" "oris %0,%0,%2@h\n" "mtspr %1,%0" - : "=&r"(tmp) : "i"(SPRN_DBCR0), "i"(DBCR0_RST_SYSTEM) + : "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM) ); } +void ibm40x_dbcr_reset(void) +{ + unsigned long tmp; + + asm volatile ( + "mfspr %0,%1\n" + "oris %0,%0,%2@h\n" + "mtspr %1,%0" + : "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM) + ); +} + +#define EMAC_RESET 0x20000000 +void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1) +{ + /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us */ + if (emac0) + *emac0 = EMAC_RESET; + if (emac1) + *emac1 = EMAC_RESET; + + mtdcr(DCRN_MAL0_CFG, MAL_RESET); +} + /* Read 4xx EBC bus bridge registers to get mappings of the peripheral * banks into the OPB address space */ void ibm4xx_fixup_ebc_ranges(const char *ebc) diff --git a/arch/powerpc/boot/4xx.h b/arch/powerpc/boot/4xx.h new file mode 100644 index 0000000..6500842 --- /dev/null +++ b/arch/powerpc/boot/4xx.h @@ -0,0 +1,20 @@ +/* + * PowerPC 4xx related functions + * + * Copyright 2007 IBM Corporation. + * Josh Boyer <jwboyer@linux.vnet.ibm.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#ifndef _POWERPC_BOOT_4XX_H_ +#define _POWERPC_BOOT_4XX_H_ + +void ibm4xx_fixup_memsize(void); +void ibm44x_dbcr_reset(void); +void ibm40x_dbcr_reset(void); +void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1); +void ibm4xx_fixup_ebc_ranges(const char *ebc); + +#endif /* _POWERPC_BOOT_4XX_H_ */ diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h index 14b44aa..c95d1a9 100644 --- a/arch/powerpc/boot/dcr.h +++ b/arch/powerpc/boot/dcr.h @@ -121,4 +121,7 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2C #define DCRN_CPC0_MIRQ1 0x0ed #define DCRN_CPC0_JTAGID 0x0ef +#define DCRN_MAL0_CFG 0x180 +#define MAL_RESET 0x80000000 + #endif /* _PPC_BOOT_DCR_H_ */ diff --git a/arch/powerpc/boot/ebony.c b/arch/powerpc/boot/ebony.c index eaf0b9b..2b9a809 100644 --- a/arch/powerpc/boot/ebony.c +++ b/arch/powerpc/boot/ebony.c @@ -26,6 +26,7 @@ #include "reg.h" #include "io.h" #include "dcr.h" +#include "4xx.h" #include "44x.h" extern char _dtb_start[]; @@ -136,7 +137,7 @@ static void ebony_fixups(void) unsigned long sysclk = 33000000; ibm440gp_fixup_clocks(sysclk, 6 * 1843200); - ibm44x_fixup_memsize(); + ibm4xx_fixup_memsize(); dt_fixup_mac_addresses(ebony_mac0, ebony_mac1); ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); ebony_flashsel_fixup(); |
