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-rw-r--r--arch/m68k/include/asm/m532xsim.h33
-rw-r--r--arch/m68knommu/platform/coldfire/intc-simr.c5
2 files changed, 5 insertions, 33 deletions
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 41c57e0..021a0e1 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -56,8 +56,6 @@
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
-#define MCFSIM_IMR_MASKALL 0xFFFFFFFF /* All SIM intr sources */
-
#define MCFINTC0_SIMR 0xFC04801C
#define MCFINTC0_CIMR 0xFC04801D
#define MCFINTC0_ICR0 0xFC048040
@@ -70,37 +68,6 @@
/*
- * Macro to set IMR register. It is 32 bits on the 5307.
- */
-#define mcf_getimr() \
- *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
-
-#define mcf_setimr(imr) \
- *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
-
-#define mcf_getipr() \
- *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
-
-#define mcf_getiprl() \
- *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRL))
-
-#define mcf_getiprh() \
- *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRH))
-
-
-#define mcf_enable_irq0(irq) \
- *((volatile unsigned char *) (MCFINTC0_CIMR)) = (irq);
-
-#define mcf_enable_irq1(irq) \
- *((volatile unsigned char *) (MCFINTC1_CIMR)) = (irq);
-
-#define mcf_disable_irq0(irq) \
- *((volatile unsigned char *) (MCFINTC0_SIMR)) = (irq);
-
-#define mcf_disable_irq1(irq) \
- *((volatile unsigned char *) (MCFINTC1_SIMR)) = (irq);
-
-/*
* Define the Cache register flags.
*/
#define CACR_EC (1<<31)
diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c
index 86fc204..1b01e79 100644
--- a/arch/m68knommu/platform/coldfire/intc-simr.c
+++ b/arch/m68knommu/platform/coldfire/intc-simr.c
@@ -62,6 +62,11 @@ void __init init_IRQ(void)
init_vectors();
+ /* Mask all interrupt sources */
+ __raw_writeb(0xff, MCFINTC0_SIMR);
+ if (MCFINTC1_SIMR)
+ __raw_writeb(0xff, MCFINTC1_SIMR);
+
for (irq = 0; (irq < NR_IRQS); irq++) {
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = NULL;
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