diff options
| -rw-r--r-- | arch/arm/mach-pxa/ssp.c | 2 | ||||
| -rw-r--r-- | drivers/video/pxafb.c | 6 | ||||
| -rw-r--r-- | include/asm-arm/arch-pxa/regs-lcd.h | 5 |
3 files changed, 9 insertions, 4 deletions
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c index 00af7f2..0bb3198 100644 --- a/arch/arm/mach-pxa/ssp.c +++ b/arch/arm/mach-pxa/ssp.c @@ -330,7 +330,7 @@ struct ssp_device *ssp_request(int port, const char *label) mutex_unlock(&ssp_lock); - if (ssp->port_id != port) + if (&ssp->node == &ssp_list) return NULL; return ssp; diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index 274bc93..7dcda18 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c @@ -573,8 +573,8 @@ static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; } else { - pal_desc = &fbi->dma_buff->pal_desc[dma]; - pal_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[pal]); + pal_desc = &fbi->dma_buff->pal_desc[pal]; + pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]); pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE; pal_desc->fidr = 0; @@ -1276,6 +1276,8 @@ static int __init pxafb_map_video_memory(struct pxafb_info *fbi) fbi->dma_buff_phys = fbi->map_dma; fbi->palette_cpu = (u16 *) fbi->dma_buff->palette; + pr_debug("pxafb: palette_mem_size = 0x%08lx\n", fbi->palette_size*sizeof(u16)); + #ifdef CONFIG_FB_PXA_SMARTPANEL fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff; fbi->n_smart_cmds = 0; diff --git a/include/asm-arm/arch-pxa/regs-lcd.h b/include/asm-arm/arch-pxa/regs-lcd.h index f762493..3ba464c9 100644 --- a/include/asm-arm/arch-pxa/regs-lcd.h +++ b/include/asm-arm/arch-pxa/regs-lcd.h @@ -1,5 +1,8 @@ #ifndef __ASM_ARCH_REGS_LCD_H #define __ASM_ARCH_REGS_LCD_H + +#include <asm/arch/bitfield.h> + /* * LCD Controller Registers and Bits Definitions */ @@ -69,7 +72,7 @@ #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ #define LCCR0_PDD_S 12 -#define LCCR0_BM (1 << 20) /* Branch mask */ +#define LCCR0_BM (1 << 20) /* Branch mask */ #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ #define LCCR0_LCDT (1 << 22) /* LCD panel type */ #define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ |
