diff options
95 files changed, 2064 insertions, 10015 deletions
diff --git a/Documentation/Makefile b/Documentation/Makefile index 6883a1b..bc05482 100644 --- a/Documentation/Makefile +++ b/Documentation/Makefile @@ -1,4 +1,4 @@ -subdir-y := accounting arm auxdisplay blackfin connector \ +subdir-y := accounting auxdisplay blackfin connector \ filesystems filesystems ia64 laptops mic misc-devices \ networking pcmcia prctl ptp spi timers vDSO video4linux \ watchdog diff --git a/Documentation/arm/Makefile b/Documentation/arm/Makefile deleted file mode 100644 index 732c770..0000000 --- a/Documentation/arm/Makefile +++ /dev/null @@ -1 +0,0 @@ -subdir-y := SH-Mobile diff --git a/Documentation/arm/SH-Mobile/Makefile b/Documentation/arm/SH-Mobile/Makefile deleted file mode 100644 index bca8a7e..0000000 --- a/Documentation/arm/SH-Mobile/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# List of programs to build -hostprogs-y := vrl4 - -# Tell kbuild to always build the programs -always := $(hostprogs-y) - -HOSTCFLAGS_vrl4.o += -I$(objtree)/usr/include -I$(srctree)/tools/include diff --git a/Documentation/arm/SH-Mobile/vrl4.c b/Documentation/arm/SH-Mobile/vrl4.c deleted file mode 100644 index f4cd8ad..0000000 --- a/Documentation/arm/SH-Mobile/vrl4.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * vrl4 format generator - * - * Copyright (C) 2010 Simon Horman - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -/* - * usage: vrl4 < zImage > out - * dd if=out of=/dev/sdx bs=512 seek=1 # Write the image to sector 1 - * - * Reads a zImage from stdin and writes a vrl4 image to stdout. - * In practice this means writing a padded vrl4 header to stdout followed - * by the zImage. - * - * The padding places the zImage at ALIGN bytes into the output. - * The vrl4 uses ALIGN + START_BASE as the start_address. - * This is where the mask ROM will jump to after verifying the header. - * - * The header sets copy_size to min(sizeof(zImage), MAX_BOOT_PROG_LEN) + ALIGN. - * That is, the mask ROM will load the padded header (ALIGN bytes) - * And then MAX_BOOT_PROG_LEN bytes of the image, or the entire image, - * whichever is smaller. - * - * The zImage is not modified in any way. - */ - -#define _BSD_SOURCE -#include <endian.h> -#include <unistd.h> -#include <stdint.h> -#include <stdio.h> -#include <errno.h> -#include <tools/endian.h> - -struct hdr { - uint32_t magic1; - uint32_t reserved1; - uint32_t magic2; - uint32_t reserved2; - uint16_t copy_size; - uint16_t boot_options; - uint32_t reserved3; - uint32_t start_address; - uint32_t reserved4; - uint32_t reserved5; - char reserved6[308]; -}; - -#define DECLARE_HDR(h) \ - struct hdr (h) = { \ - .magic1 = htole32(0xea000000), \ - .reserved1 = htole32(0x56), \ - .magic2 = htole32(0xe59ff008), \ - .reserved3 = htole16(0x1) } - -/* Align to 512 bytes, the MMCIF sector size */ -#define ALIGN_BITS 9 -#define ALIGN (1 << ALIGN_BITS) - -#define START_BASE 0xe55b0000 - -/* - * With an alignment of 512 the header uses the first sector. - * There is a 128 sector (64kbyte) limit on the data loaded by the mask ROM. - * So there are 127 sectors left for the boot programme. But in practice - * Only a small portion of a zImage is needed, 16 sectors should be more - * than enough. - * - * Note that this sets how much of the zImage is copied by the mask ROM. - * The entire zImage is present after the header and is loaded - * by the code in the boot program (which is the first portion of the zImage). - */ -#define MAX_BOOT_PROG_LEN (16 * 512) - -#define ROUND_UP(x) ((x + ALIGN - 1) & ~(ALIGN - 1)) - -static ssize_t do_read(int fd, void *buf, size_t count) -{ - size_t offset = 0; - ssize_t l; - - while (offset < count) { - l = read(fd, buf + offset, count - offset); - if (!l) - break; - if (l < 0) { - if (errno == EAGAIN || errno == EWOULDBLOCK) - continue; - perror("read"); - return -1; - } - offset += l; - } - - return offset; -} - -static ssize_t do_write(int fd, const void *buf, size_t count) -{ - size_t offset = 0; - ssize_t l; - - while (offset < count) { - l = write(fd, buf + offset, count - offset); - if (l < 0) { - if (errno == EAGAIN || errno == EWOULDBLOCK) - continue; - perror("write"); - return -1; - } - offset += l; - } - - return offset; -} - -static ssize_t write_zero(int fd, size_t len) -{ - size_t i = len; - - while (i--) { - const char x = 0; - if (do_write(fd, &x, 1) < 0) - return -1; - } - - return len; -} - -int main(void) -{ - DECLARE_HDR(hdr); - char boot_program[MAX_BOOT_PROG_LEN]; - size_t aligned_hdr_len, alligned_prog_len; - ssize_t prog_len; - - prog_len = do_read(0, boot_program, sizeof(boot_program)); - if (prog_len <= 0) - return -1; - - aligned_hdr_len = ROUND_UP(sizeof(hdr)); - hdr.start_address = htole32(START_BASE + aligned_hdr_len); - alligned_prog_len = ROUND_UP(prog_len); - hdr.copy_size = htole16(aligned_hdr_len + alligned_prog_len); - - if (do_write(1, &hdr, sizeof(hdr)) < 0) - return -1; - if (write_zero(1, aligned_hdr_len - sizeof(hdr)) < 0) - return -1; - - if (do_write(1, boot_program, prog_len) < 0) - return 1; - - /* Write out the rest of the kernel */ - while (1) { - prog_len = do_read(0, boot_program, sizeof(boot_program)); - if (prog_len < 0) - return 1; - if (prog_len == 0) - break; - if (do_write(1, boot_program, prog_len) < 0) - return 1; - } - - return 0; -} diff --git a/Documentation/arm/SH-Mobile/zboot-rom-mmcif.txt b/Documentation/arm/SH-Mobile/zboot-rom-mmcif.txt deleted file mode 100644 index efff8ae..0000000 --- a/Documentation/arm/SH-Mobile/zboot-rom-mmcif.txt +++ /dev/null @@ -1,29 +0,0 @@ -ROM-able zImage boot from MMC ------------------------------ - -An ROM-able zImage compiled with ZBOOT_ROM_MMCIF may be written to MMC and -SuperH Mobile ARM will to boot directly from the MMCIF hardware block. - -This is achieved by the mask ROM loading the first portion of the image into -MERAM and then jumping to it. This portion contains loader code which -copies the entire image to SDRAM and jumps to it. From there the zImage -boot code proceeds as normal, uncompressing the image into its final -location and then jumping to it. - -This code has been tested on an AP4EB board using the developer 1A eMMC -boot mode which is configured using the following jumper settings. -The board used for testing required a patched mask ROM in order for -this mode to function. - - 8 7 6 5 4 3 2 1 - x|x|x|x|x| |x| -S4 -+-+-+-+-+-+-+- - | | | | |x| |x on - -The zImage must be written to the MMC card at sector 1 (512 bytes) in -vrl4 format. A utility vrl4 is supplied to accomplish this. - -e.g. - vrl4 < zImage | dd of=/dev/sdX bs=512 seek=1 - -A dual-voltage MMC 4.0 card was used for testing. diff --git a/Documentation/arm/SH-Mobile/zboot-rom-sdhi.txt b/Documentation/arm/SH-Mobile/zboot-rom-sdhi.txt deleted file mode 100644 index 4419598..0000000 --- a/Documentation/arm/SH-Mobile/zboot-rom-sdhi.txt +++ /dev/null @@ -1,42 +0,0 @@ -ROM-able zImage boot from eSD ------------------------------ - -An ROM-able zImage compiled with ZBOOT_ROM_SDHI may be written to eSD and -SuperH Mobile ARM will to boot directly from the SDHI hardware block. - -This is achieved by the mask ROM loading the first portion of the image into -MERAM and then jumping to it. This portion contains loader code which -copies the entire image to SDRAM and jumps to it. From there the zImage -boot code proceeds as normal, uncompressing the image into its final -location and then jumping to it. - -This code has been tested on an mackerel board using the developer 1A eSD -boot mode which is configured using the following jumper settings. - - 8 7 6 5 4 3 2 1 - x|x|x|x| |x|x| -S4 -+-+-+-+-+-+-+- - | | | |x| | |x on - -The eSD card needs to be present in SDHI slot 1 (CN7). -As such S1 and S33 also need to be configured as per -the notes in arch/arm/mach-shmobile/board-mackerel.c. - -A partial zImage must be written to physical partition #1 (boot) -of the eSD at sector 0 in vrl4 format. A utility vrl4 is supplied to -accomplish this. - -e.g. - vrl4 < zImage | dd of=/dev/sdX bs=512 count=17 - -A full copy of _the same_ zImage should be written to physical partition #1 -(boot) of the eSD at sector 0. This should _not_ be in vrl4 format. - - vrl4 < zImage | dd of=/dev/sdX bs=512 - -Note: The commands above assume that the physical partition has been -switched. No such facility currently exists in the Linux Kernel. - -Physical partitions are described in the eSD specification. At the time of -writing they are not the same as partitions that are typically configured -using fdisk and visible through /proc/partitions diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 51147cb..c4f19b2 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -7,8 +7,6 @@ SoCs: compatible = "renesas,emev2" - RZ/A1H (R7S72100) compatible = "renesas,r7s72100" - - SH-Mobile AP4 (R8A73720/SH7372) - compatible = "renesas,sh7372" - SH-Mobile AG5 (R8A73A00/SH73A0) compatible = "renesas,sh73a0" - R-Mobile APE6 (R8A73A40) @@ -37,8 +35,6 @@ Boards: compatible = "renesas,alt", "renesas,r8a7794" - APE6-EVM compatible = "renesas,ape6evm", "renesas,r8a73a4" - - APE6-EVM - Reference Device Tree Implementation - compatible = "renesas,ape6evm-reference", "renesas,r8a73a4" - Atmark Techno Armadillo-800 EVA compatible = "renesas,armadillo800eva" - BOCK-W @@ -57,12 +53,8 @@ Boards: compatible = "renesas,kzm9d", "renesas,emev2" - Kyoto Microcomputer Co. KZM-A9-GT compatible = "renesas,kzm9g", "renesas,sh73a0" - - Kyoto Microcomputer Co. KZM-A9-GT - Reference Device Tree Implementation - compatible = "renesas,kzm9g-reference", "renesas,sh73a0" - Lager (RTP0RC7790SEB00010S) compatible = "renesas,lager", "renesas,r8a7790" - - Mackerel (R0P7372LC0016RL, AP4 EVM 2nd) - compatible = "renesas,mackerel" - Marzen compatible = "renesas,marzen", "renesas,r8a7779" diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt new file mode 100644 index 0000000..2f3747f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt @@ -0,0 +1,25 @@ +* Renesas R8A7778 Clock Pulse Generator (CPG) + +The CPG generates core clocks for the R8A7778. It includes two PLLs and +several fixed ratio dividers + +Required Properties: + + - compatible: Must be "renesas,r8a7778-cpg-clocks" + - reg: Base address and length of the memory resource used by the CPG + - #clock-cells: Must be 1 + - clock-output-names: The names of the clocks. Supported clocks are + "plla", "pllb", "b", "out", "p", "s", and "s1". + + +Example +------- + + cpg_clocks: cpg_clocks@ffc80000 { + compatible = "renesas,r8a7778-cpg-clocks"; + reg = <0xffc80000 0x80>; + #clock-cells = <1>; + clocks = <&extal_clk>; + clock-output-names = "plla", "pllb", "b", + "out", "p", "s", "s1"; + }; diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index 003bd77..ad0c4ac 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -77,6 +77,7 @@ nxp,pca9556 Octal SMBus and I2C registered interface nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset nxp,pcf8563 Real-time clock/calendar nxp,pcf85063 Tiny Real-Time Clock +oki,ml86v7667 OKI ML86V7667 video decoder ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus pericom,pt7c4338 Real-time Clock Module plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch diff --git a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt index cc3b1f0..beda7d2 100644 --- a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt +++ b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt @@ -11,6 +11,7 @@ Required properties: - compatible: Should be "renesas,sysc-<soctype>", "renesas,sysc-rmobile" as fallback. Examples with soctypes are: + - "renesas,sysc-r8a73a4" (R-Mobile APE6) - "renesas,sysc-r8a7740" (R-Mobile A1) - "renesas,sysc-sh73a0" (SH-Mobile AG5) - reg: Two address start and address range blocks for the device: diff --git a/MAINTAINERS b/MAINTAINERS index 39fb043..f6f5950 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1426,11 +1426,9 @@ F: arch/arm/boot/dts/emev2* F: arch/arm/boot/dts/r7s* F: arch/arm/boot/dts/r8a* F: arch/arm/boot/dts/sh* -F: arch/arm/configs/ape6evm_defconfig F: arch/arm/configs/armadillo800eva_defconfig F: arch/arm/configs/bockw_defconfig F: arch/arm/configs/kzm9g_defconfig -F: arch/arm/configs/mackerel_defconfig F: arch/arm/configs/marzen_defconfig F: arch/arm/configs/shmobile_defconfig F: arch/arm/include/debug/renesas-scif.S diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 29e80ad..45df48b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -362,19 +362,6 @@ config ARCH_VERSATILE help This enables support for ARM Ltd Versatile board. -config ARCH_AT91 - bool "Atmel AT91" - select ARCH_REQUIRE_GPIOLIB - select CLKDEV_LOOKUP - select IRQ_DOMAIN - select PINCTRL - select PINCTRL_AT91 - select SOC_BUS - select USE_OF - help - This enables support for systems based on Atmel - AT91RM9200, AT91SAM9 and SAMA5 processors. - config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" select ARCH_REQUIRE_GPIOLIB @@ -641,7 +628,6 @@ config ARCH_SHMOBILE_LEGACY select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP - select HAVE_MACH_CLKDEV select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select MULTI_IRQ_HANDLER @@ -1511,7 +1497,7 @@ config HZ_FIXED int default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ ARCH_S5PV210 || ARCH_EXYNOS4 - default AT91_TIMER_HZ if ARCH_AT91 + default 128 if SOC_AT91RM9200 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY default 0 @@ -1844,35 +1830,6 @@ config ZBOOT_ROM Say Y here if you intend to execute your compressed kernel image (zImage) directly from ROM or flash. If unsure, say N. -choice - prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" - depends on ZBOOT_ROM && ARCH_SH7372 - default ZBOOT_ROM_NONE - help - Include experimental SD/MMC loading code in the ROM-able zImage. - With this enabled it is possible to write the ROM-able zImage - kernel image to an MMC or SD card and boot the kernel straight - from the reset vector. At reset the processor Mask ROM will load - the first part of the ROM-able zImage which in turn loads the - rest the kernel image to RAM. - -config ZBOOT_ROM_NONE - bool "No SD/MMC loader in zImage (EXPERIMENTAL)" - help - Do not load image from SD or MMC - -config ZBOOT_ROM_MMCIF - bool "Include MMCIF loader in zImage (EXPERIMENTAL)" - help - Load image from MMCIF hardware block. - -config ZBOOT_ROM_SH_MOBILE_SDHI - bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" - help - Load image from SDHI hardware block - -endchoice - config ARM_APPENDED_DTB bool "Use appended device tree blob to zImage (EXPERIMENTAL)" depends on OF diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 771d518..0c12ffb 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -810,12 +810,11 @@ choice via SCIF2 on Renesas R-Car E2 (R8A7794). config DEBUG_RMOBILE_SCIFA0 - bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4/SH7372" - depends on ARCH_R8A73A4 || ARCH_SH7372 + bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4" + depends on ARCH_R8A73A4 help Say Y here if you want kernel low-level debugging support - via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4) or SH-Mobile - AP4 (SH7372). + via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4). config DEBUG_RMOBILE_SCIFA1 bool "Kernel low-level debugging messages via SCIFA1 on R8A7740" @@ -1562,7 +1561,8 @@ config DEBUG_UNCOMPRESS config UNCOMPRESS_INCLUDE string default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \ - PLAT_SAMSUNG || ARCH_EFM32 + PLAT_SAMSUNG || ARCH_EFM32 || \ + ARCH_SHMOBILE_LEGACY default "mach/uncompress.h" config EARLY_PRINTK diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 3ea230a..6e1fb2b 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -6,21 +6,6 @@ OBJS = -# Ensure that MMCIF loader code appears early in the image -# to minimise that number of bocks that have to be read in -# order to load it. -ifeq ($(CONFIG_ZBOOT_ROM_MMCIF),y) -OBJS += mmcif-sh7372.o -endif - -# Ensure that SDHI loader code appears early in the image -# to minimise that number of bocks that have to be read in -# order to load it. -ifeq ($(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI),y) -OBJS += sdhi-shmobile.o -OBJS += sdhi-sh7372.o -endif - AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) HEAD = head.o OBJS += misc.o decompress.o diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S index e7f8092..22a7525 100644 --- a/arch/arm/boot/compressed/head-shmobile.S +++ b/arch/arm/boot/compressed/head-shmobile.S @@ -25,36 +25,6 @@ /* load board-specific initialization code */ #include <mach/zboot.h> -#if defined(CONFIG_ZBOOT_ROM_MMCIF) || defined(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI) - /* Load image from MMC/SD */ - adr sp, __tmp_stack + 256 - ldr r0, __image_start - ldr r1, __image_end - subs r1, r1, r0 - ldr r0, __load_base - bl mmc_loader - - /* Jump to loaded code */ - ldr r0, __loaded - ldr r1, __image_start - sub r0, r0, r1 - ldr r1, __load_base - add pc, r0, r1 - -__image_start: - .long _start -__image_end: - .long _got_end -__load_base: - .long MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM -__loaded: - .long __continue - .align -__tmp_stack: - .space 256 -__continue: -#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */ - adr r0, dtb_info ldmia r0, {r1, r3, r4, r5, r7} diff --git a/arch/arm/boot/compressed/mmcif-sh7372.c b/arch/arm/boot/compressed/mmcif-sh7372.c deleted file mode 100644 index 672ae95..0000000 --- a/arch/arm/boot/compressed/mmcif-sh7372.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * sh7372 MMCIF loader - * - * Copyright (C) 2010 Magnus Damm - * Copyright (C) 2010 Simon Horman - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#include <linux/mmc/sh_mmcif.h> -#include <linux/mmc/boot.h> -#include <mach/mmc.h> - -#define MMCIF_BASE (void __iomem *)0xe6bd0000 - -#define PORT84CR (void __iomem *)0xe6050054 -#define PORT85CR (void __iomem *)0xe6050055 -#define PORT86CR (void __iomem *)0xe6050056 -#define PORT87CR (void __iomem *)0xe6050057 -#define PORT88CR (void __iomem *)0xe6050058 -#define PORT89CR (void __iomem *)0xe6050059 -#define PORT90CR (void __iomem *)0xe605005a -#define PORT91CR (void __iomem *)0xe605005b -#define PORT92CR (void __iomem *)0xe605005c -#define PORT99CR (void __iomem *)0xe6050063 - -#define SMSTPCR3 (void __iomem *)0xe615013c - -/* SH7372 specific MMCIF loader - * - * loads the zImage from an MMC card starting from block 1. - * - * The image must be start with a vrl4 header and - * the zImage must start at offset 512 of the image. That is, - * at block 2 (=byte 1024) on the media - * - * Use the following line to write the vrl4 formated zImage - * to an MMC card - * # dd if=vrl4.out of=/dev/sdx bs=512 seek=1 - */ -asmlinkage void mmc_loader(unsigned char *buf, unsigned long len) -{ - mmc_init_progress(); - mmc_update_progress(MMC_PROGRESS_ENTER); - - /* Initialise MMC - * registers: PORT84CR-PORT92CR - * (MMCD0_0-MMCD0_7,MMCCMD0 Control) - * value: 0x04 - select function 4 - */ - __raw_writeb(0x04, PORT84CR); - __raw_writeb(0x04, PORT85CR); - __raw_writeb(0x04, PORT86CR); - __raw_writeb(0x04, PORT87CR); - __raw_writeb(0x04, PORT88CR); - __raw_writeb(0x04, PORT89CR); - __raw_writeb(0x04, PORT90CR); - __raw_writeb(0x04, PORT91CR); - __raw_writeb(0x04, PORT92CR); - - /* Initialise MMC - * registers: PORT99CR (MMCCLK0 Control) - * value: 0x10 | 0x04 - enable output | select function 4 - */ - __raw_writeb(0x14, PORT99CR); - - /* Enable clock to MMC hardware block */ - __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3); - - mmc_update_progress(MMC_PROGRESS_INIT); - - /* setup MMCIF hardware */ - sh_mmcif_boot_init(MMCIF_BASE); - - mmc_update_progress(MMC_PROGRESS_LOAD); - - /* load kernel via MMCIF interface */ - sh_mmcif_boot_do_read(MMCIF_BASE, 2, /* Kernel is at block 2 */ - (len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf); - - - /* Disable clock to MMC hardware block */ - __raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3); - - mmc_update_progress(MMC_PROGRESS_DONE); -} diff --git a/arch/arm/boot/compressed/sdhi-sh7372.c b/arch/arm/boot/compressed/sdhi-sh7372.c deleted file mode 100644 index d279294..0000000 --- a/arch/arm/boot/compressed/sdhi-sh7372.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * SuperH Mobile SDHI - * - * Copyright (C) 2010 Magnus Damm - * Copyright (C) 2010 Kuninori Morimoto - * Copyright (C) 2010 Simon Horman - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Parts inspired by u-boot - */ - -#include <linux/io.h> -#include <mach/mmc.h> -#include <linux/mmc/boot.h> -#include <linux/mmc/tmio.h> - -#include "sdhi-shmobile.h" - -#define PORT179CR 0xe60520b3 -#define PORT180CR 0xe60520b4 -#define PORT181CR 0xe60520b5 -#define PORT182CR 0xe60520b6 -#define PORT183CR 0xe60520b7 -#define PORT184CR 0xe60520b8 - -#define SMSTPCR3 0xe615013c - -#define CR_INPUT_ENABLE 0x10 -#define CR_FUNCTION1 0x01 - -#define SDHI1_BASE (void __iomem *)0xe6860000 -#define SDHI_BASE SDHI1_BASE - -/* SuperH Mobile SDHI loader - * - * loads the zImage from an SD card starting from block 0 - * on physical partition 1 - * - * The image must be start with a vrl4 header and - * the zImage must start at offset 512 of the image. That is, - * at block 1 (=byte 512) of physical partition 1 - * - * Use the following line to write the vrl4 formated zImage - * to an SD card - * # dd if=vrl4.out of=/dev/sdx bs=512 - */ -asmlinkage void mmc_loader(unsigned short *buf, unsigned long len) -{ - int high_capacity; - - mmc_init_progress(); - - mmc_update_progress(MMC_PROGRESS_ENTER); - /* Initialise SDHI1 */ - /* PORT184CR: GPIO_FN_SDHICMD1 Control */ - __raw_writeb(CR_FUNCTION1, PORT184CR); - /* PORT179CR: GPIO_FN_SDHICLK1 Control */ - __raw_writeb(CR_INPUT_ENABLE|CR_FUNCTION1, PORT179CR); - /* PORT181CR: GPIO_FN_SDHID1_3 Control */ - __raw_writeb(CR_FUNCTION1, PORT183CR); - /* PORT182CR: GPIO_FN_SDHID1_2 Control */ - __raw_writeb(CR_FUNCTION1, PORT182CR); - /* PORT183CR: GPIO_FN_SDHID1_1 Control */ - __raw_writeb(CR_FUNCTION1, PORT181CR); - /* PORT180CR: GPIO_FN_SDHID1_0 Control */ - __raw_writeb(CR_FUNCTION1, PORT180CR); - - /* Enable clock to SDHI1 hardware block */ - __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 13), SMSTPCR3); - - /* setup SDHI hardware */ - mmc_update_progress(MMC_PROGRESS_INIT); - high_capacity = sdhi_boot_init(SDHI_BASE); - if (high_capacity < 0) - goto err; - - mmc_update_progress(MMC_PROGRESS_LOAD); - /* load kernel */ - if (sdhi_boot_do_read(SDHI_BASE, high_capacity, - 0, /* Kernel is at block 1 */ - (len + TMIO_BBS - 1) / TMIO_BBS, buf)) - goto err; - - /* Disable clock to SDHI1 hardware block */ - __raw_writel(__raw_readl(SMSTPCR3) | (1 << 13), SMSTPCR3); - - mmc_update_progress(MMC_PROGRESS_DONE); - - return; -err: - for(;;); -} diff --git a/arch/arm/boot/compressed/sdhi-shmobile.c b/arch/arm/boot/compressed/sdhi-shmobile.c deleted file mode 100644 index bd3d469..0000000 --- a/arch/arm/boot/compressed/sdhi-shmobile.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * SuperH Mobile SDHI - * - * Copyright (C) 2010 Magnus Damm - * Copyright (C) 2010 Kuninori Morimoto - * Copyright (C) 2010 Simon Horman - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Parts inspired by u-boot - */ - -#include <linux/io.h> -#include <linux/mmc/host.h> -#include <linux/mmc/core.h> -#include <linux/mmc/mmc.h> -#include <linux/mmc/sd.h> -#include <linux/mmc/tmio.h> -#include <mach/sdhi.h> - -#define OCR_FASTBOOT (1<<29) -#define OCR_HCS (1<<30) -#define OCR_BUSY (1<<31) - -#define RESP_CMD12 0x00000030 - -static inline u16 sd_ctrl_read16(void __iomem *base, int addr) -{ - return __raw_readw(base + addr); -} - -static inline u32 sd_ctrl_read32(void __iomem *base, int addr) -{ - return __raw_readw(base + addr) | - __raw_readw(base + addr + 2) << 16; -} - -static inline void sd_ctrl_write16(void __iomem *base, int addr, u16 val) -{ - __raw_writew(val, base + addr); -} - -static inline void sd_ctrl_write32(void __iomem *base, int addr, u32 val) -{ - __raw_writew(val, base + addr); - __raw_writew(val >> 16, base + addr + 2); -} - -#define ALL_ERROR (TMIO_STAT_CMD_IDX_ERR | TMIO_STAT_CRCFAIL | \ - TMIO_STAT_STOPBIT_ERR | TMIO_STAT_DATATIMEOUT | \ - TMIO_STAT_RXOVERFLOW | TMIO_STAT_TXUNDERRUN | \ - TMIO_STAT_CMDTIMEOUT | TMIO_STAT_ILL_ACCESS | \ - TMIO_STAT_ILL_FUNC) - -static int sdhi_intr(void __iomem *base) -{ - unsigned long state = sd_ctrl_read32(base, CTL_STATUS); - - if (state & ALL_ERROR) { - sd_ctrl_write32(base, CTL_STATUS, ~ALL_ERROR); - sd_ctrl_write32(base, CTL_IRQ_MASK, - ALL_ERROR | - sd_ctrl_read32(base, CTL_IRQ_MASK)); - return -EINVAL; - } - if (state & TMIO_STAT_CMDRESPEND) { - sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND); - sd_ctrl_write32(base, CTL_IRQ_MASK, - TMIO_STAT_CMDRESPEND | - sd_ctrl_read32(base, CTL_IRQ_MASK)); - return 0; - } - if (state & TMIO_STAT_RXRDY) { - sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_RXRDY); - sd_ctrl_write32(base, CTL_IRQ_MASK, - TMIO_STAT_RXRDY | TMIO_STAT_TXUNDERRUN | - sd_ctrl_read32(base, CTL_IRQ_MASK)); - return 0; - } - if (state & TMIO_STAT_DATAEND) { - sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_DATAEND); - sd_ctrl_write32(base, CTL_IRQ_MASK, - TMIO_STAT_DATAEND | - sd_ctrl_read32(base, CTL_IRQ_MASK)); - return 0; - } - - return -EAGAIN; -} - -static int sdhi_boot_wait_resp_end(void __iomem *base) -{ - int err = -EAGAIN, timeout = 10000000; - - while (timeout--) { - err = sdhi_intr(base); - if (err != -EAGAIN) - break; - udelay(1); - } - - return err; -} - -/* SDHI_CLK_CTRL */ -#define CLK_MMC_ENABLE (1 << 8) -#define CLK_MMC_INIT (1 << 6) /* clk / 256 */ - -static void sdhi_boot_mmc_clk_stop(void __iomem *base) -{ - sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, 0x0000); - msleep(10); - sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, ~CLK_MMC_ENABLE & - sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL)); - msleep(10); -} - -static void sdhi_boot_mmc_clk_start(void __iomem *base) -{ - sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, CLK_MMC_ENABLE | - sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL)); - msleep(10); - sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, CLK_MMC_ENABLE); - msleep(10); -} - -static void sdhi_boot_reset(void __iomem *base) -{ - sd_ctrl_write16(base, CTL_RESET_SD, 0x0000); - msleep(10); - sd_ctrl_write16(base, CTL_RESET_SD, 0x0001); - msleep(10); -} - -/* Set MMC clock / power. - * Note: This controller uses a simple divider scheme therefore it cannot - * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as - * MMC wont run that fast, it has to be clocked at 12MHz which is the next - * slowest setting. - */ -static int sdhi_boot_mmc_set_ios(void __iomem *base, struct mmc_ios *ios) -{ - if (sd_ctrl_read32(base, CTL_STATUS) & TMIO_STAT_CMD_BUSY) - return -EBUSY; - - if (ios->clock) - sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, - ios->clock | CLK_MMC_ENABLE); - - /* Power sequence - OFF -> ON -> UP */ - switch (ios->power_mode) { - case MMC_POWER_OFF: /* power down SD bus */ - sdhi_boot_mmc_clk_stop(base); - break; - case MMC_POWER_ON: /* power up SD bus */ - break; - case MMC_POWER_UP: /* start bus clock */ - sdhi_boot_mmc_clk_start(base); - break; - } - - switch (ios->bus_width) { - case MMC_BUS_WIDTH_1: - sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x80e0); - break; - case MMC_BUS_WIDTH_4: - sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x00e0); - break; - } - - /* Let things settle. delay taken from winCE driver */ - udelay(140); - - return 0; -} - -/* These are the bitmasks the tmio chip requires to implement the MMC response - * types. Note that R1 and R6 are the same in this scheme. */ -#define RESP_NONE 0x0300 -#define RESP_R1 0x0400 -#define RESP_R1B 0x0500 -#define RESP_R2 0x0600 -#define RESP_R3 0x0700 -#define DATA_PRESENT 0x0800 -#define TRANSFER_READ 0x1000 - -static int sdhi_boot_request(void __iomem *base, struct mmc_command *cmd) -{ - int err, c = cmd->opcode; - - switch (mmc_resp_type(cmd)) { - case MMC_RSP_NONE: c |= RESP_NONE; break; - case MMC_RSP_R1: c |= RESP_R1; break; - case MMC_RSP_R1B: c |= RESP_R1B; break; - case MMC_RSP_R2: c |= RESP_R2; break; - case MMC_RSP_R3: c |= RESP_R3; break; - default: - return -EINVAL; - } - - /* No interrupts so this may not be cleared */ - sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND); - - sd_ctrl_write32(base, CTL_IRQ_MASK, TMIO_STAT_CMDRESPEND | - sd_ctrl_read32(base, CTL_IRQ_MASK)); - sd_ctrl_write32(base, CTL_ARG_REG, cmd->arg); - sd_ctrl_write16(base, CTL_SD_CMD, c); - - - sd_ctrl_write32(base, CTL_IRQ_MASK, - ~(TMIO_STAT_CMDRESPEND | ALL_ERROR) & - sd_ctrl_read32(base, CTL_IRQ_MASK)); - - err = sdhi_boot_wait_resp_end(base); - if (err) - return err; - - cmd->resp[0] = sd_ctrl_read32(base, CTL_RESPONSE); - - return 0; -} - -static int sdhi_boot_do_read_single(void __iomem *base, int high_capacity, - unsigned long block, unsigned short *buf) -{ - int err, i; - - /* CMD17 - Read */ - { - struct mmc_command cmd; - - cmd.opcode = MMC_READ_SINGLE_BLOCK | \ - TRANSFER_READ | DATA_PRESENT; - if (high_capacity) - cmd.arg = block; - else - cmd.arg = block * TMIO_BBS; - cmd.flags = MMC_RSP_R1; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - } - - sd_ctrl_write32(base, CTL_IRQ_MASK, - ~(TMIO_STAT_DATAEND | TMIO_STAT_RXRDY | - TMIO_STAT_TXUNDERRUN) & - sd_ctrl_read32(base, CTL_IRQ_MASK)); - err = sdhi_boot_wait_resp_end(base); - if (err) - return err; - - sd_ctrl_write16(base, CTL_SD_XFER_LEN, TMIO_BBS); - for (i = 0; i < TMIO_BBS / sizeof(*buf); i++) - *buf++ = sd_ctrl_read16(base, RESP_CMD12); - - err = sdhi_boot_wait_resp_end(base); - if (err) - return err; - - return 0; -} - -int sdhi_boot_do_read(void __iomem *base, int high_capacity, - unsigned long offset, unsigned short count, - unsigned short *buf) -{ - unsigned long i; - int err = 0; - - for (i = 0; i < count; i++) { - err = sdhi_boot_do_read_single(base, high_capacity, offset + i, - buf + (i * TMIO_BBS / - sizeof(*buf))); - if (err) - return err; - } - - return 0; -} - -#define VOLTAGES (MMC_VDD_32_33 | MMC_VDD_33_34) - -int sdhi_boot_init(void __iomem *base) -{ - bool sd_v2 = false, sd_v1_0 = false; - unsigned short cid; - int err, high_capacity = 0; - - sdhi_boot_mmc_clk_stop(base); - sdhi_boot_reset(base); - - /* mmc0: clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 21 width 0 timing 0 */ - { - struct mmc_ios ios; - ios.power_mode = MMC_POWER_ON; - ios.bus_width = MMC_BUS_WIDTH_1; - ios.clock = CLK_MMC_INIT; - err = sdhi_boot_mmc_set_ios(base, &ios); - if (err) - return err; - } - - /* CMD0 */ - { - struct mmc_command cmd; - msleep(1); - cmd.opcode = MMC_GO_IDLE_STATE; - cmd.arg = 0; - cmd.flags = MMC_RSP_NONE; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - msleep(2); - } - - /* CMD8 - Test for SD version 2 */ - { - struct mmc_command cmd; - cmd.opcode = SD_SEND_IF_COND; - cmd.arg = (VOLTAGES != 0) << 8 | 0xaa; - cmd.flags = MMC_RSP_R1; - err = sdhi_boot_request(base, &cmd); /* Ignore error */ - if ((cmd.resp[0] & 0xff) == 0xaa) - sd_v2 = true; - } - - /* CMD55 - Get OCR (SD) */ - { - int timeout = 1000; - struct mmc_command cmd; - - cmd.arg = 0; - - do { - cmd.opcode = MMC_APP_CMD; - cmd.flags = MMC_RSP_R1; - cmd.arg = 0; - err = sdhi_boot_request(base, &cmd); - if (err) - break; - - cmd.opcode = SD_APP_OP_COND; - cmd.flags = MMC_RSP_R3; - cmd.arg = (VOLTAGES & 0xff8000); - if (sd_v2) - cmd.arg |= OCR_HCS; - cmd.arg |= OCR_FASTBOOT; - err = sdhi_boot_request(base, &cmd); - if (err) - break; - - msleep(1); - } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout); - - if (!err && timeout) { - if (!sd_v2) - sd_v1_0 = true; - high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS; - } - } - - /* CMD1 - Get OCR (MMC) */ - if (!sd_v2 && !sd_v1_0) { - int timeout = 1000; - struct mmc_command cmd; - - do { - cmd.opcode = MMC_SEND_OP_COND; - cmd.arg = VOLTAGES | OCR_HCS; - cmd.flags = MMC_RSP_R3; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - - msleep(1); - } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout); - - if (!timeout) - return -EAGAIN; - - high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS; - } - - /* CMD2 - Get CID */ - { - struct mmc_command cmd; - cmd.opcode = MMC_ALL_SEND_CID; - cmd.arg = 0; - cmd.flags = MMC_RSP_R2; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - } - - /* CMD3 - * MMC: Set the relative address - * SD: Get the relative address - * Also puts the card into the standby state - */ - { - struct mmc_command cmd; - cmd.opcode = MMC_SET_RELATIVE_ADDR; - cmd.arg = 0; - cmd.flags = MMC_RSP_R1; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - cid = cmd.resp[0] >> 16; - } - - /* CMD9 - Get CSD */ - { - struct mmc_command cmd; - cmd.opcode = MMC_SEND_CSD; - cmd.arg = cid << 16; - cmd.flags = MMC_RSP_R2; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - } - - /* CMD7 - Select the card */ - { - struct mmc_command cmd; - cmd.opcode = MMC_SELECT_CARD; - //cmd.arg = rca << 16; - cmd.arg = cid << 16; - //cmd.flags = MMC_RSP_R1B; - cmd.flags = MMC_RSP_R1; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - } - - /* CMD16 - Set the block size */ - { - struct mmc_command cmd; - cmd.opcode = MMC_SET_BLOCKLEN; - cmd.arg = TMIO_BBS; - cmd.flags = MMC_RSP_R1; - err = sdhi_boot_request(base, &cmd); - if (err) - return err; - } - - return high_capacity; -} diff --git a/arch/arm/boot/compressed/sdhi-shmobile.h b/arch/arm/boot/compressed/sdhi-shmobile.h deleted file mode 100644 index 92eaa09..0000000 --- a/arch/arm/boot/compressed/sdhi-shmobile.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef SDHI_MOBILE_H -#define SDHI_MOBILE_H - -#include <linux/compiler.h> - -int sdhi_boot_do_read(void __iomem *base, int high_capacity, - unsigned long offset, unsigned short count, - unsigned short *buf); -int sdhi_boot_init(void __iomem *base); - -#endif diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d0c219d..a384cce 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -475,25 +475,23 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-smdkv210.dtb \ s5pv210-torbreck.dtb dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \ - r8a73a4-ape6evm.dtb \ - r8a73a4-ape6evm-reference.dtb \ r8a7740-armadillo800eva.dtb \ r8a7778-bockw.dtb \ r8a7778-bockw-reference.dtb \ r8a7779-marzen.dtb \ - sh7372-mackerel.dtb \ - sh73a0-kzm9g.dtb \ - sh73a0-kzm9g-reference.dtb + sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ emev2-kzm9d.dtb \ r7s72100-genmai.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \ r8a7791-henninger.dtb \ r8a7791-koelsch.dtb \ - r8a7794-alt.dtb + r8a7794-alt.dtb \ + sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk.dtb \ diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts deleted file mode 100644 index b3d8f84..0000000 --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Device Tree Source for the APE6EVM board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r8a73a4.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "APE6EVM"; - compatible = "renesas,ape6evm-reference", "renesas,r8a73a4"; - - aliases { - serial0 = &scifa0; - }; - - chosen { - bootargs = "ignore_loglevel rw"; - stdout-path = &scifa0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - vcc_mmc0: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "MMC0 Vcc"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - vcc_sdhi0: regulator@1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pfc 76 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /* Common 3.3V rail, used by several devices on APE6EVM */ - ape6evm_fixed_3v3: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - lbsc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x20000000>; - }; -}; - -&i2c5 { - status = "okay"; - vdd_dvfs: max8973@1b { - compatible = "maxim,max8973"; - reg = <0x1b>; - - regulator-min-microvolt = <935000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; - operating-points = < - /* kHz uV */ - 1950000 1115000 - 1462500 995000 - >; - voltage-tolerance = <1>; /* 1% */ -}; - -&cmt1 { - status = "okay"; -}; - -&pfc { - scifa0_pins: serial0 { - renesas,groups = "scifa0_data"; - renesas,function = "scifa0"; - }; - - mmc0_pins: mmc { - renesas,groups = "mmc0_data8", "mmc0_ctrl"; - renesas,function = "mmc0"; - }; - - sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; - renesas,function = "sdhi0"; - }; - - sdhi1_pins: sd1 { - renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; - renesas,function = "sdhi1"; - }; -}; - -&mmcif0 { - vmmc-supply = <&vcc_mmc0>; - bus-width = <8>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "okay"; -}; - -&scifa0 { - pinctrl-0 = <&scifa0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - vmmc-supply = <&vcc_sdhi0>; - bus-width = <4>; - toshiba,mmc-wrprotect-disable; - pinctrl-names = "default"; - pinctrl-0 = <&sdhi0_pins>; - status = "okay"; -}; - -&sdhi1 { - vmmc-supply = <&ape6evm_fixed_3v3>; - bus-width = <4>; - broken-cd; - toshiba,mmc-wrprotect-disable; - pinctrl-names = "default"; - pinctrl-0 = <&sdhi1_pins>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index d1b6a07..81a38ce 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -22,7 +22,7 @@ }; chosen { - bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; + bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw"; stdout-path = &scifa0; }; @@ -72,26 +72,6 @@ regulator-always-on; }; - lbsc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x20000000>; - - ethernet@8000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x08000000 0x1000>; - interrupt-parent = <&irqc1>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&ape6evm_fixed_3v3>; - vddvario-supply = <&ape6evm_fixed_1v8>; - }; - }; - leds { compatible = "gpio-leds"; led1 { @@ -188,6 +168,21 @@ voltage-tolerance = <1>; /* 1% */ }; +&bsc { + ethernet@8000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x08000000 0x1000>; + interrupt-parent = <&irqc1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&ape6evm_fixed_3v3>; + vddvario-supply = <&ape6evm_fixed_1v8>; + }; +}; + &cmt1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 38136d9..0fd889f 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -9,6 +9,7 @@ * kind, whether express or implied. */ +#include <dt-bindings/clock/r8a73a4-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -27,9 +28,15 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1500000000>; + power-domains = <&pd_a2sl>; }; }; + ptm { + compatible = "arm,coresight-etm3x"; + power-domains = <&pd_d4>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -41,11 +48,13 @@ dbsc1: memory-controller@e6790000 { compatible = "renesas,dbsc-r8a73a4"; reg = <0 0xe6790000 0 0x10000>; + power-domains = <&pd_a3bc>; }; dbsc2: memory-controller@e67a0000 { compatible = "renesas,dbsc-r8a73a4"; reg = <0 0xe67a0000 0 0x10000>; + power-domains = <&pd_a3bc>; }; dmac: dma-multiplexer { @@ -87,38 +96,19 @@ "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15", "ch16", "ch17", "ch18", "ch19"; + clocks = <&mstp2_clks R8A73A4_CLK_DMAC>; + power-domains = <&pd_a3sp>; }; }; - pfc: pfc@e6050000 { - compatible = "renesas,pfc-r8a73a4"; - reg = <0 0xe6050000 0 0x9000>; - gpio-controller; - #gpio-cells = <2>; - interrupts-extended = - <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, - <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, - <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, - <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, - <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, - <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, - <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, - <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, - <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, - <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, - <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, - <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, - <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, - <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, - <&irqc1 24 0>, <&irqc1 25 0>; - }; - i2c5: i2c@e60b0000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x428>; interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -127,6 +117,9 @@ compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; reg = <0 0xe6130000 0 0x1004>; interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; + clock-names = "fck"; + power-domains = <&pd_c5>; renesas,channels-mask = <0xff>; @@ -170,6 +163,7 @@ <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>, <0 31 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_c4>; }; irqc1: interrupt-controller@e61c0200 { @@ -203,6 +197,31 @@ <0 55 IRQ_TYPE_LEVEL_HIGH>, <0 56 IRQ_TYPE_LEVEL_HIGH>, <0 57 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_c4>; + }; + + pfc: pfc@e6050000 { + compatible = "renesas,pfc-r8a73a4"; + reg = <0 0xe6050000 0 0x9000>; + gpio-controller; + #gpio-cells = <2>; + interrupts-extended = + <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, + <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, + <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, + <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, + <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, + <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, + <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, + <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, + <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, + <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, + <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, + <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, + <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, + <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, + <&irqc1 24 0>, <&irqc1 25 0>; + power-domains = <&pd_c5>; }; thermal@e61f0000 { @@ -210,6 +229,8 @@ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; + power-domains = <&pd_c5>; }; i2c0: i2c@e6500000 { @@ -218,6 +239,8 @@ compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x428>; interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -227,6 +250,8 @@ compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x428>; interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -236,6 +261,8 @@ compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6520000 0 0x428>; interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -245,6 +272,8 @@ compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6530000 0 0x428>; interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -254,6 +283,8 @@ compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6540000 0 0x428>; interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -263,6 +294,8 @@ compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6550000 0 0x428>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -272,6 +305,8 @@ compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6560000 0 0x428>; interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -281,6 +316,8 @@ compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6570000 0 0x428>; interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -288,6 +325,9 @@ compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; + clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -295,6 +335,9 @@ compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; + clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -302,6 +345,9 @@ compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; reg = <0 0xe6c40000 0 0x100>; interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; + clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -309,6 +355,9 @@ compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; reg = <0 0xe6c50000 0 0x100>; interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; + clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -316,6 +365,9 @@ compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; + clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -323,6 +375,9 @@ compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6cf0000 0 0x100>; interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; + clock-names = "sci_ick"; + power-domains = <&pd_c4>; status = "disabled"; }; @@ -330,6 +385,8 @@ compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee100000 0 0x100>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; + power-domains = <&pd_a3sp>; cap-sd-highspeed; status = "disabled"; }; @@ -338,6 +395,8 @@ compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee120000 0 0x100>; interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; + power-domains = <&pd_a3sp>; cap-sd-highspeed; status = "disabled"; }; @@ -346,6 +405,8 @@ compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee140000 0 0x100>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; + power-domains = <&pd_a3sp>; cap-sd-highspeed; status = "disabled"; }; @@ -354,6 +415,8 @@ compatible = "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; + power-domains = <&pd_a3sp>; reg-io-width = <4>; status = "disabled"; }; @@ -362,6 +425,8 @@ compatible = "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; + power-domains = <&pd_a3sp>; reg-io-width = <4>; status = "disabled"; }; @@ -377,4 +442,450 @@ <0 0xf1006000 0 0x2000>; interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + + bsc: bus@fec10000 { + compatible = "renesas,bsc-r8a73a4", "renesas,bsc", + "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; + reg = <0 0xfec10000 0 0x400>; + clocks = <&zb_clk>; + power-domains = <&pd_c4>; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* External root clocks */ + extalr_clk: extalr_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "extalr"; + }; + extal1_clk: extal1_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "extal1"; + }; + extal2_clk: extal2_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "extal2"; + }; + fsiack_clk: fsiack_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + clock-output-names = "fsiack"; + }; + fsibck_clk: fsibck_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + clock-output-names = "fsibck"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a73a4-cpg-clocks"; + reg = <0 0xe6150000 0 0x10000>; + clocks = <&extal1_clk>, <&extal2_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll2", + "pll2s", "pll2h", "z", "z2", + "i", "m3", "b", "m1", "m2", + "zx", "zs", "hp"; + }; + + /* Variable factor clocks (DIV6) */ + zb_clk: zb_clk@e6150010 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150010 0 4>; + clocks = <&pll1_div2_clk>, <0>, + <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; + #clock-cells = <0>; + clock-output-names = "zb"; + }; + sdhi0_clk: sdhi0_clk@e6150074 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150074 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "sdhi0ck"; + }; + sdhi1_clk: sdhi1_clk@e6150078 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "sdhi1ck"; + }; + sdhi2_clk: sdhi2_clk@e615007c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615007c 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "sdhi2ck"; + }; + mmc0_clk: mmc0_clk@e6150240 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150240 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc0"; + }; + mmc1_clk: mmc1_clk@e6150244 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150244 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc1"; + }; + vclk1_clk: vclk1_clk@e6150008 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150008 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "vclk1"; + }; + vclk2_clk: vclk2_clk@e615000c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615000c 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "vclk2"; + }; + vclk3_clk: vclk3_clk@e615001c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615001c 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "vclk3"; + }; + vclk4_clk: vclk4_clk@e6150014 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150014 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "vclk4"; + }; + vclk5_clk: vclk5_clk@e6150034 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150034 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <0>, <&extal2_clk>, <&main_div2_clk>, + <&extalr_clk>, <0>, <0>; + #clock-cells = <0>; + clock-output-names = "vclk5"; + }; + fsia_clk: fsia_clk@e6150018 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150018 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <&fsiack_clk>, <0>; + #clock-cells = <0>; + clock-output-names = "fsia"; + }; + fsib_clk: fsib_clk@e6150090 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150090 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <&fsibck_clk>, <0>; + #clock-cells = <0>; + clock-output-names = "fsib"; + }; + mp_clk: mp_clk@e6150080 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150080 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <&extal2_clk>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "mp"; + }; + m4_clk: m4_clk@e6150098 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150098 0 4>; + clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; + #clock-cells = <0>; + clock-output-names = "m4"; + }; + hsi_clk: hsi_clk@e615026c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615026c 0 4>; + clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, + <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; + #clock-cells = <0>; + clock-output-names = "hsi"; + }; + spuv_clk: spuv_clk@e6150094 { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150094 0 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, + <&extal2_clk>, <&extal2_clk>; + #clock-cells = <0>; + clock-output-names = "spuv"; + }; + + /* Fixed factor clocks */ + main_div2_clk: main_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "main_div2"; + }; + pll0_div2_clk: pll0_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll0_div2"; + }; + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + extal1_div2_clk: extal1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal1_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "extal1_div2"; + }; + + /* Gate clocks */ + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 + R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 + R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 + R8A73A4_CLK_DMAC + >; + clock-output-names = + "scifa0", "scifa1", "scifb0", "scifb1", + "scifb2", "scifb3", "dmac"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, + <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, + <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, + <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks + R8A73A4_CLK_HP>, <&cpg_clocks + R8A73A4_CLK_HP>, <&extalr_clk>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 + R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 + R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 + R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 + R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 + R8A73A4_CLK_CMT1 + >; + clock-output-names = + "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", + "mmcif0", "iic6", "iic7", "iic0", "iic1", + "cmt1"; + }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>, + <&cpg_clocks R8A73A4_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 + R8A73A4_CLK_IIC3 + >; + clock-output-names = + "iic5", "iic4", "iic3"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 + >; + clock-output-names = + "thermal", "iic8"; + }; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; + reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; + + pm-domains { + pd_c5: c5 { + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_c4: c4@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3sg: a3sg@16 { + reg = <16>; + #power-domain-cells = <0>; + }; + + pd_a3ex: a3ex@17 { + reg = <17>; + #power-domain-cells = <0>; + }; + + pd_a3sp: a3sp@18 { + reg = <18>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2us: a2us@19 { + reg = <19>; + #power-domain-cells = <0>; + }; + }; + + pd_a3sm: a3sm@20 { + reg = <20>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2sl: a2sl@21 { + reg = <21>; + #power-domain-cells = <0>; + }; + }; + + pd_a3km: a3km@22 { + reg = <22>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2kl: a2kl@23 { + reg = <23>; + #power-domain-cells = <0>; + }; + }; + }; + + pd_c4ma: c4ma@1 { + reg = <1>; + #power-domain-cells = <0>; + }; + + pd_c4cl: c4cl@2 { + reg = <2>; + #power-domain-cells = <0>; + }; + + pd_d4: d4@3 { + reg = <3>; + #power-domain-cells = <0>; + }; + + pd_a4bc: a4bc@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3bc: a3bc@5 { + reg = <5>; + #power-domain-cells = <0>; + }; + }; + + pd_a4l: a4l@6 { + reg = <6>; + #power-domain-cells = <0>; + }; + + pd_a4lc: a4lc@7 { + reg = <7>; + #power-domain-cells = <0>; + }; + + pd_a4mp: a4mp@8 { + reg = <8>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3mp: a3mp@9 { + reg = <9>; + #power-domain-cells = <0>; + }; + + pd_a3vc: a3vc@10 { + reg = <10>; + #power-domain-cells = <0>; + }; + }; + + pd_a4sf: a4sf@11 { + reg = <11>; + #power-domain-cells = <0>; + }; + + pd_a3r: a3r@12 { + reg = <12>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2rv: a2rv@13 { + reg = <13>; + #power-domain-cells = <0>; + }; + + pd_a2is: a2is@14 { + reg = <14>; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts index 46a884d..787fa6f 100644 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -16,17 +16,191 @@ /dts-v1/; #include "r8a7778.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "bockw"; compatible = "renesas,bockw", "renesas,r8a7778"; + aliases { + serial0 = &scif0; + }; + chosen { bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw"; + stdout-path = &scif0; }; memory { device_type = "memory"; reg = <0x60000000 0x10000000>; }; + + fixedregulator3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + system-clock-frequency = <11289600>; + }; + }; +}; + +&bsc { + ethernet@18300000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x18300000 0x1000>; + + phy-mode = "mii"; + interrupt-parent = <&irqpin>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + reg-io-width = <4>; + vddvario-supply = <&fixedregulator3v3>; + vdd33a-supply = <&fixedregulator3v3>; + }; +}; + +&extal_clk { + clock-frequency = <33333333>; +}; + +&i2c0 { + status = "okay"; + + ak4643: sound-codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + camera@41 { + compatible = "oki,ml86v7667"; + reg = <0x41>; + }; + + camera@43 { + compatible = "oki,ml86v7667"; + reg = <0x43>; + }; + + rx8581: rtc@51 { + compatible = "epson,rx8581"; + reg = <0x51>; + }; +}; + +&mmcif { + pinctrl-0 = <&mmc_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <8>; + broken-cd; + status = "okay"; +}; + +&irqpin { + status = "okay"; +}; + +&tmu0 { + status = "okay"; +}; + +&pfc { + scif0_pins: serial0 { + renesas,groups = "scif0_data_a", "scif0_ctrl"; + renesas,function = "scif0"; + }; + + mmc_pins: mmc { + renesas,groups = "mmc_data8", "mmc_ctrl"; + renesas,function = "mmc"; + }; + + sdhi0_pins: sd0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl", + "sdhi0_cd"; + renesas,function = "sdhi0"; + }; + + hspi0_pins: hspi0 { + renesas,groups = "hspi0_a"; + renesas,function = "hspi0"; + }; + + usb0_pins: usb0 { + renesas,groups = "usb0"; + renesas,function = "usb0"; + }; + + usb1_pins: usb1 { + renesas,groups = "usb1"; + renesas,function = "usb1"; + }; + + vin0_pins: vin0 { + renesas,groups = "vin0_data8", "vin0_clk"; + renesas,function = "vin0"; + }; + + vin1_pins: vin1 { + renesas,groups = "vin1_data8", "vin1_clk"; + renesas,function = "vin1"; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <4>; + status = "okay"; + wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; +}; + +&hspi0 { + pinctrl-0 = <&hspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl008k"; + reg = <0>; + spi-max-frequency = <104000000>; + m25p,fast-read; + + partition@0 { + label = "data(spi)"; + reg = <0x00000000 0x00100000>; + }; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index ef85339..868f973 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -16,6 +16,7 @@ /include/ "skeleton.dtsi" +#include <dt-bindings/clock/r8a7778-clock.h> #include <dt-bindings/interrupt-controller/irq.h> / { @@ -40,6 +41,24 @@ spi2 = &hspi2; }; + bsc: bus@1c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1c000000>; + }; + + ether: ethernet@fde00000 { + compatible = "renesas,ether-r8a7778"; + reg = <0xfde00000 0x400>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7778_CLK_ETHER>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@fe438000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -132,6 +151,7 @@ compatible = "renesas,i2c-r8a7778"; reg = <0xffc70000 0x1000>; interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C0>; status = "disabled"; }; @@ -141,6 +161,7 @@ compatible = "renesas,i2c-r8a7778"; reg = <0xffc71000 0x1000>; interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C1>; status = "disabled"; }; @@ -150,6 +171,7 @@ compatible = "renesas,i2c-r8a7778"; reg = <0xffc72000 0x1000>; interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C2>; status = "disabled"; }; @@ -159,6 +181,7 @@ compatible = "renesas,i2c-r8a7778"; reg = <0xffc73000 0x1000>; interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_I2C3>; status = "disabled"; }; @@ -168,6 +191,8 @@ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, <0 33 IRQ_TYPE_LEVEL_HIGH>, <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_TMU0>; + clock-names = "fck"; #renesas,channels = <3>; @@ -180,6 +205,8 @@ interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, <0 37 IRQ_TYPE_LEVEL_HIGH>, <0 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_TMU1>; + clock-names = "fck"; #renesas,channels = <3>; @@ -192,16 +219,75 @@ interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, <0 41 IRQ_TYPE_LEVEL_HIGH>, <0 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_TMU2>; + clock-names = "fck"; #renesas,channels = <3>; status = "disabled"; }; + rcar_sound: sound@ffd90000 { + #sound-dai-cells = <1>; + compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1"; + reg = <0xffd90000 0x1000>, /* SRU */ + <0xffd91000 0x1240>, /* SSI */ + <0xfffe0000 0x24>; /* ADG */ + clocks = <&mstp3_clks R8A7778_CLK_SSI8>, + <&mstp3_clks R8A7778_CLK_SSI7>, + <&mstp3_clks R8A7778_CLK_SSI6>, + <&mstp3_clks R8A7778_CLK_SSI5>, + <&mstp3_clks R8A7778_CLK_SSI4>, + <&mstp0_clks R8A7778_CLK_SSI3>, + <&mstp0_clks R8A7778_CLK_SSI2>, + <&mstp0_clks R8A7778_CLK_SSI1>, + <&mstp0_clks R8A7778_CLK_SSI0>, + <&mstp5_clks R8A7778_CLK_SRU_SRC8>, + <&mstp5_clks R8A7778_CLK_SRU_SRC7>, + <&mstp5_clks R8A7778_CLK_SRU_SRC6>, + <&mstp5_clks R8A7778_CLK_SRU_SRC5>, + <&mstp5_clks R8A7778_CLK_SRU_SRC4>, + <&mstp5_clks R8A7778_CLK_SRU_SRC3>, + <&mstp5_clks R8A7778_CLK_SRU_SRC2>, + <&mstp5_clks R8A7778_CLK_SRU_SRC1>, + <&mstp5_clks R8A7778_CLK_SRU_SRC0>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg_clocks R8A7778_CLK_S1>; + clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", + "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.8", "src.7", "src.6", "src.5", "src.4", + "src.3", "src.2", "src.1", "src.0", + "clk_a", "clk_b", "clk_c", "clk_i"; + + status = "disabled"; + + rcar_sound,src { + src3: src@3 { }; + src4: src@4 { }; + src5: src@5 { }; + src6: src@6 { }; + src7: src@7 { }; + src8: src@8 { }; + src9: src@9 { }; + }; + + rcar_sound,ssi { + ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; }; + ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; }; + ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; + ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; + ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; + ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; + ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; + }; + }; + scif0: serial@ffe40000 { compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe40000 0x100>; interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF0>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -209,6 +295,8 @@ compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe41000 0x100>; interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF1>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -216,6 +304,8 @@ compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe42000 0x100>; interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF2>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -223,6 +313,8 @@ compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe43000 0x100>; interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF3>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -230,6 +322,8 @@ compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe44000 0x100>; interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF4>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -237,6 +331,8 @@ compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe45000 0x100>; interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_SCIF5>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -244,6 +340,7 @@ compatible = "renesas,sh-mmcif"; reg = <0xffe4e000 0x100>; interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7778_CLK_MMC>; status = "disabled"; }; @@ -251,6 +348,7 @@ compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4c000 0x100>; interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; status = "disabled"; }; @@ -258,6 +356,7 @@ compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4d000 0x100>; interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; status = "disabled"; }; @@ -265,6 +364,7 @@ compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4f000 0x100>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; status = "disabled"; }; @@ -272,6 +372,7 @@ compatible = "renesas,hspi-r8a7778", "renesas,hspi"; reg = <0xfffc7000 0x18>; interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_HSPI>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -281,6 +382,7 @@ compatible = "renesas,hspi-r8a7778", "renesas,hspi"; reg = <0xfffc8000 0x18>; interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_HSPI>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -290,8 +392,199 @@ compatible = "renesas,hspi-r8a7778", "renesas,hspi"; reg = <0xfffc6000 0x18>; interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7778_CLK_HSPI>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* External input clock */ + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@ffc80000 { + compatible = "renesas,r8a7778-cpg-clocks"; + reg = <0xffc80000 0x80>; + #clock-cells = <1>; + clocks = <&extal_clk>; + clock-output-names = "plla", "pllb", "b", + "out", "p", "s", "s1"; + }; + + /* Audio clocks; frequencies are set by boards if applicable. */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "audio_clk_a"; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "audio_clk_b"; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "audio_clk_c"; + }; + + /* Fixed ratio clocks */ + g_clk: g_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "g"; + }; + i_clk: i_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "i"; + }; + s3_clk: s3_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "s3"; + }; + s4_clk: s4_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "s4"; + }; + z_clk: z_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7778_CLK_PLLB>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "z"; + }; + + /* Gate clocks */ + mstp0_clks: mstp0_clks@ffc80030 { + compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xffc80030 4>; + clocks = <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_S>; + #clock-cells = <1>; + clock-indices = < + R8A7778_CLK_I2C0 R8A7778_CLK_I2C1 + R8A7778_CLK_I2C2 R8A7778_CLK_I2C3 + R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1 + R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3 + R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5 + R8A7778_CLK_TMU0 R8A7778_CLK_TMU1 + R8A7778_CLK_TMU2 R8A7778_CLK_SSI0 + R8A7778_CLK_SSI1 R8A7778_CLK_SSI2 + R8A7778_CLK_SSI3 R8A7778_CLK_SRU + R8A7778_CLK_HSPI + >; + clock-output-names = + "i2c0", "i2c1", "i2c2", "i2c3", "scif0", + "scif1", "scif2", "scif3", "scif4", "scif5", + "tmu0", "tmu1", "tmu2", "ssi0", "ssi1", + "ssi2", "ssi3", "sru", "hspi"; + }; + mstp1_clks: mstp1_clks@ffc80034 { + compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xffc80034 4>, <0xffc80044 4>; + clocks = <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_S>, + <&cpg_clocks R8A7778_CLK_S>, + <&cpg_clocks R8A7778_CLK_P>; + #clock-cells = <1>; + clock-indices = < + R8A7778_CLK_ETHER R8A7778_CLK_VIN0 + R8A7778_CLK_VIN1 R8A7778_CLK_USB + >; + clock-output-names = + "ether", "vin0", "vin1", "usb"; + }; + mstp3_clks: mstp3_clks@ffc8003c { + compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xffc8003c 4>; + clocks = <&s4_clk>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>; + #clock-cells = <1>; + clock-indices = < + R8A7778_CLK_MMC R8A7778_CLK_SDHI0 + R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2 + R8A7778_CLK_SSI4 R8A7778_CLK_SSI5 + R8A7778_CLK_SSI6 R8A7778_CLK_SSI7 + R8A7778_CLK_SSI8 + >; + clock-output-names = + "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4", + "ssi5", "ssi6", "ssi7", "ssi8"; + }; + mstp5_clks: mstp5_clks@ffc80054 { + compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xffc80054 4>; + clocks = <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>, + <&cpg_clocks R8A7778_CLK_P>; + #clock-cells = <1>; + clock-indices = < + R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1 + R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3 + R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5 + R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7 + R8A7778_CLK_SRU_SRC8 + >; + clock-output-names = + "sru-src0", "sru-src1", "sru-src2", + "sru-src3", "sru-src4", "sru-src5", + "sru-src6", "sru-src7", "sru-src8"; + }; + }; }; diff --git a/arch/arm/boot/dts/sh7372-mackerel.dts b/arch/arm/boot/dts/sh7372-mackerel.dts deleted file mode 100644 index a759a27..0000000 --- a/arch/arm/boot/dts/sh7372-mackerel.dts +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Device Tree Source for the mackerel board - * - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "sh7372.dtsi" - -/ { - model = "Mackerel (AP4 EVM 2nd)"; - compatible = "renesas,mackerel"; - - chosen { - bootargs = "console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp mem=240m rw"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x10000000>; - }; -}; diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi deleted file mode 100644 index f863a10..0000000 --- a/arch/arm/boot/dts/sh7372.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Device Tree Source for the sh7372 SoC - * - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "renesas,sh7372"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0x0>; - clock-frequency = <800000000>; - }; - }; - - pfc: pfc@e6050000 { - compatible = "renesas,pfc-sh7372"; - reg = <0xe6050000 0x8000>, - <0xe605801c 0x1c>; - gpio-controller; - #gpio-cells = <2>; - }; -}; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts deleted file mode 100644 index bf365f7..0000000 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ /dev/null @@ -1,398 +0,0 @@ -/* - * Device Tree Source for the KZM-A9-GT board - * - * Copyright (C) 2012 Horms Solutions Ltd. - * - * Based on sh73a0-kzm9g.dts - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "sh73a0.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "KZM-A9-GT"; - compatible = "renesas,kzm9g-reference", "renesas,sh73a0"; - - aliases { - serial4 = &scifa4; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vdd_dvfs>; - operating-points = < - /* kHz uV */ - 1196000 1315000 - 598000 1175000 - 398667 1065000 - >; - voltage-tolerance = <1>; /* 1% */ - }; - }; - - chosen { - bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw"; - stdout-path = &scifa4; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - reg_1p8v: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vmmc_sdhi0: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pfc 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vmmc_sdhi2: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pfc 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - lan9220@10000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x10000000 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqpin0>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - reg-io-width = <4>; - smsc,irq-push-pull; - smsc,save-mac-address; - vddvario-supply = <®_1p8v>; - vdd33a-supply = <®_3p3v>; - }; - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&pfc 20 GPIO_ACTIVE_LOW>; - label = "LED1"; - }; - led2 { - gpios = <&pfc 21 GPIO_ACTIVE_LOW>; - label = "LED2"; - }; - led3 { - gpios = <&pfc 22 GPIO_ACTIVE_LOW>; - label = "LED3"; - }; - led4 { - gpios = <&pfc 23 GPIO_ACTIVE_LOW>; - label = "LED4"; - }; - }; - - keyboard { - compatible = "gpio-keys"; - - back-key { - gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; - linux,code = <KEY_BACK>; - label = "SW3"; - }; - - right-key { - gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; - linux,code = <KEY_RIGHT>; - label = "SW2-R"; - }; - - left-key { - gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; - linux,code = <KEY_LEFT>; - label = "SW2-L"; - }; - - enter-key { - gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; - linux,code = <KEY_ENTER>; - label = "SW2-P"; - }; - - up-key { - gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; - linux,code = <KEY_UP>; - label = "SW2-U"; - }; - - down-key { - gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; - linux,code = <KEY_DOWN>; - label = "SW2-D"; - }; - - home-key { - gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; - linux,code = <KEY_HOME>; - label = "SW1"; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "left_j"; - simple-audio-card,cpu { - sound-dai = <&sh_fsi2 0>; - }; - simple-audio-card,codec { - sound-dai = <&ak4648>; - bitclock-master; - frame-master; - system-clock-frequency = <11289600>; - }; - }; -}; - -&cmt1 { - status = "okay"; -}; - -&extal2_clk { - clock-frequency = <48000000>; -}; - -&i2c0 { - status = "okay"; - - compass@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - interrupt-parent = <&irqpin3>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - }; - - ak4648: codec@12 { - compatible = "asahi-kasei,ak4648"; - reg = <0x12>; - #sound-dai-cells = <0>; - }; - - accelerometer@1d { - compatible = "adi,adxl34x"; - reg = <0x1d>; - interrupt-parent = <&irqpin3>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, - <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - rtc@32 { - compatible = "ricoh,r2025sd"; - reg = <0x32>; - }; - - as3711@40 { - compatible = "ams,as3711"; - reg = <0x40>; - - regulators { - vdd_dvfs: sd1 { - regulator-name = "1.315V CPU"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - sd2 { - regulator-name = "1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - sd4 { - regulator-name = "1.215V"; - regulator-min-microvolt = <1215000>; - regulator-max-microvolt = <1235000>; - regulator-always-on; - regulator-boot-on; - }; - ldo2 { - regulator-name = "2.8V CPU"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo3 { - regulator-name = "3.0V CPU"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - }; - ldo4 { - regulator-name = "2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo5 { - regulator-name = "2.8V #2"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - }; - ldo7 { - regulator-name = "1.15V CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - ldo8 { - regulator-name = "1.15V CPU #2"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - touchscreen@55 { - compatible = "sitronix,st1232"; - reg = <0x55>; - interrupt-parent = <&irqpin1>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - status = "okay"; - - pcf8575: gpio@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - interrupt-parent = <&irqpin2>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&mmcif { - pinctrl-0 = <&mmcif_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - vmmc-supply = <®_1p8v>; - status = "okay"; -}; - -&pfc { - i2c3_pins: i2c3 { - renesas,groups = "i2c3_1"; - renesas,function = "i2c3"; - }; - - mmcif_pins: mmc { - mux { - renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; - renesas,function = "mmc0"; - }; - cfg { - renesas,groups = "mmc0_data8_0"; - renesas,pins = "PORT279"; - bias-pull-up; - }; - }; - - scifa4_pins: serial4 { - renesas,groups = "scifa4_data", "scifa4_ctrl"; - renesas,function = "scifa4"; - }; - - sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; - renesas,function = "sdhi0"; - }; - - sdhi2_pins: sd2 { - renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; - renesas,function = "sdhi2"; - }; - - fsia_pins: sounda { - renesas,groups = "fsia_mclk_in", "fsia_sclk_in", - "fsia_data_in", "fsia_data_out"; - renesas,function = "fsia"; - }; -}; - -&scifa4 { - pinctrl-0 = <&scifa4_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vmmc_sdhi0>; - bus-width = <4>; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vmmc_sdhi2>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&sh_fsi2 { - pinctrl-0 = <&fsia_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index e7dae01..022ba50 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -1,6 +1,9 @@ /* * Device Tree Source for the KZM-A9-GT board * + * Copyright (C) 2012 Horms Solutions Ltd. + * + * Based on sh73a0-kzm9g.dts * Copyright (C) 2012 Renesas Solutions Corp. * * This file is licensed under the terms of the GNU General Public License @@ -10,17 +13,388 @@ /dts-v1/; #include "sh73a0.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> / { model = "KZM-A9-GT"; compatible = "renesas,kzm9g", "renesas,sh73a0"; + aliases { + serial4 = &scifa4; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd_dvfs>; + operating-points = < + /* kHz uV */ + 1196000 1315000 + 598000 1175000 + 398667 1065000 + >; + voltage-tolerance = <1>; /* 1% */ + }; + }; + chosen { - bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200 rw"; + bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw"; + stdout-path = &scifa4; }; memory { device_type = "memory"; reg = <0x40000000 0x20000000>; }; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc_sdhi0: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pfc 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vmmc_sdhi2: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pfc 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + leds { + compatible = "gpio-leds"; + led1 { + gpios = <&pfc 20 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + led2 { + gpios = <&pfc 21 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + led3 { + gpios = <&pfc 22 GPIO_ACTIVE_LOW>; + label = "LED3"; + }; + led4 { + gpios = <&pfc 23 GPIO_ACTIVE_LOW>; + label = "LED4"; + }; + }; + + keyboard { + compatible = "gpio-keys"; + + back-key { + gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; + linux,code = <KEY_BACK>; + label = "SW3"; + }; + + right-key { + gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RIGHT>; + label = "SW2-R"; + }; + + left-key { + gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; + linux,code = <KEY_LEFT>; + label = "SW2-L"; + }; + + enter-key { + gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + label = "SW2-P"; + }; + + up-key { + gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + label = "SW2-U"; + }; + + down-key { + gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + label = "SW2-D"; + }; + + home-key { + gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOME>; + label = "SW1"; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "left_j"; + simple-audio-card,cpu { + sound-dai = <&sh_fsi2 0>; + }; + simple-audio-card,codec { + sound-dai = <&ak4648>; + bitclock-master; + frame-master; + system-clock-frequency = <11289600>; + }; + }; +}; + +&bsc { + ethernet@10000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x10000000 0x100>; + phy-mode = "mii"; + interrupt-parent = <&irqpin0>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + reg-io-width = <4>; + smsc,irq-push-pull; + smsc,save-mac-address; + vddvario-supply = <®_1p8v>; + vdd33a-supply = <®_3p3v>; + }; +}; + +&cmt1 { + status = "okay"; +}; + +&extal2_clk { + clock-frequency = <48000000>; +}; + +&i2c0 { + status = "okay"; + + compass@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + interrupt-parent = <&irqpin3>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + }; + + ak4648: codec@12 { + compatible = "asahi-kasei,ak4648"; + reg = <0x12>; + #sound-dai-cells = <0>; + }; + + accelerometer@1d { + compatible = "adi,adxl34x"; + reg = <0x1d>; + interrupt-parent = <&irqpin3>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>; + }; + + rtc@32 { + compatible = "ricoh,r2025sd"; + reg = <0x32>; + }; + + as3711@40 { + compatible = "ams,as3711"; + reg = <0x40>; + + regulators { + vdd_dvfs: sd1 { + regulator-name = "1.315V CPU"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + sd2 { + regulator-name = "1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + sd4 { + regulator-name = "1.215V"; + regulator-min-microvolt = <1215000>; + regulator-max-microvolt = <1235000>; + regulator-always-on; + regulator-boot-on; + }; + ldo2 { + regulator-name = "2.8V CPU"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + ldo3 { + regulator-name = "3.0V CPU"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + ldo4 { + regulator-name = "2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + ldo5 { + regulator-name = "2.8V #2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + ldo7 { + regulator-name = "1.15V CPU"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + ldo8 { + regulator-name = "1.15V CPU #2"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + touchscreen@55 { + compatible = "sitronix,st1232"; + reg = <0x55>; + interrupt-parent = <&irqpin1>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + status = "okay"; + + pcf8575: gpio@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + interrupt-parent = <&irqpin2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&mmcif { + pinctrl-0 = <&mmcif_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + vmmc-supply = <®_1p8v>; + status = "okay"; +}; + +&pfc { + i2c3_pins: i2c3 { + renesas,groups = "i2c3_1"; + renesas,function = "i2c3"; + }; + + mmcif_pins: mmc { + mux { + renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; + renesas,function = "mmc0"; + }; + cfg { + renesas,groups = "mmc0_data8_0"; + renesas,pins = "PORT279"; + bias-pull-up; + }; + }; + + scifa4_pins: serial4 { + renesas,groups = "scifa4_data", "scifa4_ctrl"; + renesas,function = "scifa4"; + }; + + sdhi0_pins: sd0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; + renesas,function = "sdhi0"; + }; + + sdhi2_pins: sd2 { + renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; + renesas,function = "sdhi2"; + }; + + fsia_pins: sounda { + renesas,groups = "fsia_mclk_in", "fsia_sclk_in", + "fsia_data_in", "fsia_data_out"; + renesas,function = "fsia"; + }; +}; + +&scifa4 { + pinctrl-0 = <&scifa4_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vmmc_sdhi0>; + bus-width = <4>; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vmmc_sdhi2>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; + +&sh_fsi2 { + pinctrl-0 = <&fsia_pins>; + pinctrl-names = "default"; + + status = "okay"; }; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index ab319b7..45b539c 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -11,6 +11,7 @@ /include/ "skeleton.dtsi" #include <dt-bindings/clock/sh73a0-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> / { @@ -26,15 +27,24 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <1196000000>; + power-domains = <&pd_a2sl>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; clock-frequency = <1196000000>; + power-domains = <&pd_a2sl>; }; }; + timer@f0000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf0000600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&twd_clk>; + }; + gic: interrupt-controller@f0001000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -49,6 +59,7 @@ interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>, <0 38 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "sec", "temp"; + power-domains = <&pd_a4bc1>; }; sbsc1: memory-controller@fe400000 { @@ -57,6 +68,7 @@ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, <0 36 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "sec", "temp"; + power-domains = <&pd_a4bc0>; }; pmu { @@ -69,11 +81,12 @@ compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; reg = <0xe6138000 0x200>; interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks SH73A0_CLK_CMT1>; + clock-names = "fck"; + power-domains = <&pd_c5>; renesas,channels-mask = <0x3f>; - clocks = <&mstp3_clks SH73A0_CLK_CMT1>; - clock-names = "fck"; status = "disabled"; }; @@ -95,6 +108,7 @@ 0 7 IRQ_TYPE_LEVEL_HIGH 0 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; + power-domains = <&pd_a4s>; control-parent; }; @@ -116,6 +130,7 @@ 0 15 IRQ_TYPE_LEVEL_HIGH 0 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; + power-domains = <&pd_a4s>; control-parent; }; @@ -137,6 +152,7 @@ 0 23 IRQ_TYPE_LEVEL_HIGH 0 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; + power-domains = <&pd_a4s>; control-parent; }; @@ -158,6 +174,7 @@ 0 31 IRQ_TYPE_LEVEL_HIGH 0 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; + power-domains = <&pd_a4s>; control-parent; }; @@ -171,6 +188,7 @@ 0 169 IRQ_TYPE_LEVEL_HIGH 0 170 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks SH73A0_CLK_IIC0>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -184,6 +202,7 @@ 0 53 IRQ_TYPE_LEVEL_HIGH 0 54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_IIC1>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -197,6 +216,7 @@ 0 173 IRQ_TYPE_LEVEL_HIGH 0 174 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks SH73A0_CLK_IIC2>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -210,6 +230,7 @@ 0 185 IRQ_TYPE_LEVEL_HIGH 0 186 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks SH73A0_CLK_IIC3>; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -223,6 +244,7 @@ 0 189 IRQ_TYPE_LEVEL_HIGH 0 190 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks SH73A0_CLK_IIC4>; + power-domains = <&pd_c5>; status = "disabled"; }; @@ -232,6 +254,7 @@ interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH 0 141 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; + power-domains = <&pd_a3sp>; reg-io-width = <4>; status = "disabled"; }; @@ -243,6 +266,7 @@ 0 84 IRQ_TYPE_LEVEL_HIGH 0 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; + power-domains = <&pd_a3sp>; cap-sd-highspeed; status = "disabled"; }; @@ -254,6 +278,7 @@ interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH 0 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; + power-domains = <&pd_a3sp>; toshiba,mmc-wrprotect-disable; cap-sd-highspeed; status = "disabled"; @@ -265,6 +290,7 @@ interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH 0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; + power-domains = <&pd_a3sp>; toshiba,mmc-wrprotect-disable; cap-sd-highspeed; status = "disabled"; @@ -276,6 +302,7 @@ interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -285,6 +312,7 @@ interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -294,6 +322,7 @@ interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -303,6 +332,7 @@ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -312,6 +342,7 @@ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -321,6 +352,7 @@ interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -330,6 +362,7 @@ interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -339,6 +372,7 @@ interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -348,6 +382,7 @@ interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; clock-names = "sci_ick"; + power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -366,6 +401,117 @@ <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; + power-domains = <&pd_c5>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile"; + reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; + + pm-domains { + pd_c5: c5 { + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_c4: c4@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + + pd_d4: d4@1 { + reg = <1>; + #power-domain-cells = <0>; + }; + + pd_a4bc0: a4bc0@4 { + reg = <4>; + #power-domain-cells = <0>; + }; + + pd_a4bc1: a4bc1@5 { + reg = <5>; + #power-domain-cells = <0>; + }; + + pd_a4lc0: a4lc0@6 { + reg = <6>; + #power-domain-cells = <0>; + }; + + pd_a4lc1: a4lc1@7 { + reg = <7>; + #power-domain-cells = <0>; + }; + + pd_a4mp: a4mp@8 { + reg = <8>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3mp: a3mp@9 { + reg = <9>; + #power-domain-cells = <0>; + }; + + pd_a3vc: a3vc@10 { + reg = <10>; + #power-domain-cells = <0>; + }; + }; + + pd_a4rm: a4rm@12 { + reg = <12>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3r: a3r@13 { + reg = <13>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2rv: a2rv@14 { + reg = <14>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + }; + }; + }; + + pd_a4s: a4s@16 { + reg = <16>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3sp: a3sp@17 { + reg = <17>; + #power-domain-cells = <0>; + }; + + pd_a3sg: a3sg@18 { + reg = <18>; + #power-domain-cells = <0>; + }; + + pd_a3sm: a3sm@19 { + reg = <19>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a2sl: a2sl@20 { + reg = <20>; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; }; sh_fsi2: sound@ec230000 { @@ -373,9 +519,22 @@ compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; reg = <0xec230000 0x400>; interrupts = <0 146 0x4>; + power-domains = <&pd_a4mp>; status = "disabled"; }; + bsc: bus@fec10000 { + compatible = "renesas,bsc-sh73a0", "renesas,bsc", + "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20000000>; + reg = <0xfec10000 0x400>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&zb_clk>; + power-domains = <&pd_a4s>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig deleted file mode 100644 index 9e9a72e..0000000 --- a/arch/arm/configs/ape6evm_defconfig +++ /dev/null @@ -1,109 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_CGROUPS=y -CONFIG_CGROUP_SCHED=y -CONFIG_KALLSYMS_ALL=y -CONFIG_EMBEDDED=y -CONFIG_PERF_EVENTS=y -CONFIG_SLAB=y -CONFIG_ARCH_SHMOBILE_LEGACY=y -CONFIG_ARCH_R8A73A4=y -CONFIG_MACH_APE6EVM=y -# CONFIG_ARM_THUMB is not set -CONFIG_CPU_BPREDICT_DISABLE=y -CONFIG_PL310_ERRATA_588369=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_SMP=y -CONFIG_SCHED_MC=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_NR_CPUS=8 -CONFIG_AEABI=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -# CONFIG_HW_PERF_EVENTS is not set -# CONFIG_COMPACTION is not set -# CONFIG_CROSS_MEMORY_ATTACH is not set -CONFIG_ARM_APPENDED_DTB=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6_SIT is not set -CONFIG_NETFILTER=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_FW_LOADER_USER_HELPER is not set -CONFIG_NETDEVICES=y -# CONFIG_NET_CADENCE is not set -CONFIG_SMC91X=y -CONFIG_SMSC911X=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_NONSTANDARD=y -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_NR_UARTS=12 -CONFIG_SERIAL_SH_SCI_CONSOLE=y -CONFIG_I2C=y -CONFIG_I2C_SH_MOBILE=y -CONFIG_GPIO_SH_PFC=y -CONFIG_GPIOLIB=y -# CONFIG_HWMON is not set -CONFIG_THERMAL=y -CONFIG_RCAR_THERMAL=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_MAX8973=y -# CONFIG_HID is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_SDHI=y -CONFIG_MMC_SH_MMCIF=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_DMADEVICES=y -CONFIG_SH_DMAE=y -# CONFIG_IOMMU_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_ROOT_NFS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_ENABLE_DEFAULT_TRACERS=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 811e72b..bcef49a 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -13,10 +13,13 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_MULTI_V4T=y +CONFIG_ARCH_MULTI_V5=y +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_AT91=y +CONFIG_SOC_SAM_V4_V5=y CONFIG_SOC_AT91RM9200=y CONFIG_SOC_AT91SAM9=y -CONFIG_AT91_TIMER_HZ=128 CONFIG_AEABI=y CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig deleted file mode 100644 index 05a5293..0000000 --- a/arch/arm/configs/mackerel_defconfig +++ /dev/null @@ -1,157 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -# CONFIG_UTS_NS is not set -# CONFIG_IPC_NS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set -# CONFIG_NET_NS is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_SHMOBILE_LEGACY=y -CONFIG_ARCH_SH7372=y -CONFIG_MACH_MACKEREL=y -CONFIG_MEMORY_SIZE=0x10000000 -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_FORCE_MAX_ZONEORDER=15 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ARM_APPENDED_DTB=y -CONFIG_KEXEC=y -CONFIG_VFP=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_ARM_INTEGRATOR=y -CONFIG_MTD_BLOCK2MTD=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMSC911X=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_NR_UARTS=8 -CONFIG_SERIAL_SH_SCI_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_SH_MOBILE=y -# CONFIG_HWMON is not set -# CONFIG_MFD_SUPPORT is not set -CONFIG_REGULATOR=y -CONFIG_FB=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_SH_MOBILE_LCDC=y -CONFIG_FB_SH_MOBILE_HDMI=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_CLUT224 is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -CONFIG_SND_SOC_SH4_FSI=y -CONFIG_USB=y -CONFIG_USB_RENESAS_USBHS_HCD=y -CONFIG_USB_RENESAS_USBHS=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_RENESAS_USBHS_UDC=y -CONFIG_MMC=y -CONFIG_MMC_SDHI=y -CONFIG_MMC_SH_MMCIF=y -CONFIG_DMADEVICES=y -CONFIG_SH_DMAE=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT2_FS_XIP=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=y -CONFIG_NLS_CODEPAGE_775=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_CODEPAGE_852=y -CONFIG_NLS_CODEPAGE_855=y -CONFIG_NLS_CODEPAGE_857=y -CONFIG_NLS_CODEPAGE_860=y -CONFIG_NLS_CODEPAGE_861=y -CONFIG_NLS_CODEPAGE_862=y -CONFIG_NLS_CODEPAGE_863=y -CONFIG_NLS_CODEPAGE_864=y -CONFIG_NLS_CODEPAGE_865=y -CONFIG_NLS_CODEPAGE_866=y -CONFIG_NLS_CODEPAGE_869=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=y -CONFIG_NLS_ISO8859_3=y -CONFIG_NLS_ISO8859_4=y -CONFIG_NLS_ISO8859_5=y -CONFIG_NLS_ISO8859_6=y -CONFIG_NLS_ISO8859_7=y -CONFIG_NLS_ISO8859_9=y -CONFIG_NLS_ISO8859_13=y -CONFIG_NLS_ISO8859_14=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_KOI8_R=y -CONFIG_NLS_KOI8_U=y -CONFIG_NLS_UTF8=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_ARM_UNWIND is not set -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ANSI_CPRNG=y diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 24b59c7..fd95f34 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -1,55 +1,15 @@ -if ARCH_AT91 - -config HAVE_AT91_UTMI - bool - -config HAVE_AT91_USB_CLK - bool - -config COMMON_CLK_AT91 - bool - select COMMON_CLK - -config HAVE_AT91_SMD - bool - -config HAVE_AT91_H32MX - bool - -config SOC_SAMA5 - bool - select ATMEL_AIC5_IRQ +menuconfig ARCH_AT91 + bool "Atmel SoCs" + depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7 + select ARCH_REQUIRE_GPIOLIB select COMMON_CLK_AT91 - select CPU_V7 - select GENERIC_CLOCKEVENTS - select MEMORY - select ATMEL_SDRAMC - select SRAM if PM - -menu "Atmel AT91 System-on-Chip" - -choice - - prompt "Core type" - -config SOC_SAM_V4_V5 - bool "ARM9 AT91SAM9/AT91RM9200" - help - Select this if you are using one of Atmel's AT91SAM9 or - AT91RM9200 SoC. - -config SOC_SAM_V7 - bool "Cortex A5" - help - Select this if you are using one of Atmel's SAMA5D3 SoC. + select PINCTRL + select PINCTRL_AT91 + select SOC_BUS -endchoice - -comment "Atmel AT91 Processor" - -if SOC_SAM_V7 +if ARCH_AT91 config SOC_SAMA5D3 - bool "SAMA5D3 family" + bool "SAMA5D3 family" if ARCH_MULTI_V7 select SOC_SAMA5 select HAVE_FB_ATMEL select HAVE_AT91_UTMI @@ -60,9 +20,8 @@ config SOC_SAMA5D3 This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36. config SOC_SAMA5D4 - bool "SAMA5D4 family" + bool "SAMA5D4 family" if ARCH_MULTI_V7 select SOC_SAMA5 - select CLKSRC_MMIO select CACHE_L2X0 select HAVE_FB_ATMEL select HAVE_AT91_UTMI @@ -71,32 +30,30 @@ config SOC_SAMA5D4 select HAVE_AT91_H32MX help Select this if you are using one of Atmel's SAMA5D4 family SoC. -endif -if SOC_SAM_V4_V5 config SOC_AT91RM9200 - bool "AT91RM9200" + bool "AT91RM9200" if ARCH_MULTI_V4T select ATMEL_AIC_IRQ select ATMEL_ST - select COMMON_CLK_AT91 select CPU_ARM920T - select GENERIC_CLOCKEVENTS select HAVE_AT91_USB_CLK select MIGHT_HAVE_PCI + select SOC_SAM_V4_V5 select SRAM if PM + help + Select this if you are using Atmel's AT91RM9200 SoC. config SOC_AT91SAM9 - bool "AT91SAM9" + bool "AT91SAM9" if ARCH_MULTI_V5 select ATMEL_AIC_IRQ select ATMEL_SDRAMC - select COMMON_CLK_AT91 select CPU_ARM926T - select GENERIC_CLOCKEVENTS select HAVE_AT91_SMD select HAVE_AT91_USB_CLK select HAVE_AT91_UTMI select HAVE_FB_ATMEL select MEMORY + select SOC_SAM_V4_V5 select SRAM if PM help Select this if you are using one of those Atmel SoC: @@ -116,26 +73,35 @@ config SOC_AT91SAM9 AT91SAM9X25 AT91SAM9X35 AT91SAM9XE -endif # SOC_SAM_V4_V5 -comment "AT91 Feature Selections" +config HAVE_AT91_UTMI + bool + +config HAVE_AT91_USB_CLK + bool + +config COMMON_CLK_AT91 + bool + select COMMON_CLK + +config HAVE_AT91_SMD + bool + +config HAVE_AT91_H32MX + bool -config AT91_TIMER_HZ - int "Kernel HZ (jiffies per second)" - range 32 1024 - depends on ARCH_AT91 - default "128" if SOC_AT91RM9200 - default "100" - help - On AT91rm9200 chips where you're using a system clock derived - from the 32768 Hz hardware clock, this tick rate should divide - it exactly: use a power-of-two value, such as 128 or 256, to - reduce timing errors caused by rounding. +config SOC_SAM_V4_V5 + bool - On AT91sam926x chips, or otherwise when using a higher precision - system clock (of at least several MHz), rounding is less of a - problem so it can be safer to use a decimal values like 100. +config SOC_SAM_V7 + bool -endmenu +config SOC_SAMA5 + bool + select ATMEL_AIC5_IRQ + select ATMEL_SDRAMC + select MEMORY + select SOC_SAM_V7 + select SRAM if PM endif diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 38aaef7..4fa8b45 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,6 +1,8 @@ # # Makefile for the linux kernel. # +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include +asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include obj-y := soc.o @@ -15,6 +17,9 @@ obj-$(CONFIG_SOC_SAMA5) += sama5.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += pm_suspend.o +ifeq ($(CONFIG_CPU_V7),y) +AFLAGS_pm_suspend.o := -march=armv7-a +endif ifeq ($(CONFIG_PM_DEBUG),y) CFLAGS_pm.o += -DDEBUG endif diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h deleted file mode 100644 index 42925e8..0000000 --- a/arch/arm/mach-at91/include/mach/at91_dbgu.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91_dbgu.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Debug Unit (DBGU) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_DBGU_H -#define AT91_DBGU_H - -#define AT91_DBGU_CR (0x00) /* Control Register */ -#define AT91_DBGU_MR (0x04) /* Mode Register */ -#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ -#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ -#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ -#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */ -#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */ -#define AT91_DBGU_SR (0x14) /* Status Register */ -#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */ -#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */ -#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */ - -#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */ -#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */ -#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */ -#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ - -/* - * Some AT91 parts that don't have full DEBUG units still support the ID - * and extensions register. - */ -#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ -#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ -#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ -#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ -#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ -#define AT91_CIDR_SRAMSIZ_1K (1 << 16) -#define AT91_CIDR_SRAMSIZ_2K (2 << 16) -#define AT91_CIDR_SRAMSIZ_112K (4 << 16) -#define AT91_CIDR_SRAMSIZ_4K (5 << 16) -#define AT91_CIDR_SRAMSIZ_80K (6 << 16) -#define AT91_CIDR_SRAMSIZ_160K (7 << 16) -#define AT91_CIDR_SRAMSIZ_8K (8 << 16) -#define AT91_CIDR_SRAMSIZ_16K (9 << 16) -#define AT91_CIDR_SRAMSIZ_32K (10 << 16) -#define AT91_CIDR_SRAMSIZ_64K (11 << 16) -#define AT91_CIDR_SRAMSIZ_128K (12 << 16) -#define AT91_CIDR_SRAMSIZ_256K (13 << 16) -#define AT91_CIDR_SRAMSIZ_96K (14 << 16) -#define AT91_CIDR_SRAMSIZ_512K (15 << 16) -#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ -#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ -#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h index e4492b1..493bc48 100644 --- a/arch/arm/mach-at91/include/mach/at91_ramc.h +++ b/arch/arm/mach-at91/include/mach/at91_ramc.h @@ -21,10 +21,6 @@ extern void __iomem *at91_ramc_base[]; .extern at91_ramc_base #endif -#define AT91_MEMCTRL_MC 0 -#define AT91_MEMCTRL_SDRAMC 1 -#define AT91_MEMCTRL_DDRSDR 2 - #include <soc/at91/at91rm9200_sdramc.h> #include <soc/at91/at91sam9_ddrsdr.h> #include <soc/at91/at91sam9_sdramc.h> diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h deleted file mode 100644 index e67317c..0000000 --- a/arch/arm/mach-at91/include/mach/at91rm9200.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91rm9200.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Common definitions. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91RM9200_H -#define AT91RM9200_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */ -#define AT91RM9200_ID_US0 6 /* USART 0 */ -#define AT91RM9200_ID_US1 7 /* USART 1 */ -#define AT91RM9200_ID_US2 8 /* USART 2 */ -#define AT91RM9200_ID_US3 9 /* USART 3 */ -#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */ -#define AT91RM9200_ID_UDP 11 /* USB Device Port */ -#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */ -#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */ -#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */ -#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */ -#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */ -#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */ -#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */ -#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */ -#define AT91RM9200_ID_UHP 23 /* USB Host port */ -#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */ -#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ -#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ -#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ -#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ -#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ - - -/* - * Peripheral physical base addresses. - */ -#define AT91RM9200_BASE_TCB0 0xfffa0000 -#define AT91RM9200_BASE_TC0 0xfffa0000 -#define AT91RM9200_BASE_TC1 0xfffa0040 -#define AT91RM9200_BASE_TC2 0xfffa0080 -#define AT91RM9200_BASE_TCB1 0xfffa4000 -#define AT91RM9200_BASE_TC3 0xfffa4000 -#define AT91RM9200_BASE_TC4 0xfffa4040 -#define AT91RM9200_BASE_TC5 0xfffa4080 -#define AT91RM9200_BASE_UDP 0xfffb0000 -#define AT91RM9200_BASE_MCI 0xfffb4000 -#define AT91RM9200_BASE_TWI 0xfffb8000 -#define AT91RM9200_BASE_EMAC 0xfffbc000 -#define AT91RM9200_BASE_US0 0xfffc0000 -#define AT91RM9200_BASE_US1 0xfffc4000 -#define AT91RM9200_BASE_US2 0xfffc8000 -#define AT91RM9200_BASE_US3 0xfffcc000 -#define AT91RM9200_BASE_SSC0 0xfffd0000 -#define AT91RM9200_BASE_SSC1 0xfffd4000 -#define AT91RM9200_BASE_SSC2 0xfffd8000 -#define AT91RM9200_BASE_SPI 0xfffe0000 - - -/* - * System Peripherals - */ -#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */ -#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */ -#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */ -#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */ -#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */ -#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */ -#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ -#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */ - -/* - * Internal Memory. - */ -#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */ -#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ - -#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */ - - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h deleted file mode 100644 index 416c7b6..0000000 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9260.h - * - * (C) 2006 Andrew Victor - * - * Common definitions. - * Based on AT91SAM9260 datasheet revision A (Preliminary). - * - * Includes also definitions for AT91SAM9XE and AT91SAM9G families - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9260_H -#define AT91SAM9260_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ -#define AT91SAM9260_ID_US0 6 /* USART 0 */ -#define AT91SAM9260_ID_US1 7 /* USART 1 */ -#define AT91SAM9260_ID_US2 8 /* USART 2 */ -#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ -#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9260_ID_UHP 20 /* USB Host port */ -#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ -#define AT91SAM9260_ID_US3 23 /* USART 3 */ -#define AT91SAM9260_ID_US4 24 /* USART 4 */ -#define AT91SAM9260_ID_US5 25 /* USART 5 */ -#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ -#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ -#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ -#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9260_BASE_TCB0 0xfffa0000 -#define AT91SAM9260_BASE_TC0 0xfffa0000 -#define AT91SAM9260_BASE_TC1 0xfffa0040 -#define AT91SAM9260_BASE_TC2 0xfffa0080 -#define AT91SAM9260_BASE_UDP 0xfffa4000 -#define AT91SAM9260_BASE_MCI 0xfffa8000 -#define AT91SAM9260_BASE_TWI 0xfffac000 -#define AT91SAM9260_BASE_US0 0xfffb0000 -#define AT91SAM9260_BASE_US1 0xfffb4000 -#define AT91SAM9260_BASE_US2 0xfffb8000 -#define AT91SAM9260_BASE_SSC 0xfffbc000 -#define AT91SAM9260_BASE_ISI 0xfffc0000 -#define AT91SAM9260_BASE_EMAC 0xfffc4000 -#define AT91SAM9260_BASE_SPI0 0xfffc8000 -#define AT91SAM9260_BASE_SPI1 0xfffcc000 -#define AT91SAM9260_BASE_US3 0xfffd0000 -#define AT91SAM9260_BASE_US4 0xfffd4000 -#define AT91SAM9260_BASE_US5 0xfffd8000 -#define AT91SAM9260_BASE_TCB1 0xfffdc000 -#define AT91SAM9260_BASE_TC3 0xfffdc000 -#define AT91SAM9260_BASE_TC4 0xfffdc040 -#define AT91SAM9260_BASE_TC5 0xfffdc080 -#define AT91SAM9260_BASE_ADC 0xfffe0000 - -/* - * System Peripherals - */ -#define AT91SAM9260_BASE_ECC 0xffffe800 -#define AT91SAM9260_BASE_SDRAMC 0xffffea00 -#define AT91SAM9260_BASE_SMC 0xffffec00 -#define AT91SAM9260_BASE_MATRIX 0xffffee00 -#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0 -#define AT91SAM9260_BASE_PIOA 0xfffff400 -#define AT91SAM9260_BASE_PIOB 0xfffff600 -#define AT91SAM9260_BASE_PIOC 0xfffff800 -#define AT91SAM9260_BASE_RSTC 0xfffffd00 -#define AT91SAM9260_BASE_SHDWC 0xfffffd10 -#define AT91SAM9260_BASE_RTT 0xfffffd20 -#define AT91SAM9260_BASE_PIT 0xfffffd30 -#define AT91SAM9260_BASE_WDT 0xfffffd40 -#define AT91SAM9260_BASE_GPBR 0xfffffd50 - - -/* - * Internal Memory. - */ -#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ -#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ -#define AT91SAM9260_SRAM_BASE 0x002FF000 /* Internal SRAM base address */ -#define AT91SAM9260_SRAM_SIZE SZ_8K /* Internal SRAM size (8Kb) */ - -#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ - -#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ -#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ - -#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */ -#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ -#define AT91SAM9G20_SRAM_BASE 0x002FC000 /* Internal SRAM base address */ -#define AT91SAM9G20_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ - -#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h deleted file mode 100644 index a041406..0000000 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9261.h - * - * Copyright (C) SAN People - * - * Common definitions. - * Based on AT91SAM9261 datasheet revision E. (Preliminary) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9261_H -#define AT91SAM9261_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9261_ID_US0 6 /* USART 0 */ -#define AT91SAM9261_ID_US1 7 /* USART 1 */ -#define AT91SAM9261_ID_US2 8 /* USART 2 */ -#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9261_ID_UHP 20 /* USB Host port */ -#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ -#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9261_BASE_TCB0 0xfffa0000 -#define AT91SAM9261_BASE_TC0 0xfffa0000 -#define AT91SAM9261_BASE_TC1 0xfffa0040 -#define AT91SAM9261_BASE_TC2 0xfffa0080 -#define AT91SAM9261_BASE_UDP 0xfffa4000 -#define AT91SAM9261_BASE_MCI 0xfffa8000 -#define AT91SAM9261_BASE_TWI 0xfffac000 -#define AT91SAM9261_BASE_US0 0xfffb0000 -#define AT91SAM9261_BASE_US1 0xfffb4000 -#define AT91SAM9261_BASE_US2 0xfffb8000 -#define AT91SAM9261_BASE_SSC0 0xfffbc000 -#define AT91SAM9261_BASE_SSC1 0xfffc0000 -#define AT91SAM9261_BASE_SSC2 0xfffc4000 -#define AT91SAM9261_BASE_SPI0 0xfffc8000 -#define AT91SAM9261_BASE_SPI1 0xfffcc000 - - -/* - * System Peripherals - */ -#define AT91SAM9261_BASE_SMC 0xffffec00 -#define AT91SAM9261_BASE_MATRIX 0xffffee00 -#define AT91SAM9261_BASE_SDRAMC 0xffffea00 -#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 -#define AT91SAM9261_BASE_PIOA 0xfffff400 -#define AT91SAM9261_BASE_PIOB 0xfffff600 -#define AT91SAM9261_BASE_PIOC 0xfffff800 -#define AT91SAM9261_BASE_RSTC 0xfffffd00 -#define AT91SAM9261_BASE_SHDWC 0xfffffd10 -#define AT91SAM9261_BASE_RTT 0xfffffd20 -#define AT91SAM9261_BASE_PIT 0xfffffd30 -#define AT91SAM9261_BASE_WDT 0xfffffd40 -#define AT91SAM9261_BASE_GPBR 0xfffffd50 - - -/* - * Internal Memory. - */ -#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ - -#define AT91SAM9G10_SRAM_BASE AT91SAM9261_SRAM_BASE /* Internal SRAM base address */ -#define AT91SAM9G10_SRAM_SIZE 0x00004000 /* Internal SRAM size (16Kb) */ - -#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ -#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ - - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h deleted file mode 100644 index d201029..0000000 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9263.h - * - * (C) 2007 Atmel Corporation. - * - * Common definitions. - * Based on AT91SAM9263 datasheet revision B (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9263_H -#define AT91SAM9263_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ -#define AT91SAM9263_ID_US0 7 /* USART 0 */ -#define AT91SAM9263_ID_US1 8 /* USART 1 */ -#define AT91SAM9263_ID_US2 9 /* USART 2 */ -#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ -#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ -#define AT91SAM9263_ID_CAN 12 /* CAN */ -#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ -#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ -#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ -#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ -#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ -#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ -#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ -#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ -#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ -#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ -#define AT91SAM9263_ID_UHP 29 /* USB Host port */ -#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9263_BASE_UDP 0xfff78000 -#define AT91SAM9263_BASE_TCB0 0xfff7c000 -#define AT91SAM9263_BASE_TC0 0xfff7c000 -#define AT91SAM9263_BASE_TC1 0xfff7c040 -#define AT91SAM9263_BASE_TC2 0xfff7c080 -#define AT91SAM9263_BASE_MCI0 0xfff80000 -#define AT91SAM9263_BASE_MCI1 0xfff84000 -#define AT91SAM9263_BASE_TWI 0xfff88000 -#define AT91SAM9263_BASE_US0 0xfff8c000 -#define AT91SAM9263_BASE_US1 0xfff90000 -#define AT91SAM9263_BASE_US2 0xfff94000 -#define AT91SAM9263_BASE_SSC0 0xfff98000 -#define AT91SAM9263_BASE_SSC1 0xfff9c000 -#define AT91SAM9263_BASE_AC97C 0xfffa0000 -#define AT91SAM9263_BASE_SPI0 0xfffa4000 -#define AT91SAM9263_BASE_SPI1 0xfffa8000 -#define AT91SAM9263_BASE_CAN 0xfffac000 -#define AT91SAM9263_BASE_PWMC 0xfffb8000 -#define AT91SAM9263_BASE_EMAC 0xfffbc000 -#define AT91SAM9263_BASE_ISI 0xfffc4000 -#define AT91SAM9263_BASE_2DGE 0xfffc8000 - -/* - * System Peripherals - */ -#define AT91SAM9263_BASE_ECC0 0xffffe000 -#define AT91SAM9263_BASE_SDRAMC0 0xffffe200 -#define AT91SAM9263_BASE_SMC0 0xffffe400 -#define AT91SAM9263_BASE_ECC1 0xffffe600 -#define AT91SAM9263_BASE_SDRAMC1 0xffffe800 -#define AT91SAM9263_BASE_SMC1 0xffffea00 -#define AT91SAM9263_BASE_MATRIX 0xffffec00 -#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1 -#define AT91SAM9263_BASE_PIOA 0xfffff200 -#define AT91SAM9263_BASE_PIOB 0xfffff400 -#define AT91SAM9263_BASE_PIOC 0xfffff600 -#define AT91SAM9263_BASE_PIOD 0xfffff800 -#define AT91SAM9263_BASE_PIOE 0xfffffa00 -#define AT91SAM9263_BASE_RSTC 0xfffffd00 -#define AT91SAM9263_BASE_SHDWC 0xfffffd10 -#define AT91SAM9263_BASE_RTT0 0xfffffd20 -#define AT91SAM9263_BASE_PIT 0xfffffd30 -#define AT91SAM9263_BASE_WDT 0xfffffd40 -#define AT91SAM9263_BASE_RTT1 0xfffffd50 -#define AT91SAM9263_BASE_GPBR 0xfffffd60 - -#define AT91_SMC AT91_SMC0 - -/* - * Internal Memory. - */ -#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ -#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ - -#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ -#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ - -#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ -#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ -#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ - - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h index 175e1fd..ff54a0c 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h @@ -16,8 +16,6 @@ #ifndef AT91SAM9_SMC_H #define AT91SAM9_SMC_H -#include <mach/cpu.h> - #ifndef __ASSEMBLY__ struct sam9_smc_config { /* Setup register */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h deleted file mode 100644 index 8eba102..0000000 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Chip-specific header file for the AT91SAM9G45 family - * - * Copyright (C) 2008-2009 Atmel Corporation. - * - * Common definitions. - * Based on AT91SAM9G45 preliminary datasheet. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9G45_H -#define AT91SAM9G45_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ -#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ -#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ -#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ -#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ -#define AT91SAM9G45_ID_US0 7 /* USART 0 */ -#define AT91SAM9G45_ID_US1 8 /* USART 1 */ -#define AT91SAM9G45_ID_US2 9 /* USART 2 */ -#define AT91SAM9G45_ID_US3 10 /* USART 3 */ -#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ -#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ -#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ -#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ -#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ -#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ -#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ -#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ -#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ -#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ -#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ -#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ -#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ -#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ -#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ -#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9G45_BASE_UDPHS 0xfff78000 -#define AT91SAM9G45_BASE_TCB0 0xfff7c000 -#define AT91SAM9G45_BASE_TC0 0xfff7c000 -#define AT91SAM9G45_BASE_TC1 0xfff7c040 -#define AT91SAM9G45_BASE_TC2 0xfff7c080 -#define AT91SAM9G45_BASE_MCI0 0xfff80000 -#define AT91SAM9G45_BASE_TWI0 0xfff84000 -#define AT91SAM9G45_BASE_TWI1 0xfff88000 -#define AT91SAM9G45_BASE_US0 0xfff8c000 -#define AT91SAM9G45_BASE_US1 0xfff90000 -#define AT91SAM9G45_BASE_US2 0xfff94000 -#define AT91SAM9G45_BASE_US3 0xfff98000 -#define AT91SAM9G45_BASE_SSC0 0xfff9c000 -#define AT91SAM9G45_BASE_SSC1 0xfffa0000 -#define AT91SAM9G45_BASE_SPI0 0xfffa4000 -#define AT91SAM9G45_BASE_SPI1 0xfffa8000 -#define AT91SAM9G45_BASE_AC97C 0xfffac000 -#define AT91SAM9G45_BASE_TSC 0xfffb0000 -#define AT91SAM9G45_BASE_ISI 0xfffb4000 -#define AT91SAM9G45_BASE_PWMC 0xfffb8000 -#define AT91SAM9G45_BASE_EMAC 0xfffbc000 -#define AT91SAM9G45_BASE_AES 0xfffc0000 -#define AT91SAM9G45_BASE_TDES 0xfffc4000 -#define AT91SAM9G45_BASE_SHA 0xfffc8000 -#define AT91SAM9G45_BASE_TRNG 0xfffcc000 -#define AT91SAM9G45_BASE_MCI1 0xfffd0000 -#define AT91SAM9G45_BASE_TCB1 0xfffd4000 -#define AT91SAM9G45_BASE_TC3 0xfffd4000 -#define AT91SAM9G45_BASE_TC4 0xfffd4040 -#define AT91SAM9G45_BASE_TC5 0xfffd4080 - -/* - * System Peripherals - */ -#define AT91SAM9G45_BASE_ECC 0xffffe200 -#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400 -#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600 -#define AT91SAM9G45_BASE_DMA 0xffffec00 -#define AT91SAM9G45_BASE_SMC 0xffffe800 -#define AT91SAM9G45_BASE_MATRIX 0xffffea00 -#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1 -#define AT91SAM9G45_BASE_PIOA 0xfffff200 -#define AT91SAM9G45_BASE_PIOB 0xfffff400 -#define AT91SAM9G45_BASE_PIOC 0xfffff600 -#define AT91SAM9G45_BASE_PIOD 0xfffff800 -#define AT91SAM9G45_BASE_PIOE 0xfffffa00 -#define AT91SAM9G45_BASE_RSTC 0xfffffd00 -#define AT91SAM9G45_BASE_SHDWC 0xfffffd10 -#define AT91SAM9G45_BASE_RTT 0xfffffd20 -#define AT91SAM9G45_BASE_PIT 0xfffffd30 -#define AT91SAM9G45_BASE_WDT 0xfffffd40 -#define AT91SAM9G45_BASE_RTC 0xfffffdb0 -#define AT91SAM9G45_BASE_GPBR 0xfffffd60 - -/* - * Internal Memory. - */ -#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ - -#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ - -#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ -#define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */ -#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ -#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ - -/* - * DMA peripheral identifiers - * for hardware handshaking interface - */ -#define AT_DMA_ID_MCI0 0 -#define AT_DMA_ID_SPI0_TX 1 -#define AT_DMA_ID_SPI0_RX 2 -#define AT_DMA_ID_SPI1_TX 3 -#define AT_DMA_ID_SPI1_RX 4 -#define AT_DMA_ID_SSC0_TX 5 -#define AT_DMA_ID_SSC0_RX 6 -#define AT_DMA_ID_SSC1_TX 7 -#define AT_DMA_ID_SSC1_RX 8 -#define AT_DMA_ID_AC97_TX 9 -#define AT_DMA_ID_AC97_RX 10 -#define AT_DMA_ID_AES_TX 11 -#define AT_DMA_ID_AES_RX 12 -#define AT_DMA_ID_MCI1 13 - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h deleted file mode 100644 index 0151bcf..0000000 --- a/arch/arm/mach-at91/include/mach/at91sam9n12.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * SoC specific header file for the AT91SAM9N12 - * - * Copyright (C) 2012 Atmel Corporation - * - * Common definitions, based on AT91SAM9N12 SoC datasheet - * - * Licensed under GPLv2 or later - */ - -#ifndef _AT91SAM9N12_H_ -#define _AT91SAM9N12_H_ - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */ -#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */ -#define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */ -#define AT91SAM9N12_ID_USART0 5 /* USART 0 */ -#define AT91SAM9N12_ID_USART1 6 /* USART 1 */ -#define AT91SAM9N12_ID_USART2 7 /* USART 2 */ -#define AT91SAM9N12_ID_USART3 8 /* USART 3 */ -#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */ -#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */ -#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */ -#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */ -#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */ -#define AT91SAM9N12_ID_UART0 15 /* UART 0 */ -#define AT91SAM9N12_ID_UART1 16 /* UART 1 */ -#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */ -#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */ -#define AT91SAM9N12_ID_DMA 20 /* DMA Controller */ -#define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */ -#define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */ -#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */ -#define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */ -#define AT91SAM9N12_ID_TRNG 30 /* TRNG */ -#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9N12_BASE_USART0 0xf801c000 -#define AT91SAM9N12_BASE_USART1 0xf8020000 -#define AT91SAM9N12_BASE_USART2 0xf8024000 -#define AT91SAM9N12_BASE_USART3 0xf8028000 - -/* - * System Peripherals - */ -#define AT91SAM9N12_BASE_RTC 0xfffffeb0 - -/* - * Internal Memory. - */ -#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ - -#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h deleted file mode 100644 index a15db56..0000000 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9260.h - * - * Copyright (C) 2007 Atmel Corporation - * - * Common definitions. - * Based on AT91SAM9RL datasheet revision A. (Preliminary) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#ifndef AT91SAM9RL_H -#define AT91SAM9RL_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ -#define AT91SAM9RL_ID_US0 6 /* USART 0 */ -#define AT91SAM9RL_ID_US1 7 /* USART 1 */ -#define AT91SAM9RL_ID_US2 8 /* USART 2 */ -#define AT91SAM9RL_ID_US3 9 /* USART 3 */ -#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ -#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ -#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ -#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ -#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ -#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ -#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ -#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ -#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ -#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ -#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ -#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ -#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9RL_BASE_TCB0 0xfffa0000 -#define AT91SAM9RL_BASE_TC0 0xfffa0000 -#define AT91SAM9RL_BASE_TC1 0xfffa0040 -#define AT91SAM9RL_BASE_TC2 0xfffa0080 -#define AT91SAM9RL_BASE_MCI 0xfffa4000 -#define AT91SAM9RL_BASE_TWI0 0xfffa8000 -#define AT91SAM9RL_BASE_TWI1 0xfffac000 -#define AT91SAM9RL_BASE_US0 0xfffb0000 -#define AT91SAM9RL_BASE_US1 0xfffb4000 -#define AT91SAM9RL_BASE_US2 0xfffb8000 -#define AT91SAM9RL_BASE_US3 0xfffbc000 -#define AT91SAM9RL_BASE_SSC0 0xfffc0000 -#define AT91SAM9RL_BASE_SSC1 0xfffc4000 -#define AT91SAM9RL_BASE_PWMC 0xfffc8000 -#define AT91SAM9RL_BASE_SPI 0xfffcc000 -#define AT91SAM9RL_BASE_TSC 0xfffd0000 -#define AT91SAM9RL_BASE_UDPHS 0xfffd4000 -#define AT91SAM9RL_BASE_AC97C 0xfffd8000 - - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) - -#define AT91SAM9RL_BASE_DMA 0xffffe600 -#define AT91SAM9RL_BASE_ECC 0xffffe800 -#define AT91SAM9RL_BASE_SDRAMC 0xffffea00 -#define AT91SAM9RL_BASE_SMC 0xffffec00 -#define AT91SAM9RL_BASE_MATRIX 0xffffee00 -#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0 -#define AT91SAM9RL_BASE_PIOA 0xfffff400 -#define AT91SAM9RL_BASE_PIOB 0xfffff600 -#define AT91SAM9RL_BASE_PIOC 0xfffff800 -#define AT91SAM9RL_BASE_PIOD 0xfffffa00 -#define AT91SAM9RL_BASE_RSTC 0xfffffd00 -#define AT91SAM9RL_BASE_SHDWC 0xfffffd10 -#define AT91SAM9RL_BASE_RTT 0xfffffd20 -#define AT91SAM9RL_BASE_PIT 0xfffffd30 -#define AT91SAM9RL_BASE_WDT 0xfffffd40 -#define AT91SAM9RL_BASE_GPBR 0xfffffd60 -#define AT91SAM9RL_BASE_RTC 0xfffffe00 - - -/* - * Internal Memory. - */ -#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ - -#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ - -#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h deleted file mode 100644 index 2fc76c4..0000000 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Chip-specific header file for the AT91SAM9x5 family - * - * Copyright (C) 2009-2012 Atmel Corporation. - * - * Common definitions. - * Based on AT91SAM9x5 datasheet. - * - * Licensed under GPLv2 or later. - */ - -#ifndef AT91SAM9X5_H -#define AT91SAM9X5_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */ -#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */ -#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */ -#define AT91SAM9X5_ID_USART0 5 /* USART 0 */ -#define AT91SAM9X5_ID_USART1 6 /* USART 1 */ -#define AT91SAM9X5_ID_USART2 7 /* USART 2 */ -#define AT91SAM9X5_ID_USART3 8 /* USART 3 */ -#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */ -#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */ -#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */ -#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */ -#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */ -#define AT91SAM9X5_ID_UART0 15 /* UART 0 */ -#define AT91SAM9X5_ID_UART1 16 /* UART 1 */ -#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */ -#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */ -#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */ -#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */ -#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */ -#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */ -#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */ -#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */ -#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */ -#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */ -#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */ -#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */ -#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */ -#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9X5_BASE_USART0 0xf801c000 -#define AT91SAM9X5_BASE_USART1 0xf8020000 -#define AT91SAM9X5_BASE_USART2 0xf8024000 - -/* - * System Peripherals - */ -#define AT91SAM9X5_BASE_RTC 0xfffffeb0 - -/* - * Internal Memory. - */ -#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ - -#define AT91SAM9X5_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h deleted file mode 100644 index ce7c80a..0000000 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/cpu.h - * - * Copyright (C) 2006 SAN People - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __MACH_CPU_H__ -#define __MACH_CPU_H__ - -#define ARCH_ID_AT91RM9200 0x09290780 -#define ARCH_ID_AT91SAM9260 0x019803a0 -#define ARCH_ID_AT91SAM9261 0x019703a0 -#define ARCH_ID_AT91SAM9263 0x019607a0 -#define ARCH_ID_AT91SAM9G10 0x019903a0 -#define ARCH_ID_AT91SAM9G20 0x019905a0 -#define ARCH_ID_AT91SAM9RL64 0x019b03a0 -#define ARCH_ID_AT91SAM9G45 0x819b05a0 -#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ -#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ -#define ARCH_ID_AT91SAM9X5 0x819a05a0 -#define ARCH_ID_AT91SAM9N12 0x819a07a0 - -#define ARCH_ID_AT91SAM9XE128 0x329973a0 -#define ARCH_ID_AT91SAM9XE256 0x329a93a0 -#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 - -#define ARCH_ID_AT91M40800 0x14080044 -#define ARCH_ID_AT91R40807 0x44080746 -#define ARCH_ID_AT91M40807 0x14080745 -#define ARCH_ID_AT91R40008 0x44000840 - -#define ARCH_ID_SAMA5 0x8A5C07C0 - -#define ARCH_EXID_AT91SAM9M11 0x00000001 -#define ARCH_EXID_AT91SAM9M10 0x00000002 -#define ARCH_EXID_AT91SAM9G46 0x00000003 -#define ARCH_EXID_AT91SAM9G45 0x00000004 - -#define ARCH_EXID_AT91SAM9G15 0x00000000 -#define ARCH_EXID_AT91SAM9G35 0x00000001 -#define ARCH_EXID_AT91SAM9X35 0x00000002 -#define ARCH_EXID_AT91SAM9G25 0x00000003 -#define ARCH_EXID_AT91SAM9X25 0x00000004 - -#define ARCH_EXID_SAMA5D3 0x00004300 -#define ARCH_EXID_SAMA5D31 0x00444300 -#define ARCH_EXID_SAMA5D33 0x00414300 -#define ARCH_EXID_SAMA5D34 0x00414301 -#define ARCH_EXID_SAMA5D35 0x00584300 -#define ARCH_EXID_SAMA5D36 0x00004301 - -#define ARCH_EXID_SAMA5D4 0x00000007 -#define ARCH_EXID_SAMA5D41 0x00000001 -#define ARCH_EXID_SAMA5D42 0x00000002 -#define ARCH_EXID_SAMA5D43 0x00000003 -#define ARCH_EXID_SAMA5D44 0x00000004 - -#define ARCH_FAMILY_AT91SAM9 0x01900000 -#define ARCH_FAMILY_AT91SAM9XE 0x02900000 - -/* RM9200 type */ -#define ARCH_REVISON_9200_BGA (0 << 0) -#define ARCH_REVISON_9200_PQFP (1 << 0) - -#ifndef __ASSEMBLY__ -enum at91_soc_type { - /* 920T */ - AT91_SOC_RM9200, - - /* SAM92xx */ - AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263, - - /* SAM9Gxx */ - AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45, - - /* SAM9RL */ - AT91_SOC_SAM9RL, - - /* SAM9X5 */ - AT91_SOC_SAM9X5, - - /* SAM9N12 */ - AT91_SOC_SAM9N12, - - /* SAMA5D3 */ - AT91_SOC_SAMA5D3, - - /* SAMA5D4 */ - AT91_SOC_SAMA5D4, - - /* Unknown type */ - AT91_SOC_UNKNOWN, -}; - -enum at91_soc_subtype { - /* RM9200 */ - AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP, - - /* SAM9260 */ - AT91_SOC_SAM9XE, - - /* SAM9G45 */ - AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11, - - /* SAM9X5 */ - AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, - AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, - - /* SAMA5D3 */ - AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, - AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36, - - /* SAMA5D4 */ - AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43, - AT91_SOC_SAMA5D44, - - /* No subtype for this SoC */ - AT91_SOC_SUBTYPE_NONE, - - /* Unknown subtype */ - AT91_SOC_SUBTYPE_UNKNOWN, -}; - -struct at91_socinfo { - unsigned int type, subtype; - unsigned int cidr, exid; -}; - -extern struct at91_socinfo at91_soc_initdata; -const char *at91_get_soc_type(struct at91_socinfo *c); -const char *at91_get_soc_subtype(struct at91_socinfo *c); - -static inline int at91_soc_is_detected(void) -{ - return at91_soc_initdata.type != AT91_SOC_UNKNOWN; -} - -#ifdef CONFIG_SOC_AT91RM9200 -#define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200) -#define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA) -#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP) -#else -#define cpu_is_at91rm9200() (0) -#define cpu_is_at91rm9200_bga() (0) -#define cpu_is_at91rm9200_pqfp() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9 -#define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE) -#define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260) -#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20) -#define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261) -#define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10) -#define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263) -#define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL) -#define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45) -#define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES) -#define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10) -#define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46) -#define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11) -#define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5) -#define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15) -#define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35) -#define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35) -#define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25) -#define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25) -#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12) -#else -#define cpu_is_at91sam9xe() (0) -#define cpu_is_at91sam9260() (0) -#define cpu_is_at91sam9g20() (0) -#define cpu_is_at91sam9261() (0) -#define cpu_is_at91sam9g10() (0) -#define cpu_is_at91sam9263() (0) -#define cpu_is_at91sam9rl() (0) -#define cpu_is_at91sam9g45() (0) -#define cpu_is_at91sam9g45es() (0) -#define cpu_is_at91sam9m10() (0) -#define cpu_is_at91sam9g46() (0) -#define cpu_is_at91sam9m11() (0) -#define cpu_is_at91sam9x5() (0) -#define cpu_is_at91sam9g15() (0) -#define cpu_is_at91sam9g35() (0) -#define cpu_is_at91sam9x35() (0) -#define cpu_is_at91sam9g25() (0) -#define cpu_is_at91sam9x25() (0) -#define cpu_is_at91sam9n12() (0) -#endif - -#ifdef CONFIG_SOC_SAMA5D3 -#define cpu_is_sama5d3() (at91_soc_initdata.type == AT91_SOC_SAMA5D3) -#else -#define cpu_is_sama5d3() (0) -#endif - -#ifdef CONFIG_SOC_SAMA5D4 -#define cpu_is_sama5d4() (at91_soc_initdata.type == AT91_SOC_SAMA5D4) -#else -#define cpu_is_sama5d4() (0) -#endif - -/* - * Since this is ARM, we will never run on any AVR32 CPU. But these - * definitions may reduce clutter in common drivers. - */ -#define cpu_is_at32ap7000() (0) -#endif /* __ASSEMBLY__ */ - -#endif /* __MACH_CPU_H__ */ diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h deleted file mode 100644 index cacbaa5..0000000 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/hardware.h - * - * Copyright (C) 2003 SAN People - * Copyright (C) 2003 ATMEL - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/sizes.h> - -/* DBGU base */ -/* rm9200, 9260/9g20, 9261/9g10, 9rl */ -#define AT91_BASE_DBGU0 0xfffff200 -/* 9263, 9g45, sama5d3 */ -#define AT91_BASE_DBGU1 0xffffee00 -/* sama5d4 */ -#define AT91_BASE_DBGU2 0xfc069000 - -#include <mach/at91rm9200.h> -#include <mach/at91sam9260.h> -#include <mach/at91sam9261.h> -#include <mach/at91sam9263.h> -#include <mach/at91sam9rl.h> -#include <mach/at91sam9g45.h> -#include <mach/at91sam9x5.h> -#include <mach/at91sam9n12.h> -#include <mach/sama5d3.h> -#include <mach/sama5d4.h> - -/* - * On all at91 except rm9200 and x40 have the System Controller starts - * at address 0xffffc000 and has a size of 16KiB. - * - * On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting - * at 0xfffff000 - * - * Removes the individual definitions of AT91_BASE_SYS and - * replaces them with a common version at base 0xfffffc000 and size 16KiB - * and map the same memory space - */ -#define AT91_BASE_SYS 0xffffc000 - -/* - * On sama5d4 there is no system controller, we map some needed peripherals - */ -#define AT91_ALT_BASE_SYS 0xfc069000 - -/* - * On all at91 have the Advanced Interrupt Controller starts at address - * 0xfffff000 and the Power Management Controller starts at 0xfffffc00 - */ -#define AT91_AIC 0xfffff000 -#define AT91_PMC 0xfffffc00 - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ - -#ifdef CONFIG_MMU -/* - * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF - * to 0xFEF78000 .. 0xFF000000. (544Kb) - */ -#define AT91_IO_PHYS_BASE 0xFFF78000 -#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE) - -/* - * On sama5d4, remap the peripherals from address 0xFC069000 .. 0xFC06F000 - * to 0xFB069000 .. 0xFB06F000. (24Kb) - */ -#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS -#define AT91_ALT_IO_VIRT_BASE IOMEM(0xFB069000) -#else -/* - * Identity mapping for the non MMU case. - */ -#define AT91_IO_PHYS_BASE AT91_BASE_SYS -#define AT91_IO_VIRT_BASE IOMEM(AT91_IO_PHYS_BASE) - -#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS -#define AT91_ALT_IO_VIRT_BASE IOMEM(AT91_ALT_BASE_SYS) -#endif - -#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) - - /* Convert a physical IO address to virtual IO address */ -#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) -#define AT91_ALT_IO_P2V(x) ((x) - AT91_ALT_IO_PHYS_BASE + AT91_ALT_IO_VIRT_BASE) - -/* - * Virtual to Physical Address mapping for IO devices. - */ -#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) -#define AT91_ALT_VA_BASE_SYS AT91_ALT_IO_P2V(AT91_ALT_BASE_SYS) - - /* Internal SRAM is mapped below the IO devices */ -#define AT91_SRAM_MAX SZ_1M -#define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX) - -/* External Memory Map */ -#define AT91_CHIPSELECT_0 0x10000000 -#define AT91_CHIPSELECT_1 0x20000000 -#define AT91_CHIPSELECT_2 0x30000000 -#define AT91_CHIPSELECT_3 0x40000000 -#define AT91_CHIPSELECT_4 0x50000000 -#define AT91_CHIPSELECT_5 0x60000000 -#define AT91_CHIPSELECT_6 0x70000000 -#define AT91_CHIPSELECT_7 0x80000000 - -/* Clocks */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -/* - * FIXME: this is needed to communicate between the pinctrl driver and - * the PM implementation in the machine. Possibly part of the PM - * implementation should be moved down into the pinctrl driver and get - * called as part of the generic suspend/resume path. - */ -#ifndef __ASSEMBLY__ -extern void at91_pinctrl_gpio_suspend(void); -extern void at91_pinctrl_gpio_resume(void); -#endif - -#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h deleted file mode 100644 index 25613d8..0000000 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Chip-specific header file for the SAMA5D3 family - * - * Copyright (C) 2013 Atmel, - * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> - * - * Common definitions. - * Based on SAMA5D3 datasheet. - * - * Licensed under GPLv2 or later. - */ - -#ifndef SAMA5D3_H -#define SAMA5D3_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */ -#define AT91_ID_PIT 3 /* PIT */ -#define SAMA5D3_ID_WDT 4 /* Watchdog Timer Interrupt */ -#define SAMA5D3_ID_HSMC 5 /* Static Memory Controller */ -#define SAMA5D3_ID_PIOA 6 /* PIOA */ -#define SAMA5D3_ID_PIOB 7 /* PIOB */ -#define SAMA5D3_ID_PIOC 8 /* PIOC */ -#define SAMA5D3_ID_PIOD 9 /* PIOD */ -#define SAMA5D3_ID_PIOE 10 /* PIOE */ -#define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */ -#define SAMA5D3_ID_USART0 12 /* USART0 */ -#define SAMA5D3_ID_USART1 13 /* USART1 */ -#define SAMA5D3_ID_USART2 14 /* USART2 */ -#define SAMA5D3_ID_USART3 15 /* USART3 */ -#define SAMA5D3_ID_UART0 16 /* UART 0 */ -#define SAMA5D3_ID_UART1 17 /* UART 1 */ -#define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */ -#define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */ -#define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */ -#define SAMA5D3_ID_HSMCI0 21 /* MCI */ -#define SAMA5D3_ID_HSMCI1 22 /* MCI */ -#define SAMA5D3_ID_HSMCI2 23 /* MCI */ -#define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */ -#define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */ -#define SAMA5D3_ID_TC0 26 /* Timer Counter 0 */ -#define SAMA5D3_ID_TC1 27 /* Timer Counter 2 */ -#define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */ -#define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */ -#define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */ -#define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */ -#define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */ -#define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */ -#define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */ -#define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */ -#define SAMA5D3_ID_LCDC 36 /* LCD Controller */ -#define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */ -#define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */ -#define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */ -#define SAMA5D3_ID_CAN0 40 /* CAN Controller 0 */ -#define SAMA5D3_ID_CAN1 41 /* CAN Controller 1 */ -#define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */ -#define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */ -#define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */ -#define SAMA5D3_ID_TRNG 45 /* True Random Generator Number */ -#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */ - -/* - * User Peripheral physical base addresses. - */ -#define SAMA5D3_BASE_USART0 0xf001c000 -#define SAMA5D3_BASE_USART1 0xf0020000 -#define SAMA5D3_BASE_USART2 0xf8020000 -#define SAMA5D3_BASE_USART3 0xf8024000 - -/* - * System Peripherals - */ -#define SAMA5D3_BASE_RTC 0xfffffeb0 - -/* - * Internal Memory - */ -#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h deleted file mode 100644 index f256a45..0000000 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Chip-specific header file for the SAMA5D4 family - * - * Copyright (C) 2013 Atmel Corporation, - * Nicolas Ferre <nicolas.ferre@atmel.com> - * - * Common definitions. - * Based on SAMA5D4 datasheet. - * - * Licensed under GPLv2 or later. - */ - -#ifndef SAMA5D4_H -#define SAMA5D4_H - -/* - * User Peripheral physical base addresses. - */ -#define SAMA5D4_BASE_USART3 0xfc00c000 /* (USART3 non-secure) Base Address */ -#define SAMA5D4_BASE_PMC 0xf0018000 /* (PMC) Base Address */ -#define SAMA5D4_BASE_MPDDRC 0xf0010000 /* (MPDDRC) Base Address */ -#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */ - -/* Some other peripherals */ -#define SAMA5D4_BASE_SYS2 SAMA5D4_BASE_PIOD - -/* - * Internal Memory. - */ -#define SAMA5D4_NS_SRAM_BASE 0x00210000 /* Internal SRAM base address Non-Secure */ -#define SAMA5D4_NS_SRAM_SIZE (64 * SZ_1K) /* Internal SRAM size Non-Secure part (64Kb) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h deleted file mode 100644 index 4ebb609..0000000 --- a/arch/arm/mach-at91/include/mach/uncompress.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/uncompress.h - * - * Copyright (C) 2003 SAN People - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <linux/io.h> -#include <linux/atmel_serial.h> -#include <mach/hardware.h> - -#include <mach/at91_dbgu.h> -#include <mach/cpu.h> - -void __iomem *at91_uart; - -static const u32 uarts_rm9200[] = { - AT91_BASE_DBGU0, - AT91RM9200_BASE_US0, - AT91RM9200_BASE_US1, - AT91RM9200_BASE_US2, - AT91RM9200_BASE_US3, - 0, -}; - -static const u32 uarts_sam9260[] = { - AT91_BASE_DBGU0, - AT91SAM9260_BASE_US0, - AT91SAM9260_BASE_US1, - AT91SAM9260_BASE_US2, - AT91SAM9260_BASE_US3, - AT91SAM9260_BASE_US4, - AT91SAM9260_BASE_US5, - 0, -}; - -static const u32 uarts_sam9261[] = { - AT91_BASE_DBGU0, - AT91SAM9261_BASE_US0, - AT91SAM9261_BASE_US1, - AT91SAM9261_BASE_US2, - 0, -}; - -static const u32 uarts_sam9263[] = { - AT91_BASE_DBGU1, - AT91SAM9263_BASE_US0, - AT91SAM9263_BASE_US1, - AT91SAM9263_BASE_US2, - 0, -}; - -static const u32 uarts_sam9g45[] = { - AT91_BASE_DBGU1, - AT91SAM9G45_BASE_US0, - AT91SAM9G45_BASE_US1, - AT91SAM9G45_BASE_US2, - AT91SAM9G45_BASE_US3, - 0, -}; - -static const u32 uarts_sam9rl[] = { - AT91_BASE_DBGU0, - AT91SAM9RL_BASE_US0, - AT91SAM9RL_BASE_US1, - AT91SAM9RL_BASE_US2, - AT91SAM9RL_BASE_US3, - 0, -}; - -static const u32 uarts_sam9x5[] = { - AT91_BASE_DBGU0, - AT91SAM9X5_BASE_USART0, - AT91SAM9X5_BASE_USART1, - AT91SAM9X5_BASE_USART2, - 0, -}; - -static const u32 uarts_sama5d3[] = { - AT91_BASE_DBGU1, - SAMA5D3_BASE_USART0, - SAMA5D3_BASE_USART1, - SAMA5D3_BASE_USART2, - SAMA5D3_BASE_USART3, - 0, -}; - -static const u32 uarts_sama5d4[] = { - AT91_BASE_DBGU2, - SAMA5D4_BASE_USART3, - 0, -}; - -static inline const u32* decomp_soc_detect(void __iomem *dbgu_base) -{ - u32 cidr, socid; - - cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR); - socid = cidr & ~AT91_CIDR_VERSION; - - switch (socid) { - case ARCH_ID_AT91RM9200: - return uarts_rm9200; - - case ARCH_ID_AT91SAM9G20: - case ARCH_ID_AT91SAM9260: - return uarts_sam9260; - - case ARCH_ID_AT91SAM9261: - return uarts_sam9261; - - case ARCH_ID_AT91SAM9263: - return uarts_sam9263; - - case ARCH_ID_AT91SAM9G45: - return uarts_sam9g45; - - case ARCH_ID_AT91SAM9RL64: - return uarts_sam9rl; - - case ARCH_ID_AT91SAM9N12: - case ARCH_ID_AT91SAM9X5: - return uarts_sam9x5; - - case ARCH_ID_SAMA5: - cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID); - if (cidr & ARCH_EXID_SAMA5D3) - return uarts_sama5d3; - else if (cidr & ARCH_EXID_SAMA5D4) - return uarts_sama5d4; - - break; - } - - /* at91sam9g10 */ - if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { - return uarts_sam9261; - } - /* at91sam9xe */ - else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) { - return uarts_sam9260; - } - - return NULL; -} - -static inline void arch_decomp_setup(void) -{ - int i = 0; - const u32* usarts; - - usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0); - if (!usarts) - usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1); - if (!usarts) - usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2); - if (!usarts) { - at91_uart = NULL; - return; - } - - do { - /* physical address */ - at91_uart = (void __iomem *)usarts[i]; - - if (__raw_readl(at91_uart + ATMEL_US_BRGR)) - return; - i++; - } while (usarts[i]); - - at91_uart = NULL; -} - -/* - * The following code assumes the serial port has already been - * initialized by the bootloader. If you didn't setup a port in - * your bootloader then nothing will appear (which might be desired). - * - * This does not append a newline - */ -static void putc(int c) -{ - if (!at91_uart) - return; - - while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY)) - barrier(); - __raw_writel(c, at91_uart + ATMEL_US_THR); -} - -static inline void flush(void) -{ - if (!at91_uart) - return; - - /* wait for transmission to complete */ - while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) - barrier(); -} - -#endif diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index ac947cd..5062699 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -32,12 +32,18 @@ #include <asm/fncpy.h> #include <asm/cacheflush.h> -#include <mach/cpu.h> -#include <mach/hardware.h> - #include "generic.h" #include "pm.h" +/* + * FIXME: this is needed to communicate between the pinctrl driver and + * the PM implementation in the machine. Possibly part of the PM + * implementation should be moved down into the pinctrl driver and get + * called as part of the generic suspend/resume path. + */ +extern void at91_pinctrl_gpio_suspend(void); +extern void at91_pinctrl_gpio_resume(void); + static struct { unsigned long uhp_udp_mask; int memctrl; @@ -216,6 +222,95 @@ static void at91_pm_set_standby(void (*at91_standby)(void)) at91_cpuidle_device.dev.platform_data = at91_standby; } +/* + * The AT91RM9200 goes into self-refresh mode with this command, and will + * terminate self-refresh automatically on the next SDRAM access. + * + * Self-refresh mode is exited as soon as a memory access is made, but we don't + * know for sure when that happens. However, we need to restore the low-power + * mode if it was enabled before going idle. Restoring low-power mode while + * still in self-refresh is "not recommended", but seems to work. + */ +static void at91rm9200_standby(void) +{ + u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR); + + asm volatile( + "b 1f\n\t" + ".align 5\n\t" + "1: mcr p15, 0, %0, c7, c10, 4\n\t" + " str %0, [%1, %2]\n\t" + " str %3, [%1, %4]\n\t" + " mcr p15, 0, %0, c7, c0, 4\n\t" + " str %5, [%1, %2]" + : + : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR), + "r" (1), "r" (AT91RM9200_SDRAMC_SRR), + "r" (lpr)); +} + +/* We manage both DDRAM/SDRAM controllers, we need more than one value to + * remember. + */ +static void at91_ddr_standby(void) +{ + /* Those two values allow us to delay self-refresh activation + * to the maximum. */ + u32 lpr0, lpr1 = 0; + u32 saved_lpr0, saved_lpr1 = 0; + + if (at91_ramc_base[1]) { + saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); + lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; + lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; + } + + saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); + lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; + lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; + + /* self-refresh mode now */ + at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); + if (at91_ramc_base[1]) + at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); + + cpu_do_idle(); + + at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); + if (at91_ramc_base[1]) + at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); +} + +/* We manage both DDRAM/SDRAM controllers, we need more than one value to + * remember. + */ +static void at91sam9_sdram_standby(void) +{ + u32 lpr0, lpr1 = 0; + u32 saved_lpr0, saved_lpr1 = 0; + + if (at91_ramc_base[1]) { + saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); + lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; + lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; + } + + saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); + lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; + lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; + + /* self-refresh mode now */ + at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); + if (at91_ramc_base[1]) + at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); + + cpu_do_idle(); + + at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); + if (at91_ramc_base[1]) + at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); +} + static const struct of_device_id ramc_ids[] __initconst = { { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby }, { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index dcacfa1..ecd875a 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -15,6 +15,10 @@ #include <mach/at91_ramc.h> +#define AT91_MEMCTRL_MC 0 +#define AT91_MEMCTRL_SDRAMC 1 +#define AT91_MEMCTRL_DDRSDR 2 + #define AT91_PM_MEMTYPE_MASK 0x0f #define AT91_PM_MODE_OFFSET 4 @@ -23,96 +27,4 @@ #define AT91_PM_SLOW_CLOCK 0x01 -/* - * The AT91RM9200 goes into self-refresh mode with this command, and will - * terminate self-refresh automatically on the next SDRAM access. - * - * Self-refresh mode is exited as soon as a memory access is made, but we don't - * know for sure when that happens. However, we need to restore the low-power - * mode if it was enabled before going idle. Restoring low-power mode while - * still in self-refresh is "not recommended", but seems to work. - */ - -#ifndef __ASSEMBLY__ -static inline void at91rm9200_standby(void) -{ - u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR); - - asm volatile( - "b 1f\n\t" - ".align 5\n\t" - "1: mcr p15, 0, %0, c7, c10, 4\n\t" - " str %0, [%1, %2]\n\t" - " str %3, [%1, %4]\n\t" - " mcr p15, 0, %0, c7, c0, 4\n\t" - " str %5, [%1, %2]" - : - : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR), - "r" (1), "r" (AT91RM9200_SDRAMC_SRR), - "r" (lpr)); -} - -/* We manage both DDRAM/SDRAM controllers, we need more than one value to - * remember. - */ -static inline void at91_ddr_standby(void) -{ - /* Those two values allow us to delay self-refresh activation - * to the maximum. */ - u32 lpr0, lpr1 = 0; - u32 saved_lpr0, saved_lpr1 = 0; - - if (at91_ramc_base[1]) { - saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); - lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; - lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; - } - - saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); - lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; - lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; - - /* self-refresh mode now */ - at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); - - cpu_do_idle(); - - at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); -} - -/* We manage both DDRAM/SDRAM controllers, we need more than one value to - * remember. - */ -static inline void at91sam9_sdram_standby(void) -{ - u32 lpr0, lpr1 = 0; - u32 saved_lpr0, saved_lpr1 = 0; - - if (at91_ramc_base[1]) { - saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); - lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; - lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; - } - - saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); - lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; - lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; - - /* self-refresh mode now */ - at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); - - cpu_do_idle(); - - at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); - if (at91_ramc_base[1]) - at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); -} - -#endif #endif diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index 7c444c2..bd22b2c 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -13,7 +13,6 @@ */ #include <linux/linkage.h> #include <linux/clk/at91_pmc.h> -#include <mach/hardware.h> #include <mach/at91_ramc.h> #include "pm.h" diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c index ef5d207..41d829d 100644 --- a/arch/arm/mach-at91/sama5.c +++ b/arch/arm/mach-at91/sama5.c @@ -14,8 +14,6 @@ #include <asm/mach/map.h> #include <asm/system_misc.h> -#include <mach/hardware.h> - #include "generic.h" #include "soc.h" diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 347b6a5..0fb4842 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -62,6 +62,10 @@ config ARCH_R8A7740 select ARCH_RMOBILE select RENESAS_INTC_IRQPIN +config ARCH_R8A7778 + bool "R-Car M1A (R8A77781)" + select ARCH_RCAR_GEN1 + config ARCH_R8A7779 bool "R-Car H1 (R8A77790)" select ARCH_RCAR_GEN1 @@ -80,6 +84,11 @@ config ARCH_R8A7794 bool "R-Car E2 (R8A77940)" select ARCH_RCAR_GEN2 +config ARCH_SH73A0 + bool "SH-Mobile AG5 (R8A73A00)" + select ARCH_RMOBILE + select RENESAS_INTC_IRQPIN + comment "Renesas ARM SoCs Board Type" config MACH_MARZEN @@ -94,13 +103,6 @@ if ARCH_SHMOBILE_LEGACY comment "Renesas ARM SoCs System Type" -config ARCH_SH7372 - bool "SH-Mobile AP4 (SH7372)" - select ARCH_RMOBILE - select ARCH_WANT_OPTIONAL_GPIOLIB - select ARM_CPU_SUSPEND if PM || CPU_IDLE - select SH_INTC - config ARCH_SH73A0 bool "SH-Mobile AG5 (R8A73A00)" select ARCH_RMOBILE @@ -110,13 +112,6 @@ config ARCH_SH73A0 select SH_INTC select RENESAS_INTC_IRQPIN -config ARCH_R8A73A4 - bool "R-Mobile APE6 (R8A73A40)" - select ARCH_RMOBILE - select ARCH_WANT_OPTIONAL_GPIOLIB - select ARM_GIC - select RENESAS_IRQC - config ARCH_R8A7740 bool "R-Mobile A1 (R8A77400)" select ARCH_RMOBILE @@ -138,33 +133,6 @@ config ARCH_R8A7779 comment "Renesas ARM SoCs Board Type" -config MACH_APE6EVM - bool "APE6EVM board" - depends on ARCH_R8A73A4 - select SMSC_PHY if SMSC911X - select USE_OF - -config MACH_APE6EVM_REFERENCE - bool "APE6EVM board - Reference Device Tree Implementation" - depends on ARCH_R8A73A4 - select SMSC_PHY if SMSC911X - select USE_OF - ---help--- - Use reference implementation of APE6EVM board support - which makes a greater use of device tree at the expense - of not supporting a number of devices. - - This is intended to aid developers - -config MACH_MACKEREL - bool "mackerel board" - depends on ARCH_SH7372 - select ARCH_REQUIRE_GPIOLIB - select REGULATOR_FIXED_VOLTAGE if REGULATOR - select SMSC_PHY if SMSC911X - select SND_SOC_AK4642 if SND_SIMPLE_CARD - select USE_OF - config MACH_ARMADILLO800EVA bool "Armadillo-800 EVA board" depends on ARCH_R8A7740 @@ -211,20 +179,6 @@ config MACH_KZM9G select SND_SOC_AK4642 if SND_SIMPLE_CARD select USE_OF -config MACH_KZM9G_REFERENCE - bool "KZM-A9-GT board - Reference Device Tree Implementation" - depends on ARCH_SH73A0 - select ARCH_REQUIRE_GPIOLIB - select REGULATOR_FIXED_VOLTAGE if REGULATOR - select SND_SOC_AK4642 if SND_SIMPLE_CARD - select USE_OF - ---help--- - Use reference implementation of KZM-A9-GT board support - which makes as greater use of device tree at the expense - of not supporting a number of devices. - - This is intended to aid developers - comment "Renesas ARM SoCs System Configuration" config CPU_HAS_INTEVT diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 3631d8b..89e463d 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -6,8 +6,7 @@ obj-y := timer.o console.o # CPU objects -obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o intc-sh7372.o pm-sh7372.o -obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o pm-sh73a0.o +obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o pm-sh73a0.o obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o @@ -21,9 +20,7 @@ obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o # Clock objects ifndef CONFIG_COMMON_CLK obj-y += clock.o -obj-$(CONFIG_ARCH_SH7372) += clock-sh7372.o obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o -obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o @@ -53,22 +50,15 @@ obj-$(CONFIG_PM_RCAR) += pm-rcar.o obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o obj-$(CONFIG_ARCH_RCAR_GEN2) += pm-rcar-gen2.o -# special sh7372 handling for IRQ objects and low level sleep code -obj-$(CONFIG_ARCH_SH7372) += entry-intc.o sleep-sh7372.o - # Board objects ifdef CONFIG_ARCH_SHMOBILE_MULTI obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o else -obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o -obj-$(CONFIG_MACH_APE6EVM_REFERENCE) += board-ape6evm-reference.o -obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o obj-$(CONFIG_MACH_BOCKW) += board-bockw.o obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o obj-$(CONFIG_MACH_MARZEN) += board-marzen.o obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o -obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o -obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o +obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o intc-sh73a0.o endif # Framework support diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot index 02532be..e1ef19c 100644 --- a/arch/arm/mach-shmobile/Makefile.boot +++ b/arch/arm/mach-shmobile/Makefile.boot @@ -1,13 +1,9 @@ # per-board load address for uImage loadaddr-y := -loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000 -loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000 loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 -loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 -loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000 loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 __ZRELADDR := $(sort $(loadaddr-y)) diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c deleted file mode 100644 index 3b68370..0000000 --- a/arch/arm/mach-shmobile/board-ape6evm-reference.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * APE6EVM board support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/of_platform.h> -#include <linux/pinctrl/machine.h> -#include <linux/platform_device.h> -#include <linux/sh_clk.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include "common.h" -#include "r8a73a4.h" - -static void __init ape6evm_add_standard_devices(void) -{ - - struct clk *parent; - struct clk *mp; - - r8a73a4_clock_init(); - - /* MP clock parent = extal2 */ - parent = clk_get(NULL, "extal2"); - mp = clk_get(NULL, "mp"); - BUG_ON(IS_ERR(parent) || IS_ERR(mp)); - - clk_set_parent(mp, parent); - clk_put(parent); - clk_put(mp); - - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - -static const char *ape6evm_boards_compat_dt[] __initdata = { - "renesas,ape6evm-reference", - NULL, -}; - -DT_MACHINE_START(APE6EVM_DT, "ape6evm") - .init_early = shmobile_init_delay, - .init_machine = ape6evm_add_standard_devices, - .init_late = shmobile_init_late, - .dt_compat = ape6evm_boards_compat_dt, -MACHINE_END diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c deleted file mode 100644 index 444f22d..0000000 --- a/arch/arm/mach-shmobile/board-ape6evm.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * APE6EVM board support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/gpio.h> -#include <linux/gpio_keys.h> -#include <linux/input.h> -#include <linux/interrupt.h> -#include <linux/irqchip.h> -#include <linux/irqchip/arm-gic.h> -#include <linux/kernel.h> -#include <linux/mfd/tmio.h> -#include <linux/mmc/host.h> -#include <linux/mmc/sh_mmcif.h> -#include <linux/mmc/sh_mobile_sdhi.h> -#include <linux/pinctrl/machine.h> -#include <linux/platform_device.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/machine.h> -#include <linux/sh_clk.h> -#include <linux/smsc911x.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include "common.h" -#include "irqs.h" -#include "r8a73a4.h" - -/* LEDS */ -static struct gpio_led ape6evm_leds[] = { - { - .name = "gnss-en", - .gpio = 28, - .default_state = LEDS_GPIO_DEFSTATE_OFF, - }, { - .name = "nfc-nrst", - .gpio = 126, - .default_state = LEDS_GPIO_DEFSTATE_OFF, - }, { - .name = "gnss-nrst", - .gpio = 132, - .default_state = LEDS_GPIO_DEFSTATE_OFF, - }, { - .name = "bt-wakeup", - .gpio = 232, - .default_state = LEDS_GPIO_DEFSTATE_OFF, - }, { - .name = "strobe", - .gpio = 250, - .default_state = LEDS_GPIO_DEFSTATE_OFF, - }, { - .name = "bbresetout", - .gpio = 288, - .default_state = LEDS_GPIO_DEFSTATE_OFF, - }, -}; - -static __initdata struct gpio_led_platform_data ape6evm_leds_pdata = { - .leds = ape6evm_leds, - .num_leds = ARRAY_SIZE(ape6evm_leds), -}; - -/* GPIO KEY */ -#define GPIO_KEY(c, g, d, ...) \ - { .code = c, .gpio = g, .desc = d, .active_low = 1 } - -static struct gpio_keys_button gpio_buttons[] = { - GPIO_KEY(KEY_0, 324, "S16"), - GPIO_KEY(KEY_MENU, 325, "S17"), - GPIO_KEY(KEY_HOME, 326, "S18"), - GPIO_KEY(KEY_BACK, 327, "S19"), - GPIO_KEY(KEY_VOLUMEUP, 328, "S20"), - GPIO_KEY(KEY_VOLUMEDOWN, 329, "S21"), -}; - -static struct gpio_keys_platform_data ape6evm_keys_pdata __initdata = { - .buttons = gpio_buttons, - .nbuttons = ARRAY_SIZE(gpio_buttons), -}; - -/* Dummy supplies, where voltage doesn't matter */ -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vddvario", "smsc911x"), - REGULATOR_SUPPLY("vdd33a", "smsc911x"), -}; - -/* SMSC LAN9220 */ -static const struct resource lan9220_res[] __initconst = { - DEFINE_RES_MEM(0x08000000, 0x1000), - { - .start = irq_pin(40), /* IRQ40 */ - .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, - }, -}; - -static const struct smsc911x_platform_config lan9220_data __initconst = { - .flags = SMSC911X_USE_32BIT, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, -}; - -/* - * MMC0 power supplies: - * Both Vcc and VccQ to eMMC on APE6EVM are supplied by a tps80032 voltage - * regulator. Until support for it is added to this file we simulate the - * Vcc supply by a fixed always-on regulator - */ -static struct regulator_consumer_supply vcc_mmc0_consumers[] = -{ - REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), -}; - -/* - * SDHI0 power supplies: - * Vcc to SDHI0 on APE6EVM is supplied by a GPIO-switchable regulator. VccQ is - * provided by the same tps80032 regulator as both MMC0 voltages - see comment - * above - */ -static struct regulator_consumer_supply vcc_sdhi0_consumers[] = -{ - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), -}; - -static struct regulator_init_data vcc_sdhi0_init_data = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers), - .consumer_supplies = vcc_sdhi0_consumers, -}; - -static const struct fixed_voltage_config vcc_sdhi0_info __initconst = { - .supply_name = "SDHI0 Vcc", - .microvolts = 3300000, - .gpio = 76, - .enable_high = 1, - .init_data = &vcc_sdhi0_init_data, -}; - -/* - * SDHI1 power supplies: - * Vcc and VccQ to SDHI1 on APE6EVM are both fixed at 3.3V - */ -static struct regulator_consumer_supply vcc_sdhi1_consumers[] = -{ - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), -}; - -/* MMCIF */ -static const struct sh_mmcif_plat_data mmcif0_pdata __initconst = { - .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, - .slave_id_tx = SHDMA_SLAVE_MMCIF0_TX, - .slave_id_rx = SHDMA_SLAVE_MMCIF0_RX, - .ccs_unsupported = true, -}; - -static const struct resource mmcif0_resources[] __initconst = { - DEFINE_RES_MEM(0xee200000, 0x100), - DEFINE_RES_IRQ(gic_spi(169)), -}; - -/* SDHI0 */ -static const struct sh_mobile_sdhi_info sdhi0_pdata __initconst = { - .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE, - .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, -}; - -static const struct resource sdhi0_resources[] __initconst = { - DEFINE_RES_MEM(0xee100000, 0x100), - DEFINE_RES_IRQ(gic_spi(165)), -}; - -/* SDHI1 */ -static const struct sh_mobile_sdhi_info sdhi1_pdata __initconst = { - .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE, - .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | - MMC_CAP_NEEDS_POLL, -}; - -static const struct resource sdhi1_resources[] __initconst = { - DEFINE_RES_MEM(0xee120000, 0x100), - DEFINE_RES_IRQ(gic_spi(166)), -}; - -static const struct pinctrl_map ape6evm_pinctrl_map[] __initconst = { - /* SCIFA0 console */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4", - "scifa0_data", "scifa0"), - /* SMSC */ - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4", - "irqc_irq40", "irqc"), - /* MMCIF0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4", - "mmc0_data8", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4", - "mmc0_ctrl", "mmc0"), - /* SDHI0: uSD: no WP */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4", - "sdhi0_cd", "sdhi0"), - /* SDHI1 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4", - "sdhi1_data4", "sdhi1"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4", - "sdhi1_ctrl", "sdhi1"), -}; - -static void __init ape6evm_add_standard_devices(void) -{ - - struct clk *parent; - struct clk *mp; - - r8a73a4_clock_init(); - - /* MP clock parent = extal2 */ - parent = clk_get(NULL, "extal2"); - mp = clk_get(NULL, "mp"); - BUG_ON(IS_ERR(parent) || IS_ERR(mp)); - - clk_set_parent(mp, parent); - clk_put(parent); - clk_put(mp); - - pinctrl_register_mappings(ape6evm_pinctrl_map, - ARRAY_SIZE(ape6evm_pinctrl_map)); - r8a73a4_pinmux_init(); - r8a73a4_add_standard_devices(); - - /* LAN9220 ethernet */ - gpio_request_one(270, GPIOF_OUT_INIT_HIGH, NULL); /* smsc9220 RESET */ - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - platform_device_register_resndata(NULL, "smsc911x", -1, - lan9220_res, ARRAY_SIZE(lan9220_res), - &lan9220_data, sizeof(lan9220_data)); - - regulator_register_always_on(1, "MMC0 Vcc", vcc_mmc0_consumers, - ARRAY_SIZE(vcc_mmc0_consumers), 2800000); - platform_device_register_resndata(NULL, "sh_mmcif", 0, - mmcif0_resources, ARRAY_SIZE(mmcif0_resources), - &mmcif0_pdata, sizeof(mmcif0_pdata)); - platform_device_register_data(NULL, "reg-fixed-voltage", 2, - &vcc_sdhi0_info, sizeof(vcc_sdhi0_info)); - platform_device_register_resndata(NULL, "sh_mobile_sdhi", 0, - sdhi0_resources, ARRAY_SIZE(sdhi0_resources), - &sdhi0_pdata, sizeof(sdhi0_pdata)); - regulator_register_always_on(3, "SDHI1 Vcc", vcc_sdhi1_consumers, - ARRAY_SIZE(vcc_sdhi1_consumers), 3300000); - platform_device_register_resndata(NULL, "sh_mobile_sdhi", 1, - sdhi1_resources, ARRAY_SIZE(sdhi1_resources), - &sdhi1_pdata, sizeof(sdhi1_pdata)); - platform_device_register_data(NULL, "gpio-keys", -1, - &ape6evm_keys_pdata, - sizeof(ape6evm_keys_pdata)); - platform_device_register_data(NULL, "leds-gpio", -1, - &ape6evm_leds_pdata, - sizeof(ape6evm_leds_pdata)); -} - -static void __init ape6evm_legacy_init_time(void) -{ - /* Do not invoke DT-based timers via clocksource_of_init() */ -} - -static void __init ape6evm_legacy_init_irq(void) -{ - void __iomem *gic_dist_base = ioremap_nocache(0xf1001000, 0x1000); - void __iomem *gic_cpu_base = ioremap_nocache(0xf1002000, 0x1000); - - gic_init(0, 29, gic_dist_base, gic_cpu_base); - - /* Do not invoke DT-based interrupt code via irqchip_init() */ -} - - -static const char *ape6evm_boards_compat_dt[] __initdata = { - "renesas,ape6evm", - NULL, -}; - -DT_MACHINE_START(APE6EVM_DT, "ape6evm") - .init_early = shmobile_init_delay, - .init_irq = ape6evm_legacy_init_irq, - .init_machine = ape6evm_add_standard_devices, - .init_late = shmobile_init_late, - .dt_compat = ape6evm_boards_compat_dt, - .init_time = ape6evm_legacy_init_time, -MACHINE_END diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c index d649ade..9a74efd 100644 --- a/arch/arm/mach-shmobile/board-bockw-reference.c +++ b/arch/arm/mach-shmobile/board-bockw-reference.c @@ -36,7 +36,9 @@ static void __init bockw_init(void) void __iomem *fpga; void __iomem *pfc; +#ifndef CONFIG_COMMON_CLK r8a7778_clock_init(); +#endif r8a7778_init_irq_extpin_dt(1); r8a7778_add_dt_devices(); diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c deleted file mode 100644 index 2e82e44..0000000 --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * KZM-A9-GT board support - Reference Device Tree Implementation - * - * Copyright (C) 2012 Horms Solutions Ltd. - * - * Based on board-kzm9g.c - * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/input.h> -#include <linux/of_platform.h> - -#include <asm/hardware/cache-l2x0.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include "common.h" -#include "sh73a0.h" - -static void __init kzm_init(void) -{ - sh73a0_add_standard_devices_dt(); - -#ifdef CONFIG_CACHE_L2X0 - /* Shared attribute override enable, 64K*8way */ - l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); -#endif -} - -#define RESCNT2 IOMEM(0xe6188020) -static void kzm9g_restart(enum reboot_mode mode, const char *cmd) -{ - /* Do soft power on reset */ - writel((1 << 31), RESCNT2); -} - -static const char *kzm9g_boards_compat_dt[] __initdata = { - "renesas,kzm9g-reference", - NULL, -}; - -DT_MACHINE_START(KZM9G_DT, "kzm9g-reference") - .smp = smp_ops(sh73a0_smp_ops), - .map_io = sh73a0_map_io, - .init_early = shmobile_init_delay, - .init_machine = kzm_init, - .init_late = shmobile_init_late, - .restart = kzm9g_restart, - .dt_compat = kzm9g_boards_compat_dt, -MACHINE_END diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c deleted file mode 100644 index a1c1dfb..0000000 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ /dev/null @@ -1,1522 +0,0 @@ -/* - * mackerel board support - * - * Copyright (C) 2010 Renesas Solutions Corp. - * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * - * based on ap4evb - * Copyright (C) 2010 Magnus Damm - * Copyright (C) 2008 Yoshihiro Shimoda - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/delay.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/input.h> -#include <linux/io.h> -#include <linux/i2c.h> -#include <linux/leds.h> -#include <linux/mfd/tmio.h> -#include <linux/mmc/host.h> -#include <linux/mmc/sh_mmcif.h> -#include <linux/mmc/sh_mobile_sdhi.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/sh_flctl.h> -#include <linux/pinctrl/machine.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/platform_data/gpio_backlight.h> -#include <linux/pm_clock.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/machine.h> -#include <linux/smsc911x.h> -#include <linux/sh_clk.h> -#include <linux/tca6416_keypad.h> -#include <linux/usb/renesas_usbhs.h> -#include <linux/dma-mapping.h> - -#include <video/sh_mobile_hdmi.h> -#include <video/sh_mobile_lcdc.h> -#include <media/sh_mobile_ceu.h> -#include <media/soc_camera.h> -#include <media/soc_camera_platform.h> -#include <sound/sh_fsi.h> -#include <sound/simple_card.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include "common.h" -#include "intc.h" -#include "irqs.h" -#include "pm-rmobile.h" -#include "sh-gpio.h" -#include "sh7372.h" - -/* - * Address Interface BusWidth note - * ------------------------------------------------------------------ - * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON - * 0x0800_0000 user area - - * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF - * 0x1400_0000 Ether (LAN9220) 16bit - * 0x1600_0000 user area - cannot use with NAND - * 0x1800_0000 user area - - * 0x1A00_0000 - - * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit - */ - -/* - * CPU mode - * - * SW4 | Boot Area| Master | Remarks - * 1 | 2 | 3 | 4 | 5 | 6 | 8 | | Processor| - * ----+-----+-----+-----+-----+-----+-----+----------+----------+-------------- - * ON | ON | OFF | ON | ON | OFF | OFF | External | System | External ROM - * ON | ON | ON | ON | ON | OFF | OFF | External | System | ROM Debug - * ON | ON | X | ON | OFF | OFF | OFF | Built-in | System | ROM Debug - * X | OFF | X | X | X | X | OFF | Built-in | System | MaskROM - * OFF | X | X | X | X | X | OFF | Built-in | System | MaskROM - * X | X | X | OFF | X | X | OFF | Built-in | System | MaskROM - * OFF | ON | OFF | X | X | OFF | ON | External | System | Standalone - * ON | OFF | OFF | X | X | OFF | ON | External | Realtime | Standalone -*/ - -/* - * NOR Flash ROM - * - * SW1 | SW2 | SW7 | NOR Flash ROM - * bit1 | bit1 bit2 | bit1 | Memory allocation - * ------+------------+------+------------------ - * OFF | ON OFF | ON | Area 0 - * OFF | ON OFF | OFF | Area 4 - */ - -/* - * SMSC 9220 - * - * SW1 SMSC 9220 - * ----------------------- - * ON access disable - * OFF access enable - */ - -/* - * NAND Flash ROM - * - * SW1 | SW2 | SW7 | NAND Flash ROM - * bit1 | bit1 bit2 | bit2 | Memory allocation - * ------+------------+------+------------------ - * OFF | ON OFF | ON | FCE 0 - * OFF | ON OFF | OFF | FCE 1 - */ - -/* - * External interrupt pin settings - * - * IRQX | pin setting | device | level - * ------+--------------------+--------------------+------- - * IRQ0 | ICR1A.IRQ0SA=0010 | SDHI2 card detect | Low - * IRQ6 | ICR1A.IRQ6SA=0011 | Ether(LAN9220) | High - * IRQ7 | ICR1A.IRQ7SA=0010 | LCD Touch Panel | Low - * IRQ8 | ICR2A.IRQ8SA=0010 | MMC/SD card detect | Low - * IRQ9 | ICR2A.IRQ9SA=0010 | KEY(TCA6408) | Low - * IRQ21 | ICR4A.IRQ21SA=0011 | Sensor(ADXL345) | High - * IRQ22 | ICR4A.IRQ22SA=0011 | Sensor(AK8975) | High - */ - -/* - * USB - * - * USB0 : CN22 : Function - * USB1 : CN31 : Function/Host *1 - * - * J30 (for CN31) *1 - * ----------+---------------+------------- - * 1-2 short | VBUS 5V | Host - * open | external VBUS | Function - * - * CAUTION - * - * renesas_usbhs driver can use external interrupt mode - * (which come from USB-PHY) or autonomy mode (it use own interrupt) - * for detecting connection/disconnection when Function. - * USB will be power OFF while it has been disconnecting - * if external interrupt mode, and it is always power ON if autonomy mode, - * - * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0", - * because Touchscreen is using IRQ7-PORT40. - * It is impossible to use IRQ7 demux on this board. - */ - -/* - * SDHI0 (CN12) - * - * SW56 : OFF - * - */ - -/* MMC /SDHI1 (CN7) - * - * I/O voltage : 1.8v - * - * Power voltage : 1.8v or 3.3v - * J22 : select power voltage *1 - * 1-2 pin : 1.8v - * 2-3 pin : 3.3v - * - * *1 - * Please change J22 depends the card to be used. - * MMC's OCR field set to support either voltage for the card inserted. - * - * SW1 | SW33 - * | bit1 | bit2 | bit3 | bit4 - * -------------+------+------+------+------- - * MMC0 OFF | OFF | X | ON | X (Use MMCIF) - * SDHI1 OFF | ON | X | OFF | X (Use MFD_SH_MOBILE_SDHI) - * - */ - -/* - * SDHI2 (CN23) - * - * microSD card sloct - * - */ - -/* - * FSI - AK4642 - * - * it needs amixer settings for playing - * - * amixer set "Headphone Enable" on - */ - -/* Fixed 3.3V and 1.8V regulators to be used by multiple devices */ -static struct regulator_consumer_supply fixed1v8_power_consumers[] = -{ - /* - * J22 on mackerel switches mmcif.0 and sdhi.1 between 1.8V and 3.3V - * Since we cannot support both voltages, we support the default 1.8V - */ - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), - REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"), - REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), - REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"), -}; - -static struct regulator_consumer_supply fixed3v3_power_consumers[] = -{ - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), - REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), - REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"), - REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.2"), -}; - -/* Dummy supplies, where voltage doesn't matter */ -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vddvario", "smsc911x"), - REGULATOR_SUPPLY("vdd33a", "smsc911x"), -}; - -/* MTD */ -static struct mtd_partition nor_flash_partitions[] = { - { - .name = "loader", - .offset = 0x00000000, - .size = 512 * 1024, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "bootenv", - .offset = MTDPART_OFS_APPEND, - .size = 512 * 1024, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "kernel_ro", - .offset = MTDPART_OFS_APPEND, - .size = 8 * 1024 * 1024, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = 8 * 1024 * 1024, - }, - { - .name = "data", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct physmap_flash_data nor_flash_data = { - .width = 2, - .parts = nor_flash_partitions, - .nr_parts = ARRAY_SIZE(nor_flash_partitions), -}; - -static struct resource nor_flash_resources[] = { - [0] = { - .start = 0x20000000, /* CS0 shadow instead of regular CS0 */ - .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */ - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device nor_flash_device = { - .name = "physmap-flash", - .dev = { - .platform_data = &nor_flash_data, - }, - .num_resources = ARRAY_SIZE(nor_flash_resources), - .resource = nor_flash_resources, -}; - -/* SMSC */ -static struct resource smc911x_resources[] = { - { - .start = 0x14000000, - .end = 0x16000000 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = evt2irq(0x02c0) /* IRQ6A */, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_info = { - .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, -}; - -static struct platform_device smc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smc911x_resources), - .resource = smc911x_resources, - .dev = { - .platform_data = &smsc911x_info, - }, -}; - -/* MERAM */ -static struct sh_mobile_meram_info mackerel_meram_info = { - .addr_mode = SH_MOBILE_MERAM_MODE1, -}; - -static struct resource meram_resources[] = { - [0] = { - .name = "regs", - .start = 0xe8000000, - .end = 0xe807ffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = "meram", - .start = 0xe8080000, - .end = 0xe81fffff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device meram_device = { - .name = "sh_mobile_meram", - .id = 0, - .num_resources = ARRAY_SIZE(meram_resources), - .resource = meram_resources, - .dev = { - .platform_data = &mackerel_meram_info, - }, -}; - -/* LCDC and backlight */ -static struct fb_videomode mackerel_lcdc_modes[] = { - { - .name = "WVGA Panel", - .xres = 800, - .yres = 480, - .left_margin = 220, - .right_margin = 110, - .hsync_len = 70, - .upper_margin = 20, - .lower_margin = 5, - .vsync_len = 5, - .sync = 0, - }, -}; - -static const struct sh_mobile_meram_cfg lcd_meram_cfg = { - .icb[0] = { - .meram_size = 0x40, - }, - .icb[1] = { - .meram_size = 0x40, - }, -}; - -static struct sh_mobile_lcdc_info lcdc_info = { - .meram_dev = &mackerel_meram_info, - .clock_source = LCDC_CLK_BUS, - .ch[0] = { - .chan = LCDC_CHAN_MAINLCD, - .fourcc = V4L2_PIX_FMT_RGB565, - .lcd_modes = mackerel_lcdc_modes, - .num_modes = ARRAY_SIZE(mackerel_lcdc_modes), - .interface_type = RGB24, - .clock_divider = 3, - .flags = 0, - .panel_cfg = { - .width = 152, - .height = 91, - }, - .meram_cfg = &lcd_meram_cfg, - } -}; - -static struct resource lcdc_resources[] = { - [0] = { - .name = "LCDC", - .start = 0xfe940000, - .end = 0xfe943fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = intcs_evt2irq(0x580), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device lcdc_device = { - .name = "sh_mobile_lcdc_fb", - .num_resources = ARRAY_SIZE(lcdc_resources), - .resource = lcdc_resources, - .dev = { - .platform_data = &lcdc_info, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct gpio_backlight_platform_data gpio_backlight_data = { - .fbdev = &lcdc_device.dev, - .gpio = 31, - .def_value = 1, - .name = "backlight", -}; - -static struct platform_device gpio_backlight_device = { - .name = "gpio-backlight", - .dev = { - .platform_data = &gpio_backlight_data, - }, -}; - -/* HDMI */ -static struct sh_mobile_hdmi_info hdmi_info = { - .flags = HDMI_SND_SRC_SPDIF, -}; - -static struct resource hdmi_resources[] = { - [0] = { - .name = "HDMI", - .start = 0xe6be0000, - .end = 0xe6be00ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - /* There's also an HDMI interrupt on INTCS @ 0x18e0 */ - .start = evt2irq(0x17e0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device hdmi_device = { - .name = "sh-mobile-hdmi", - .num_resources = ARRAY_SIZE(hdmi_resources), - .resource = hdmi_resources, - .id = -1, - .dev = { - .platform_data = &hdmi_info, - }, -}; - -static const struct sh_mobile_meram_cfg hdmi_meram_cfg = { - .icb[0] = { - .meram_size = 0x100, - }, - .icb[1] = { - .meram_size = 0x100, - }, -}; - -static struct sh_mobile_lcdc_info hdmi_lcdc_info = { - .meram_dev = &mackerel_meram_info, - .clock_source = LCDC_CLK_EXTERNAL, - .ch[0] = { - .chan = LCDC_CHAN_MAINLCD, - .fourcc = V4L2_PIX_FMT_RGB565, - .interface_type = RGB24, - .clock_divider = 1, - .flags = LCDC_FLAGS_DWPOL, - .meram_cfg = &hdmi_meram_cfg, - .tx_dev = &hdmi_device, - } -}; - -static struct resource hdmi_lcdc_resources[] = { - [0] = { - .name = "LCDC1", - .start = 0xfe944000, - .end = 0xfe947fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = intcs_evt2irq(0x1780), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device hdmi_lcdc_device = { - .name = "sh_mobile_lcdc_fb", - .num_resources = ARRAY_SIZE(hdmi_lcdc_resources), - .resource = hdmi_lcdc_resources, - .id = 1, - .dev = { - .platform_data = &hdmi_lcdc_info, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct asoc_simple_card_info fsi2_hdmi_info = { - .name = "HDMI", - .card = "FSI2B-HDMI", - .codec = "sh-mobile-hdmi", - .platform = "sh_fsi2", - .daifmt = SND_SOC_DAIFMT_CBS_CFS, - .cpu_dai = { - .name = "fsib-dai", - }, - .codec_dai = { - .name = "sh_mobile_hdmi-hifi", - }, -}; - -static struct platform_device fsi_hdmi_device = { - .name = "asoc-simple-card", - .id = 1, - .dev = { - .platform_data = &fsi2_hdmi_info, - .coherent_dma_mask = DMA_BIT_MASK(32), - .dma_mask = &fsi_hdmi_device.dev.coherent_dma_mask, - }, -}; - -static void __init hdmi_init_pm_clock(void) -{ - struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); - int ret; - long rate; - - if (IS_ERR(hdmi_ick)) { - ret = PTR_ERR(hdmi_ick); - pr_err("Cannot get HDMI ICK: %d\n", ret); - goto out; - } - - ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk); - if (ret < 0) { - pr_err("Cannot set PLLC2 parent: %d, %d users\n", - ret, sh7372_pllc2_clk.usecount); - goto out; - } - - pr_debug("PLLC2 initial frequency %lu\n", - clk_get_rate(&sh7372_pllc2_clk)); - - rate = clk_round_rate(&sh7372_pllc2_clk, 594000000); - if (rate <= 0) { - pr_err("Cannot get suitable rate: %ld\n", rate); - ret = -EINVAL; - goto out; - } - - ret = clk_set_rate(&sh7372_pllc2_clk, rate); - if (ret < 0) { - pr_err("Cannot set rate %ld: %d\n", rate, ret); - goto out; - } - - pr_debug("PLLC2 set frequency %lu\n", rate); - - ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); - if (ret < 0) - pr_err("Cannot set HDMI parent: %d\n", ret); - -out: - if (!IS_ERR(hdmi_ick)) - clk_put(hdmi_ick); -} - -/* USBHS0 is connected to CN22 which takes a USB Mini-B plug - * - * The sh7372 SoC has IRQ7 set aside for USBHS0 hotplug, - * but on this particular board IRQ7 is already used by - * the touch screen. This leaves us with software polling. - */ -#define USBHS0_POLL_INTERVAL (HZ * 5) - -struct usbhs_private { - void __iomem *usbphyaddr; - void __iomem *usbcrcaddr; - struct renesas_usbhs_platform_info info; - struct delayed_work work; - struct platform_device *pdev; -}; - -#define usbhs_get_priv(pdev) \ - container_of(renesas_usbhs_get_info(pdev), \ - struct usbhs_private, info) - -#define usbhs_is_connected(priv) \ - (!((1 << 7) & __raw_readw(priv->usbcrcaddr))) - -static int usbhs_get_vbus(struct platform_device *pdev) -{ - return usbhs_is_connected(usbhs_get_priv(pdev)); -} - -static int usbhs_phy_reset(struct platform_device *pdev) -{ - struct usbhs_private *priv = usbhs_get_priv(pdev); - - /* init phy */ - __raw_writew(0x8a0a, priv->usbcrcaddr); - - return 0; -} - -static int usbhs0_get_id(struct platform_device *pdev) -{ - return USBHS_GADGET; -} - -static void usbhs0_work_function(struct work_struct *work) -{ - struct usbhs_private *priv = container_of(work, struct usbhs_private, - work.work); - - renesas_usbhs_call_notify_hotplug(priv->pdev); - schedule_delayed_work(&priv->work, USBHS0_POLL_INTERVAL); -} - -static int usbhs0_hardware_init(struct platform_device *pdev) -{ - struct usbhs_private *priv = usbhs_get_priv(pdev); - - priv->pdev = pdev; - INIT_DELAYED_WORK(&priv->work, usbhs0_work_function); - schedule_delayed_work(&priv->work, USBHS0_POLL_INTERVAL); - return 0; -} - -static int usbhs0_hardware_exit(struct platform_device *pdev) -{ - struct usbhs_private *priv = usbhs_get_priv(pdev); - - cancel_delayed_work_sync(&priv->work); - - return 0; -} - -static struct usbhs_private usbhs0_private = { - .usbcrcaddr = IOMEM(0xe605810c), /* USBCR2 */ - .info = { - .platform_callback = { - .hardware_init = usbhs0_hardware_init, - .hardware_exit = usbhs0_hardware_exit, - .phy_reset = usbhs_phy_reset, - .get_id = usbhs0_get_id, - .get_vbus = usbhs_get_vbus, - }, - .driver_param = { - .buswait_bwait = 4, - .d0_tx_id = SHDMA_SLAVE_USB0_TX, - .d1_rx_id = SHDMA_SLAVE_USB0_RX, - }, - }, -}; - -static struct resource usbhs0_resources[] = { - [0] = { - .name = "USBHS0", - .start = 0xe6890000, - .end = 0xe68900e6 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = evt2irq(0x1ca0) /* USB0_USB0I0 */, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device usbhs0_device = { - .name = "renesas_usbhs", - .id = 0, - .dev = { - .platform_data = &usbhs0_private.info, - }, - .num_resources = ARRAY_SIZE(usbhs0_resources), - .resource = usbhs0_resources, -}; - -/* USBHS1 is connected to CN31 which takes a USB Mini-AB plug - * - * Use J30 to select between Host and Function. This setting - * can however not be detected by software. Hotplug of USBHS1 - * is provided via IRQ8. - * - * Current USB1 works as "USB Host". - * - set J30 "short" - * - * If you want to use it as "USB gadget", - * - J30 "open" - * - modify usbhs1_get_id() USBHS_HOST -> USBHS_GADGET - * - add .get_vbus = usbhs_get_vbus in usbhs1_private - * - check usbhs0_device(pio)/usbhs1_device(irq) order in mackerel_devices. - */ -#define IRQ8 evt2irq(0x0300) -#define USB_PHY_MODE (1 << 4) -#define USB_PHY_INT_EN ((1 << 3) | (1 << 2)) -#define USB_PHY_ON (1 << 1) -#define USB_PHY_OFF (1 << 0) -#define USB_PHY_INT_CLR (USB_PHY_ON | USB_PHY_OFF) - -static irqreturn_t usbhs1_interrupt(int irq, void *data) -{ - struct platform_device *pdev = data; - struct usbhs_private *priv = usbhs_get_priv(pdev); - - dev_dbg(&pdev->dev, "%s\n", __func__); - - renesas_usbhs_call_notify_hotplug(pdev); - - /* clear status */ - __raw_writew(__raw_readw(priv->usbphyaddr) | USB_PHY_INT_CLR, - priv->usbphyaddr); - - return IRQ_HANDLED; -} - -static int usbhs1_hardware_init(struct platform_device *pdev) -{ - struct usbhs_private *priv = usbhs_get_priv(pdev); - int ret; - - /* clear interrupt status */ - __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr); - - ret = request_irq(IRQ8, usbhs1_interrupt, IRQF_TRIGGER_HIGH, - dev_name(&pdev->dev), pdev); - if (ret) { - dev_err(&pdev->dev, "request_irq err\n"); - return ret; - } - - /* enable USB phy interrupt */ - __raw_writew(USB_PHY_MODE | USB_PHY_INT_EN, priv->usbphyaddr); - - return 0; -} - -static int usbhs1_hardware_exit(struct platform_device *pdev) -{ - struct usbhs_private *priv = usbhs_get_priv(pdev); - - /* clear interrupt status */ - __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr); - - free_irq(IRQ8, pdev); - - return 0; -} - -static int usbhs1_get_id(struct platform_device *pdev) -{ - return USBHS_HOST; -} - -static u32 usbhs1_pipe_cfg[] = { - USB_ENDPOINT_XFER_CONTROL, - USB_ENDPOINT_XFER_ISOC, - USB_ENDPOINT_XFER_ISOC, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_INT, - USB_ENDPOINT_XFER_INT, - USB_ENDPOINT_XFER_INT, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, - USB_ENDPOINT_XFER_BULK, -}; - -static struct usbhs_private usbhs1_private = { - .usbphyaddr = IOMEM(0xe60581e2), /* USBPHY1INTAP */ - .usbcrcaddr = IOMEM(0xe6058130), /* USBCR4 */ - .info = { - .platform_callback = { - .hardware_init = usbhs1_hardware_init, - .hardware_exit = usbhs1_hardware_exit, - .get_id = usbhs1_get_id, - .phy_reset = usbhs_phy_reset, - }, - .driver_param = { - .buswait_bwait = 4, - .has_otg = 1, - .pipe_type = usbhs1_pipe_cfg, - .pipe_size = ARRAY_SIZE(usbhs1_pipe_cfg), - .d0_tx_id = SHDMA_SLAVE_USB1_TX, - .d1_rx_id = SHDMA_SLAVE_USB1_RX, - }, - }, -}; - -static struct resource usbhs1_resources[] = { - [0] = { - .name = "USBHS1", - .start = 0xe68b0000, - .end = 0xe68b00e6 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = evt2irq(0x1ce0) /* USB1_USB1I0 */, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device usbhs1_device = { - .name = "renesas_usbhs", - .id = 1, - .dev = { - .platform_data = &usbhs1_private.info, - .dma_mask = &usbhs1_device.dev.coherent_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(usbhs1_resources), - .resource = usbhs1_resources, -}; - -/* LED */ -static struct gpio_led mackerel_leds[] = { - { - .name = "led0", - .gpio = 0, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, - { - .name = "led1", - .gpio = 1, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, - { - .name = "led2", - .gpio = 2, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, - { - .name = "led3", - .gpio = 159, - .default_state = LEDS_GPIO_DEFSTATE_ON, - } -}; - -static struct gpio_led_platform_data mackerel_leds_pdata = { - .leds = mackerel_leds, - .num_leds = ARRAY_SIZE(mackerel_leds), -}; - -static struct platform_device leds_device = { - .name = "leds-gpio", - .id = 0, - .dev = { - .platform_data = &mackerel_leds_pdata, - }, -}; - -/* FSI */ -#define IRQ_FSI evt2irq(0x1840) -static struct sh_fsi_platform_info fsi_info = { - .port_a = { - .tx_id = SHDMA_SLAVE_FSIA_TX, - .rx_id = SHDMA_SLAVE_FSIA_RX, - }, - .port_b = { - .flags = SH_FSI_CLK_CPG | - SH_FSI_FMT_SPDIF, - } -}; - -static struct resource fsi_resources[] = { - [0] = { - /* we need 0xFE1F0000 to access DMA - * instead of 0xFE3C0000 */ - .name = "FSI", - .start = 0xFE1F0000, - .end = 0xFE1F0400 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_FSI, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device fsi_device = { - .name = "sh_fsi2", - .id = -1, - .num_resources = ARRAY_SIZE(fsi_resources), - .resource = fsi_resources, - .dev = { - .platform_data = &fsi_info, - }, -}; - -static struct asoc_simple_card_info fsi2_ak4643_info = { - .name = "AK4643", - .card = "FSI2A-AK4643", - .codec = "ak4642-codec.0-0013", - .platform = "sh_fsi2", - .daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM, - .cpu_dai = { - .name = "fsia-dai", - }, - .codec_dai = { - .name = "ak4642-hifi", - .sysclk = 11289600, - }, -}; - -static struct platform_device fsi_ak4643_device = { - .name = "asoc-simple-card", - .dev = { - .platform_data = &fsi2_ak4643_info, - .coherent_dma_mask = DMA_BIT_MASK(32), - .dma_mask = &fsi_ak4643_device.dev.coherent_dma_mask, - }, -}; - -/* FLCTL */ -static struct mtd_partition nand_partition_info[] = { - { - .name = "system", - .offset = 0, - .size = 128 * 1024 * 1024, - }, - { - .name = "userdata", - .offset = MTDPART_OFS_APPEND, - .size = 256 * 1024 * 1024, - }, - { - .name = "cache", - .offset = MTDPART_OFS_APPEND, - .size = 128 * 1024 * 1024, - }, -}; - -static struct resource nand_flash_resources[] = { - [0] = { - .start = 0xe6a30000, - .end = 0xe6a3009b, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = evt2irq(0x0d80), /* flstei: status error irq */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct sh_flctl_platform_data nand_flash_data = { - .parts = nand_partition_info, - .nr_parts = ARRAY_SIZE(nand_partition_info), - .flcmncr_val = CLK_16B_12L_4H | TYPESEL_SET - | SHBUSSEL | SEL_16BIT | SNAND_E, - .use_holden = 1, -}; - -static struct platform_device nand_flash_device = { - .name = "sh_flctl", - .resource = nand_flash_resources, - .num_resources = ARRAY_SIZE(nand_flash_resources), - .dev = { - .platform_data = &nand_flash_data, - }, -}; - -/* SDHI0 */ -static struct sh_mobile_sdhi_info sdhi0_info = { - .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, - .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, - .tmio_flags = TMIO_MMC_USE_GPIO_CD, - .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, - .cd_gpio = 172, -}; - -static struct resource sdhi0_resources[] = { - { - .name = "SDHI0", - .start = 0xe6850000, - .end = 0xe68500ff, - .flags = IORESOURCE_MEM, - }, { - .name = SH_MOBILE_SDHI_IRQ_SDCARD, - .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */, - .flags = IORESOURCE_IRQ, - }, { - .name = SH_MOBILE_SDHI_IRQ_SDIO, - .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device sdhi0_device = { - .name = "sh_mobile_sdhi", - .num_resources = ARRAY_SIZE(sdhi0_resources), - .resource = sdhi0_resources, - .id = 0, - .dev = { - .platform_data = &sdhi0_info, - }, -}; - -#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF) -/* SDHI1 */ - -/* GPIO 41 can trigger IRQ8, but it is used by USBHS1, we have to poll */ -static struct sh_mobile_sdhi_info sdhi1_info = { - .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, - .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, - .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD, - .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | - MMC_CAP_NEEDS_POLL, - .cd_gpio = 41, -}; - -static struct resource sdhi1_resources[] = { - { - .name = "SDHI1", - .start = 0xe6860000, - .end = 0xe68600ff, - .flags = IORESOURCE_MEM, - }, { - .name = SH_MOBILE_SDHI_IRQ_SDCARD, - .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */ - .flags = IORESOURCE_IRQ, - }, { - .name = SH_MOBILE_SDHI_IRQ_SDIO, - .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device sdhi1_device = { - .name = "sh_mobile_sdhi", - .num_resources = ARRAY_SIZE(sdhi1_resources), - .resource = sdhi1_resources, - .id = 1, - .dev = { - .platform_data = &sdhi1_info, - }, -}; -#endif - -/* SDHI2 */ - -/* - * The card detect pin of the top SD/MMC slot (CN23) is active low and is - * connected to GPIO SCIFB_SCK of SH7372 (GPIO 162). - */ -static struct sh_mobile_sdhi_info sdhi2_info = { - .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX, - .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX, - .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD, - .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | - MMC_CAP_NEEDS_POLL, - .cd_gpio = 162, -}; - -static struct resource sdhi2_resources[] = { - { - .name = "SDHI2", - .start = 0xe6870000, - .end = 0xe68700ff, - .flags = IORESOURCE_MEM, - }, { - .name = SH_MOBILE_SDHI_IRQ_SDCARD, - .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */ - .flags = IORESOURCE_IRQ, - }, { - .name = SH_MOBILE_SDHI_IRQ_SDIO, - .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device sdhi2_device = { - .name = "sh_mobile_sdhi", - .num_resources = ARRAY_SIZE(sdhi2_resources), - .resource = sdhi2_resources, - .id = 2, - .dev = { - .platform_data = &sdhi2_info, - }, -}; - -/* SH_MMCIF */ -#if IS_ENABLED(CONFIG_MMC_SH_MMCIF) -static struct resource sh_mmcif_resources[] = { - [0] = { - .name = "MMCIF", - .start = 0xE6BD0000, - .end = 0xE6BD00FF, - .flags = IORESOURCE_MEM, - }, - [1] = { - /* MMC ERR */ - .start = evt2irq(0x1ac0), - .flags = IORESOURCE_IRQ, - }, - [2] = { - /* MMC NOR */ - .start = evt2irq(0x1ae0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct sh_mmcif_plat_data sh_mmcif_plat = { - .sup_pclk = 0, - .caps = MMC_CAP_4_BIT_DATA | - MMC_CAP_8_BIT_DATA | - MMC_CAP_NEEDS_POLL, - .use_cd_gpio = true, - /* card detect pin for SD/MMC slot (CN7) */ - .cd_gpio = 41, - .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, - .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, -}; - -static struct platform_device sh_mmcif_device = { - .name = "sh_mmcif", - .id = 0, - .dev = { - .dma_mask = NULL, - .coherent_dma_mask = 0xffffffff, - .platform_data = &sh_mmcif_plat, - }, - .num_resources = ARRAY_SIZE(sh_mmcif_resources), - .resource = sh_mmcif_resources, -}; -#endif - -static int mackerel_camera_add(struct soc_camera_device *icd); -static void mackerel_camera_del(struct soc_camera_device *icd); - -static int camera_set_capture(struct soc_camera_platform_info *info, - int enable) -{ - return 0; /* camera sensor always enabled */ -} - -static struct soc_camera_platform_info camera_info = { - .format_name = "UYVY", - .format_depth = 16, - .format = { - .code = MEDIA_BUS_FMT_UYVY8_2X8, - .colorspace = V4L2_COLORSPACE_SMPTE170M, - .field = V4L2_FIELD_NONE, - .width = 640, - .height = 480, - }, - .mbus_param = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER | - V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH | - V4L2_MBUS_DATA_ACTIVE_HIGH, - .mbus_type = V4L2_MBUS_PARALLEL, - .set_capture = camera_set_capture, -}; - -static struct soc_camera_link camera_link = { - .bus_id = 0, - .add_device = mackerel_camera_add, - .del_device = mackerel_camera_del, - .module_name = "soc_camera_platform", - .priv = &camera_info, -}; - -static struct platform_device *camera_device; - -static void mackerel_camera_release(struct device *dev) -{ - soc_camera_platform_release(&camera_device); -} - -static int mackerel_camera_add(struct soc_camera_device *icd) -{ - return soc_camera_platform_add(icd, &camera_device, &camera_link, - mackerel_camera_release, 0); -} - -static void mackerel_camera_del(struct soc_camera_device *icd) -{ - soc_camera_platform_del(icd, camera_device, &camera_link); -} - -static struct sh_mobile_ceu_info sh_mobile_ceu_info = { - .flags = SH_CEU_FLAG_USE_8BIT_BUS, - .max_width = 8188, - .max_height = 8188, -}; - -static struct resource ceu_resources[] = { - [0] = { - .name = "CEU", - .start = 0xfe910000, - .end = 0xfe91009f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = intcs_evt2irq(0x880), - .flags = IORESOURCE_IRQ, - }, - [2] = { - /* place holder for contiguous memory */ - }, -}; - -static struct platform_device ceu_device = { - .name = "sh_mobile_ceu", - .id = 0, /* "ceu0" clock */ - .num_resources = ARRAY_SIZE(ceu_resources), - .resource = ceu_resources, - .dev = { - .platform_data = &sh_mobile_ceu_info, - .coherent_dma_mask = 0xffffffff, - }, -}; - -static struct platform_device mackerel_camera = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &camera_link, - }, -}; - -static struct platform_device *mackerel_devices[] __initdata = { - &nor_flash_device, - &smc911x_device, - &lcdc_device, - &gpio_backlight_device, - &usbhs0_device, - &usbhs1_device, - &leds_device, - &fsi_device, - &fsi_ak4643_device, - &fsi_hdmi_device, - &nand_flash_device, - &sdhi0_device, -#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF) - &sdhi1_device, -#else - &sh_mmcif_device, -#endif - &sdhi2_device, - &ceu_device, - &mackerel_camera, - &hdmi_device, - &hdmi_lcdc_device, - &meram_device, -}; - -/* Keypad Initialization */ -#define KEYPAD_BUTTON(ev_type, ev_code, act_low) \ -{ \ - .type = ev_type, \ - .code = ev_code, \ - .active_low = act_low, \ -} - -#define KEYPAD_BUTTON_LOW(event_code) KEYPAD_BUTTON(EV_KEY, event_code, 1) - -static struct tca6416_button mackerel_gpio_keys[] = { - KEYPAD_BUTTON_LOW(KEY_HOME), - KEYPAD_BUTTON_LOW(KEY_MENU), - KEYPAD_BUTTON_LOW(KEY_BACK), - KEYPAD_BUTTON_LOW(KEY_POWER), -}; - -static struct tca6416_keys_platform_data mackerel_tca6416_keys_info = { - .buttons = mackerel_gpio_keys, - .nbuttons = ARRAY_SIZE(mackerel_gpio_keys), - .rep = 1, - .use_polling = 0, - .pinmask = 0x000F, -}; - -/* I2C */ -#define IRQ7 evt2irq(0x02e0) -#define IRQ9 evt2irq(0x0320) - -static struct i2c_board_info i2c0_devices[] = { - { - I2C_BOARD_INFO("ak4643", 0x13), - }, - /* Keypad */ - { - I2C_BOARD_INFO("tca6408-keys", 0x20), - .platform_data = &mackerel_tca6416_keys_info, - .irq = IRQ9, - }, - /* Touchscreen */ - { - I2C_BOARD_INFO("st1232-ts", 0x55), - .irq = IRQ7, - }, -}; - -#define IRQ21 evt2irq(0x32a0) - -static struct i2c_board_info i2c1_devices[] = { - /* Accelerometer */ - { - I2C_BOARD_INFO("adxl34x", 0x53), - .irq = IRQ21, - }, -}; - -static unsigned long pin_pulldown_conf[] = { - PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0), -}; - -static const struct pinctrl_map mackerel_pinctrl_map[] = { - /* ADXL34X */ - PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372", - "intc_irq21", "intc"), - /* CEU */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", - "ceu_data_0_7", "ceu"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", - "ceu_clk_0", "ceu"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", - "ceu_sync", "ceu"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372", - "ceu_field", "ceu"), - /* FLCTL */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372", - "flctl_data", "flctl"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372", - "flctl_ce0", "flctl"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372", - "flctl_ctrl", "flctl"), - /* FSIA (AK4643) */ - PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", - "fsia_sclk_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", - "fsia_data_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372", - "fsia_data_out", "fsia"), - /* FSIB (HDMI) */ - PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372", - "fsib_mclk_in", "fsib"), - /* HDMI */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372", - "hdmi", "hdmi"), - /* LCDC */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", - "lcd_data24", "lcd"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372", - "lcd_sync", "lcd"), - /* SCIFA0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372", - "scifa0_data", "scifa0"), - /* SCIFA2 (GT-720F GPS module) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh7372", - "scifa2_data", "scifa2"), - /* SDHI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_wp", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "intc_irq26_1", "intc"), - /* SDHI1 */ -#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF) - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", - "sdhi1_data4", "sdhi1"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", - "sdhi1_ctrl", "sdhi1"), -#else - /* MMCIF */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", - "mmc0_data8_0", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", - "mmc0_ctrl_0", "mmc0"), -#endif - /* SDHI2 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372", - "sdhi2_data4", "sdhi2"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372", - "sdhi2_ctrl", "sdhi2"), - /* SMSC911X */ - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", - "bsc_cs5a", "bsc"), - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372", - "intc_irq6_0", "intc"), - /* ST1232 */ - PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372", - "intc_irq7_0", "intc"), - /* TCA6416 */ - PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372", - "intc_irq9_0", "intc"), - /* USBHS0 */ - PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372", - "usb0_vbus", "usb0"), - PIN_MAP_CONFIGS_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372", - "usb0_vbus", pin_pulldown_conf), - /* USBHS1 */ - PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372", - "usb1_vbus", "usb1"), - PIN_MAP_CONFIGS_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372", - "usb1_vbus", pin_pulldown_conf), - PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372", - "usb1_otg_id_0", "usb1"), -}; - -#define GPIO_PORT9CR IOMEM(0xE6051009) -#define GPIO_PORT10CR IOMEM(0xE605100A) -#define SRCR4 IOMEM(0xe61580bc) -#define USCCR1 IOMEM(0xE6058144) -static void __init mackerel_init(void) -{ - static struct pm_domain_device domain_devices[] __initdata = { - { "A4LC", &lcdc_device, }, - { "A4LC", &hdmi_lcdc_device, }, - { "A4LC", &meram_device, }, - { "A4MP", &fsi_device, }, - { "A3SP", &usbhs0_device, }, - { "A3SP", &usbhs1_device, }, - { "A3SP", &nand_flash_device, }, - { "A3SP", &sdhi0_device, }, -#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF) - { "A3SP", &sdhi1_device, }, -#else - { "A3SP", &sh_mmcif_device, }, -#endif - { "A3SP", &sdhi2_device, }, - { "A4R", &ceu_device, }, - }; - u32 srcr4; - struct clk *clk; - - regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, - ARRAY_SIZE(fixed1v8_power_consumers), 1800000); - regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers, - ARRAY_SIZE(fixed3v3_power_consumers), 3300000); - regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - /* External clock source */ - clk_set_rate(&sh7372_dv_clki_clk, 27000000); - - pinctrl_register_mappings(mackerel_pinctrl_map, - ARRAY_SIZE(mackerel_pinctrl_map)); - sh7372_pinmux_init(); - - gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ - - /* FSI2 port A (ak4643) */ - gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ - - gpio_request(9, NULL); - gpio_request(10, NULL); - gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */ - gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */ - - intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */ - - /* FSI2 port B (HDMI) */ - __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ - - /* set SPU2 clock to 119.6 MHz */ - clk = clk_get(NULL, "spu_clk"); - if (!IS_ERR(clk)) { - clk_set_rate(clk, clk_round_rate(clk, 119600000)); - clk_put(clk); - } - - /* Keypad */ - irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); - - /* Touchscreen */ - irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); - - /* Accelerometer */ - irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); - - /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ - srcr4 = __raw_readl(SRCR4); - __raw_writel(srcr4 | (1 << 13), SRCR4); - udelay(50); - __raw_writel(srcr4 & ~(1 << 13), SRCR4); - - i2c_register_board_info(0, i2c0_devices, - ARRAY_SIZE(i2c0_devices)); - i2c_register_board_info(1, i2c1_devices, - ARRAY_SIZE(i2c1_devices)); - - sh7372_add_standard_devices(); - - platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices)); - - rmobile_add_devices_to_domains(domain_devices, - ARRAY_SIZE(domain_devices)); - - hdmi_init_pm_clock(); - sh7372_pm_init(); - pm_clk_add(&fsi_device.dev, "spu2"); - pm_clk_add(&hdmi_lcdc_device.dev, "hdmi"); -} - -static const char *mackerel_boards_compat_dt[] __initdata = { - "renesas,mackerel", - NULL, -}; - -DT_MACHINE_START(MACKEREL_DT, "mackerel") - .map_io = sh7372_map_io, - .init_early = sh7372_add_early_devices, - .init_irq = sh7372_init_irq, - .handle_irq = shmobile_handle_irq_intc, - .init_machine = mackerel_init, - .init_late = sh7372_pm_init_late, - .init_time = sh7372_earlytimer_init, - .dt_compat = mackerel_boards_compat_dt, -MACHINE_END diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c deleted file mode 100644 index 1cf44dc..0000000 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ /dev/null @@ -1,659 +0,0 @@ -/* - * r8a73a4 clock framework support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/init.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <linux/sh_clk.h> -#include <linux/clkdev.h> -#include "common.h" -#include "clock.h" - -#define CPG_BASE 0xe6150000 -#define CPG_LEN 0x270 - -#define SMSTPCR2 0xe6150138 -#define SMSTPCR3 0xe615013c -#define SMSTPCR4 0xe6150140 -#define SMSTPCR5 0xe6150144 - -#define FRQCRA 0xE6150000 -#define FRQCRB 0xE6150004 -#define FRQCRC 0xE61500E0 -#define VCLKCR1 0xE6150008 -#define VCLKCR2 0xE615000C -#define VCLKCR3 0xE615001C -#define VCLKCR4 0xE6150014 -#define VCLKCR5 0xE6150034 -#define ZBCKCR 0xE6150010 -#define SD0CKCR 0xE6150074 -#define SD1CKCR 0xE6150078 -#define SD2CKCR 0xE615007C -#define MMC0CKCR 0xE6150240 -#define MMC1CKCR 0xE6150244 -#define FSIACKCR 0xE6150018 -#define FSIBCKCR 0xE6150090 -#define MPCKCR 0xe6150080 -#define SPUVCKCR 0xE6150094 -#define HSICKCR 0xE615026C -#define M4CKCR 0xE6150098 -#define PLLECR 0xE61500D0 -#define PLL0CR 0xE61500D8 -#define PLL1CR 0xE6150028 -#define PLL2CR 0xE615002C -#define PLL2SCR 0xE61501F4 -#define PLL2HCR 0xE61501E4 -#define CKSCR 0xE61500C0 - -#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base) - -static struct clk_mapping cpg_mapping = { - .phys = CPG_BASE, - .len = CPG_LEN, -}; - -static struct clk extalr_clk = { - .rate = 32768, - .mapping = &cpg_mapping, -}; - -static struct clk extal1_clk = { - .rate = 26000000, - .mapping = &cpg_mapping, -}; - -static struct clk extal2_clk = { - .rate = 48000000, - .mapping = &cpg_mapping, -}; - -static struct sh_clk_ops followparent_clk_ops = { - .recalc = followparent_recalc, -}; - -static struct clk main_clk = { - /* .parent will be set r8a73a4_clock_init */ - .ops = &followparent_clk_ops, -}; - -SH_CLK_RATIO(div2, 1, 2); -SH_CLK_RATIO(div4, 1, 4); - -SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2); -SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); -SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); -SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4); - -/* External FSIACK/FSIBCK clock */ -static struct clk fsiack_clk = { -}; - -static struct clk fsibck_clk = { -}; - -/* - * PLL clocks - */ -static struct clk *pll_parent_main[] = { - [0] = &main_clk, - [1] = &main_div2_clk -}; - -static struct clk *pll_parent_main_extal[8] = { - [0] = &main_div2_clk, - [1] = &extal2_div2_clk, - [3] = &extal2_div4_clk, - [4] = &main_clk, - [5] = &extal2_clk, -}; - -static unsigned long pll_recalc(struct clk *clk) -{ - unsigned long mult = 1; - - if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit)) - mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1); - - return clk->parent->rate * mult; -} - -static int pll_set_parent(struct clk *clk, struct clk *parent) -{ - u32 val; - int i, ret; - - if (!clk->parent_table || !clk->parent_num) - return -EINVAL; - - /* Search the parent */ - for (i = 0; i < clk->parent_num; i++) - if (clk->parent_table[i] == parent) - break; - - if (i == clk->parent_num) - return -ENODEV; - - ret = clk_reparent(clk, parent); - if (ret < 0) - return ret; - - val = ioread32(clk->mapped_reg) & - ~(((1 << clk->src_width) - 1) << clk->src_shift); - - iowrite32(val | i << clk->src_shift, clk->mapped_reg); - - return 0; -} - -static struct sh_clk_ops pll_clk_ops = { - .recalc = pll_recalc, - .set_parent = pll_set_parent, -}; - -#define PLL_CLOCK(name, p, pt, w, s, reg, e) \ - static struct clk name = { \ - .ops = &pll_clk_ops, \ - .flags = CLK_ENABLE_ON_INIT, \ - .parent = p, \ - .parent_table = pt, \ - .parent_num = ARRAY_SIZE(pt), \ - .src_width = w, \ - .src_shift = s, \ - .enable_reg = (void __iomem *)reg, \ - .enable_bit = e, \ - .mapping = &cpg_mapping, \ - } - -PLL_CLOCK(pll0_clk, &main_clk, pll_parent_main, 1, 20, PLL0CR, 0); -PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1); -PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2); -PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4); -PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5); - -SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); - -static atomic_t frqcr_lock; - -/* Several clocks need to access FRQCRB, have to lock */ -static bool frqcr_kick_check(struct clk *clk) -{ - return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31)); -} - -static int frqcr_kick_do(struct clk *clk) -{ - int i; - - /* set KICK bit in FRQCRB to update hardware setting, check success */ - iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB)); - for (i = 1000; i; i--) - if (ioread32(CPG_MAP(FRQCRB)) & BIT(31)) - cpu_relax(); - else - return 0; - - return -ETIMEDOUT; -} - -static int zclk_set_rate(struct clk *clk, unsigned long rate) -{ - void __iomem *frqcrc; - int ret; - unsigned long step, p_rate; - u32 val; - - if (!clk->parent || !__clk_get(clk->parent)) - return -ENODEV; - - if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) { - ret = -EBUSY; - goto done; - } - - /* - * Users are supposed to first call clk_set_rate() only with - * clk_round_rate() results. So, we don't fix wrong rates here, but - * guard against them anyway - */ - - p_rate = clk_get_rate(clk->parent); - if (rate == p_rate) { - val = 0; - } else { - step = DIV_ROUND_CLOSEST(p_rate, 32); - - if (rate > p_rate || rate < step) { - ret = -EINVAL; - goto done; - } - - val = 32 - rate / step; - } - - frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg); - - iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) | - (val << clk->enable_bit), frqcrc); - - ret = frqcr_kick_do(clk); - -done: - atomic_dec(&frqcr_lock); - __clk_put(clk->parent); - return ret; -} - -static long zclk_round_rate(struct clk *clk, unsigned long rate) -{ - /* - * theoretical rate = parent rate * multiplier / 32, - * where 1 <= multiplier <= 32. Therefore we should do - * multiplier = rate * 32 / parent rate - * rounded rate = parent rate * multiplier / 32. - * However, multiplication before division won't fit in 32 bits, so - * we sacrifice some precision by first dividing and then multiplying. - * To find the nearest divisor we calculate both and pick up the best - * one. This avoids 64-bit arithmetics. - */ - unsigned long step, mul_min, mul_max, rate_min, rate_max; - - rate_max = clk_get_rate(clk->parent); - - /* output freq <= parent */ - if (rate >= rate_max) - return rate_max; - - step = DIV_ROUND_CLOSEST(rate_max, 32); - /* output freq >= parent / 32 */ - if (step >= rate) - return step; - - mul_min = rate / step; - mul_max = DIV_ROUND_UP(rate, step); - rate_min = step * mul_min; - if (mul_max == mul_min) - return rate_min; - - rate_max = step * mul_max; - - if (rate_max - rate < rate - rate_min) - return rate_max; - - return rate_min; -} - -static unsigned long zclk_recalc(struct clk *clk) -{ - void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg; - unsigned int max = clk->div_mask + 1; - unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) & - clk->div_mask); - - return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) * - (max - val); -} - -static struct sh_clk_ops zclk_ops = { - .recalc = zclk_recalc, - .set_rate = zclk_set_rate, - .round_rate = zclk_round_rate, -}; - -static struct clk z_clk = { - .parent = &pll0_clk, - .div_mask = 0x1f, - .enable_bit = 8, - /* We'll need to access FRQCRB and FRQCRC */ - .enable_reg = (void __iomem *)FRQCRB, - .ops = &zclk_ops, -}; - -/* - * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3 - * switching is only available in auto-DVFS mode - */ -SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2); - -static struct clk z2_clk = { - .parent = &pll0_div2_clk, - .div_mask = 0x1f, - .enable_bit = 0, - /* We'll need to access FRQCRB and FRQCRC */ - .enable_reg = (void __iomem *)FRQCRB, - .ops = &zclk_ops, -}; - -static struct clk *main_clks[] = { - &extalr_clk, - &extal1_clk, - &extal1_div2_clk, - &extal2_clk, - &extal2_div2_clk, - &extal2_div4_clk, - &main_clk, - &main_div2_clk, - &fsiack_clk, - &fsibck_clk, - &pll0_clk, - &pll1_clk, - &pll1_div2_clk, - &pll2_clk, - &pll2s_clk, - &pll2h_clk, - &z_clk, - &pll0_div2_clk, - &z2_clk, -}; - -/* DIV4 */ -static void div4_kick(struct clk *clk) -{ - if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n")) - frqcr_kick_do(clk); - atomic_dec(&frqcr_lock); -} - -static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10}; - -static struct clk_div_mult_table div4_div_mult_table = { - .divisors = divisors, - .nr_divisors = ARRAY_SIZE(divisors), -}; - -static struct clk_div4_table div4_table = { - .div_mult_table = &div4_div_mult_table, - .kick = div4_kick, -}; - -enum { - DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, - DIV4_ZX, DIV4_ZS, DIV4_HP, - DIV4_NR }; - -static struct clk div4_clks[DIV4_NR] = { - [DIV4_I] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT), - [DIV4_M3] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), - [DIV4_B] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT), - [DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0), - [DIV4_M2] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 0, 0x1dff, 0), - [DIV4_ZX] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0), - [DIV4_ZS] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 8, 0x0dff, 0), - [DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0), -}; - -enum { - DIV6_ZB, - DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, - DIV6_MMC0, DIV6_MMC1, - DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5, - DIV6_FSIA, DIV6_FSIB, - DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV, - DIV6_NR }; - -static struct clk *div6_parents[8] = { - [0] = &pll1_div2_clk, - [1] = &pll2s_clk, - [3] = &extal2_clk, - [4] = &main_div2_clk, - [6] = &extalr_clk, -}; - -static struct clk *fsia_parents[4] = { - [0] = &pll1_div2_clk, - [1] = &pll2s_clk, - [2] = &fsiack_clk, -}; - -static struct clk *fsib_parents[4] = { - [0] = &pll1_div2_clk, - [1] = &pll2s_clk, - [2] = &fsibck_clk, -}; - -static struct clk *mp_parents[4] = { - [0] = &pll1_div2_clk, - [1] = &pll2s_clk, - [2] = &extal2_clk, - [3] = &extal2_clk, -}; - -static struct clk *m4_parents[2] = { - [0] = &pll2s_clk, -}; - -static struct clk *hsi_parents[4] = { - [0] = &pll2h_clk, - [1] = &pll1_div2_clk, - [3] = &pll2s_clk, -}; - -/*** FIXME *** - * SH_CLK_DIV6_EXT() macro doesn't care .mapping - * but, it is necessary on R-Car (= ioremap() base CPG) - * The difference between - * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT() - * is only .mapping - */ -#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents, \ - _num_parents, _src_shift, _src_width) \ -{ \ - .enable_reg = (void __iomem *)_reg, \ - .enable_bit = 0, /* unused */ \ - .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \ - .div_mask = SH_CLK_DIV6_MSK, \ - .parent_table = _parents, \ - .parent_num = _num_parents, \ - .src_shift = _src_shift, \ - .src_width = _src_width, \ - .mapping = &cpg_mapping, \ -} - -static struct clk div6_clks[DIV6_NR] = { - [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT, - div6_parents, 2, 7, 1), - [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0, - div6_parents, 2, 6, 2), - [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0, - div6_parents, 2, 6, 2), - [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0, - div6_parents, 2, 6, 2), - [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0, - div6_parents, 2, 6, 2), - [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0, - div6_parents, 2, 6, 2), - [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */ - div6_parents, ARRAY_SIZE(div6_parents), 12, 3), - [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */ - div6_parents, ARRAY_SIZE(div6_parents), 12, 3), - [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */ - div6_parents, ARRAY_SIZE(div6_parents), 12, 3), - [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */ - div6_parents, ARRAY_SIZE(div6_parents), 12, 3), - [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */ - div6_parents, ARRAY_SIZE(div6_parents), 12, 3), - [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0, - fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2), - [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0, - fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), - [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */ - mp_parents, ARRAY_SIZE(mp_parents), 6, 2), - /* pll2s will be selected always for M4 */ - [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */ - m4_parents, ARRAY_SIZE(m4_parents), 6, 1), - [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */ - hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2), - [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0, - mp_parents, ARRAY_SIZE(mp_parents), 6, 2), -}; - -/* MSTP */ -enum { - MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, - MSTP329, MSTP323, MSTP318, MSTP317, MSTP316, - MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300, - MSTP411, MSTP410, MSTP409, - MSTP522, MSTP515, - MSTP_NR -}; - -static struct clk mstp_clks[MSTP_NR] = { - [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 4, 0), /* SCIFA0 */ - [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 3, 0), /* SCIFA1 */ - [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 6, 0), /* SCIFB0 */ - [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ - [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ - [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ - [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC */ - [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */ - [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ - [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ - [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */ - [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */ - [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */ - [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 16, 0), /* IIC6 */ - [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 17, 0), /* IIC7 */ - [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* IIC0 */ - [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ - [MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */ - [MSTP409] = SH_CLK_MSTP32(&main_div2_clk, SMSTPCR4, 9, 0), /* IIC5 */ - [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */ - [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */ - [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ - [MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR5, 15, 0), /* IIC8 */ -}; - -static struct clk_lookup lookups[] = { - /* main clock */ - CLKDEV_CON_ID("extal1", &extal1_clk), - CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk), - CLKDEV_CON_ID("extal2", &extal2_clk), - CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk), - CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk), - CLKDEV_CON_ID("fsiack", &fsiack_clk), - CLKDEV_CON_ID("fsibck", &fsibck_clk), - - /* pll clock */ - CLKDEV_CON_ID("pll1", &pll1_clk), - CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk), - CLKDEV_CON_ID("pll2", &pll2_clk), - CLKDEV_CON_ID("pll2s", &pll2s_clk), - CLKDEV_CON_ID("pll2h", &pll2h_clk), - - /* CPU clock */ - CLKDEV_DEV_ID("cpu0", &z_clk), - - /* DIV6 */ - CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]), - CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]), - CLKDEV_CON_ID("vck2", &div6_clks[DIV6_VCK2]), - CLKDEV_CON_ID("vck3", &div6_clks[DIV6_VCK3]), - CLKDEV_CON_ID("vck4", &div6_clks[DIV6_VCK4]), - CLKDEV_CON_ID("vck5", &div6_clks[DIV6_VCK5]), - CLKDEV_CON_ID("fsia", &div6_clks[DIV6_FSIA]), - CLKDEV_CON_ID("fsib", &div6_clks[DIV6_FSIB]), - CLKDEV_CON_ID("mp", &div6_clks[DIV6_MP]), - CLKDEV_CON_ID("m4", &div6_clks[DIV6_M4]), - CLKDEV_CON_ID("hsi", &div6_clks[DIV6_HSI]), - CLKDEV_CON_ID("spuv", &div6_clks[DIV6_SPUV]), - - /* MSTP */ - CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), - CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), - CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), - CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]), - CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), - CLKDEV_DEV_ID("e6c20000.serial", &mstp_clks[MSTP206]), - CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), - CLKDEV_DEV_ID("e6c30000.serial", &mstp_clks[MSTP207]), - CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), - CLKDEV_DEV_ID("e6ce0000.serial", &mstp_clks[MSTP216]), - CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), - CLKDEV_DEV_ID("e6cf0000.serial", &mstp_clks[MSTP217]), - CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), - CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]), - CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), - CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]), - CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), - CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]), - CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), - CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]), - CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), - CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), - CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), - CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), - CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), - CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]), - CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]), - CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]), - CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]), - CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]), - CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.1", &mstp_clks[MSTP329]), - CLKDEV_ICK_ID("fck", "e6130000.timer", &mstp_clks[MSTP329]), - CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]), - CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]), - CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]), - CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]), - - /* for DT */ - CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), -}; - -void __init r8a73a4_clock_init(void) -{ - void __iomem *reg; - int k, ret = 0; - u32 ckscr; - - atomic_set(&frqcr_lock, -1); - - reg = ioremap_nocache(CKSCR, PAGE_SIZE); - BUG_ON(!reg); - ckscr = ioread32(reg); - iounmap(reg); - - switch ((ckscr >> 28) & 0x3) { - case 0: - main_clk.parent = &extal1_clk; - break; - case 1: - main_clk.parent = &extal1_div2_clk; - break; - case 2: - main_clk.parent = &extal2_clk; - break; - case 3: - main_clk.parent = &extal2_div2_clk; - break; - } - - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) - ret = clk_register(main_clks[k]); - - if (!ret) - ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); - - if (!ret) - ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); - - if (!ret) - ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - if (!ret) - shmobile_clk_init(); - else - panic("failed to setup r8a73a4 clocks\n"); -} diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c deleted file mode 100644 index 3bc92f4..0000000 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ /dev/null @@ -1,620 +0,0 @@ -/* - * SH7372 clock framework support - * - * Copyright (C) 2010 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/sh_clk.h> -#include <linux/clkdev.h> -#include "clock.h" -#include "common.h" - -/* SH7372 registers */ -#define FRQCRA IOMEM(0xe6150000) -#define FRQCRB IOMEM(0xe6150004) -#define FRQCRC IOMEM(0xe61500e0) -#define FRQCRD IOMEM(0xe61500e4) -#define VCLKCR1 IOMEM(0xe6150008) -#define VCLKCR2 IOMEM(0xe615000c) -#define VCLKCR3 IOMEM(0xe615001c) -#define FMSICKCR IOMEM(0xe6150010) -#define FMSOCKCR IOMEM(0xe6150014) -#define FSIACKCR IOMEM(0xe6150018) -#define FSIBCKCR IOMEM(0xe6150090) -#define SUBCKCR IOMEM(0xe6150080) -#define SPUCKCR IOMEM(0xe6150084) -#define VOUCKCR IOMEM(0xe6150088) -#define HDMICKCR IOMEM(0xe6150094) -#define DSITCKCR IOMEM(0xe6150060) -#define DSI0PCKCR IOMEM(0xe6150064) -#define DSI1PCKCR IOMEM(0xe6150098) -#define PLLC01CR IOMEM(0xe6150028) -#define PLLC2CR IOMEM(0xe615002c) -#define RMSTPCR0 IOMEM(0xe6150110) -#define RMSTPCR1 IOMEM(0xe6150114) -#define RMSTPCR2 IOMEM(0xe6150118) -#define RMSTPCR3 IOMEM(0xe615011c) -#define RMSTPCR4 IOMEM(0xe6150120) -#define SMSTPCR0 IOMEM(0xe6150130) -#define SMSTPCR1 IOMEM(0xe6150134) -#define SMSTPCR2 IOMEM(0xe6150138) -#define SMSTPCR3 IOMEM(0xe615013c) -#define SMSTPCR4 IOMEM(0xe6150140) - -#define FSIDIVA 0xFE1F8000 -#define FSIDIVB 0xFE1F8008 - -/* Platforms must set frequency on their DV_CLKI pin */ -struct clk sh7372_dv_clki_clk = { -}; - -/* Fixed 32 KHz root clock from EXTALR pin */ -static struct clk r_clk = { - .rate = 32768, -}; - -/* - * 26MHz default rate for the EXTAL1 root input clock. - * If needed, reset this with clk_set_rate() from the platform code. - */ -struct clk sh7372_extal1_clk = { - .rate = 26000000, -}; - -/* - * 48MHz default rate for the EXTAL2 root input clock. - * If needed, reset this with clk_set_rate() from the platform code. - */ -struct clk sh7372_extal2_clk = { - .rate = 48000000, -}; - -SH_CLK_RATIO(div2, 1, 2); - -SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk, sh7372_dv_clki_clk, div2); -SH_FIXED_RATIO_CLK(extal1_div2_clk, sh7372_extal1_clk, div2); -SH_FIXED_RATIO_CLK(extal2_div2_clk, sh7372_extal2_clk, div2); -SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_div2_clk, div2); - -/* PLLC0 and PLLC1 */ -static unsigned long pllc01_recalc(struct clk *clk) -{ - unsigned long mult = 1; - - if (__raw_readl(PLLC01CR) & (1 << 14)) - mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2; - - return clk->parent->rate * mult; -} - -static struct sh_clk_ops pllc01_clk_ops = { - .recalc = pllc01_recalc, -}; - -static struct clk pllc0_clk = { - .ops = &pllc01_clk_ops, - .flags = CLK_ENABLE_ON_INIT, - .parent = &extal1_div2_clk, - .enable_reg = (void __iomem *)FRQCRC, -}; - -static struct clk pllc1_clk = { - .ops = &pllc01_clk_ops, - .flags = CLK_ENABLE_ON_INIT, - .parent = &extal1_div2_clk, - .enable_reg = (void __iomem *)FRQCRA, -}; - -/* Divide PLLC1 by two */ -SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2); - -/* PLLC2 */ - -/* Indices are important - they are the actual src selecting values */ -static struct clk *pllc2_parent[] = { - [0] = &extal1_div2_clk, - [1] = &extal2_div2_clk, - [2] = &sh7372_dv_clki_div2_clk, -}; - -/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */ -static struct cpufreq_frequency_table pllc2_freq_table[29]; - -static void pllc2_table_rebuild(struct clk *clk) -{ - int i; - - /* Initialise PLLC2 frequency table */ - for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) { - pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2; - pllc2_freq_table[i].driver_data = i; - } - - /* This is a special entry - switching PLL off makes it a repeater */ - pllc2_freq_table[i].frequency = clk->parent->rate; - pllc2_freq_table[i].driver_data = i; - - pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END; - pllc2_freq_table[i].driver_data = i; -} - -static unsigned long pllc2_recalc(struct clk *clk) -{ - unsigned long mult = 1; - - pllc2_table_rebuild(clk); - - /* - * If the PLL is off, mult == 1, clk->rate will be updated in - * pllc2_enable(). - */ - if (__raw_readl(PLLC2CR) & (1 << 31)) - mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2; - - return clk->parent->rate * mult; -} - -static long pllc2_round_rate(struct clk *clk, unsigned long rate) -{ - return clk_rate_table_round(clk, clk->freq_table, rate); -} - -static int pllc2_enable(struct clk *clk) -{ - int i; - - __raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR); - - for (i = 0; i < 100; i++) - if (__raw_readl(PLLC2CR) & 0x80000000) { - clk->rate = pllc2_recalc(clk); - return 0; - } - - pr_err("%s(): timeout!\n", __func__); - - return -ETIMEDOUT; -} - -static void pllc2_disable(struct clk *clk) -{ - __raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR); -} - -static int pllc2_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long value; - int idx; - - idx = clk_rate_table_find(clk, clk->freq_table, rate); - if (idx < 0) - return idx; - - if (rate == clk->parent->rate) - return -EINVAL; - - value = __raw_readl(PLLC2CR) & ~(0x3f << 24); - - __raw_writel(value | ((idx + 19) << 24), PLLC2CR); - - clk->rate = clk->freq_table[idx].frequency; - - return 0; -} - -static int pllc2_set_parent(struct clk *clk, struct clk *parent) -{ - u32 value; - int ret, i; - - if (!clk->parent_table || !clk->parent_num) - return -EINVAL; - - /* Search the parent */ - for (i = 0; i < clk->parent_num; i++) - if (clk->parent_table[i] == parent) - break; - - if (i == clk->parent_num) - return -ENODEV; - - ret = clk_reparent(clk, parent); - if (ret < 0) - return ret; - - value = __raw_readl(PLLC2CR) & ~(3 << 6); - - __raw_writel(value | (i << 6), PLLC2CR); - - /* Rebiuld the frequency table */ - pllc2_table_rebuild(clk); - - return 0; -} - -static struct sh_clk_ops pllc2_clk_ops = { - .recalc = pllc2_recalc, - .round_rate = pllc2_round_rate, - .set_rate = pllc2_set_rate, - .enable = pllc2_enable, - .disable = pllc2_disable, - .set_parent = pllc2_set_parent, -}; - -struct clk sh7372_pllc2_clk = { - .ops = &pllc2_clk_ops, - .parent = &extal1_div2_clk, - .freq_table = pllc2_freq_table, - .nr_freqs = ARRAY_SIZE(pllc2_freq_table) - 1, - .parent_table = pllc2_parent, - .parent_num = ARRAY_SIZE(pllc2_parent), -}; - -/* External input clock (pin name: FSIACK/FSIBCK ) */ -static struct clk fsiack_clk = { -}; - -static struct clk fsibck_clk = { -}; - -static struct clk *main_clks[] = { - &sh7372_dv_clki_clk, - &r_clk, - &sh7372_extal1_clk, - &sh7372_extal2_clk, - &sh7372_dv_clki_div2_clk, - &extal1_div2_clk, - &extal2_div2_clk, - &extal2_div4_clk, - &pllc0_clk, - &pllc1_clk, - &pllc1_div2_clk, - &sh7372_pllc2_clk, - &fsiack_clk, - &fsibck_clk, -}; - -static void div4_kick(struct clk *clk) -{ - unsigned long value; - - /* set KICK bit in FRQCRB to update hardware setting */ - value = __raw_readl(FRQCRB); - value |= (1 << 31); - __raw_writel(value, FRQCRB); -} - -static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, - 24, 32, 36, 48, 0, 72, 96, 0 }; - -static struct clk_div_mult_table div4_div_mult_table = { - .divisors = divisors, - .nr_divisors = ARRAY_SIZE(divisors), -}; - -static struct clk_div4_table div4_table = { - .div_mult_table = &div4_div_mult_table, - .kick = div4_kick, -}; - -enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, - DIV4_ZX, DIV4_HP, - DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP, - DIV4_DDRP, DIV4_NR }; - -#define DIV4(_reg, _bit, _mask, _flags) \ - SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags) - -static struct clk div4_clks[DIV4_NR] = { - [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0), - [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0), - [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0), - [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0), - [DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0), - [DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0), - [DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0), - [DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0), - [DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0), -}; - -enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO, - DIV6_SUB, DIV6_SPU, - DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P, - DIV6_NR }; - -static struct clk div6_clks[DIV6_NR] = { - [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0), - [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0), - [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0), - [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0), - [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0), - [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0), - [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0), - [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0), - [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0), - [DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0), - [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0), -}; - -enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR }; - -/* Indices are important - they are the actual src selecting values */ -static struct clk *hdmi_parent[] = { - [0] = &pllc1_div2_clk, - [1] = &sh7372_pllc2_clk, - [2] = &sh7372_dv_clki_clk, - [3] = NULL, /* pllc2_div4 not implemented yet */ -}; - -static struct clk *fsiackcr_parent[] = { - [0] = &pllc1_div2_clk, - [1] = &sh7372_pllc2_clk, - [2] = &fsiack_clk, /* external input for FSI A */ - [3] = NULL, /* setting prohibited */ -}; - -static struct clk *fsibckcr_parent[] = { - [0] = &pllc1_div2_clk, - [1] = &sh7372_pllc2_clk, - [2] = &fsibck_clk, /* external input for FSI B */ - [3] = NULL, /* setting prohibited */ -}; - -static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { - [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0, - hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2), - [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0, - fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2), - [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0, - fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2), -}; - -/* FSI DIV */ -enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR }; - -static struct clk fsidivs[] = { - [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]), - [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]), -}; - -enum { MSTP001, MSTP000, - MSTP131, MSTP130, - MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, - MSTP118, MSTP117, MSTP116, MSTP113, - MSTP106, MSTP101, MSTP100, - MSTP223, - MSTP218, MSTP217, MSTP216, MSTP214, MSTP208, MSTP207, - MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, - MSTP328, MSTP323, MSTP322, MSTP315, MSTP314, MSTP313, MSTP312, - MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406, - MSTP405, MSTP404, MSTP403, MSTP400, - MSTP_NR }; - -#define MSTP(_parent, _reg, _bit, _flags) \ - SH_CLK_MSTP32(_parent, _reg, _bit, _flags) - -static struct clk mstp_clks[MSTP_NR] = { - [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */ - [MSTP000] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 0, 0), /* MSIOF0 */ - [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */ - [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */ - [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */ - [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */ - [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */ - [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */ - [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ - [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */ - [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ - [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ - [MSTP113] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 13, 0), /* MERAM */ - [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */ - [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */ - [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ - [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */ - [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */ - [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */ - [MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */ - [MSTP214] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */ - [MSTP208] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 8, 0), /* MSIOF1 */ - [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ - [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ - [MSTP205] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 5, 0), /* MSIOF2 */ - [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ - [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */ - [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */ - [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ - [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ - [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */ - [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */ - [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */ - [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL*/ - [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */ - [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */ - [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */ - [MSTP423] = MSTP(&div4_clks[DIV4_B], SMSTPCR4, 23, 0), /* DSITX1 */ - [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */ - [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */ - [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */ - [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */ - [MSTP407] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-DMAC1 */ - [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */ - [MSTP405] = MSTP(&r_clk, SMSTPCR4, 5, 0), /* CMT4 */ - [MSTP404] = MSTP(&r_clk, SMSTPCR4, 4, 0), /* CMT3 */ - [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */ - [MSTP400] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* CMT2 */ -}; - -static struct clk_lookup lookups[] = { - /* main clocks */ - CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk), - CLKDEV_CON_ID("r_clk", &r_clk), - CLKDEV_CON_ID("extal1", &sh7372_extal1_clk), - CLKDEV_CON_ID("extal2", &sh7372_extal2_clk), - CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk), - CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk), - CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk), - CLKDEV_CON_ID("pllc0_clk", &pllc0_clk), - CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), - CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), - CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk), - CLKDEV_CON_ID("fsiack", &fsiack_clk), - CLKDEV_CON_ID("fsibck", &fsibck_clk), - - /* DIV4 clocks */ - CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), - CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]), - CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), - CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), - CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]), - CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]), - CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), - CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]), - CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]), - CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]), - CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]), - CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]), - CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]), - - /* DIV6 clocks */ - CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), - CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]), - CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]), - CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]), - CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]), - CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]), - CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]), - CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]), - CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]), - - /* MSTP32 clocks */ - CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */ - CLKDEV_DEV_ID("fff30000.i2c", &mstp_clks[MSTP001]), /* IIC2 */ - CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */ - CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */ - CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */ - CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */ - CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */ - CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */ - CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */ - CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */ - CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */ - CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */ - CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]), /* IIC0 */ - CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[MSTP113]), /* MERAM */ - CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */ - CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */ - CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */ - CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */ - CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */ - CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* DMAC1 */ - CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */ - CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */ - CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), /* USB-DMAC0 */ - CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[MSTP208]), /* MSIOF1 */ - CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ - CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */ - CLKDEV_DEV_ID("spi_sh_msiof.2", &mstp_clks[MSTP205]), /* MSIOF2 */ - CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ - CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ - CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */ - CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ - CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ - CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */ - CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */ - CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), /* IIC1 */ - CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */ - CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */ - CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */ - CLKDEV_DEV_ID("sh_flctl.0", &mstp_clks[MSTP315]), /* FLCTL */ - CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ - CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */ - CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ - CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */ - CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */ - CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMC */ - CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */ - CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */ - CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), /* SDHI2 */ - CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */ - CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */ - CLKDEV_DEV_ID("e6d20000.i2c", &mstp_clks[MSTP411]), /* IIC3 */ - CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */ - CLKDEV_DEV_ID("e6d30000.i2c", &mstp_clks[MSTP410]), /* IIC4 */ - CLKDEV_DEV_ID("sh-dma-engine.4", &mstp_clks[MSTP407]), /* USB-DMAC1 */ - CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */ - CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */ - CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */ - CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ - - /* ICK */ - CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]), - CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), - CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), - CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), - CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1", - &div6_reparent_clks[DIV6_HDMI]), - CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]), - CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]), - CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]), - CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), /* TMU0 */ - CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]), - CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.4", &mstp_clks[MSTP405]), /* CMT4 */ - CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.3", &mstp_clks[MSTP404]), /* CMT3 */ - CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.2", &mstp_clks[MSTP400]), /* CMT2 */ - CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]), - CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]), - CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk), - CLKDEV_ICK_ID("xckb", "sh_fsi2", &fsibck_clk), -}; - -void __init sh7372_clock_init(void) -{ - int k, ret = 0; - - /* make sure MSTP bits on the RT/SH4AL-DSP side are off */ - __raw_writel(0xe4ef8087, RMSTPCR0); - __raw_writel(0xffffffff, RMSTPCR1); - __raw_writel(0x37c7f7ff, RMSTPCR2); - __raw_writel(0xffffffff, RMSTPCR3); - __raw_writel(0xffe0fffd, RMSTPCR4); - - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) - ret = clk_register(main_clks[k]); - - if (!ret) - ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); - - if (!ret) - ret = sh_clk_div6_register(div6_clks, DIV6_NR); - - if (!ret) - ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR); - - if (!ret) - ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); - - if (!ret) - ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - if (!ret) - shmobile_clk_init(); - else - panic("failed to setup sh7372 clocks\n"); -} diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c index 34f056f..68c2d06 100644 --- a/arch/arm/mach-shmobile/clock.c +++ b/arch/arm/mach-shmobile/clock.c @@ -45,14 +45,3 @@ int __init shmobile_clk_init(void) return 0; } - -int __clk_get(struct clk *clk) -{ - return 1; -} -EXPORT_SYMBOL(__clk_get); - -void __clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(__clk_put); diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h index 1dc0971..afc60ba 100644 --- a/arch/arm/mach-shmobile/common.h +++ b/arch/arm/mach-shmobile/common.h @@ -21,7 +21,6 @@ extern void shmobile_smp_scu_cpu_die(unsigned int cpu); extern int shmobile_smp_scu_cpu_kill(unsigned int cpu); struct clk; extern int shmobile_clk_init(void); -extern void shmobile_handle_irq_intc(struct pt_regs *); extern struct platform_suspend_ops shmobile_suspend_ops; #ifdef CONFIG_SUSPEND diff --git a/arch/arm/mach-shmobile/entry-intc.S b/arch/arm/mach-shmobile/entry-intc.S deleted file mode 100644 index 1a1c00c..0000000 --- a/arch/arm/mach-shmobile/entry-intc.S +++ /dev/null @@ -1,54 +0,0 @@ -/* - * ARM Interrupt demux handler using INTC - * - * Copyright (C) 2010 Magnus Damm - * Copyright (C) 2008 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <asm/entry-macro-multi.S> - -#define INTCA_BASE 0xe6980000 -#define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */ -#define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */ -#define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */ -#define INTLVLB_OFFS 0x00000034 /* previous priority level */ - - .macro get_irqnr_preamble, base, tmp - ldr \base, =INTCA_BASE - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - /* The single INTFLGA read access below results in the following: - * - * 1. INTLVLB is updated with old priority value from INTLVLA - * 2. Highest priority interrupt is accepted - * 3. INTLVLA is updated to contain priority of accepted interrupt - * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA - */ - ldr \irqnr, [\base, #INTFLGA_OFFS] - - /* Restore INTLVLA with the value saved in INTLVLB. - * This is required to support interrupt priorities properly. - */ - ldrb \tmp, [\base, #INTLVLB_OFFS] - strb \tmp, [\base, #INTLVLA_OFFS] - - /* Handle invalid vector number case */ - cmp \irqnr, #0 - beq 1000f - - /* Convert vector to irq number, same as the evt2irq() macro */ - lsr \irqnr, \irqnr, #0x5 - subs \irqnr, \irqnr, #16 - -1000: - .endm - - .macro test_for_ipi, irqnr, irqstat, base, tmp - .endm - - arch_irq_handler shmobile_handle_irq_intc diff --git a/arch/arm/mach-shmobile/include/mach/clkdev.h b/arch/arm/mach-shmobile/include/mach/clkdev.h deleted file mode 100644 index 36d0163..0000000 --- a/arch/arm/mach-shmobile/include/mach/clkdev.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_MACH_CLKDEV_H -#define __ASM_MACH_CLKDEV_H - -int __clk_get(struct clk *clk); -void __clk_put(struct clk *clk); - -#endif /* __ASM_MACH_CLKDEV_H */ diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt deleted file mode 100644 index 9f134df..0000000 --- a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt +++ /dev/null @@ -1,93 +0,0 @@ -LIST "partner-jet-setup.txt" -LIST "(C) Copyright 2010 Renesas Solutions Corp" -LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>" - -LIST "RWT Setting" -EW 0xE6020004, 0xA500 -EW 0xE6030004, 0xA500 - -LIST "GPIO Setting" -EB 0xE6051013, 0xA2 - -LIST "CPG" -ED 0xE61500C0, 0x00000002 - -WAIT 1, 0xFE40009C - -LIST "FRQCR" -ED 0xE6150000, 0x2D1305C3 -ED 0xE61500E0, 0x9E40358E -ED 0xE6150004, 0x80331050 - -WAIT 1, 0xFE40009C - -ED 0xE61500E4, 0x00002000 - -WAIT 1, 0xFE40009C - -LIST "PLL" -ED 0xE6150028, 0x00004000 - -WAIT 1, 0xFE40009C - -ED 0xE615002C, 0x93000040 - -WAIT 1, 0xFE40009C - -LIST "SUB/USBClk" -ED 0xE6150080, 0x00000180 - -LIST "BSC" -ED 0xFEC10000, 0x00E0001B - -LIST "SBSC1" -ED 0xFE400354, 0x01AD8000 -ED 0xFE400354, 0x01AD8001 - -WAIT 5, 0xFE40009C - -ED 0xFE400008, 0xBCC90151 -ED 0xFE400040, 0x41774113 -ED 0xFE400044, 0x2712E229 -ED 0xFE400048, 0x20C18505 -ED 0xFE40004C, 0x00110209 -ED 0xFE400010, 0x00000087 - -WAIT 30, 0xFE40009C - -ED 0xFE400084, 0x0000003F -EB 0xFE500000, 0x00 - -WAIT 5, 0xFE40009C - -ED 0xFE400084, 0x0000FF0A -EB 0xFE500000, 0x00 - -WAIT 1, 0xFE40009C - -ED 0xFE400084, 0x00002201 -EB 0xFE500000, 0x00 -ED 0xFE400084, 0x00000302 -EB 0xFE500000, 0x00 -EB 0xFE5C0000, 0x00 -ED 0xFE400008, 0xBCC90159 -ED 0xFE40008C, 0x88800004 -ED 0xFE400094, 0x00000004 -ED 0xFE400028, 0xA55A0032 -ED 0xFE40002C, 0xA55A000C -ED 0xFE400020, 0xA55A2048 -ED 0xFE400008, 0xBCC90959 - -LIST "Change CPGA setting" -ED 0xE61500E0, 0x9E40352E -ED 0xE6150004, 0x80331050 - -WAIT 1, 0xFE40009C - -ED 0xFE400354, 0x01AD8002 - -LIST "SCIF0 - Serial port for earlyprintk" -EB 0xE6053098, 0xe1 -EW 0xE6C40000, 0x0000 -EB 0xE6C40004, 0x19 -EW 0xE6C40008, 0x0030 diff --git a/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h b/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h deleted file mode 100644 index 15d3a9e..0000000 --- a/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef MMC_MACKEREL_H -#define MMC_MACKEREL_H - -#define PORT0CR (void __iomem *)0xe6051000 -#define PORT1CR (void __iomem *)0xe6051001 -#define PORT2CR (void __iomem *)0xe6051002 -#define PORT159CR (void __iomem *)0xe605009f - -#define PORTR031_000DR (void __iomem *)0xe6055000 -#define PORTL159_128DR (void __iomem *)0xe6054010 - -static inline void mmc_init_progress(void) -{ - /* Initialise LEDS0-3 - * registers: PORT0CR-PORT2CR,PORT159CR (LED0-LED3 Control) - * value: 0x10 - enable output - */ - __raw_writeb(0x10, PORT0CR); - __raw_writeb(0x10, PORT1CR); - __raw_writeb(0x10, PORT2CR); - __raw_writeb(0x10, PORT159CR); -} - -static inline void mmc_update_progress(int n) -{ - unsigned a = 0, b = 0; - - if (n < 3) - a = 1 << n; - else - b = 1 << 31; - - __raw_writel((__raw_readl(PORTR031_000DR) & ~0x7) | a, - PORTR031_000DR); - __raw_writel((__raw_readl(PORTL159_128DR) & ~(1 << 31)) | b, - PORTL159_128DR); -} -#endif /* MMC_MACKEREL_H */ diff --git a/arch/arm/mach-shmobile/include/mach/mmc.h b/arch/arm/mach-shmobile/include/mach/mmc.h deleted file mode 100644 index e979b8f..0000000 --- a/arch/arm/mach-shmobile/include/mach/mmc.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef MMC_H -#define MMC_H - -/************************************************** - * - * board specific settings - * - **************************************************/ - -#ifdef CONFIG_MACH_MACKEREL -#include "mach/mmc-mackerel.h" -#else -#error "unsupported board." -#endif - -#endif /* MMC_H */ diff --git a/arch/arm/mach-shmobile/include/mach/sdhi-sh7372.h b/arch/arm/mach-shmobile/include/mach/sdhi-sh7372.h deleted file mode 100644 index 4a81b01..0000000 --- a/arch/arm/mach-shmobile/include/mach/sdhi-sh7372.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef SDHI_SH7372_H -#define SDHI_SH7372_H - -#define SDGENCNTA 0xfe40009c - -/* The countdown of SDGENCNTA is controlled by - * ZB3D2CLK which runs at 149.5MHz. - * That is 149.5ticks/us. Approximate this as 150ticks/us. - */ -static void udelay(int us) -{ - __raw_writel(us * 150, SDGENCNTA); - while(__raw_readl(SDGENCNTA)) ; -} - -static void msleep(int ms) -{ - udelay(ms * 1000); -} - -#endif diff --git a/arch/arm/mach-shmobile/include/mach/sdhi.h b/arch/arm/mach-shmobile/include/mach/sdhi.h deleted file mode 100644 index 0ec9e69..0000000 --- a/arch/arm/mach-shmobile/include/mach/sdhi.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef SDHI_H -#define SDHI_H - -/************************************************** - * - * CPU specific settings - * - **************************************************/ - -#ifdef CONFIG_ARCH_SH7372 -#include "mach/sdhi-sh7372.h" -#else -#error "unsupported CPU." -#endif - -#endif /* SDHI_H */ diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h deleted file mode 100644 index 540eaff..0000000 --- a/arch/arm/mach-shmobile/include/mach/system.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include <asm/system_misc.h> - -static inline void arch_reset(char mode, const char *cmd) -{ - soft_restart(0); -} - -#endif diff --git a/arch/arm/mach-shmobile/include/mach/uncompress.h b/arch/arm/mach-shmobile/include/mach/uncompress.h deleted file mode 100644 index f1aee567..0000000 --- a/arch/arm/mach-shmobile/include/mach/uncompress.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __ASM_MACH_UNCOMPRESS_H -#define __ASM_MACH_UNCOMPRESS_H - -/* - * This does not append a newline - */ -static void putc(int c) -{ -} - -static inline void flush(void) -{ -} - -static void arch_decomp_setup(void) -{ -} - -#endif /* __ASM_MACH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h index 727cc78..175ee05 100644 --- a/arch/arm/mach-shmobile/include/mach/zboot.h +++ b/arch/arm/mach-shmobile/include/mach/zboot.h @@ -9,10 +9,7 @@ * **************************************************/ -#ifdef CONFIG_MACH_MACKEREL -#define MEMORY_START 0x40000000 -#include "mach/head-mackerel.txt" -#elif defined(CONFIG_MACH_KZM9G) || defined(CONFIG_MACH_KZM9G_REFERENCE) +#ifdef CONFIG_MACH_KZM9G #define MEMORY_START 0x43000000 #include "mach/head-kzm9g.txt" #else diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c deleted file mode 100644 index 1ccf49c..0000000 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ /dev/null @@ -1,672 +0,0 @@ -/* - * sh7372 processor support - INTC hardware block - * - * Copyright (C) 2010 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/module.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include "intc.h" -#include "irqs.h" - -enum { - UNUSED_INTCA = 0, - - /* interrupt sources INTCA */ - DIRC, - CRYPT_STD, - IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, - AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX, - MFI_MFIM, MFI_MFIS, - BBIF1, BBIF2, - USBHSDMAC0_USHDMI, - _3DG_SGX540, - CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, - KEYSC_KEY, - SCIFA0, SCIFA1, SCIFA2, SCIFA3, - MSIOF2, MSIOF1, - SCIFA4, SCIFA5, SCIFB, - FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, - SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3, - SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2, - IRREM, - IRDA, - TPU0, - TTI20, - DDM, - SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3, - RWDT0, - DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3, - DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR, - DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, - DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, - DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, - DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, - SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, - HDMI, - SPU2_SPU0, SPU2_SPU1, - FSI, FMSI, - MIPI_HSI, - IPMMU_IPMMUD, - CEC_1, CEC_2, - AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ, - MFIS2, - CPORTR2S, - CMT14, CMT15, - MMC_MMC_ERR, MMC_MMC_NOR, - IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4, - IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3, - USB0_USB0I1, USB0_USB0I0, - USB1_USB1I1, USB1_USB1I0, - USBHSDMAC1_USHDMI, - - /* interrupt groups INTCA */ - DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, - AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2 -}; - -static struct intc_vect intca_vectors[] __initdata = { - INTC_VECT(DIRC, 0x0560), - INTC_VECT(CRYPT_STD, 0x0700), - INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), - INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0), - INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840), - INTC_VECT(AP_ARM_COMMRX, 0x0860), - INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), - INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), - INTC_VECT(USBHSDMAC0_USHDMI, 0x0a00), - INTC_VECT(_3DG_SGX540, 0x0a60), - INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), - INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), - INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0), - INTC_VECT(KEYSC_KEY, 0x0be0), - INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20), - INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60), - INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00), - INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40), - INTC_VECT(SCIFB, 0x0d60), - INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), - INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), - INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20), - INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60), - INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0), - INTC_VECT(SDHI1_SDHI1I2, 0x0ec0), - INTC_VECT(IRREM, 0x0f60), - INTC_VECT(IRDA, 0x0480), - INTC_VECT(TPU0, 0x04a0), - INTC_VECT(TTI20, 0x1100), - INTC_VECT(DDM, 0x1140), - INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220), - INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260), - INTC_VECT(RWDT0, 0x1280), - INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020), - INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060), - INTC_VECT(DMAC1_2_DEI4, 0x2080), INTC_VECT(DMAC1_2_DEI5, 0x20a0), - INTC_VECT(DMAC1_2_DADERR, 0x20c0), - INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), - INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), - INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), - INTC_VECT(DMAC2_2_DADERR, 0x21c0), - INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220), - INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), - INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), - INTC_VECT(DMAC3_2_DADERR, 0x22c0), - INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1320), - INTC_VECT(SHWYSTAT_COM, 0x1340), - INTC_VECT(HDMI, 0x17e0), - INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820), - INTC_VECT(FSI, 0x1840), - INTC_VECT(FMSI, 0x1860), - INTC_VECT(MIPI_HSI, 0x18e0), - INTC_VECT(IPMMU_IPMMUD, 0x1920), - INTC_VECT(CEC_1, 0x1940), INTC_VECT(CEC_2, 0x1960), - INTC_VECT(AP_ARM_CTIIRQ, 0x1980), - INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0), - INTC_VECT(AP_ARM_DMAIRQ, 0x19c0), - INTC_VECT(AP_ARM_DMASIRQ, 0x19e0), - INTC_VECT(MFIS2, 0x1a00), - INTC_VECT(CPORTR2S, 0x1a20), - INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60), - INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0), - INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20), - INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60), - INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0), - INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0), - INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0), - INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0), - INTC_VECT(USBHSDMAC1_USHDMI, 0x1d00), -}; - -static struct intc_group intca_groups[] __initdata = { - INTC_GROUP(DMAC1_1, DMAC1_1_DEI0, - DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3), - INTC_GROUP(DMAC1_2, DMAC1_2_DEI4, - DMAC1_2_DEI5, DMAC1_2_DADERR), - INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, - DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), - INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, - DMAC2_2_DEI5, DMAC2_2_DADERR), - INTC_GROUP(DMAC3_1, DMAC3_1_DEI0, - DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), - INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, - DMAC3_2_DEI5, DMAC3_2_DADERR), - INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX), - INTC_GROUP(AP_ARM2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, - AP_ARM_DMAIRQ, AP_ARM_DMASIRQ), - INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), - INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, - FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), - INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), - INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1, - SDHI0_SDHI0I2, SDHI0_SDHI0I3), - INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1, - SDHI1_SDHI1I2), - INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1, - SDHI2_SDHI2I2, SDHI2_SDHI2I3), - INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), -}; - -static struct intc_mask_reg intca_mask_registers[] __initdata = { - { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ - { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, - AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, - { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ - { 0, CRYPT_STD, DIRC, 0, - DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } }, - { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ - { 0, 0, 0, 0, - BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, - { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */ - { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, - DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, - { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */ - { DDM, 0, 0, 0, - 0, 0, 0, 0 } }, - { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ - { KEYSC_KEY, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4, - SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, - { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ - { SCIFB, SCIFA5, SCIFA4, MSIOF1, - 0, 0, MSIOF2, 0 } }, - { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ - { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0, - FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, - { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ - { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0, - TTI20, USBHSDMAC0_USHDMI, 0, 0 } }, - { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ - { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, - CMT2, 0, 0, _3DG_SGX540 } }, - { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */ - { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, - 0, 0, 0, 0 } }, - { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */ - { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1, - 0, 0, IRREM, 0 } }, - { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */ - { 0, 0, TPU0, 0, - 0, 0, 0, 0 } }, - { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ - { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0, - 0, CMT3, 0, RWDT0 } }, - { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */ - { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, - 0, 0, 0, 0 } }, - { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */ - { 0, 0, 0, 0, - 0, 0, 0, HDMI } }, - { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */ - { SPU2_SPU0, SPU2_SPU1, FSI, FMSI, - 0, 0, 0, MIPI_HSI } }, - { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */ - { 0, IPMMU_IPMMUD, CEC_1, CEC_2, - AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, - AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } }, - { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ - { MFIS2, CPORTR2S, CMT14, CMT15, - 0, 0, MMC_MMC_ERR, MMC_MMC_NOR } }, - { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */ - { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4, - IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } }, - { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */ - { 0, 0, 0, 0, - USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } }, - { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */ - { USBHSDMAC1_USHDMI, 0, 0, 0, - 0, 0, 0, 0 } }, -}; - -static struct intc_prio_reg intca_prio_registers[] __initdata = { - { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } }, - { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, - { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD, - CMT1_CMT11, AP_ARM1 } }, - { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, - CMT1_CMT12, 0 } }, - { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFI_MFIS, - MFI_MFIM, 0 } }, - { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC1_2, - _3DG_SGX540, CMT1_CMT10 } }, - { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, - SCIFA2, SCIFA3 } }, - { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC0_USHDMI, - FLCTL, SDHI0 } }, - { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, - 0/* MSU */, IIC1 } }, - { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, - 0/* MSUG */, TTI20 } }, - { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } }, - { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } }, - { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } }, - { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } }, - { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, - { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } }, - { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } }, - { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, - { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } }, - { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0, - CEC_1, CEC_2 } }, - { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, - { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, - CMT14, CMT15 } }, - { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0, - MMC_MMC_ERR, MMC_MMC_NOR } }, - { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4, - IIC4_WAITI4, IIC4_DTEI4 } }, - { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3, - IIC3_WAITI3, IIC3_DTEI3 } }, - { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/, - 0/*TXI*/, 0/*TEI*/} }, - { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0, - USB1_USB1I1, USB1_USB1I0 } }, - { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } }, -}; - -static DECLARE_INTC_DESC(intca_desc, "sh7372-intca", - intca_vectors, intca_groups, - intca_mask_registers, intca_prio_registers, - NULL); - -INTC_IRQ_PINS_16(intca_irq_pins_lo, 0xe6900000, - INTC_VECT, "sh7372-intca-irq-lo"); - -INTC_IRQ_PINS_16H(intca_irq_pins_hi, 0xe6900000, - INTC_VECT, "sh7372-intca-irq-hi"); - -enum { - UNUSED_INTCS = 0, - ENABLED_INTCS, - - /* interrupt sources INTCS */ - - /* IRQ0S - IRQ31S */ - VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3, - RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3, - CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2, - /* MFI */ - /* BBIF2 */ - VPU, - TSIF1, - /* 3DG */ - _2DDMAC, - IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, - IPMMU_IPMMUR, IPMMU_IPMMUR2, - RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR, - /* KEYSC */ - /* TTI20 */ - MSIOF, - IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0, - TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, - CMT0, - TSIF0, - /* CMT2 */ - LMB, - CTI, - /* RWDT0 */ - ICB, - JPU_JPEG, - LCDC, - LCRC, - RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3, - RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, - ISP, - LCDC1, - CSIRX, - DSITX_DSITX0, - DSITX_DSITX1, - /* SPU2 */ - /* FSI */ - /* FMSI */ - /* HDMI */ - TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, - CMT4, - DSITX1_DSITX1_0, - DSITX1_DSITX1_1, - MFIS2_INTCS, /* Priority always enabled using ENABLED_INTCS */ - CPORTS2R, - /* CEC */ - JPU6E, - - /* interrupt groups INTCS */ - RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2, - RTDMAC2_1, RTDMAC2_2, TMU1, DSITX, -}; - -static struct intc_vect intcs_vectors[] = { - /* IRQ0S - IRQ31S */ - INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720), - INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760), - INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820), - INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860), - INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0), - INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0), - /* MFI */ - /* BBIF2 */ - INTCS_VECT(VPU, 0x980), - INTCS_VECT(TSIF1, 0x9a0), - /* 3DG */ - INTCS_VECT(_2DDMAC, 0xa00), - INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0), - INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0), - INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20), - INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0), - INTCS_VECT(RTDMAC_2_DADERR, 0xbc0), - /* KEYSC */ - /* TTI20 */ - INTCS_VECT(MSIOF, 0x0d20), - INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20), - INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60), - INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0), - INTCS_VECT(TMU_TUNI2, 0xec0), - INTCS_VECT(CMT0, 0xf00), - INTCS_VECT(TSIF0, 0xf20), - /* CMT2 */ - INTCS_VECT(LMB, 0xf60), - INTCS_VECT(CTI, 0x400), - /* RWDT0 */ - INTCS_VECT(ICB, 0x480), - INTCS_VECT(JPU_JPEG, 0x560), - INTCS_VECT(LCDC, 0x580), - INTCS_VECT(LCRC, 0x5a0), - INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320), - INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360), - INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0), - INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0), - INTCS_VECT(ISP, 0x1720), - INTCS_VECT(LCDC1, 0x1780), - INTCS_VECT(CSIRX, 0x17a0), - INTCS_VECT(DSITX_DSITX0, 0x17c0), - INTCS_VECT(DSITX_DSITX1, 0x17e0), - /* SPU2 */ - /* FSI */ - /* FMSI */ - /* HDMI */ - INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920), - INTCS_VECT(TMU1_TUNI2, 0x1940), - INTCS_VECT(CMT4, 0x1980), - INTCS_VECT(DSITX1_DSITX1_0, 0x19a0), - INTCS_VECT(DSITX1_DSITX1_1, 0x19c0), - INTCS_VECT(MFIS2_INTCS, 0x1a00), - INTCS_VECT(CPORTS2R, 0x1a20), - /* CEC */ - INTCS_VECT(JPU6E, 0x1a80), -}; - -static struct intc_group intcs_groups[] __initdata = { - INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1, - RTDMAC_1_DEI2, RTDMAC_1_DEI3), - INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR), - INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3), - INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2), - INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0), - INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2), - INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2), - INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, - RTDMAC2_1_DEI2, RTDMAC2_1_DEI3), - INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, - RTDMAC2_2_DEI5, RTDMAC2_2_DADERR), - INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0), - INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1), -}; - -static struct intc_mask_reg intcs_mask_registers[] = { - { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */ - { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU, - VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } }, - { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */ - { 0, 0, 0, VPU, - 0, 0, 0, 0 } }, - { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */ - { 0, 0, 0, _2DDMAC, - 0, 0, 0, ICB } }, - { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */ - { 0, 0, 0, CTI, - JPU_JPEG, 0, LCRC, LCDC } }, - { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */ - { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4, - RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } }, - { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ - { 0, 0, MSIOF, 0, - 0, 0, 0, 0 } }, - { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ - { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0, - 0, 0, 0, 0 } }, - { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */ - { 0, 0, 0, CMT0, - IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } }, - { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */ - { 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR, - 0, 0, 0, 0 } }, - { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */ - { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0, - 0, TSIF1, LMB, TSIF0 } }, - { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */ - { 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4, - RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } }, - { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */ - { 0, ISP, 0, 0, - LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } }, - { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */ - { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, - CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } }, - { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */ - { MFIS2_INTCS, CPORTS2R, 0, 0, - JPU6E, 0, 0, 0 } }, -}; - -/* Priority is needed for INTCA to receive the INTCS interrupt */ -static struct intc_prio_reg intcs_prio_registers[] = { - { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } }, - { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } }, - { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } }, - { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } }, - { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1, - TMU_TUNI2, TSIF1 } }, - { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } }, - { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } }, - { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } }, - { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } }, - { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } }, - { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } }, - { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } }, - { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } }, - { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } }, - { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } }, - { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0, - DSITX1_DSITX1_1, 0 } }, - { 0xffd50038, 0, 16, 4, /* IPROS3 */ { ENABLED_INTCS, CPORTS2R, - 0, 0 } }, - { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } }, -}; - -static struct resource intcs_resources[] __initdata = { - [0] = { - .start = 0xffd20000, - .end = 0xffd201ff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0xffd50000, - .end = 0xffd501ff, - .flags = IORESOURCE_MEM, - } -}; - -static struct intc_desc intcs_desc __initdata = { - .name = "sh7372-intcs", - .force_enable = ENABLED_INTCS, - .skip_syscore_suspend = true, - .resource = intcs_resources, - .num_resources = ARRAY_SIZE(intcs_resources), - .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, - intcs_prio_registers, NULL, NULL), -}; - -static void intcs_demux(unsigned int irq, struct irq_desc *desc) -{ - void __iomem *reg = (void *)irq_get_handler_data(irq); - unsigned int evtcodeas = ioread32(reg); - - generic_handle_irq(intcs_evt2irq(evtcodeas)); -} - -static void __iomem *intcs_ffd2; -static void __iomem *intcs_ffd5; - -void __init sh7372_init_irq(void) -{ - void __iomem *intevtsa; - int n; - - intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE); - intevtsa = intcs_ffd2 + 0x100; - intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE); - - register_intc_controller(&intca_desc); - register_intc_controller(&intca_irq_pins_lo_desc); - register_intc_controller(&intca_irq_pins_hi_desc); - register_intc_controller(&intcs_desc); - - /* setup dummy cascade chip for INTCS */ - n = evt2irq(0xf80); - irq_alloc_desc_at(n, numa_node_id()); - irq_set_chip_and_handler_name(n, &dummy_irq_chip, - handle_level_irq, "level"); - set_irq_flags(n, IRQF_VALID); /* yuck */ - - /* demux using INTEVTSA */ - irq_set_handler_data(n, (void *)intevtsa); - irq_set_chained_handler(n, intcs_demux); - - /* unmask INTCS in INTAMASK */ - iowrite16(0, intcs_ffd2 + 0x104); -} - -static unsigned short ffd2[0x200]; -static unsigned short ffd5[0x100]; - -void sh7372_intcs_suspend(void) -{ - int k; - - for (k = 0x00; k <= 0x30; k += 4) - ffd2[k] = __raw_readw(intcs_ffd2 + k); - - for (k = 0x80; k <= 0xb0; k += 4) - ffd2[k] = __raw_readb(intcs_ffd2 + k); - - for (k = 0x180; k <= 0x188; k += 4) - ffd2[k] = __raw_readb(intcs_ffd2 + k); - - for (k = 0x00; k <= 0x3c; k += 4) - ffd5[k] = __raw_readw(intcs_ffd5 + k); - - for (k = 0x80; k <= 0x9c; k += 4) - ffd5[k] = __raw_readb(intcs_ffd5 + k); -} - -void sh7372_intcs_resume(void) -{ - int k; - - for (k = 0x00; k <= 0x30; k += 4) - __raw_writew(ffd2[k], intcs_ffd2 + k); - - for (k = 0x80; k <= 0xb0; k += 4) - __raw_writeb(ffd2[k], intcs_ffd2 + k); - - for (k = 0x180; k <= 0x188; k += 4) - __raw_writeb(ffd2[k], intcs_ffd2 + k); - - for (k = 0x00; k <= 0x3c; k += 4) - __raw_writew(ffd5[k], intcs_ffd5 + k); - - for (k = 0x80; k <= 0x9c; k += 4) - __raw_writeb(ffd5[k], intcs_ffd5 + k); -} - -#define E694_BASE IOMEM(0xe6940000) -#define E695_BASE IOMEM(0xe6950000) - -static unsigned short e694[0x200]; -static unsigned short e695[0x200]; - -void sh7372_intca_suspend(void) -{ - int k; - - for (k = 0x00; k <= 0x38; k += 4) - e694[k] = __raw_readw(E694_BASE + k); - - for (k = 0x80; k <= 0xb4; k += 4) - e694[k] = __raw_readb(E694_BASE + k); - - for (k = 0x180; k <= 0x1b4; k += 4) - e694[k] = __raw_readb(E694_BASE + k); - - for (k = 0x00; k <= 0x50; k += 4) - e695[k] = __raw_readw(E695_BASE + k); - - for (k = 0x80; k <= 0xa8; k += 4) - e695[k] = __raw_readb(E695_BASE + k); - - for (k = 0x180; k <= 0x1a8; k += 4) - e695[k] = __raw_readb(E695_BASE + k); -} - -void sh7372_intca_resume(void) -{ - int k; - - for (k = 0x00; k <= 0x38; k += 4) - __raw_writew(e694[k], E694_BASE + k); - - for (k = 0x80; k <= 0xb4; k += 4) - __raw_writeb(e694[k], E694_BASE + k); - - for (k = 0x180; k <= 0x1b4; k += 4) - __raw_writeb(e694[k], E694_BASE + k); - - for (k = 0x00; k <= 0x50; k += 4) - __raw_writew(e695[k], E695_BASE + k); - - for (k = 0x80; k <= 0xa8; k += 4) - __raw_writeb(e695[k], E695_BASE + k); - - for (k = 0x180; k <= 0x1a8; k += 4) - __raw_writeb(e695[k], E695_BASE + k); -} diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c deleted file mode 100644 index 9f19052..0000000 --- a/arch/arm/mach-shmobile/pm-sh7372.c +++ /dev/null @@ -1,549 +0,0 @@ -/* - * sh7372 Power management support - * - * Copyright (C) 2011 Magnus Damm - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#include <linux/pm.h> -#include <linux/suspend.h> -#include <linux/cpuidle.h> -#include <linux/module.h> -#include <linux/list.h> -#include <linux/err.h> -#include <linux/slab.h> -#include <linux/pm_clock.h> -#include <linux/platform_device.h> -#include <linux/delay.h> -#include <linux/irq.h> -#include <linux/bitrev.h> -#include <linux/console.h> - -#include <asm/cpuidle.h> -#include <asm/io.h> -#include <asm/tlbflush.h> -#include <asm/suspend.h> - -#include "common.h" -#include "pm-rmobile.h" -#include "sh7372.h" - -/* DBG */ -#define DBGREG1 IOMEM(0xe6100020) -#define DBGREG9 IOMEM(0xe6100040) - -/* CPGA */ -#define SYSTBCR IOMEM(0xe6150024) -#define MSTPSR0 IOMEM(0xe6150030) -#define MSTPSR1 IOMEM(0xe6150038) -#define MSTPSR2 IOMEM(0xe6150040) -#define MSTPSR3 IOMEM(0xe6150048) -#define MSTPSR4 IOMEM(0xe615004c) -#define PLLC01STPCR IOMEM(0xe61500c8) - -/* SYSC */ -#define SYSC_BASE IOMEM(0xe6180000) - -#define SBAR IOMEM(0xe6180020) -#define WUPRMSK IOMEM(0xe6180028) -#define WUPSMSK IOMEM(0xe618002c) -#define WUPSMSK2 IOMEM(0xe6180048) -#define WUPSFAC IOMEM(0xe6180098) -#define IRQCR IOMEM(0xe618022c) -#define IRQCR2 IOMEM(0xe6180238) -#define IRQCR3 IOMEM(0xe6180244) -#define IRQCR4 IOMEM(0xe6180248) -#define PDNSEL IOMEM(0xe6180254) - -/* INTC */ -#define ICR1A IOMEM(0xe6900000) -#define ICR2A IOMEM(0xe6900004) -#define ICR3A IOMEM(0xe6900008) -#define ICR4A IOMEM(0xe690000c) -#define INTMSK00A IOMEM(0xe6900040) -#define INTMSK10A IOMEM(0xe6900044) -#define INTMSK20A IOMEM(0xe6900048) -#define INTMSK30A IOMEM(0xe690004c) - -/* MFIS */ -/* FIXME: pointing where? */ -#define SMFRAM 0xe6a70000 - -/* AP-System Core */ -#define APARMBAREA IOMEM(0xe6f10020) - -#ifdef CONFIG_PM - -#define PM_DOMAIN_ON_OFF_LATENCY_NS 250000 - -static int sh7372_a4r_pd_suspend(void) -{ - sh7372_intcs_suspend(); - __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */ - return 0; -} - -static bool a4s_suspend_ready; - -static int sh7372_a4s_pd_suspend(void) -{ - /* - * The A4S domain contains the CPU core and therefore it should - * only be turned off if the CPU is not in use. This may happen - * during system suspend, when SYSC is going to be used for generating - * resume signals and a4s_suspend_ready is set to let - * sh7372_enter_suspend() know that it can turn A4S off. - */ - a4s_suspend_ready = true; - return -EBUSY; -} - -static void sh7372_a4s_pd_resume(void) -{ - a4s_suspend_ready = false; -} - -static int sh7372_a3sp_pd_suspend(void) -{ - /* - * Serial consoles make use of SCIF hardware located in A3SP, - * keep such power domain on if "no_console_suspend" is set. - */ - return console_suspend_enabled ? 0 : -EBUSY; -} - -static struct rmobile_pm_domain sh7372_pm_domains[] = { - { - .genpd.name = "A4LC", - .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .base = SYSC_BASE, - .bit_shift = 1, - }, - { - .genpd.name = "A4MP", - .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .base = SYSC_BASE, - .bit_shift = 2, - }, - { - .genpd.name = "D4", - .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .base = SYSC_BASE, - .bit_shift = 3, - }, - { - .genpd.name = "A4R", - .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .base = SYSC_BASE, - .bit_shift = 5, - .suspend = sh7372_a4r_pd_suspend, - .resume = sh7372_intcs_resume, - }, - { - .genpd.name = "A3RV", - .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .base = SYSC_BASE, - .bit_shift = 6, - }, - { - .genpd.name = "A3RI", - .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .base = SYSC_BASE, - .bit_shift = 8, - }, - { - .genpd.name = "A4S", - .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .base = SYSC_BASE, - .bit_shift = 10, - .gov = &pm_domain_always_on_gov, - .no_debug = true, - .suspend = sh7372_a4s_pd_suspend, - .resume = sh7372_a4s_pd_resume, - }, - { - .genpd.name = "A3SP", - .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .base = SYSC_BASE, - .bit_shift = 11, - .gov = &pm_domain_always_on_gov, - .no_debug = true, - .suspend = sh7372_a3sp_pd_suspend, - }, - { - .genpd.name = "A3SG", - .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS, - .base = SYSC_BASE, - .bit_shift = 13, - }, -}; - -void __init sh7372_init_pm_domains(void) -{ - rmobile_init_domains(sh7372_pm_domains, ARRAY_SIZE(sh7372_pm_domains)); - pm_genpd_add_subdomain_names("A4LC", "A3RV"); - pm_genpd_add_subdomain_names("A4R", "A4LC"); - pm_genpd_add_subdomain_names("A4S", "A3SG"); - pm_genpd_add_subdomain_names("A4S", "A3SP"); -} - -#endif /* CONFIG_PM */ - -#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) -static void sh7372_set_reset_vector(unsigned long address) -{ - /* set reset vector, translate 4k */ - __raw_writel(address, SBAR); - __raw_writel(0, APARMBAREA); -} - -static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode) -{ - if (pllc0_on) - __raw_writel(0, PLLC01STPCR); - else - __raw_writel(1 << 28, PLLC01STPCR); - - __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */ - cpu_suspend(sleep_mode, sh7372_do_idle_sysc); - __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */ - - /* disable reset vector translation */ - __raw_writel(0, SBAR); -} - -static int sh7372_sysc_valid(unsigned long *mskp, unsigned long *msk2p) -{ - unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4; - unsigned long msk, msk2; - - /* check active clocks to determine potential wakeup sources */ - - mstpsr0 = __raw_readl(MSTPSR0); - if ((mstpsr0 & 0x00000003) != 0x00000003) { - pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0); - return 0; - } - - mstpsr1 = __raw_readl(MSTPSR1); - if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) { - pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1); - return 0; - } - - mstpsr2 = __raw_readl(MSTPSR2); - if ((mstpsr2 & 0x000741ff) != 0x000741ff) { - pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2); - return 0; - } - - mstpsr3 = __raw_readl(MSTPSR3); - if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) { - pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3); - return 0; - } - - mstpsr4 = __raw_readl(MSTPSR4); - if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) { - pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4); - return 0; - } - - msk = 0; - msk2 = 0; - - /* make bitmaps of limited number of wakeup sources */ - - if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */ - msk |= 1 << 31; - - if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */ - msk |= 1 << 21; - - if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */ - msk |= 1 << 2; - - if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */ - msk |= 1 << 1; - - if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */ - msk |= 1 << 1; - - if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */ - msk |= 1 << 1; - - if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */ - msk2 |= 1 << 17; - - *mskp = msk; - *msk2p = msk2; - - return 1; -} - -static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p) -{ - u16 tmp, irqcr1, irqcr2; - int k; - - irqcr1 = 0; - irqcr2 = 0; - - /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */ - for (k = 0; k <= 7; k++) { - tmp = (icr >> ((7 - k) * 4)) & 0xf; - irqcr1 |= (tmp & 0x03) << (k * 2); - irqcr2 |= (tmp >> 2) << (k * 2); - } - - *irqcr1p = irqcr1; - *irqcr2p = irqcr2; -} - -static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2) -{ - u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high; - unsigned long tmp; - - /* read IRQ0A -> IRQ15A mask */ - tmp = bitrev8(__raw_readb(INTMSK00A)); - tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8; - - /* setup WUPSMSK from clocks and external IRQ mask */ - msk = (~msk & 0xc030000f) | (tmp << 4); - __raw_writel(msk, WUPSMSK); - - /* propage level/edge trigger for external IRQ 0->15 */ - sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low); - sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high); - __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR); - __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2); - - /* read IRQ16A -> IRQ31A mask */ - tmp = bitrev8(__raw_readb(INTMSK20A)); - tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8; - - /* setup WUPSMSK2 from clocks and external IRQ mask */ - msk2 = (~msk2 & 0x00030000) | tmp; - __raw_writel(msk2, WUPSMSK2); - - /* propage level/edge trigger for external IRQ 16->31 */ - sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low); - sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high); - __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3); - __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4); -} - -static void sh7372_enter_a3sm_common(int pllc0_on) -{ - /* use INTCA together with SYSC for wakeup */ - sh7372_setup_sysc(1 << 0, 0); - sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc)); - sh7372_enter_sysc(pllc0_on, 1 << 12); -} - -static void sh7372_enter_a4s_common(int pllc0_on) -{ - sh7372_intca_suspend(); - sh7372_set_reset_vector(SMFRAM); - sh7372_enter_sysc(pllc0_on, 1 << 10); - sh7372_intca_resume(); -} - -static void sh7372_pm_setup_smfram(void) -{ - /* pass physical address of cpu_resume() to assembly resume code */ - sh7372_cpu_resume = virt_to_phys(cpu_resume); - - memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100); -} -#else -static inline void sh7372_pm_setup_smfram(void) {} -#endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */ - -#ifdef CONFIG_CPU_IDLE -static int sh7372_do_idle_core_standby(unsigned long unused) -{ - cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */ - return 0; -} - -static int sh7372_enter_core_standby(struct cpuidle_device *dev, - struct cpuidle_driver *drv, int index) -{ - sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc)); - - /* enter sleep mode with SYSTBCR to 0x10 */ - __raw_writel(0x10, SYSTBCR); - cpu_suspend(0, sh7372_do_idle_core_standby); - __raw_writel(0, SYSTBCR); - - /* disable reset vector translation */ - __raw_writel(0, SBAR); - - return 1; -} - -static int sh7372_enter_a3sm_pll_on(struct cpuidle_device *dev, - struct cpuidle_driver *drv, int index) -{ - sh7372_enter_a3sm_common(1); - return 2; -} - -static int sh7372_enter_a3sm_pll_off(struct cpuidle_device *dev, - struct cpuidle_driver *drv, int index) -{ - sh7372_enter_a3sm_common(0); - return 3; -} - -static int sh7372_enter_a4s(struct cpuidle_device *dev, - struct cpuidle_driver *drv, int index) -{ - unsigned long msk, msk2; - - if (!sh7372_sysc_valid(&msk, &msk2)) - return sh7372_enter_a3sm_pll_off(dev, drv, index); - - sh7372_setup_sysc(msk, msk2); - sh7372_enter_a4s_common(0); - return 4; -} - -static struct cpuidle_driver sh7372_cpuidle_driver = { - .name = "sh7372_cpuidle", - .owner = THIS_MODULE, - .state_count = 5, - .safe_state_index = 0, /* C1 */ - .states[0] = ARM_CPUIDLE_WFI_STATE, - .states[1] = { - .name = "C2", - .desc = "Core Standby Mode", - .exit_latency = 10, - .target_residency = 20 + 10, - .enter = sh7372_enter_core_standby, - }, - .states[2] = { - .name = "C3", - .desc = "A3SM PLL ON", - .exit_latency = 20, - .target_residency = 30 + 20, - .enter = sh7372_enter_a3sm_pll_on, - }, - .states[3] = { - .name = "C4", - .desc = "A3SM PLL OFF", - .exit_latency = 120, - .target_residency = 30 + 120, - .enter = sh7372_enter_a3sm_pll_off, - }, - .states[4] = { - .name = "C5", - .desc = "A4S PLL OFF", - .exit_latency = 240, - .target_residency = 30 + 240, - .enter = sh7372_enter_a4s, - .disabled = true, - }, -}; - -static void __init sh7372_cpuidle_init(void) -{ - return cpuidle_register(cpuidle_drv, NULL); -} -#else -static void __init sh7372_cpuidle_init(void) {} -#endif - -#ifdef CONFIG_SUSPEND -static int sh7372_enter_suspend(suspend_state_t suspend_state) -{ - unsigned long msk, msk2; - - /* check active clocks to determine potential wakeup sources */ - if (sh7372_sysc_valid(&msk, &msk2) && a4s_suspend_ready) { - /* convert INTC mask/sense to SYSC mask/sense */ - sh7372_setup_sysc(msk, msk2); - - /* enter A4S sleep with PLLC0 off */ - pr_debug("entering A4S\n"); - sh7372_enter_a4s_common(0); - return 0; - } - - /* default to enter A3SM sleep with PLLC0 off */ - pr_debug("entering A3SM\n"); - sh7372_enter_a3sm_common(0); - return 0; -} - -/** - * sh7372_pm_notifier_fn - SH7372 PM notifier routine. - * @notifier: Unused. - * @pm_event: Event being handled. - * @unused: Unused. - */ -static int sh7372_pm_notifier_fn(struct notifier_block *notifier, - unsigned long pm_event, void *unused) -{ - switch (pm_event) { - case PM_SUSPEND_PREPARE: - /* - * This is necessary, because the A4R domain has to be "on" - * when suspend_device_irqs() and resume_device_irqs() are - * executed during system suspend and resume, respectively, so - * that those functions don't crash while accessing the INTCS. - */ - pm_genpd_name_poweron("A4R"); - break; - case PM_POST_SUSPEND: - pm_genpd_poweroff_unused(); - break; - } - - return NOTIFY_DONE; -} - -static void sh7372_suspend_init(void) -{ - shmobile_suspend_ops.enter = sh7372_enter_suspend; - pm_notifier(sh7372_pm_notifier_fn, 0); -} -#else -static void sh7372_suspend_init(void) {} -#endif - -void __init sh7372_pm_init(void) -{ - /* enable DBG hardware block to kick SYSC */ - __raw_writel(0x0000a500, DBGREG9); - __raw_writel(0x0000a501, DBGREG9); - __raw_writel(0x00000000, DBGREG1); - - /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */ - __raw_writel(0, PDNSEL); - - sh7372_pm_setup_smfram(); - - sh7372_suspend_init(); - sh7372_cpuidle_init(); -} - -void __init sh7372_pm_init_late(void) -{ - shmobile_init_late(); - pm_genpd_name_attach_cpuidle("A4S", 4); -} diff --git a/arch/arm/mach-shmobile/r8a73a4.h b/arch/arm/mach-shmobile/r8a73a4.h deleted file mode 100644 index 70dcd84..0000000 --- a/arch/arm/mach-shmobile/r8a73a4.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __ASM_R8A73A4_H__ -#define __ASM_R8A73A4_H__ - -/* DMA slave IDs */ -enum { - SHDMA_SLAVE_INVALID, - SHDMA_SLAVE_MMCIF0_TX, - SHDMA_SLAVE_MMCIF0_RX, - SHDMA_SLAVE_MMCIF1_TX, - SHDMA_SLAVE_MMCIF1_RX, -}; - -void r8a73a4_add_standard_devices(void); -void r8a73a4_clock_init(void); -void r8a73a4_pinmux_init(void); - -#endif /* __ASM_R8A73A4_H__ */ diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index c276822..446cee6 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -13,280 +13,12 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <linux/irq.h> -#include <linux/kernel.h> -#include <linux/of_platform.h> -#include <linux/platform_data/irq-renesas-irqc.h> -#include <linux/serial_sci.h> -#include <linux/sh_dma.h> -#include <linux/sh_timer.h> + +#include <linux/init.h> #include <asm/mach/arch.h> #include "common.h" -#include "dma-register.h" -#include "irqs.h" -#include "r8a73a4.h" - -static const struct resource pfc_resources[] = { - DEFINE_RES_MEM(0xe6050000, 0x9000), -}; - -void __init r8a73a4_pinmux_init(void) -{ - platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources, - ARRAY_SIZE(pfc_resources)); -} - -#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \ -static struct plat_sci_port scif##index##_platform_data = { \ - .type = scif_type, \ - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ - .scscr = _scscr, \ -}; \ - \ -static struct resource scif##index##_resources[] = { \ - DEFINE_RES_MEM(baseaddr, 0x100), \ - DEFINE_RES_IRQ(irq), \ -} - -#define R8A73A4_SCIFA(index, baseaddr, irq) \ - R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ - index, baseaddr, irq) - -#define R8A73A4_SCIFB(index, baseaddr, irq) \ - R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \ - index, baseaddr, irq) - -R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ -R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ -R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ -R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ -R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ -R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */ - -#define r8a73a4_register_scif(index) \ - platform_device_register_resndata(NULL, "sh-sci", index, \ - scif##index##_resources, \ - ARRAY_SIZE(scif##index##_resources), \ - &scif##index##_platform_data, \ - sizeof(scif##index##_platform_data)) - -static const struct renesas_irqc_config irqc0_data = { - .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ -}; - -static const struct resource irqc0_resources[] = { - DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ - DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ - DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ - DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ - DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ - DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */ - DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */ - DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */ - DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */ - DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */ - DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */ - DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */ - DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */ - DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */ - DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */ - DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */ - DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */ - DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */ - DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */ - DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */ - DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */ - DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */ - DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */ - DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */ - DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */ - DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */ - DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */ - DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */ - DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */ - DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */ - DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */ - DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */ - DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */ -}; - -static const struct renesas_irqc_config irqc1_data = { - .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */ -}; - -static const struct resource irqc1_resources[] = { - DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */ - DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */ - DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */ - DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */ - DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */ - DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */ - DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */ - DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */ - DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */ - DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */ - DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */ - DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */ - DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */ - DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */ - DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */ - DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */ - DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */ - DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */ - DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */ - DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */ - DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */ - DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */ - DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */ - DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */ - DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */ - DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */ - DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */ -}; - -#define r8a73a4_register_irqc(idx) \ - platform_device_register_resndata(NULL, "renesas_irqc", \ - idx, irqc##idx##_resources, \ - ARRAY_SIZE(irqc##idx##_resources), \ - &irqc##idx##_data, \ - sizeof(struct renesas_irqc_config)) - -/* Thermal0 -> Thermal2 */ -static const struct resource thermal0_resources[] = { - DEFINE_RES_MEM(0xe61f0000, 0x14), - DEFINE_RES_MEM(0xe61f0100, 0x38), - DEFINE_RES_MEM(0xe61f0200, 0x38), - DEFINE_RES_MEM(0xe61f0300, 0x38), - DEFINE_RES_IRQ(gic_spi(69)), -}; - -#define r8a73a4_register_thermal() \ - platform_device_register_simple("rcar_thermal", -1, \ - thermal0_resources, \ - ARRAY_SIZE(thermal0_resources)) - -static struct sh_timer_config cmt1_platform_data = { - .channels_mask = 0xff, -}; - -static struct resource cmt1_resources[] = { - DEFINE_RES_MEM(0xe6130000, 0x1004), - DEFINE_RES_IRQ(gic_spi(120)), -}; - -#define r8a73a4_register_cmt(idx) \ - platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \ - idx, cmt##idx##_resources, \ - ARRAY_SIZE(cmt##idx##_resources), \ - &cmt##idx##_platform_data, \ - sizeof(struct sh_timer_config)) - -/* DMA */ -static const struct sh_dmae_slave_config dma_slaves[] = { - { - .slave_id = SHDMA_SLAVE_MMCIF0_TX, - .addr = 0xee200034, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0xd1, - }, { - .slave_id = SHDMA_SLAVE_MMCIF0_RX, - .addr = 0xee200034, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0xd2, - }, { - .slave_id = SHDMA_SLAVE_MMCIF1_TX, - .addr = 0xee220034, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0xe1, - }, { - .slave_id = SHDMA_SLAVE_MMCIF1_RX, - .addr = 0xee220034, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0xe2, - }, -}; - -#define DMAE_CHANNEL(a, b) \ - { \ - .offset = (a) - 0x20, \ - .dmars = (a) - 0x20 + 0x40, \ - .chclr_bit = (b), \ - .chclr_offset = 0x80 - 0x20, \ - } - -static const struct sh_dmae_channel dma_channels[] = { - DMAE_CHANNEL(0x8000, 0), - DMAE_CHANNEL(0x8080, 1), - DMAE_CHANNEL(0x8100, 2), - DMAE_CHANNEL(0x8180, 3), - DMAE_CHANNEL(0x8200, 4), - DMAE_CHANNEL(0x8280, 5), - DMAE_CHANNEL(0x8300, 6), - DMAE_CHANNEL(0x8380, 7), - DMAE_CHANNEL(0x8400, 8), - DMAE_CHANNEL(0x8480, 9), - DMAE_CHANNEL(0x8500, 10), - DMAE_CHANNEL(0x8580, 11), - DMAE_CHANNEL(0x8600, 12), - DMAE_CHANNEL(0x8680, 13), - DMAE_CHANNEL(0x8700, 14), - DMAE_CHANNEL(0x8780, 15), - DMAE_CHANNEL(0x8800, 16), - DMAE_CHANNEL(0x8880, 17), - DMAE_CHANNEL(0x8900, 18), - DMAE_CHANNEL(0x8980, 19), -}; - -static const struct sh_dmae_pdata dma_pdata = { - .slave = dma_slaves, - .slave_num = ARRAY_SIZE(dma_slaves), - .channel = dma_channels, - .channel_num = ARRAY_SIZE(dma_channels), - .ts_low_shift = TS_LOW_SHIFT, - .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, - .ts_high_shift = TS_HI_SHIFT, - .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, - .ts_shift = dma_ts_shift, - .ts_shift_num = ARRAY_SIZE(dma_ts_shift), - .dmaor_init = DMAOR_DME, - .chclr_present = 1, - .chclr_bitwise = 1, -}; - -static struct resource dma_resources[] = { - DEFINE_RES_MEM(0xe6700020, 0x89e0), - DEFINE_RES_IRQ(gic_spi(220)), - { - /* IRQ for channels 0-19 */ - .start = gic_spi(200), - .end = gic_spi(219), - .flags = IORESOURCE_IRQ, - }, -}; - -#define r8a73a4_register_dmac() \ - platform_device_register_resndata(NULL, "sh-dma-engine", 0, \ - dma_resources, ARRAY_SIZE(dma_resources), \ - &dma_pdata, sizeof(dma_pdata)) - -void __init r8a73a4_add_standard_devices(void) -{ - r8a73a4_register_cmt(1); - r8a73a4_register_scif(0); - r8a73a4_register_scif(1); - r8a73a4_register_scif(2); - r8a73a4_register_scif(3); - r8a73a4_register_scif(4); - r8a73a4_register_scif(5); - r8a73a4_register_irqc(0); - r8a73a4_register_irqc(1); - r8a73a4_register_thermal(); - r8a73a4_register_dmac(); -} - -#ifdef CONFIG_USE_OF static const char *r8a73a4_boards_compat_dt[] __initdata = { "renesas,r8a73a4", @@ -298,4 +30,3 @@ DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") .init_late = shmobile_init_late, .dt_compat = r8a73a4_boards_compat_dt, MACHINE_END -#endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index cef8895..c49aa09 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <linux/clk/shmobile.h> #include <linux/kernel.h> #include <linux/io.h> #include <linux/irqchip/arm-gic.h> @@ -41,6 +42,21 @@ #include "irqs.h" #include "r8a7778.h" +#define MODEMR 0xffcc0020 + +#ifdef CONFIG_COMMON_CLK +static void __init r8a7778_timer_init(void) +{ + u32 mode; + void __iomem *modemr = ioremap_nocache(MODEMR, 4); + + BUG_ON(!modemr); + mode = ioread32(modemr); + iounmap(modemr); + r8a7778_clocks_init(mode); +} +#endif + /* SCIF */ #define R8A7778_SCIF(index, baseaddr, irq) \ static struct plat_sci_port scif##index##_platform_data = { \ @@ -608,6 +624,9 @@ DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") .init_early = shmobile_init_delay, .init_irq = r8a7778_init_irq_dt, .init_late = shmobile_init_late, +#ifdef CONFIG_COMMON_CLK + .init_time = r8a7778_timer_init, +#endif .dt_compat = r8a7778_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c deleted file mode 100644 index 458a2cf..0000000 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ /dev/null @@ -1,1016 +0,0 @@ -/* - * sh7372 processor support - * - * Copyright (C) 2010 Magnus Damm - * Copyright (C) 2008 Yoshihiro Shimoda - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/of_platform.h> -#include <linux/uio_driver.h> -#include <linux/delay.h> -#include <linux/input.h> -#include <linux/io.h> -#include <linux/serial_sci.h> -#include <linux/sh_dma.h> -#include <linux/sh_timer.h> -#include <linux/pm_domain.h> -#include <linux/dma-mapping.h> -#include <linux/platform_data/sh_ipmmu.h> - -#include <asm/mach/map.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "dma-register.h" -#include "intc.h" -#include "irqs.h" -#include "pm-rmobile.h" -#include "sh7372.h" - -static struct map_desc sh7372_io_desc[] __initdata = { - /* create a 1:1 identity mapping for 0xe6xxxxxx - * used by CPGA, INTC and PFC. - */ - { - .virtual = 0xe6000000, - .pfn = __phys_to_pfn(0xe6000000), - .length = 256 << 20, - .type = MT_DEVICE_NONSHARED - }, -}; - -void __init sh7372_map_io(void) -{ - debug_ll_io_init(); - iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc)); -} - -/* PFC */ -static struct resource sh7372_pfc_resources[] = { - [0] = { - .start = 0xe6050000, - .end = 0xe6057fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0xe605800c, - .end = 0xe6058027, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device sh7372_pfc_device = { - .name = "pfc-sh7372", - .id = -1, - .resource = sh7372_pfc_resources, - .num_resources = ARRAY_SIZE(sh7372_pfc_resources), -}; - -void __init sh7372_pinmux_init(void) -{ - platform_device_register(&sh7372_pfc_device); -} - -/* SCIF */ -#define SH7372_SCIF(scif_type, index, baseaddr, irq) \ -static struct plat_sci_port scif##index##_platform_data = { \ - .type = scif_type, \ - .flags = UPF_BOOT_AUTOCONF, \ - .scscr = SCSCR_RE | SCSCR_TE, \ -}; \ - \ -static struct resource scif##index##_resources[] = { \ - DEFINE_RES_MEM(baseaddr, 0x100), \ - DEFINE_RES_IRQ(irq), \ -}; \ - \ -static struct platform_device scif##index##_device = { \ - .name = "sh-sci", \ - .id = index, \ - .resource = scif##index##_resources, \ - .num_resources = ARRAY_SIZE(scif##index##_resources), \ - .dev = { \ - .platform_data = &scif##index##_platform_data, \ - }, \ -} - -SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00)); -SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20)); -SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40)); -SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60)); -SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20)); -SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40)); -SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60)); - -/* CMT */ -static struct sh_timer_config cmt2_platform_data = { - .channels_mask = 0x20, -}; - -static struct resource cmt2_resources[] = { - DEFINE_RES_MEM(0xe6130000, 0x50), - DEFINE_RES_IRQ(evt2irq(0x0b80)), -}; - -static struct platform_device cmt2_device = { - .name = "sh-cmt-32-fast", - .id = 2, - .dev = { - .platform_data = &cmt2_platform_data, - }, - .resource = cmt2_resources, - .num_resources = ARRAY_SIZE(cmt2_resources), -}; - -/* TMU */ -static struct sh_timer_config tmu0_platform_data = { - .channels_mask = 7, -}; - -static struct resource tmu0_resources[] = { - DEFINE_RES_MEM(0xfff60000, 0x2c), - DEFINE_RES_IRQ(intcs_evt2irq(0xe80)), - DEFINE_RES_IRQ(intcs_evt2irq(0xea0)), - DEFINE_RES_IRQ(intcs_evt2irq(0xec0)), -}; - -static struct platform_device tmu0_device = { - .name = "sh-tmu", - .id = 0, - .dev = { - .platform_data = &tmu0_platform_data, - }, - .resource = tmu0_resources, - .num_resources = ARRAY_SIZE(tmu0_resources), -}; - -/* I2C */ -static struct resource iic0_resources[] = { - [0] = { - .name = "IIC0", - .start = 0xFFF20000, - .end = 0xFFF20425 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */ - .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device iic0_device = { - .name = "i2c-sh_mobile", - .id = 0, /* "i2c0" clock */ - .num_resources = ARRAY_SIZE(iic0_resources), - .resource = iic0_resources, -}; - -static struct resource iic1_resources[] = { - [0] = { - .name = "IIC1", - .start = 0xE6C20000, - .end = 0xE6C20425 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = evt2irq(0x780), /* IIC1_ALI1 */ - .end = evt2irq(0x7e0), /* IIC1_DTEI1 */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device iic1_device = { - .name = "i2c-sh_mobile", - .id = 1, /* "i2c1" clock */ - .num_resources = ARRAY_SIZE(iic1_resources), - .resource = iic1_resources, -}; - -/* DMA */ -static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = { - { - .slave_id = SHDMA_SLAVE_SCIF0_TX, - .addr = 0xe6c40020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x21, - }, { - .slave_id = SHDMA_SLAVE_SCIF0_RX, - .addr = 0xe6c40024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x22, - }, { - .slave_id = SHDMA_SLAVE_SCIF1_TX, - .addr = 0xe6c50020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x25, - }, { - .slave_id = SHDMA_SLAVE_SCIF1_RX, - .addr = 0xe6c50024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x26, - }, { - .slave_id = SHDMA_SLAVE_SCIF2_TX, - .addr = 0xe6c60020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x29, - }, { - .slave_id = SHDMA_SLAVE_SCIF2_RX, - .addr = 0xe6c60024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x2a, - }, { - .slave_id = SHDMA_SLAVE_SCIF3_TX, - .addr = 0xe6c70020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x2d, - }, { - .slave_id = SHDMA_SLAVE_SCIF3_RX, - .addr = 0xe6c70024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x2e, - }, { - .slave_id = SHDMA_SLAVE_SCIF4_TX, - .addr = 0xe6c80020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x39, - }, { - .slave_id = SHDMA_SLAVE_SCIF4_RX, - .addr = 0xe6c80024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x3a, - }, { - .slave_id = SHDMA_SLAVE_SCIF5_TX, - .addr = 0xe6cb0020, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x35, - }, { - .slave_id = SHDMA_SLAVE_SCIF5_RX, - .addr = 0xe6cb0024, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x36, - }, { - .slave_id = SHDMA_SLAVE_SCIF6_TX, - .addr = 0xe6c30040, - .chcr = CHCR_TX(XMIT_SZ_8BIT), - .mid_rid = 0x3d, - }, { - .slave_id = SHDMA_SLAVE_SCIF6_RX, - .addr = 0xe6c30060, - .chcr = CHCR_RX(XMIT_SZ_8BIT), - .mid_rid = 0x3e, - }, { - .slave_id = SHDMA_SLAVE_FLCTL0_TX, - .addr = 0xe6a30050, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0x83, - }, { - .slave_id = SHDMA_SLAVE_FLCTL0_RX, - .addr = 0xe6a30050, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0x83, - }, { - .slave_id = SHDMA_SLAVE_FLCTL1_TX, - .addr = 0xe6a30060, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0x87, - }, { - .slave_id = SHDMA_SLAVE_FLCTL1_RX, - .addr = 0xe6a30060, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0x87, - }, { - .slave_id = SHDMA_SLAVE_SDHI0_TX, - .addr = 0xe6850030, - .chcr = CHCR_TX(XMIT_SZ_16BIT), - .mid_rid = 0xc1, - }, { - .slave_id = SHDMA_SLAVE_SDHI0_RX, - .addr = 0xe6850030, - .chcr = CHCR_RX(XMIT_SZ_16BIT), - .mid_rid = 0xc2, - }, { - .slave_id = SHDMA_SLAVE_SDHI1_TX, - .addr = 0xe6860030, - .chcr = CHCR_TX(XMIT_SZ_16BIT), - .mid_rid = 0xc9, - }, { - .slave_id = SHDMA_SLAVE_SDHI1_RX, - .addr = 0xe6860030, - .chcr = CHCR_RX(XMIT_SZ_16BIT), - .mid_rid = 0xca, - }, { - .slave_id = SHDMA_SLAVE_SDHI2_TX, - .addr = 0xe6870030, - .chcr = CHCR_TX(XMIT_SZ_16BIT), - .mid_rid = 0xcd, - }, { - .slave_id = SHDMA_SLAVE_SDHI2_RX, - .addr = 0xe6870030, - .chcr = CHCR_RX(XMIT_SZ_16BIT), - .mid_rid = 0xce, - }, { - .slave_id = SHDMA_SLAVE_FSIA_TX, - .addr = 0xfe1f0024, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0xb1, - }, { - .slave_id = SHDMA_SLAVE_FSIA_RX, - .addr = 0xfe1f0020, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0xb2, - }, { - .slave_id = SHDMA_SLAVE_MMCIF_TX, - .addr = 0xe6bd0034, - .chcr = CHCR_TX(XMIT_SZ_32BIT), - .mid_rid = 0xd1, - }, { - .slave_id = SHDMA_SLAVE_MMCIF_RX, - .addr = 0xe6bd0034, - .chcr = CHCR_RX(XMIT_SZ_32BIT), - .mid_rid = 0xd2, - }, -}; - -#define SH7372_CHCLR (0x220 - 0x20) - -static const struct sh_dmae_channel sh7372_dmae_channels[] = { - { - .offset = 0, - .dmars = 0, - .dmars_bit = 0, - .chclr_offset = SH7372_CHCLR + 0, - }, { - .offset = 0x10, - .dmars = 0, - .dmars_bit = 8, - .chclr_offset = SH7372_CHCLR + 0x10, - }, { - .offset = 0x20, - .dmars = 4, - .dmars_bit = 0, - .chclr_offset = SH7372_CHCLR + 0x20, - }, { - .offset = 0x30, - .dmars = 4, - .dmars_bit = 8, - .chclr_offset = SH7372_CHCLR + 0x30, - }, { - .offset = 0x50, - .dmars = 8, - .dmars_bit = 0, - .chclr_offset = SH7372_CHCLR + 0x50, - }, { - .offset = 0x60, - .dmars = 8, - .dmars_bit = 8, - .chclr_offset = SH7372_CHCLR + 0x60, - } -}; - -static struct sh_dmae_pdata dma_platform_data = { - .slave = sh7372_dmae_slaves, - .slave_num = ARRAY_SIZE(sh7372_dmae_slaves), - .channel = sh7372_dmae_channels, - .channel_num = ARRAY_SIZE(sh7372_dmae_channels), - .ts_low_shift = TS_LOW_SHIFT, - .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, - .ts_high_shift = TS_HI_SHIFT, - .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, - .ts_shift = dma_ts_shift, - .ts_shift_num = ARRAY_SIZE(dma_ts_shift), - .dmaor_init = DMAOR_DME, - .chclr_present = 1, -}; - -/* Resource order important! */ -static struct resource sh7372_dmae0_resources[] = { - { - /* Channel registers and DMAOR */ - .start = 0xfe008020, - .end = 0xfe00828f, - .flags = IORESOURCE_MEM, - }, - { - /* DMARSx */ - .start = 0xfe009000, - .end = 0xfe00900b, - .flags = IORESOURCE_MEM, - }, - { - .name = "error_irq", - .start = evt2irq(0x20c0), - .end = evt2irq(0x20c0), - .flags = IORESOURCE_IRQ, - }, - { - /* IRQ for channels 0-5 */ - .start = evt2irq(0x2000), - .end = evt2irq(0x20a0), - .flags = IORESOURCE_IRQ, - }, -}; - -/* Resource order important! */ -static struct resource sh7372_dmae1_resources[] = { - { - /* Channel registers and DMAOR */ - .start = 0xfe018020, - .end = 0xfe01828f, - .flags = IORESOURCE_MEM, - }, - { - /* DMARSx */ - .start = 0xfe019000, - .end = 0xfe01900b, - .flags = IORESOURCE_MEM, - }, - { - .name = "error_irq", - .start = evt2irq(0x21c0), - .end = evt2irq(0x21c0), - .flags = IORESOURCE_IRQ, - }, - { - /* IRQ for channels 0-5 */ - .start = evt2irq(0x2100), - .end = evt2irq(0x21a0), - .flags = IORESOURCE_IRQ, - }, -}; - -/* Resource order important! */ -static struct resource sh7372_dmae2_resources[] = { - { - /* Channel registers and DMAOR */ - .start = 0xfe028020, - .end = 0xfe02828f, - .flags = IORESOURCE_MEM, - }, - { - /* DMARSx */ - .start = 0xfe029000, - .end = 0xfe02900b, - .flags = IORESOURCE_MEM, - }, - { - .name = "error_irq", - .start = evt2irq(0x22c0), - .end = evt2irq(0x22c0), - .flags = IORESOURCE_IRQ, - }, - { - /* IRQ for channels 0-5 */ - .start = evt2irq(0x2200), - .end = evt2irq(0x22a0), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dma0_device = { - .name = "sh-dma-engine", - .id = 0, - .resource = sh7372_dmae0_resources, - .num_resources = ARRAY_SIZE(sh7372_dmae0_resources), - .dev = { - .platform_data = &dma_platform_data, - }, -}; - -static struct platform_device dma1_device = { - .name = "sh-dma-engine", - .id = 1, - .resource = sh7372_dmae1_resources, - .num_resources = ARRAY_SIZE(sh7372_dmae1_resources), - .dev = { - .platform_data = &dma_platform_data, - }, -}; - -static struct platform_device dma2_device = { - .name = "sh-dma-engine", - .id = 2, - .resource = sh7372_dmae2_resources, - .num_resources = ARRAY_SIZE(sh7372_dmae2_resources), - .dev = { - .platform_data = &dma_platform_data, - }, -}; - -/* - * USB-DMAC - */ -static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = { - { - .offset = 0, - }, { - .offset = 0x20, - }, -}; - -/* USB DMAC0 */ -static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = { - { - .slave_id = SHDMA_SLAVE_USB0_TX, - .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), - }, { - .slave_id = SHDMA_SLAVE_USB0_RX, - .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), - }, -}; - -static struct sh_dmae_pdata usb_dma0_platform_data = { - .slave = sh7372_usb_dmae0_slaves, - .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves), - .channel = sh7372_usb_dmae_channels, - .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels), - .ts_low_shift = USBTS_LOW_SHIFT, - .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT, - .ts_high_shift = USBTS_HI_SHIFT, - .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT, - .ts_shift = dma_usbts_shift, - .ts_shift_num = ARRAY_SIZE(dma_usbts_shift), - .dmaor_init = DMAOR_DME, - .chcr_offset = 0x14, - .chcr_ie_bit = 1 << 5, - .dmaor_is_32bit = 1, - .needs_tend_set = 1, - .no_dmars = 1, - .slave_only = 1, -}; - -static struct resource sh7372_usb_dmae0_resources[] = { - { - /* Channel registers and DMAOR */ - .start = 0xe68a0020, - .end = 0xe68a0064 - 1, - .flags = IORESOURCE_MEM, - }, - { - /* VCR/SWR/DMICR */ - .start = 0xe68a0000, - .end = 0xe68a0014 - 1, - .flags = IORESOURCE_MEM, - }, - { - /* IRQ for channels */ - .start = evt2irq(0x0a00), - .end = evt2irq(0x0a00), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device usb_dma0_device = { - .name = "sh-dma-engine", - .id = 3, - .resource = sh7372_usb_dmae0_resources, - .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources), - .dev = { - .platform_data = &usb_dma0_platform_data, - }, -}; - -/* USB DMAC1 */ -static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = { - { - .slave_id = SHDMA_SLAVE_USB1_TX, - .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), - }, { - .slave_id = SHDMA_SLAVE_USB1_RX, - .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), - }, -}; - -static struct sh_dmae_pdata usb_dma1_platform_data = { - .slave = sh7372_usb_dmae1_slaves, - .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves), - .channel = sh7372_usb_dmae_channels, - .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels), - .ts_low_shift = USBTS_LOW_SHIFT, - .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT, - .ts_high_shift = USBTS_HI_SHIFT, - .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT, - .ts_shift = dma_usbts_shift, - .ts_shift_num = ARRAY_SIZE(dma_usbts_shift), - .dmaor_init = DMAOR_DME, - .chcr_offset = 0x14, - .chcr_ie_bit = 1 << 5, - .dmaor_is_32bit = 1, - .needs_tend_set = 1, - .no_dmars = 1, - .slave_only = 1, -}; - -static struct resource sh7372_usb_dmae1_resources[] = { - { - /* Channel registers and DMAOR */ - .start = 0xe68c0020, - .end = 0xe68c0064 - 1, - .flags = IORESOURCE_MEM, - }, - { - /* VCR/SWR/DMICR */ - .start = 0xe68c0000, - .end = 0xe68c0014 - 1, - .flags = IORESOURCE_MEM, - }, - { - /* IRQ for channels */ - .start = evt2irq(0x1d00), - .end = evt2irq(0x1d00), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device usb_dma1_device = { - .name = "sh-dma-engine", - .id = 4, - .resource = sh7372_usb_dmae1_resources, - .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources), - .dev = { - .platform_data = &usb_dma1_platform_data, - }, -}; - -/* VPU */ -static struct uio_info vpu_platform_data = { - .name = "VPU5HG", - .version = "0", - .irq = intcs_evt2irq(0x980), -}; - -static struct resource vpu_resources[] = { - [0] = { - .name = "VPU", - .start = 0xfe900000, - .end = 0xfe900157, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device vpu_device = { - .name = "uio_pdrv_genirq", - .id = 0, - .dev = { - .platform_data = &vpu_platform_data, - }, - .resource = vpu_resources, - .num_resources = ARRAY_SIZE(vpu_resources), -}; - -/* VEU0 */ -static struct uio_info veu0_platform_data = { - .name = "VEU0", - .version = "0", - .irq = intcs_evt2irq(0x700), -}; - -static struct resource veu0_resources[] = { - [0] = { - .name = "VEU0", - .start = 0xfe920000, - .end = 0xfe9200cb, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device veu0_device = { - .name = "uio_pdrv_genirq", - .id = 1, - .dev = { - .platform_data = &veu0_platform_data, - }, - .resource = veu0_resources, - .num_resources = ARRAY_SIZE(veu0_resources), -}; - -/* VEU1 */ -static struct uio_info veu1_platform_data = { - .name = "VEU1", - .version = "0", - .irq = intcs_evt2irq(0x720), -}; - -static struct resource veu1_resources[] = { - [0] = { - .name = "VEU1", - .start = 0xfe924000, - .end = 0xfe9240cb, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device veu1_device = { - .name = "uio_pdrv_genirq", - .id = 2, - .dev = { - .platform_data = &veu1_platform_data, - }, - .resource = veu1_resources, - .num_resources = ARRAY_SIZE(veu1_resources), -}; - -/* VEU2 */ -static struct uio_info veu2_platform_data = { - .name = "VEU2", - .version = "0", - .irq = intcs_evt2irq(0x740), -}; - -static struct resource veu2_resources[] = { - [0] = { - .name = "VEU2", - .start = 0xfe928000, - .end = 0xfe928307, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device veu2_device = { - .name = "uio_pdrv_genirq", - .id = 3, - .dev = { - .platform_data = &veu2_platform_data, - }, - .resource = veu2_resources, - .num_resources = ARRAY_SIZE(veu2_resources), -}; - -/* VEU3 */ -static struct uio_info veu3_platform_data = { - .name = "VEU3", - .version = "0", - .irq = intcs_evt2irq(0x760), -}; - -static struct resource veu3_resources[] = { - [0] = { - .name = "VEU3", - .start = 0xfe92c000, - .end = 0xfe92c307, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device veu3_device = { - .name = "uio_pdrv_genirq", - .id = 4, - .dev = { - .platform_data = &veu3_platform_data, - }, - .resource = veu3_resources, - .num_resources = ARRAY_SIZE(veu3_resources), -}; - -/* JPU */ -static struct uio_info jpu_platform_data = { - .name = "JPU", - .version = "0", - .irq = intcs_evt2irq(0x560), -}; - -static struct resource jpu_resources[] = { - [0] = { - .name = "JPU", - .start = 0xfe980000, - .end = 0xfe9902d3, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device jpu_device = { - .name = "uio_pdrv_genirq", - .id = 5, - .dev = { - .platform_data = &jpu_platform_data, - }, - .resource = jpu_resources, - .num_resources = ARRAY_SIZE(jpu_resources), -}; - -/* SPU2DSP0 */ -static struct uio_info spu0_platform_data = { - .name = "SPU2DSP0", - .version = "0", - .irq = evt2irq(0x1800), -}; - -static struct resource spu0_resources[] = { - [0] = { - .name = "SPU2DSP0", - .start = 0xfe200000, - .end = 0xfe2fffff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device spu0_device = { - .name = "uio_pdrv_genirq", - .id = 6, - .dev = { - .platform_data = &spu0_platform_data, - }, - .resource = spu0_resources, - .num_resources = ARRAY_SIZE(spu0_resources), -}; - -/* SPU2DSP1 */ -static struct uio_info spu1_platform_data = { - .name = "SPU2DSP1", - .version = "0", - .irq = evt2irq(0x1820), -}; - -static struct resource spu1_resources[] = { - [0] = { - .name = "SPU2DSP1", - .start = 0xfe300000, - .end = 0xfe3fffff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device spu1_device = { - .name = "uio_pdrv_genirq", - .id = 7, - .dev = { - .platform_data = &spu1_platform_data, - }, - .resource = spu1_resources, - .num_resources = ARRAY_SIZE(spu1_resources), -}; - -/* IPMMUI (an IPMMU module for ICB/LMB) */ -static struct resource ipmmu_resources[] = { - [0] = { - .name = "IPMMUI", - .start = 0xfe951000, - .end = 0xfe9510ff, - .flags = IORESOURCE_MEM, - }, -}; - -static const char * const ipmmu_dev_names[] = { - "sh_mobile_lcdc_fb.0", - "sh_mobile_lcdc_fb.1", - "sh_mobile_ceu.0", - "uio_pdrv_genirq.0", - "uio_pdrv_genirq.1", - "uio_pdrv_genirq.2", - "uio_pdrv_genirq.3", - "uio_pdrv_genirq.4", - "uio_pdrv_genirq.5", -}; - -static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { - .dev_names = ipmmu_dev_names, - .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), -}; - -static struct platform_device ipmmu_device = { - .name = "ipmmu", - .id = -1, - .dev = { - .platform_data = &ipmmu_platform_data, - }, - .resource = ipmmu_resources, - .num_resources = ARRAY_SIZE(ipmmu_resources), -}; - -static struct platform_device *sh7372_early_devices[] __initdata = { - &scif0_device, - &scif1_device, - &scif2_device, - &scif3_device, - &scif4_device, - &scif5_device, - &scif6_device, - &cmt2_device, - &tmu0_device, - &ipmmu_device, -}; - -static struct platform_device *sh7372_late_devices[] __initdata = { - &iic0_device, - &iic1_device, - &dma0_device, - &dma1_device, - &dma2_device, - &usb_dma0_device, - &usb_dma1_device, - &vpu_device, - &veu0_device, - &veu1_device, - &veu2_device, - &veu3_device, - &jpu_device, - &spu0_device, - &spu1_device, -}; - -void __init sh7372_add_standard_devices(void) -{ - static struct pm_domain_device domain_devices[] __initdata = { - { "A3RV", &vpu_device, }, - { "A4MP", &spu0_device, }, - { "A4MP", &spu1_device, }, - { "A3SP", &scif0_device, }, - { "A3SP", &scif1_device, }, - { "A3SP", &scif2_device, }, - { "A3SP", &scif3_device, }, - { "A3SP", &scif4_device, }, - { "A3SP", &scif5_device, }, - { "A3SP", &scif6_device, }, - { "A3SP", &iic1_device, }, - { "A3SP", &dma0_device, }, - { "A3SP", &dma1_device, }, - { "A3SP", &dma2_device, }, - { "A3SP", &usb_dma0_device, }, - { "A3SP", &usb_dma1_device, }, - { "A4R", &iic0_device, }, - { "A4R", &veu0_device, }, - { "A4R", &veu1_device, }, - { "A4R", &veu2_device, }, - { "A4R", &veu3_device, }, - { "A4R", &jpu_device, }, - { "A4R", &tmu0_device, }, - }; - - sh7372_init_pm_domains(); - - platform_add_devices(sh7372_early_devices, - ARRAY_SIZE(sh7372_early_devices)); - - platform_add_devices(sh7372_late_devices, - ARRAY_SIZE(sh7372_late_devices)); - - rmobile_add_devices_to_domains(domain_devices, - ARRAY_SIZE(domain_devices)); -} - -void __init sh7372_earlytimer_init(void) -{ - sh7372_clock_init(); - shmobile_earlytimer_init(); -} - -void __init sh7372_add_early_devices(void) -{ - early_platform_add_devices(sh7372_early_devices, - ARRAY_SIZE(sh7372_early_devices)); - - /* setup early console here as well */ - shmobile_setup_console(); -} - -#ifdef CONFIG_USE_OF - -void __init sh7372_add_early_devices_dt(void) -{ - shmobile_init_delay(); - - sh7372_add_early_devices(); -} - -void __init sh7372_add_standard_devices_dt(void) -{ - /* clocks are setup late during boot in the case of DT */ - sh7372_clock_init(); - - platform_add_devices(sh7372_early_devices, - ARRAY_SIZE(sh7372_early_devices)); - - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - -static const char *sh7372_boards_compat_dt[] __initdata = { - "renesas,sh7372", - NULL, -}; - -DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)") - .map_io = sh7372_map_io, - .init_early = sh7372_add_early_devices_dt, - .init_irq = sh7372_init_irq, - .handle_irq = shmobile_handle_irq_intc, - .init_machine = sh7372_add_standard_devices_dt, - .init_late = shmobile_init_late, - .dt_compat = sh7372_boards_compat_dt, -MACHINE_END - -#endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index faea74a..fb2ab75 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -30,6 +30,7 @@ #include <linux/platform_data/sh_ipmmu.h> #include <linux/platform_data/irq-renesas-intc-irqpin.h> +#include <asm/hardware/cache-l2x0.h> #include <asm/mach-types.h> #include <asm/mach/map.h> #include <asm/mach/arch.h> @@ -784,22 +785,15 @@ void __init sh73a0_add_early_devices(void) #ifdef CONFIG_USE_OF -void __init sh73a0_add_standard_devices_dt(void) +static void __init sh73a0_generic_init(void) { - /* clocks are setup late during boot in the case of DT */ -#ifndef CONFIG_COMMON_CLK - sh73a0_clock_init(); +#ifdef CONFIG_CACHE_L2X0 + /* Shared attribute override enable, 64K*8way */ + l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); #endif of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -#define RESCNT2 IOMEM(0xe6188020) -static void sh73a0_restart(enum reboot_mode mode, const char *cmd) -{ - /* Do soft power on reset */ - writel((1 << 31), RESCNT2); -} - static const char *sh73a0_boards_compat_dt[] __initdata = { "renesas,sh73a0", NULL, @@ -809,9 +803,8 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") .smp = smp_ops(sh73a0_smp_ops), .map_io = sh73a0_map_io, .init_early = shmobile_init_delay, - .init_machine = sh73a0_add_standard_devices_dt, + .init_machine = sh73a0_generic_init, .init_late = shmobile_init_late, - .restart = sh73a0_restart, .dt_compat = sh73a0_boards_compat_dt, MACHINE_END #endif /* CONFIG_USE_OF */ diff --git a/arch/arm/mach-shmobile/sh7372.h b/arch/arm/mach-shmobile/sh7372.h deleted file mode 100644 index 4ad960d..0000000 --- a/arch/arm/mach-shmobile/sh7372.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (C) 2010 Renesas Solutions Corp. - * - * Kuninori Morimoto <morimoto.kuninori@renesas.com> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#ifndef __ASM_SH7372_H__ -#define __ASM_SH7372_H__ - -/* DMA slave IDs */ -enum { - SHDMA_SLAVE_INVALID, - SHDMA_SLAVE_SCIF0_TX, - SHDMA_SLAVE_SCIF0_RX, - SHDMA_SLAVE_SCIF1_TX, - SHDMA_SLAVE_SCIF1_RX, - SHDMA_SLAVE_SCIF2_TX, - SHDMA_SLAVE_SCIF2_RX, - SHDMA_SLAVE_SCIF3_TX, - SHDMA_SLAVE_SCIF3_RX, - SHDMA_SLAVE_SCIF4_TX, - SHDMA_SLAVE_SCIF4_RX, - SHDMA_SLAVE_SCIF5_TX, - SHDMA_SLAVE_SCIF5_RX, - SHDMA_SLAVE_SCIF6_TX, - SHDMA_SLAVE_SCIF6_RX, - SHDMA_SLAVE_FLCTL0_TX, - SHDMA_SLAVE_FLCTL0_RX, - SHDMA_SLAVE_FLCTL1_TX, - SHDMA_SLAVE_FLCTL1_RX, - SHDMA_SLAVE_SDHI0_RX, - SHDMA_SLAVE_SDHI0_TX, - SHDMA_SLAVE_SDHI1_RX, - SHDMA_SLAVE_SDHI1_TX, - SHDMA_SLAVE_SDHI2_RX, - SHDMA_SLAVE_SDHI2_TX, - SHDMA_SLAVE_FSIA_RX, - SHDMA_SLAVE_FSIA_TX, - SHDMA_SLAVE_MMCIF_RX, - SHDMA_SLAVE_MMCIF_TX, - SHDMA_SLAVE_USB0_TX, - SHDMA_SLAVE_USB0_RX, - SHDMA_SLAVE_USB1_TX, - SHDMA_SLAVE_USB1_RX, -}; - -extern struct clk sh7372_extal1_clk; -extern struct clk sh7372_extal2_clk; -extern struct clk sh7372_dv_clki_clk; -extern struct clk sh7372_dv_clki_div2_clk; -extern struct clk sh7372_pllc2_clk; - -extern void sh7372_init_irq(void); -extern void sh7372_map_io(void); -extern void sh7372_earlytimer_init(void); -extern void sh7372_add_early_devices(void); -extern void sh7372_add_standard_devices(void); -extern void sh7372_add_early_devices_dt(void); -extern void sh7372_add_standard_devices_dt(void); -extern void sh7372_clock_init(void); -extern void sh7372_pinmux_init(void); -extern void sh7372_pm_init(void); -extern void sh7372_resume_core_standby_sysc(void); -extern int sh7372_do_idle_sysc(unsigned long sleep_mode); -extern void sh7372_intcs_suspend(void); -extern void sh7372_intcs_resume(void); -extern void sh7372_intca_suspend(void); -extern void sh7372_intca_resume(void); - -extern unsigned long sh7372_cpu_resume; - -#ifdef CONFIG_PM -extern void __init sh7372_init_pm_domains(void); -#else -static inline void sh7372_init_pm_domains(void) {} -#endif - -extern void __init sh7372_pm_init_late(void); - -#endif /* __ASM_SH7372_H__ */ diff --git a/arch/arm/mach-shmobile/sh73a0.h b/arch/arm/mach-shmobile/sh73a0.h index f037c64..5a80f18 100644 --- a/arch/arm/mach-shmobile/sh73a0.h +++ b/arch/arm/mach-shmobile/sh73a0.h @@ -77,7 +77,6 @@ extern void sh73a0_map_io(void); extern void sh73a0_earlytimer_init(void); extern void sh73a0_add_early_devices(void); extern void sh73a0_add_standard_devices(void); -extern void sh73a0_add_standard_devices_dt(void); extern void sh73a0_clock_init(void); extern void sh73a0_pinmux_init(void); extern void sh73a0_pm_init(void); diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S deleted file mode 100644 index 146b8de..0000000 --- a/arch/arm/mach-shmobile/sleep-sh7372.S +++ /dev/null @@ -1,98 +0,0 @@ -/* - * sh7372 lowlevel sleep code for "Core Standby Mode" - * - * Copyright (C) 2011 Magnus Damm - * - * In "Core Standby Mode" the ARM core is off, but L2 cache is still on - * - * Based on mach-omap2/sleep34xx.S - * - * (C) Copyright 2007 Texas Instruments - * Karthik Dasu <karthik-dp@ti.com> - * - * (C) Copyright 2004 Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/linkage.h> -#include <linux/init.h> -#include <asm/memory.h> -#include <asm/assembler.h> - -#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) - .align 12 - .text - .global sh7372_resume_core_standby_sysc -sh7372_resume_core_standby_sysc: - ldr pc, 1f - - .align 2 - .globl sh7372_cpu_resume -sh7372_cpu_resume: -1: .space 4 - -#define SPDCR 0xe6180008 - - /* A3SM & A4S power down */ - .global sh7372_do_idle_sysc -sh7372_do_idle_sysc: - mov r8, r0 /* sleep mode passed in r0 */ - - /* - * Clear the SCTLR.C bit to prevent further data cache - * allocation. Clearing SCTLR.C would make all the data accesses - * strongly ordered and would not hit the cache. - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #(1 << 2) @ Disable the C bit - mcr p15, 0, r0, c1, c0, 0 - isb - - /* - * Clean and invalidate data cache again. - */ - ldr r1, kernel_flush - blx r1 - - /* disable L2 cache in the aux control register */ - mrc p15, 0, r10, c1, c0, 1 - bic r10, r10, #2 - mcr p15, 0, r10, c1, c0, 1 - isb - - /* - * The kernel doesn't interwork: v7_flush_dcache_all in particluar will - * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. - * This sequence switches back to ARM. Note that .align may insert a - * nop: bx pc needs to be word-aligned in order to work. - */ - THUMB( .thumb ) - THUMB( .align ) - THUMB( bx pc ) - THUMB( nop ) - .arm - - /* Data memory barrier and Data sync barrier */ - dsb - dmb - - /* SYSC power down */ - ldr r0, =SPDCR - str r8, [r0] -1: - b 1b - - .align 2 -kernel_flush: - .word v7_flush_dcache_all -#endif diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 9fc280e..01f792f 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -124,19 +124,12 @@ static int r8a7779_cpu_kill(unsigned int cpu) return 0; } - -static int r8a7779_cpu_disable(unsigned int cpu) -{ - /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */ - return cpu == 0 ? -EPERM : 0; -} #endif /* CONFIG_HOTPLUG_CPU */ struct smp_operations r8a7779_smp_ops __initdata = { .smp_prepare_cpus = r8a7779_smp_prepare_cpus, .smp_boot_secondary = r8a7779_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU - .cpu_disable = r8a7779_cpu_disable, .cpu_die = shmobile_smp_scu_cpu_die, .cpu_kill = r8a7779_cpu_kill, #endif diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index c16dbfe..2106d6b 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -33,7 +33,7 @@ #define SH73A0_SCU_BASE 0xf0000000 -#ifdef CONFIG_HAVE_ARM_TWD +#if defined(CONFIG_HAVE_ARM_TWD) && !defined(CONFIG_ARCH_MULTIPLATFORM) static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); void __init sh73a0_register_twd(void) { diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index a10297d..2ed1b8a 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -526,7 +526,6 @@ ag5evm MACH_AG5EVM AG5EVM 3189 ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206 wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207 trimslice MACH_TRIMSLICE TRIMSLICE 3209 -mackerel MACH_MACKEREL MACKEREL 3211 kaen MACH_KAEN KAEN 3217 nokia_rm680 MACH_NOKIA_RM680 NOKIA_RM680 3220 msm8960_sim MACH_MSM8960_SIM MSM8960_SIM 3230 diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile index 0689d7f..97c71c8 100644 --- a/drivers/clk/shmobile/Makefile +++ b/drivers/clk/shmobile/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o +obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o diff --git a/drivers/clk/shmobile/clk-r8a7778.c b/drivers/clk/shmobile/clk-r8a7778.c new file mode 100644 index 0000000..cb33b57 --- /dev/null +++ b/drivers/clk/shmobile/clk-r8a7778.c @@ -0,0 +1,143 @@ +/* + * r8a7778 Core CPG Clocks + * + * Copyright (C) 2014 Ulrich Hecht + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +#include <linux/clk-provider.h> +#include <linux/clkdev.h> +#include <linux/clk/shmobile.h> +#include <linux/of_address.h> + +struct r8a7778_cpg { + struct clk_onecell_data data; + spinlock_t lock; + void __iomem *reg; +}; + +/* PLL multipliers per bits 11, 12, and 18 of MODEMR */ +struct { + unsigned long plla_mult; + unsigned long pllb_mult; +} r8a7778_rates[] __initdata = { + [0] = { 21, 21 }, + [1] = { 24, 24 }, + [2] = { 28, 28 }, + [3] = { 32, 32 }, + [5] = { 24, 21 }, + [6] = { 28, 21 }, + [7] = { 32, 24 }, +}; + +/* Clock dividers per bits 1 and 2 of MODEMR */ +struct { + const char *name; + unsigned int div[4]; +} r8a7778_divs[6] __initdata = { + { "b", { 12, 12, 16, 18 } }, + { "out", { 12, 12, 16, 18 } }, + { "p", { 16, 12, 16, 12 } }, + { "s", { 4, 3, 4, 3 } }, + { "s1", { 8, 6, 8, 6 } }, +}; + +static u32 cpg_mode_rates __initdata; +static u32 cpg_mode_divs __initdata; + +static struct clk * __init +r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg, + const char *name) +{ + if (!strcmp(name, "plla")) { + return clk_register_fixed_factor(NULL, "plla", + of_clk_get_parent_name(np, 0), 0, + r8a7778_rates[cpg_mode_rates].plla_mult, 1); + } else if (!strcmp(name, "pllb")) { + return clk_register_fixed_factor(NULL, "pllb", + of_clk_get_parent_name(np, 0), 0, + r8a7778_rates[cpg_mode_rates].pllb_mult, 1); + } else { + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(r8a7778_divs); i++) { + if (!strcmp(name, r8a7778_divs[i].name)) { + return clk_register_fixed_factor(NULL, + r8a7778_divs[i].name, + "plla", 0, 1, + r8a7778_divs[i].div[cpg_mode_divs]); + } + } + } + + return ERR_PTR(-EINVAL); +} + + +static void __init r8a7778_cpg_clocks_init(struct device_node *np) +{ + struct r8a7778_cpg *cpg; + struct clk **clks; + unsigned int i; + int num_clks; + + num_clks = of_property_count_strings(np, "clock-output-names"); + if (num_clks < 0) { + pr_err("%s: failed to count clocks\n", __func__); + return; + } + + cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); + clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); + if (cpg == NULL || clks == NULL) { + /* We're leaking memory on purpose, there's no point in cleaning + * up as the system won't boot anyway. + */ + return; + } + + spin_lock_init(&cpg->lock); + + cpg->data.clks = clks; + cpg->data.clk_num = num_clks; + + cpg->reg = of_iomap(np, 0); + if (WARN_ON(cpg->reg == NULL)) + return; + + for (i = 0; i < num_clks; ++i) { + const char *name; + struct clk *clk; + + of_property_read_string_index(np, "clock-output-names", i, + &name); + + clk = r8a7778_cpg_register_clock(np, cpg, name); + if (IS_ERR(clk)) + pr_err("%s: failed to register %s %s clock (%ld)\n", + __func__, np->name, name, PTR_ERR(clk)); + else + cpg->data.clks[i] = clk; + } + + of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); +} + +CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks", + r8a7778_cpg_clocks_init); + +void __init r8a7778_clocks_init(u32 mode) +{ + BUG_ON(!(mode & BIT(19))); + + cpg_mode_rates = (!!(mode & BIT(18)) << 2) | + (!!(mode & BIT(12)) << 1) | + (!!(mode & BIT(11))); + cpg_mode_divs = (!!(mode & BIT(2)) << 1) | + (!!(mode & BIT(1))); + + of_clk_init(NULL); +} diff --git a/include/dt-bindings/clock/r8a73a4-clock.h b/include/dt-bindings/clock/r8a73a4-clock.h new file mode 100644 index 0000000..9a4b4c9 --- /dev/null +++ b/include/dt-bindings/clock/r8a73a4-clock.h @@ -0,0 +1,62 @@ +/* + * Copyright 2014 Ulrich Hecht + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A73A4_H__ +#define __DT_BINDINGS_CLOCK_R8A73A4_H__ + +/* CPG */ +#define R8A73A4_CLK_MAIN 0 +#define R8A73A4_CLK_PLL0 1 +#define R8A73A4_CLK_PLL1 2 +#define R8A73A4_CLK_PLL2 3 +#define R8A73A4_CLK_PLL2S 4 +#define R8A73A4_CLK_PLL2H 5 +#define R8A73A4_CLK_Z 6 +#define R8A73A4_CLK_Z2 7 +#define R8A73A4_CLK_I 8 +#define R8A73A4_CLK_M3 9 +#define R8A73A4_CLK_B 10 +#define R8A73A4_CLK_M1 11 +#define R8A73A4_CLK_M2 12 +#define R8A73A4_CLK_ZX 13 +#define R8A73A4_CLK_ZS 14 +#define R8A73A4_CLK_HP 15 + +/* MSTP2 */ +#define R8A73A4_CLK_DMAC 18 +#define R8A73A4_CLK_SCIFB3 17 +#define R8A73A4_CLK_SCIFB2 16 +#define R8A73A4_CLK_SCIFB1 7 +#define R8A73A4_CLK_SCIFB0 6 +#define R8A73A4_CLK_SCIFA0 4 +#define R8A73A4_CLK_SCIFA1 3 + +/* MSTP3 */ +#define R8A73A4_CLK_CMT1 29 +#define R8A73A4_CLK_IIC1 23 +#define R8A73A4_CLK_IIC0 18 +#define R8A73A4_CLK_IIC7 17 +#define R8A73A4_CLK_IIC6 16 +#define R8A73A4_CLK_MMCIF0 15 +#define R8A73A4_CLK_SDHI0 14 +#define R8A73A4_CLK_SDHI1 13 +#define R8A73A4_CLK_SDHI2 12 +#define R8A73A4_CLK_MMCIF1 5 +#define R8A73A4_CLK_IIC2 0 + +/* MSTP4 */ +#define R8A73A4_CLK_IIC3 11 +#define R8A73A4_CLK_IIC4 10 +#define R8A73A4_CLK_IIC5 9 + +/* MSTP5 */ +#define R8A73A4_CLK_THERMAL 22 +#define R8A73A4_CLK_IIC8 15 + +#endif /* __DT_BINDINGS_CLOCK_R8A73A4_H__ */ diff --git a/include/dt-bindings/clock/r8a7778-clock.h b/include/dt-bindings/clock/r8a7778-clock.h new file mode 100644 index 0000000..f6b07c5 --- /dev/null +++ b/include/dt-bindings/clock/r8a7778-clock.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2014 Ulrich Hecht + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7778_H__ +#define __DT_BINDINGS_CLOCK_R8A7778_H__ + +/* CPG */ +#define R8A7778_CLK_PLLA 0 +#define R8A7778_CLK_PLLB 1 +#define R8A7778_CLK_B 2 +#define R8A7778_CLK_OUT 3 +#define R8A7778_CLK_P 4 +#define R8A7778_CLK_S 5 +#define R8A7778_CLK_S1 6 + +/* MSTP0 */ +#define R8A7778_CLK_I2C0 30 +#define R8A7778_CLK_I2C1 29 +#define R8A7778_CLK_I2C2 28 +#define R8A7778_CLK_I2C3 27 +#define R8A7778_CLK_SCIF0 26 +#define R8A7778_CLK_SCIF1 25 +#define R8A7778_CLK_SCIF2 24 +#define R8A7778_CLK_SCIF3 23 +#define R8A7778_CLK_SCIF4 22 +#define R8A7778_CLK_SCIF5 21 +#define R8A7778_CLK_TMU0 16 +#define R8A7778_CLK_TMU1 15 +#define R8A7778_CLK_TMU2 14 +#define R8A7778_CLK_SSI0 12 +#define R8A7778_CLK_SSI1 11 +#define R8A7778_CLK_SSI2 10 +#define R8A7778_CLK_SSI3 9 +#define R8A7778_CLK_SRU 8 +#define R8A7778_CLK_HSPI 7 + +/* MSTP1 */ +#define R8A7778_CLK_ETHER 14 +#define R8A7778_CLK_VIN0 10 +#define R8A7778_CLK_VIN1 9 +#define R8A7778_CLK_USB 0 + +/* MSTP3 */ +#define R8A7778_CLK_MMC 31 +#define R8A7778_CLK_SDHI0 23 +#define R8A7778_CLK_SDHI1 22 +#define R8A7778_CLK_SDHI2 21 +#define R8A7778_CLK_SSI4 11 +#define R8A7778_CLK_SSI5 10 +#define R8A7778_CLK_SSI6 9 +#define R8A7778_CLK_SSI7 8 +#define R8A7778_CLK_SSI8 7 + +/* MSTP5 */ +#define R8A7778_CLK_SRU_SRC0 31 +#define R8A7778_CLK_SRU_SRC1 30 +#define R8A7778_CLK_SRU_SRC2 29 +#define R8A7778_CLK_SRU_SRC3 28 +#define R8A7778_CLK_SRU_SRC4 27 +#define R8A7778_CLK_SRU_SRC5 26 +#define R8A7778_CLK_SRU_SRC6 25 +#define R8A7778_CLK_SRU_SRC7 24 +#define R8A7778_CLK_SRU_SRC8 23 + +#endif /* __DT_BINDINGS_CLOCK_R8A7778_H__ */ diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h index 9f8a140..63a8159 100644 --- a/include/linux/clk/shmobile.h +++ b/include/linux/clk/shmobile.h @@ -16,6 +16,7 @@ #include <linux/types.h> +void r8a7778_clocks_init(u32 mode); void r8a7779_clocks_init(u32 mode); void rcar_gen2_clocks_init(u32 mode); |
