diff options
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 8 | ||||
| -rw-r--r-- | include/asm-mips/cpu-features.h | 4 | ||||
| -rw-r--r-- | include/asm-mips/cpu.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/mach-cobalt/cpu-feature-overrides.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/mach-excite/cpu-feature-overrides.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/mach-ip27/cpu-feature-overrides.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/mach-ja/cpu-feature-overrides.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/mach-mips/cpu-feature-overrides.h | 4 | ||||
| -rw-r--r-- | include/asm-mips/mach-ocelot3/cpu-feature-overrides.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/mach-sibyte/cpu-feature-overrides.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/mach-sim/cpu-feature-overrides.h | 4 | ||||
| -rw-r--r-- | include/asm-mips/mach-yosemite/cpu-feature-overrides.h | 2 |
12 files changed, 18 insertions, 18 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 857b726..ed35ee5 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -578,7 +578,7 @@ static inline void local_r4k_flush_icache_page(void *args) * secondary cache will result in any entries in the primary caches * also getting invalidated which hopefully is a bit more economical. */ - if (cpu_has_subset_pcaches) { + if (cpu_has_inclusive_pcaches) { unsigned long addr = (unsigned long) page_address(page); r4k_blast_scache_page(addr); @@ -634,7 +634,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) /* Catch bad driver code */ BUG_ON(size == 0); - if (cpu_has_subset_pcaches) { + if (cpu_has_inclusive_pcaches) { if (size >= scache_size) r4k_blast_scache(); else @@ -662,7 +662,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) /* Catch bad driver code */ BUG_ON(size == 0); - if (cpu_has_subset_pcaches) { + if (cpu_has_inclusive_pcaches) { if (size >= scache_size) r4k_blast_scache(); else @@ -1192,7 +1192,7 @@ static void __init setup_scache(void) printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); - c->options |= MIPS_CPU_SUBSET_CACHES; + c->options |= MIPS_CPU_INCLUSIVE_CACHES; } void au1x00_fixup_config_od(void) diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 3c2fc2b..eadca26 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -195,8 +195,8 @@ # define cpu_has_veic 0 #endif -#ifndef cpu_has_subset_pcaches -#define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES) +#ifndef cpu_has_inclusive_pcaches +#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES) #endif #ifndef cpu_dcache_line_size diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index dff2a0a..d38fdbf 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -242,7 +242,7 @@ #define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ #define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ #define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */ +#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */ #define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ #define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h index e0e08fc..c6dfa59d 100644 --- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h +++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h @@ -27,7 +27,7 @@ #define cpu_has_mcheck 0 #define cpu_has_ejtag 0 -#define cpu_has_subset_pcaches 0 +#define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 #define cpu_scache_line_size() 0 diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h index abb76b2..0d31854 100644 --- a/include/asm-mips/mach-excite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h @@ -31,7 +31,7 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 -#define cpu_has_subset_pcaches 0 +#define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h index 19c2d13..a071974 100644 --- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h @@ -34,7 +34,7 @@ #define cpu_has_4kex 1 #define cpu_has_4k_cache 1 -#define cpu_has_subset_pcaches 1 +#define cpu_has_inclusive_pcaches 1 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 64 diff --git a/include/asm-mips/mach-ja/cpu-feature-overrides.h b/include/asm-mips/mach-ja/cpu-feature-overrides.h index 90ff087..84b6dea 100644 --- a/include/asm-mips/mach-ja/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ja/cpu-feature-overrides.h @@ -31,7 +31,7 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 -#define cpu_has_subset_pcaches 0 +#define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h index e960679..7f3e3f9 100644 --- a/include/asm-mips/mach-mips/cpu-feature-overrides.h +++ b/include/asm-mips/mach-mips/cpu-feature-overrides.h @@ -39,7 +39,7 @@ #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_subset_pcaches ? */ +/* #define cpu_has_inclusive_pcaches ? */ #define cpu_icache_snoops_remote_store 1 #endif @@ -65,7 +65,7 @@ #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_subset_pcaches ? */ +/* #define cpu_has_inclusive_pcaches ? */ #define cpu_icache_snoops_remote_store 1 #endif diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h index 782b986..57a12de 100644 --- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h @@ -34,7 +34,7 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 -#define cpu_has_subset_pcaches 0 +#define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h index 193a666..a25968f 100644 --- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h +++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h @@ -31,7 +31,7 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 -#define cpu_has_subset_pcaches 0 +#define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-sim/cpu-feature-overrides.h index d736bda..779b022 100644 --- a/include/asm-mips/mach-sim/cpu-feature-overrides.h +++ b/include/asm-mips/mach-sim/cpu-feature-overrides.h @@ -34,7 +34,7 @@ #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_subset_pcaches ? */ +/* #define cpu_has_inclusive_pcaches ? */ #endif #ifdef CONFIG_CPU_MIPS64 @@ -59,7 +59,7 @@ #define cpu_has_nofpuex 0 /* #define cpu_has_64bits ? */ /* #define cpu_has_64bit_zero_reg ? */ -/* #define cpu_has_subset_pcaches ? */ +/* #define cpu_has_inclusive_pcaches ? */ #endif #endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h index 3073542..42cebb7 100644 --- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h @@ -31,7 +31,7 @@ #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 -#define cpu_has_subset_pcaches 0 +#define cpu_has_inclusive_pcaches 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 |
