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-rw-r--r--arch/arm/kernel/traps.c2
-rw-r--r--arch/arm/mach-footbridge/dc21285.c27
-rw-r--r--arch/arm/vfp/vfpinstr.h8
-rw-r--r--include/asm-arm/arch-l7200/io.h8
-rw-r--r--include/asm-arm/tlbflush.h76
5 files changed, 62 insertions, 59 deletions
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index aeeed80..bede380 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -191,7 +191,7 @@ void show_stack(struct task_struct *tsk, unsigned long *sp)
if (tsk != current)
fp = thread_saved_fp(tsk);
else
- asm("mov%? %0, fp" : "=r" (fp));
+ asm("mov %0, fp" : "=r" (fp) : : "cc");
c_backtrace(fp, 0x10);
barrier();
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 823e25d..a1ae49d 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -69,16 +69,16 @@ dc21285_read_config(struct pci_bus *bus, unsigned int devfn, int where,
if (addr)
switch (size) {
case 1:
- asm("ldr%?b %0, [%1, %2]"
- : "=r" (v) : "r" (addr), "r" (where));
+ asm("ldrb %0, [%1, %2]"
+ : "=r" (v) : "r" (addr), "r" (where) : "cc");
break;
case 2:
- asm("ldr%?h %0, [%1, %2]"
- : "=r" (v) : "r" (addr), "r" (where));
+ asm("ldrh %0, [%1, %2]"
+ : "=r" (v) : "r" (addr), "r" (where) : "cc");
break;
case 4:
- asm("ldr%? %0, [%1, %2]"
- : "=r" (v) : "r" (addr), "r" (where));
+ asm("ldr %0, [%1, %2]"
+ : "=r" (v) : "r" (addr), "r" (where) : "cc");
break;
}
@@ -103,16 +103,19 @@ dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where,
if (addr)
switch (size) {
case 1:
- asm("str%?b %0, [%1, %2]"
- : : "r" (value), "r" (addr), "r" (where));
+ asm("strb %0, [%1, %2]"
+ : : "r" (value), "r" (addr), "r" (where)
+ : "cc");
break;
case 2:
- asm("str%?h %0, [%1, %2]"
- : : "r" (value), "r" (addr), "r" (where));
+ asm("strh %0, [%1, %2]"
+ : : "r" (value), "r" (addr), "r" (where)
+ : "cc");
break;
case 4:
- asm("str%? %0, [%1, %2]"
- : : "r" (value), "r" (addr), "r" (where));
+ asm("str %0, [%1, %2]"
+ : : "r" (value), "r" (addr), "r" (where)
+ : "cc");
break;
}
diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h
index 6c819ae..7f343a4 100644
--- a/arch/arm/vfp/vfpinstr.h
+++ b/arch/arm/vfp/vfpinstr.h
@@ -73,14 +73,14 @@
#define fmrx(_vfp_) ({ \
u32 __v; \
- asm("mrc%? p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
- : "=r" (__v)); \
+ asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
+ : "=r" (__v) : : "cc"); \
__v; \
})
#define fmxr(_vfp_,_var_) \
- asm("mcr%? p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
- : : "r" (_var_))
+ asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
+ : : "r" (_var_) : "cc")
u32 vfp_single_cpdo(u32 inst, u32 fpscr);
u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs);
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
index cd080d8..d744d97 100644
--- a/include/asm-arm/arch-l7200/io.h
+++ b/include/asm-arm/arch-l7200/io.h
@@ -31,9 +31,9 @@
static inline unsigned int __arch_getw(unsigned long a)
{
unsigned int value;
- __asm__ __volatile__("ldr%?h %0, [%1, #0] @ getw"
+ __asm__ __volatile__("ldrh %0, [%1, #0] @ getw"
: "=&r" (value)
- : "r" (a));
+ : "r" (a) : "cc");
return value;
}
@@ -42,8 +42,8 @@ static inline unsigned int __arch_getw(unsigned long a)
static inline void __arch_putw(unsigned int value, unsigned long a)
{
- __asm__ __volatile__("str%?h %0, [%1, #0] @ putw"
- : : "r" (value), "r" (a));
+ __asm__ __volatile__("strh %0, [%1, #0] @ putw"
+ : : "r" (value), "r" (a) : "cc");
}
/*
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index d97fc76..cd10a0b 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -247,16 +247,16 @@ static inline void local_flush_tlb_all(void)
const unsigned int __tlb_flag = __cpu_tlb_flags;
if (tlb_flag(TLB_WB))
- asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V3_FULL))
- asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero));
+ asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
- asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero));
+ asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
- asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero));
+ asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
- asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
+ asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
}
static inline void local_flush_tlb_mm(struct mm_struct *mm)
@@ -266,25 +266,25 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
const unsigned int __tlb_flag = __cpu_tlb_flags;
if (tlb_flag(TLB_WB))
- asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
if (tlb_flag(TLB_V3_FULL))
- asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero));
+ asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V4_U_FULL))
- asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero));
+ asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V4_D_FULL))
- asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero));
+ asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V4_I_FULL))
- asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
+ asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
}
if (tlb_flag(TLB_V6_U_ASID))
- asm("mcr%? p15, 0, %0, c8, c7, 2" : : "r" (asid));
+ asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
if (tlb_flag(TLB_V6_D_ASID))
- asm("mcr%? p15, 0, %0, c8, c6, 2" : : "r" (asid));
+ asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
if (tlb_flag(TLB_V6_I_ASID))
- asm("mcr%? p15, 0, %0, c8, c5, 2" : : "r" (asid));
+ asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
}
static inline void
@@ -296,27 +296,27 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
if (tlb_flag(TLB_WB))
- asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero));
if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
if (tlb_flag(TLB_V3_PAGE))
- asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (uaddr));
+ asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
if (tlb_flag(TLB_V4_U_PAGE))
- asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr));
+ asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
if (tlb_flag(TLB_V4_D_PAGE))
- asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr));
+ asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
if (tlb_flag(TLB_V4_I_PAGE))
- asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
+ asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
- asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
+ asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
}
if (tlb_flag(TLB_V6_U_PAGE))
- asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr));
+ asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
if (tlb_flag(TLB_V6_D_PAGE))
- asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr));
+ asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
if (tlb_flag(TLB_V6_I_PAGE))
- asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
+ asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
}
static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
@@ -327,31 +327,31 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
kaddr &= PAGE_MASK;
if (tlb_flag(TLB_WB))
- asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V3_PAGE))
- asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (kaddr));
+ asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
if (tlb_flag(TLB_V4_U_PAGE))
- asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr));
+ asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
if (tlb_flag(TLB_V4_D_PAGE))
- asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
+ asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
if (tlb_flag(TLB_V4_I_PAGE))
- asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
+ asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
- asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
+ asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
if (tlb_flag(TLB_V6_U_PAGE))
- asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr));
+ asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
if (tlb_flag(TLB_V6_D_PAGE))
- asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
+ asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
if (tlb_flag(TLB_V6_I_PAGE))
- asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
+ asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
/* The ARM ARM states that the completion of a TLB maintenance
* operation is only guaranteed by a DSB instruction
*/
if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))
- asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
}
/*
@@ -373,11 +373,11 @@ static inline void flush_pmd_entry(pmd_t *pmd)
const unsigned int __tlb_flag = __cpu_tlb_flags;
if (tlb_flag(TLB_DCLEAN))
- asm("mcr%? p15, 0, %0, c7, c10, 1 @ flush_pmd"
- : : "r" (pmd));
+ asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
+ : : "r" (pmd) : "cc");
if (tlb_flag(TLB_WB))
- asm("mcr%? p15, 0, %0, c7, c10, 4 @ flush_pmd"
- : : "r" (zero));
+ asm("mcr p15, 0, %0, c7, c10, 4 @ flush_pmd"
+ : : "r" (zero) : "cc");
}
static inline void clean_pmd_entry(pmd_t *pmd)
@@ -385,8 +385,8 @@ static inline void clean_pmd_entry(pmd_t *pmd)
const unsigned int __tlb_flag = __cpu_tlb_flags;
if (tlb_flag(TLB_DCLEAN))
- asm("mcr%? p15, 0, %0, c7, c10, 1 @ flush_pmd"
- : : "r" (pmd));
+ asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
+ : : "r" (pmd) : "cc");
}
#undef tlb_flag
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