diff options
| -rw-r--r-- | arch/arm/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arm/common/Kconfig | 7 | ||||
| -rw-r--r-- | arch/arm/common/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/common/vic.c | 92 | ||||
| -rw-r--r-- | arch/arm/mach-versatile/core.c | 58 | ||||
| -rw-r--r-- | include/asm-arm/arch-versatile/entry-macro.S | 1 | ||||
| -rw-r--r-- | include/asm-arm/arch-versatile/platform.h | 23 | ||||
| -rw-r--r-- | include/asm-arm/hardware/vic.h | 45 |
8 files changed, 151 insertions, 77 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 50b9afa..c4d585e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -180,6 +180,7 @@ config ARCH_OMAP config ARCH_VERSATILE bool "Versatile" select ARM_AMBA + select ARM_VIC select ICST307 help This enables support for ARM Ltd Versatile board. diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index d7509c7..5e34ca6 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -1,7 +1,10 @@ -config ICST525 +config ARM_GIC bool -config ARM_GIC +config ARM_VIC + bool + +config ICST525 bool config ICST307 diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index ec8d17c..c81a2ff 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -4,6 +4,7 @@ obj-y += rtctime.o obj-$(CONFIG_ARM_GIC) += gic.o +obj-$(CONFIG_ARM_VIC) += vic.o obj-$(CONFIG_ICST525) += icst525.o obj-$(CONFIG_ICST307) += icst307.o obj-$(CONFIG_SA1111) += sa1111.o diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c new file mode 100644 index 0000000..a45ed16 --- /dev/null +++ b/arch/arm/common/vic.c @@ -0,0 +1,92 @@ +/* + * linux/arch/arm/common/vic.c + * + * Copyright (C) 1999 - 2003 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/init.h> +#include <linux/list.h> + +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/mach/irq.h> +#include <asm/hardware/vic.h> + +static void __iomem *vic_base; + +static void vic_mask_irq(unsigned int irq) +{ + irq -= IRQ_VIC_START; + writel(1 << irq, vic_base + VIC_INT_ENABLE_CLEAR); +} + +static void vic_unmask_irq(unsigned int irq) +{ + irq -= IRQ_VIC_START; + writel(1 << irq, vic_base + VIC_INT_ENABLE); +} + +static struct irqchip vic_chip = { + .ack = vic_mask_irq, + .mask = vic_mask_irq, + .unmask = vic_unmask_irq, +}; + +void __init vic_init(void __iomem *base, u32 vic_sources) +{ + unsigned int i; + + vic_base = base; + + /* Disable all interrupts initially. */ + + writel(0, vic_base + VIC_INT_SELECT); + writel(0, vic_base + VIC_INT_ENABLE); + writel(~0, vic_base + VIC_INT_ENABLE_CLEAR); + writel(0, vic_base + VIC_IRQ_STATUS); + writel(0, vic_base + VIC_ITCR); + writel(~0, vic_base + VIC_INT_SOFT_CLEAR); + + /* + * Make sure we clear all existing interrupts + */ + writel(0, vic_base + VIC_VECT_ADDR); + for (i = 0; i < 19; i++) { + unsigned int value; + + value = readl(vic_base + VIC_VECT_ADDR); + writel(value, vic_base + VIC_VECT_ADDR); + } + + for (i = 0; i < 16; i++) { + void __iomem *reg = vic_base + VIC_VECT_CNTL0 + (i * 4); + writel(VIC_VECT_CNTL_ENABLE | i, reg); + } + + writel(32, vic_base + VIC_DEF_VECT_ADDR); + + for (i = 0; i < 32; i++) { + unsigned int irq = IRQ_VIC_START + i; + + set_irq_chip(irq, &vic_chip); + + if (vic_sources & (1 << i)) { + set_irq_handler(irq, do_level_IRQ); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + } + } +} diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 9002374..9ebbe80 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -35,6 +35,7 @@ #include <asm/leds.h> #include <asm/hardware/arm_timer.h> #include <asm/hardware/icst307.h> +#include <asm/hardware/vic.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> @@ -56,24 +57,6 @@ #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) -static void vic_mask_irq(unsigned int irq) -{ - irq -= IRQ_VIC_START; - writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR); -} - -static void vic_unmask_irq(unsigned int irq) -{ - irq -= IRQ_VIC_START; - writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE); -} - -static struct irqchip vic_chip = { - .ack = vic_mask_irq, - .mask = vic_mask_irq, - .unmask = vic_unmask_irq, -}; - static void sic_mask_irq(unsigned int irq) { irq -= IRQ_SIC_START; @@ -127,43 +110,12 @@ sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) void __init versatile_init_irq(void) { - unsigned int i, value; - - /* Disable all interrupts initially. */ + unsigned int i; - writel(0, VA_VIC_BASE + VIC_INT_SELECT); - writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE); - writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR); - writel(0, VA_VIC_BASE + VIC_IRQ_STATUS); - writel(0, VA_VIC_BASE + VIC_ITCR); - writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR); - - /* - * Make sure we clear all existing interrupts - */ - writel(0, VA_VIC_BASE + VIC_VECT_ADDR); - for (i = 0; i < 19; i++) { - value = readl(VA_VIC_BASE + VIC_VECT_ADDR); - writel(value, VA_VIC_BASE + VIC_VECT_ADDR); - } - - for (i = 0; i < 16; i++) { - value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4)); - writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4)); - } - - writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR); - - for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) { - if (i != IRQ_VICSOURCE31) { - set_irq_chip(i, &vic_chip); - set_irq_handler(i, do_level_IRQ); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } - } + vic_init(VA_VIC_BASE, ~(1 << 31)); set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq); - vic_unmask_irq(IRQ_VICSOURCE31); + enable_irq(IRQ_VICSOURCE31); /* Do second interrupt controller */ writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); @@ -877,7 +829,7 @@ static unsigned long versatile_gettimeoffset(void) ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff; do { ticks1 = ticks2; - status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS); + status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS); ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff; } while (ticks2 > ticks1); diff --git a/include/asm-arm/arch-versatile/entry-macro.S b/include/asm-arm/arch-versatile/entry-macro.S index 58f0d71..feff771 100644 --- a/include/asm-arm/arch-versatile/entry-macro.S +++ b/include/asm-arm/arch-versatile/entry-macro.S @@ -8,6 +8,7 @@ * warranty of any kind, whether express or implied. */ #include <asm/hardware.h> +#include <asm/hardware/vic.h> .macro disable_fiq .endm diff --git a/include/asm-arm/arch-versatile/platform.h b/include/asm-arm/arch-versatile/platform.h index cbdd9fb..72ef874 100644 --- a/include/asm-arm/arch-versatile/platform.h +++ b/include/asm-arm/arch-versatile/platform.h @@ -293,26 +293,7 @@ * VERSATILE_SYS_IC * */ -#define VIC_IRQ_STATUS 0 -#define VIC_FIQ_STATUS 0x04 -#define VIC_IRQ_RAW_STATUS 0x08 -#define VIC_INT_SELECT 0x0C /* 1 = FIQ, 0 = IRQ */ -#define VIC_IRQ_ENABLE 0x10 /* 1 = enable, 0 = disable */ -#define VIC_IRQ_ENABLE_CLEAR 0x14 -#define VIC_IRQ_SOFT 0x18 -#define VIC_IRQ_SOFT_CLEAR 0x1C -#define VIC_PROTECT 0x20 -#define VIC_VECT_ADDR 0x30 -#define VIC_DEF_VECT_ADDR 0x34 -#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */ -#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */ -#define VIC_ITCR 0x300 /* VIC test control register */ - -#define VIC_FIQ_RAW_STATUS 0x08 -#define VIC_FIQ_ENABLE 0x10 /* 1 = enable, 0 = disable */ -#define VIC_FIQ_ENABLE_CLEAR 0x14 -#define VIC_FIQ_SOFT 0x18 -#define VIC_FIQ_SOFT_CLEAR 0x1C +/* VIC definitions in include/asm-arm/hardware/vic.h */ #define SIC_IRQ_STATUS 0 #define SIC_IRQ_RAW_STATUS 0x04 @@ -325,8 +306,6 @@ #define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */ #define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */ -#define VICVectCntl_Enable (1 << 5) - /* ------------------------------------------------------------------------ * Interrupts - bit assignment (primary) * ------------------------------------------------------------------------ diff --git a/include/asm-arm/hardware/vic.h b/include/asm-arm/hardware/vic.h new file mode 100644 index 0000000..81825eb --- /dev/null +++ b/include/asm-arm/hardware/vic.h @@ -0,0 +1,45 @@ +/* + * linux/include/asm-arm/hardware/vic.h + * + * Copyright (c) ARM Limited 2003. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_HARDWARE_VIC_H +#define __ASM_ARM_HARDWARE_VIC_H + +#define VIC_IRQ_STATUS 0x00 +#define VIC_FIQ_STATUS 0x04 +#define VIC_RAW_STATUS 0x08 +#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */ +#define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */ +#define VIC_INT_ENABLE_CLEAR 0x14 +#define VIC_INT_SOFT 0x18 +#define VIC_INT_SOFT_CLEAR 0x1c +#define VIC_PROTECT 0x20 +#define VIC_VECT_ADDR 0x30 +#define VIC_DEF_VECT_ADDR 0x34 + +#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */ +#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */ +#define VIC_ITCR 0x300 /* VIC test control register */ + +#define VIC_VECT_CNTL_ENABLE (1 << 5) + +#ifndef __ASSEMBLY__ +void vic_init(void __iomem *base, u32 vic_sources); +#endif + +#endif |
