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-rw-r--r--arch/blackfin/mach-common/ints-priority-dc.c4
-rw-r--r--arch/blackfin/mach-common/ints-priority-sc.c13
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h1
-rw-r--r--include/asm-blackfin/mach-bf561/cdefBF561.h1
-rw-r--r--include/asm-blackfin/mman.h2
5 files changed, 8 insertions, 13 deletions
diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c
index 7977c2c..6b9fd03 100644
--- a/arch/blackfin/mach-common/ints-priority-dc.c
+++ b/arch/blackfin/mach-common/ints-priority-dc.c
@@ -371,8 +371,8 @@ int __init init_arch_irq(void)
bfin_write_SICA_IMASK1(SIC_UNMASK_ALL);
SSYNC();
- bfin_write_SICA_IWR0(IWR_ENABLE_ALL);
- bfin_write_SICA_IWR1(IWR_ENABLE_ALL);
+ bfin_write_SICA_IWR0(IWR_ENABLE_ALL);
+ bfin_write_SICA_IWR1(IWR_ENABLE_ALL);
local_irq_disable();
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c
index c3bb2fb..28a878c 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority-sc.c
@@ -147,8 +147,8 @@ static void bfin_internal_mask_irq(unsigned int irq)
unsigned mask_bank, mask_bit;
mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
- bfin_write_SIC_IMASK( mask_bank, bfin_read_SIC_IMASK(mask_bank) & \
- ~(1 << mask_bit));
+ bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
+ ~(1 << mask_bit));
#endif
SSYNC();
}
@@ -161,9 +161,9 @@ static void bfin_internal_unmask_irq(unsigned int irq)
#else
unsigned mask_bank, mask_bit;
mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
- mask_bit = (irq - (IRQ_CORETMR + 1))%32;
- bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | \
- ( 1 << mask_bit));
+ mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
+ bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
+ (1 << mask_bit));
#endif
SSYNC();
}
@@ -728,7 +728,7 @@ int __init init_arch_irq(void)
bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
- bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
+ bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
#else
bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
@@ -878,7 +878,6 @@ void do_irq(int vec, struct pt_regs *fp)
sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
-
for (;; ivg++) {
if (ivg >= ivg_stop) {
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index 87f2385..98d35a9 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -68,7 +68,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
bfin_write32(SIC_IWR2, iwr2);
-
}
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index 6e8b816..1a8ec9e 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -74,7 +74,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
local_irq_restore(flags);
bfin_write32(SICA_IWR0, iwr0);
bfin_write32(SICA_IWR1, iwr1);
-
}
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
diff --git a/include/asm-blackfin/mman.h b/include/asm-blackfin/mman.h
index 4d504f9..b58f5ad 100644
--- a/include/asm-blackfin/mman.h
+++ b/include/asm-blackfin/mman.h
@@ -22,8 +22,6 @@
#define MAP_NORESERVE 0x4000 /* don't check for reservations */
#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
#define MAP_NONBLOCK 0x10000 /* do not block on IO */
-#define MAP_UNINITIALIZE 0x4000000 /* For anonymous mmap, memory could
- be uninitialized. */
#define MS_ASYNC 1 /* sync memory asynchronously */
#define MS_INVALIDATE 2 /* invalidate the caches */
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