diff options
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 40 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dpll_mgr.c | 11 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_runtime_pm.c | 5 |
4 files changed, 34 insertions, 23 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b2adb01..58b8d75 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5497,8 +5497,15 @@ skl_dpll0_update(struct drm_i915_private *dev_priv) return; } + WARN_ON((val & LCPLL_PLL_LOCK) == 0); + val = I915_READ(DPLL_CTRL1); + WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | + DPLL_CTRL1_SSC(SKL_DPLL0) | + DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != + DPLL_CTRL1_OVERRIDE(SKL_DPLL0)); + switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): @@ -5668,6 +5675,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) intel_update_cdclk(dev); } +static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); + void skl_uninit_cdclk(struct drm_i915_private *dev_priv) { /* disable DBUF power */ @@ -5684,10 +5693,19 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv) void skl_init_cdclk(struct drm_i915_private *dev_priv) { - /* DPLL0 not enabled (happens on early BIOS versions) */ - if (dev_priv->skl_vco_freq == 0) { - int cdclk, vco; + int cdclk, vco; + + skl_sanitize_cdclk(dev_priv); + if (dev_priv->cdclk_freq != 0 && dev_priv->skl_vco_freq != 0) { + /* + * Use the current vco as our initial + * guess as to what the preferred vco is. + */ + if (dev_priv->skl_preferred_vco_freq == 0) + skl_set_preferred_cdclk_vco(dev_priv, + dev_priv->skl_vco_freq); + } else { /* set CDCLK to the lowest frequency, Modeset follows */ vco = dev_priv->skl_preferred_vco_freq; if (vco == 0) @@ -5707,7 +5725,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv) DRM_ERROR("DBuf power enable timeout\n"); } -int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) +static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) { uint32_t cdctl, expected; @@ -5730,6 +5748,8 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) DPLL_CTRL1_OVERRIDE(SKL_DPLL0)) goto sanitize; + intel_update_cdclk(dev_priv->dev); + /* DPLL okay; verify the cdclock * * Noticed in some instances that the freq selection is correct but @@ -5741,13 +5761,15 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) skl_cdclk_decimal(dev_priv->cdclk_freq); if (cdctl == expected) /* All well; nothing to sanitize */ - return false; -sanitize: + return; - skl_init_cdclk(dev_priv); +sanitize: + DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); - /* we did have to sanitize */ - return true; + /* force cdclk programming */ + dev_priv->cdclk_freq = 0; + /* force full PLL disable + enable */ + dev_priv->skl_vco_freq = -1; } /* Adjust CDclk dividers to allow high res or save power if possible */ diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 34ec149..6b70e1e 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -1630,17 +1630,10 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { static void intel_ddi_pll_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - uint32_t val = I915_READ(LCPLL_CTL); - if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { - if (skl_sanitize_cdclk(dev_priv)) - DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n"); + if (INTEL_GEN(dev_priv) < 9) { + uint32_t val = I915_READ(LCPLL_CTL); - /* We'll want to keep using the current vco from now on */ - if (dev_priv->skl_vco_freq != 0) - skl_set_preferred_cdclk_vco(dev_priv, - dev_priv->skl_vco_freq); - } else if (!IS_BROXTON(dev_priv)) { /* * The LCPLL register should be turned on by the BIOS. For now * let's just check its state and print errors in case diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 2bee217..3854b2e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1279,7 +1279,6 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv); void bxt_disable_dc9(struct drm_i915_private *dev_priv); void gen9_enable_dc5(struct drm_i915_private *dev_priv); void skl_init_cdclk(struct drm_i915_private *dev_priv); -int skl_sanitize_cdclk(struct drm_i915_private *dev_priv); void skl_uninit_cdclk(struct drm_i915_private *dev_priv); unsigned int skl_cdclk_get_vco(unsigned int freq); void skl_enable_dc6(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index b69b935..fefe22c 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2200,12 +2200,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, mutex_unlock(&power_domains->lock); - if (!resume) - return; - skl_init_cdclk(dev_priv); - if (dev_priv->csr.dmc_payload) + if (resume && dev_priv->csr.dmc_payload) intel_csr_load_program(dev_priv); } |
