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-rw-r--r--arch/mips/kernel/cpu-probe.c15
-rw-r--r--include/asm-mips/mipsregs.h2
2 files changed, 15 insertions, 2 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 0fc90ba..b12eeee 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -137,13 +137,24 @@ static inline void check_wait(void)
case CPU_4KEC:
case CPU_4KSC:
case CPU_5KC:
- case CPU_24K:
case CPU_25KF:
+ case CPU_PR4450:
+ cpu_wait = r4k_wait;
+ break;
+
+ case CPU_24K:
case CPU_34K:
+ cpu_wait = r4k_wait;
+ if (read_c0_config7() & MIPS_CONF7_WII)
+ cpu_wait = r4k_wait_irqoff;
+ break;
+
case CPU_74K:
- case CPU_PR4450:
cpu_wait = r4k_wait;
+ if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
+ cpu_wait = r4k_wait_irqoff;
break;
+
case CPU_TX49XX:
cpu_wait = r4k_wait_irqoff;
break;
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 9985cb7..89c8192 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -534,6 +534,8 @@
#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
+#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
+
/*
* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
*/
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