diff options
| -rw-r--r-- | drivers/gpu/ipu-v3/ipu-common.c | 25 | ||||
| -rw-r--r-- | include/video/imx-ipu-v3.h | 1 |
2 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c index e542d5e..0a02465 100644 --- a/drivers/gpu/ipu-v3/ipu-common.c +++ b/drivers/gpu/ipu-v3/ipu-common.c @@ -536,6 +536,31 @@ int ipu_idmac_disable_channel(struct ipuv3_channel *channel) } EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel); +/* + * The imx6 rev. D TRM says that enabling the WM feature will increase + * a channel's priority. Refer to Table 36-8 Calculated priority value. + * The sub-module that is the sink or source for the channel must enable + * watermark signal for this to take effect (SMFC_WM for instance). + */ +void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable) +{ + struct ipu_soc *ipu = channel->ipu; + unsigned long flags; + u32 val; + + spin_lock_irqsave(&ipu->lock, flags); + + val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); + if (enable) + val |= 1 << (channel->num % 32); + else + val &= ~(1 << (channel->num % 32)); + ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); + + spin_unlock_irqrestore(&ipu->lock, flags); +} +EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark); + static int ipu_memory_reset(struct ipu_soc *ipu) { unsigned long timeout; diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h index f24ef9a..d0cce6e 100644 --- a/include/video/imx-ipu-v3.h +++ b/include/video/imx-ipu-v3.h @@ -160,6 +160,7 @@ void ipu_idmac_put(struct ipuv3_channel *); int ipu_idmac_enable_channel(struct ipuv3_channel *channel); int ipu_idmac_disable_channel(struct ipuv3_channel *channel); +void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable); int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms); void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, |
