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authorDaniel Glöckner <dg@emlix.com>2009-04-06 11:50:22 +0200
committerMark Brown <broonie@opensource.wolfsonmicro.com>2009-04-06 11:18:39 +0100
commit80fbe6ac9b47cbc11e174a9bf853834dc281da35 (patch)
tree1ad5a6dfdf219fd8e8ce3e0a0ec0be26b11d96a7 /virt/kvm
parent2b7dbbe0c9491e62b50978d1615193bec33a8291 (diff)
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op-kernel-dev-80fbe6ac9b47cbc11e174a9bf853834dc281da35.tar.gz
ASoC: correct s6000 I2S clock polarity
According to the data sheet data is clocked out on the falling edge and latched on the rising edge of the bit clock. While the left sample is transmitted the word clock line is low. Signed-off-by: Daniel Glöckner <dg@emlix.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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