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author | Rashmica Gupta <rashmicy@gmail.com> | 2015-12-23 16:49:51 +1100 |
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committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-05-11 21:54:12 +1000 |
commit | da3ddc3b5fea695f7b2fa89c4ca17dfd529293d2 (patch) | |
tree | 2a463c39e1567a184d24dc9c18e236adb62cc68f /tools/testing/selftests/powerpc/tm/tm-resched-dscr.c | |
parent | 2d59b3b25659463a24f05df367574d90b3cd7145 (diff) | |
download | op-kernel-dev-da3ddc3b5fea695f7b2fa89c4ca17dfd529293d2.zip op-kernel-dev-da3ddc3b5fea695f7b2fa89c4ca17dfd529293d2.tar.gz |
selftests/powerpc: Standardise TM calls
Currently tbegin, tend etc are written as opcodes or asm instructions. So
standardise these to asm instructions.
Signed-off-by: Rashmica Gupta <rashmicy@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'tools/testing/selftests/powerpc/tm/tm-resched-dscr.c')
-rw-r--r-- | tools/testing/selftests/powerpc/tm/tm-resched-dscr.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c b/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c index 8fde93d..d9c49f4 100644 --- a/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c +++ b/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c @@ -31,12 +31,6 @@ #include "utils.h" #include "tm.h" -#define TBEGIN ".long 0x7C00051D ;" -#define TEND ".long 0x7C00055D ;" -#define TCHECK ".long 0x7C00059C ;" -#define TSUSPEND ".long 0x7C0005DD ;" -#define TRESUME ".long 0x7C2005DD ;" -#define SPRN_TEXASR 0x82 #define SPRN_DSCR 0x03 int test_body(void) @@ -55,13 +49,13 @@ int test_body(void) "mtspr %[sprn_dscr], 3;" /* start and suspend a transaction */ - TBEGIN + "tbegin.;" "beq 1f;" - TSUSPEND + "tsuspend.;" /* hard loop until the transaction becomes doomed */ "2: ;" - TCHECK + "tcheck 0;" "bc 4, 0, 2b;" /* record DSCR and TEXASR */ @@ -70,8 +64,8 @@ int test_body(void) "mfspr 3, %[sprn_texasr];" "std 3, %[texasr];" - TRESUME - TEND + "tresume.;" + "tend.;" "li %[rv], 0;" "1: ;" : [rv]"=r"(rv), [dscr2]"=m"(dscr2), [texasr]"=m"(texasr) |