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authorMichael Williamson <michael.williamson@criticallink.com>2011-05-20 10:26:06 -0400
committerLiam Girdwood <lrg@ti.com>2011-05-21 12:07:56 +0100
commit2aba76f014a7b56ab4fe75845c5fd57b5590acc2 (patch)
tree67cd2be68adce646b25b74e6e52bb6cc4f25f6c7 /sound
parent4a787a3ff3f419c23ab0a5cef677fa441356b818 (diff)
downloadop-kernel-dev-2aba76f014a7b56ab4fe75845c5fd57b5590acc2.zip
op-kernel-dev-2aba76f014a7b56ab4fe75845c5fd57b5590acc2.tar.gz
audio: tlv320aic26: fix PLL register configuration
The current PLL configuration code for the tlc320aic26 codec appears to assume a hardcoded system clock of 12 MHz. Use the clock value provided by the DAI_OPS API for the calculation. Tested using a MityDSP-L138 platform providing a 24.576 MHz clock. Signed-off-by: Michael Williamson <michael.williamson@criticallink.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@ti.com>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/codecs/tlv320aic26.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/sound/soc/codecs/tlv320aic26.c b/sound/soc/codecs/tlv320aic26.c
index e2a7608..7859bdc 100644
--- a/sound/soc/codecs/tlv320aic26.c
+++ b/sound/soc/codecs/tlv320aic26.c
@@ -161,10 +161,18 @@ static int aic26_hw_params(struct snd_pcm_substream *substream,
dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL;
}
- /* Configure PLL */
+ /**
+ * Configure PLL
+ * fsref = (mclk * PLLM) / 2048
+ * where PLLM = J.DDDD (DDDD register ranges from 0 to 9999, decimal)
+ */
pval = 1;
- jval = (fsref == 44100) ? 7 : 8;
- dval = (fsref == 44100) ? 5264 : 1920;
+ /* compute J portion of multiplier */
+ jval = fsref / (aic26->mclk / 2048);
+ /* compute fractional DDDD component of multiplier */
+ dval = fsref - (jval * (aic26->mclk / 2048));
+ dval = (10000 * dval) / (aic26->mclk / 2048);
+ dev_dbg(&aic26->spi->dev, "Setting PLLM to %d.%04d\n", jval, dval);
qval = 0;
reg = 0x8000 | qval << 11 | pval << 8 | jval << 2;
aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg);
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