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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2014-01-03 15:27:52 +0200
committerMark Brown <broonie@linaro.org>2014-01-08 12:48:53 +0000
commit8b3bca2966985f559f9ace1effc98955006f2b05 (patch)
treeb7041006495fffd09daa656d3fb2a7bdba416d39 /sound
parent0dc41562a44c9e1012bb810c2a84e81c425867b0 (diff)
downloadop-kernel-dev-8b3bca2966985f559f9ace1effc98955006f2b05.zip
op-kernel-dev-8b3bca2966985f559f9ace1effc98955006f2b05.tar.gz
ASoC: twl4030: Introduce local ctl register cache
Few registers need to be cached in the codec driver level. These registers should only be written when the path is active to avoid pop noise on the given path. This patch adds an array which covers the range where the sensitive registers are located and uppon loadinf the driver the ctl cache will be initialized. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/codecs/twl4030.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index ab2f222..f882077 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -150,10 +150,22 @@ struct twl4030_priv {
u8 earpiece_enabled;
u8 predrivel_enabled, predriver_enabled;
u8 carkitl_enabled, carkitr_enabled;
+ u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1];
struct twl4030_codec_data *pdata;
};
+static void tw4030_init_ctl_cache(struct twl4030_priv *twl4030)
+{
+ int i;
+ u8 byte;
+
+ for (i = TWL4030_REG_EAR_CTL; i <= TWL4030_REG_PRECKR_CTL; i++) {
+ twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, i);
+ twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte;
+ }
+}
+
/*
* read twl4030 register cache
*/
@@ -348,6 +360,9 @@ static void twl4030_init_chip(struct snd_soc_codec *codec)
}
}
+ /* Initialize the local ctl register cache */
+ tw4030_init_ctl_cache(twl4030);
+
/* Refresh APLL_CTL register from HW */
twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
TWL4030_REG_APLL_CTL);
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