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author | Nicolin Chen <Guangyu.Chen@freescale.com> | 2014-05-06 16:56:02 +0800 |
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committer | Mark Brown <broonie@linaro.org> | 2014-05-12 23:13:13 +0100 |
commit | 4f8210f66e5a200c63770ea9445ff913a28a3be2 (patch) | |
tree | a7ff3110a8aa5ae93022644559ee0eea00d51235 /sound | |
parent | 57ebbcafab0ce8cce4493c6a243ecdd7066e6ef1 (diff) | |
download | op-kernel-dev-4f8210f66e5a200c63770ea9445ff913a28a3be2.zip op-kernel-dev-4f8210f66e5a200c63770ea9445ff913a28a3be2.tar.gz |
ASoC: fsl_esai: Set PCRC and PRRC registers at the end of hw_params()
According to Reference Manual -- ESAI Initialization chapter, as the
standard procedure of ESAI personal reset, the PCRC and PRRC registers
should be remained in its reset value and then configured after T/RCCR
and T/RCR configurations's done but before TE/RE's enabling.
So this patch moves PCRC and PRRC settings to the end of hw_params().
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'sound')
-rw-r--r-- | sound/soc/fsl/fsl_esai.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c index c674fd9..496ce2e 100644 --- a/sound/soc/fsl/fsl_esai.c +++ b/sound/soc/fsl/fsl_esai.c @@ -461,12 +461,6 @@ static int fsl_esai_startup(struct snd_pcm_substream *substream, } if (!dai->active) { - /* Reset Port C */ - regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, - ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO)); - regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, - ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO)); - /* Set synchronous mode */ regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR, ESAI_SAICR_SYNC, esai_priv->synchronous ? @@ -526,6 +520,11 @@ static int fsl_esai_hw_params(struct snd_pcm_substream *substream, regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val); + /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */ + regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, + ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO)); + regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, + ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO)); return 0; } |