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| author | Dylan Reid <dgreid@chromium.org> | 2014-03-17 22:08:49 -0700 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-03-19 23:09:45 +0000 |
| commit | 591d14f00796a4250d800d316e3db1fea8a57e20 (patch) | |
| tree | d4dd85a397ed441ae610a50aef5ae7223955b56d /sound/soc/tegra/tegra20_das.c | |
| parent | 38dbfb59d1175ef458d006556061adeaa8751b72 (diff) | |
| download | op-kernel-dev-591d14f00796a4250d800d316e3db1fea8a57e20.zip op-kernel-dev-591d14f00796a4250d800d316e3db1fea8a57e20.tar.gz | |
ASoC: tegra: Use flat regcache
When using an rbtree cache, there can be allocations the first time a
register is accessed. This can cause an attempt to schedule while
atomic in the case that the regmap is using a spinlock. This could be
fixed by either initializing all the registers or using a flat cache.
The register maps for tegra30_ahub and tegra30_i2s are dense and don't
save much from using a tree so convert them to flat.
Tegra30 changes tested on Norrin, Tegra20 changes compile.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'sound/soc/tegra/tegra20_das.c')
| -rw-r--r-- | sound/soc/tegra/tegra20_das.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/tegra/tegra20_das.c b/sound/soc/tegra/tegra20_das.c index e723929..a634f13 100644 --- a/sound/soc/tegra/tegra20_das.c +++ b/sound/soc/tegra/tegra20_das.c @@ -128,7 +128,7 @@ static const struct regmap_config tegra20_das_regmap_config = { .max_register = LAST_REG(DAC_INPUT_DATA_CLK_SEL), .writeable_reg = tegra20_das_wr_rd_reg, .readable_reg = tegra20_das_wr_rd_reg, - .cache_type = REGCACHE_RBTREE, + .cache_type = REGCACHE_FLAT, }; static int tegra20_das_probe(struct platform_device *pdev) |
