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| author | Dharageswari R <dharageswari.r@intel.com> | 2016-06-03 18:29:37 +0530 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-06-07 14:19:11 +0100 |
| commit | 51a01b8c2ea632ed9a57f98c234a0cd9dafe181a (patch) | |
| tree | 7c13c502568b2af9cfce3f34f477deaeaad586d4 /sound/soc/intel | |
| parent | 1ae7ca041a460502b0f9877d84d0f0d9bed9cb72 (diff) | |
| download | op-kernel-dev-51a01b8c2ea632ed9a57f98c234a0cd9dafe181a.zip op-kernel-dev-51a01b8c2ea632ed9a57f98c234a0cd9dafe181a.tar.gz | |
ASoC: Intel: Skylake: Disable SRAM Retention before D3
SW needs to set the PGCTL.LSRMD = 1 to disable LPSRAM retention
feature,otherwise it may lead to SRAM ECC Errors.
Signed-off-by: Dharageswari R <dharageswari.r@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/intel')
| -rw-r--r-- | sound/soc/intel/skylake/skl.c | 3 | ||||
| -rw-r--r-- | sound/soc/intel/skylake/skl.h | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c index 55c301b..cb3eb41 100644 --- a/sound/soc/intel/skylake/skl.c +++ b/sound/soc/intel/skylake/skl.c @@ -186,6 +186,7 @@ static int _skl_suspend(struct hdac_ext_bus *ebus) { struct skl *skl = ebus_to_skl(ebus); struct hdac_bus *bus = ebus_to_hbus(ebus); + struct pci_dev *pci = to_pci_dev(bus->dev); int ret; snd_hdac_ext_bus_link_power_down_all(ebus); @@ -195,6 +196,8 @@ static int _skl_suspend(struct hdac_ext_bus *ebus) return ret; snd_hdac_bus_stop_chip(bus); + update_pci_dword(pci, AZX_PCIREG_PGCTL, + AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); skl_enable_miscbdcge(bus->dev, false); snd_hdac_bus_enter_link_reset(bus); skl_enable_miscbdcge(bus->dev, true); diff --git a/sound/soc/intel/skylake/skl.h b/sound/soc/intel/skylake/skl.h index f66be17..25b8d48 100644 --- a/sound/soc/intel/skylake/skl.h +++ b/sound/soc/intel/skylake/skl.h @@ -48,6 +48,8 @@ #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 +#define AZX_PCIREG_PGCTL 0x44 +#define AZX_PGCTL_LSRMD_MASK (1 << 4) #define AZX_PCIREG_CGCTL 0x48 #define AZX_CGCTL_MISCBDCGE_MASK (1 << 6) |
