diff options
| author | Nicolin Chen <Guangyu.Chen@freescale.com> | 2014-08-04 15:07:25 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-08-16 17:30:45 -0500 |
| commit | 855675f6e6a65688a7f4cf45b9b5a98cf6c6f5c3 (patch) | |
| tree | c5ac2924c488a161660c0300e550a93b160812d9 /sound/soc/fsl/fsl_sai.c | |
| parent | ce7344a4ebabe90e064d3e087727f45624cdc942 (diff) | |
| download | op-kernel-dev-855675f6e6a65688a7f4cf45b9b5a98cf6c6f5c3.zip op-kernel-dev-855675f6e6a65688a7f4cf45b9b5a98cf6c6f5c3.tar.gz | |
ASoC: fsl_sai: Set SYNC bit of TCR2 to Asynchronous Mode
There is one design rule according to SAI's reference manual:
If the transmitter bit clock and frame sync are to be used by both transmitter
and receiver, the transmitter must be configured for asynchronous operation
and the receiver for synchronous operation.
And SYNC of TCR2 is a 2-width control bit:
00 Asynchronous mode.
01 Synchronous with receiver.
10 Synchronous with another SAI transmitter.
11 Synchronous with another SAI receiver.
So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC
bit of RCR2 to 0x1 (Synchronous with transmitter).
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'sound/soc/fsl/fsl_sai.c')
| -rw-r--r-- | sound/soc/fsl/fsl_sai.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 4c9e71c..60fe7c7 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -334,8 +334,7 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. */ - regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, - sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); + regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, 0); regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC, sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); |
