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authorMark Brown <broonie@opensource.wolfsonmicro.com>2010-04-20 12:56:18 +0900
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-04-21 01:41:26 +0900
commit136ff2a272ad4bee33bf85f8c490ff8a2dd08f96 (patch)
tree4f8876c8acdb816e432916f5cd8ad84e1533cdd0 /sound/soc/codecs/wm8994.c
parent4f6f22d7bef77dfb6b27eaed4240784339c546e6 (diff)
downloadop-kernel-dev-136ff2a272ad4bee33bf85f8c490ff8a2dd08f96.zip
op-kernel-dev-136ff2a272ad4bee33bf85f8c490ff8a2dd08f96.tar.gz
ASoC: Support FLL input clock selection on WM8994
The WM8994 FLL can be clocked from one of four inputs, the two MCLKs and the LRCLK and BCLK of the AIF associated with the FLL. Allow all four inputs to be used rather than defaulting to MCLK1. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/wm8994.c')
-rw-r--r--sound/soc/codecs/wm8994.c17
1 files changed, 15 insertions, 2 deletions
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 29c4cfc..a27b2ff 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -2843,6 +2843,16 @@ static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
return -EINVAL;
}
+ switch (src) {
+ case WM8994_FLL_SRC_MCLK1:
+ case WM8994_FLL_SRC_MCLK2:
+ case WM8994_FLL_SRC_LRCLK:
+ case WM8994_FLL_SRC_BCLK:
+ break;
+ default:
+ return -EINVAL;
+ }
+
/* Are we changing anything? */
if (wm8994->fll[id].src == src &&
wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
@@ -2883,8 +2893,10 @@ static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
fll.n << WM8994_FLL1_N_SHIFT);
snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
- WM8994_FLL1_REFCLK_DIV_MASK,
- fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT);
+ WM8994_FLL1_REFCLK_DIV_MASK |
+ WM8994_FLL1_REFCLK_SRC_MASK,
+ (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
+ (src - 1));
/* Enable (with fractional mode if required) */
if (freq_out) {
@@ -2899,6 +2911,7 @@ static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
wm8994->fll[id].in = freq_in;
wm8994->fll[id].out = freq_out;
+ wm8994->fll[id].src = src;
/* Enable any gated AIF clocks */
snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
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