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author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2009-07-17 22:13:01 +0100 |
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committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2009-07-17 22:13:01 +0100 |
commit | 0c11f655553c84bb695fdd5ea8b19d42b41b7133 (patch) | |
tree | 51efcff77d1e22ee6d0a12bb3d36e0db76db4314 /sound/soc/codecs/wm8993.c | |
parent | 8aa2df53088f024b13cb005956bd6da94cc1fd2d (diff) | |
download | op-kernel-dev-0c11f655553c84bb695fdd5ea8b19d42b41b7133.zip op-kernel-dev-0c11f655553c84bb695fdd5ea8b19d42b41b7133.tar.gz |
ASoC: Fix FLL reference clock division setup in WM8993
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/wm8993.c')
-rw-r--r-- | sound/soc/codecs/wm8993.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c index f9c49b3..e246ca0 100644 --- a/sound/soc/codecs/wm8993.c +++ b/sound/soc/codecs/wm8993.c @@ -345,8 +345,10 @@ static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, /* Fref must be <=13.5MHz */ div = 1; + fll_div->fll_clk_ref_div = 0; while ((Fref / div) > 13500000) { div *= 2; + fll_div->fll_clk_ref_div++; if (div > 8) { pr_err("Can't scale %dMHz input down to <=13.5MHz\n", |