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| author | Zidan Wang <zidan.wang@freescale.com> | 2015-08-11 19:25:15 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-08-11 17:11:52 +0100 |
| commit | 3176bf2d7ccd64da9be7b07036e0ba8293179906 (patch) | |
| tree | e82349c7447e81c9aa3e7f75f0bfce4bfa7ad33f /sound/soc/codecs/wm8960.h | |
| parent | bc0195aad0daa2ad5b0d76cce22b167bc3435590 (diff) | |
| download | op-kernel-dev-3176bf2d7ccd64da9be7b07036e0ba8293179906.zip op-kernel-dev-3176bf2d7ccd64da9be7b07036e0ba8293179906.tar.gz | |
ASoC: wm8960: update pll and clock setting function
Add sysclk auto mode. When it's sysclk auto mode, if the MCLK is
available for clock configure, using MCLK to provide sysclk directly,
otherwise, search a available pll out frequcncy and set pll.
Configure clock in hw_params may cause problems when using bypass style
paths without hw_params in machine driver getting called. So add configure
clock to set_bias_level.
Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/wm8960.h')
| -rw-r--r-- | sound/soc/codecs/wm8960.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm8960.h b/sound/soc/codecs/wm8960.h index 2d8163d..ab3220d 100644 --- a/sound/soc/codecs/wm8960.h +++ b/sound/soc/codecs/wm8960.h @@ -82,6 +82,7 @@ #define WM8960_SYSCLK_MCLK (0 << 0) #define WM8960_SYSCLK_PLL (1 << 0) +#define WM8960_SYSCLK_AUTO (2 << 0) #define WM8960_DAC_DIV_1 (0 << 3) #define WM8960_DAC_DIV_1_5 (1 << 3) |
