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authorJiri Prchal <jiri.prchal@aksignal.cz>2012-07-04 08:12:50 +0200
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-07-04 12:34:26 +0100
commit784a897e2310410ed169b5b331f2b7f06b7d58b7 (patch)
treefdc11932a520213a47b143bf215f2ad8bdffaedf /sound/soc/codecs/tlv320aic3x.h
parent2974d6b1aa5261d8db1b614437cc6bafd3ddf0f2 (diff)
downloadop-kernel-dev-784a897e2310410ed169b5b331f2b7f06b7d58b7.zip
op-kernel-dev-784a897e2310410ed169b5b331f2b7f06b7d58b7.tar.gz
ASoC: tlv320aic3x: add missing registers and bits
Adds register and bit shift definitions in header file. Changes are for TLV320AIC310x based on data sheet. Signed-off-by: Jiri Prchal <jiri.prchal@aksignal.cz> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/tlv320aic3x.h')
-rw-r--r--sound/soc/codecs/tlv320aic3x.h19
1 files changed, 18 insertions, 1 deletions
diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h
index 6f097fb..5da5eb3 100644
--- a/sound/soc/codecs/tlv320aic3x.h
+++ b/sound/soc/codecs/tlv320aic3x.h
@@ -13,7 +13,7 @@
#define _AIC3X_H
/* AIC3X register space */
-#define AIC3X_CACHEREGNUM 103
+#define AIC3X_CACHEREGNUM 110
/* Page select register */
#define AIC3X_PAGE_SELECT 0
@@ -74,6 +74,8 @@
#define HPLCOM_CFG 37
/* Right High Power Output control registers */
#define HPRCOM_CFG 38
+/* High Power Output Stage Control Register */
+#define HPOUT_SC 40
/* DAC Output Switching control registers */
#define DAC_LINE_MUX 41
/* High Power Output Driver Pop Reduction registers */
@@ -148,6 +150,17 @@
#define AIC3X_GPIOB_REG 101
/* Clock generation control register */
#define AIC3X_CLKGEN_CTRL_REG 102
+/* New AGC registers */
+#define LAGCN_ATTACK 103
+#define LAGCN_DECAY 104
+#define RAGCN_ATTACK 105
+#define RAGCN_DECAY 106
+/* New Programmable ADC Digital Path and I2C Bus Condition Register */
+#define NEW_ADC_DIGITALPATH 107
+/* Passive Analog Signal Bypass Selection During Powerdown Register */
+#define PASSIVE_BYPASS 108
+/* DAC Quiescent Current Adjustment Register */
+#define DAC_ICC_ADJ 109
/* Page select register bits */
#define PAGE0_SELECT 0
@@ -163,6 +176,10 @@
#define DUAL_RATE_MODE ((1 << 5) | (1 << 6))
#define LDAC2LCH (0x1 << 3)
#define RDAC2RCH (0x1 << 1)
+#define LDAC2RCH (0x2 << 3)
+#define RDAC2LCH (0x2 << 1)
+#define LDAC2MONOMIX (0x3 << 3)
+#define RDAC2MONOMIX (0x3 << 1)
/* PLL registers bitfields */
#define PLLP_SHIFT 0
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