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author | Axel Lin <axel.lin@ingics.com> | 2015-07-27 09:39:43 +0800 |
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committer | Mark Brown <broonie@kernel.org> | 2015-07-29 15:11:50 +0100 |
commit | 62d6d47cb8bd5ace08a90a1cd78f6908e9f9c2d3 (patch) | |
tree | e6b1d32738a20588db6a4ea9faec9c5d316c4cca /sound/soc/codecs/max98090.c | |
parent | 9acc7f08716b98730e1ead7e785fb0f3ad3a2d07 (diff) | |
download | op-kernel-dev-62d6d47cb8bd5ace08a90a1cd78f6908e9f9c2d3.zip op-kernel-dev-62d6d47cb8bd5ace08a90a1cd78f6908e9f9c2d3.tar.gz |
ASoC: max98090: Simplify max98090_readable_register implementation
The readable registers are in consecutive ranges:
0x01 ~ 0x03, 0x0D ~ 0xD1, 0xFF
So simplify the implementation by specifying a range of consecutive values
in a single case label.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Tested-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/max98090.c')
-rw-r--r-- | sound/soc/codecs/max98090.c | 71 |
1 files changed, 2 insertions, 69 deletions
diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c index 1697340..17ab597 100644 --- a/sound/soc/codecs/max98090.c +++ b/sound/soc/codecs/max98090.c @@ -267,75 +267,8 @@ static bool max98090_volatile_register(struct device *dev, unsigned int reg) static bool max98090_readable_register(struct device *dev, unsigned int reg) { switch (reg) { - case M98090_REG_DEVICE_STATUS: - case M98090_REG_JACK_STATUS: - case M98090_REG_INTERRUPT_S: - case M98090_REG_RESERVED: - case M98090_REG_LINE_INPUT_CONFIG: - case M98090_REG_LINE_INPUT_LEVEL: - case M98090_REG_INPUT_MODE: - case M98090_REG_MIC1_INPUT_LEVEL: - case M98090_REG_MIC2_INPUT_LEVEL: - case M98090_REG_MIC_BIAS_VOLTAGE: - case M98090_REG_DIGITAL_MIC_ENABLE: - case M98090_REG_DIGITAL_MIC_CONFIG: - case M98090_REG_LEFT_ADC_MIXER: - case M98090_REG_RIGHT_ADC_MIXER: - case M98090_REG_LEFT_ADC_LEVEL: - case M98090_REG_RIGHT_ADC_LEVEL: - case M98090_REG_ADC_BIQUAD_LEVEL: - case M98090_REG_ADC_SIDETONE: - case M98090_REG_SYSTEM_CLOCK: - case M98090_REG_CLOCK_MODE: - case M98090_REG_CLOCK_RATIO_NI_MSB: - case M98090_REG_CLOCK_RATIO_NI_LSB: - case M98090_REG_CLOCK_RATIO_MI_MSB: - case M98090_REG_CLOCK_RATIO_MI_LSB: - case M98090_REG_MASTER_MODE: - case M98090_REG_INTERFACE_FORMAT: - case M98090_REG_TDM_CONTROL: - case M98090_REG_TDM_FORMAT: - case M98090_REG_IO_CONFIGURATION: - case M98090_REG_FILTER_CONFIG: - case M98090_REG_DAI_PLAYBACK_LEVEL: - case M98090_REG_DAI_PLAYBACK_LEVEL_EQ: - case M98090_REG_LEFT_HP_MIXER: - case M98090_REG_RIGHT_HP_MIXER: - case M98090_REG_HP_CONTROL: - case M98090_REG_LEFT_HP_VOLUME: - case M98090_REG_RIGHT_HP_VOLUME: - case M98090_REG_LEFT_SPK_MIXER: - case M98090_REG_RIGHT_SPK_MIXER: - case M98090_REG_SPK_CONTROL: - case M98090_REG_LEFT_SPK_VOLUME: - case M98090_REG_RIGHT_SPK_VOLUME: - case M98090_REG_DRC_TIMING: - case M98090_REG_DRC_COMPRESSOR: - case M98090_REG_DRC_EXPANDER: - case M98090_REG_DRC_GAIN: - case M98090_REG_RCV_LOUTL_MIXER: - case M98090_REG_RCV_LOUTL_CONTROL: - case M98090_REG_RCV_LOUTL_VOLUME: - case M98090_REG_LOUTR_MIXER: - case M98090_REG_LOUTR_CONTROL: - case M98090_REG_LOUTR_VOLUME: - case M98090_REG_JACK_DETECT: - case M98090_REG_INPUT_ENABLE: - case M98090_REG_OUTPUT_ENABLE: - case M98090_REG_LEVEL_CONTROL: - case M98090_REG_DSP_FILTER_ENABLE: - case M98090_REG_BIAS_CONTROL: - case M98090_REG_DAC_CONTROL: - case M98090_REG_ADC_CONTROL: - case M98090_REG_DEVICE_SHUTDOWN: - case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68: - case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E: - case M98090_REG_DMIC3_VOLUME: - case M98090_REG_DMIC4_VOLUME: - case M98090_REG_DMIC34_BQ_PREATTEN: - case M98090_REG_RECORD_TDM_SLOT: - case M98090_REG_SAMPLE_RATE: - case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E: + case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S: + case M98090_REG_LINE_INPUT_CONFIG ... 0xD1: case M98090_REG_REVISION_ID: return true; default: |