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authorJaroslav Kysela <perex@perex.cz>2009-04-21 15:30:31 +0200
committerJaroslav Kysela <perex@perex.cz>2009-04-21 15:36:58 +0200
commit30fd9940eee910d847f48bd8740b2d0eaa8d2cfc (patch)
treecac55ee05fbf85d3e48ee1118a70ac07be59a97b /sound/pci/intel8x0.c
parente10f9d87c9ac9fdfadb6305dbbc9052e49a02fdd (diff)
downloadop-kernel-dev-30fd9940eee910d847f48bd8740b2d0eaa8d2cfc.zip
op-kernel-dev-30fd9940eee910d847f48bd8740b2d0eaa8d2cfc.tar.gz
[ALSA] intel8x0: another attempt to fix ac97_clock measure routine
Appearently, a big delay ~300ms is required before hw is settled and ready to transfer samples on some hardware variants. Also, return back "clocking to 48000Hz" message when something fails. Signed-off-by: Jaroslav Kysela <perex@perex.cz>
Diffstat (limited to 'sound/pci/intel8x0.c')
-rw-r--r--sound/pci/intel8x0.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/sound/pci/intel8x0.c b/sound/pci/intel8x0.c
index 5dced5b..c4ba486 100644
--- a/sound/pci/intel8x0.c
+++ b/sound/pci/intel8x0.c
@@ -2751,11 +2751,12 @@ static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
if (pos == 0) {
snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
__retry:
- if (attempt < 2) {
+ if (attempt < 3) {
+ msleep(300);
attempt++;
goto __again;
}
- return;
+ goto __end;
}
pos /= 4;
@@ -2782,6 +2783,7 @@ static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
else if (pos < 47500 || pos > 48500)
/* not 48000Hz, tuning the clock.. */
chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
+ __end:
printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
}
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