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| author | Chew, Chiau Ee <chiau.ee.chew@intel.com> | 2014-04-18 00:26:06 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-04-18 18:06:07 +0100 |
| commit | d6ba32d5c60f569d252ec9dcd96cd46b19785b60 (patch) | |
| tree | 89d76a1a9d3ba8b7bfc23d9626de3836ea83b40d /net | |
| parent | c9eaa447e77efe77b7fa4c953bd62de8297fd6c5 (diff) | |
| download | op-kernel-dev-d6ba32d5c60f569d252ec9dcd96cd46b19785b60.zip op-kernel-dev-d6ba32d5c60f569d252ec9dcd96cd46b19785b60.tar.gz | |
spi/pxa2xx-pci: Add PCI mode support for BayTrail LPSS SPI
Similar to CE4100, BayTrail LPSS SPI can be PCI enumerated
as well. Thus, the functions are renamed from ce4100_xxx
to pxa2xx_spi_pci_xxx to clarify that this is a generic
PCI glue layer. Also, added required infrastructure to
support SPI hosts with different configurations.
This patch is based on Mika Westerberg's previous work.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'net')
0 files changed, 0 insertions, 0 deletions
