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| author | Thierry Reding <treding@nvidia.com> | 2015-04-20 14:47:25 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 12:41:48 +0200 |
| commit | 3d0f4e5f7a7c9ef2d8504f2b42f9c4d3233ba707 (patch) | |
| tree | 0cfdef423920ea986eaa0bec6d8892ec741bc0ce /net/ipv6/xfrm6_mode_ro.c | |
| parent | 1ec7032ad517714108cc53a6ee7067276ca21e80 (diff) | |
| download | op-kernel-dev-3d0f4e5f7a7c9ef2d8504f2b42f9c4d3233ba707.zip op-kernel-dev-3d0f4e5f7a7c9ef2d8504f2b42f9c4d3233ba707.tar.gz | |
clk: tegra: Use correct parent for dpaux clock
The dpaux clock is derived from pll_p_out0 (pll_p), not clk_m.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'net/ipv6/xfrm6_mode_ro.c')
0 files changed, 0 insertions, 0 deletions
