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authorClemens Ladisch <clemens@ladisch.de>2010-04-01 16:40:18 +0200
committerStefan Richter <stefanr@s5r6.in-berlin.de>2010-04-10 16:51:14 +0200
commite7014dada041982ae12ba7fd1967ca0ab0243e04 (patch)
treeb82e8047c6f00cfdfd9254a9cdcb66867a673e74 /mm
parent4a96b4fcd6b35e9233df07b3c9ab38091edcfe7e (diff)
downloadop-kernel-dev-e7014dada041982ae12ba7fd1967ca0ab0243e04.zip
op-kernel-dev-e7014dada041982ae12ba7fd1967ca0ab0243e04.tar.gz
firewire: ohci: do not clear PHY interrupt status inadvertently
The interrupt status bits in PHY register 5 are cleared by writing a one bit. To avoid clearing them unadvertently, do not write them back when they were read as set, but only when they have been explicitly requested to be set. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
Diffstat (limited to 'mm')
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