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authorTuomas Tynkkynen <ttynkkynen@nvidia.com>2015-05-13 17:58:43 +0300
committerThierry Reding <treding@nvidia.com>2015-07-16 10:40:20 +0200
commit79cf95c763a11d4b365cd5a627fd1ab4dca67890 (patch)
treec314059d2be0ef328cb28b533cb2e66fbe414b97 /mm/pgtable-generic.c
parentc38864a703f3fe50e2b87883a0def392dd5bf26f (diff)
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clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
The DFLL clocksource was missing from the list of possible parents for the fast CPU cluster. Add it to the list. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'mm/pgtable-generic.c')
0 files changed, 0 insertions, 0 deletions
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