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authorMark Brown <broonie@opensource.wolfsonmicro.com>2011-06-28 20:26:49 -0700
committerDave Jones <davej@redhat.com>2011-07-13 18:29:59 -0400
commitef993ef8dcd4f3e4d058400c5bd2f7c547344e74 (patch)
treea9e38c3c04c686b283c0f0ebfc752cac93ac629f /lib
parentfe7f1bcbff917f22e121d4b2c045fb1de80cc450 (diff)
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[CPUFREQ] S3C6410: Add some lower frequencies for 800MHz base clock operation
By extension from the 667MHz based clocks currently supported add 100MHz and 200MHz operating points. Due to a lack of documentation these have not been confirmed as supported but by extension from the existing frequencies they should be OK, and I've given them quite a bit of runtime testing. The major risk is synchronization with the non-ARM clocks but as we can't currently scale the ARM PLL the risk should be relatively low. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Dave Jones <davej@redhat.com>
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