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| author | Andrew Jeffery <andrew@aj.id.au> | 2017-01-24 16:46:46 +1030 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2017-01-26 14:45:43 +0100 |
| commit | 1736f75d35e47409ad776273133d0f558a4c8253 (patch) | |
| tree | 2c00dd66c1fba12ce3b3b89cd77cf87a025c8e49 /lib/crc32defs.h | |
| parent | 8ccb6dc6e999008bc5d50bdb5badedd636f58e1c (diff) | |
| download | op-kernel-dev-1736f75d35e47409ad776273133d0f558a4c8253.zip op-kernel-dev-1736f75d35e47409ad776273133d0f558a4c8253.tar.gz | |
gpio: aspeed: Add banks Y, Z, AA, AB and AC
This is less straight-forward than one would hope, as some banks only
have 4 pins rather than 8, others are output only, yet more (W and
X, already supported) are input-only, and in the case of the g4 SoC bank
AC doesn't exist.
Add some structs to describe the varying properties of different banks
and integrate mechanisms to deny requests for unsupported
configurations.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'lib/crc32defs.h')
0 files changed, 0 insertions, 0 deletions
